1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
192 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
193 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
202 static const arm_feature_set arm_arch_any
= ARM_ANY
;
203 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
204 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
205 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
207 static const arm_feature_set arm_cext_iwmmxt2
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
209 static const arm_feature_set arm_cext_iwmmxt
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
211 static const arm_feature_set arm_cext_xscale
=
212 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
213 static const arm_feature_set arm_cext_maverick
=
214 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
215 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
216 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
217 static const arm_feature_set fpu_vfp_ext_v1xd
=
218 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
219 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
220 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
221 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
222 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
223 static const arm_feature_set fpu_vfp_ext_d32
=
224 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
225 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
226 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
227 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
229 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
230 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* Set to the opcode if the instruction needs relaxation.
353 Zero if the instruction is not relaxed. */
357 bfd_reloc_code_real_type type
;
362 enum it_instruction_type it_insn_type
;
368 struct neon_type_el vectype
;
369 unsigned present
: 1; /* Operand present. */
370 unsigned isreg
: 1; /* Operand was a register. */
371 unsigned immisreg
: 1; /* .imm field is a second register. */
372 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
373 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
374 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
375 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
376 instructions. This allows us to disambiguate ARM <-> vector insns. */
377 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
378 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
379 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
380 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
381 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
382 unsigned writeback
: 1; /* Operand has trailing ! */
383 unsigned preind
: 1; /* Preindexed address. */
384 unsigned postind
: 1; /* Postindexed address. */
385 unsigned negative
: 1; /* Index register was negated. */
386 unsigned shifted
: 1; /* Shift applied to operation. */
387 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
391 static struct arm_it inst
;
393 #define NUM_FLOAT_VALS 8
395 const char * fp_const
[] =
397 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
400 /* Number of littlenums required to hold an extended precision number. */
401 #define MAX_LITTLENUMS 6
403 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
413 #define CP_T_X 0x00008000
414 #define CP_T_Y 0x00400000
416 #define CONDS_BIT 0x00100000
417 #define LOAD_BIT 0x00100000
419 #define DOUBLE_LOAD_FLAG 0x00000001
423 const char * template_name
;
427 #define COND_ALWAYS 0xE
431 const char * template_name
;
435 struct asm_barrier_opt
437 const char * template_name
;
441 /* The bit that distinguishes CPSR and SPSR. */
442 #define SPSR_BIT (1 << 22)
444 /* The individual PSR flag bits. */
445 #define PSR_c (1 << 16)
446 #define PSR_x (1 << 17)
447 #define PSR_s (1 << 18)
448 #define PSR_f (1 << 19)
453 bfd_reloc_code_real_type reloc
;
458 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
459 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
464 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
467 /* Bits for DEFINED field in neon_typed_alias. */
468 #define NTA_HASTYPE 1
469 #define NTA_HASINDEX 2
471 struct neon_typed_alias
473 unsigned char defined
;
475 struct neon_type_el eltype
;
478 /* ARM register categories. This includes coprocessor numbers and various
479 architecture extensions' registers. */
505 /* Structure for a hash table entry for a register.
506 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
507 information which states whether a vector type or index is specified (for a
508 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
512 unsigned char number
;
514 unsigned char builtin
;
515 struct neon_typed_alias
* neon
;
518 /* Diagnostics used when we don't get a register of the expected type. */
519 const char * const reg_expected_msgs
[] =
521 N_("ARM register expected"),
522 N_("bad or missing co-processor number"),
523 N_("co-processor register expected"),
524 N_("FPA register expected"),
525 N_("VFP single precision register expected"),
526 N_("VFP/Neon double precision register expected"),
527 N_("Neon quad precision register expected"),
528 N_("VFP single or double precision register expected"),
529 N_("Neon double or quad precision register expected"),
530 N_("VFP single, double or Neon quad precision register expected"),
531 N_("VFP system register expected"),
532 N_("Maverick MVF register expected"),
533 N_("Maverick MVD register expected"),
534 N_("Maverick MVFX register expected"),
535 N_("Maverick MVDX register expected"),
536 N_("Maverick MVAX register expected"),
537 N_("Maverick DSPSC register expected"),
538 N_("iWMMXt data register expected"),
539 N_("iWMMXt control register expected"),
540 N_("iWMMXt scalar register expected"),
541 N_("XScale accumulator register expected"),
544 /* Some well known registers that we refer to directly elsewhere. */
549 /* ARM instructions take 4bytes in the object file, Thumb instructions
555 /* Basic string to match. */
556 const char * template_name
;
558 /* Parameters to instruction. */
559 unsigned char operands
[8];
561 /* Conditional tag - see opcode_lookup. */
562 unsigned int tag
: 4;
564 /* Basic instruction code. */
565 unsigned int avalue
: 28;
567 /* Thumb-format instruction code. */
570 /* Which architecture variant provides this instruction. */
571 const arm_feature_set
* avariant
;
572 const arm_feature_set
* tvariant
;
574 /* Function to call to encode instruction in ARM format. */
575 void (* aencode
) (void);
577 /* Function to call to encode instruction in Thumb format. */
578 void (* tencode
) (void);
581 /* Defines for various bits that we will want to toggle. */
582 #define INST_IMMEDIATE 0x02000000
583 #define OFFSET_REG 0x02000000
584 #define HWOFFSET_IMM 0x00400000
585 #define SHIFT_BY_REG 0x00000010
586 #define PRE_INDEX 0x01000000
587 #define INDEX_UP 0x00800000
588 #define WRITE_BACK 0x00200000
589 #define LDM_TYPE_2_OR_3 0x00400000
590 #define CPSI_MMOD 0x00020000
592 #define LITERAL_MASK 0xf000f000
593 #define OPCODE_MASK 0xfe1fffff
594 #define V4_STR_BIT 0x00000020
596 #define T2_SUBS_PC_LR 0xf3de8f00
598 #define DATA_OP_SHIFT 21
600 #define T2_OPCODE_MASK 0xfe1fffff
601 #define T2_DATA_OP_SHIFT 21
603 /* Codes to distinguish the arithmetic instructions. */
614 #define OPCODE_CMP 10
615 #define OPCODE_CMN 11
616 #define OPCODE_ORR 12
617 #define OPCODE_MOV 13
618 #define OPCODE_BIC 14
619 #define OPCODE_MVN 15
621 #define T2_OPCODE_AND 0
622 #define T2_OPCODE_BIC 1
623 #define T2_OPCODE_ORR 2
624 #define T2_OPCODE_ORN 3
625 #define T2_OPCODE_EOR 4
626 #define T2_OPCODE_ADD 8
627 #define T2_OPCODE_ADC 10
628 #define T2_OPCODE_SBC 11
629 #define T2_OPCODE_SUB 13
630 #define T2_OPCODE_RSB 14
632 #define T_OPCODE_MUL 0x4340
633 #define T_OPCODE_TST 0x4200
634 #define T_OPCODE_CMN 0x42c0
635 #define T_OPCODE_NEG 0x4240
636 #define T_OPCODE_MVN 0x43c0
638 #define T_OPCODE_ADD_R3 0x1800
639 #define T_OPCODE_SUB_R3 0x1a00
640 #define T_OPCODE_ADD_HI 0x4400
641 #define T_OPCODE_ADD_ST 0xb000
642 #define T_OPCODE_SUB_ST 0xb080
643 #define T_OPCODE_ADD_SP 0xa800
644 #define T_OPCODE_ADD_PC 0xa000
645 #define T_OPCODE_ADD_I8 0x3000
646 #define T_OPCODE_SUB_I8 0x3800
647 #define T_OPCODE_ADD_I3 0x1c00
648 #define T_OPCODE_SUB_I3 0x1e00
650 #define T_OPCODE_ASR_R 0x4100
651 #define T_OPCODE_LSL_R 0x4080
652 #define T_OPCODE_LSR_R 0x40c0
653 #define T_OPCODE_ROR_R 0x41c0
654 #define T_OPCODE_ASR_I 0x1000
655 #define T_OPCODE_LSL_I 0x0000
656 #define T_OPCODE_LSR_I 0x0800
658 #define T_OPCODE_MOV_I8 0x2000
659 #define T_OPCODE_CMP_I8 0x2800
660 #define T_OPCODE_CMP_LR 0x4280
661 #define T_OPCODE_MOV_HR 0x4600
662 #define T_OPCODE_CMP_HR 0x4500
664 #define T_OPCODE_LDR_PC 0x4800
665 #define T_OPCODE_LDR_SP 0x9800
666 #define T_OPCODE_STR_SP 0x9000
667 #define T_OPCODE_LDR_IW 0x6800
668 #define T_OPCODE_STR_IW 0x6000
669 #define T_OPCODE_LDR_IH 0x8800
670 #define T_OPCODE_STR_IH 0x8000
671 #define T_OPCODE_LDR_IB 0x7800
672 #define T_OPCODE_STR_IB 0x7000
673 #define T_OPCODE_LDR_RW 0x5800
674 #define T_OPCODE_STR_RW 0x5000
675 #define T_OPCODE_LDR_RH 0x5a00
676 #define T_OPCODE_STR_RH 0x5200
677 #define T_OPCODE_LDR_RB 0x5c00
678 #define T_OPCODE_STR_RB 0x5400
680 #define T_OPCODE_PUSH 0xb400
681 #define T_OPCODE_POP 0xbc00
683 #define T_OPCODE_BRANCH 0xe000
685 #define THUMB_SIZE 2 /* Size of thumb instruction. */
686 #define THUMB_PP_PC_LR 0x0100
687 #define THUMB_LOAD_BIT 0x0800
688 #define THUMB2_LOAD_BIT 0x00100000
690 #define BAD_ARGS _("bad arguments to instruction")
691 #define BAD_SP _("r13 not allowed here")
692 #define BAD_PC _("r15 not allowed here")
693 #define BAD_COND _("instruction cannot be conditional")
694 #define BAD_OVERLAP _("registers may not be the same")
695 #define BAD_HIREG _("lo register required")
696 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
697 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
698 #define BAD_BRANCH _("branch must be last instruction in IT block")
699 #define BAD_NOT_IT _("instruction not allowed in IT block")
700 #define BAD_FPU _("selected FPU does not support instruction")
701 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
702 #define BAD_IT_COND _("incorrect condition in IT block")
703 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
704 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
706 static struct hash_control
* arm_ops_hsh
;
707 static struct hash_control
* arm_cond_hsh
;
708 static struct hash_control
* arm_shift_hsh
;
709 static struct hash_control
* arm_psr_hsh
;
710 static struct hash_control
* arm_v7m_psr_hsh
;
711 static struct hash_control
* arm_reg_hsh
;
712 static struct hash_control
* arm_reloc_hsh
;
713 static struct hash_control
* arm_barrier_opt_hsh
;
715 /* Stuff needed to resolve the label ambiguity
724 symbolS
* last_label_seen
;
725 static int label_is_thumb_function_name
= FALSE
;
727 /* Literal pool structure. Held on a per-section
728 and per-sub-section basis. */
730 #define MAX_LITERAL_POOL_SIZE 1024
731 typedef struct literal_pool
733 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
734 unsigned int next_free_entry
;
739 struct literal_pool
* next
;
742 /* Pointer to a linked list of literal pools. */
743 literal_pool
* list_of_pools
= NULL
;
746 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
748 static struct current_it now_it
;
752 now_it_compatible (int cond
)
754 return (cond
& ~1) == (now_it
.cc
& ~1);
758 conditional_insn (void)
760 return inst
.cond
!= COND_ALWAYS
;
763 static int in_it_block (void);
765 static int handle_it_state (void);
767 static void force_automatic_it_block_close (void);
769 static void it_fsm_post_encode (void);
771 #define set_it_insn_type(type) \
774 inst.it_insn_type = type; \
775 if (handle_it_state () == FAIL) \
780 #define set_it_insn_type_nonvoid(type, failret) \
783 inst.it_insn_type = type; \
784 if (handle_it_state () == FAIL) \
789 #define set_it_insn_type_last() \
792 if (inst.cond == COND_ALWAYS) \
793 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
795 set_it_insn_type (INSIDE_IT_LAST_INSN); \
801 /* This array holds the chars that always start a comment. If the
802 pre-processor is disabled, these aren't very useful. */
803 const char comment_chars
[] = "@";
805 /* This array holds the chars that only start a comment at the beginning of
806 a line. If the line seems to have the form '# 123 filename'
807 .line and .file directives will appear in the pre-processed output. */
808 /* Note that input_file.c hand checks for '#' at the beginning of the
809 first line of the input file. This is because the compiler outputs
810 #NO_APP at the beginning of its output. */
811 /* Also note that comments like this one will always work. */
812 const char line_comment_chars
[] = "#";
814 const char line_separator_chars
[] = ";";
816 /* Chars that can be used to separate mant
817 from exp in floating point numbers. */
818 const char EXP_CHARS
[] = "eE";
820 /* Chars that mean this number is a floating point constant. */
824 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
826 /* Prefix characters that indicate the start of an immediate
828 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
830 /* Separator character handling. */
832 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
835 skip_past_char (char ** str
, char c
)
846 #define skip_past_comma(str) skip_past_char (str, ',')
848 /* Arithmetic expressions (possibly involving symbols). */
850 /* Return TRUE if anything in the expression is a bignum. */
853 walk_no_bignums (symbolS
* sp
)
855 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
858 if (symbol_get_value_expression (sp
)->X_add_symbol
)
860 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
861 || (symbol_get_value_expression (sp
)->X_op_symbol
862 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
868 static int in_my_get_expression
= 0;
870 /* Third argument to my_get_expression. */
871 #define GE_NO_PREFIX 0
872 #define GE_IMM_PREFIX 1
873 #define GE_OPT_PREFIX 2
874 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
875 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
876 #define GE_OPT_PREFIX_BIG 3
879 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
884 /* In unified syntax, all prefixes are optional. */
886 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
891 case GE_NO_PREFIX
: break;
893 if (!is_immediate_prefix (**str
))
895 inst
.error
= _("immediate expression requires a # prefix");
901 case GE_OPT_PREFIX_BIG
:
902 if (is_immediate_prefix (**str
))
908 memset (ep
, 0, sizeof (expressionS
));
910 save_in
= input_line_pointer
;
911 input_line_pointer
= *str
;
912 in_my_get_expression
= 1;
913 seg
= expression (ep
);
914 in_my_get_expression
= 0;
916 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
918 /* We found a bad or missing expression in md_operand(). */
919 *str
= input_line_pointer
;
920 input_line_pointer
= save_in
;
921 if (inst
.error
== NULL
)
922 inst
.error
= (ep
->X_op
== O_absent
923 ? _("missing expression") :_("bad expression"));
928 if (seg
!= absolute_section
929 && seg
!= text_section
930 && seg
!= data_section
931 && seg
!= bss_section
932 && seg
!= undefined_section
)
934 inst
.error
= _("bad segment");
935 *str
= input_line_pointer
;
936 input_line_pointer
= save_in
;
941 /* Get rid of any bignums now, so that we don't generate an error for which
942 we can't establish a line number later on. Big numbers are never valid
943 in instructions, which is where this routine is always called. */
944 if (prefix_mode
!= GE_OPT_PREFIX_BIG
945 && (ep
->X_op
== O_big
947 && (walk_no_bignums (ep
->X_add_symbol
)
949 && walk_no_bignums (ep
->X_op_symbol
))))))
951 inst
.error
= _("invalid constant");
952 *str
= input_line_pointer
;
953 input_line_pointer
= save_in
;
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
962 /* Turn a string in input_line_pointer into a floating point constant
963 of type TYPE, and store the appropriate bytes in *LITP. The number
964 of LITTLENUMS emitted is stored in *SIZEP. An error message is
965 returned, or NULL on OK.
967 Note that fp constants aren't represent in the normal way on the ARM.
968 In big endian mode, things are as expected. However, in little endian
969 mode fp constants are big-endian word-wise, and little-endian byte-wise
970 within the words. For example, (double) 1.1 in big endian mode is
971 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
972 the byte sequence 99 99 f1 3f 9a 99 99 99.
974 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
977 md_atof (int type
, char * litP
, int * sizeP
)
980 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1012 return _("Unrecognized or unsupported floating point constant");
1015 t
= atof_ieee (input_line_pointer
, type
, words
);
1017 input_line_pointer
= t
;
1018 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1020 if (target_big_endian
)
1022 for (i
= 0; i
< prec
; i
++)
1024 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1025 litP
+= sizeof (LITTLENUM_TYPE
);
1030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1031 for (i
= prec
- 1; i
>= 0; i
--)
1033 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1034 litP
+= sizeof (LITTLENUM_TYPE
);
1037 /* For a 4 byte float the order of elements in `words' is 1 0.
1038 For an 8 byte float the order is 1 0 3 2. */
1039 for (i
= 0; i
< prec
; i
+= 2)
1041 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1042 sizeof (LITTLENUM_TYPE
));
1043 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1044 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1045 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1052 /* We handle all bad expressions here, so that we can report the faulty
1053 instruction in the error message. */
1055 md_operand (expressionS
* expr
)
1057 if (in_my_get_expression
)
1058 expr
->X_op
= O_illegal
;
1061 /* Immediate values. */
1063 /* Generic immediate-value read function for use in directives.
1064 Accepts anything that 'expression' can fold to a constant.
1065 *val receives the number. */
1068 immediate_for_directive (int *val
)
1071 exp
.X_op
= O_illegal
;
1073 if (is_immediate_prefix (*input_line_pointer
))
1075 input_line_pointer
++;
1079 if (exp
.X_op
!= O_constant
)
1081 as_bad (_("expected #constant"));
1082 ignore_rest_of_line ();
1085 *val
= exp
.X_add_number
;
1090 /* Register parsing. */
1092 /* Generic register parser. CCP points to what should be the
1093 beginning of a register name. If it is indeed a valid register
1094 name, advance CCP over it and return the reg_entry structure;
1095 otherwise return NULL. Does not issue diagnostics. */
1097 static struct reg_entry
*
1098 arm_reg_parse_multi (char **ccp
)
1102 struct reg_entry
*reg
;
1104 #ifdef REGISTER_PREFIX
1105 if (*start
!= REGISTER_PREFIX
)
1109 #ifdef OPTIONAL_REGISTER_PREFIX
1110 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1115 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1120 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1122 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1132 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1133 enum arm_reg_type type
)
1135 /* Alternative syntaxes are accepted for a few register classes. */
1142 /* Generic coprocessor register names are allowed for these. */
1143 if (reg
&& reg
->type
== REG_TYPE_CN
)
1148 /* For backward compatibility, a bare number is valid here. */
1150 unsigned long processor
= strtoul (start
, ccp
, 10);
1151 if (*ccp
!= start
&& processor
<= 15)
1155 case REG_TYPE_MMXWC
:
1156 /* WC includes WCG. ??? I'm not sure this is true for all
1157 instructions that take WC registers. */
1158 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1169 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1170 return value is the register number or FAIL. */
1173 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1176 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1179 /* Do not allow a scalar (reg+index) to parse as a register. */
1180 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1183 if (reg
&& reg
->type
== type
)
1186 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1193 /* Parse a Neon type specifier. *STR should point at the leading '.'
1194 character. Does no verification at this stage that the type fits the opcode
1201 Can all be legally parsed by this function.
1203 Fills in neon_type struct pointer with parsed information, and updates STR
1204 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1205 type, FAIL if not. */
1208 parse_neon_type (struct neon_type
*type
, char **str
)
1215 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1217 enum neon_el_type thistype
= NT_untyped
;
1218 unsigned thissize
= -1u;
1225 /* Just a size without an explicit type. */
1229 switch (TOLOWER (*ptr
))
1231 case 'i': thistype
= NT_integer
; break;
1232 case 'f': thistype
= NT_float
; break;
1233 case 'p': thistype
= NT_poly
; break;
1234 case 's': thistype
= NT_signed
; break;
1235 case 'u': thistype
= NT_unsigned
; break;
1237 thistype
= NT_float
;
1242 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1248 /* .f is an abbreviation for .f32. */
1249 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1254 thissize
= strtoul (ptr
, &ptr
, 10);
1256 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1259 as_bad (_("bad size %d in type specifier"), thissize
);
1267 type
->el
[type
->elems
].type
= thistype
;
1268 type
->el
[type
->elems
].size
= thissize
;
1273 /* Empty/missing type is not a successful parse. */
1274 if (type
->elems
== 0)
1282 /* Errors may be set multiple times during parsing or bit encoding
1283 (particularly in the Neon bits), but usually the earliest error which is set
1284 will be the most meaningful. Avoid overwriting it with later (cascading)
1285 errors by calling this function. */
1288 first_error (const char *err
)
1294 /* Parse a single type, e.g. ".s32", leading period included. */
1296 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1299 struct neon_type optype
;
1303 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1305 if (optype
.elems
== 1)
1306 *vectype
= optype
.el
[0];
1309 first_error (_("only one type should be specified for operand"));
1315 first_error (_("vector type expected"));
1327 /* Special meanings for indices (which have a range of 0-7), which will fit into
1330 #define NEON_ALL_LANES 15
1331 #define NEON_INTERLEAVE_LANES 14
1333 /* Parse either a register or a scalar, with an optional type. Return the
1334 register number, and optionally fill in the actual type of the register
1335 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1336 type/index information in *TYPEINFO. */
1339 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1340 enum arm_reg_type
*rtype
,
1341 struct neon_typed_alias
*typeinfo
)
1344 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1345 struct neon_typed_alias atype
;
1346 struct neon_type_el parsetype
;
1350 atype
.eltype
.type
= NT_invtype
;
1351 atype
.eltype
.size
= -1;
1353 /* Try alternate syntax for some types of register. Note these are mutually
1354 exclusive with the Neon syntax extensions. */
1357 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1365 /* Undo polymorphism when a set of register types may be accepted. */
1366 if ((type
== REG_TYPE_NDQ
1367 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1368 || (type
== REG_TYPE_VFSD
1369 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1370 || (type
== REG_TYPE_NSDQ
1371 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1372 || reg
->type
== REG_TYPE_NQ
))
1373 || (type
== REG_TYPE_MMXWC
1374 && (reg
->type
== REG_TYPE_MMXWCG
)))
1375 type
= (enum arm_reg_type
) reg
->type
;
1377 if (type
!= reg
->type
)
1383 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1385 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1387 first_error (_("can't redefine type for operand"));
1390 atype
.defined
|= NTA_HASTYPE
;
1391 atype
.eltype
= parsetype
;
1394 if (skip_past_char (&str
, '[') == SUCCESS
)
1396 if (type
!= REG_TYPE_VFD
)
1398 first_error (_("only D registers may be indexed"));
1402 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1404 first_error (_("can't change index for operand"));
1408 atype
.defined
|= NTA_HASINDEX
;
1410 if (skip_past_char (&str
, ']') == SUCCESS
)
1411 atype
.index
= NEON_ALL_LANES
;
1416 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1418 if (exp
.X_op
!= O_constant
)
1420 first_error (_("constant expression required"));
1424 if (skip_past_char (&str
, ']') == FAIL
)
1427 atype
.index
= exp
.X_add_number
;
1442 /* Like arm_reg_parse, but allow allow the following extra features:
1443 - If RTYPE is non-zero, return the (possibly restricted) type of the
1444 register (e.g. Neon double or quad reg when either has been requested).
1445 - If this is a Neon vector type with additional type information, fill
1446 in the struct pointed to by VECTYPE (if non-NULL).
1447 This function will fault on encountering a scalar. */
1450 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1451 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1453 struct neon_typed_alias atype
;
1455 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1460 /* Do not allow a scalar (reg+index) to parse as a register. */
1461 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1463 first_error (_("register operand expected, but got scalar"));
1468 *vectype
= atype
.eltype
;
1475 #define NEON_SCALAR_REG(X) ((X) >> 4)
1476 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1478 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1479 have enough information to be able to do a good job bounds-checking. So, we
1480 just do easy checks here, and do further checks later. */
1483 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1487 struct neon_typed_alias atype
;
1489 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1491 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1494 if (atype
.index
== NEON_ALL_LANES
)
1496 first_error (_("scalar must have an index"));
1499 else if (atype
.index
>= 64 / elsize
)
1501 first_error (_("scalar index out of range"));
1506 *type
= atype
.eltype
;
1510 return reg
* 16 + atype
.index
;
1513 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1516 parse_reg_list (char ** strp
)
1518 char * str
= * strp
;
1522 /* We come back here if we get ranges concatenated by '+' or '|'. */
1537 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1539 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1549 first_error (_("bad range in register list"));
1553 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1555 if (range
& (1 << i
))
1557 (_("Warning: duplicated register (r%d) in register list"),
1565 if (range
& (1 << reg
))
1566 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1568 else if (reg
<= cur_reg
)
1569 as_tsktsk (_("Warning: register range not in ascending order"));
1574 while (skip_past_comma (&str
) != FAIL
1575 || (in_range
= 1, *str
++ == '-'));
1580 first_error (_("missing `}'"));
1588 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1591 if (expr
.X_op
== O_constant
)
1593 if (expr
.X_add_number
1594 != (expr
.X_add_number
& 0x0000ffff))
1596 inst
.error
= _("invalid register mask");
1600 if ((range
& expr
.X_add_number
) != 0)
1602 int regno
= range
& expr
.X_add_number
;
1605 regno
= (1 << regno
) - 1;
1607 (_("Warning: duplicated register (r%d) in register list"),
1611 range
|= expr
.X_add_number
;
1615 if (inst
.reloc
.type
!= 0)
1617 inst
.error
= _("expression too complex");
1621 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1622 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1623 inst
.reloc
.pc_rel
= 0;
1627 if (*str
== '|' || *str
== '+')
1633 while (another_range
);
1639 /* Types of registers in a list. */
1648 /* Parse a VFP register list. If the string is invalid return FAIL.
1649 Otherwise return the number of registers, and set PBASE to the first
1650 register. Parses registers of type ETYPE.
1651 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1652 - Q registers can be used to specify pairs of D registers
1653 - { } can be omitted from around a singleton register list
1654 FIXME: This is not implemented, as it would require backtracking in
1657 This could be done (the meaning isn't really ambiguous), but doesn't
1658 fit in well with the current parsing framework.
1659 - 32 D registers may be used (also true for VFPv3).
1660 FIXME: Types are ignored in these register lists, which is probably a
1664 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1669 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1673 unsigned long mask
= 0;
1678 inst
.error
= _("expecting {");
1687 regtype
= REG_TYPE_VFS
;
1692 regtype
= REG_TYPE_VFD
;
1695 case REGLIST_NEON_D
:
1696 regtype
= REG_TYPE_NDQ
;
1700 if (etype
!= REGLIST_VFP_S
)
1702 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1707 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1710 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1717 base_reg
= max_regs
;
1721 int setmask
= 1, addregs
= 1;
1723 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1725 if (new_base
== FAIL
)
1727 first_error (_(reg_expected_msgs
[regtype
]));
1731 if (new_base
>= max_regs
)
1733 first_error (_("register out of range in list"));
1737 /* Note: a value of 2 * n is returned for the register Q<n>. */
1738 if (regtype
== REG_TYPE_NQ
)
1744 if (new_base
< base_reg
)
1745 base_reg
= new_base
;
1747 if (mask
& (setmask
<< new_base
))
1749 first_error (_("invalid register list"));
1753 if ((mask
>> new_base
) != 0 && ! warned
)
1755 as_tsktsk (_("register list not in ascending order"));
1759 mask
|= setmask
<< new_base
;
1762 if (*str
== '-') /* We have the start of a range expression */
1768 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1771 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1775 if (high_range
>= max_regs
)
1777 first_error (_("register out of range in list"));
1781 if (regtype
== REG_TYPE_NQ
)
1782 high_range
= high_range
+ 1;
1784 if (high_range
<= new_base
)
1786 inst
.error
= _("register range not in ascending order");
1790 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1792 if (mask
& (setmask
<< new_base
))
1794 inst
.error
= _("invalid register list");
1798 mask
|= setmask
<< new_base
;
1803 while (skip_past_comma (&str
) != FAIL
);
1807 /* Sanity check -- should have raised a parse error above. */
1808 if (count
== 0 || count
> max_regs
)
1813 /* Final test -- the registers must be consecutive. */
1815 for (i
= 0; i
< count
; i
++)
1817 if ((mask
& (1u << i
)) == 0)
1819 inst
.error
= _("non-contiguous register range");
1829 /* True if two alias types are the same. */
1832 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1840 if (a
->defined
!= b
->defined
)
1843 if ((a
->defined
& NTA_HASTYPE
) != 0
1844 && (a
->eltype
.type
!= b
->eltype
.type
1845 || a
->eltype
.size
!= b
->eltype
.size
))
1848 if ((a
->defined
& NTA_HASINDEX
) != 0
1849 && (a
->index
!= b
->index
))
1855 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1856 The base register is put in *PBASE.
1857 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1859 The register stride (minus one) is put in bit 4 of the return value.
1860 Bits [6:5] encode the list length (minus one).
1861 The type of the list elements is put in *ELTYPE, if non-NULL. */
1863 #define NEON_LANE(X) ((X) & 0xf)
1864 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1865 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1868 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1869 struct neon_type_el
*eltype
)
1876 int leading_brace
= 0;
1877 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1879 const char *const incr_error
= _("register stride must be 1 or 2");
1880 const char *const type_error
= _("mismatched element/structure types in list");
1881 struct neon_typed_alias firsttype
;
1883 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1888 struct neon_typed_alias atype
;
1889 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1893 first_error (_(reg_expected_msgs
[rtype
]));
1900 if (rtype
== REG_TYPE_NQ
)
1907 else if (reg_incr
== -1)
1909 reg_incr
= getreg
- base_reg
;
1910 if (reg_incr
< 1 || reg_incr
> 2)
1912 first_error (_(incr_error
));
1916 else if (getreg
!= base_reg
+ reg_incr
* count
)
1918 first_error (_(incr_error
));
1922 if (! neon_alias_types_same (&atype
, &firsttype
))
1924 first_error (_(type_error
));
1928 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1932 struct neon_typed_alias htype
;
1933 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1935 lane
= NEON_INTERLEAVE_LANES
;
1936 else if (lane
!= NEON_INTERLEAVE_LANES
)
1938 first_error (_(type_error
));
1943 else if (reg_incr
!= 1)
1945 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1949 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1952 first_error (_(reg_expected_msgs
[rtype
]));
1955 if (! neon_alias_types_same (&htype
, &firsttype
))
1957 first_error (_(type_error
));
1960 count
+= hireg
+ dregs
- getreg
;
1964 /* If we're using Q registers, we can't use [] or [n] syntax. */
1965 if (rtype
== REG_TYPE_NQ
)
1971 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1975 else if (lane
!= atype
.index
)
1977 first_error (_(type_error
));
1981 else if (lane
== -1)
1982 lane
= NEON_INTERLEAVE_LANES
;
1983 else if (lane
!= NEON_INTERLEAVE_LANES
)
1985 first_error (_(type_error
));
1990 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1992 /* No lane set by [x]. We must be interleaving structures. */
1994 lane
= NEON_INTERLEAVE_LANES
;
1997 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1998 || (count
> 1 && reg_incr
== -1))
2000 first_error (_("error parsing element/structure list"));
2004 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2006 first_error (_("expected }"));
2014 *eltype
= firsttype
.eltype
;
2019 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2022 /* Parse an explicit relocation suffix on an expression. This is
2023 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2024 arm_reloc_hsh contains no entries, so this function can only
2025 succeed if there is no () after the word. Returns -1 on error,
2026 BFD_RELOC_UNUSED if there wasn't any suffix. */
2028 parse_reloc (char **str
)
2030 struct reloc_entry
*r
;
2034 return BFD_RELOC_UNUSED
;
2039 while (*q
&& *q
!= ')' && *q
!= ',')
2044 if ((r
= (struct reloc_entry
*)
2045 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2052 /* Directives: register aliases. */
2054 static struct reg_entry
*
2055 insert_reg_alias (char *str
, int number
, int type
)
2057 struct reg_entry
*new_reg
;
2060 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2062 if (new_reg
->builtin
)
2063 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2065 /* Only warn about a redefinition if it's not defined as the
2067 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2068 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2073 name
= xstrdup (str
);
2074 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2076 new_reg
->name
= name
;
2077 new_reg
->number
= number
;
2078 new_reg
->type
= type
;
2079 new_reg
->builtin
= FALSE
;
2080 new_reg
->neon
= NULL
;
2082 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2089 insert_neon_reg_alias (char *str
, int number
, int type
,
2090 struct neon_typed_alias
*atype
)
2092 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2096 first_error (_("attempt to redefine typed alias"));
2102 reg
->neon
= (struct neon_typed_alias
*)
2103 xmalloc (sizeof (struct neon_typed_alias
));
2104 *reg
->neon
= *atype
;
2108 /* Look for the .req directive. This is of the form:
2110 new_register_name .req existing_register_name
2112 If we find one, or if it looks sufficiently like one that we want to
2113 handle any error here, return TRUE. Otherwise return FALSE. */
2116 create_register_alias (char * newname
, char *p
)
2118 struct reg_entry
*old
;
2119 char *oldname
, *nbuf
;
2122 /* The input scrubber ensures that whitespace after the mnemonic is
2123 collapsed to single spaces. */
2125 if (strncmp (oldname
, " .req ", 6) != 0)
2129 if (*oldname
== '\0')
2132 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2135 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2139 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2140 the desired alias name, and p points to its end. If not, then
2141 the desired alias name is in the global original_case_string. */
2142 #ifdef TC_CASE_SENSITIVE
2145 newname
= original_case_string
;
2146 nlen
= strlen (newname
);
2149 nbuf
= (char *) alloca (nlen
+ 1);
2150 memcpy (nbuf
, newname
, nlen
);
2153 /* Create aliases under the new name as stated; an all-lowercase
2154 version of the new name; and an all-uppercase version of the new
2156 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2158 for (p
= nbuf
; *p
; p
++)
2161 if (strncmp (nbuf
, newname
, nlen
))
2163 /* If this attempt to create an additional alias fails, do not bother
2164 trying to create the all-lower case alias. We will fail and issue
2165 a second, duplicate error message. This situation arises when the
2166 programmer does something like:
2169 The second .req creates the "Foo" alias but then fails to create
2170 the artificial FOO alias because it has already been created by the
2172 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2176 for (p
= nbuf
; *p
; p
++)
2179 if (strncmp (nbuf
, newname
, nlen
))
2180 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2186 /* Create a Neon typed/indexed register alias using directives, e.g.:
2191 These typed registers can be used instead of the types specified after the
2192 Neon mnemonic, so long as all operands given have types. Types can also be
2193 specified directly, e.g.:
2194 vadd d0.s32, d1.s32, d2.s32 */
2197 create_neon_reg_alias (char *newname
, char *p
)
2199 enum arm_reg_type basetype
;
2200 struct reg_entry
*basereg
;
2201 struct reg_entry mybasereg
;
2202 struct neon_type ntype
;
2203 struct neon_typed_alias typeinfo
;
2204 char *namebuf
, *nameend
;
2207 typeinfo
.defined
= 0;
2208 typeinfo
.eltype
.type
= NT_invtype
;
2209 typeinfo
.eltype
.size
= -1;
2210 typeinfo
.index
= -1;
2214 if (strncmp (p
, " .dn ", 5) == 0)
2215 basetype
= REG_TYPE_VFD
;
2216 else if (strncmp (p
, " .qn ", 5) == 0)
2217 basetype
= REG_TYPE_NQ
;
2226 basereg
= arm_reg_parse_multi (&p
);
2228 if (basereg
&& basereg
->type
!= basetype
)
2230 as_bad (_("bad type for register"));
2234 if (basereg
== NULL
)
2237 /* Try parsing as an integer. */
2238 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2239 if (exp
.X_op
!= O_constant
)
2241 as_bad (_("expression must be constant"));
2244 basereg
= &mybasereg
;
2245 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2251 typeinfo
= *basereg
->neon
;
2253 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2255 /* We got a type. */
2256 if (typeinfo
.defined
& NTA_HASTYPE
)
2258 as_bad (_("can't redefine the type of a register alias"));
2262 typeinfo
.defined
|= NTA_HASTYPE
;
2263 if (ntype
.elems
!= 1)
2265 as_bad (_("you must specify a single type only"));
2268 typeinfo
.eltype
= ntype
.el
[0];
2271 if (skip_past_char (&p
, '[') == SUCCESS
)
2274 /* We got a scalar index. */
2276 if (typeinfo
.defined
& NTA_HASINDEX
)
2278 as_bad (_("can't redefine the index of a scalar alias"));
2282 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2284 if (exp
.X_op
!= O_constant
)
2286 as_bad (_("scalar index must be constant"));
2290 typeinfo
.defined
|= NTA_HASINDEX
;
2291 typeinfo
.index
= exp
.X_add_number
;
2293 if (skip_past_char (&p
, ']') == FAIL
)
2295 as_bad (_("expecting ]"));
2300 namelen
= nameend
- newname
;
2301 namebuf
= (char *) alloca (namelen
+ 1);
2302 strncpy (namebuf
, newname
, namelen
);
2303 namebuf
[namelen
] = '\0';
2305 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2306 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2308 /* Insert name in all uppercase. */
2309 for (p
= namebuf
; *p
; p
++)
2312 if (strncmp (namebuf
, newname
, namelen
))
2313 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2314 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2316 /* Insert name in all lowercase. */
2317 for (p
= namebuf
; *p
; p
++)
2320 if (strncmp (namebuf
, newname
, namelen
))
2321 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2322 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2327 /* Should never be called, as .req goes between the alias and the
2328 register name, not at the beginning of the line. */
2331 s_req (int a ATTRIBUTE_UNUSED
)
2333 as_bad (_("invalid syntax for .req directive"));
2337 s_dn (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .dn directive"));
2343 s_qn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .qn directive"));
2348 /* The .unreq directive deletes an alias which was previously defined
2349 by .req. For example:
2355 s_unreq (int a ATTRIBUTE_UNUSED
)
2360 name
= input_line_pointer
;
2362 while (*input_line_pointer
!= 0
2363 && *input_line_pointer
!= ' '
2364 && *input_line_pointer
!= '\n')
2365 ++input_line_pointer
;
2367 saved_char
= *input_line_pointer
;
2368 *input_line_pointer
= 0;
2371 as_bad (_("invalid syntax for .unreq directive"));
2374 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2378 as_bad (_("unknown register alias '%s'"), name
);
2379 else if (reg
->builtin
)
2380 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2387 hash_delete (arm_reg_hsh
, name
, FALSE
);
2388 free ((char *) reg
->name
);
2393 /* Also locate the all upper case and all lower case versions.
2394 Do not complain if we cannot find one or the other as it
2395 was probably deleted above. */
2397 nbuf
= strdup (name
);
2398 for (p
= nbuf
; *p
; p
++)
2400 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2403 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2404 free ((char *) reg
->name
);
2410 for (p
= nbuf
; *p
; p
++)
2412 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2415 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2416 free ((char *) reg
->name
);
2426 *input_line_pointer
= saved_char
;
2427 demand_empty_rest_of_line ();
2430 /* Directives: Instruction set selection. */
2433 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2434 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2435 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2436 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2438 /* Create a new mapping symbol for the transition to STATE. */
2441 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2444 const char * symname
;
2451 type
= BSF_NO_FLAGS
;
2455 type
= BSF_NO_FLAGS
;
2459 type
= BSF_NO_FLAGS
;
2465 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2466 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2471 THUMB_SET_FUNC (symbolP
, 0);
2472 ARM_SET_THUMB (symbolP
, 0);
2473 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2477 THUMB_SET_FUNC (symbolP
, 1);
2478 ARM_SET_THUMB (symbolP
, 1);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2487 /* Save the mapping symbols for future reference. Also check that
2488 we do not place two mapping symbols at the same offset within a
2489 frag. We'll handle overlap between frags in
2490 check_mapping_symbols. */
2493 know (frag
->tc_frag_data
.first_map
== NULL
);
2494 frag
->tc_frag_data
.first_map
= symbolP
;
2496 if (frag
->tc_frag_data
.last_map
!= NULL
)
2497 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2498 frag
->tc_frag_data
.last_map
= symbolP
;
2501 /* We must sometimes convert a region marked as code to data during
2502 code alignment, if an odd number of bytes have to be padded. The
2503 code mapping symbol is pushed to an aligned address. */
2506 insert_data_mapping_symbol (enum mstate state
,
2507 valueT value
, fragS
*frag
, offsetT bytes
)
2509 /* If there was already a mapping symbol, remove it. */
2510 if (frag
->tc_frag_data
.last_map
!= NULL
2511 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2513 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2517 know (frag
->tc_frag_data
.first_map
== symp
);
2518 frag
->tc_frag_data
.first_map
= NULL
;
2520 frag
->tc_frag_data
.last_map
= NULL
;
2521 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2524 make_mapping_symbol (MAP_DATA
, value
, frag
);
2525 make_mapping_symbol (state
, value
+ bytes
, frag
);
2528 static void mapping_state_2 (enum mstate state
, int max_chars
);
2530 /* Set the mapping state to STATE. Only call this when about to
2531 emit some STATE bytes to the file. */
2534 mapping_state (enum mstate state
)
2536 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2538 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2540 if (mapstate
== state
)
2541 /* The mapping symbol has already been emitted.
2542 There is nothing else to do. */
2544 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2545 /* This case will be evaluated later in the next else. */
2547 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2548 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2550 /* Only add the symbol if the offset is > 0:
2551 if we're at the first frag, check it's size > 0;
2552 if we're not at the first frag, then for sure
2553 the offset is > 0. */
2554 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2555 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2558 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2561 mapping_state_2 (state
, 0);
2565 /* Same as mapping_state, but MAX_CHARS bytes have already been
2566 allocated. Put the mapping symbol that far back. */
2569 mapping_state_2 (enum mstate state
, int max_chars
)
2571 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2573 if (!SEG_NORMAL (now_seg
))
2576 if (mapstate
== state
)
2577 /* The mapping symbol has already been emitted.
2578 There is nothing else to do. */
2581 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2582 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2585 #define mapping_state(x) ((void)0)
2586 #define mapping_state_2(x, y) ((void)0)
2589 /* Find the real, Thumb encoded start of a Thumb function. */
2593 find_real_start (symbolS
* symbolP
)
2596 const char * name
= S_GET_NAME (symbolP
);
2597 symbolS
* new_target
;
2599 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2600 #define STUB_NAME ".real_start_of"
2605 /* The compiler may generate BL instructions to local labels because
2606 it needs to perform a branch to a far away location. These labels
2607 do not have a corresponding ".real_start_of" label. We check
2608 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2609 the ".real_start_of" convention for nonlocal branches. */
2610 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2613 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2614 new_target
= symbol_find (real_start
);
2616 if (new_target
== NULL
)
2618 as_warn (_("Failed to find real start of function: %s\n"), name
);
2619 new_target
= symbolP
;
2627 opcode_select (int width
)
2634 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2635 as_bad (_("selected processor does not support THUMB opcodes"));
2638 /* No need to force the alignment, since we will have been
2639 coming from ARM mode, which is word-aligned. */
2640 record_alignment (now_seg
, 1);
2647 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2648 as_bad (_("selected processor does not support ARM opcodes"));
2653 frag_align (2, 0, 0);
2655 record_alignment (now_seg
, 1);
2660 as_bad (_("invalid instruction size selected (%d)"), width
);
2665 s_arm (int ignore ATTRIBUTE_UNUSED
)
2668 demand_empty_rest_of_line ();
2672 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2675 demand_empty_rest_of_line ();
2679 s_code (int unused ATTRIBUTE_UNUSED
)
2683 temp
= get_absolute_expression ();
2688 opcode_select (temp
);
2692 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2697 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2699 /* If we are not already in thumb mode go into it, EVEN if
2700 the target processor does not support thumb instructions.
2701 This is used by gcc/config/arm/lib1funcs.asm for example
2702 to compile interworking support functions even if the
2703 target processor should not support interworking. */
2707 record_alignment (now_seg
, 1);
2710 demand_empty_rest_of_line ();
2714 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2718 /* The following label is the name/address of the start of a Thumb function.
2719 We need to know this for the interworking support. */
2720 label_is_thumb_function_name
= TRUE
;
2723 /* Perform a .set directive, but also mark the alias as
2724 being a thumb function. */
2727 s_thumb_set (int equiv
)
2729 /* XXX the following is a duplicate of the code for s_set() in read.c
2730 We cannot just call that code as we need to get at the symbol that
2737 /* Especial apologies for the random logic:
2738 This just grew, and could be parsed much more simply!
2740 name
= input_line_pointer
;
2741 delim
= get_symbol_end ();
2742 end_name
= input_line_pointer
;
2745 if (*input_line_pointer
!= ',')
2748 as_bad (_("expected comma after name \"%s\""), name
);
2750 ignore_rest_of_line ();
2754 input_line_pointer
++;
2757 if (name
[0] == '.' && name
[1] == '\0')
2759 /* XXX - this should not happen to .thumb_set. */
2763 if ((symbolP
= symbol_find (name
)) == NULL
2764 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2767 /* When doing symbol listings, play games with dummy fragments living
2768 outside the normal fragment chain to record the file and line info
2770 if (listing
& LISTING_SYMBOLS
)
2772 extern struct list_info_struct
* listing_tail
;
2773 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2775 memset (dummy_frag
, 0, sizeof (fragS
));
2776 dummy_frag
->fr_type
= rs_fill
;
2777 dummy_frag
->line
= listing_tail
;
2778 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2779 dummy_frag
->fr_symbol
= symbolP
;
2783 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2786 /* "set" symbols are local unless otherwise specified. */
2787 SF_SET_LOCAL (symbolP
);
2788 #endif /* OBJ_COFF */
2789 } /* Make a new symbol. */
2791 symbol_table_insert (symbolP
);
2796 && S_IS_DEFINED (symbolP
)
2797 && S_GET_SEGMENT (symbolP
) != reg_section
)
2798 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2800 pseudo_set (symbolP
);
2802 demand_empty_rest_of_line ();
2804 /* XXX Now we come to the Thumb specific bit of code. */
2806 THUMB_SET_FUNC (symbolP
, 1);
2807 ARM_SET_THUMB (symbolP
, 1);
2808 #if defined OBJ_ELF || defined OBJ_COFF
2809 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2813 /* Directives: Mode selection. */
2815 /* .syntax [unified|divided] - choose the new unified syntax
2816 (same for Arm and Thumb encoding, modulo slight differences in what
2817 can be represented) or the old divergent syntax for each mode. */
2819 s_syntax (int unused ATTRIBUTE_UNUSED
)
2823 name
= input_line_pointer
;
2824 delim
= get_symbol_end ();
2826 if (!strcasecmp (name
, "unified"))
2827 unified_syntax
= TRUE
;
2828 else if (!strcasecmp (name
, "divided"))
2829 unified_syntax
= FALSE
;
2832 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2835 *input_line_pointer
= delim
;
2836 demand_empty_rest_of_line ();
2839 /* Directives: sectioning and alignment. */
2841 /* Same as s_align_ptwo but align 0 => align 2. */
2844 s_align (int unused ATTRIBUTE_UNUSED
)
2849 long max_alignment
= 15;
2851 temp
= get_absolute_expression ();
2852 if (temp
> max_alignment
)
2853 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2856 as_bad (_("alignment negative. 0 assumed."));
2860 if (*input_line_pointer
== ',')
2862 input_line_pointer
++;
2863 temp_fill
= get_absolute_expression ();
2875 /* Only make a frag if we HAVE to. */
2876 if (temp
&& !need_pass_2
)
2878 if (!fill_p
&& subseg_text_p (now_seg
))
2879 frag_align_code (temp
, 0);
2881 frag_align (temp
, (int) temp_fill
, 0);
2883 demand_empty_rest_of_line ();
2885 record_alignment (now_seg
, temp
);
2889 s_bss (int ignore ATTRIBUTE_UNUSED
)
2891 /* We don't support putting frags in the BSS segment, we fake it by
2892 marking in_bss, then looking at s_skip for clues. */
2893 subseg_set (bss_section
, 0);
2894 demand_empty_rest_of_line ();
2896 #ifdef md_elf_section_change_hook
2897 md_elf_section_change_hook ();
2902 s_even (int ignore ATTRIBUTE_UNUSED
)
2904 /* Never make frag if expect extra pass. */
2906 frag_align (1, 0, 0);
2908 record_alignment (now_seg
, 1);
2910 demand_empty_rest_of_line ();
2913 /* Directives: Literal pools. */
2915 static literal_pool
*
2916 find_literal_pool (void)
2918 literal_pool
* pool
;
2920 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2922 if (pool
->section
== now_seg
2923 && pool
->sub_section
== now_subseg
)
2930 static literal_pool
*
2931 find_or_make_literal_pool (void)
2933 /* Next literal pool ID number. */
2934 static unsigned int latest_pool_num
= 1;
2935 literal_pool
* pool
;
2937 pool
= find_literal_pool ();
2941 /* Create a new pool. */
2942 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2946 pool
->next_free_entry
= 0;
2947 pool
->section
= now_seg
;
2948 pool
->sub_section
= now_subseg
;
2949 pool
->next
= list_of_pools
;
2950 pool
->symbol
= NULL
;
2952 /* Add it to the list. */
2953 list_of_pools
= pool
;
2956 /* New pools, and emptied pools, will have a NULL symbol. */
2957 if (pool
->symbol
== NULL
)
2959 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2960 (valueT
) 0, &zero_address_frag
);
2961 pool
->id
= latest_pool_num
++;
2968 /* Add the literal in the global 'inst'
2969 structure to the relevant literal pool. */
2972 add_to_lit_pool (void)
2974 literal_pool
* pool
;
2977 pool
= find_or_make_literal_pool ();
2979 /* Check if this literal value is already in the pool. */
2980 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2982 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2983 && (inst
.reloc
.exp
.X_op
== O_constant
)
2984 && (pool
->literals
[entry
].X_add_number
2985 == inst
.reloc
.exp
.X_add_number
)
2986 && (pool
->literals
[entry
].X_unsigned
2987 == inst
.reloc
.exp
.X_unsigned
))
2990 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2991 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2992 && (pool
->literals
[entry
].X_add_number
2993 == inst
.reloc
.exp
.X_add_number
)
2994 && (pool
->literals
[entry
].X_add_symbol
2995 == inst
.reloc
.exp
.X_add_symbol
)
2996 && (pool
->literals
[entry
].X_op_symbol
2997 == inst
.reloc
.exp
.X_op_symbol
))
3001 /* Do we need to create a new entry? */
3002 if (entry
== pool
->next_free_entry
)
3004 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3006 inst
.error
= _("literal pool overflow");
3010 pool
->literals
[entry
] = inst
.reloc
.exp
;
3011 pool
->next_free_entry
+= 1;
3014 inst
.reloc
.exp
.X_op
= O_symbol
;
3015 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3016 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3021 /* Can't use symbol_new here, so have to create a symbol and then at
3022 a later date assign it a value. Thats what these functions do. */
3025 symbol_locate (symbolS
* symbolP
,
3026 const char * name
, /* It is copied, the caller can modify. */
3027 segT segment
, /* Segment identifier (SEG_<something>). */
3028 valueT valu
, /* Symbol value. */
3029 fragS
* frag
) /* Associated fragment. */
3031 unsigned int name_length
;
3032 char * preserved_copy_of_name
;
3034 name_length
= strlen (name
) + 1; /* +1 for \0. */
3035 obstack_grow (¬es
, name
, name_length
);
3036 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3038 #ifdef tc_canonicalize_symbol_name
3039 preserved_copy_of_name
=
3040 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3043 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3045 S_SET_SEGMENT (symbolP
, segment
);
3046 S_SET_VALUE (symbolP
, valu
);
3047 symbol_clear_list_pointers (symbolP
);
3049 symbol_set_frag (symbolP
, frag
);
3051 /* Link to end of symbol chain. */
3053 extern int symbol_table_frozen
;
3055 if (symbol_table_frozen
)
3059 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3061 obj_symbol_new_hook (symbolP
);
3063 #ifdef tc_symbol_new_hook
3064 tc_symbol_new_hook (symbolP
);
3068 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3069 #endif /* DEBUG_SYMS */
3074 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3077 literal_pool
* pool
;
3080 pool
= find_literal_pool ();
3082 || pool
->symbol
== NULL
3083 || pool
->next_free_entry
== 0)
3086 mapping_state (MAP_DATA
);
3088 /* Align pool as you have word accesses.
3089 Only make a frag if we have to. */
3091 frag_align (2, 0, 0);
3093 record_alignment (now_seg
, 2);
3095 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3097 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3098 (valueT
) frag_now_fix (), frag_now
);
3099 symbol_table_insert (pool
->symbol
);
3101 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3103 #if defined OBJ_COFF || defined OBJ_ELF
3104 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3107 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3108 /* First output the expression in the instruction to the pool. */
3109 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3111 /* Mark the pool as empty. */
3112 pool
->next_free_entry
= 0;
3113 pool
->symbol
= NULL
;
3117 /* Forward declarations for functions below, in the MD interface
3119 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3120 static valueT
create_unwind_entry (int);
3121 static void start_unwind_section (const segT
, int);
3122 static void add_unwind_opcode (valueT
, int);
3123 static void flush_pending_unwind (void);
3125 /* Directives: Data. */
3128 s_arm_elf_cons (int nbytes
)
3132 #ifdef md_flush_pending_output
3133 md_flush_pending_output ();
3136 if (is_it_end_of_statement ())
3138 demand_empty_rest_of_line ();
3142 #ifdef md_cons_align
3143 md_cons_align (nbytes
);
3146 mapping_state (MAP_DATA
);
3150 char *base
= input_line_pointer
;
3154 if (exp
.X_op
!= O_symbol
)
3155 emit_expr (&exp
, (unsigned int) nbytes
);
3158 char *before_reloc
= input_line_pointer
;
3159 reloc
= parse_reloc (&input_line_pointer
);
3162 as_bad (_("unrecognized relocation suffix"));
3163 ignore_rest_of_line ();
3166 else if (reloc
== BFD_RELOC_UNUSED
)
3167 emit_expr (&exp
, (unsigned int) nbytes
);
3170 reloc_howto_type
*howto
= (reloc_howto_type
*)
3171 bfd_reloc_type_lookup (stdoutput
,
3172 (bfd_reloc_code_real_type
) reloc
);
3173 int size
= bfd_get_reloc_size (howto
);
3175 if (reloc
== BFD_RELOC_ARM_PLT32
)
3177 as_bad (_("(plt) is only valid on branch targets"));
3178 reloc
= BFD_RELOC_UNUSED
;
3183 as_bad (_("%s relocations do not fit in %d bytes"),
3184 howto
->name
, nbytes
);
3187 /* We've parsed an expression stopping at O_symbol.
3188 But there may be more expression left now that we
3189 have parsed the relocation marker. Parse it again.
3190 XXX Surely there is a cleaner way to do this. */
3191 char *p
= input_line_pointer
;
3193 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3194 memcpy (save_buf
, base
, input_line_pointer
- base
);
3195 memmove (base
+ (input_line_pointer
- before_reloc
),
3196 base
, before_reloc
- base
);
3198 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3200 memcpy (base
, save_buf
, p
- base
);
3202 offset
= nbytes
- size
;
3203 p
= frag_more ((int) nbytes
);
3204 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3205 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3210 while (*input_line_pointer
++ == ',');
3212 /* Put terminator back into stream. */
3213 input_line_pointer
--;
3214 demand_empty_rest_of_line ();
3217 /* Emit an expression containing a 32-bit thumb instruction.
3218 Implementation based on put_thumb32_insn. */
3221 emit_thumb32_expr (expressionS
* exp
)
3223 expressionS exp_high
= *exp
;
3225 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3226 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3227 exp
->X_add_number
&= 0xffff;
3228 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3231 /* Guess the instruction size based on the opcode. */
3234 thumb_insn_size (int opcode
)
3236 if ((unsigned int) opcode
< 0xe800u
)
3238 else if ((unsigned int) opcode
>= 0xe8000000u
)
3245 emit_insn (expressionS
*exp
, int nbytes
)
3249 if (exp
->X_op
== O_constant
)
3254 size
= thumb_insn_size (exp
->X_add_number
);
3258 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3260 as_bad (_(".inst.n operand too big. "\
3261 "Use .inst.w instead"));
3266 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3267 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3269 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3271 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3272 emit_thumb32_expr (exp
);
3274 emit_expr (exp
, (unsigned int) size
);
3276 it_fsm_post_encode ();
3280 as_bad (_("cannot determine Thumb instruction size. " \
3281 "Use .inst.n/.inst.w instead"));
3284 as_bad (_("constant expression required"));
3289 /* Like s_arm_elf_cons but do not use md_cons_align and
3290 set the mapping state to MAP_ARM/MAP_THUMB. */
3293 s_arm_elf_inst (int nbytes
)
3295 if (is_it_end_of_statement ())
3297 demand_empty_rest_of_line ();
3301 /* Calling mapping_state () here will not change ARM/THUMB,
3302 but will ensure not to be in DATA state. */
3305 mapping_state (MAP_THUMB
);
3310 as_bad (_("width suffixes are invalid in ARM mode"));
3311 ignore_rest_of_line ();
3317 mapping_state (MAP_ARM
);
3326 if (! emit_insn (& exp
, nbytes
))
3328 ignore_rest_of_line ();
3332 while (*input_line_pointer
++ == ',');
3334 /* Put terminator back into stream. */
3335 input_line_pointer
--;
3336 demand_empty_rest_of_line ();
3339 /* Parse a .rel31 directive. */
3342 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3349 if (*input_line_pointer
== '1')
3350 highbit
= 0x80000000;
3351 else if (*input_line_pointer
!= '0')
3352 as_bad (_("expected 0 or 1"));
3354 input_line_pointer
++;
3355 if (*input_line_pointer
!= ',')
3356 as_bad (_("missing comma"));
3357 input_line_pointer
++;
3359 #ifdef md_flush_pending_output
3360 md_flush_pending_output ();
3363 #ifdef md_cons_align
3367 mapping_state (MAP_DATA
);
3372 md_number_to_chars (p
, highbit
, 4);
3373 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3374 BFD_RELOC_ARM_PREL31
);
3376 demand_empty_rest_of_line ();
3379 /* Directives: AEABI stack-unwind tables. */
3381 /* Parse an unwind_fnstart directive. Simply records the current location. */
3384 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3386 demand_empty_rest_of_line ();
3387 if (unwind
.proc_start
)
3389 as_bad (_("duplicate .fnstart directive"));
3393 /* Mark the start of the function. */
3394 unwind
.proc_start
= expr_build_dot ();
3396 /* Reset the rest of the unwind info. */
3397 unwind
.opcode_count
= 0;
3398 unwind
.table_entry
= NULL
;
3399 unwind
.personality_routine
= NULL
;
3400 unwind
.personality_index
= -1;
3401 unwind
.frame_size
= 0;
3402 unwind
.fp_offset
= 0;
3403 unwind
.fp_reg
= REG_SP
;
3405 unwind
.sp_restored
= 0;
3409 /* Parse a handlerdata directive. Creates the exception handling table entry
3410 for the function. */
3413 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3415 demand_empty_rest_of_line ();
3416 if (!unwind
.proc_start
)
3417 as_bad (MISSING_FNSTART
);
3419 if (unwind
.table_entry
)
3420 as_bad (_("duplicate .handlerdata directive"));
3422 create_unwind_entry (1);
3425 /* Parse an unwind_fnend directive. Generates the index table entry. */
3428 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3433 unsigned int marked_pr_dependency
;
3435 demand_empty_rest_of_line ();
3437 if (!unwind
.proc_start
)
3439 as_bad (_(".fnend directive without .fnstart"));
3443 /* Add eh table entry. */
3444 if (unwind
.table_entry
== NULL
)
3445 val
= create_unwind_entry (0);
3449 /* Add index table entry. This is two words. */
3450 start_unwind_section (unwind
.saved_seg
, 1);
3451 frag_align (2, 0, 0);
3452 record_alignment (now_seg
, 2);
3454 ptr
= frag_more (8);
3455 where
= frag_now_fix () - 8;
3457 /* Self relative offset of the function start. */
3458 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3459 BFD_RELOC_ARM_PREL31
);
3461 /* Indicate dependency on EHABI-defined personality routines to the
3462 linker, if it hasn't been done already. */
3463 marked_pr_dependency
3464 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3465 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3466 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3468 static const char *const name
[] =
3470 "__aeabi_unwind_cpp_pr0",
3471 "__aeabi_unwind_cpp_pr1",
3472 "__aeabi_unwind_cpp_pr2"
3474 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3475 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3476 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3477 |= 1 << unwind
.personality_index
;
3481 /* Inline exception table entry. */
3482 md_number_to_chars (ptr
+ 4, val
, 4);
3484 /* Self relative offset of the table entry. */
3485 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3486 BFD_RELOC_ARM_PREL31
);
3488 /* Restore the original section. */
3489 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3491 unwind
.proc_start
= NULL
;
3495 /* Parse an unwind_cantunwind directive. */
3498 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3500 demand_empty_rest_of_line ();
3501 if (!unwind
.proc_start
)
3502 as_bad (MISSING_FNSTART
);
3504 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3505 as_bad (_("personality routine specified for cantunwind frame"));
3507 unwind
.personality_index
= -2;
3511 /* Parse a personalityindex directive. */
3514 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3518 if (!unwind
.proc_start
)
3519 as_bad (MISSING_FNSTART
);
3521 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3522 as_bad (_("duplicate .personalityindex directive"));
3526 if (exp
.X_op
!= O_constant
3527 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3529 as_bad (_("bad personality routine number"));
3530 ignore_rest_of_line ();
3534 unwind
.personality_index
= exp
.X_add_number
;
3536 demand_empty_rest_of_line ();
3540 /* Parse a personality directive. */
3543 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3547 if (!unwind
.proc_start
)
3548 as_bad (MISSING_FNSTART
);
3550 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3551 as_bad (_("duplicate .personality directive"));
3553 name
= input_line_pointer
;
3554 c
= get_symbol_end ();
3555 p
= input_line_pointer
;
3556 unwind
.personality_routine
= symbol_find_or_make (name
);
3558 demand_empty_rest_of_line ();
3562 /* Parse a directive saving core registers. */
3565 s_arm_unwind_save_core (void)
3571 range
= parse_reg_list (&input_line_pointer
);
3574 as_bad (_("expected register list"));
3575 ignore_rest_of_line ();
3579 demand_empty_rest_of_line ();
3581 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3582 into .unwind_save {..., sp...}. We aren't bothered about the value of
3583 ip because it is clobbered by calls. */
3584 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3585 && (range
& 0x3000) == 0x1000)
3587 unwind
.opcode_count
--;
3588 unwind
.sp_restored
= 0;
3589 range
= (range
| 0x2000) & ~0x1000;
3590 unwind
.pending_offset
= 0;
3596 /* See if we can use the short opcodes. These pop a block of up to 8
3597 registers starting with r4, plus maybe r14. */
3598 for (n
= 0; n
< 8; n
++)
3600 /* Break at the first non-saved register. */
3601 if ((range
& (1 << (n
+ 4))) == 0)
3604 /* See if there are any other bits set. */
3605 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3607 /* Use the long form. */
3608 op
= 0x8000 | ((range
>> 4) & 0xfff);
3609 add_unwind_opcode (op
, 2);
3613 /* Use the short form. */
3615 op
= 0xa8; /* Pop r14. */
3617 op
= 0xa0; /* Do not pop r14. */
3619 add_unwind_opcode (op
, 1);
3626 op
= 0xb100 | (range
& 0xf);
3627 add_unwind_opcode (op
, 2);
3630 /* Record the number of bytes pushed. */
3631 for (n
= 0; n
< 16; n
++)
3633 if (range
& (1 << n
))
3634 unwind
.frame_size
+= 4;
3639 /* Parse a directive saving FPA registers. */
3642 s_arm_unwind_save_fpa (int reg
)
3648 /* Get Number of registers to transfer. */
3649 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3652 exp
.X_op
= O_illegal
;
3654 if (exp
.X_op
!= O_constant
)
3656 as_bad (_("expected , <constant>"));
3657 ignore_rest_of_line ();
3661 num_regs
= exp
.X_add_number
;
3663 if (num_regs
< 1 || num_regs
> 4)
3665 as_bad (_("number of registers must be in the range [1:4]"));
3666 ignore_rest_of_line ();
3670 demand_empty_rest_of_line ();
3675 op
= 0xb4 | (num_regs
- 1);
3676 add_unwind_opcode (op
, 1);
3681 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3682 add_unwind_opcode (op
, 2);
3684 unwind
.frame_size
+= num_regs
* 12;
3688 /* Parse a directive saving VFP registers for ARMv6 and above. */
3691 s_arm_unwind_save_vfp_armv6 (void)
3696 int num_vfpv3_regs
= 0;
3697 int num_regs_below_16
;
3699 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3702 as_bad (_("expected register list"));
3703 ignore_rest_of_line ();
3707 demand_empty_rest_of_line ();
3709 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3710 than FSTMX/FLDMX-style ones). */
3712 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3714 num_vfpv3_regs
= count
;
3715 else if (start
+ count
> 16)
3716 num_vfpv3_regs
= start
+ count
- 16;
3718 if (num_vfpv3_regs
> 0)
3720 int start_offset
= start
> 16 ? start
- 16 : 0;
3721 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3722 add_unwind_opcode (op
, 2);
3725 /* Generate opcode for registers numbered in the range 0 .. 15. */
3726 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3727 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3728 if (num_regs_below_16
> 0)
3730 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3731 add_unwind_opcode (op
, 2);
3734 unwind
.frame_size
+= count
* 8;
3738 /* Parse a directive saving VFP registers for pre-ARMv6. */
3741 s_arm_unwind_save_vfp (void)
3747 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3760 op
= 0xb8 | (count
- 1);
3761 add_unwind_opcode (op
, 1);
3766 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3767 add_unwind_opcode (op
, 2);
3769 unwind
.frame_size
+= count
* 8 + 4;
3773 /* Parse a directive saving iWMMXt data registers. */
3776 s_arm_unwind_save_mmxwr (void)
3784 if (*input_line_pointer
== '{')
3785 input_line_pointer
++;
3789 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3793 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3798 as_tsktsk (_("register list not in ascending order"));
3801 if (*input_line_pointer
== '-')
3803 input_line_pointer
++;
3804 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3807 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3810 else if (reg
>= hi_reg
)
3812 as_bad (_("bad register range"));
3815 for (; reg
< hi_reg
; reg
++)
3819 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3821 if (*input_line_pointer
== '}')
3822 input_line_pointer
++;
3824 demand_empty_rest_of_line ();
3826 /* Generate any deferred opcodes because we're going to be looking at
3828 flush_pending_unwind ();
3830 for (i
= 0; i
< 16; i
++)
3832 if (mask
& (1 << i
))
3833 unwind
.frame_size
+= 8;
3836 /* Attempt to combine with a previous opcode. We do this because gcc
3837 likes to output separate unwind directives for a single block of
3839 if (unwind
.opcode_count
> 0)
3841 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3842 if ((i
& 0xf8) == 0xc0)
3845 /* Only merge if the blocks are contiguous. */
3848 if ((mask
& 0xfe00) == (1 << 9))
3850 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3851 unwind
.opcode_count
--;
3854 else if (i
== 6 && unwind
.opcode_count
>= 2)
3856 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3860 op
= 0xffff << (reg
- 1);
3862 && ((mask
& op
) == (1u << (reg
- 1))))
3864 op
= (1 << (reg
+ i
+ 1)) - 1;
3865 op
&= ~((1 << reg
) - 1);
3867 unwind
.opcode_count
-= 2;
3874 /* We want to generate opcodes in the order the registers have been
3875 saved, ie. descending order. */
3876 for (reg
= 15; reg
>= -1; reg
--)
3878 /* Save registers in blocks. */
3880 || !(mask
& (1 << reg
)))
3882 /* We found an unsaved reg. Generate opcodes to save the
3889 op
= 0xc0 | (hi_reg
- 10);
3890 add_unwind_opcode (op
, 1);
3895 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3896 add_unwind_opcode (op
, 2);
3905 ignore_rest_of_line ();
3909 s_arm_unwind_save_mmxwcg (void)
3916 if (*input_line_pointer
== '{')
3917 input_line_pointer
++;
3921 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3925 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3931 as_tsktsk (_("register list not in ascending order"));
3934 if (*input_line_pointer
== '-')
3936 input_line_pointer
++;
3937 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3940 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3943 else if (reg
>= hi_reg
)
3945 as_bad (_("bad register range"));
3948 for (; reg
< hi_reg
; reg
++)
3952 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3954 if (*input_line_pointer
== '}')
3955 input_line_pointer
++;
3957 demand_empty_rest_of_line ();
3959 /* Generate any deferred opcodes because we're going to be looking at
3961 flush_pending_unwind ();
3963 for (reg
= 0; reg
< 16; reg
++)
3965 if (mask
& (1 << reg
))
3966 unwind
.frame_size
+= 4;
3969 add_unwind_opcode (op
, 2);
3972 ignore_rest_of_line ();
3976 /* Parse an unwind_save directive.
3977 If the argument is non-zero, this is a .vsave directive. */
3980 s_arm_unwind_save (int arch_v6
)
3983 struct reg_entry
*reg
;
3984 bfd_boolean had_brace
= FALSE
;
3986 if (!unwind
.proc_start
)
3987 as_bad (MISSING_FNSTART
);
3989 /* Figure out what sort of save we have. */
3990 peek
= input_line_pointer
;
3998 reg
= arm_reg_parse_multi (&peek
);
4002 as_bad (_("register expected"));
4003 ignore_rest_of_line ();
4012 as_bad (_("FPA .unwind_save does not take a register list"));
4013 ignore_rest_of_line ();
4016 input_line_pointer
= peek
;
4017 s_arm_unwind_save_fpa (reg
->number
);
4020 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4023 s_arm_unwind_save_vfp_armv6 ();
4025 s_arm_unwind_save_vfp ();
4027 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4028 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4031 as_bad (_(".unwind_save does not support this kind of register"));
4032 ignore_rest_of_line ();
4037 /* Parse an unwind_movsp directive. */
4040 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4052 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4053 ignore_rest_of_line ();
4057 /* Optional constant. */
4058 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4060 if (immediate_for_directive (&offset
) == FAIL
)
4066 demand_empty_rest_of_line ();
4068 if (reg
== REG_SP
|| reg
== REG_PC
)
4070 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4074 if (unwind
.fp_reg
!= REG_SP
)
4075 as_bad (_("unexpected .unwind_movsp directive"));
4077 /* Generate opcode to restore the value. */
4079 add_unwind_opcode (op
, 1);
4081 /* Record the information for later. */
4082 unwind
.fp_reg
= reg
;
4083 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4084 unwind
.sp_restored
= 1;
4087 /* Parse an unwind_pad directive. */
4090 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 if (immediate_for_directive (&offset
) == FAIL
)
4102 as_bad (_("stack increment must be multiple of 4"));
4103 ignore_rest_of_line ();
4107 /* Don't generate any opcodes, just record the details for later. */
4108 unwind
.frame_size
+= offset
;
4109 unwind
.pending_offset
+= offset
;
4111 demand_empty_rest_of_line ();
4114 /* Parse an unwind_setfp directive. */
4117 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4123 if (!unwind
.proc_start
)
4124 as_bad (MISSING_FNSTART
);
4126 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4127 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4130 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4132 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4134 as_bad (_("expected <reg>, <reg>"));
4135 ignore_rest_of_line ();
4139 /* Optional constant. */
4140 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4142 if (immediate_for_directive (&offset
) == FAIL
)
4148 demand_empty_rest_of_line ();
4150 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4152 as_bad (_("register must be either sp or set by a previous"
4153 "unwind_movsp directive"));
4157 /* Don't generate any opcodes, just record the information for later. */
4158 unwind
.fp_reg
= fp_reg
;
4160 if (sp_reg
== REG_SP
)
4161 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4163 unwind
.fp_offset
-= offset
;
4166 /* Parse an unwind_raw directive. */
4169 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4172 /* This is an arbitrary limit. */
4173 unsigned char op
[16];
4176 if (!unwind
.proc_start
)
4177 as_bad (MISSING_FNSTART
);
4180 if (exp
.X_op
== O_constant
4181 && skip_past_comma (&input_line_pointer
) != FAIL
)
4183 unwind
.frame_size
+= exp
.X_add_number
;
4187 exp
.X_op
= O_illegal
;
4189 if (exp
.X_op
!= O_constant
)
4191 as_bad (_("expected <offset>, <opcode>"));
4192 ignore_rest_of_line ();
4198 /* Parse the opcode. */
4203 as_bad (_("unwind opcode too long"));
4204 ignore_rest_of_line ();
4206 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4208 as_bad (_("invalid unwind opcode"));
4209 ignore_rest_of_line ();
4212 op
[count
++] = exp
.X_add_number
;
4214 /* Parse the next byte. */
4215 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4221 /* Add the opcode bytes in reverse order. */
4223 add_unwind_opcode (op
[count
], 1);
4225 demand_empty_rest_of_line ();
4229 /* Parse a .eabi_attribute directive. */
4232 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4234 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4236 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4237 attributes_set_explicitly
[tag
] = 1;
4239 #endif /* OBJ_ELF */
4241 static void s_arm_arch (int);
4242 static void s_arm_object_arch (int);
4243 static void s_arm_cpu (int);
4244 static void s_arm_fpu (int);
4249 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4256 if (exp
.X_op
== O_symbol
)
4257 exp
.X_op
= O_secrel
;
4259 emit_expr (&exp
, 4);
4261 while (*input_line_pointer
++ == ',');
4263 input_line_pointer
--;
4264 demand_empty_rest_of_line ();
4268 /* This table describes all the machine specific pseudo-ops the assembler
4269 has to support. The fields are:
4270 pseudo-op name without dot
4271 function to call to execute this pseudo-op
4272 Integer arg to pass to the function. */
4274 const pseudo_typeS md_pseudo_table
[] =
4276 /* Never called because '.req' does not start a line. */
4277 { "req", s_req
, 0 },
4278 /* Following two are likewise never called. */
4281 { "unreq", s_unreq
, 0 },
4282 { "bss", s_bss
, 0 },
4283 { "align", s_align
, 0 },
4284 { "arm", s_arm
, 0 },
4285 { "thumb", s_thumb
, 0 },
4286 { "code", s_code
, 0 },
4287 { "force_thumb", s_force_thumb
, 0 },
4288 { "thumb_func", s_thumb_func
, 0 },
4289 { "thumb_set", s_thumb_set
, 0 },
4290 { "even", s_even
, 0 },
4291 { "ltorg", s_ltorg
, 0 },
4292 { "pool", s_ltorg
, 0 },
4293 { "syntax", s_syntax
, 0 },
4294 { "cpu", s_arm_cpu
, 0 },
4295 { "arch", s_arm_arch
, 0 },
4296 { "object_arch", s_arm_object_arch
, 0 },
4297 { "fpu", s_arm_fpu
, 0 },
4299 { "word", s_arm_elf_cons
, 4 },
4300 { "long", s_arm_elf_cons
, 4 },
4301 { "inst.n", s_arm_elf_inst
, 2 },
4302 { "inst.w", s_arm_elf_inst
, 4 },
4303 { "inst", s_arm_elf_inst
, 0 },
4304 { "rel31", s_arm_rel31
, 0 },
4305 { "fnstart", s_arm_unwind_fnstart
, 0 },
4306 { "fnend", s_arm_unwind_fnend
, 0 },
4307 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4308 { "personality", s_arm_unwind_personality
, 0 },
4309 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4310 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4311 { "save", s_arm_unwind_save
, 0 },
4312 { "vsave", s_arm_unwind_save
, 1 },
4313 { "movsp", s_arm_unwind_movsp
, 0 },
4314 { "pad", s_arm_unwind_pad
, 0 },
4315 { "setfp", s_arm_unwind_setfp
, 0 },
4316 { "unwind_raw", s_arm_unwind_raw
, 0 },
4317 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4321 /* These are used for dwarf. */
4325 /* These are used for dwarf2. */
4326 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4327 { "loc", dwarf2_directive_loc
, 0 },
4328 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4330 { "extend", float_cons
, 'x' },
4331 { "ldouble", float_cons
, 'x' },
4332 { "packed", float_cons
, 'p' },
4334 {"secrel32", pe_directive_secrel
, 0},
4339 /* Parser functions used exclusively in instruction operands. */
4341 /* Generic immediate-value read function for use in insn parsing.
4342 STR points to the beginning of the immediate (the leading #);
4343 VAL receives the value; if the value is outside [MIN, MAX]
4344 issue an error. PREFIX_OPT is true if the immediate prefix is
4348 parse_immediate (char **str
, int *val
, int min
, int max
,
4349 bfd_boolean prefix_opt
)
4352 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4353 if (exp
.X_op
!= O_constant
)
4355 inst
.error
= _("constant expression required");
4359 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4361 inst
.error
= _("immediate value out of range");
4365 *val
= exp
.X_add_number
;
4369 /* Less-generic immediate-value read function with the possibility of loading a
4370 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4371 instructions. Puts the result directly in inst.operands[i]. */
4374 parse_big_immediate (char **str
, int i
)
4379 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4381 if (exp
.X_op
== O_constant
)
4383 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4384 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4385 O_constant. We have to be careful not to break compilation for
4386 32-bit X_add_number, though. */
4387 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4389 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4390 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4391 inst
.operands
[i
].regisimm
= 1;
4394 else if (exp
.X_op
== O_big
4395 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4396 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4398 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4399 /* Bignums have their least significant bits in
4400 generic_bignum[0]. Make sure we put 32 bits in imm and
4401 32 bits in reg, in a (hopefully) portable way. */
4402 gas_assert (parts
!= 0);
4403 inst
.operands
[i
].imm
= 0;
4404 for (j
= 0; j
< parts
; j
++, idx
++)
4405 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4406 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4407 inst
.operands
[i
].reg
= 0;
4408 for (j
= 0; j
< parts
; j
++, idx
++)
4409 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4410 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4411 inst
.operands
[i
].regisimm
= 1;
4421 /* Returns the pseudo-register number of an FPA immediate constant,
4422 or FAIL if there isn't a valid constant here. */
4425 parse_fpa_immediate (char ** str
)
4427 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4433 /* First try and match exact strings, this is to guarantee
4434 that some formats will work even for cross assembly. */
4436 for (i
= 0; fp_const
[i
]; i
++)
4438 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4442 *str
+= strlen (fp_const
[i
]);
4443 if (is_end_of_line
[(unsigned char) **str
])
4449 /* Just because we didn't get a match doesn't mean that the constant
4450 isn't valid, just that it is in a format that we don't
4451 automatically recognize. Try parsing it with the standard
4452 expression routines. */
4454 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4456 /* Look for a raw floating point number. */
4457 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4458 && is_end_of_line
[(unsigned char) *save_in
])
4460 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4462 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4464 if (words
[j
] != fp_values
[i
][j
])
4468 if (j
== MAX_LITTLENUMS
)
4476 /* Try and parse a more complex expression, this will probably fail
4477 unless the code uses a floating point prefix (eg "0f"). */
4478 save_in
= input_line_pointer
;
4479 input_line_pointer
= *str
;
4480 if (expression (&exp
) == absolute_section
4481 && exp
.X_op
== O_big
4482 && exp
.X_add_number
< 0)
4484 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4486 if (gen_to_words (words
, 5, (long) 15) == 0)
4488 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4490 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4492 if (words
[j
] != fp_values
[i
][j
])
4496 if (j
== MAX_LITTLENUMS
)
4498 *str
= input_line_pointer
;
4499 input_line_pointer
= save_in
;
4506 *str
= input_line_pointer
;
4507 input_line_pointer
= save_in
;
4508 inst
.error
= _("invalid FPA immediate expression");
4512 /* Returns 1 if a number has "quarter-precision" float format
4513 0baBbbbbbc defgh000 00000000 00000000. */
4516 is_quarter_float (unsigned imm
)
4518 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4519 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4522 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4523 0baBbbbbbc defgh000 00000000 00000000.
4524 The zero and minus-zero cases need special handling, since they can't be
4525 encoded in the "quarter-precision" float format, but can nonetheless be
4526 loaded as integer constants. */
4529 parse_qfloat_immediate (char **ccp
, int *immed
)
4533 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4534 int found_fpchar
= 0;
4536 skip_past_char (&str
, '#');
4538 /* We must not accidentally parse an integer as a floating-point number. Make
4539 sure that the value we parse is not an integer by checking for special
4540 characters '.' or 'e'.
4541 FIXME: This is a horrible hack, but doing better is tricky because type
4542 information isn't in a very usable state at parse time. */
4544 skip_whitespace (fpnum
);
4546 if (strncmp (fpnum
, "0x", 2) == 0)
4550 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4551 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4561 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4563 unsigned fpword
= 0;
4566 /* Our FP word must be 32 bits (single-precision FP). */
4567 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4569 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4573 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4586 /* Shift operands. */
4589 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4592 struct asm_shift_name
4595 enum shift_kind kind
;
4598 /* Third argument to parse_shift. */
4599 enum parse_shift_mode
4601 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4602 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4603 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4604 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4605 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4608 /* Parse a <shift> specifier on an ARM data processing instruction.
4609 This has three forms:
4611 (LSL|LSR|ASL|ASR|ROR) Rs
4612 (LSL|LSR|ASL|ASR|ROR) #imm
4615 Note that ASL is assimilated to LSL in the instruction encoding, and
4616 RRX to ROR #0 (which cannot be written as such). */
4619 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4621 const struct asm_shift_name
*shift_name
;
4622 enum shift_kind shift
;
4627 for (p
= *str
; ISALPHA (*p
); p
++)
4632 inst
.error
= _("shift expression expected");
4636 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4639 if (shift_name
== NULL
)
4641 inst
.error
= _("shift expression expected");
4645 shift
= shift_name
->kind
;
4649 case NO_SHIFT_RESTRICT
:
4650 case SHIFT_IMMEDIATE
: break;
4652 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4653 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4655 inst
.error
= _("'LSL' or 'ASR' required");
4660 case SHIFT_LSL_IMMEDIATE
:
4661 if (shift
!= SHIFT_LSL
)
4663 inst
.error
= _("'LSL' required");
4668 case SHIFT_ASR_IMMEDIATE
:
4669 if (shift
!= SHIFT_ASR
)
4671 inst
.error
= _("'ASR' required");
4679 if (shift
!= SHIFT_RRX
)
4681 /* Whitespace can appear here if the next thing is a bare digit. */
4682 skip_whitespace (p
);
4684 if (mode
== NO_SHIFT_RESTRICT
4685 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4687 inst
.operands
[i
].imm
= reg
;
4688 inst
.operands
[i
].immisreg
= 1;
4690 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4693 inst
.operands
[i
].shift_kind
= shift
;
4694 inst
.operands
[i
].shifted
= 1;
4699 /* Parse a <shifter_operand> for an ARM data processing instruction:
4702 #<immediate>, <rotate>
4706 where <shift> is defined by parse_shift above, and <rotate> is a
4707 multiple of 2 between 0 and 30. Validation of immediate operands
4708 is deferred to md_apply_fix. */
4711 parse_shifter_operand (char **str
, int i
)
4716 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4718 inst
.operands
[i
].reg
= value
;
4719 inst
.operands
[i
].isreg
= 1;
4721 /* parse_shift will override this if appropriate */
4722 inst
.reloc
.exp
.X_op
= O_constant
;
4723 inst
.reloc
.exp
.X_add_number
= 0;
4725 if (skip_past_comma (str
) == FAIL
)
4728 /* Shift operation on register. */
4729 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4732 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4735 if (skip_past_comma (str
) == SUCCESS
)
4737 /* #x, y -- ie explicit rotation by Y. */
4738 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4741 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4743 inst
.error
= _("constant expression expected");
4747 value
= expr
.X_add_number
;
4748 if (value
< 0 || value
> 30 || value
% 2 != 0)
4750 inst
.error
= _("invalid rotation");
4753 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4755 inst
.error
= _("invalid constant");
4759 /* Convert to decoded value. md_apply_fix will put it back. */
4760 inst
.reloc
.exp
.X_add_number
4761 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4762 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4765 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4766 inst
.reloc
.pc_rel
= 0;
4770 /* Group relocation information. Each entry in the table contains the
4771 textual name of the relocation as may appear in assembler source
4772 and must end with a colon.
4773 Along with this textual name are the relocation codes to be used if
4774 the corresponding instruction is an ALU instruction (ADD or SUB only),
4775 an LDR, an LDRS, or an LDC. */
4777 struct group_reloc_table_entry
4788 /* Varieties of non-ALU group relocation. */
4795 static struct group_reloc_table_entry group_reloc_table
[] =
4796 { /* Program counter relative: */
4798 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4803 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4804 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4805 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4806 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4808 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4813 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4814 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4815 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4816 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4818 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4819 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4820 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4821 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4822 /* Section base relative */
4824 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4829 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4830 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4831 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4832 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4834 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4839 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4840 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4841 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4842 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4844 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4845 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4846 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4847 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4849 /* Given the address of a pointer pointing to the textual name of a group
4850 relocation as may appear in assembler source, attempt to find its details
4851 in group_reloc_table. The pointer will be updated to the character after
4852 the trailing colon. On failure, FAIL will be returned; SUCCESS
4853 otherwise. On success, *entry will be updated to point at the relevant
4854 group_reloc_table entry. */
4857 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4860 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4862 int length
= strlen (group_reloc_table
[i
].name
);
4864 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4865 && (*str
)[length
] == ':')
4867 *out
= &group_reloc_table
[i
];
4868 *str
+= (length
+ 1);
4876 /* Parse a <shifter_operand> for an ARM data processing instruction
4877 (as for parse_shifter_operand) where group relocations are allowed:
4880 #<immediate>, <rotate>
4881 #:<group_reloc>:<expression>
4885 where <group_reloc> is one of the strings defined in group_reloc_table.
4886 The hashes are optional.
4888 Everything else is as for parse_shifter_operand. */
4890 static parse_operand_result
4891 parse_shifter_operand_group_reloc (char **str
, int i
)
4893 /* Determine if we have the sequence of characters #: or just :
4894 coming next. If we do, then we check for a group relocation.
4895 If we don't, punt the whole lot to parse_shifter_operand. */
4897 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4898 || (*str
)[0] == ':')
4900 struct group_reloc_table_entry
*entry
;
4902 if ((*str
)[0] == '#')
4907 /* Try to parse a group relocation. Anything else is an error. */
4908 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4910 inst
.error
= _("unknown group relocation");
4911 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4914 /* We now have the group relocation table entry corresponding to
4915 the name in the assembler source. Next, we parse the expression. */
4916 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4917 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4919 /* Record the relocation type (always the ALU variant here). */
4920 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4921 gas_assert (inst
.reloc
.type
!= 0);
4923 return PARSE_OPERAND_SUCCESS
;
4926 return parse_shifter_operand (str
, i
) == SUCCESS
4927 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4929 /* Never reached. */
4932 /* Parse all forms of an ARM address expression. Information is written
4933 to inst.operands[i] and/or inst.reloc.
4935 Preindexed addressing (.preind=1):
4937 [Rn, #offset] .reg=Rn .reloc.exp=offset
4938 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4939 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4940 .shift_kind=shift .reloc.exp=shift_imm
4942 These three may have a trailing ! which causes .writeback to be set also.
4944 Postindexed addressing (.postind=1, .writeback=1):
4946 [Rn], #offset .reg=Rn .reloc.exp=offset
4947 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4948 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4949 .shift_kind=shift .reloc.exp=shift_imm
4951 Unindexed addressing (.preind=0, .postind=0):
4953 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4957 [Rn]{!} shorthand for [Rn,#0]{!}
4958 =immediate .isreg=0 .reloc.exp=immediate
4959 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4961 It is the caller's responsibility to check for addressing modes not
4962 supported by the instruction, and to set inst.reloc.type. */
4964 static parse_operand_result
4965 parse_address_main (char **str
, int i
, int group_relocations
,
4966 group_reloc_type group_type
)
4971 if (skip_past_char (&p
, '[') == FAIL
)
4973 if (skip_past_char (&p
, '=') == FAIL
)
4975 /* Bare address - translate to PC-relative offset. */
4976 inst
.reloc
.pc_rel
= 1;
4977 inst
.operands
[i
].reg
= REG_PC
;
4978 inst
.operands
[i
].isreg
= 1;
4979 inst
.operands
[i
].preind
= 1;
4981 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
4983 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4984 return PARSE_OPERAND_FAIL
;
4987 return PARSE_OPERAND_SUCCESS
;
4990 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4992 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4993 return PARSE_OPERAND_FAIL
;
4995 inst
.operands
[i
].reg
= reg
;
4996 inst
.operands
[i
].isreg
= 1;
4998 if (skip_past_comma (&p
) == SUCCESS
)
5000 inst
.operands
[i
].preind
= 1;
5003 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5005 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5007 inst
.operands
[i
].imm
= reg
;
5008 inst
.operands
[i
].immisreg
= 1;
5010 if (skip_past_comma (&p
) == SUCCESS
)
5011 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5012 return PARSE_OPERAND_FAIL
;
5014 else if (skip_past_char (&p
, ':') == SUCCESS
)
5016 /* FIXME: '@' should be used here, but it's filtered out by generic
5017 code before we get to see it here. This may be subject to
5020 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5021 if (exp
.X_op
!= O_constant
)
5023 inst
.error
= _("alignment must be constant");
5024 return PARSE_OPERAND_FAIL
;
5026 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5027 inst
.operands
[i
].immisalign
= 1;
5028 /* Alignments are not pre-indexes. */
5029 inst
.operands
[i
].preind
= 0;
5033 if (inst
.operands
[i
].negative
)
5035 inst
.operands
[i
].negative
= 0;
5039 if (group_relocations
5040 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5042 struct group_reloc_table_entry
*entry
;
5044 /* Skip over the #: or : sequence. */
5050 /* Try to parse a group relocation. Anything else is an
5052 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5054 inst
.error
= _("unknown group relocation");
5055 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5058 /* We now have the group relocation table entry corresponding to
5059 the name in the assembler source. Next, we parse the
5061 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5062 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5064 /* Record the relocation type. */
5068 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5072 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5076 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5083 if (inst
.reloc
.type
== 0)
5085 inst
.error
= _("this group relocation is not allowed on this instruction");
5086 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5090 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5091 return PARSE_OPERAND_FAIL
;
5095 if (skip_past_char (&p
, ']') == FAIL
)
5097 inst
.error
= _("']' expected");
5098 return PARSE_OPERAND_FAIL
;
5101 if (skip_past_char (&p
, '!') == SUCCESS
)
5102 inst
.operands
[i
].writeback
= 1;
5104 else if (skip_past_comma (&p
) == SUCCESS
)
5106 if (skip_past_char (&p
, '{') == SUCCESS
)
5108 /* [Rn], {expr} - unindexed, with option */
5109 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5110 0, 255, TRUE
) == FAIL
)
5111 return PARSE_OPERAND_FAIL
;
5113 if (skip_past_char (&p
, '}') == FAIL
)
5115 inst
.error
= _("'}' expected at end of 'option' field");
5116 return PARSE_OPERAND_FAIL
;
5118 if (inst
.operands
[i
].preind
)
5120 inst
.error
= _("cannot combine index with option");
5121 return PARSE_OPERAND_FAIL
;
5124 return PARSE_OPERAND_SUCCESS
;
5128 inst
.operands
[i
].postind
= 1;
5129 inst
.operands
[i
].writeback
= 1;
5131 if (inst
.operands
[i
].preind
)
5133 inst
.error
= _("cannot combine pre- and post-indexing");
5134 return PARSE_OPERAND_FAIL
;
5138 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5140 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5142 /* We might be using the immediate for alignment already. If we
5143 are, OR the register number into the low-order bits. */
5144 if (inst
.operands
[i
].immisalign
)
5145 inst
.operands
[i
].imm
|= reg
;
5147 inst
.operands
[i
].imm
= reg
;
5148 inst
.operands
[i
].immisreg
= 1;
5150 if (skip_past_comma (&p
) == SUCCESS
)
5151 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5152 return PARSE_OPERAND_FAIL
;
5156 if (inst
.operands
[i
].negative
)
5158 inst
.operands
[i
].negative
= 0;
5161 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5162 return PARSE_OPERAND_FAIL
;
5167 /* If at this point neither .preind nor .postind is set, we have a
5168 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5169 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5171 inst
.operands
[i
].preind
= 1;
5172 inst
.reloc
.exp
.X_op
= O_constant
;
5173 inst
.reloc
.exp
.X_add_number
= 0;
5176 return PARSE_OPERAND_SUCCESS
;
5180 parse_address (char **str
, int i
)
5182 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5186 static parse_operand_result
5187 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5189 return parse_address_main (str
, i
, 1, type
);
5192 /* Parse an operand for a MOVW or MOVT instruction. */
5194 parse_half (char **str
)
5199 skip_past_char (&p
, '#');
5200 if (strncasecmp (p
, ":lower16:", 9) == 0)
5201 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5202 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5203 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5205 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5208 skip_whitespace (p
);
5211 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5214 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5216 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5218 inst
.error
= _("constant expression expected");
5221 if (inst
.reloc
.exp
.X_add_number
< 0
5222 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5224 inst
.error
= _("immediate value out of range");
5232 /* Miscellaneous. */
5234 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5235 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5237 parse_psr (char **str
)
5240 unsigned long psr_field
;
5241 const struct asm_psr
*psr
;
5244 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5245 feature for ease of use and backwards compatibility. */
5247 if (strncasecmp (p
, "SPSR", 4) == 0)
5248 psr_field
= SPSR_BIT
;
5249 else if (strncasecmp (p
, "CPSR", 4) == 0)
5256 while (ISALNUM (*p
) || *p
== '_');
5258 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5270 /* A suffix follows. */
5276 while (ISALNUM (*p
) || *p
== '_');
5278 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5283 psr_field
|= psr
->field
;
5288 goto error
; /* Garbage after "[CS]PSR". */
5290 psr_field
|= (PSR_c
| PSR_f
);
5296 inst
.error
= _("flag for {c}psr instruction expected");
5300 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5301 value suitable for splatting into the AIF field of the instruction. */
5304 parse_cps_flags (char **str
)
5313 case '\0': case ',':
5316 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5317 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5318 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5321 inst
.error
= _("unrecognized CPS flag");
5326 if (saw_a_flag
== 0)
5328 inst
.error
= _("missing CPS flags");
5336 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5337 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5340 parse_endian_specifier (char **str
)
5345 if (strncasecmp (s
, "BE", 2))
5347 else if (strncasecmp (s
, "LE", 2))
5351 inst
.error
= _("valid endian specifiers are be or le");
5355 if (ISALNUM (s
[2]) || s
[2] == '_')
5357 inst
.error
= _("valid endian specifiers are be or le");
5362 return little_endian
;
5365 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5366 value suitable for poking into the rotate field of an sxt or sxta
5367 instruction, or FAIL on error. */
5370 parse_ror (char **str
)
5375 if (strncasecmp (s
, "ROR", 3) == 0)
5379 inst
.error
= _("missing rotation field after comma");
5383 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5388 case 0: *str
= s
; return 0x0;
5389 case 8: *str
= s
; return 0x1;
5390 case 16: *str
= s
; return 0x2;
5391 case 24: *str
= s
; return 0x3;
5394 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5399 /* Parse a conditional code (from conds[] below). The value returned is in the
5400 range 0 .. 14, or FAIL. */
5402 parse_cond (char **str
)
5405 const struct asm_cond
*c
;
5407 /* Condition codes are always 2 characters, so matching up to
5408 3 characters is sufficient. */
5413 while (ISALPHA (*q
) && n
< 3)
5415 cond
[n
] = TOLOWER (*q
);
5420 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5423 inst
.error
= _("condition required");
5431 /* Parse an option for a barrier instruction. Returns the encoding for the
5434 parse_barrier (char **str
)
5437 const struct asm_barrier_opt
*o
;
5440 while (ISALPHA (*q
))
5443 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5452 /* Parse the operands of a table branch instruction. Similar to a memory
5455 parse_tb (char **str
)
5460 if (skip_past_char (&p
, '[') == FAIL
)
5462 inst
.error
= _("'[' expected");
5466 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5468 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5471 inst
.operands
[0].reg
= reg
;
5473 if (skip_past_comma (&p
) == FAIL
)
5475 inst
.error
= _("',' expected");
5479 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5481 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5484 inst
.operands
[0].imm
= reg
;
5486 if (skip_past_comma (&p
) == SUCCESS
)
5488 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5490 if (inst
.reloc
.exp
.X_add_number
!= 1)
5492 inst
.error
= _("invalid shift");
5495 inst
.operands
[0].shifted
= 1;
5498 if (skip_past_char (&p
, ']') == FAIL
)
5500 inst
.error
= _("']' expected");
5507 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5508 information on the types the operands can take and how they are encoded.
5509 Up to four operands may be read; this function handles setting the
5510 ".present" field for each read operand itself.
5511 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5512 else returns FAIL. */
5515 parse_neon_mov (char **str
, int *which_operand
)
5517 int i
= *which_operand
, val
;
5518 enum arm_reg_type rtype
;
5520 struct neon_type_el optype
;
5522 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5524 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5525 inst
.operands
[i
].reg
= val
;
5526 inst
.operands
[i
].isscalar
= 1;
5527 inst
.operands
[i
].vectype
= optype
;
5528 inst
.operands
[i
++].present
= 1;
5530 if (skip_past_comma (&ptr
) == FAIL
)
5533 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5536 inst
.operands
[i
].reg
= val
;
5537 inst
.operands
[i
].isreg
= 1;
5538 inst
.operands
[i
].present
= 1;
5540 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5543 /* Cases 0, 1, 2, 3, 5 (D only). */
5544 if (skip_past_comma (&ptr
) == FAIL
)
5547 inst
.operands
[i
].reg
= val
;
5548 inst
.operands
[i
].isreg
= 1;
5549 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5550 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5551 inst
.operands
[i
].isvec
= 1;
5552 inst
.operands
[i
].vectype
= optype
;
5553 inst
.operands
[i
++].present
= 1;
5555 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5557 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5558 Case 13: VMOV <Sd>, <Rm> */
5559 inst
.operands
[i
].reg
= val
;
5560 inst
.operands
[i
].isreg
= 1;
5561 inst
.operands
[i
].present
= 1;
5563 if (rtype
== REG_TYPE_NQ
)
5565 first_error (_("can't use Neon quad register here"));
5568 else if (rtype
!= REG_TYPE_VFS
)
5571 if (skip_past_comma (&ptr
) == FAIL
)
5573 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5575 inst
.operands
[i
].reg
= val
;
5576 inst
.operands
[i
].isreg
= 1;
5577 inst
.operands
[i
].present
= 1;
5580 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5583 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5584 Case 1: VMOV<c><q> <Dd>, <Dm>
5585 Case 8: VMOV.F32 <Sd>, <Sm>
5586 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5588 inst
.operands
[i
].reg
= val
;
5589 inst
.operands
[i
].isreg
= 1;
5590 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5591 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5592 inst
.operands
[i
].isvec
= 1;
5593 inst
.operands
[i
].vectype
= optype
;
5594 inst
.operands
[i
].present
= 1;
5596 if (skip_past_comma (&ptr
) == SUCCESS
)
5601 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5604 inst
.operands
[i
].reg
= val
;
5605 inst
.operands
[i
].isreg
= 1;
5606 inst
.operands
[i
++].present
= 1;
5608 if (skip_past_comma (&ptr
) == FAIL
)
5611 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5614 inst
.operands
[i
].reg
= val
;
5615 inst
.operands
[i
].isreg
= 1;
5616 inst
.operands
[i
++].present
= 1;
5619 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5620 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5621 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5622 Case 10: VMOV.F32 <Sd>, #<imm>
5623 Case 11: VMOV.F64 <Dd>, #<imm> */
5624 inst
.operands
[i
].immisfloat
= 1;
5625 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5626 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5627 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5631 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5635 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5638 inst
.operands
[i
].reg
= val
;
5639 inst
.operands
[i
].isreg
= 1;
5640 inst
.operands
[i
++].present
= 1;
5642 if (skip_past_comma (&ptr
) == FAIL
)
5645 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5647 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5648 inst
.operands
[i
].reg
= val
;
5649 inst
.operands
[i
].isscalar
= 1;
5650 inst
.operands
[i
].present
= 1;
5651 inst
.operands
[i
].vectype
= optype
;
5653 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5655 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5656 inst
.operands
[i
].reg
= val
;
5657 inst
.operands
[i
].isreg
= 1;
5658 inst
.operands
[i
++].present
= 1;
5660 if (skip_past_comma (&ptr
) == FAIL
)
5663 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5666 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5670 inst
.operands
[i
].reg
= val
;
5671 inst
.operands
[i
].isreg
= 1;
5672 inst
.operands
[i
].isvec
= 1;
5673 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5674 inst
.operands
[i
].vectype
= optype
;
5675 inst
.operands
[i
].present
= 1;
5677 if (rtype
== REG_TYPE_VFS
)
5681 if (skip_past_comma (&ptr
) == FAIL
)
5683 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5686 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5689 inst
.operands
[i
].reg
= val
;
5690 inst
.operands
[i
].isreg
= 1;
5691 inst
.operands
[i
].isvec
= 1;
5692 inst
.operands
[i
].issingle
= 1;
5693 inst
.operands
[i
].vectype
= optype
;
5694 inst
.operands
[i
].present
= 1;
5697 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5701 inst
.operands
[i
].reg
= val
;
5702 inst
.operands
[i
].isreg
= 1;
5703 inst
.operands
[i
].isvec
= 1;
5704 inst
.operands
[i
].issingle
= 1;
5705 inst
.operands
[i
].vectype
= optype
;
5706 inst
.operands
[i
++].present
= 1;
5711 first_error (_("parse error"));
5715 /* Successfully parsed the operands. Update args. */
5721 first_error (_("expected comma"));
5725 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5729 /* Matcher codes for parse_operands. */
5730 enum operand_parse_code
5732 OP_stop
, /* end of line */
5734 OP_RR
, /* ARM register */
5735 OP_RRnpc
, /* ARM register, not r15 */
5736 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5737 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5738 OP_RCP
, /* Coprocessor number */
5739 OP_RCN
, /* Coprocessor register */
5740 OP_RF
, /* FPA register */
5741 OP_RVS
, /* VFP single precision register */
5742 OP_RVD
, /* VFP double precision register (0..15) */
5743 OP_RND
, /* Neon double precision register (0..31) */
5744 OP_RNQ
, /* Neon quad precision register */
5745 OP_RVSD
, /* VFP single or double precision register */
5746 OP_RNDQ
, /* Neon double or quad precision register */
5747 OP_RNSDQ
, /* Neon single, double or quad precision register */
5748 OP_RNSC
, /* Neon scalar D[X] */
5749 OP_RVC
, /* VFP control register */
5750 OP_RMF
, /* Maverick F register */
5751 OP_RMD
, /* Maverick D register */
5752 OP_RMFX
, /* Maverick FX register */
5753 OP_RMDX
, /* Maverick DX register */
5754 OP_RMAX
, /* Maverick AX register */
5755 OP_RMDS
, /* Maverick DSPSC register */
5756 OP_RIWR
, /* iWMMXt wR register */
5757 OP_RIWC
, /* iWMMXt wC register */
5758 OP_RIWG
, /* iWMMXt wCG register */
5759 OP_RXA
, /* XScale accumulator register */
5761 OP_REGLST
, /* ARM register list */
5762 OP_VRSLST
, /* VFP single-precision register list */
5763 OP_VRDLST
, /* VFP double-precision register list */
5764 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5765 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5766 OP_NSTRLST
, /* Neon element/structure list */
5768 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5769 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5770 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5771 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5772 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5773 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5774 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5775 OP_VMOV
, /* Neon VMOV operands. */
5776 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5777 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5778 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5780 OP_I0
, /* immediate zero */
5781 OP_I7
, /* immediate value 0 .. 7 */
5782 OP_I15
, /* 0 .. 15 */
5783 OP_I16
, /* 1 .. 16 */
5784 OP_I16z
, /* 0 .. 16 */
5785 OP_I31
, /* 0 .. 31 */
5786 OP_I31w
, /* 0 .. 31, optional trailing ! */
5787 OP_I32
, /* 1 .. 32 */
5788 OP_I32z
, /* 0 .. 32 */
5789 OP_I63
, /* 0 .. 63 */
5790 OP_I63s
, /* -64 .. 63 */
5791 OP_I64
, /* 1 .. 64 */
5792 OP_I64z
, /* 0 .. 64 */
5793 OP_I255
, /* 0 .. 255 */
5795 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5796 OP_I7b
, /* 0 .. 7 */
5797 OP_I15b
, /* 0 .. 15 */
5798 OP_I31b
, /* 0 .. 31 */
5800 OP_SH
, /* shifter operand */
5801 OP_SHG
, /* shifter operand with possible group relocation */
5802 OP_ADDR
, /* Memory address expression (any mode) */
5803 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5804 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5805 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5806 OP_EXP
, /* arbitrary expression */
5807 OP_EXPi
, /* same, with optional immediate prefix */
5808 OP_EXPr
, /* same, with optional relocation suffix */
5809 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5811 OP_CPSF
, /* CPS flags */
5812 OP_ENDI
, /* Endianness specifier */
5813 OP_PSR
, /* CPSR/SPSR mask for msr */
5814 OP_COND
, /* conditional code */
5815 OP_TB
, /* Table branch. */
5817 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5818 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5820 OP_RRnpc_I0
, /* ARM register or literal 0 */
5821 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5822 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5823 OP_RF_IF
, /* FPA register or immediate */
5824 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5825 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5827 /* Optional operands. */
5828 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5829 OP_oI31b
, /* 0 .. 31 */
5830 OP_oI32b
, /* 1 .. 32 */
5831 OP_oIffffb
, /* 0 .. 65535 */
5832 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5834 OP_oRR
, /* ARM register */
5835 OP_oRRnpc
, /* ARM register, not the PC */
5836 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5837 OP_oRND
, /* Optional Neon double precision register */
5838 OP_oRNQ
, /* Optional Neon quad precision register */
5839 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5840 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5841 OP_oSHll
, /* LSL immediate */
5842 OP_oSHar
, /* ASR immediate */
5843 OP_oSHllar
, /* LSL or ASR immediate */
5844 OP_oROR
, /* ROR 0/8/16/24 */
5845 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5847 OP_FIRST_OPTIONAL
= OP_oI7b
5850 /* Generic instruction operand parser. This does no encoding and no
5851 semantic validation; it merely squirrels values away in the inst
5852 structure. Returns SUCCESS or FAIL depending on whether the
5853 specified grammar matched. */
5855 parse_operands (char *str
, const unsigned char *pattern
)
5857 unsigned const char *upat
= pattern
;
5858 char *backtrack_pos
= 0;
5859 const char *backtrack_error
= 0;
5860 int i
, val
, backtrack_index
= 0;
5861 enum arm_reg_type rtype
;
5862 parse_operand_result result
;
5864 #define po_char_or_fail(chr) \
5867 if (skip_past_char (&str, chr) == FAIL) \
5872 #define po_reg_or_fail(regtype) \
5875 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5876 & inst.operands[i].vectype); \
5879 first_error (_(reg_expected_msgs[regtype])); \
5882 inst.operands[i].reg = val; \
5883 inst.operands[i].isreg = 1; \
5884 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5885 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5886 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5887 || rtype == REG_TYPE_VFD \
5888 || rtype == REG_TYPE_NQ); \
5892 #define po_reg_or_goto(regtype, label) \
5895 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5896 & inst.operands[i].vectype); \
5900 inst.operands[i].reg = val; \
5901 inst.operands[i].isreg = 1; \
5902 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5903 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5904 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5905 || rtype == REG_TYPE_VFD \
5906 || rtype == REG_TYPE_NQ); \
5910 #define po_imm_or_fail(min, max, popt) \
5913 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5915 inst.operands[i].imm = val; \
5919 #define po_scalar_or_goto(elsz, label) \
5922 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5925 inst.operands[i].reg = val; \
5926 inst.operands[i].isscalar = 1; \
5930 #define po_misc_or_fail(expr) \
5938 #define po_misc_or_fail_no_backtrack(expr) \
5942 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5943 backtrack_pos = 0; \
5944 if (result != PARSE_OPERAND_SUCCESS) \
5949 skip_whitespace (str
);
5951 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5953 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5955 /* Remember where we are in case we need to backtrack. */
5956 gas_assert (!backtrack_pos
);
5957 backtrack_pos
= str
;
5958 backtrack_error
= inst
.error
;
5959 backtrack_index
= i
;
5962 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5963 po_char_or_fail (',');
5971 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5972 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5973 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5974 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5975 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5976 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5978 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5980 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5982 /* Also accept generic coprocessor regs for unknown registers. */
5984 po_reg_or_fail (REG_TYPE_CN
);
5986 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5987 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5988 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5989 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5990 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5991 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5992 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5993 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5994 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5995 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5997 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5999 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6000 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6002 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6004 /* Neon scalar. Using an element size of 8 means that some invalid
6005 scalars are accepted here, so deal with those in later code. */
6006 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6008 /* WARNING: We can expand to two operands here. This has the potential
6009 to totally confuse the backtracking mechanism! It will be OK at
6010 least as long as we don't try to use optional args as well,
6014 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6015 inst
.operands
[i
].present
= 1;
6017 skip_past_comma (&str
);
6018 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6021 /* Optional register operand was omitted. Unfortunately, it's in
6022 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6023 here (this is a bit grotty). */
6024 inst
.operands
[i
] = inst
.operands
[i
-1];
6025 inst
.operands
[i
-1].present
= 0;
6028 /* There's a possibility of getting a 64-bit immediate here, so
6029 we need special handling. */
6030 if (parse_big_immediate (&str
, i
) == FAIL
)
6032 inst
.error
= _("immediate value is out of range");
6040 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6043 po_imm_or_fail (0, 0, TRUE
);
6048 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6053 po_scalar_or_goto (8, try_rr
);
6056 po_reg_or_fail (REG_TYPE_RN
);
6062 po_scalar_or_goto (8, try_nsdq
);
6065 po_reg_or_fail (REG_TYPE_NSDQ
);
6071 po_scalar_or_goto (8, try_ndq
);
6074 po_reg_or_fail (REG_TYPE_NDQ
);
6080 po_scalar_or_goto (8, try_vfd
);
6083 po_reg_or_fail (REG_TYPE_VFD
);
6088 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6089 not careful then bad things might happen. */
6090 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6095 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6098 /* There's a possibility of getting a 64-bit immediate here, so
6099 we need special handling. */
6100 if (parse_big_immediate (&str
, i
) == FAIL
)
6102 inst
.error
= _("immediate value is out of range");
6110 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6113 po_imm_or_fail (0, 63, TRUE
);
6118 po_char_or_fail ('[');
6119 po_reg_or_fail (REG_TYPE_RN
);
6120 po_char_or_fail (']');
6125 po_reg_or_fail (REG_TYPE_RN
);
6126 if (skip_past_char (&str
, '!') == SUCCESS
)
6127 inst
.operands
[i
].writeback
= 1;
6131 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6132 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6133 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6134 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6135 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6136 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6137 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6138 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6139 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6140 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6141 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6142 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6144 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6146 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6147 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6149 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6150 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6151 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6153 /* Immediate variants */
6155 po_char_or_fail ('{');
6156 po_imm_or_fail (0, 255, TRUE
);
6157 po_char_or_fail ('}');
6161 /* The expression parser chokes on a trailing !, so we have
6162 to find it first and zap it. */
6165 while (*s
&& *s
!= ',')
6170 inst
.operands
[i
].writeback
= 1;
6172 po_imm_or_fail (0, 31, TRUE
);
6180 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6185 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6190 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6192 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6194 val
= parse_reloc (&str
);
6197 inst
.error
= _("unrecognized relocation suffix");
6200 else if (val
!= BFD_RELOC_UNUSED
)
6202 inst
.operands
[i
].imm
= val
;
6203 inst
.operands
[i
].hasreloc
= 1;
6208 /* Operand for MOVW or MOVT. */
6210 po_misc_or_fail (parse_half (&str
));
6213 /* Register or expression. */
6214 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6215 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6217 /* Register or immediate. */
6218 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6219 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6221 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6223 if (!is_immediate_prefix (*str
))
6226 val
= parse_fpa_immediate (&str
);
6229 /* FPA immediates are encoded as registers 8-15.
6230 parse_fpa_immediate has already applied the offset. */
6231 inst
.operands
[i
].reg
= val
;
6232 inst
.operands
[i
].isreg
= 1;
6235 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6236 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6238 /* Two kinds of register. */
6241 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6243 || (rege
->type
!= REG_TYPE_MMXWR
6244 && rege
->type
!= REG_TYPE_MMXWC
6245 && rege
->type
!= REG_TYPE_MMXWCG
))
6247 inst
.error
= _("iWMMXt data or control register expected");
6250 inst
.operands
[i
].reg
= rege
->number
;
6251 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6257 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6259 || (rege
->type
!= REG_TYPE_MMXWC
6260 && rege
->type
!= REG_TYPE_MMXWCG
))
6262 inst
.error
= _("iWMMXt control register expected");
6265 inst
.operands
[i
].reg
= rege
->number
;
6266 inst
.operands
[i
].isreg
= 1;
6271 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6272 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6273 case OP_oROR
: val
= parse_ror (&str
); break;
6274 case OP_PSR
: val
= parse_psr (&str
); break;
6275 case OP_COND
: val
= parse_cond (&str
); break;
6276 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6279 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6280 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6283 val
= parse_psr (&str
);
6287 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6290 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6292 if (strncasecmp (str
, "APSR_", 5) == 0)
6299 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6300 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6301 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6302 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6303 default: found
= 16;
6307 inst
.operands
[i
].isvec
= 1;
6308 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6309 inst
.operands
[i
].reg
= REG_PC
;
6316 po_misc_or_fail (parse_tb (&str
));
6319 /* Register lists. */
6321 val
= parse_reg_list (&str
);
6324 inst
.operands
[1].writeback
= 1;
6330 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6334 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6338 /* Allow Q registers too. */
6339 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6344 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6346 inst
.operands
[i
].issingle
= 1;
6351 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6356 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6357 &inst
.operands
[i
].vectype
);
6360 /* Addressing modes */
6362 po_misc_or_fail (parse_address (&str
, i
));
6366 po_misc_or_fail_no_backtrack (
6367 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6371 po_misc_or_fail_no_backtrack (
6372 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6376 po_misc_or_fail_no_backtrack (
6377 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6381 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6385 po_misc_or_fail_no_backtrack (
6386 parse_shifter_operand_group_reloc (&str
, i
));
6390 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6394 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6398 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6402 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6405 /* Various value-based sanity checks and shared operations. We
6406 do not signal immediate failures for the register constraints;
6407 this allows a syntax error to take precedence. */
6416 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6417 inst
.error
= BAD_PC
;
6435 inst
.operands
[i
].imm
= val
;
6442 /* If we get here, this operand was successfully parsed. */
6443 inst
.operands
[i
].present
= 1;
6447 inst
.error
= BAD_ARGS
;
6452 /* The parse routine should already have set inst.error, but set a
6453 default here just in case. */
6455 inst
.error
= _("syntax error");
6459 /* Do not backtrack over a trailing optional argument that
6460 absorbed some text. We will only fail again, with the
6461 'garbage following instruction' error message, which is
6462 probably less helpful than the current one. */
6463 if (backtrack_index
== i
&& backtrack_pos
!= str
6464 && upat
[i
+1] == OP_stop
)
6467 inst
.error
= _("syntax error");
6471 /* Try again, skipping the optional argument at backtrack_pos. */
6472 str
= backtrack_pos
;
6473 inst
.error
= backtrack_error
;
6474 inst
.operands
[backtrack_index
].present
= 0;
6475 i
= backtrack_index
;
6479 /* Check that we have parsed all the arguments. */
6480 if (*str
!= '\0' && !inst
.error
)
6481 inst
.error
= _("garbage following instruction");
6483 return inst
.error
? FAIL
: SUCCESS
;
6486 #undef po_char_or_fail
6487 #undef po_reg_or_fail
6488 #undef po_reg_or_goto
6489 #undef po_imm_or_fail
6490 #undef po_scalar_or_fail
6492 /* Shorthand macro for instruction encoding functions issuing errors. */
6493 #define constraint(expr, err) \
6504 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6505 instructions are unpredictable if these registers are used. This
6506 is the BadReg predicate in ARM's Thumb-2 documentation. */
6507 #define reject_bad_reg(reg) \
6509 if (reg == REG_SP || reg == REG_PC) \
6511 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6516 /* If REG is R13 (the stack pointer), warn that its use is
6518 #define warn_deprecated_sp(reg) \
6520 if (warn_on_deprecated && reg == REG_SP) \
6521 as_warn (_("use of r13 is deprecated")); \
6524 /* Functions for operand encoding. ARM, then Thumb. */
6526 #define rotate_left(v, n) (v << n | v >> (32 - n))
6528 /* If VAL can be encoded in the immediate field of an ARM instruction,
6529 return the encoded form. Otherwise, return FAIL. */
6532 encode_arm_immediate (unsigned int val
)
6536 for (i
= 0; i
< 32; i
+= 2)
6537 if ((a
= rotate_left (val
, i
)) <= 0xff)
6538 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6543 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6544 return the encoded form. Otherwise, return FAIL. */
6546 encode_thumb32_immediate (unsigned int val
)
6553 for (i
= 1; i
<= 24; i
++)
6556 if ((val
& ~(0xff << i
)) == 0)
6557 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6561 if (val
== ((a
<< 16) | a
))
6563 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6567 if (val
== ((a
<< 16) | a
))
6568 return 0x200 | (a
>> 8);
6572 /* Encode a VFP SP or DP register number into inst.instruction. */
6575 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6577 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6580 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6583 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6586 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6591 first_error (_("D register out of range for selected VFP version"));
6599 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6603 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6607 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6611 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6615 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6619 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6627 /* Encode a <shift> in an ARM-format instruction. The immediate,
6628 if any, is handled by md_apply_fix. */
6630 encode_arm_shift (int i
)
6632 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6633 inst
.instruction
|= SHIFT_ROR
<< 5;
6636 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6637 if (inst
.operands
[i
].immisreg
)
6639 inst
.instruction
|= SHIFT_BY_REG
;
6640 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6643 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6648 encode_arm_shifter_operand (int i
)
6650 if (inst
.operands
[i
].isreg
)
6652 inst
.instruction
|= inst
.operands
[i
].reg
;
6653 encode_arm_shift (i
);
6656 inst
.instruction
|= INST_IMMEDIATE
;
6659 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6661 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6663 gas_assert (inst
.operands
[i
].isreg
);
6664 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6666 if (inst
.operands
[i
].preind
)
6670 inst
.error
= _("instruction does not accept preindexed addressing");
6673 inst
.instruction
|= PRE_INDEX
;
6674 if (inst
.operands
[i
].writeback
)
6675 inst
.instruction
|= WRITE_BACK
;
6678 else if (inst
.operands
[i
].postind
)
6680 gas_assert (inst
.operands
[i
].writeback
);
6682 inst
.instruction
|= WRITE_BACK
;
6684 else /* unindexed - only for coprocessor */
6686 inst
.error
= _("instruction does not accept unindexed addressing");
6690 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6691 && (((inst
.instruction
& 0x000f0000) >> 16)
6692 == ((inst
.instruction
& 0x0000f000) >> 12)))
6693 as_warn ((inst
.instruction
& LOAD_BIT
)
6694 ? _("destination register same as write-back base")
6695 : _("source register same as write-back base"));
6698 /* inst.operands[i] was set up by parse_address. Encode it into an
6699 ARM-format mode 2 load or store instruction. If is_t is true,
6700 reject forms that cannot be used with a T instruction (i.e. not
6703 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6705 encode_arm_addr_mode_common (i
, is_t
);
6707 if (inst
.operands
[i
].immisreg
)
6709 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6710 inst
.instruction
|= inst
.operands
[i
].imm
;
6711 if (!inst
.operands
[i
].negative
)
6712 inst
.instruction
|= INDEX_UP
;
6713 if (inst
.operands
[i
].shifted
)
6715 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6716 inst
.instruction
|= SHIFT_ROR
<< 5;
6719 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6720 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6724 else /* immediate offset in inst.reloc */
6726 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6727 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6731 /* inst.operands[i] was set up by parse_address. Encode it into an
6732 ARM-format mode 3 load or store instruction. Reject forms that
6733 cannot be used with such instructions. If is_t is true, reject
6734 forms that cannot be used with a T instruction (i.e. not
6737 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6739 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6741 inst
.error
= _("instruction does not accept scaled register index");
6745 encode_arm_addr_mode_common (i
, is_t
);
6747 if (inst
.operands
[i
].immisreg
)
6749 inst
.instruction
|= inst
.operands
[i
].imm
;
6750 if (!inst
.operands
[i
].negative
)
6751 inst
.instruction
|= INDEX_UP
;
6753 else /* immediate offset in inst.reloc */
6755 inst
.instruction
|= HWOFFSET_IMM
;
6756 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6757 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6761 /* inst.operands[i] was set up by parse_address. Encode it into an
6762 ARM-format instruction. Reject all forms which cannot be encoded
6763 into a coprocessor load/store instruction. If wb_ok is false,
6764 reject use of writeback; if unind_ok is false, reject use of
6765 unindexed addressing. If reloc_override is not 0, use it instead
6766 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6767 (in which case it is preserved). */
6770 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6772 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6774 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6776 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6778 gas_assert (!inst
.operands
[i
].writeback
);
6781 inst
.error
= _("instruction does not support unindexed addressing");
6784 inst
.instruction
|= inst
.operands
[i
].imm
;
6785 inst
.instruction
|= INDEX_UP
;
6789 if (inst
.operands
[i
].preind
)
6790 inst
.instruction
|= PRE_INDEX
;
6792 if (inst
.operands
[i
].writeback
)
6794 if (inst
.operands
[i
].reg
== REG_PC
)
6796 inst
.error
= _("pc may not be used with write-back");
6801 inst
.error
= _("instruction does not support writeback");
6804 inst
.instruction
|= WRITE_BACK
;
6808 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6809 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6810 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6811 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6814 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6816 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6822 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6823 Determine whether it can be performed with a move instruction; if
6824 it can, convert inst.instruction to that move instruction and
6825 return TRUE; if it can't, convert inst.instruction to a literal-pool
6826 load and return FALSE. If this is not a valid thing to do in the
6827 current context, set inst.error and return TRUE.
6829 inst.operands[i] describes the destination register. */
6832 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6837 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6841 if ((inst
.instruction
& tbit
) == 0)
6843 inst
.error
= _("invalid pseudo operation");
6846 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6848 inst
.error
= _("constant expression expected");
6851 if (inst
.reloc
.exp
.X_op
== O_constant
)
6855 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6857 /* This can be done with a mov(1) instruction. */
6858 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6859 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6865 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6868 /* This can be done with a mov instruction. */
6869 inst
.instruction
&= LITERAL_MASK
;
6870 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6871 inst
.instruction
|= value
& 0xfff;
6875 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6878 /* This can be done with a mvn instruction. */
6879 inst
.instruction
&= LITERAL_MASK
;
6880 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6881 inst
.instruction
|= value
& 0xfff;
6887 if (add_to_lit_pool () == FAIL
)
6889 inst
.error
= _("literal pool insertion failed");
6892 inst
.operands
[1].reg
= REG_PC
;
6893 inst
.operands
[1].isreg
= 1;
6894 inst
.operands
[1].preind
= 1;
6895 inst
.reloc
.pc_rel
= 1;
6896 inst
.reloc
.type
= (thumb_p
6897 ? BFD_RELOC_ARM_THUMB_OFFSET
6899 ? BFD_RELOC_ARM_HWLITERAL
6900 : BFD_RELOC_ARM_LITERAL
));
6904 /* Functions for instruction encoding, sorted by sub-architecture.
6905 First some generics; their names are taken from the conventional
6906 bit positions for register arguments in ARM format instructions. */
6916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6923 inst
.instruction
|= inst
.operands
[1].reg
;
6929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6930 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6936 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6937 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6943 unsigned Rn
= inst
.operands
[2].reg
;
6944 /* Enforce restrictions on SWP instruction. */
6945 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6946 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6947 _("Rn must not overlap other operands"));
6948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6949 inst
.instruction
|= inst
.operands
[1].reg
;
6950 inst
.instruction
|= Rn
<< 16;
6956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6958 inst
.instruction
|= inst
.operands
[2].reg
;
6964 inst
.instruction
|= inst
.operands
[0].reg
;
6965 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6966 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6972 inst
.instruction
|= inst
.operands
[0].imm
;
6978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6979 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6982 /* ARM instructions, in alphabetical order by function name (except
6983 that wrapper functions appear immediately after the function they
6986 /* This is a pseudo-op of the form "adr rd, label" to be converted
6987 into a relative address of the form "add rd, pc, #label-.-8". */
6992 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6994 /* Frag hacking will turn this into a sub instruction if the offset turns
6995 out to be negative. */
6996 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6997 inst
.reloc
.pc_rel
= 1;
6998 inst
.reloc
.exp
.X_add_number
-= 8;
7001 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7002 into a relative address of the form:
7003 add rd, pc, #low(label-.-8)"
7004 add rd, rd, #high(label-.-8)" */
7009 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7011 /* Frag hacking will turn this into a sub instruction if the offset turns
7012 out to be negative. */
7013 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7014 inst
.reloc
.pc_rel
= 1;
7015 inst
.size
= INSN_SIZE
* 2;
7016 inst
.reloc
.exp
.X_add_number
-= 8;
7022 if (!inst
.operands
[1].present
)
7023 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7025 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7026 encode_arm_shifter_operand (2);
7032 if (inst
.operands
[0].present
)
7034 constraint ((inst
.instruction
& 0xf0) != 0x40
7035 && inst
.operands
[0].imm
!= 0xf,
7036 _("bad barrier type"));
7037 inst
.instruction
|= inst
.operands
[0].imm
;
7040 inst
.instruction
|= 0xf;
7046 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7047 constraint (msb
> 32, _("bit-field extends past end of register"));
7048 /* The instruction encoding stores the LSB and MSB,
7049 not the LSB and width. */
7050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7051 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7052 inst
.instruction
|= (msb
- 1) << 16;
7060 /* #0 in second position is alternative syntax for bfc, which is
7061 the same instruction but with REG_PC in the Rm field. */
7062 if (!inst
.operands
[1].isreg
)
7063 inst
.operands
[1].reg
= REG_PC
;
7065 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7066 constraint (msb
> 32, _("bit-field extends past end of register"));
7067 /* The instruction encoding stores the LSB and MSB,
7068 not the LSB and width. */
7069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7070 inst
.instruction
|= inst
.operands
[1].reg
;
7071 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7072 inst
.instruction
|= (msb
- 1) << 16;
7078 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7079 _("bit-field extends past end of register"));
7080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7081 inst
.instruction
|= inst
.operands
[1].reg
;
7082 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7083 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7086 /* ARM V5 breakpoint instruction (argument parse)
7087 BKPT <16 bit unsigned immediate>
7088 Instruction is not conditional.
7089 The bit pattern given in insns[] has the COND_ALWAYS condition,
7090 and it is an error if the caller tried to override that. */
7095 /* Top 12 of 16 bits to bits 19:8. */
7096 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7098 /* Bottom 4 of 16 bits to bits 3:0. */
7099 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7103 encode_branch (int default_reloc
)
7105 if (inst
.operands
[0].hasreloc
)
7107 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7108 _("the only suffix valid here is '(plt)'"));
7109 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7113 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7115 inst
.reloc
.pc_rel
= 1;
7122 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7123 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7126 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7133 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7135 if (inst
.cond
== COND_ALWAYS
)
7136 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7138 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7142 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7145 /* ARM V5 branch-link-exchange instruction (argument parse)
7146 BLX <target_addr> ie BLX(1)
7147 BLX{<condition>} <Rm> ie BLX(2)
7148 Unfortunately, there are two different opcodes for this mnemonic.
7149 So, the insns[].value is not used, and the code here zaps values
7150 into inst.instruction.
7151 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7156 if (inst
.operands
[0].isreg
)
7158 /* Arg is a register; the opcode provided by insns[] is correct.
7159 It is not illegal to do "blx pc", just useless. */
7160 if (inst
.operands
[0].reg
== REG_PC
)
7161 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7163 inst
.instruction
|= inst
.operands
[0].reg
;
7167 /* Arg is an address; this instruction cannot be executed
7168 conditionally, and the opcode must be adjusted.
7169 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7170 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7171 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7172 inst
.instruction
= 0xfa000000;
7173 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7180 bfd_boolean want_reloc
;
7182 if (inst
.operands
[0].reg
== REG_PC
)
7183 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7185 inst
.instruction
|= inst
.operands
[0].reg
;
7186 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7187 it is for ARMv4t or earlier. */
7188 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7189 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7193 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7198 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7202 /* ARM v5TEJ. Jump to Jazelle code. */
7207 if (inst
.operands
[0].reg
== REG_PC
)
7208 as_tsktsk (_("use of r15 in bxj is not really useful"));
7210 inst
.instruction
|= inst
.operands
[0].reg
;
7213 /* Co-processor data operation:
7214 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7215 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7219 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7220 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7221 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7222 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7223 inst
.instruction
|= inst
.operands
[4].reg
;
7224 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7230 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7231 encode_arm_shifter_operand (1);
7234 /* Transfer between coprocessor and ARM registers.
7235 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7240 No special properties. */
7247 Rd
= inst
.operands
[2].reg
;
7250 if (inst
.instruction
== 0xee000010
7251 || inst
.instruction
== 0xfe000010)
7253 reject_bad_reg (Rd
);
7256 constraint (Rd
== REG_SP
, BAD_SP
);
7261 if (inst
.instruction
== 0xe000010)
7262 constraint (Rd
== REG_PC
, BAD_PC
);
7266 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7267 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7268 inst
.instruction
|= Rd
<< 12;
7269 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7270 inst
.instruction
|= inst
.operands
[4].reg
;
7271 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7274 /* Transfer between coprocessor register and pair of ARM registers.
7275 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7280 Two XScale instructions are special cases of these:
7282 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7283 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7285 Result unpredictable if Rd or Rn is R15. */
7292 Rd
= inst
.operands
[2].reg
;
7293 Rn
= inst
.operands
[3].reg
;
7297 reject_bad_reg (Rd
);
7298 reject_bad_reg (Rn
);
7302 constraint (Rd
== REG_PC
, BAD_PC
);
7303 constraint (Rn
== REG_PC
, BAD_PC
);
7306 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7307 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7308 inst
.instruction
|= Rd
<< 12;
7309 inst
.instruction
|= Rn
<< 16;
7310 inst
.instruction
|= inst
.operands
[4].reg
;
7316 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7317 if (inst
.operands
[1].present
)
7319 inst
.instruction
|= CPSI_MMOD
;
7320 inst
.instruction
|= inst
.operands
[1].imm
;
7327 inst
.instruction
|= inst
.operands
[0].imm
;
7333 /* There is no IT instruction in ARM mode. We
7334 process it to do the validation as if in
7335 thumb mode, just in case the code gets
7336 assembled for thumb using the unified syntax. */
7341 set_it_insn_type (IT_INSN
);
7342 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7343 now_it
.cc
= inst
.operands
[0].imm
;
7350 int base_reg
= inst
.operands
[0].reg
;
7351 int range
= inst
.operands
[1].imm
;
7353 inst
.instruction
|= base_reg
<< 16;
7354 inst
.instruction
|= range
;
7356 if (inst
.operands
[1].writeback
)
7357 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7359 if (inst
.operands
[0].writeback
)
7361 inst
.instruction
|= WRITE_BACK
;
7362 /* Check for unpredictable uses of writeback. */
7363 if (inst
.instruction
& LOAD_BIT
)
7365 /* Not allowed in LDM type 2. */
7366 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7367 && ((range
& (1 << REG_PC
)) == 0))
7368 as_warn (_("writeback of base register is UNPREDICTABLE"));
7369 /* Only allowed if base reg not in list for other types. */
7370 else if (range
& (1 << base_reg
))
7371 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7375 /* Not allowed for type 2. */
7376 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7377 as_warn (_("writeback of base register is UNPREDICTABLE"));
7378 /* Only allowed if base reg not in list, or first in list. */
7379 else if ((range
& (1 << base_reg
))
7380 && (range
& ((1 << base_reg
) - 1)))
7381 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7386 /* ARMv5TE load-consecutive (argument parse)
7395 constraint (inst
.operands
[0].reg
% 2 != 0,
7396 _("first destination register must be even"));
7397 constraint (inst
.operands
[1].present
7398 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7399 _("can only load two consecutive registers"));
7400 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7401 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7403 if (!inst
.operands
[1].present
)
7404 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7406 if (inst
.instruction
& LOAD_BIT
)
7408 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7409 register and the first register written; we have to diagnose
7410 overlap between the base and the second register written here. */
7412 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7413 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7414 as_warn (_("base register written back, and overlaps "
7415 "second destination register"));
7417 /* For an index-register load, the index register must not overlap the
7418 destination (even if not write-back). */
7419 else if (inst
.operands
[2].immisreg
7420 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7421 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7422 as_warn (_("index register overlaps destination register"));
7425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7426 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7432 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7433 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7434 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7435 || inst
.operands
[1].negative
7436 /* This can arise if the programmer has written
7438 or if they have mistakenly used a register name as the last
7441 It is very difficult to distinguish between these two cases
7442 because "rX" might actually be a label. ie the register
7443 name has been occluded by a symbol of the same name. So we
7444 just generate a general 'bad addressing mode' type error
7445 message and leave it up to the programmer to discover the
7446 true cause and fix their mistake. */
7447 || (inst
.operands
[1].reg
== REG_PC
),
7450 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7451 || inst
.reloc
.exp
.X_add_number
!= 0,
7452 _("offset must be zero in ARM encoding"));
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7456 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7462 constraint (inst
.operands
[0].reg
% 2 != 0,
7463 _("even register required"));
7464 constraint (inst
.operands
[1].present
7465 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7466 _("can only load two consecutive registers"));
7467 /* If op 1 were present and equal to PC, this function wouldn't
7468 have been called in the first place. */
7469 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7472 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7479 if (!inst
.operands
[1].isreg
)
7480 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7482 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7488 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7490 if (inst
.operands
[1].preind
)
7492 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7493 || inst
.reloc
.exp
.X_add_number
!= 0,
7494 _("this instruction requires a post-indexed address"));
7496 inst
.operands
[1].preind
= 0;
7497 inst
.operands
[1].postind
= 1;
7498 inst
.operands
[1].writeback
= 1;
7500 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7501 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7504 /* Halfword and signed-byte load/store operations. */
7509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7510 if (!inst
.operands
[1].isreg
)
7511 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7513 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7519 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7521 if (inst
.operands
[1].preind
)
7523 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7524 || inst
.reloc
.exp
.X_add_number
!= 0,
7525 _("this instruction requires a post-indexed address"));
7527 inst
.operands
[1].preind
= 0;
7528 inst
.operands
[1].postind
= 1;
7529 inst
.operands
[1].writeback
= 1;
7531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7532 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7535 /* Co-processor register load/store.
7536 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7540 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7541 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7542 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7548 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7549 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7550 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7551 && !(inst
.instruction
& 0x00400000))
7552 as_tsktsk (_("Rd and Rm should be different in mla"));
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7555 inst
.instruction
|= inst
.operands
[1].reg
;
7556 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7557 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7564 encode_arm_shifter_operand (1);
7567 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7574 top
= (inst
.instruction
& 0x00400000) != 0;
7575 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7576 _(":lower16: not allowed this instruction"));
7577 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7578 _(":upper16: not allowed instruction"));
7579 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7580 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7582 imm
= inst
.reloc
.exp
.X_add_number
;
7583 /* The value is in two pieces: 0:11, 16:19. */
7584 inst
.instruction
|= (imm
& 0x00000fff);
7585 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7589 static void do_vfp_nsyn_opcode (const char *);
7592 do_vfp_nsyn_mrs (void)
7594 if (inst
.operands
[0].isvec
)
7596 if (inst
.operands
[1].reg
!= 1)
7597 first_error (_("operand 1 must be FPSCR"));
7598 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7599 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7600 do_vfp_nsyn_opcode ("fmstat");
7602 else if (inst
.operands
[1].isvec
)
7603 do_vfp_nsyn_opcode ("fmrx");
7611 do_vfp_nsyn_msr (void)
7613 if (inst
.operands
[0].isvec
)
7614 do_vfp_nsyn_opcode ("fmxr");
7624 unsigned Rt
= inst
.operands
[0].reg
;
7626 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7628 inst
.error
= BAD_SP
;
7632 /* APSR_ sets isvec. All other refs to PC are illegal. */
7633 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7635 inst
.error
= BAD_PC
;
7639 if (inst
.operands
[1].reg
!= 1)
7640 first_error (_("operand 1 must be FPSCR"));
7642 inst
.instruction
|= (Rt
<< 12);
7648 unsigned Rt
= inst
.operands
[1].reg
;
7651 reject_bad_reg (Rt
);
7652 else if (Rt
== REG_PC
)
7654 inst
.error
= BAD_PC
;
7658 if (inst
.operands
[0].reg
!= 1)
7659 first_error (_("operand 0 must be FPSCR"));
7661 inst
.instruction
|= (Rt
<< 12);
7667 if (do_vfp_nsyn_mrs () == SUCCESS
)
7670 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7671 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7673 _("'CPSR' or 'SPSR' expected"));
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7675 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7678 /* Two possible forms:
7679 "{C|S}PSR_<field>, Rm",
7680 "{C|S}PSR_f, #expression". */
7685 if (do_vfp_nsyn_msr () == SUCCESS
)
7688 inst
.instruction
|= inst
.operands
[0].imm
;
7689 if (inst
.operands
[1].isreg
)
7690 inst
.instruction
|= inst
.operands
[1].reg
;
7693 inst
.instruction
|= INST_IMMEDIATE
;
7694 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7695 inst
.reloc
.pc_rel
= 0;
7702 if (!inst
.operands
[2].present
)
7703 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7704 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7705 inst
.instruction
|= inst
.operands
[1].reg
;
7706 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7708 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7709 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7710 as_tsktsk (_("Rd and Rm should be different in mul"));
7713 /* Long Multiply Parser
7714 UMULL RdLo, RdHi, Rm, Rs
7715 SMULL RdLo, RdHi, Rm, Rs
7716 UMLAL RdLo, RdHi, Rm, Rs
7717 SMLAL RdLo, RdHi, Rm, Rs. */
7722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7723 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7724 inst
.instruction
|= inst
.operands
[2].reg
;
7725 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7727 /* rdhi and rdlo must be different. */
7728 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7729 as_tsktsk (_("rdhi and rdlo must be different"));
7731 /* rdhi, rdlo and rm must all be different before armv6. */
7732 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7733 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7734 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7735 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7741 if (inst
.operands
[0].present
7742 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7744 /* Architectural NOP hints are CPSR sets with no bits selected. */
7745 inst
.instruction
&= 0xf0000000;
7746 inst
.instruction
|= 0x0320f000;
7747 if (inst
.operands
[0].present
)
7748 inst
.instruction
|= inst
.operands
[0].imm
;
7752 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7753 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7754 Condition defaults to COND_ALWAYS.
7755 Error if Rd, Rn or Rm are R15. */
7760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7761 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7762 inst
.instruction
|= inst
.operands
[2].reg
;
7763 if (inst
.operands
[3].present
)
7764 encode_arm_shift (3);
7767 /* ARM V6 PKHTB (Argument Parse). */
7772 if (!inst
.operands
[3].present
)
7774 /* If the shift specifier is omitted, turn the instruction
7775 into pkhbt rd, rm, rn. */
7776 inst
.instruction
&= 0xfff00010;
7777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7778 inst
.instruction
|= inst
.operands
[1].reg
;
7779 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7783 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7784 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7785 inst
.instruction
|= inst
.operands
[2].reg
;
7786 encode_arm_shift (3);
7790 /* ARMv5TE: Preload-Cache
7794 Syntactically, like LDR with B=1, W=0, L=1. */
7799 constraint (!inst
.operands
[0].isreg
,
7800 _("'[' expected after PLD mnemonic"));
7801 constraint (inst
.operands
[0].postind
,
7802 _("post-indexed expression used in preload instruction"));
7803 constraint (inst
.operands
[0].writeback
,
7804 _("writeback used in preload instruction"));
7805 constraint (!inst
.operands
[0].preind
,
7806 _("unindexed addressing used in preload instruction"));
7807 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7810 /* ARMv7: PLI <addr_mode> */
7814 constraint (!inst
.operands
[0].isreg
,
7815 _("'[' expected after PLI mnemonic"));
7816 constraint (inst
.operands
[0].postind
,
7817 _("post-indexed expression used in preload instruction"));
7818 constraint (inst
.operands
[0].writeback
,
7819 _("writeback used in preload instruction"));
7820 constraint (!inst
.operands
[0].preind
,
7821 _("unindexed addressing used in preload instruction"));
7822 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7823 inst
.instruction
&= ~PRE_INDEX
;
7829 inst
.operands
[1] = inst
.operands
[0];
7830 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7831 inst
.operands
[0].isreg
= 1;
7832 inst
.operands
[0].writeback
= 1;
7833 inst
.operands
[0].reg
= REG_SP
;
7837 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7838 word at the specified address and the following word
7840 Unconditionally executed.
7841 Error if Rn is R15. */
7846 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7847 if (inst
.operands
[0].writeback
)
7848 inst
.instruction
|= WRITE_BACK
;
7851 /* ARM V6 ssat (argument parse). */
7856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7857 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7858 inst
.instruction
|= inst
.operands
[2].reg
;
7860 if (inst
.operands
[3].present
)
7861 encode_arm_shift (3);
7864 /* ARM V6 usat (argument parse). */
7869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7870 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7871 inst
.instruction
|= inst
.operands
[2].reg
;
7873 if (inst
.operands
[3].present
)
7874 encode_arm_shift (3);
7877 /* ARM V6 ssat16 (argument parse). */
7882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7883 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7884 inst
.instruction
|= inst
.operands
[2].reg
;
7890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7891 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7892 inst
.instruction
|= inst
.operands
[2].reg
;
7895 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7896 preserving the other bits.
7898 setend <endian_specifier>, where <endian_specifier> is either
7904 if (inst
.operands
[0].imm
)
7905 inst
.instruction
|= 0x200;
7911 unsigned int Rm
= (inst
.operands
[1].present
7912 ? inst
.operands
[1].reg
7913 : inst
.operands
[0].reg
);
7915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7916 inst
.instruction
|= Rm
;
7917 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7919 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7920 inst
.instruction
|= SHIFT_BY_REG
;
7923 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7929 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7930 inst
.reloc
.pc_rel
= 0;
7936 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7937 inst
.reloc
.pc_rel
= 0;
7940 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7941 SMLAxy{cond} Rd,Rm,Rs,Rn
7942 SMLAWy{cond} Rd,Rm,Rs,Rn
7943 Error if any register is R15. */
7948 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7949 inst
.instruction
|= inst
.operands
[1].reg
;
7950 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7951 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7954 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7955 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7956 Error if any register is R15.
7957 Warning if Rdlo == Rdhi. */
7962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7963 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7964 inst
.instruction
|= inst
.operands
[2].reg
;
7965 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7967 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7968 as_tsktsk (_("rdhi and rdlo must be different"));
7971 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7972 SMULxy{cond} Rd,Rm,Rs
7973 Error if any register is R15. */
7978 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7979 inst
.instruction
|= inst
.operands
[1].reg
;
7980 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7983 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7984 the same for both ARM and Thumb-2. */
7991 if (inst
.operands
[0].present
)
7993 reg
= inst
.operands
[0].reg
;
7994 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7999 inst
.instruction
|= reg
<< 16;
8000 inst
.instruction
|= inst
.operands
[1].imm
;
8001 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8002 inst
.instruction
|= WRITE_BACK
;
8005 /* ARM V6 strex (argument parse). */
8010 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8011 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8012 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8013 || inst
.operands
[2].negative
8014 /* See comment in do_ldrex(). */
8015 || (inst
.operands
[2].reg
== REG_PC
),
8018 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8019 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8021 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8022 || inst
.reloc
.exp
.X_add_number
!= 0,
8023 _("offset must be zero in ARM encoding"));
8025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8026 inst
.instruction
|= inst
.operands
[1].reg
;
8027 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8028 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8034 constraint (inst
.operands
[1].reg
% 2 != 0,
8035 _("even register required"));
8036 constraint (inst
.operands
[2].present
8037 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8038 _("can only store two consecutive registers"));
8039 /* If op 2 were present and equal to PC, this function wouldn't
8040 have been called in the first place. */
8041 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8043 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8044 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8045 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8049 inst
.instruction
|= inst
.operands
[1].reg
;
8050 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8053 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8054 extends it to 32-bits, and adds the result to a value in another
8055 register. You can specify a rotation by 0, 8, 16, or 24 bits
8056 before extracting the 16-bit value.
8057 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8058 Condition defaults to COND_ALWAYS.
8059 Error if any register uses R15. */
8064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8065 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8066 inst
.instruction
|= inst
.operands
[2].reg
;
8067 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8072 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8073 Condition defaults to COND_ALWAYS.
8074 Error if any register uses R15. */
8079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8080 inst
.instruction
|= inst
.operands
[1].reg
;
8081 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8084 /* VFP instructions. In a logical order: SP variant first, monad
8085 before dyad, arithmetic then move then load/store. */
8088 do_vfp_sp_monadic (void)
8090 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8091 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8095 do_vfp_sp_dyadic (void)
8097 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8098 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8099 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8103 do_vfp_sp_compare_z (void)
8105 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8109 do_vfp_dp_sp_cvt (void)
8111 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8112 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8116 do_vfp_sp_dp_cvt (void)
8118 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8119 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8123 do_vfp_reg_from_sp (void)
8125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8126 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8130 do_vfp_reg2_from_sp2 (void)
8132 constraint (inst
.operands
[2].imm
!= 2,
8133 _("only two consecutive VFP SP registers allowed here"));
8134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8135 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8136 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8140 do_vfp_sp_from_reg (void)
8142 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8143 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8147 do_vfp_sp2_from_reg2 (void)
8149 constraint (inst
.operands
[0].imm
!= 2,
8150 _("only two consecutive VFP SP registers allowed here"));
8151 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8152 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8153 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8157 do_vfp_sp_ldst (void)
8159 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8160 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8164 do_vfp_dp_ldst (void)
8166 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8167 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8172 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8174 if (inst
.operands
[0].writeback
)
8175 inst
.instruction
|= WRITE_BACK
;
8177 constraint (ldstm_type
!= VFP_LDSTMIA
,
8178 _("this addressing mode requires base-register writeback"));
8179 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8180 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8181 inst
.instruction
|= inst
.operands
[1].imm
;
8185 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8189 if (inst
.operands
[0].writeback
)
8190 inst
.instruction
|= WRITE_BACK
;
8192 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8193 _("this addressing mode requires base-register writeback"));
8195 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8196 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8198 count
= inst
.operands
[1].imm
<< 1;
8199 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8202 inst
.instruction
|= count
;
8206 do_vfp_sp_ldstmia (void)
8208 vfp_sp_ldstm (VFP_LDSTMIA
);
8212 do_vfp_sp_ldstmdb (void)
8214 vfp_sp_ldstm (VFP_LDSTMDB
);
8218 do_vfp_dp_ldstmia (void)
8220 vfp_dp_ldstm (VFP_LDSTMIA
);
8224 do_vfp_dp_ldstmdb (void)
8226 vfp_dp_ldstm (VFP_LDSTMDB
);
8230 do_vfp_xp_ldstmia (void)
8232 vfp_dp_ldstm (VFP_LDSTMIAX
);
8236 do_vfp_xp_ldstmdb (void)
8238 vfp_dp_ldstm (VFP_LDSTMDBX
);
8242 do_vfp_dp_rd_rm (void)
8244 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8245 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8249 do_vfp_dp_rn_rd (void)
8251 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8252 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8256 do_vfp_dp_rd_rn (void)
8258 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8259 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8263 do_vfp_dp_rd_rn_rm (void)
8265 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8266 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8267 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8273 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8277 do_vfp_dp_rm_rd_rn (void)
8279 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8280 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8281 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8284 /* VFPv3 instructions. */
8286 do_vfp_sp_const (void)
8288 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8289 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8290 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8294 do_vfp_dp_const (void)
8296 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8297 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8298 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8302 vfp_conv (int srcsize
)
8304 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8305 inst
.instruction
|= (immbits
& 1) << 5;
8306 inst
.instruction
|= (immbits
>> 1);
8310 do_vfp_sp_conv_16 (void)
8312 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8317 do_vfp_dp_conv_16 (void)
8319 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8324 do_vfp_sp_conv_32 (void)
8326 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8331 do_vfp_dp_conv_32 (void)
8333 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8337 /* FPA instructions. Also in a logical order. */
8342 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8343 inst
.instruction
|= inst
.operands
[1].reg
;
8347 do_fpa_ldmstm (void)
8349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8350 switch (inst
.operands
[1].imm
)
8352 case 1: inst
.instruction
|= CP_T_X
; break;
8353 case 2: inst
.instruction
|= CP_T_Y
; break;
8354 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8359 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8361 /* The instruction specified "ea" or "fd", so we can only accept
8362 [Rn]{!}. The instruction does not really support stacking or
8363 unstacking, so we have to emulate these by setting appropriate
8364 bits and offsets. */
8365 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8366 || inst
.reloc
.exp
.X_add_number
!= 0,
8367 _("this instruction does not support indexing"));
8369 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8370 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8372 if (!(inst
.instruction
& INDEX_UP
))
8373 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8375 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8377 inst
.operands
[2].preind
= 0;
8378 inst
.operands
[2].postind
= 1;
8382 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8385 /* iWMMXt instructions: strictly in alphabetical order. */
8388 do_iwmmxt_tandorc (void)
8390 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8394 do_iwmmxt_textrc (void)
8396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8397 inst
.instruction
|= inst
.operands
[1].imm
;
8401 do_iwmmxt_textrm (void)
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8404 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8405 inst
.instruction
|= inst
.operands
[2].imm
;
8409 do_iwmmxt_tinsr (void)
8411 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8412 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8413 inst
.instruction
|= inst
.operands
[2].imm
;
8417 do_iwmmxt_tmia (void)
8419 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8420 inst
.instruction
|= inst
.operands
[1].reg
;
8421 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8425 do_iwmmxt_waligni (void)
8427 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8428 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8429 inst
.instruction
|= inst
.operands
[2].reg
;
8430 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8434 do_iwmmxt_wmerge (void)
8436 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8437 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8438 inst
.instruction
|= inst
.operands
[2].reg
;
8439 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8443 do_iwmmxt_wmov (void)
8445 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8447 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8448 inst
.instruction
|= inst
.operands
[1].reg
;
8452 do_iwmmxt_wldstbh (void)
8455 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8457 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8459 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8460 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8464 do_iwmmxt_wldstw (void)
8466 /* RIWR_RIWC clears .isreg for a control register. */
8467 if (!inst
.operands
[0].isreg
)
8469 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8470 inst
.instruction
|= 0xf0000000;
8473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8474 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8478 do_iwmmxt_wldstd (void)
8480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8481 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8482 && inst
.operands
[1].immisreg
)
8484 inst
.instruction
&= ~0x1a000ff;
8485 inst
.instruction
|= (0xf << 28);
8486 if (inst
.operands
[1].preind
)
8487 inst
.instruction
|= PRE_INDEX
;
8488 if (!inst
.operands
[1].negative
)
8489 inst
.instruction
|= INDEX_UP
;
8490 if (inst
.operands
[1].writeback
)
8491 inst
.instruction
|= WRITE_BACK
;
8492 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8493 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8494 inst
.instruction
|= inst
.operands
[1].imm
;
8497 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8501 do_iwmmxt_wshufh (void)
8503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8504 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8505 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8506 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8510 do_iwmmxt_wzero (void)
8512 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8513 inst
.instruction
|= inst
.operands
[0].reg
;
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8519 do_iwmmxt_wrwrwr_or_imm5 (void)
8521 if (inst
.operands
[2].isreg
)
8524 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8525 _("immediate operand requires iWMMXt2"));
8527 if (inst
.operands
[2].imm
== 0)
8529 switch ((inst
.instruction
>> 20) & 0xf)
8535 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8536 inst
.operands
[2].imm
= 16;
8537 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8543 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8544 inst
.operands
[2].imm
= 32;
8545 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8552 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8554 wrn
= (inst
.instruction
>> 16) & 0xf;
8555 inst
.instruction
&= 0xff0fff0f;
8556 inst
.instruction
|= wrn
;
8557 /* Bail out here; the instruction is now assembled. */
8562 /* Map 32 -> 0, etc. */
8563 inst
.operands
[2].imm
&= 0x1f;
8564 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8568 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8569 operations first, then control, shift, and load/store. */
8571 /* Insns like "foo X,Y,Z". */
8574 do_mav_triple (void)
8576 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[1].reg
;
8578 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8581 /* Insns like "foo W,X,Y,Z".
8582 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8587 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8588 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8589 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8590 inst
.instruction
|= inst
.operands
[3].reg
;
8593 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8597 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8600 /* Maverick shift immediate instructions.
8601 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8602 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8607 int imm
= inst
.operands
[2].imm
;
8609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8610 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8612 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8613 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8614 Bit 4 should be 0. */
8615 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8617 inst
.instruction
|= imm
;
8620 /* XScale instructions. Also sorted arithmetic before move. */
8622 /* Xscale multiply-accumulate (argument parse)
8625 MIAxycc acc0,Rm,Rs. */
8630 inst
.instruction
|= inst
.operands
[1].reg
;
8631 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8634 /* Xscale move-accumulator-register (argument parse)
8636 MARcc acc0,RdLo,RdHi. */
8641 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8642 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8645 /* Xscale move-register-accumulator (argument parse)
8647 MRAcc RdLo,RdHi,acc0. */
8652 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8657 /* Encoding functions relevant only to Thumb. */
8659 /* inst.operands[i] is a shifted-register operand; encode
8660 it into inst.instruction in the format used by Thumb32. */
8663 encode_thumb32_shifted_operand (int i
)
8665 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8666 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8668 constraint (inst
.operands
[i
].immisreg
,
8669 _("shift by register not allowed in thumb mode"));
8670 inst
.instruction
|= inst
.operands
[i
].reg
;
8671 if (shift
== SHIFT_RRX
)
8672 inst
.instruction
|= SHIFT_ROR
<< 4;
8675 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8676 _("expression too complex"));
8678 constraint (value
> 32
8679 || (value
== 32 && (shift
== SHIFT_LSL
8680 || shift
== SHIFT_ROR
)),
8681 _("shift expression is too large"));
8685 else if (value
== 32)
8688 inst
.instruction
|= shift
<< 4;
8689 inst
.instruction
|= (value
& 0x1c) << 10;
8690 inst
.instruction
|= (value
& 0x03) << 6;
8695 /* inst.operands[i] was set up by parse_address. Encode it into a
8696 Thumb32 format load or store instruction. Reject forms that cannot
8697 be used with such instructions. If is_t is true, reject forms that
8698 cannot be used with a T instruction; if is_d is true, reject forms
8699 that cannot be used with a D instruction. */
8702 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8704 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8706 constraint (!inst
.operands
[i
].isreg
,
8707 _("Instruction does not support =N addresses"));
8709 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8710 if (inst
.operands
[i
].immisreg
)
8712 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8713 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8714 constraint (inst
.operands
[i
].negative
,
8715 _("Thumb does not support negative register indexing"));
8716 constraint (inst
.operands
[i
].postind
,
8717 _("Thumb does not support register post-indexing"));
8718 constraint (inst
.operands
[i
].writeback
,
8719 _("Thumb does not support register indexing with writeback"));
8720 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8721 _("Thumb supports only LSL in shifted register indexing"));
8723 inst
.instruction
|= inst
.operands
[i
].imm
;
8724 if (inst
.operands
[i
].shifted
)
8726 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8727 _("expression too complex"));
8728 constraint (inst
.reloc
.exp
.X_add_number
< 0
8729 || inst
.reloc
.exp
.X_add_number
> 3,
8730 _("shift out of range"));
8731 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8733 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8735 else if (inst
.operands
[i
].preind
)
8737 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8738 _("cannot use writeback with PC-relative addressing"));
8739 constraint (is_t
&& inst
.operands
[i
].writeback
,
8740 _("cannot use writeback with this instruction"));
8744 inst
.instruction
|= 0x01000000;
8745 if (inst
.operands
[i
].writeback
)
8746 inst
.instruction
|= 0x00200000;
8750 inst
.instruction
|= 0x00000c00;
8751 if (inst
.operands
[i
].writeback
)
8752 inst
.instruction
|= 0x00000100;
8754 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8756 else if (inst
.operands
[i
].postind
)
8758 gas_assert (inst
.operands
[i
].writeback
);
8759 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8760 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8763 inst
.instruction
|= 0x00200000;
8765 inst
.instruction
|= 0x00000900;
8766 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8768 else /* unindexed - only for coprocessor */
8769 inst
.error
= _("instruction does not accept unindexed addressing");
8772 /* Table of Thumb instructions which exist in both 16- and 32-bit
8773 encodings (the latter only in post-V6T2 cores). The index is the
8774 value used in the insns table below. When there is more than one
8775 possible 16-bit encoding for the instruction, this table always
8777 Also contains several pseudo-instructions used during relaxation. */
8778 #define T16_32_TAB \
8779 X(_adc, 4140, eb400000), \
8780 X(_adcs, 4140, eb500000), \
8781 X(_add, 1c00, eb000000), \
8782 X(_adds, 1c00, eb100000), \
8783 X(_addi, 0000, f1000000), \
8784 X(_addis, 0000, f1100000), \
8785 X(_add_pc,000f, f20f0000), \
8786 X(_add_sp,000d, f10d0000), \
8787 X(_adr, 000f, f20f0000), \
8788 X(_and, 4000, ea000000), \
8789 X(_ands, 4000, ea100000), \
8790 X(_asr, 1000, fa40f000), \
8791 X(_asrs, 1000, fa50f000), \
8792 X(_b, e000, f000b000), \
8793 X(_bcond, d000, f0008000), \
8794 X(_bic, 4380, ea200000), \
8795 X(_bics, 4380, ea300000), \
8796 X(_cmn, 42c0, eb100f00), \
8797 X(_cmp, 2800, ebb00f00), \
8798 X(_cpsie, b660, f3af8400), \
8799 X(_cpsid, b670, f3af8600), \
8800 X(_cpy, 4600, ea4f0000), \
8801 X(_dec_sp,80dd, f1ad0d00), \
8802 X(_eor, 4040, ea800000), \
8803 X(_eors, 4040, ea900000), \
8804 X(_inc_sp,00dd, f10d0d00), \
8805 X(_ldmia, c800, e8900000), \
8806 X(_ldr, 6800, f8500000), \
8807 X(_ldrb, 7800, f8100000), \
8808 X(_ldrh, 8800, f8300000), \
8809 X(_ldrsb, 5600, f9100000), \
8810 X(_ldrsh, 5e00, f9300000), \
8811 X(_ldr_pc,4800, f85f0000), \
8812 X(_ldr_pc2,4800, f85f0000), \
8813 X(_ldr_sp,9800, f85d0000), \
8814 X(_lsl, 0000, fa00f000), \
8815 X(_lsls, 0000, fa10f000), \
8816 X(_lsr, 0800, fa20f000), \
8817 X(_lsrs, 0800, fa30f000), \
8818 X(_mov, 2000, ea4f0000), \
8819 X(_movs, 2000, ea5f0000), \
8820 X(_mul, 4340, fb00f000), \
8821 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8822 X(_mvn, 43c0, ea6f0000), \
8823 X(_mvns, 43c0, ea7f0000), \
8824 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8825 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8826 X(_orr, 4300, ea400000), \
8827 X(_orrs, 4300, ea500000), \
8828 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8829 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8830 X(_rev, ba00, fa90f080), \
8831 X(_rev16, ba40, fa90f090), \
8832 X(_revsh, bac0, fa90f0b0), \
8833 X(_ror, 41c0, fa60f000), \
8834 X(_rors, 41c0, fa70f000), \
8835 X(_sbc, 4180, eb600000), \
8836 X(_sbcs, 4180, eb700000), \
8837 X(_stmia, c000, e8800000), \
8838 X(_str, 6000, f8400000), \
8839 X(_strb, 7000, f8000000), \
8840 X(_strh, 8000, f8200000), \
8841 X(_str_sp,9000, f84d0000), \
8842 X(_sub, 1e00, eba00000), \
8843 X(_subs, 1e00, ebb00000), \
8844 X(_subi, 8000, f1a00000), \
8845 X(_subis, 8000, f1b00000), \
8846 X(_sxtb, b240, fa4ff080), \
8847 X(_sxth, b200, fa0ff080), \
8848 X(_tst, 4200, ea100f00), \
8849 X(_uxtb, b2c0, fa5ff080), \
8850 X(_uxth, b280, fa1ff080), \
8851 X(_nop, bf00, f3af8000), \
8852 X(_yield, bf10, f3af8001), \
8853 X(_wfe, bf20, f3af8002), \
8854 X(_wfi, bf30, f3af8003), \
8855 X(_sev, bf40, f3af8004),
8857 /* To catch errors in encoding functions, the codes are all offset by
8858 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8859 as 16-bit instructions. */
8860 #define X(a,b,c) T_MNEM##a
8861 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8864 #define X(a,b,c) 0x##b
8865 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8866 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8869 #define X(a,b,c) 0x##c
8870 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8871 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8872 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8876 /* Thumb instruction encoders, in alphabetical order. */
8881 do_t_add_sub_w (void)
8885 Rd
= inst
.operands
[0].reg
;
8886 Rn
= inst
.operands
[1].reg
;
8888 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8889 is the SP-{plus,minus}-immediate form of the instruction. */
8891 constraint (Rd
== REG_PC
, BAD_PC
);
8893 reject_bad_reg (Rd
);
8895 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8896 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8899 /* Parse an add or subtract instruction. We get here with inst.instruction
8900 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8907 Rd
= inst
.operands
[0].reg
;
8908 Rs
= (inst
.operands
[1].present
8909 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8910 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8913 set_it_insn_type_last ();
8921 flags
= (inst
.instruction
== T_MNEM_adds
8922 || inst
.instruction
== T_MNEM_subs
);
8924 narrow
= !in_it_block ();
8926 narrow
= in_it_block ();
8927 if (!inst
.operands
[2].isreg
)
8931 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8933 add
= (inst
.instruction
== T_MNEM_add
8934 || inst
.instruction
== T_MNEM_adds
);
8936 if (inst
.size_req
!= 4)
8938 /* Attempt to use a narrow opcode, with relaxation if
8940 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8941 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8942 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8943 opcode
= T_MNEM_add_sp
;
8944 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8945 opcode
= T_MNEM_add_pc
;
8946 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8949 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8951 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8955 inst
.instruction
= THUMB_OP16(opcode
);
8956 inst
.instruction
|= (Rd
<< 4) | Rs
;
8957 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8958 if (inst
.size_req
!= 2)
8959 inst
.relax
= opcode
;
8962 constraint (inst
.size_req
== 2, BAD_HIREG
);
8964 if (inst
.size_req
== 4
8965 || (inst
.size_req
!= 2 && !opcode
))
8969 constraint (add
, BAD_PC
);
8970 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8971 _("only SUBS PC, LR, #const allowed"));
8972 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8973 _("expression too complex"));
8974 constraint (inst
.reloc
.exp
.X_add_number
< 0
8975 || inst
.reloc
.exp
.X_add_number
> 0xff,
8976 _("immediate value out of range"));
8977 inst
.instruction
= T2_SUBS_PC_LR
8978 | inst
.reloc
.exp
.X_add_number
;
8979 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8982 else if (Rs
== REG_PC
)
8984 /* Always use addw/subw. */
8985 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8986 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8990 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8991 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8994 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8996 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8998 inst
.instruction
|= Rd
<< 8;
8999 inst
.instruction
|= Rs
<< 16;
9004 Rn
= inst
.operands
[2].reg
;
9005 /* See if we can do this with a 16-bit instruction. */
9006 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9008 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9013 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9014 || inst
.instruction
== T_MNEM_add
)
9017 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9021 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9023 /* Thumb-1 cores (except v6-M) require at least one high
9024 register in a narrow non flag setting add. */
9025 if (Rd
> 7 || Rn
> 7
9026 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9027 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9034 inst
.instruction
= T_OPCODE_ADD_HI
;
9035 inst
.instruction
|= (Rd
& 8) << 4;
9036 inst
.instruction
|= (Rd
& 7);
9037 inst
.instruction
|= Rn
<< 3;
9043 constraint (Rd
== REG_PC
, BAD_PC
);
9044 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9045 constraint (Rs
== REG_PC
, BAD_PC
);
9046 reject_bad_reg (Rn
);
9048 /* If we get here, it can't be done in 16 bits. */
9049 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9050 _("shift must be constant"));
9051 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9052 inst
.instruction
|= Rd
<< 8;
9053 inst
.instruction
|= Rs
<< 16;
9054 encode_thumb32_shifted_operand (2);
9059 constraint (inst
.instruction
== T_MNEM_adds
9060 || inst
.instruction
== T_MNEM_subs
,
9063 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9065 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9066 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9069 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9071 inst
.instruction
|= (Rd
<< 4) | Rs
;
9072 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9076 Rn
= inst
.operands
[2].reg
;
9077 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9079 /* We now have Rd, Rs, and Rn set to registers. */
9080 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9082 /* Can't do this for SUB. */
9083 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9084 inst
.instruction
= T_OPCODE_ADD_HI
;
9085 inst
.instruction
|= (Rd
& 8) << 4;
9086 inst
.instruction
|= (Rd
& 7);
9088 inst
.instruction
|= Rn
<< 3;
9090 inst
.instruction
|= Rs
<< 3;
9092 constraint (1, _("dest must overlap one source register"));
9096 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9097 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9098 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9108 Rd
= inst
.operands
[0].reg
;
9109 reject_bad_reg (Rd
);
9111 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9113 /* Defer to section relaxation. */
9114 inst
.relax
= inst
.instruction
;
9115 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9116 inst
.instruction
|= Rd
<< 4;
9118 else if (unified_syntax
&& inst
.size_req
!= 2)
9120 /* Generate a 32-bit opcode. */
9121 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9122 inst
.instruction
|= Rd
<< 8;
9123 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9124 inst
.reloc
.pc_rel
= 1;
9128 /* Generate a 16-bit opcode. */
9129 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9130 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9131 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9132 inst
.reloc
.pc_rel
= 1;
9134 inst
.instruction
|= Rd
<< 4;
9138 /* Arithmetic instructions for which there is just one 16-bit
9139 instruction encoding, and it allows only two low registers.
9140 For maximal compatibility with ARM syntax, we allow three register
9141 operands even when Thumb-32 instructions are not available, as long
9142 as the first two are identical. For instance, both "sbc r0,r1" and
9143 "sbc r0,r0,r1" are allowed. */
9149 Rd
= inst
.operands
[0].reg
;
9150 Rs
= (inst
.operands
[1].present
9151 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9152 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9153 Rn
= inst
.operands
[2].reg
;
9155 reject_bad_reg (Rd
);
9156 reject_bad_reg (Rs
);
9157 if (inst
.operands
[2].isreg
)
9158 reject_bad_reg (Rn
);
9162 if (!inst
.operands
[2].isreg
)
9164 /* For an immediate, we always generate a 32-bit opcode;
9165 section relaxation will shrink it later if possible. */
9166 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9167 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9168 inst
.instruction
|= Rd
<< 8;
9169 inst
.instruction
|= Rs
<< 16;
9170 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9176 /* See if we can do this with a 16-bit instruction. */
9177 if (THUMB_SETS_FLAGS (inst
.instruction
))
9178 narrow
= !in_it_block ();
9180 narrow
= in_it_block ();
9182 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9184 if (inst
.operands
[2].shifted
)
9186 if (inst
.size_req
== 4)
9192 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9193 inst
.instruction
|= Rd
;
9194 inst
.instruction
|= Rn
<< 3;
9198 /* If we get here, it can't be done in 16 bits. */
9199 constraint (inst
.operands
[2].shifted
9200 && inst
.operands
[2].immisreg
,
9201 _("shift must be constant"));
9202 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9203 inst
.instruction
|= Rd
<< 8;
9204 inst
.instruction
|= Rs
<< 16;
9205 encode_thumb32_shifted_operand (2);
9210 /* On its face this is a lie - the instruction does set the
9211 flags. However, the only supported mnemonic in this mode
9213 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9215 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9216 _("unshifted register required"));
9217 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9218 constraint (Rd
!= Rs
,
9219 _("dest and source1 must be the same register"));
9221 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9222 inst
.instruction
|= Rd
;
9223 inst
.instruction
|= Rn
<< 3;
9227 /* Similarly, but for instructions where the arithmetic operation is
9228 commutative, so we can allow either of them to be different from
9229 the destination operand in a 16-bit instruction. For instance, all
9230 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9237 Rd
= inst
.operands
[0].reg
;
9238 Rs
= (inst
.operands
[1].present
9239 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9240 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9241 Rn
= inst
.operands
[2].reg
;
9243 reject_bad_reg (Rd
);
9244 reject_bad_reg (Rs
);
9245 if (inst
.operands
[2].isreg
)
9246 reject_bad_reg (Rn
);
9250 if (!inst
.operands
[2].isreg
)
9252 /* For an immediate, we always generate a 32-bit opcode;
9253 section relaxation will shrink it later if possible. */
9254 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9255 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9256 inst
.instruction
|= Rd
<< 8;
9257 inst
.instruction
|= Rs
<< 16;
9258 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9264 /* See if we can do this with a 16-bit instruction. */
9265 if (THUMB_SETS_FLAGS (inst
.instruction
))
9266 narrow
= !in_it_block ();
9268 narrow
= in_it_block ();
9270 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9272 if (inst
.operands
[2].shifted
)
9274 if (inst
.size_req
== 4)
9281 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9282 inst
.instruction
|= Rd
;
9283 inst
.instruction
|= Rn
<< 3;
9288 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9289 inst
.instruction
|= Rd
;
9290 inst
.instruction
|= Rs
<< 3;
9295 /* If we get here, it can't be done in 16 bits. */
9296 constraint (inst
.operands
[2].shifted
9297 && inst
.operands
[2].immisreg
,
9298 _("shift must be constant"));
9299 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9300 inst
.instruction
|= Rd
<< 8;
9301 inst
.instruction
|= Rs
<< 16;
9302 encode_thumb32_shifted_operand (2);
9307 /* On its face this is a lie - the instruction does set the
9308 flags. However, the only supported mnemonic in this mode
9310 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9312 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9313 _("unshifted register required"));
9314 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9316 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9317 inst
.instruction
|= Rd
;
9320 inst
.instruction
|= Rn
<< 3;
9322 inst
.instruction
|= Rs
<< 3;
9324 constraint (1, _("dest must overlap one source register"));
9331 if (inst
.operands
[0].present
)
9333 constraint ((inst
.instruction
& 0xf0) != 0x40
9334 && inst
.operands
[0].imm
!= 0xf,
9335 _("bad barrier type"));
9336 inst
.instruction
|= inst
.operands
[0].imm
;
9339 inst
.instruction
|= 0xf;
9346 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9347 constraint (msb
> 32, _("bit-field extends past end of register"));
9348 /* The instruction encoding stores the LSB and MSB,
9349 not the LSB and width. */
9350 Rd
= inst
.operands
[0].reg
;
9351 reject_bad_reg (Rd
);
9352 inst
.instruction
|= Rd
<< 8;
9353 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9354 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9355 inst
.instruction
|= msb
- 1;
9364 Rd
= inst
.operands
[0].reg
;
9365 reject_bad_reg (Rd
);
9367 /* #0 in second position is alternative syntax for bfc, which is
9368 the same instruction but with REG_PC in the Rm field. */
9369 if (!inst
.operands
[1].isreg
)
9373 Rn
= inst
.operands
[1].reg
;
9374 reject_bad_reg (Rn
);
9377 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9378 constraint (msb
> 32, _("bit-field extends past end of register"));
9379 /* The instruction encoding stores the LSB and MSB,
9380 not the LSB and width. */
9381 inst
.instruction
|= Rd
<< 8;
9382 inst
.instruction
|= Rn
<< 16;
9383 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9384 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9385 inst
.instruction
|= msb
- 1;
9393 Rd
= inst
.operands
[0].reg
;
9394 Rn
= inst
.operands
[1].reg
;
9396 reject_bad_reg (Rd
);
9397 reject_bad_reg (Rn
);
9399 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9400 _("bit-field extends past end of register"));
9401 inst
.instruction
|= Rd
<< 8;
9402 inst
.instruction
|= Rn
<< 16;
9403 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9404 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9405 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9408 /* ARM V5 Thumb BLX (argument parse)
9409 BLX <target_addr> which is BLX(1)
9410 BLX <Rm> which is BLX(2)
9411 Unfortunately, there are two different opcodes for this mnemonic.
9412 So, the insns[].value is not used, and the code here zaps values
9413 into inst.instruction.
9415 ??? How to take advantage of the additional two bits of displacement
9416 available in Thumb32 mode? Need new relocation? */
9421 set_it_insn_type_last ();
9423 if (inst
.operands
[0].isreg
)
9425 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9426 /* We have a register, so this is BLX(2). */
9427 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9431 /* No register. This must be BLX(1). */
9432 inst
.instruction
= 0xf000e800;
9433 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9434 inst
.reloc
.pc_rel
= 1;
9445 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9449 /* Conditional branches inside IT blocks are encoded as unconditional
9456 if (cond
!= COND_ALWAYS
)
9457 opcode
= T_MNEM_bcond
;
9459 opcode
= inst
.instruction
;
9461 if (unified_syntax
&& inst
.size_req
== 4)
9463 inst
.instruction
= THUMB_OP32(opcode
);
9464 if (cond
== COND_ALWAYS
)
9465 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9468 gas_assert (cond
!= 0xF);
9469 inst
.instruction
|= cond
<< 22;
9470 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9475 inst
.instruction
= THUMB_OP16(opcode
);
9476 if (cond
== COND_ALWAYS
)
9477 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9480 inst
.instruction
|= cond
<< 8;
9481 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9483 /* Allow section relaxation. */
9484 if (unified_syntax
&& inst
.size_req
!= 2)
9485 inst
.relax
= opcode
;
9488 inst
.reloc
.pc_rel
= 1;
9494 constraint (inst
.cond
!= COND_ALWAYS
,
9495 _("instruction is always unconditional"));
9496 if (inst
.operands
[0].present
)
9498 constraint (inst
.operands
[0].imm
> 255,
9499 _("immediate value out of range"));
9500 inst
.instruction
|= inst
.operands
[0].imm
;
9501 set_it_insn_type (NEUTRAL_IT_INSN
);
9506 do_t_branch23 (void)
9508 set_it_insn_type_last ();
9509 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9510 inst
.reloc
.pc_rel
= 1;
9512 #if defined(OBJ_COFF)
9513 /* If the destination of the branch is a defined symbol which does not have
9514 the THUMB_FUNC attribute, then we must be calling a function which has
9515 the (interfacearm) attribute. We look for the Thumb entry point to that
9516 function and change the branch to refer to that function instead. */
9517 if ( inst
.reloc
.exp
.X_op
== O_symbol
9518 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9519 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9520 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9521 inst
.reloc
.exp
.X_add_symbol
=
9522 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9529 set_it_insn_type_last ();
9530 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9531 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9532 should cause the alignment to be checked once it is known. This is
9533 because BX PC only works if the instruction is word aligned. */
9541 set_it_insn_type_last ();
9542 Rm
= inst
.operands
[0].reg
;
9543 reject_bad_reg (Rm
);
9544 inst
.instruction
|= Rm
<< 16;
9553 Rd
= inst
.operands
[0].reg
;
9554 Rm
= inst
.operands
[1].reg
;
9556 reject_bad_reg (Rd
);
9557 reject_bad_reg (Rm
);
9559 inst
.instruction
|= Rd
<< 8;
9560 inst
.instruction
|= Rm
<< 16;
9561 inst
.instruction
|= Rm
;
9567 set_it_insn_type (OUTSIDE_IT_INSN
);
9568 inst
.instruction
|= inst
.operands
[0].imm
;
9574 set_it_insn_type (OUTSIDE_IT_INSN
);
9576 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9577 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9579 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9580 inst
.instruction
= 0xf3af8000;
9581 inst
.instruction
|= imod
<< 9;
9582 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9583 if (inst
.operands
[1].present
)
9584 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9588 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9589 && (inst
.operands
[0].imm
& 4),
9590 _("selected processor does not support 'A' form "
9591 "of this instruction"));
9592 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9593 _("Thumb does not support the 2-argument "
9594 "form of this instruction"));
9595 inst
.instruction
|= inst
.operands
[0].imm
;
9599 /* THUMB CPY instruction (argument parse). */
9604 if (inst
.size_req
== 4)
9606 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9607 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9608 inst
.instruction
|= inst
.operands
[1].reg
;
9612 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9613 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9614 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9621 set_it_insn_type (OUTSIDE_IT_INSN
);
9622 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9623 inst
.instruction
|= inst
.operands
[0].reg
;
9624 inst
.reloc
.pc_rel
= 1;
9625 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9631 inst
.instruction
|= inst
.operands
[0].imm
;
9637 unsigned Rd
, Rn
, Rm
;
9639 Rd
= inst
.operands
[0].reg
;
9640 Rn
= (inst
.operands
[1].present
9641 ? inst
.operands
[1].reg
: Rd
);
9642 Rm
= inst
.operands
[2].reg
;
9644 reject_bad_reg (Rd
);
9645 reject_bad_reg (Rn
);
9646 reject_bad_reg (Rm
);
9648 inst
.instruction
|= Rd
<< 8;
9649 inst
.instruction
|= Rn
<< 16;
9650 inst
.instruction
|= Rm
;
9656 if (unified_syntax
&& inst
.size_req
== 4)
9657 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9659 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9665 unsigned int cond
= inst
.operands
[0].imm
;
9667 set_it_insn_type (IT_INSN
);
9668 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9671 /* If the condition is a negative condition, invert the mask. */
9672 if ((cond
& 0x1) == 0x0)
9674 unsigned int mask
= inst
.instruction
& 0x000f;
9676 if ((mask
& 0x7) == 0)
9677 /* no conversion needed */;
9678 else if ((mask
& 0x3) == 0)
9680 else if ((mask
& 0x1) == 0)
9685 inst
.instruction
&= 0xfff0;
9686 inst
.instruction
|= mask
;
9689 inst
.instruction
|= cond
<< 4;
9692 /* Helper function used for both push/pop and ldm/stm. */
9694 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9698 load
= (inst
.instruction
& (1 << 20)) != 0;
9700 if (mask
& (1 << 13))
9701 inst
.error
= _("SP not allowed in register list");
9704 if (mask
& (1 << 15))
9706 if (mask
& (1 << 14))
9707 inst
.error
= _("LR and PC should not both be in register list");
9709 set_it_insn_type_last ();
9712 if ((mask
& (1 << base
)) != 0
9714 as_warn (_("base register should not be in register list "
9715 "when written back"));
9719 if (mask
& (1 << 15))
9720 inst
.error
= _("PC not allowed in register list");
9722 if (mask
& (1 << base
))
9723 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9726 if ((mask
& (mask
- 1)) == 0)
9728 /* Single register transfers implemented as str/ldr. */
9731 if (inst
.instruction
& (1 << 23))
9732 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9734 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9738 if (inst
.instruction
& (1 << 23))
9739 inst
.instruction
= 0x00800000; /* ia -> [base] */
9741 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9744 inst
.instruction
|= 0xf8400000;
9746 inst
.instruction
|= 0x00100000;
9748 mask
= ffs (mask
) - 1;
9752 inst
.instruction
|= WRITE_BACK
;
9754 inst
.instruction
|= mask
;
9755 inst
.instruction
|= base
<< 16;
9761 /* This really doesn't seem worth it. */
9762 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9763 _("expression too complex"));
9764 constraint (inst
.operands
[1].writeback
,
9765 _("Thumb load/store multiple does not support {reglist}^"));
9773 /* See if we can use a 16-bit instruction. */
9774 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9775 && inst
.size_req
!= 4
9776 && !(inst
.operands
[1].imm
& ~0xff))
9778 mask
= 1 << inst
.operands
[0].reg
;
9780 if (inst
.operands
[0].reg
<= 7
9781 && (inst
.instruction
== T_MNEM_stmia
9782 ? inst
.operands
[0].writeback
9783 : (inst
.operands
[0].writeback
9784 == !(inst
.operands
[1].imm
& mask
))))
9786 if (inst
.instruction
== T_MNEM_stmia
9787 && (inst
.operands
[1].imm
& mask
)
9788 && (inst
.operands
[1].imm
& (mask
- 1)))
9789 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9790 inst
.operands
[0].reg
);
9792 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9793 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9794 inst
.instruction
|= inst
.operands
[1].imm
;
9797 else if (inst
.operands
[0] .reg
== REG_SP
9798 && inst
.operands
[0].writeback
)
9800 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9801 ? T_MNEM_push
: T_MNEM_pop
);
9802 inst
.instruction
|= inst
.operands
[1].imm
;
9809 if (inst
.instruction
< 0xffff)
9810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9812 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9813 inst
.operands
[0].writeback
);
9818 constraint (inst
.operands
[0].reg
> 7
9819 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9820 constraint (inst
.instruction
!= T_MNEM_ldmia
9821 && inst
.instruction
!= T_MNEM_stmia
,
9822 _("Thumb-2 instruction only valid in unified syntax"));
9823 if (inst
.instruction
== T_MNEM_stmia
)
9825 if (!inst
.operands
[0].writeback
)
9826 as_warn (_("this instruction will write back the base register"));
9827 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9828 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9829 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9830 inst
.operands
[0].reg
);
9834 if (!inst
.operands
[0].writeback
9835 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9836 as_warn (_("this instruction will write back the base register"));
9837 else if (inst
.operands
[0].writeback
9838 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9839 as_warn (_("this instruction will not write back the base register"));
9842 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9844 inst
.instruction
|= inst
.operands
[1].imm
;
9851 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9852 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9853 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9854 || inst
.operands
[1].negative
,
9857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9858 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9859 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9865 if (!inst
.operands
[1].present
)
9867 constraint (inst
.operands
[0].reg
== REG_LR
,
9868 _("r14 not allowed as first register "
9869 "when second register is omitted"));
9870 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9872 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9876 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9877 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9883 unsigned long opcode
;
9886 if (inst
.operands
[0].isreg
9887 && !inst
.operands
[0].preind
9888 && inst
.operands
[0].reg
== REG_PC
)
9889 set_it_insn_type_last ();
9891 opcode
= inst
.instruction
;
9894 if (!inst
.operands
[1].isreg
)
9896 if (opcode
<= 0xffff)
9897 inst
.instruction
= THUMB_OP32 (opcode
);
9898 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9901 if (inst
.operands
[1].isreg
9902 && !inst
.operands
[1].writeback
9903 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9904 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9906 && inst
.size_req
!= 4)
9908 /* Insn may have a 16-bit form. */
9909 Rn
= inst
.operands
[1].reg
;
9910 if (inst
.operands
[1].immisreg
)
9912 inst
.instruction
= THUMB_OP16 (opcode
);
9914 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9917 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9918 && opcode
!= T_MNEM_ldrsb
)
9919 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9920 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9927 if (inst
.reloc
.pc_rel
)
9928 opcode
= T_MNEM_ldr_pc2
;
9930 opcode
= T_MNEM_ldr_pc
;
9934 if (opcode
== T_MNEM_ldr
)
9935 opcode
= T_MNEM_ldr_sp
;
9937 opcode
= T_MNEM_str_sp
;
9939 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9943 inst
.instruction
= inst
.operands
[0].reg
;
9944 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9946 inst
.instruction
|= THUMB_OP16 (opcode
);
9947 if (inst
.size_req
== 2)
9948 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9950 inst
.relax
= opcode
;
9954 /* Definitely a 32-bit variant. */
9955 inst
.instruction
= THUMB_OP32 (opcode
);
9956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9957 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9961 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9963 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9965 /* Only [Rn,Rm] is acceptable. */
9966 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9967 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9968 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9969 || inst
.operands
[1].negative
,
9970 _("Thumb does not support this addressing mode"));
9971 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9975 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9976 if (!inst
.operands
[1].isreg
)
9977 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9980 constraint (!inst
.operands
[1].preind
9981 || inst
.operands
[1].shifted
9982 || inst
.operands
[1].writeback
,
9983 _("Thumb does not support this addressing mode"));
9984 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9986 constraint (inst
.instruction
& 0x0600,
9987 _("byte or halfword not valid for base register"));
9988 constraint (inst
.operands
[1].reg
== REG_PC
9989 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9990 _("r15 based store not allowed"));
9991 constraint (inst
.operands
[1].immisreg
,
9992 _("invalid base register for register offset"));
9994 if (inst
.operands
[1].reg
== REG_PC
)
9995 inst
.instruction
= T_OPCODE_LDR_PC
;
9996 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9997 inst
.instruction
= T_OPCODE_LDR_SP
;
9999 inst
.instruction
= T_OPCODE_STR_SP
;
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10002 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10006 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10007 if (!inst
.operands
[1].immisreg
)
10009 /* Immediate offset. */
10010 inst
.instruction
|= inst
.operands
[0].reg
;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10012 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10016 /* Register offset. */
10017 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10018 constraint (inst
.operands
[1].negative
,
10019 _("Thumb does not support this addressing mode"));
10022 switch (inst
.instruction
)
10024 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10025 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10026 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10027 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10028 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10029 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10030 case 0x5600 /* ldrsb */:
10031 case 0x5e00 /* ldrsh */: break;
10035 inst
.instruction
|= inst
.operands
[0].reg
;
10036 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10037 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10043 if (!inst
.operands
[1].present
)
10045 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10046 constraint (inst
.operands
[0].reg
== REG_LR
,
10047 _("r14 not allowed here"));
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10050 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10051 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10058 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10064 unsigned Rd
, Rn
, Rm
, Ra
;
10066 Rd
= inst
.operands
[0].reg
;
10067 Rn
= inst
.operands
[1].reg
;
10068 Rm
= inst
.operands
[2].reg
;
10069 Ra
= inst
.operands
[3].reg
;
10071 reject_bad_reg (Rd
);
10072 reject_bad_reg (Rn
);
10073 reject_bad_reg (Rm
);
10074 reject_bad_reg (Ra
);
10076 inst
.instruction
|= Rd
<< 8;
10077 inst
.instruction
|= Rn
<< 16;
10078 inst
.instruction
|= Rm
;
10079 inst
.instruction
|= Ra
<< 12;
10085 unsigned RdLo
, RdHi
, Rn
, Rm
;
10087 RdLo
= inst
.operands
[0].reg
;
10088 RdHi
= inst
.operands
[1].reg
;
10089 Rn
= inst
.operands
[2].reg
;
10090 Rm
= inst
.operands
[3].reg
;
10092 reject_bad_reg (RdLo
);
10093 reject_bad_reg (RdHi
);
10094 reject_bad_reg (Rn
);
10095 reject_bad_reg (Rm
);
10097 inst
.instruction
|= RdLo
<< 12;
10098 inst
.instruction
|= RdHi
<< 8;
10099 inst
.instruction
|= Rn
<< 16;
10100 inst
.instruction
|= Rm
;
10104 do_t_mov_cmp (void)
10108 Rn
= inst
.operands
[0].reg
;
10109 Rm
= inst
.operands
[1].reg
;
10112 set_it_insn_type_last ();
10114 if (unified_syntax
)
10116 int r0off
= (inst
.instruction
== T_MNEM_mov
10117 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10118 unsigned long opcode
;
10119 bfd_boolean narrow
;
10120 bfd_boolean low_regs
;
10122 low_regs
= (Rn
<= 7 && Rm
<= 7);
10123 opcode
= inst
.instruction
;
10124 if (in_it_block ())
10125 narrow
= opcode
!= T_MNEM_movs
;
10127 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10128 if (inst
.size_req
== 4
10129 || inst
.operands
[1].shifted
)
10132 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10133 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10134 && !inst
.operands
[1].shifted
10138 inst
.instruction
= T2_SUBS_PC_LR
;
10142 if (opcode
== T_MNEM_cmp
)
10144 constraint (Rn
== REG_PC
, BAD_PC
);
10147 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10149 warn_deprecated_sp (Rm
);
10150 /* R15 was documented as a valid choice for Rm in ARMv6,
10151 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10152 tools reject R15, so we do too. */
10153 constraint (Rm
== REG_PC
, BAD_PC
);
10156 reject_bad_reg (Rm
);
10158 else if (opcode
== T_MNEM_mov
10159 || opcode
== T_MNEM_movs
)
10161 if (inst
.operands
[1].isreg
)
10163 if (opcode
== T_MNEM_movs
)
10165 reject_bad_reg (Rn
);
10166 reject_bad_reg (Rm
);
10168 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10169 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10170 reject_bad_reg (Rm
);
10173 reject_bad_reg (Rn
);
10176 if (!inst
.operands
[1].isreg
)
10178 /* Immediate operand. */
10179 if (!in_it_block () && opcode
== T_MNEM_mov
)
10181 if (low_regs
&& narrow
)
10183 inst
.instruction
= THUMB_OP16 (opcode
);
10184 inst
.instruction
|= Rn
<< 8;
10185 if (inst
.size_req
== 2)
10186 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10188 inst
.relax
= opcode
;
10192 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10193 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10194 inst
.instruction
|= Rn
<< r0off
;
10195 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10198 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10199 && (inst
.instruction
== T_MNEM_mov
10200 || inst
.instruction
== T_MNEM_movs
))
10202 /* Register shifts are encoded as separate shift instructions. */
10203 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10205 if (in_it_block ())
10210 if (inst
.size_req
== 4)
10213 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10219 switch (inst
.operands
[1].shift_kind
)
10222 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10225 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10228 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10231 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10237 inst
.instruction
= opcode
;
10240 inst
.instruction
|= Rn
;
10241 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10246 inst
.instruction
|= CONDS_BIT
;
10248 inst
.instruction
|= Rn
<< 8;
10249 inst
.instruction
|= Rm
<< 16;
10250 inst
.instruction
|= inst
.operands
[1].imm
;
10255 /* Some mov with immediate shift have narrow variants.
10256 Register shifts are handled above. */
10257 if (low_regs
&& inst
.operands
[1].shifted
10258 && (inst
.instruction
== T_MNEM_mov
10259 || inst
.instruction
== T_MNEM_movs
))
10261 if (in_it_block ())
10262 narrow
= (inst
.instruction
== T_MNEM_mov
);
10264 narrow
= (inst
.instruction
== T_MNEM_movs
);
10269 switch (inst
.operands
[1].shift_kind
)
10271 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10272 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10273 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10274 default: narrow
= FALSE
; break;
10280 inst
.instruction
|= Rn
;
10281 inst
.instruction
|= Rm
<< 3;
10282 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10286 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10287 inst
.instruction
|= Rn
<< r0off
;
10288 encode_thumb32_shifted_operand (1);
10292 switch (inst
.instruction
)
10295 inst
.instruction
= T_OPCODE_MOV_HR
;
10296 inst
.instruction
|= (Rn
& 0x8) << 4;
10297 inst
.instruction
|= (Rn
& 0x7);
10298 inst
.instruction
|= Rm
<< 3;
10302 /* We know we have low registers at this point.
10303 Generate ADD Rd, Rs, #0. */
10304 inst
.instruction
= T_OPCODE_ADD_I3
;
10305 inst
.instruction
|= Rn
;
10306 inst
.instruction
|= Rm
<< 3;
10312 inst
.instruction
= T_OPCODE_CMP_LR
;
10313 inst
.instruction
|= Rn
;
10314 inst
.instruction
|= Rm
<< 3;
10318 inst
.instruction
= T_OPCODE_CMP_HR
;
10319 inst
.instruction
|= (Rn
& 0x8) << 4;
10320 inst
.instruction
|= (Rn
& 0x7);
10321 inst
.instruction
|= Rm
<< 3;
10328 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10330 /* PR 10443: Do not silently ignore shifted operands. */
10331 constraint (inst
.operands
[1].shifted
,
10332 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10334 if (inst
.operands
[1].isreg
)
10336 if (Rn
< 8 && Rm
< 8)
10338 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10339 since a MOV instruction produces unpredictable results. */
10340 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10341 inst
.instruction
= T_OPCODE_ADD_I3
;
10343 inst
.instruction
= T_OPCODE_CMP_LR
;
10345 inst
.instruction
|= Rn
;
10346 inst
.instruction
|= Rm
<< 3;
10350 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10351 inst
.instruction
= T_OPCODE_MOV_HR
;
10353 inst
.instruction
= T_OPCODE_CMP_HR
;
10359 constraint (Rn
> 7,
10360 _("only lo regs allowed with immediate"));
10361 inst
.instruction
|= Rn
<< 8;
10362 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10373 top
= (inst
.instruction
& 0x00800000) != 0;
10374 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10376 constraint (top
, _(":lower16: not allowed this instruction"));
10377 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10379 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10381 constraint (!top
, _(":upper16: not allowed this instruction"));
10382 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10385 Rd
= inst
.operands
[0].reg
;
10386 reject_bad_reg (Rd
);
10388 inst
.instruction
|= Rd
<< 8;
10389 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10391 imm
= inst
.reloc
.exp
.X_add_number
;
10392 inst
.instruction
|= (imm
& 0xf000) << 4;
10393 inst
.instruction
|= (imm
& 0x0800) << 15;
10394 inst
.instruction
|= (imm
& 0x0700) << 4;
10395 inst
.instruction
|= (imm
& 0x00ff);
10400 do_t_mvn_tst (void)
10404 Rn
= inst
.operands
[0].reg
;
10405 Rm
= inst
.operands
[1].reg
;
10407 if (inst
.instruction
== T_MNEM_cmp
10408 || inst
.instruction
== T_MNEM_cmn
)
10409 constraint (Rn
== REG_PC
, BAD_PC
);
10411 reject_bad_reg (Rn
);
10412 reject_bad_reg (Rm
);
10414 if (unified_syntax
)
10416 int r0off
= (inst
.instruction
== T_MNEM_mvn
10417 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10418 bfd_boolean narrow
;
10420 if (inst
.size_req
== 4
10421 || inst
.instruction
> 0xffff
10422 || inst
.operands
[1].shifted
10423 || Rn
> 7 || Rm
> 7)
10425 else if (inst
.instruction
== T_MNEM_cmn
)
10427 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10428 narrow
= !in_it_block ();
10430 narrow
= in_it_block ();
10432 if (!inst
.operands
[1].isreg
)
10434 /* For an immediate, we always generate a 32-bit opcode;
10435 section relaxation will shrink it later if possible. */
10436 if (inst
.instruction
< 0xffff)
10437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10438 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10439 inst
.instruction
|= Rn
<< r0off
;
10440 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10444 /* See if we can do this with a 16-bit instruction. */
10447 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10448 inst
.instruction
|= Rn
;
10449 inst
.instruction
|= Rm
<< 3;
10453 constraint (inst
.operands
[1].shifted
10454 && inst
.operands
[1].immisreg
,
10455 _("shift must be constant"));
10456 if (inst
.instruction
< 0xffff)
10457 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10458 inst
.instruction
|= Rn
<< r0off
;
10459 encode_thumb32_shifted_operand (1);
10465 constraint (inst
.instruction
> 0xffff
10466 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10467 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10468 _("unshifted register required"));
10469 constraint (Rn
> 7 || Rm
> 7,
10472 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10473 inst
.instruction
|= Rn
;
10474 inst
.instruction
|= Rm
<< 3;
10484 if (do_vfp_nsyn_mrs () == SUCCESS
)
10487 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10491 _("selected processor does not support "
10492 "requested special purpose register"));
10496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10497 _("selected processor does not support "
10498 "requested special purpose register"));
10499 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10500 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10501 _("'CPSR' or 'SPSR' expected"));
10504 Rd
= inst
.operands
[0].reg
;
10505 reject_bad_reg (Rd
);
10507 inst
.instruction
|= Rd
<< 8;
10508 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10509 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10518 if (do_vfp_nsyn_msr () == SUCCESS
)
10521 constraint (!inst
.operands
[1].isreg
,
10522 _("Thumb encoding does not support an immediate here"));
10523 flags
= inst
.operands
[0].imm
;
10526 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10527 _("selected processor does not support "
10528 "requested special purpose register"));
10532 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10533 _("selected processor does not support "
10534 "requested special purpose register"));
10538 Rn
= inst
.operands
[1].reg
;
10539 reject_bad_reg (Rn
);
10541 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10542 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10543 inst
.instruction
|= (flags
& 0xff);
10544 inst
.instruction
|= Rn
<< 16;
10550 bfd_boolean narrow
;
10551 unsigned Rd
, Rn
, Rm
;
10553 if (!inst
.operands
[2].present
)
10554 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10556 Rd
= inst
.operands
[0].reg
;
10557 Rn
= inst
.operands
[1].reg
;
10558 Rm
= inst
.operands
[2].reg
;
10560 if (unified_syntax
)
10562 if (inst
.size_req
== 4
10568 else if (inst
.instruction
== T_MNEM_muls
)
10569 narrow
= !in_it_block ();
10571 narrow
= in_it_block ();
10575 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10576 constraint (Rn
> 7 || Rm
> 7,
10583 /* 16-bit MULS/Conditional MUL. */
10584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10585 inst
.instruction
|= Rd
;
10588 inst
.instruction
|= Rm
<< 3;
10590 inst
.instruction
|= Rn
<< 3;
10592 constraint (1, _("dest must overlap one source register"));
10596 constraint (inst
.instruction
!= T_MNEM_mul
,
10597 _("Thumb-2 MUL must not set flags"));
10599 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10600 inst
.instruction
|= Rd
<< 8;
10601 inst
.instruction
|= Rn
<< 16;
10602 inst
.instruction
|= Rm
<< 0;
10604 reject_bad_reg (Rd
);
10605 reject_bad_reg (Rn
);
10606 reject_bad_reg (Rm
);
10613 unsigned RdLo
, RdHi
, Rn
, Rm
;
10615 RdLo
= inst
.operands
[0].reg
;
10616 RdHi
= inst
.operands
[1].reg
;
10617 Rn
= inst
.operands
[2].reg
;
10618 Rm
= inst
.operands
[3].reg
;
10620 reject_bad_reg (RdLo
);
10621 reject_bad_reg (RdHi
);
10622 reject_bad_reg (Rn
);
10623 reject_bad_reg (Rm
);
10625 inst
.instruction
|= RdLo
<< 12;
10626 inst
.instruction
|= RdHi
<< 8;
10627 inst
.instruction
|= Rn
<< 16;
10628 inst
.instruction
|= Rm
;
10631 as_tsktsk (_("rdhi and rdlo must be different"));
10637 set_it_insn_type (NEUTRAL_IT_INSN
);
10639 if (unified_syntax
)
10641 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10643 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10644 inst
.instruction
|= inst
.operands
[0].imm
;
10648 /* PR9722: Check for Thumb2 availability before
10649 generating a thumb2 nop instruction. */
10650 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10652 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10653 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10656 inst
.instruction
= 0x46c0;
10661 constraint (inst
.operands
[0].present
,
10662 _("Thumb does not support NOP with hints"));
10663 inst
.instruction
= 0x46c0;
10670 if (unified_syntax
)
10672 bfd_boolean narrow
;
10674 if (THUMB_SETS_FLAGS (inst
.instruction
))
10675 narrow
= !in_it_block ();
10677 narrow
= in_it_block ();
10678 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10680 if (inst
.size_req
== 4)
10685 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10686 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10687 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10692 inst
.instruction
|= inst
.operands
[0].reg
;
10693 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10698 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10700 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10702 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10703 inst
.instruction
|= inst
.operands
[0].reg
;
10704 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10713 Rd
= inst
.operands
[0].reg
;
10714 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10716 reject_bad_reg (Rd
);
10717 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10718 reject_bad_reg (Rn
);
10720 inst
.instruction
|= Rd
<< 8;
10721 inst
.instruction
|= Rn
<< 16;
10723 if (!inst
.operands
[2].isreg
)
10725 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10726 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10732 Rm
= inst
.operands
[2].reg
;
10733 reject_bad_reg (Rm
);
10735 constraint (inst
.operands
[2].shifted
10736 && inst
.operands
[2].immisreg
,
10737 _("shift must be constant"));
10738 encode_thumb32_shifted_operand (2);
10745 unsigned Rd
, Rn
, Rm
;
10747 Rd
= inst
.operands
[0].reg
;
10748 Rn
= inst
.operands
[1].reg
;
10749 Rm
= inst
.operands
[2].reg
;
10751 reject_bad_reg (Rd
);
10752 reject_bad_reg (Rn
);
10753 reject_bad_reg (Rm
);
10755 inst
.instruction
|= Rd
<< 8;
10756 inst
.instruction
|= Rn
<< 16;
10757 inst
.instruction
|= Rm
;
10758 if (inst
.operands
[3].present
)
10760 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10761 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10762 _("expression too complex"));
10763 inst
.instruction
|= (val
& 0x1c) << 10;
10764 inst
.instruction
|= (val
& 0x03) << 6;
10771 if (!inst
.operands
[3].present
)
10775 inst
.instruction
&= ~0x00000020;
10777 /* PR 10168. Swap the Rm and Rn registers. */
10778 Rtmp
= inst
.operands
[1].reg
;
10779 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10780 inst
.operands
[2].reg
= Rtmp
;
10788 if (inst
.operands
[0].immisreg
)
10789 reject_bad_reg (inst
.operands
[0].imm
);
10791 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10795 do_t_push_pop (void)
10799 constraint (inst
.operands
[0].writeback
,
10800 _("push/pop do not support {reglist}^"));
10801 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10802 _("expression too complex"));
10804 mask
= inst
.operands
[0].imm
;
10805 if ((mask
& ~0xff) == 0)
10806 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10807 else if ((inst
.instruction
== T_MNEM_push
10808 && (mask
& ~0xff) == 1 << REG_LR
)
10809 || (inst
.instruction
== T_MNEM_pop
10810 && (mask
& ~0xff) == 1 << REG_PC
))
10812 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10813 inst
.instruction
|= THUMB_PP_PC_LR
;
10814 inst
.instruction
|= mask
& 0xff;
10816 else if (unified_syntax
)
10818 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10819 encode_thumb2_ldmstm (13, mask
, TRUE
);
10823 inst
.error
= _("invalid register list to push/pop instruction");
10833 Rd
= inst
.operands
[0].reg
;
10834 Rm
= inst
.operands
[1].reg
;
10836 reject_bad_reg (Rd
);
10837 reject_bad_reg (Rm
);
10839 inst
.instruction
|= Rd
<< 8;
10840 inst
.instruction
|= Rm
<< 16;
10841 inst
.instruction
|= Rm
;
10849 Rd
= inst
.operands
[0].reg
;
10850 Rm
= inst
.operands
[1].reg
;
10852 reject_bad_reg (Rd
);
10853 reject_bad_reg (Rm
);
10855 if (Rd
<= 7 && Rm
<= 7
10856 && inst
.size_req
!= 4)
10858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10859 inst
.instruction
|= Rd
;
10860 inst
.instruction
|= Rm
<< 3;
10862 else if (unified_syntax
)
10864 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10865 inst
.instruction
|= Rd
<< 8;
10866 inst
.instruction
|= Rm
<< 16;
10867 inst
.instruction
|= Rm
;
10870 inst
.error
= BAD_HIREG
;
10878 Rd
= inst
.operands
[0].reg
;
10879 Rm
= inst
.operands
[1].reg
;
10881 reject_bad_reg (Rd
);
10882 reject_bad_reg (Rm
);
10884 inst
.instruction
|= Rd
<< 8;
10885 inst
.instruction
|= Rm
;
10893 Rd
= inst
.operands
[0].reg
;
10894 Rs
= (inst
.operands
[1].present
10895 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10896 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10898 reject_bad_reg (Rd
);
10899 reject_bad_reg (Rs
);
10900 if (inst
.operands
[2].isreg
)
10901 reject_bad_reg (inst
.operands
[2].reg
);
10903 inst
.instruction
|= Rd
<< 8;
10904 inst
.instruction
|= Rs
<< 16;
10905 if (!inst
.operands
[2].isreg
)
10907 bfd_boolean narrow
;
10909 if ((inst
.instruction
& 0x00100000) != 0)
10910 narrow
= !in_it_block ();
10912 narrow
= in_it_block ();
10914 if (Rd
> 7 || Rs
> 7)
10917 if (inst
.size_req
== 4 || !unified_syntax
)
10920 if (inst
.reloc
.exp
.X_op
!= O_constant
10921 || inst
.reloc
.exp
.X_add_number
!= 0)
10924 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10925 relaxation, but it doesn't seem worth the hassle. */
10928 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10929 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10930 inst
.instruction
|= Rs
<< 3;
10931 inst
.instruction
|= Rd
;
10935 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10936 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10940 encode_thumb32_shifted_operand (2);
10946 set_it_insn_type (OUTSIDE_IT_INSN
);
10947 if (inst
.operands
[0].imm
)
10948 inst
.instruction
|= 0x8;
10954 if (!inst
.operands
[1].present
)
10955 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10957 if (unified_syntax
)
10959 bfd_boolean narrow
;
10962 switch (inst
.instruction
)
10965 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10967 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10969 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10971 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10975 if (THUMB_SETS_FLAGS (inst
.instruction
))
10976 narrow
= !in_it_block ();
10978 narrow
= in_it_block ();
10979 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10981 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10983 if (inst
.operands
[2].isreg
10984 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10985 || inst
.operands
[2].reg
> 7))
10987 if (inst
.size_req
== 4)
10990 reject_bad_reg (inst
.operands
[0].reg
);
10991 reject_bad_reg (inst
.operands
[1].reg
);
10995 if (inst
.operands
[2].isreg
)
10997 reject_bad_reg (inst
.operands
[2].reg
);
10998 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10999 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11001 inst
.instruction
|= inst
.operands
[2].reg
;
11005 inst
.operands
[1].shifted
= 1;
11006 inst
.operands
[1].shift_kind
= shift_kind
;
11007 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11008 ? T_MNEM_movs
: T_MNEM_mov
);
11009 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11010 encode_thumb32_shifted_operand (1);
11011 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11012 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11017 if (inst
.operands
[2].isreg
)
11019 switch (shift_kind
)
11021 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11022 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11023 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11024 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11028 inst
.instruction
|= inst
.operands
[0].reg
;
11029 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11033 switch (shift_kind
)
11035 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11036 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11037 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11040 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11041 inst
.instruction
|= inst
.operands
[0].reg
;
11042 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11048 constraint (inst
.operands
[0].reg
> 7
11049 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11050 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11052 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11054 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11055 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11056 _("source1 and dest must be same register"));
11058 switch (inst
.instruction
)
11060 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11061 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11062 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11063 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11067 inst
.instruction
|= inst
.operands
[0].reg
;
11068 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11072 switch (inst
.instruction
)
11074 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11075 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11076 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11077 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11080 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11081 inst
.instruction
|= inst
.operands
[0].reg
;
11082 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11090 unsigned Rd
, Rn
, Rm
;
11092 Rd
= inst
.operands
[0].reg
;
11093 Rn
= inst
.operands
[1].reg
;
11094 Rm
= inst
.operands
[2].reg
;
11096 reject_bad_reg (Rd
);
11097 reject_bad_reg (Rn
);
11098 reject_bad_reg (Rm
);
11100 inst
.instruction
|= Rd
<< 8;
11101 inst
.instruction
|= Rn
<< 16;
11102 inst
.instruction
|= Rm
;
11108 unsigned Rd
, Rn
, Rm
;
11110 Rd
= inst
.operands
[0].reg
;
11111 Rm
= inst
.operands
[1].reg
;
11112 Rn
= inst
.operands
[2].reg
;
11114 reject_bad_reg (Rd
);
11115 reject_bad_reg (Rn
);
11116 reject_bad_reg (Rm
);
11118 inst
.instruction
|= Rd
<< 8;
11119 inst
.instruction
|= Rn
<< 16;
11120 inst
.instruction
|= Rm
;
11126 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11127 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11128 _("expression too complex"));
11129 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11130 inst
.instruction
|= (value
& 0xf000) >> 12;
11131 inst
.instruction
|= (value
& 0x0ff0);
11132 inst
.instruction
|= (value
& 0x000f) << 16;
11136 do_t_ssat_usat (int bias
)
11140 Rd
= inst
.operands
[0].reg
;
11141 Rn
= inst
.operands
[2].reg
;
11143 reject_bad_reg (Rd
);
11144 reject_bad_reg (Rn
);
11146 inst
.instruction
|= Rd
<< 8;
11147 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11148 inst
.instruction
|= Rn
<< 16;
11150 if (inst
.operands
[3].present
)
11152 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11154 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11156 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11157 _("expression too complex"));
11159 if (shift_amount
!= 0)
11161 constraint (shift_amount
> 31,
11162 _("shift expression is too large"));
11164 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11165 inst
.instruction
|= 0x00200000; /* sh bit. */
11167 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11168 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11176 do_t_ssat_usat (1);
11184 Rd
= inst
.operands
[0].reg
;
11185 Rn
= inst
.operands
[2].reg
;
11187 reject_bad_reg (Rd
);
11188 reject_bad_reg (Rn
);
11190 inst
.instruction
|= Rd
<< 8;
11191 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11192 inst
.instruction
|= Rn
<< 16;
11198 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11199 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11200 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11201 || inst
.operands
[2].negative
,
11204 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11205 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11206 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11207 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11213 if (!inst
.operands
[2].present
)
11214 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11216 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11217 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11218 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11219 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11222 inst
.instruction
|= inst
.operands
[0].reg
;
11223 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11224 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11225 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11231 unsigned Rd
, Rn
, Rm
;
11233 Rd
= inst
.operands
[0].reg
;
11234 Rn
= inst
.operands
[1].reg
;
11235 Rm
= inst
.operands
[2].reg
;
11237 reject_bad_reg (Rd
);
11238 reject_bad_reg (Rn
);
11239 reject_bad_reg (Rm
);
11241 inst
.instruction
|= Rd
<< 8;
11242 inst
.instruction
|= Rn
<< 16;
11243 inst
.instruction
|= Rm
;
11244 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11252 Rd
= inst
.operands
[0].reg
;
11253 Rm
= inst
.operands
[1].reg
;
11255 reject_bad_reg (Rd
);
11256 reject_bad_reg (Rm
);
11258 if (inst
.instruction
<= 0xffff
11259 && inst
.size_req
!= 4
11260 && Rd
<= 7 && Rm
<= 7
11261 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11263 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11264 inst
.instruction
|= Rd
;
11265 inst
.instruction
|= Rm
<< 3;
11267 else if (unified_syntax
)
11269 if (inst
.instruction
<= 0xffff)
11270 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11271 inst
.instruction
|= Rd
<< 8;
11272 inst
.instruction
|= Rm
;
11273 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11277 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11278 _("Thumb encoding does not support rotation"));
11279 constraint (1, BAD_HIREG
);
11286 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11295 half
= (inst
.instruction
& 0x10) != 0;
11296 set_it_insn_type_last ();
11297 constraint (inst
.operands
[0].immisreg
,
11298 _("instruction requires register index"));
11300 Rn
= inst
.operands
[0].reg
;
11301 Rm
= inst
.operands
[0].imm
;
11303 constraint (Rn
== REG_SP
, BAD_SP
);
11304 reject_bad_reg (Rm
);
11306 constraint (!half
&& inst
.operands
[0].shifted
,
11307 _("instruction does not allow shifted index"));
11308 inst
.instruction
|= (Rn
<< 16) | Rm
;
11314 do_t_ssat_usat (0);
11322 Rd
= inst
.operands
[0].reg
;
11323 Rn
= inst
.operands
[2].reg
;
11325 reject_bad_reg (Rd
);
11326 reject_bad_reg (Rn
);
11328 inst
.instruction
|= Rd
<< 8;
11329 inst
.instruction
|= inst
.operands
[1].imm
;
11330 inst
.instruction
|= Rn
<< 16;
11333 /* Neon instruction encoder helpers. */
11335 /* Encodings for the different types for various Neon opcodes. */
11337 /* An "invalid" code for the following tables. */
11340 struct neon_tab_entry
11343 unsigned float_or_poly
;
11344 unsigned scalar_or_imm
;
11347 /* Map overloaded Neon opcodes to their respective encodings. */
11348 #define NEON_ENC_TAB \
11349 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11350 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11351 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11352 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11353 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11354 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11355 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11356 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11357 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11358 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11359 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11360 /* Register variants of the following two instructions are encoded as
11361 vcge / vcgt with the operands reversed. */ \
11362 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11363 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11364 X(vfma, N_INV, 0x0000c10, N_INV), \
11365 X(vfms, N_INV, 0x0200c10, N_INV), \
11366 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11367 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11368 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11369 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11370 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11371 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11372 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11373 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11374 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11375 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11376 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11377 X(vshl, 0x0000400, N_INV, 0x0800510), \
11378 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11379 X(vand, 0x0000110, N_INV, 0x0800030), \
11380 X(vbic, 0x0100110, N_INV, 0x0800030), \
11381 X(veor, 0x1000110, N_INV, N_INV), \
11382 X(vorn, 0x0300110, N_INV, 0x0800010), \
11383 X(vorr, 0x0200110, N_INV, 0x0800010), \
11384 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11385 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11386 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11387 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11388 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11389 X(vst1, 0x0000000, 0x0800000, N_INV), \
11390 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11391 X(vst2, 0x0000100, 0x0800100, N_INV), \
11392 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11393 X(vst3, 0x0000200, 0x0800200, N_INV), \
11394 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11395 X(vst4, 0x0000300, 0x0800300, N_INV), \
11396 X(vmovn, 0x1b20200, N_INV, N_INV), \
11397 X(vtrn, 0x1b20080, N_INV, N_INV), \
11398 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11399 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11400 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11401 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11402 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11403 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11404 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11405 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11406 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11407 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11408 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11412 #define X(OPC,I,F,S) N_MNEM_##OPC
11417 static const struct neon_tab_entry neon_enc_tab
[] =
11419 #define X(OPC,I,F,S) { (I), (F), (S) }
11424 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11425 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11426 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11427 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11428 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11429 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11430 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11431 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11432 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11433 #define NEON_ENC_SINGLE(X) \
11434 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11435 #define NEON_ENC_DOUBLE(X) \
11436 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11438 /* Define shapes for instruction operands. The following mnemonic characters
11439 are used in this table:
11441 F - VFP S<n> register
11442 D - Neon D<n> register
11443 Q - Neon Q<n> register
11447 L - D<n> register list
11449 This table is used to generate various data:
11450 - enumerations of the form NS_DDR to be used as arguments to
11452 - a table classifying shapes into single, double, quad, mixed.
11453 - a table used to drive neon_select_shape. */
11455 #define NEON_SHAPE_DEF \
11456 X(3, (D, D, D), DOUBLE), \
11457 X(3, (Q, Q, Q), QUAD), \
11458 X(3, (D, D, I), DOUBLE), \
11459 X(3, (Q, Q, I), QUAD), \
11460 X(3, (D, D, S), DOUBLE), \
11461 X(3, (Q, Q, S), QUAD), \
11462 X(2, (D, D), DOUBLE), \
11463 X(2, (Q, Q), QUAD), \
11464 X(2, (D, S), DOUBLE), \
11465 X(2, (Q, S), QUAD), \
11466 X(2, (D, R), DOUBLE), \
11467 X(2, (Q, R), QUAD), \
11468 X(2, (D, I), DOUBLE), \
11469 X(2, (Q, I), QUAD), \
11470 X(3, (D, L, D), DOUBLE), \
11471 X(2, (D, Q), MIXED), \
11472 X(2, (Q, D), MIXED), \
11473 X(3, (D, Q, I), MIXED), \
11474 X(3, (Q, D, I), MIXED), \
11475 X(3, (Q, D, D), MIXED), \
11476 X(3, (D, Q, Q), MIXED), \
11477 X(3, (Q, Q, D), MIXED), \
11478 X(3, (Q, D, S), MIXED), \
11479 X(3, (D, Q, S), MIXED), \
11480 X(4, (D, D, D, I), DOUBLE), \
11481 X(4, (Q, Q, Q, I), QUAD), \
11482 X(2, (F, F), SINGLE), \
11483 X(3, (F, F, F), SINGLE), \
11484 X(2, (F, I), SINGLE), \
11485 X(2, (F, D), MIXED), \
11486 X(2, (D, F), MIXED), \
11487 X(3, (F, F, I), MIXED), \
11488 X(4, (R, R, F, F), SINGLE), \
11489 X(4, (F, F, R, R), SINGLE), \
11490 X(3, (D, R, R), DOUBLE), \
11491 X(3, (R, R, D), DOUBLE), \
11492 X(2, (S, R), SINGLE), \
11493 X(2, (R, S), SINGLE), \
11494 X(2, (F, R), SINGLE), \
11495 X(2, (R, F), SINGLE)
11497 #define S2(A,B) NS_##A##B
11498 #define S3(A,B,C) NS_##A##B##C
11499 #define S4(A,B,C,D) NS_##A##B##C##D
11501 #define X(N, L, C) S##N L
11514 enum neon_shape_class
11522 #define X(N, L, C) SC_##C
11524 static enum neon_shape_class neon_shape_class
[] =
11542 /* Register widths of above. */
11543 static unsigned neon_shape_el_size
[] =
11554 struct neon_shape_info
11557 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11560 #define S2(A,B) { SE_##A, SE_##B }
11561 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11562 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11564 #define X(N, L, C) { N, S##N L }
11566 static struct neon_shape_info neon_shape_tab
[] =
11576 /* Bit masks used in type checking given instructions.
11577 'N_EQK' means the type must be the same as (or based on in some way) the key
11578 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11579 set, various other bits can be set as well in order to modify the meaning of
11580 the type constraint. */
11582 enum neon_type_mask
11605 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11606 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11607 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11608 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11609 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11610 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11611 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11612 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11613 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11614 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11616 N_MAX_NONSPECIAL
= N_F64
11619 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11621 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11622 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11623 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11624 #define N_SUF_32 (N_SU_32 | N_F32)
11625 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11626 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11628 /* Pass this as the first type argument to neon_check_type to ignore types
11630 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11632 /* Select a "shape" for the current instruction (describing register types or
11633 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11634 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11635 function of operand parsing, so this function doesn't need to be called.
11636 Shapes should be listed in order of decreasing length. */
11638 static enum neon_shape
11639 neon_select_shape (enum neon_shape shape
, ...)
11642 enum neon_shape first_shape
= shape
;
11644 /* Fix missing optional operands. FIXME: we don't know at this point how
11645 many arguments we should have, so this makes the assumption that we have
11646 > 1. This is true of all current Neon opcodes, I think, but may not be
11647 true in the future. */
11648 if (!inst
.operands
[1].present
)
11649 inst
.operands
[1] = inst
.operands
[0];
11651 va_start (ap
, shape
);
11653 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11658 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11660 if (!inst
.operands
[j
].present
)
11666 switch (neon_shape_tab
[shape
].el
[j
])
11669 if (!(inst
.operands
[j
].isreg
11670 && inst
.operands
[j
].isvec
11671 && inst
.operands
[j
].issingle
11672 && !inst
.operands
[j
].isquad
))
11677 if (!(inst
.operands
[j
].isreg
11678 && inst
.operands
[j
].isvec
11679 && !inst
.operands
[j
].isquad
11680 && !inst
.operands
[j
].issingle
))
11685 if (!(inst
.operands
[j
].isreg
11686 && !inst
.operands
[j
].isvec
))
11691 if (!(inst
.operands
[j
].isreg
11692 && inst
.operands
[j
].isvec
11693 && inst
.operands
[j
].isquad
11694 && !inst
.operands
[j
].issingle
))
11699 if (!(!inst
.operands
[j
].isreg
11700 && !inst
.operands
[j
].isscalar
))
11705 if (!(!inst
.operands
[j
].isreg
11706 && inst
.operands
[j
].isscalar
))
11720 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11721 first_error (_("invalid instruction shape"));
11726 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11727 means the Q bit should be set). */
11730 neon_quad (enum neon_shape shape
)
11732 return neon_shape_class
[shape
] == SC_QUAD
;
11736 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11739 /* Allow modification to be made to types which are constrained to be
11740 based on the key element, based on bits set alongside N_EQK. */
11741 if ((typebits
& N_EQK
) != 0)
11743 if ((typebits
& N_HLF
) != 0)
11745 else if ((typebits
& N_DBL
) != 0)
11747 if ((typebits
& N_SGN
) != 0)
11748 *g_type
= NT_signed
;
11749 else if ((typebits
& N_UNS
) != 0)
11750 *g_type
= NT_unsigned
;
11751 else if ((typebits
& N_INT
) != 0)
11752 *g_type
= NT_integer
;
11753 else if ((typebits
& N_FLT
) != 0)
11754 *g_type
= NT_float
;
11755 else if ((typebits
& N_SIZ
) != 0)
11756 *g_type
= NT_untyped
;
11760 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11761 operand type, i.e. the single type specified in a Neon instruction when it
11762 is the only one given. */
11764 static struct neon_type_el
11765 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11767 struct neon_type_el dest
= *key
;
11769 gas_assert ((thisarg
& N_EQK
) != 0);
11771 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11776 /* Convert Neon type and size into compact bitmask representation. */
11778 static enum neon_type_mask
11779 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11786 case 8: return N_8
;
11787 case 16: return N_16
;
11788 case 32: return N_32
;
11789 case 64: return N_64
;
11797 case 8: return N_I8
;
11798 case 16: return N_I16
;
11799 case 32: return N_I32
;
11800 case 64: return N_I64
;
11808 case 16: return N_F16
;
11809 case 32: return N_F32
;
11810 case 64: return N_F64
;
11818 case 8: return N_P8
;
11819 case 16: return N_P16
;
11827 case 8: return N_S8
;
11828 case 16: return N_S16
;
11829 case 32: return N_S32
;
11830 case 64: return N_S64
;
11838 case 8: return N_U8
;
11839 case 16: return N_U16
;
11840 case 32: return N_U32
;
11841 case 64: return N_U64
;
11852 /* Convert compact Neon bitmask type representation to a type and size. Only
11853 handles the case where a single bit is set in the mask. */
11856 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11857 enum neon_type_mask mask
)
11859 if ((mask
& N_EQK
) != 0)
11862 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11864 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11866 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11868 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11873 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11875 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11876 *type
= NT_unsigned
;
11877 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11878 *type
= NT_integer
;
11879 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11880 *type
= NT_untyped
;
11881 else if ((mask
& (N_P8
| N_P16
)) != 0)
11883 else if ((mask
& (N_F32
| N_F64
)) != 0)
11891 /* Modify a bitmask of allowed types. This is only needed for type
11895 modify_types_allowed (unsigned allowed
, unsigned mods
)
11898 enum neon_el_type type
;
11904 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11906 if (el_type_of_type_chk (&type
, &size
,
11907 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11909 neon_modify_type_size (mods
, &type
, &size
);
11910 destmask
|= type_chk_of_el_type (type
, size
);
11917 /* Check type and return type classification.
11918 The manual states (paraphrase): If one datatype is given, it indicates the
11920 - the second operand, if there is one
11921 - the operand, if there is no second operand
11922 - the result, if there are no operands.
11923 This isn't quite good enough though, so we use a concept of a "key" datatype
11924 which is set on a per-instruction basis, which is the one which matters when
11925 only one data type is written.
11926 Note: this function has side-effects (e.g. filling in missing operands). All
11927 Neon instructions should call it before performing bit encoding. */
11929 static struct neon_type_el
11930 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11933 unsigned i
, pass
, key_el
= 0;
11934 unsigned types
[NEON_MAX_TYPE_ELS
];
11935 enum neon_el_type k_type
= NT_invtype
;
11936 unsigned k_size
= -1u;
11937 struct neon_type_el badtype
= {NT_invtype
, -1};
11938 unsigned key_allowed
= 0;
11940 /* Optional registers in Neon instructions are always (not) in operand 1.
11941 Fill in the missing operand here, if it was omitted. */
11942 if (els
> 1 && !inst
.operands
[1].present
)
11943 inst
.operands
[1] = inst
.operands
[0];
11945 /* Suck up all the varargs. */
11947 for (i
= 0; i
< els
; i
++)
11949 unsigned thisarg
= va_arg (ap
, unsigned);
11950 if (thisarg
== N_IGNORE_TYPE
)
11955 types
[i
] = thisarg
;
11956 if ((thisarg
& N_KEY
) != 0)
11961 if (inst
.vectype
.elems
> 0)
11962 for (i
= 0; i
< els
; i
++)
11963 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11965 first_error (_("types specified in both the mnemonic and operands"));
11969 /* Duplicate inst.vectype elements here as necessary.
11970 FIXME: No idea if this is exactly the same as the ARM assembler,
11971 particularly when an insn takes one register and one non-register
11973 if (inst
.vectype
.elems
== 1 && els
> 1)
11976 inst
.vectype
.elems
= els
;
11977 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11978 for (j
= 0; j
< els
; j
++)
11980 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11983 else if (inst
.vectype
.elems
== 0 && els
> 0)
11986 /* No types were given after the mnemonic, so look for types specified
11987 after each operand. We allow some flexibility here; as long as the
11988 "key" operand has a type, we can infer the others. */
11989 for (j
= 0; j
< els
; j
++)
11990 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11991 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11993 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11995 for (j
= 0; j
< els
; j
++)
11996 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11997 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12002 first_error (_("operand types can't be inferred"));
12006 else if (inst
.vectype
.elems
!= els
)
12008 first_error (_("type specifier has the wrong number of parts"));
12012 for (pass
= 0; pass
< 2; pass
++)
12014 for (i
= 0; i
< els
; i
++)
12016 unsigned thisarg
= types
[i
];
12017 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12018 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12019 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12020 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12022 /* Decay more-specific signed & unsigned types to sign-insensitive
12023 integer types if sign-specific variants are unavailable. */
12024 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12025 && (types_allowed
& N_SU_ALL
) == 0)
12026 g_type
= NT_integer
;
12028 /* If only untyped args are allowed, decay any more specific types to
12029 them. Some instructions only care about signs for some element
12030 sizes, so handle that properly. */
12031 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12032 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12033 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12034 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12035 g_type
= NT_untyped
;
12039 if ((thisarg
& N_KEY
) != 0)
12043 key_allowed
= thisarg
& ~N_KEY
;
12048 if ((thisarg
& N_VFP
) != 0)
12050 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
12051 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
12053 /* In VFP mode, operands must match register widths. If we
12054 have a key operand, use its width, else use the width of
12055 the current operand. */
12061 if (regwidth
!= match
)
12063 first_error (_("operand size must match register width"));
12068 if ((thisarg
& N_EQK
) == 0)
12070 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12072 if ((given_type
& types_allowed
) == 0)
12074 first_error (_("bad type in Neon instruction"));
12080 enum neon_el_type mod_k_type
= k_type
;
12081 unsigned mod_k_size
= k_size
;
12082 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12083 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12085 first_error (_("inconsistent types in Neon instruction"));
12093 return inst
.vectype
.el
[key_el
];
12096 /* Neon-style VFP instruction forwarding. */
12098 /* Thumb VFP instructions have 0xE in the condition field. */
12101 do_vfp_cond_or_thumb (void)
12104 inst
.instruction
|= 0xe0000000;
12106 inst
.instruction
|= inst
.cond
<< 28;
12109 /* Look up and encode a simple mnemonic, for use as a helper function for the
12110 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12111 etc. It is assumed that operand parsing has already been done, and that the
12112 operands are in the form expected by the given opcode (this isn't necessarily
12113 the same as the form in which they were parsed, hence some massaging must
12114 take place before this function is called).
12115 Checks current arch version against that in the looked-up opcode. */
12118 do_vfp_nsyn_opcode (const char *opname
)
12120 const struct asm_opcode
*opcode
;
12122 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12128 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12133 inst
.instruction
= opcode
->tvalue
;
12134 opcode
->tencode ();
12138 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12139 opcode
->aencode ();
12144 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12146 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12151 do_vfp_nsyn_opcode ("fadds");
12153 do_vfp_nsyn_opcode ("fsubs");
12158 do_vfp_nsyn_opcode ("faddd");
12160 do_vfp_nsyn_opcode ("fsubd");
12164 /* Check operand types to see if this is a VFP instruction, and if so call
12168 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12170 enum neon_shape rs
;
12171 struct neon_type_el et
;
12176 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12177 et
= neon_check_type (2, rs
,
12178 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12182 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12183 et
= neon_check_type (3, rs
,
12184 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12191 if (et
.type
!= NT_invtype
)
12203 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12205 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12210 do_vfp_nsyn_opcode ("fmacs");
12212 do_vfp_nsyn_opcode ("fnmacs");
12217 do_vfp_nsyn_opcode ("fmacd");
12219 do_vfp_nsyn_opcode ("fnmacd");
12224 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12226 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12231 do_vfp_nsyn_opcode ("ffmas");
12233 do_vfp_nsyn_opcode ("ffnmas");
12238 do_vfp_nsyn_opcode ("ffmad");
12240 do_vfp_nsyn_opcode ("ffnmad");
12245 do_vfp_nsyn_mul (enum neon_shape rs
)
12248 do_vfp_nsyn_opcode ("fmuls");
12250 do_vfp_nsyn_opcode ("fmuld");
12254 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12256 int is_neg
= (inst
.instruction
& 0x80) != 0;
12257 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12262 do_vfp_nsyn_opcode ("fnegs");
12264 do_vfp_nsyn_opcode ("fabss");
12269 do_vfp_nsyn_opcode ("fnegd");
12271 do_vfp_nsyn_opcode ("fabsd");
12275 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12276 insns belong to Neon, and are handled elsewhere. */
12279 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12281 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12285 do_vfp_nsyn_opcode ("fldmdbs");
12287 do_vfp_nsyn_opcode ("fldmias");
12292 do_vfp_nsyn_opcode ("fstmdbs");
12294 do_vfp_nsyn_opcode ("fstmias");
12299 do_vfp_nsyn_sqrt (void)
12301 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12302 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12305 do_vfp_nsyn_opcode ("fsqrts");
12307 do_vfp_nsyn_opcode ("fsqrtd");
12311 do_vfp_nsyn_div (void)
12313 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12314 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12315 N_F32
| N_F64
| N_KEY
| N_VFP
);
12318 do_vfp_nsyn_opcode ("fdivs");
12320 do_vfp_nsyn_opcode ("fdivd");
12324 do_vfp_nsyn_nmul (void)
12326 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12327 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12328 N_F32
| N_F64
| N_KEY
| N_VFP
);
12332 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12333 do_vfp_sp_dyadic ();
12337 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12338 do_vfp_dp_rd_rn_rm ();
12340 do_vfp_cond_or_thumb ();
12344 do_vfp_nsyn_cmp (void)
12346 if (inst
.operands
[1].isreg
)
12348 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12349 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12353 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12354 do_vfp_sp_monadic ();
12358 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12359 do_vfp_dp_rd_rm ();
12364 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12365 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12367 switch (inst
.instruction
& 0x0fffffff)
12370 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12373 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12381 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12382 do_vfp_sp_compare_z ();
12386 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12390 do_vfp_cond_or_thumb ();
12394 nsyn_insert_sp (void)
12396 inst
.operands
[1] = inst
.operands
[0];
12397 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12398 inst
.operands
[0].reg
= REG_SP
;
12399 inst
.operands
[0].isreg
= 1;
12400 inst
.operands
[0].writeback
= 1;
12401 inst
.operands
[0].present
= 1;
12405 do_vfp_nsyn_push (void)
12408 if (inst
.operands
[1].issingle
)
12409 do_vfp_nsyn_opcode ("fstmdbs");
12411 do_vfp_nsyn_opcode ("fstmdbd");
12415 do_vfp_nsyn_pop (void)
12418 if (inst
.operands
[1].issingle
)
12419 do_vfp_nsyn_opcode ("fldmias");
12421 do_vfp_nsyn_opcode ("fldmiad");
12424 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12425 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12428 neon_dp_fixup (unsigned i
)
12432 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12446 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12450 neon_logbits (unsigned x
)
12452 return ffs (x
) - 4;
12455 #define LOW4(R) ((R) & 0xf)
12456 #define HI1(R) (((R) >> 4) & 1)
12458 /* Encode insns with bit pattern:
12460 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12461 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12463 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12464 different meaning for some instruction. */
12467 neon_three_same (int isquad
, int ubit
, int size
)
12469 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12470 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12471 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12472 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12473 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12474 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12475 inst
.instruction
|= (isquad
!= 0) << 6;
12476 inst
.instruction
|= (ubit
!= 0) << 24;
12478 inst
.instruction
|= neon_logbits (size
) << 20;
12480 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12483 /* Encode instructions of the form:
12485 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12486 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12488 Don't write size if SIZE == -1. */
12491 neon_two_same (int qbit
, int ubit
, int size
)
12493 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12494 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12495 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12496 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12497 inst
.instruction
|= (qbit
!= 0) << 6;
12498 inst
.instruction
|= (ubit
!= 0) << 24;
12501 inst
.instruction
|= neon_logbits (size
) << 18;
12503 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12506 /* Neon instruction encoders, in approximate order of appearance. */
12509 do_neon_dyadic_i_su (void)
12511 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12512 struct neon_type_el et
= neon_check_type (3, rs
,
12513 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12514 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12518 do_neon_dyadic_i64_su (void)
12520 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12521 struct neon_type_el et
= neon_check_type (3, rs
,
12522 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12523 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12527 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12530 unsigned size
= et
.size
>> 3;
12531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12535 inst
.instruction
|= (isquad
!= 0) << 6;
12536 inst
.instruction
|= immbits
<< 16;
12537 inst
.instruction
|= (size
>> 3) << 7;
12538 inst
.instruction
|= (size
& 0x7) << 19;
12540 inst
.instruction
|= (uval
!= 0) << 24;
12542 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12546 do_neon_shl_imm (void)
12548 if (!inst
.operands
[2].isreg
)
12550 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12551 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12552 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12553 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12557 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12558 struct neon_type_el et
= neon_check_type (3, rs
,
12559 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12562 /* VSHL/VQSHL 3-register variants have syntax such as:
12564 whereas other 3-register operations encoded by neon_three_same have
12567 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12569 tmp
= inst
.operands
[2].reg
;
12570 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12571 inst
.operands
[1].reg
= tmp
;
12572 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12573 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12578 do_neon_qshl_imm (void)
12580 if (!inst
.operands
[2].isreg
)
12582 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12583 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12585 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12586 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12587 inst
.operands
[2].imm
);
12591 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12592 struct neon_type_el et
= neon_check_type (3, rs
,
12593 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12596 /* See note in do_neon_shl_imm. */
12597 tmp
= inst
.operands
[2].reg
;
12598 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12599 inst
.operands
[1].reg
= tmp
;
12600 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12601 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12606 do_neon_rshl (void)
12608 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12609 struct neon_type_el et
= neon_check_type (3, rs
,
12610 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12613 tmp
= inst
.operands
[2].reg
;
12614 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12615 inst
.operands
[1].reg
= tmp
;
12616 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12620 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12622 /* Handle .I8 pseudo-instructions. */
12625 /* Unfortunately, this will make everything apart from zero out-of-range.
12626 FIXME is this the intended semantics? There doesn't seem much point in
12627 accepting .I8 if so. */
12628 immediate
|= immediate
<< 8;
12634 if (immediate
== (immediate
& 0x000000ff))
12636 *immbits
= immediate
;
12639 else if (immediate
== (immediate
& 0x0000ff00))
12641 *immbits
= immediate
>> 8;
12644 else if (immediate
== (immediate
& 0x00ff0000))
12646 *immbits
= immediate
>> 16;
12649 else if (immediate
== (immediate
& 0xff000000))
12651 *immbits
= immediate
>> 24;
12654 if ((immediate
& 0xffff) != (immediate
>> 16))
12655 goto bad_immediate
;
12656 immediate
&= 0xffff;
12659 if (immediate
== (immediate
& 0x000000ff))
12661 *immbits
= immediate
;
12664 else if (immediate
== (immediate
& 0x0000ff00))
12666 *immbits
= immediate
>> 8;
12671 first_error (_("immediate value out of range"));
12675 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12679 neon_bits_same_in_bytes (unsigned imm
)
12681 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12682 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12683 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12684 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12687 /* For immediate of above form, return 0bABCD. */
12690 neon_squash_bits (unsigned imm
)
12692 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12693 | ((imm
& 0x01000000) >> 21);
12696 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12699 neon_qfloat_bits (unsigned imm
)
12701 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12704 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12705 the instruction. *OP is passed as the initial value of the op field, and
12706 may be set to a different value depending on the constant (i.e.
12707 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12708 MVN). If the immediate looks like a repeated pattern then also
12709 try smaller element sizes. */
12712 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12713 unsigned *immbits
, int *op
, int size
,
12714 enum neon_el_type type
)
12716 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12718 if (type
== NT_float
&& !float_p
)
12721 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12723 if (size
!= 32 || *op
== 1)
12725 *immbits
= neon_qfloat_bits (immlo
);
12731 if (neon_bits_same_in_bytes (immhi
)
12732 && neon_bits_same_in_bytes (immlo
))
12736 *immbits
= (neon_squash_bits (immhi
) << 4)
12737 | neon_squash_bits (immlo
);
12742 if (immhi
!= immlo
)
12748 if (immlo
== (immlo
& 0x000000ff))
12753 else if (immlo
== (immlo
& 0x0000ff00))
12755 *immbits
= immlo
>> 8;
12758 else if (immlo
== (immlo
& 0x00ff0000))
12760 *immbits
= immlo
>> 16;
12763 else if (immlo
== (immlo
& 0xff000000))
12765 *immbits
= immlo
>> 24;
12768 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12770 *immbits
= (immlo
>> 8) & 0xff;
12773 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12775 *immbits
= (immlo
>> 16) & 0xff;
12779 if ((immlo
& 0xffff) != (immlo
>> 16))
12786 if (immlo
== (immlo
& 0x000000ff))
12791 else if (immlo
== (immlo
& 0x0000ff00))
12793 *immbits
= immlo
>> 8;
12797 if ((immlo
& 0xff) != (immlo
>> 8))
12802 if (immlo
== (immlo
& 0x000000ff))
12804 /* Don't allow MVN with 8-bit immediate. */
12814 /* Write immediate bits [7:0] to the following locations:
12816 |28/24|23 19|18 16|15 4|3 0|
12817 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12819 This function is used by VMOV/VMVN/VORR/VBIC. */
12822 neon_write_immbits (unsigned immbits
)
12824 inst
.instruction
|= immbits
& 0xf;
12825 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12826 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12829 /* Invert low-order SIZE bits of XHI:XLO. */
12832 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12834 unsigned immlo
= xlo
? *xlo
: 0;
12835 unsigned immhi
= xhi
? *xhi
: 0;
12840 immlo
= (~immlo
) & 0xff;
12844 immlo
= (~immlo
) & 0xffff;
12848 immhi
= (~immhi
) & 0xffffffff;
12849 /* fall through. */
12852 immlo
= (~immlo
) & 0xffffffff;
12867 do_neon_logic (void)
12869 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12871 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12872 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12873 /* U bit and size field were set as part of the bitmask. */
12874 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12875 neon_three_same (neon_quad (rs
), 0, -1);
12879 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12880 struct neon_type_el et
= neon_check_type (2, rs
,
12881 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12882 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12886 if (et
.type
== NT_invtype
)
12889 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12891 immbits
= inst
.operands
[1].imm
;
12894 /* .i64 is a pseudo-op, so the immediate must be a repeating
12896 if (immbits
!= (inst
.operands
[1].regisimm
?
12897 inst
.operands
[1].reg
: 0))
12899 /* Set immbits to an invalid constant. */
12900 immbits
= 0xdeadbeef;
12907 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12911 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12915 /* Pseudo-instruction for VBIC. */
12916 neon_invert_size (&immbits
, 0, et
.size
);
12917 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12921 /* Pseudo-instruction for VORR. */
12922 neon_invert_size (&immbits
, 0, et
.size
);
12923 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12933 inst
.instruction
|= neon_quad (rs
) << 6;
12934 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12935 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12936 inst
.instruction
|= cmode
<< 8;
12937 neon_write_immbits (immbits
);
12939 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12944 do_neon_bitfield (void)
12946 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12947 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12948 neon_three_same (neon_quad (rs
), 0, -1);
12952 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12955 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12956 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12958 if (et
.type
== NT_float
)
12960 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12961 neon_three_same (neon_quad (rs
), 0, -1);
12965 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12966 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12971 do_neon_dyadic_if_su (void)
12973 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12977 do_neon_dyadic_if_su_d (void)
12979 /* This version only allow D registers, but that constraint is enforced during
12980 operand parsing so we don't need to do anything extra here. */
12981 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12985 do_neon_dyadic_if_i_d (void)
12987 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12988 affected if we specify unsigned args. */
12989 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12992 enum vfp_or_neon_is_neon_bits
12995 NEON_CHECK_ARCH
= 2
12998 /* Call this function if an instruction which may have belonged to the VFP or
12999 Neon instruction sets, but turned out to be a Neon instruction (due to the
13000 operand types involved, etc.). We have to check and/or fix-up a couple of
13003 - Make sure the user hasn't attempted to make a Neon instruction
13005 - Alter the value in the condition code field if necessary.
13006 - Make sure that the arch supports Neon instructions.
13008 Which of these operations take place depends on bits from enum
13009 vfp_or_neon_is_neon_bits.
13011 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13012 current instruction's condition is COND_ALWAYS, the condition field is
13013 changed to inst.uncond_value. This is necessary because instructions shared
13014 between VFP and Neon may be conditional for the VFP variants only, and the
13015 unconditional Neon version must have, e.g., 0xF in the condition field. */
13018 vfp_or_neon_is_neon (unsigned check
)
13020 /* Conditions are always legal in Thumb mode (IT blocks). */
13021 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13023 if (inst
.cond
!= COND_ALWAYS
)
13025 first_error (_(BAD_COND
));
13028 if (inst
.uncond_value
!= -1)
13029 inst
.instruction
|= inst
.uncond_value
<< 28;
13032 if ((check
& NEON_CHECK_ARCH
)
13033 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13035 first_error (_(BAD_FPU
));
13043 do_neon_addsub_if_i (void)
13045 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13048 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13051 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13052 affected if we specify unsigned args. */
13053 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13056 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13058 V<op> A,B (A is operand 0, B is operand 2)
13063 so handle that case specially. */
13066 neon_exchange_operands (void)
13068 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13069 if (inst
.operands
[1].present
)
13071 /* Swap operands[1] and operands[2]. */
13072 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13073 inst
.operands
[1] = inst
.operands
[2];
13074 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13078 inst
.operands
[1] = inst
.operands
[2];
13079 inst
.operands
[2] = inst
.operands
[0];
13084 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13086 if (inst
.operands
[2].isreg
)
13089 neon_exchange_operands ();
13090 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13094 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13095 struct neon_type_el et
= neon_check_type (2, rs
,
13096 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13098 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13103 inst
.instruction
|= neon_quad (rs
) << 6;
13104 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13105 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13107 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13114 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13118 do_neon_cmp_inv (void)
13120 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13126 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13129 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13130 scalars, which are encoded in 5 bits, M : Rm.
13131 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13132 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13136 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13138 unsigned regno
= NEON_SCALAR_REG (scalar
);
13139 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13144 if (regno
> 7 || elno
> 3)
13146 return regno
| (elno
<< 3);
13149 if (regno
> 15 || elno
> 1)
13151 return regno
| (elno
<< 4);
13155 first_error (_("scalar out of range for multiply instruction"));
13161 /* Encode multiply / multiply-accumulate scalar instructions. */
13164 neon_mul_mac (struct neon_type_el et
, int ubit
)
13168 /* Give a more helpful error message if we have an invalid type. */
13169 if (et
.type
== NT_invtype
)
13172 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13177 inst
.instruction
|= LOW4 (scalar
);
13178 inst
.instruction
|= HI1 (scalar
) << 5;
13179 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13180 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13181 inst
.instruction
|= (ubit
!= 0) << 24;
13183 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13187 do_neon_mac_maybe_scalar (void)
13189 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13192 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13195 if (inst
.operands
[2].isscalar
)
13197 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13198 struct neon_type_el et
= neon_check_type (3, rs
,
13199 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13200 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13201 neon_mul_mac (et
, neon_quad (rs
));
13205 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13206 affected if we specify unsigned args. */
13207 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13212 do_neon_fmac (void)
13214 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13217 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13220 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13226 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13227 struct neon_type_el et
= neon_check_type (3, rs
,
13228 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13229 neon_three_same (neon_quad (rs
), 0, et
.size
);
13232 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13233 same types as the MAC equivalents. The polynomial type for this instruction
13234 is encoded the same as the integer type. */
13239 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13242 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13245 if (inst
.operands
[2].isscalar
)
13246 do_neon_mac_maybe_scalar ();
13248 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13252 do_neon_qdmulh (void)
13254 if (inst
.operands
[2].isscalar
)
13256 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13257 struct neon_type_el et
= neon_check_type (3, rs
,
13258 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13259 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13260 neon_mul_mac (et
, neon_quad (rs
));
13264 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13265 struct neon_type_el et
= neon_check_type (3, rs
,
13266 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13267 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13268 /* The U bit (rounding) comes from bit mask. */
13269 neon_three_same (neon_quad (rs
), 0, et
.size
);
13274 do_neon_fcmp_absolute (void)
13276 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13277 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13278 /* Size field comes from bit mask. */
13279 neon_three_same (neon_quad (rs
), 1, -1);
13283 do_neon_fcmp_absolute_inv (void)
13285 neon_exchange_operands ();
13286 do_neon_fcmp_absolute ();
13290 do_neon_step (void)
13292 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13293 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13294 neon_three_same (neon_quad (rs
), 0, -1);
13298 do_neon_abs_neg (void)
13300 enum neon_shape rs
;
13301 struct neon_type_el et
;
13303 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13306 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13309 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13310 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13312 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13313 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13314 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13315 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13316 inst
.instruction
|= neon_quad (rs
) << 6;
13317 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13318 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13320 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13326 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13327 struct neon_type_el et
= neon_check_type (2, rs
,
13328 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13329 int imm
= inst
.operands
[2].imm
;
13330 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13331 _("immediate out of range for insert"));
13332 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13338 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13339 struct neon_type_el et
= neon_check_type (2, rs
,
13340 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13341 int imm
= inst
.operands
[2].imm
;
13342 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13343 _("immediate out of range for insert"));
13344 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13348 do_neon_qshlu_imm (void)
13350 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13351 struct neon_type_el et
= neon_check_type (2, rs
,
13352 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13353 int imm
= inst
.operands
[2].imm
;
13354 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13355 _("immediate out of range for shift"));
13356 /* Only encodes the 'U present' variant of the instruction.
13357 In this case, signed types have OP (bit 8) set to 0.
13358 Unsigned types have OP set to 1. */
13359 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13360 /* The rest of the bits are the same as other immediate shifts. */
13361 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13365 do_neon_qmovn (void)
13367 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13368 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13369 /* Saturating move where operands can be signed or unsigned, and the
13370 destination has the same signedness. */
13371 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13372 if (et
.type
== NT_unsigned
)
13373 inst
.instruction
|= 0xc0;
13375 inst
.instruction
|= 0x80;
13376 neon_two_same (0, 1, et
.size
/ 2);
13380 do_neon_qmovun (void)
13382 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13383 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13384 /* Saturating move with unsigned results. Operands must be signed. */
13385 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13386 neon_two_same (0, 1, et
.size
/ 2);
13390 do_neon_rshift_sat_narrow (void)
13392 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13393 or unsigned. If operands are unsigned, results must also be unsigned. */
13394 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13395 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13396 int imm
= inst
.operands
[2].imm
;
13397 /* This gets the bounds check, size encoding and immediate bits calculation
13401 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13402 VQMOVN.I<size> <Dd>, <Qm>. */
13405 inst
.operands
[2].present
= 0;
13406 inst
.instruction
= N_MNEM_vqmovn
;
13411 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13412 _("immediate out of range"));
13413 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13417 do_neon_rshift_sat_narrow_u (void)
13419 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13420 or unsigned. If operands are unsigned, results must also be unsigned. */
13421 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13422 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13423 int imm
= inst
.operands
[2].imm
;
13424 /* This gets the bounds check, size encoding and immediate bits calculation
13428 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13429 VQMOVUN.I<size> <Dd>, <Qm>. */
13432 inst
.operands
[2].present
= 0;
13433 inst
.instruction
= N_MNEM_vqmovun
;
13438 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13439 _("immediate out of range"));
13440 /* FIXME: The manual is kind of unclear about what value U should have in
13441 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13443 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13447 do_neon_movn (void)
13449 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13450 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13451 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13452 neon_two_same (0, 1, et
.size
/ 2);
13456 do_neon_rshift_narrow (void)
13458 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13459 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13460 int imm
= inst
.operands
[2].imm
;
13461 /* This gets the bounds check, size encoding and immediate bits calculation
13465 /* If immediate is zero then we are a pseudo-instruction for
13466 VMOVN.I<size> <Dd>, <Qm> */
13469 inst
.operands
[2].present
= 0;
13470 inst
.instruction
= N_MNEM_vmovn
;
13475 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13476 _("immediate out of range for narrowing operation"));
13477 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13481 do_neon_shll (void)
13483 /* FIXME: Type checking when lengthening. */
13484 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13485 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13486 unsigned imm
= inst
.operands
[2].imm
;
13488 if (imm
== et
.size
)
13490 /* Maximum shift variant. */
13491 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13492 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13493 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13494 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13495 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13496 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13498 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13502 /* A more-specific type check for non-max versions. */
13503 et
= neon_check_type (2, NS_QDI
,
13504 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13505 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13506 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13510 /* Check the various types for the VCVT instruction, and return which version
13511 the current instruction is. */
13514 neon_cvt_flavour (enum neon_shape rs
)
13516 #define CVT_VAR(C,X,Y) \
13517 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13518 if (et.type != NT_invtype) \
13520 inst.error = NULL; \
13523 struct neon_type_el et
;
13524 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13525 || rs
== NS_FF
) ? N_VFP
: 0;
13526 /* The instruction versions which take an immediate take one register
13527 argument, which is extended to the width of the full register. Thus the
13528 "source" and "destination" registers must have the same width. Hack that
13529 here by making the size equal to the key (wider, in this case) operand. */
13530 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13532 CVT_VAR (0, N_S32
, N_F32
);
13533 CVT_VAR (1, N_U32
, N_F32
);
13534 CVT_VAR (2, N_F32
, N_S32
);
13535 CVT_VAR (3, N_F32
, N_U32
);
13536 /* Half-precision conversions. */
13537 CVT_VAR (4, N_F32
, N_F16
);
13538 CVT_VAR (5, N_F16
, N_F32
);
13542 /* VFP instructions. */
13543 CVT_VAR (6, N_F32
, N_F64
);
13544 CVT_VAR (7, N_F64
, N_F32
);
13545 CVT_VAR (8, N_S32
, N_F64
| key
);
13546 CVT_VAR (9, N_U32
, N_F64
| key
);
13547 CVT_VAR (10, N_F64
| key
, N_S32
);
13548 CVT_VAR (11, N_F64
| key
, N_U32
);
13549 /* VFP instructions with bitshift. */
13550 CVT_VAR (12, N_F32
| key
, N_S16
);
13551 CVT_VAR (13, N_F32
| key
, N_U16
);
13552 CVT_VAR (14, N_F64
| key
, N_S16
);
13553 CVT_VAR (15, N_F64
| key
, N_U16
);
13554 CVT_VAR (16, N_S16
, N_F32
| key
);
13555 CVT_VAR (17, N_U16
, N_F32
| key
);
13556 CVT_VAR (18, N_S16
, N_F64
| key
);
13557 CVT_VAR (19, N_U16
, N_F64
| key
);
13563 /* Neon-syntax VFP conversions. */
13566 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13568 const char *opname
= 0;
13570 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13572 /* Conversions with immediate bitshift. */
13573 const char *enc
[] =
13597 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13599 opname
= enc
[flavour
];
13600 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13601 _("operands 0 and 1 must be the same register"));
13602 inst
.operands
[1] = inst
.operands
[2];
13603 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13608 /* Conversions without bitshift. */
13609 const char *enc
[] =
13625 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13626 opname
= enc
[flavour
];
13630 do_vfp_nsyn_opcode (opname
);
13634 do_vfp_nsyn_cvtz (void)
13636 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13637 int flavour
= neon_cvt_flavour (rs
);
13638 const char *enc
[] =
13652 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13653 do_vfp_nsyn_opcode (enc
[flavour
]);
13659 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13660 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13661 int flavour
= neon_cvt_flavour (rs
);
13663 /* VFP rather than Neon conversions. */
13666 do_vfp_nsyn_cvt (rs
, flavour
);
13676 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13678 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13681 /* Fixed-point conversion with #0 immediate is encoded as an
13682 integer conversion. */
13683 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13685 immbits
= 32 - inst
.operands
[2].imm
;
13686 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13688 inst
.instruction
|= enctab
[flavour
];
13689 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13690 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13691 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13692 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13693 inst
.instruction
|= neon_quad (rs
) << 6;
13694 inst
.instruction
|= 1 << 21;
13695 inst
.instruction
|= immbits
<< 16;
13697 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13705 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13707 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13709 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13713 inst
.instruction
|= enctab
[flavour
];
13715 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13716 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13717 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13718 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13719 inst
.instruction
|= neon_quad (rs
) << 6;
13720 inst
.instruction
|= 2 << 18;
13722 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13726 /* Half-precision conversions for Advanced SIMD -- neon. */
13731 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13733 as_bad (_("operand size must match register width"));
13738 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13740 as_bad (_("operand size must match register width"));
13745 inst
.instruction
= 0x3b60600;
13747 inst
.instruction
= 0x3b60700;
13749 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13750 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13751 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13753 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13757 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13758 do_vfp_nsyn_cvt (rs
, flavour
);
13763 do_neon_cvtb (void)
13765 inst
.instruction
= 0xeb20a40;
13767 /* The sizes are attached to the mnemonic. */
13768 if (inst
.vectype
.el
[0].type
!= NT_invtype
13769 && inst
.vectype
.el
[0].size
== 16)
13770 inst
.instruction
|= 0x00010000;
13772 /* Programmer's syntax: the sizes are attached to the operands. */
13773 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13774 && inst
.operands
[0].vectype
.size
== 16)
13775 inst
.instruction
|= 0x00010000;
13777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13778 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13779 do_vfp_cond_or_thumb ();
13784 do_neon_cvtt (void)
13787 inst
.instruction
|= 0x80;
13791 neon_move_immediate (void)
13793 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13794 struct neon_type_el et
= neon_check_type (2, rs
,
13795 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13796 unsigned immlo
, immhi
= 0, immbits
;
13797 int op
, cmode
, float_p
;
13799 constraint (et
.type
== NT_invtype
,
13800 _("operand size must be specified for immediate VMOV"));
13802 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13803 op
= (inst
.instruction
& (1 << 5)) != 0;
13805 immlo
= inst
.operands
[1].imm
;
13806 if (inst
.operands
[1].regisimm
)
13807 immhi
= inst
.operands
[1].reg
;
13809 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13810 _("immediate has bits set outside the operand size"));
13812 float_p
= inst
.operands
[1].immisfloat
;
13814 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13815 et
.size
, et
.type
)) == FAIL
)
13817 /* Invert relevant bits only. */
13818 neon_invert_size (&immlo
, &immhi
, et
.size
);
13819 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13820 with one or the other; those cases are caught by
13821 neon_cmode_for_move_imm. */
13823 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13824 &op
, et
.size
, et
.type
)) == FAIL
)
13826 first_error (_("immediate out of range"));
13831 inst
.instruction
&= ~(1 << 5);
13832 inst
.instruction
|= op
<< 5;
13834 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13835 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13836 inst
.instruction
|= neon_quad (rs
) << 6;
13837 inst
.instruction
|= cmode
<< 8;
13839 neon_write_immbits (immbits
);
13845 if (inst
.operands
[1].isreg
)
13847 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13849 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13850 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13851 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13852 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13853 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13854 inst
.instruction
|= neon_quad (rs
) << 6;
13858 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13859 neon_move_immediate ();
13862 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13865 /* Encode instructions of form:
13867 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13868 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13871 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13873 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13875 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13876 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13877 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13878 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13879 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13880 inst
.instruction
|= neon_logbits (size
) << 20;
13882 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13886 do_neon_dyadic_long (void)
13888 /* FIXME: Type checking for lengthening op. */
13889 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13890 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13891 neon_mixed_length (et
, et
.size
);
13895 do_neon_abal (void)
13897 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13898 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13899 neon_mixed_length (et
, et
.size
);
13903 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13905 if (inst
.operands
[2].isscalar
)
13907 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13908 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13909 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13910 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13914 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13915 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13916 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13917 neon_mixed_length (et
, et
.size
);
13922 do_neon_mac_maybe_scalar_long (void)
13924 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13928 do_neon_dyadic_wide (void)
13930 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13931 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13932 neon_mixed_length (et
, et
.size
);
13936 do_neon_dyadic_narrow (void)
13938 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13939 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13940 /* Operand sign is unimportant, and the U bit is part of the opcode,
13941 so force the operand type to integer. */
13942 et
.type
= NT_integer
;
13943 neon_mixed_length (et
, et
.size
/ 2);
13947 do_neon_mul_sat_scalar_long (void)
13949 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13953 do_neon_vmull (void)
13955 if (inst
.operands
[2].isscalar
)
13956 do_neon_mac_maybe_scalar_long ();
13959 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13960 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13961 if (et
.type
== NT_poly
)
13962 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13964 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13965 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13966 zero. Should be OK as-is. */
13967 neon_mixed_length (et
, et
.size
);
13974 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13975 struct neon_type_el et
= neon_check_type (3, rs
,
13976 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13977 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13979 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13980 _("shift out of range"));
13981 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13982 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13983 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13984 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13985 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13986 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13987 inst
.instruction
|= neon_quad (rs
) << 6;
13988 inst
.instruction
|= imm
<< 8;
13990 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13996 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13997 struct neon_type_el et
= neon_check_type (2, rs
,
13998 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13999 unsigned op
= (inst
.instruction
>> 7) & 3;
14000 /* N (width of reversed regions) is encoded as part of the bitmask. We
14001 extract it here to check the elements to be reversed are smaller.
14002 Otherwise we'd get a reserved instruction. */
14003 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14004 gas_assert (elsize
!= 0);
14005 constraint (et
.size
>= elsize
,
14006 _("elements must be smaller than reversal region"));
14007 neon_two_same (neon_quad (rs
), 1, et
.size
);
14013 if (inst
.operands
[1].isscalar
)
14015 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14016 struct neon_type_el et
= neon_check_type (2, rs
,
14017 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14018 unsigned sizebits
= et
.size
>> 3;
14019 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14020 int logsize
= neon_logbits (et
.size
);
14021 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14023 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14026 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
14027 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14028 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14029 inst
.instruction
|= LOW4 (dm
);
14030 inst
.instruction
|= HI1 (dm
) << 5;
14031 inst
.instruction
|= neon_quad (rs
) << 6;
14032 inst
.instruction
|= x
<< 17;
14033 inst
.instruction
|= sizebits
<< 16;
14035 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14039 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14040 struct neon_type_el et
= neon_check_type (2, rs
,
14041 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14042 /* Duplicate ARM register to lanes of vector. */
14043 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
14046 case 8: inst
.instruction
|= 0x400000; break;
14047 case 16: inst
.instruction
|= 0x000020; break;
14048 case 32: inst
.instruction
|= 0x000000; break;
14051 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14054 inst
.instruction
|= neon_quad (rs
) << 21;
14055 /* The encoding for this instruction is identical for the ARM and Thumb
14056 variants, except for the condition field. */
14057 do_vfp_cond_or_thumb ();
14061 /* VMOV has particularly many variations. It can be one of:
14062 0. VMOV<c><q> <Qd>, <Qm>
14063 1. VMOV<c><q> <Dd>, <Dm>
14064 (Register operations, which are VORR with Rm = Rn.)
14065 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14066 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14068 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14069 (ARM register to scalar.)
14070 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14071 (Two ARM registers to vector.)
14072 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14073 (Scalar to ARM register.)
14074 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14075 (Vector to two ARM registers.)
14076 8. VMOV.F32 <Sd>, <Sm>
14077 9. VMOV.F64 <Dd>, <Dm>
14078 (VFP register moves.)
14079 10. VMOV.F32 <Sd>, #imm
14080 11. VMOV.F64 <Dd>, #imm
14081 (VFP float immediate load.)
14082 12. VMOV <Rd>, <Sm>
14083 (VFP single to ARM reg.)
14084 13. VMOV <Sd>, <Rm>
14085 (ARM reg to VFP single.)
14086 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14087 (Two ARM regs to two VFP singles.)
14088 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14089 (Two VFP singles to two ARM regs.)
14091 These cases can be disambiguated using neon_select_shape, except cases 1/9
14092 and 3/11 which depend on the operand type too.
14094 All the encoded bits are hardcoded by this function.
14096 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14097 Cases 5, 7 may be used with VFPv2 and above.
14099 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14100 can specify a type where it doesn't make sense to, and is ignored). */
14105 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14106 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14108 struct neon_type_el et
;
14109 const char *ldconst
= 0;
14113 case NS_DD
: /* case 1/9. */
14114 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14115 /* It is not an error here if no type is given. */
14117 if (et
.type
== NT_float
&& et
.size
== 64)
14119 do_vfp_nsyn_opcode ("fcpyd");
14122 /* fall through. */
14124 case NS_QQ
: /* case 0/1. */
14126 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14128 /* The architecture manual I have doesn't explicitly state which
14129 value the U bit should have for register->register moves, but
14130 the equivalent VORR instruction has U = 0, so do that. */
14131 inst
.instruction
= 0x0200110;
14132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14136 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14137 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14138 inst
.instruction
|= neon_quad (rs
) << 6;
14140 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14144 case NS_DI
: /* case 3/11. */
14145 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14147 if (et
.type
== NT_float
&& et
.size
== 64)
14149 /* case 11 (fconstd). */
14150 ldconst
= "fconstd";
14151 goto encode_fconstd
;
14153 /* fall through. */
14155 case NS_QI
: /* case 2/3. */
14156 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14158 inst
.instruction
= 0x0800010;
14159 neon_move_immediate ();
14160 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14163 case NS_SR
: /* case 4. */
14165 unsigned bcdebits
= 0;
14166 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14167 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14168 int logsize
= neon_logbits (et
.size
);
14169 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14170 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14174 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14175 && et
.size
!= 32, _(BAD_FPU
));
14176 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14177 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14181 case 8: bcdebits
= 0x8; break;
14182 case 16: bcdebits
= 0x1; break;
14183 case 32: bcdebits
= 0x0; break;
14187 bcdebits
|= x
<< logsize
;
14189 inst
.instruction
= 0xe000b10;
14190 do_vfp_cond_or_thumb ();
14191 inst
.instruction
|= LOW4 (dn
) << 16;
14192 inst
.instruction
|= HI1 (dn
) << 7;
14193 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14194 inst
.instruction
|= (bcdebits
& 3) << 5;
14195 inst
.instruction
|= (bcdebits
>> 2) << 21;
14199 case NS_DRR
: /* case 5 (fmdrr). */
14200 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14203 inst
.instruction
= 0xc400b10;
14204 do_vfp_cond_or_thumb ();
14205 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14206 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14207 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14208 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14211 case NS_RS
: /* case 6. */
14213 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14214 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14215 unsigned logsize
= neon_logbits (et
.size
);
14216 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14217 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14218 unsigned abcdebits
= 0;
14220 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14222 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14223 && et
.size
!= 32, _(BAD_FPU
));
14224 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14225 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14229 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14230 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14231 case 32: abcdebits
= 0x00; break;
14235 abcdebits
|= x
<< logsize
;
14236 inst
.instruction
= 0xe100b10;
14237 do_vfp_cond_or_thumb ();
14238 inst
.instruction
|= LOW4 (dn
) << 16;
14239 inst
.instruction
|= HI1 (dn
) << 7;
14240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14241 inst
.instruction
|= (abcdebits
& 3) << 5;
14242 inst
.instruction
|= (abcdebits
>> 2) << 21;
14246 case NS_RRD
: /* case 7 (fmrrd). */
14247 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14250 inst
.instruction
= 0xc500b10;
14251 do_vfp_cond_or_thumb ();
14252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14254 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14255 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14258 case NS_FF
: /* case 8 (fcpys). */
14259 do_vfp_nsyn_opcode ("fcpys");
14262 case NS_FI
: /* case 10 (fconsts). */
14263 ldconst
= "fconsts";
14265 if (is_quarter_float (inst
.operands
[1].imm
))
14267 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14268 do_vfp_nsyn_opcode (ldconst
);
14271 first_error (_("immediate out of range"));
14274 case NS_RF
: /* case 12 (fmrs). */
14275 do_vfp_nsyn_opcode ("fmrs");
14278 case NS_FR
: /* case 13 (fmsr). */
14279 do_vfp_nsyn_opcode ("fmsr");
14282 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14283 (one of which is a list), but we have parsed four. Do some fiddling to
14284 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14286 case NS_RRFF
: /* case 14 (fmrrs). */
14287 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14288 _("VFP registers must be adjacent"));
14289 inst
.operands
[2].imm
= 2;
14290 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14291 do_vfp_nsyn_opcode ("fmrrs");
14294 case NS_FFRR
: /* case 15 (fmsrr). */
14295 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14296 _("VFP registers must be adjacent"));
14297 inst
.operands
[1] = inst
.operands
[2];
14298 inst
.operands
[2] = inst
.operands
[3];
14299 inst
.operands
[0].imm
= 2;
14300 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14301 do_vfp_nsyn_opcode ("fmsrr");
14310 do_neon_rshift_round_imm (void)
14312 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14313 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14314 int imm
= inst
.operands
[2].imm
;
14316 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14319 inst
.operands
[2].present
= 0;
14324 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14325 _("immediate out of range for shift"));
14326 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14331 do_neon_movl (void)
14333 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14334 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14335 unsigned sizebits
= et
.size
>> 3;
14336 inst
.instruction
|= sizebits
<< 19;
14337 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14343 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14344 struct neon_type_el et
= neon_check_type (2, rs
,
14345 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14346 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14347 neon_two_same (neon_quad (rs
), 1, et
.size
);
14351 do_neon_zip_uzp (void)
14353 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14354 struct neon_type_el et
= neon_check_type (2, rs
,
14355 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14356 if (rs
== NS_DD
&& et
.size
== 32)
14358 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14359 inst
.instruction
= N_MNEM_vtrn
;
14363 neon_two_same (neon_quad (rs
), 1, et
.size
);
14367 do_neon_sat_abs_neg (void)
14369 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14370 struct neon_type_el et
= neon_check_type (2, rs
,
14371 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14372 neon_two_same (neon_quad (rs
), 1, et
.size
);
14376 do_neon_pair_long (void)
14378 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14379 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14380 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14381 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14382 neon_two_same (neon_quad (rs
), 1, et
.size
);
14386 do_neon_recip_est (void)
14388 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14389 struct neon_type_el et
= neon_check_type (2, rs
,
14390 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14391 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14392 neon_two_same (neon_quad (rs
), 1, et
.size
);
14398 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14399 struct neon_type_el et
= neon_check_type (2, rs
,
14400 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14401 neon_two_same (neon_quad (rs
), 1, et
.size
);
14407 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14408 struct neon_type_el et
= neon_check_type (2, rs
,
14409 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14410 neon_two_same (neon_quad (rs
), 1, et
.size
);
14416 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14417 struct neon_type_el et
= neon_check_type (2, rs
,
14418 N_EQK
| N_INT
, N_8
| N_KEY
);
14419 neon_two_same (neon_quad (rs
), 1, et
.size
);
14425 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14426 neon_two_same (neon_quad (rs
), 1, -1);
14430 do_neon_tbl_tbx (void)
14432 unsigned listlenbits
;
14433 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14435 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14437 first_error (_("bad list length for table lookup"));
14441 listlenbits
= inst
.operands
[1].imm
- 1;
14442 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14443 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14444 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14445 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14446 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14447 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14448 inst
.instruction
|= listlenbits
<< 8;
14450 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14454 do_neon_ldm_stm (void)
14456 /* P, U and L bits are part of bitmask. */
14457 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14458 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14460 if (inst
.operands
[1].issingle
)
14462 do_vfp_nsyn_ldm_stm (is_dbmode
);
14466 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14467 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14469 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14470 _("register list must contain at least 1 and at most 16 "
14473 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14474 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14475 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14476 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14478 inst
.instruction
|= offsetbits
;
14480 do_vfp_cond_or_thumb ();
14484 do_neon_ldr_str (void)
14486 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14488 if (inst
.operands
[0].issingle
)
14491 do_vfp_nsyn_opcode ("flds");
14493 do_vfp_nsyn_opcode ("fsts");
14498 do_vfp_nsyn_opcode ("fldd");
14500 do_vfp_nsyn_opcode ("fstd");
14504 /* "interleave" version also handles non-interleaving register VLD1/VST1
14508 do_neon_ld_st_interleave (void)
14510 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14511 N_8
| N_16
| N_32
| N_64
);
14512 unsigned alignbits
= 0;
14514 /* The bits in this table go:
14515 0: register stride of one (0) or two (1)
14516 1,2: register list length, minus one (1, 2, 3, 4).
14517 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14518 We use -1 for invalid entries. */
14519 const int typetable
[] =
14521 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14522 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14523 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14524 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14528 if (et
.type
== NT_invtype
)
14531 if (inst
.operands
[1].immisalign
)
14532 switch (inst
.operands
[1].imm
>> 8)
14534 case 64: alignbits
= 1; break;
14536 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14537 goto bad_alignment
;
14541 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14542 goto bad_alignment
;
14547 first_error (_("bad alignment"));
14551 inst
.instruction
|= alignbits
<< 4;
14552 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14554 /* Bits [4:6] of the immediate in a list specifier encode register stride
14555 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14556 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14557 up the right value for "type" in a table based on this value and the given
14558 list style, then stick it back. */
14559 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14560 | (((inst
.instruction
>> 8) & 3) << 3);
14562 typebits
= typetable
[idx
];
14564 constraint (typebits
== -1, _("bad list type for instruction"));
14566 inst
.instruction
&= ~0xf00;
14567 inst
.instruction
|= typebits
<< 8;
14570 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14571 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14572 otherwise. The variable arguments are a list of pairs of legal (size, align)
14573 values, terminated with -1. */
14576 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14579 int result
= FAIL
, thissize
, thisalign
;
14581 if (!inst
.operands
[1].immisalign
)
14587 va_start (ap
, do_align
);
14591 thissize
= va_arg (ap
, int);
14592 if (thissize
== -1)
14594 thisalign
= va_arg (ap
, int);
14596 if (size
== thissize
&& align
== thisalign
)
14599 while (result
!= SUCCESS
);
14603 if (result
== SUCCESS
)
14606 first_error (_("unsupported alignment for instruction"));
14612 do_neon_ld_st_lane (void)
14614 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14615 int align_good
, do_align
= 0;
14616 int logsize
= neon_logbits (et
.size
);
14617 int align
= inst
.operands
[1].imm
>> 8;
14618 int n
= (inst
.instruction
>> 8) & 3;
14619 int max_el
= 64 / et
.size
;
14621 if (et
.type
== NT_invtype
)
14624 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14625 _("bad list length"));
14626 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14627 _("scalar index out of range"));
14628 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14630 _("stride of 2 unavailable when element size is 8"));
14634 case 0: /* VLD1 / VST1. */
14635 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14637 if (align_good
== FAIL
)
14641 unsigned alignbits
= 0;
14644 case 16: alignbits
= 0x1; break;
14645 case 32: alignbits
= 0x3; break;
14648 inst
.instruction
|= alignbits
<< 4;
14652 case 1: /* VLD2 / VST2. */
14653 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14655 if (align_good
== FAIL
)
14658 inst
.instruction
|= 1 << 4;
14661 case 2: /* VLD3 / VST3. */
14662 constraint (inst
.operands
[1].immisalign
,
14663 _("can't use alignment with this instruction"));
14666 case 3: /* VLD4 / VST4. */
14667 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14668 16, 64, 32, 64, 32, 128, -1);
14669 if (align_good
== FAIL
)
14673 unsigned alignbits
= 0;
14676 case 8: alignbits
= 0x1; break;
14677 case 16: alignbits
= 0x1; break;
14678 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14681 inst
.instruction
|= alignbits
<< 4;
14688 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14689 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14690 inst
.instruction
|= 1 << (4 + logsize
);
14692 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14693 inst
.instruction
|= logsize
<< 10;
14696 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14699 do_neon_ld_dup (void)
14701 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14702 int align_good
, do_align
= 0;
14704 if (et
.type
== NT_invtype
)
14707 switch ((inst
.instruction
>> 8) & 3)
14709 case 0: /* VLD1. */
14710 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14711 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14712 &do_align
, 16, 16, 32, 32, -1);
14713 if (align_good
== FAIL
)
14715 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14718 case 2: inst
.instruction
|= 1 << 5; break;
14719 default: first_error (_("bad list length")); return;
14721 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14724 case 1: /* VLD2. */
14725 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14726 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14727 if (align_good
== FAIL
)
14729 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14730 _("bad list length"));
14731 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14732 inst
.instruction
|= 1 << 5;
14733 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14736 case 2: /* VLD3. */
14737 constraint (inst
.operands
[1].immisalign
,
14738 _("can't use alignment with this instruction"));
14739 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14740 _("bad list length"));
14741 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14742 inst
.instruction
|= 1 << 5;
14743 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14746 case 3: /* VLD4. */
14748 int align
= inst
.operands
[1].imm
>> 8;
14749 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14750 16, 64, 32, 64, 32, 128, -1);
14751 if (align_good
== FAIL
)
14753 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14754 _("bad list length"));
14755 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14756 inst
.instruction
|= 1 << 5;
14757 if (et
.size
== 32 && align
== 128)
14758 inst
.instruction
|= 0x3 << 6;
14760 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14767 inst
.instruction
|= do_align
<< 4;
14770 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14771 apart from bits [11:4]. */
14774 do_neon_ldx_stx (void)
14776 switch (NEON_LANE (inst
.operands
[0].imm
))
14778 case NEON_INTERLEAVE_LANES
:
14779 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14780 do_neon_ld_st_interleave ();
14783 case NEON_ALL_LANES
:
14784 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14789 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14790 do_neon_ld_st_lane ();
14793 /* L bit comes from bit mask. */
14794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14796 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14798 if (inst
.operands
[1].postind
)
14800 int postreg
= inst
.operands
[1].imm
& 0xf;
14801 constraint (!inst
.operands
[1].immisreg
,
14802 _("post-index must be a register"));
14803 constraint (postreg
== 0xd || postreg
== 0xf,
14804 _("bad register for post-index"));
14805 inst
.instruction
|= postreg
;
14807 else if (inst
.operands
[1].writeback
)
14809 inst
.instruction
|= 0xd;
14812 inst
.instruction
|= 0xf;
14815 inst
.instruction
|= 0xf9000000;
14817 inst
.instruction
|= 0xf4000000;
14820 /* Overall per-instruction processing. */
14822 /* We need to be able to fix up arbitrary expressions in some statements.
14823 This is so that we can handle symbols that are an arbitrary distance from
14824 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14825 which returns part of an address in a form which will be valid for
14826 a data instruction. We do this by pushing the expression into a symbol
14827 in the expr_section, and creating a fix for that. */
14830 fix_new_arm (fragS
* frag
,
14845 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14846 (enum bfd_reloc_code_real
) reloc
);
14850 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14851 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14855 /* Mark whether the fix is to a THUMB instruction, or an ARM
14857 new_fix
->tc_fix_data
= thumb_mode
;
14860 /* Create a frg for an instruction requiring relaxation. */
14862 output_relax_insn (void)
14868 /* The size of the instruction is unknown, so tie the debug info to the
14869 start of the instruction. */
14870 dwarf2_emit_insn (0);
14872 switch (inst
.reloc
.exp
.X_op
)
14875 sym
= inst
.reloc
.exp
.X_add_symbol
;
14876 offset
= inst
.reloc
.exp
.X_add_number
;
14880 offset
= inst
.reloc
.exp
.X_add_number
;
14883 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14887 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14888 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14889 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14892 /* Write a 32-bit thumb instruction to buf. */
14894 put_thumb32_insn (char * buf
, unsigned long insn
)
14896 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14897 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14901 output_inst (const char * str
)
14907 as_bad ("%s -- `%s'", inst
.error
, str
);
14912 output_relax_insn ();
14915 if (inst
.size
== 0)
14918 to
= frag_more (inst
.size
);
14919 /* PR 9814: Record the thumb mode into the current frag so that we know
14920 what type of NOP padding to use, if necessary. We override any previous
14921 setting so that if the mode has changed then the NOPS that we use will
14922 match the encoding of the last instruction in the frag. */
14923 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14925 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14927 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14928 put_thumb32_insn (to
, inst
.instruction
);
14930 else if (inst
.size
> INSN_SIZE
)
14932 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14933 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14934 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14937 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14939 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14940 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14941 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14944 dwarf2_emit_insn (inst
.size
);
14948 output_it_inst (int cond
, int mask
, char * to
)
14950 unsigned long instruction
= 0xbf00;
14953 instruction
|= mask
;
14954 instruction
|= cond
<< 4;
14958 to
= frag_more (2);
14960 dwarf2_emit_insn (2);
14964 md_number_to_chars (to
, instruction
, 2);
14969 /* Tag values used in struct asm_opcode's tag field. */
14972 OT_unconditional
, /* Instruction cannot be conditionalized.
14973 The ARM condition field is still 0xE. */
14974 OT_unconditionalF
, /* Instruction cannot be conditionalized
14975 and carries 0xF in its ARM condition field. */
14976 OT_csuffix
, /* Instruction takes a conditional suffix. */
14977 OT_csuffixF
, /* Some forms of the instruction take a conditional
14978 suffix, others place 0xF where the condition field
14980 OT_cinfix3
, /* Instruction takes a conditional infix,
14981 beginning at character index 3. (In
14982 unified mode, it becomes a suffix.) */
14983 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14984 tsts, cmps, cmns, and teqs. */
14985 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14986 character index 3, even in unified mode. Used for
14987 legacy instructions where suffix and infix forms
14988 may be ambiguous. */
14989 OT_csuf_or_in3
, /* Instruction takes either a conditional
14990 suffix or an infix at character index 3. */
14991 OT_odd_infix_unc
, /* This is the unconditional variant of an
14992 instruction that takes a conditional infix
14993 at an unusual position. In unified mode,
14994 this variant will accept a suffix. */
14995 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14996 are the conditional variants of instructions that
14997 take conditional infixes in unusual positions.
14998 The infix appears at character index
14999 (tag - OT_odd_infix_0). These are not accepted
15000 in unified mode. */
15003 /* Subroutine of md_assemble, responsible for looking up the primary
15004 opcode from the mnemonic the user wrote. STR points to the
15005 beginning of the mnemonic.
15007 This is not simply a hash table lookup, because of conditional
15008 variants. Most instructions have conditional variants, which are
15009 expressed with a _conditional affix_ to the mnemonic. If we were
15010 to encode each conditional variant as a literal string in the opcode
15011 table, it would have approximately 20,000 entries.
15013 Most mnemonics take this affix as a suffix, and in unified syntax,
15014 'most' is upgraded to 'all'. However, in the divided syntax, some
15015 instructions take the affix as an infix, notably the s-variants of
15016 the arithmetic instructions. Of those instructions, all but six
15017 have the infix appear after the third character of the mnemonic.
15019 Accordingly, the algorithm for looking up primary opcodes given
15022 1. Look up the identifier in the opcode table.
15023 If we find a match, go to step U.
15025 2. Look up the last two characters of the identifier in the
15026 conditions table. If we find a match, look up the first N-2
15027 characters of the identifier in the opcode table. If we
15028 find a match, go to step CE.
15030 3. Look up the fourth and fifth characters of the identifier in
15031 the conditions table. If we find a match, extract those
15032 characters from the identifier, and look up the remaining
15033 characters in the opcode table. If we find a match, go
15038 U. Examine the tag field of the opcode structure, in case this is
15039 one of the six instructions with its conditional infix in an
15040 unusual place. If it is, the tag tells us where to find the
15041 infix; look it up in the conditions table and set inst.cond
15042 accordingly. Otherwise, this is an unconditional instruction.
15043 Again set inst.cond accordingly. Return the opcode structure.
15045 CE. Examine the tag field to make sure this is an instruction that
15046 should receive a conditional suffix. If it is not, fail.
15047 Otherwise, set inst.cond from the suffix we already looked up,
15048 and return the opcode structure.
15050 CM. Examine the tag field to make sure this is an instruction that
15051 should receive a conditional infix after the third character.
15052 If it is not, fail. Otherwise, undo the edits to the current
15053 line of input and proceed as for case CE. */
15055 static const struct asm_opcode
*
15056 opcode_lookup (char **str
)
15060 const struct asm_opcode
*opcode
;
15061 const struct asm_cond
*cond
;
15064 /* Scan up to the end of the mnemonic, which must end in white space,
15065 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15066 for (base
= end
= *str
; *end
!= '\0'; end
++)
15067 if (*end
== ' ' || *end
== '.')
15073 /* Handle a possible width suffix and/or Neon type suffix. */
15078 /* The .w and .n suffixes are only valid if the unified syntax is in
15080 if (unified_syntax
&& end
[1] == 'w')
15082 else if (unified_syntax
&& end
[1] == 'n')
15087 inst
.vectype
.elems
= 0;
15089 *str
= end
+ offset
;
15091 if (end
[offset
] == '.')
15093 /* See if we have a Neon type suffix (possible in either unified or
15094 non-unified ARM syntax mode). */
15095 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15098 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15104 /* Look for unaffixed or special-case affixed mnemonic. */
15105 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15110 if (opcode
->tag
< OT_odd_infix_0
)
15112 inst
.cond
= COND_ALWAYS
;
15116 if (warn_on_deprecated
&& unified_syntax
)
15117 as_warn (_("conditional infixes are deprecated in unified syntax"));
15118 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15119 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15122 inst
.cond
= cond
->value
;
15126 /* Cannot have a conditional suffix on a mnemonic of less than two
15128 if (end
- base
< 3)
15131 /* Look for suffixed mnemonic. */
15133 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15134 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15136 if (opcode
&& cond
)
15139 switch (opcode
->tag
)
15141 case OT_cinfix3_legacy
:
15142 /* Ignore conditional suffixes matched on infix only mnemonics. */
15146 case OT_cinfix3_deprecated
:
15147 case OT_odd_infix_unc
:
15148 if (!unified_syntax
)
15150 /* else fall through */
15154 case OT_csuf_or_in3
:
15155 inst
.cond
= cond
->value
;
15158 case OT_unconditional
:
15159 case OT_unconditionalF
:
15161 inst
.cond
= cond
->value
;
15164 /* Delayed diagnostic. */
15165 inst
.error
= BAD_COND
;
15166 inst
.cond
= COND_ALWAYS
;
15175 /* Cannot have a usual-position infix on a mnemonic of less than
15176 six characters (five would be a suffix). */
15177 if (end
- base
< 6)
15180 /* Look for infixed mnemonic in the usual position. */
15182 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15186 memcpy (save
, affix
, 2);
15187 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15188 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15190 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15191 memcpy (affix
, save
, 2);
15194 && (opcode
->tag
== OT_cinfix3
15195 || opcode
->tag
== OT_cinfix3_deprecated
15196 || opcode
->tag
== OT_csuf_or_in3
15197 || opcode
->tag
== OT_cinfix3_legacy
))
15200 if (warn_on_deprecated
&& unified_syntax
15201 && (opcode
->tag
== OT_cinfix3
15202 || opcode
->tag
== OT_cinfix3_deprecated
))
15203 as_warn (_("conditional infixes are deprecated in unified syntax"));
15205 inst
.cond
= cond
->value
;
15212 /* This function generates an initial IT instruction, leaving its block
15213 virtually open for the new instructions. Eventually,
15214 the mask will be updated by now_it_add_mask () each time
15215 a new instruction needs to be included in the IT block.
15216 Finally, the block is closed with close_automatic_it_block ().
15217 The block closure can be requested either from md_assemble (),
15218 a tencode (), or due to a label hook. */
15221 new_automatic_it_block (int cond
)
15223 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15224 now_it
.mask
= 0x18;
15226 now_it
.block_length
= 1;
15227 mapping_state (MAP_THUMB
);
15228 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15231 /* Close an automatic IT block.
15232 See comments in new_automatic_it_block (). */
15235 close_automatic_it_block (void)
15237 now_it
.mask
= 0x10;
15238 now_it
.block_length
= 0;
15241 /* Update the mask of the current automatically-generated IT
15242 instruction. See comments in new_automatic_it_block (). */
15245 now_it_add_mask (int cond
)
15247 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15248 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15249 | ((bitvalue) << (nbit)))
15250 const int resulting_bit
= (cond
& 1);
15252 now_it
.mask
&= 0xf;
15253 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15255 (5 - now_it
.block_length
));
15256 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15258 ((5 - now_it
.block_length
) - 1) );
15259 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15262 #undef SET_BIT_VALUE
15265 /* The IT blocks handling machinery is accessed through the these functions:
15266 it_fsm_pre_encode () from md_assemble ()
15267 set_it_insn_type () optional, from the tencode functions
15268 set_it_insn_type_last () ditto
15269 in_it_block () ditto
15270 it_fsm_post_encode () from md_assemble ()
15271 force_automatic_it_block_close () from label habdling functions
15274 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15275 initializing the IT insn type with a generic initial value depending
15276 on the inst.condition.
15277 2) During the tencode function, two things may happen:
15278 a) The tencode function overrides the IT insn type by
15279 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15280 b) The tencode function queries the IT block state by
15281 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15283 Both set_it_insn_type and in_it_block run the internal FSM state
15284 handling function (handle_it_state), because: a) setting the IT insn
15285 type may incur in an invalid state (exiting the function),
15286 and b) querying the state requires the FSM to be updated.
15287 Specifically we want to avoid creating an IT block for conditional
15288 branches, so it_fsm_pre_encode is actually a guess and we can't
15289 determine whether an IT block is required until the tencode () routine
15290 has decided what type of instruction this actually it.
15291 Because of this, if set_it_insn_type and in_it_block have to be used,
15292 set_it_insn_type has to be called first.
15294 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15295 determines the insn IT type depending on the inst.cond code.
15296 When a tencode () routine encodes an instruction that can be
15297 either outside an IT block, or, in the case of being inside, has to be
15298 the last one, set_it_insn_type_last () will determine the proper
15299 IT instruction type based on the inst.cond code. Otherwise,
15300 set_it_insn_type can be called for overriding that logic or
15301 for covering other cases.
15303 Calling handle_it_state () may not transition the IT block state to
15304 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15305 still queried. Instead, if the FSM determines that the state should
15306 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15307 after the tencode () function: that's what it_fsm_post_encode () does.
15309 Since in_it_block () calls the state handling function to get an
15310 updated state, an error may occur (due to invalid insns combination).
15311 In that case, inst.error is set.
15312 Therefore, inst.error has to be checked after the execution of
15313 the tencode () routine.
15315 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15316 any pending state change (if any) that didn't take place in
15317 handle_it_state () as explained above. */
15320 it_fsm_pre_encode (void)
15322 if (inst
.cond
!= COND_ALWAYS
)
15323 inst
.it_insn_type
= INSIDE_IT_INSN
;
15325 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15327 now_it
.state_handled
= 0;
15330 /* IT state FSM handling function. */
15333 handle_it_state (void)
15335 now_it
.state_handled
= 1;
15337 switch (now_it
.state
)
15339 case OUTSIDE_IT_BLOCK
:
15340 switch (inst
.it_insn_type
)
15342 case OUTSIDE_IT_INSN
:
15345 case INSIDE_IT_INSN
:
15346 case INSIDE_IT_LAST_INSN
:
15347 if (thumb_mode
== 0)
15350 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15351 as_tsktsk (_("Warning: conditional outside an IT block"\
15356 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15357 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15359 /* Automatically generate the IT instruction. */
15360 new_automatic_it_block (inst
.cond
);
15361 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15362 close_automatic_it_block ();
15366 inst
.error
= BAD_OUT_IT
;
15372 case IF_INSIDE_IT_LAST_INSN
:
15373 case NEUTRAL_IT_INSN
:
15377 now_it
.state
= MANUAL_IT_BLOCK
;
15378 now_it
.block_length
= 0;
15383 case AUTOMATIC_IT_BLOCK
:
15384 /* Three things may happen now:
15385 a) We should increment current it block size;
15386 b) We should close current it block (closing insn or 4 insns);
15387 c) We should close current it block and start a new one (due
15388 to incompatible conditions or
15389 4 insns-length block reached). */
15391 switch (inst
.it_insn_type
)
15393 case OUTSIDE_IT_INSN
:
15394 /* The closure of the block shall happen immediatelly,
15395 so any in_it_block () call reports the block as closed. */
15396 force_automatic_it_block_close ();
15399 case INSIDE_IT_INSN
:
15400 case INSIDE_IT_LAST_INSN
:
15401 case IF_INSIDE_IT_LAST_INSN
:
15402 now_it
.block_length
++;
15404 if (now_it
.block_length
> 4
15405 || !now_it_compatible (inst
.cond
))
15407 force_automatic_it_block_close ();
15408 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15409 new_automatic_it_block (inst
.cond
);
15413 now_it_add_mask (inst
.cond
);
15416 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15417 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15418 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15419 close_automatic_it_block ();
15422 case NEUTRAL_IT_INSN
:
15423 now_it
.block_length
++;
15425 if (now_it
.block_length
> 4)
15426 force_automatic_it_block_close ();
15428 now_it_add_mask (now_it
.cc
& 1);
15432 close_automatic_it_block ();
15433 now_it
.state
= MANUAL_IT_BLOCK
;
15438 case MANUAL_IT_BLOCK
:
15440 /* Check conditional suffixes. */
15441 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15444 now_it
.mask
&= 0x1f;
15445 is_last
= (now_it
.mask
== 0x10);
15447 switch (inst
.it_insn_type
)
15449 case OUTSIDE_IT_INSN
:
15450 inst
.error
= BAD_NOT_IT
;
15453 case INSIDE_IT_INSN
:
15454 if (cond
!= inst
.cond
)
15456 inst
.error
= BAD_IT_COND
;
15461 case INSIDE_IT_LAST_INSN
:
15462 case IF_INSIDE_IT_LAST_INSN
:
15463 if (cond
!= inst
.cond
)
15465 inst
.error
= BAD_IT_COND
;
15470 inst
.error
= BAD_BRANCH
;
15475 case NEUTRAL_IT_INSN
:
15476 /* The BKPT instruction is unconditional even in an IT block. */
15480 inst
.error
= BAD_IT_IT
;
15491 it_fsm_post_encode (void)
15495 if (!now_it
.state_handled
)
15496 handle_it_state ();
15498 is_last
= (now_it
.mask
== 0x10);
15501 now_it
.state
= OUTSIDE_IT_BLOCK
;
15507 force_automatic_it_block_close (void)
15509 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15511 close_automatic_it_block ();
15512 now_it
.state
= OUTSIDE_IT_BLOCK
;
15520 if (!now_it
.state_handled
)
15521 handle_it_state ();
15523 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15527 md_assemble (char *str
)
15530 const struct asm_opcode
* opcode
;
15532 /* Align the previous label if needed. */
15533 if (last_label_seen
!= NULL
)
15535 symbol_set_frag (last_label_seen
, frag_now
);
15536 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15537 S_SET_SEGMENT (last_label_seen
, now_seg
);
15540 memset (&inst
, '\0', sizeof (inst
));
15541 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15543 opcode
= opcode_lookup (&p
);
15546 /* It wasn't an instruction, but it might be a register alias of
15547 the form alias .req reg, or a Neon .dn/.qn directive. */
15548 if (! create_register_alias (str
, p
)
15549 && ! create_neon_reg_alias (str
, p
))
15550 as_bad (_("bad instruction `%s'"), str
);
15555 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15556 as_warn (_("s suffix on comparison instruction is deprecated"));
15558 /* The value which unconditional instructions should have in place of the
15559 condition field. */
15560 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15564 arm_feature_set variant
;
15566 variant
= cpu_variant
;
15567 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15568 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15569 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15570 /* Check that this instruction is supported for this CPU. */
15571 if (!opcode
->tvariant
15572 || (thumb_mode
== 1
15573 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15575 as_bad (_("selected processor does not support `%s'"), str
);
15578 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15579 && opcode
->tencode
!= do_t_branch
)
15581 as_bad (_("Thumb does not support conditional execution"));
15585 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15587 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15588 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15589 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15591 /* Two things are addressed here.
15592 1) Implicit require narrow instructions on Thumb-1.
15593 This avoids relaxation accidentally introducing Thumb-2
15595 2) Reject wide instructions in non Thumb-2 cores. */
15596 if (inst
.size_req
== 0)
15598 else if (inst
.size_req
== 4)
15600 as_bad (_("selected processor does not support `%s'"), str
);
15606 inst
.instruction
= opcode
->tvalue
;
15608 if (!parse_operands (p
, opcode
->operands
))
15610 /* Prepare the it_insn_type for those encodings that don't set
15612 it_fsm_pre_encode ();
15614 opcode
->tencode ();
15616 it_fsm_post_encode ();
15619 if (!(inst
.error
|| inst
.relax
))
15621 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15622 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15623 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15625 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15630 /* Something has gone badly wrong if we try to relax a fixed size
15632 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15634 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15635 *opcode
->tvariant
);
15636 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15637 set those bits when Thumb-2 32-bit instructions are seen. ie.
15638 anything other than bl/blx and v6-M instructions.
15639 This is overly pessimistic for relaxable instructions. */
15640 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15642 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15643 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15644 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15649 mapping_state (MAP_THUMB
);
15652 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15656 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15657 is_bx
= (opcode
->aencode
== do_bx
);
15659 /* Check that this instruction is supported for this CPU. */
15660 if (!(is_bx
&& fix_v4bx
)
15661 && !(opcode
->avariant
&&
15662 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15664 as_bad (_("selected processor does not support `%s'"), str
);
15669 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15673 inst
.instruction
= opcode
->avalue
;
15674 if (opcode
->tag
== OT_unconditionalF
)
15675 inst
.instruction
|= 0xF << 28;
15677 inst
.instruction
|= inst
.cond
<< 28;
15678 inst
.size
= INSN_SIZE
;
15679 if (!parse_operands (p
, opcode
->operands
))
15681 it_fsm_pre_encode ();
15682 opcode
->aencode ();
15683 it_fsm_post_encode ();
15685 /* Arm mode bx is marked as both v4T and v5 because it's still required
15686 on a hypothetical non-thumb v5 core. */
15688 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15690 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15691 *opcode
->avariant
);
15694 mapping_state (MAP_ARM
);
15699 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15707 check_it_blocks_finished (void)
15712 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15713 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15714 == MANUAL_IT_BLOCK
)
15716 as_warn (_("section '%s' finished with an open IT block."),
15720 if (now_it
.state
== MANUAL_IT_BLOCK
)
15721 as_warn (_("file finished with an open IT block."));
15725 /* Various frobbings of labels and their addresses. */
15728 arm_start_line_hook (void)
15730 last_label_seen
= NULL
;
15734 arm_frob_label (symbolS
* sym
)
15736 last_label_seen
= sym
;
15738 ARM_SET_THUMB (sym
, thumb_mode
);
15740 #if defined OBJ_COFF || defined OBJ_ELF
15741 ARM_SET_INTERWORK (sym
, support_interwork
);
15744 force_automatic_it_block_close ();
15746 /* Note - do not allow local symbols (.Lxxx) to be labelled
15747 as Thumb functions. This is because these labels, whilst
15748 they exist inside Thumb code, are not the entry points for
15749 possible ARM->Thumb calls. Also, these labels can be used
15750 as part of a computed goto or switch statement. eg gcc
15751 can generate code that looks like this:
15753 ldr r2, [pc, .Laaa]
15763 The first instruction loads the address of the jump table.
15764 The second instruction converts a table index into a byte offset.
15765 The third instruction gets the jump address out of the table.
15766 The fourth instruction performs the jump.
15768 If the address stored at .Laaa is that of a symbol which has the
15769 Thumb_Func bit set, then the linker will arrange for this address
15770 to have the bottom bit set, which in turn would mean that the
15771 address computation performed by the third instruction would end
15772 up with the bottom bit set. Since the ARM is capable of unaligned
15773 word loads, the instruction would then load the incorrect address
15774 out of the jump table, and chaos would ensue. */
15775 if (label_is_thumb_function_name
15776 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15777 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15779 /* When the address of a Thumb function is taken the bottom
15780 bit of that address should be set. This will allow
15781 interworking between Arm and Thumb functions to work
15784 THUMB_SET_FUNC (sym
, 1);
15786 label_is_thumb_function_name
= FALSE
;
15789 dwarf2_emit_label (sym
);
15793 arm_data_in_code (void)
15795 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15797 *input_line_pointer
= '/';
15798 input_line_pointer
+= 5;
15799 *input_line_pointer
= 0;
15807 arm_canonicalize_symbol_name (char * name
)
15811 if (thumb_mode
&& (len
= strlen (name
)) > 5
15812 && streq (name
+ len
- 5, "/data"))
15813 *(name
+ len
- 5) = 0;
15818 /* Table of all register names defined by default. The user can
15819 define additional names with .req. Note that all register names
15820 should appear in both upper and lowercase variants. Some registers
15821 also have mixed-case names. */
15823 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15824 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15825 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15826 #define REGSET(p,t) \
15827 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15828 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15829 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15830 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15831 #define REGSETH(p,t) \
15832 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15833 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15834 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15835 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15836 #define REGSET2(p,t) \
15837 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15838 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15839 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15840 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15842 static const struct reg_entry reg_names
[] =
15844 /* ARM integer registers. */
15845 REGSET(r
, RN
), REGSET(R
, RN
),
15847 /* ATPCS synonyms. */
15848 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15849 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15850 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15852 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15853 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15854 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15856 /* Well-known aliases. */
15857 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15858 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15860 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15861 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15863 /* Coprocessor numbers. */
15864 REGSET(p
, CP
), REGSET(P
, CP
),
15866 /* Coprocessor register numbers. The "cr" variants are for backward
15868 REGSET(c
, CN
), REGSET(C
, CN
),
15869 REGSET(cr
, CN
), REGSET(CR
, CN
),
15871 /* FPA registers. */
15872 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15873 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15875 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15876 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15878 /* VFP SP registers. */
15879 REGSET(s
,VFS
), REGSET(S
,VFS
),
15880 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15882 /* VFP DP Registers. */
15883 REGSET(d
,VFD
), REGSET(D
,VFD
),
15884 /* Extra Neon DP registers. */
15885 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15887 /* Neon QP registers. */
15888 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15890 /* VFP control registers. */
15891 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15892 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15893 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15894 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15895 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15896 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15898 /* Maverick DSP coprocessor registers. */
15899 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15900 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15902 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15903 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15904 REGDEF(dspsc
,0,DSPSC
),
15906 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15907 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15908 REGDEF(DSPSC
,0,DSPSC
),
15910 /* iWMMXt data registers - p0, c0-15. */
15911 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15913 /* iWMMXt control registers - p1, c0-3. */
15914 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15915 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15916 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15917 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15919 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15920 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15921 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15922 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15923 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15925 /* XScale accumulator registers. */
15926 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15932 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15933 within psr_required_here. */
15934 static const struct asm_psr psrs
[] =
15936 /* Backward compatibility notation. Note that "all" is no longer
15937 truly all possible PSR bits. */
15938 {"all", PSR_c
| PSR_f
},
15942 /* Individual flags. */
15947 /* Combinations of flags. */
15948 {"fs", PSR_f
| PSR_s
},
15949 {"fx", PSR_f
| PSR_x
},
15950 {"fc", PSR_f
| PSR_c
},
15951 {"sf", PSR_s
| PSR_f
},
15952 {"sx", PSR_s
| PSR_x
},
15953 {"sc", PSR_s
| PSR_c
},
15954 {"xf", PSR_x
| PSR_f
},
15955 {"xs", PSR_x
| PSR_s
},
15956 {"xc", PSR_x
| PSR_c
},
15957 {"cf", PSR_c
| PSR_f
},
15958 {"cs", PSR_c
| PSR_s
},
15959 {"cx", PSR_c
| PSR_x
},
15960 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15961 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15962 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15963 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15964 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15965 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15966 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15967 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15968 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15969 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15970 {"scf", PSR_s
| PSR_c
| PSR_f
},
15971 {"scx", PSR_s
| PSR_c
| PSR_x
},
15972 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15973 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15974 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15975 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15976 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15977 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15978 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15979 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15980 {"csf", PSR_c
| PSR_s
| PSR_f
},
15981 {"csx", PSR_c
| PSR_s
| PSR_x
},
15982 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15983 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15984 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15985 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15986 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15987 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15988 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15989 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15990 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15991 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15992 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15993 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15994 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15995 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15996 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15997 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15998 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15999 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16000 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16001 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16002 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16003 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16004 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16005 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16006 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16007 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16010 /* Table of V7M psr names. */
16011 static const struct asm_psr v7m_psrs
[] =
16013 {"apsr", 0 }, {"APSR", 0 },
16014 {"iapsr", 1 }, {"IAPSR", 1 },
16015 {"eapsr", 2 }, {"EAPSR", 2 },
16016 {"psr", 3 }, {"PSR", 3 },
16017 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16018 {"ipsr", 5 }, {"IPSR", 5 },
16019 {"epsr", 6 }, {"EPSR", 6 },
16020 {"iepsr", 7 }, {"IEPSR", 7 },
16021 {"msp", 8 }, {"MSP", 8 },
16022 {"psp", 9 }, {"PSP", 9 },
16023 {"primask", 16}, {"PRIMASK", 16},
16024 {"basepri", 17}, {"BASEPRI", 17},
16025 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16026 {"faultmask", 19}, {"FAULTMASK", 19},
16027 {"control", 20}, {"CONTROL", 20}
16030 /* Table of all shift-in-operand names. */
16031 static const struct asm_shift_name shift_names
[] =
16033 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16034 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16035 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16036 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16037 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16038 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16041 /* Table of all explicit relocation names. */
16043 static struct reloc_entry reloc_names
[] =
16045 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16046 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16047 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16048 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16049 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16050 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16051 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16052 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16053 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16054 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16055 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
16059 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16060 static const struct asm_cond conds
[] =
16064 {"cs", 0x2}, {"hs", 0x2},
16065 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16079 static struct asm_barrier_opt barrier_opt_names
[] =
16087 /* Table of ARM-format instructions. */
16089 /* Macros for gluing together operand strings. N.B. In all cases
16090 other than OPS0, the trailing OP_stop comes from default
16091 zero-initialization of the unspecified elements of the array. */
16092 #define OPS0() { OP_stop, }
16093 #define OPS1(a) { OP_##a, }
16094 #define OPS2(a,b) { OP_##a,OP_##b, }
16095 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16096 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16097 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16098 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16100 /* These macros abstract out the exact format of the mnemonic table and
16101 save some repeated characters. */
16103 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16104 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16105 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16106 THUMB_VARIANT, do_##ae, do_##te }
16108 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16109 a T_MNEM_xyz enumerator. */
16110 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16111 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16112 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16113 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16115 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16116 infix after the third character. */
16117 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16118 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16119 THUMB_VARIANT, do_##ae, do_##te }
16120 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16121 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16122 THUMB_VARIANT, do_##ae, do_##te }
16123 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16124 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16125 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16126 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16127 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16128 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16129 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16130 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16132 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16133 appear in the condition table. */
16134 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16135 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16136 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16138 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16139 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16140 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16141 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16142 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16143 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16144 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16145 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16146 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16147 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16148 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16149 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16150 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16151 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16152 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16153 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16154 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16155 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16156 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16157 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16159 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16160 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16161 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16162 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16164 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16165 field is still 0xE. Many of the Thumb variants can be executed
16166 conditionally, so this is checked separately. */
16167 #define TUE(mnem, op, top, nops, ops, ae, te) \
16168 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16169 THUMB_VARIANT, do_##ae, do_##te }
16171 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16172 condition code field. */
16173 #define TUF(mnem, op, top, nops, ops, ae, te) \
16174 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16175 THUMB_VARIANT, do_##ae, do_##te }
16177 /* ARM-only variants of all the above. */
16178 #define CE(mnem, op, nops, ops, ae) \
16179 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16181 #define C3(mnem, op, nops, ops, ae) \
16182 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16184 /* Legacy mnemonics that always have conditional infix after the third
16186 #define CL(mnem, op, nops, ops, ae) \
16187 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16188 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16190 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16191 #define cCE(mnem, op, nops, ops, ae) \
16192 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16194 /* Legacy coprocessor instructions where conditional infix and conditional
16195 suffix are ambiguous. For consistency this includes all FPA instructions,
16196 not just the potentially ambiguous ones. */
16197 #define cCL(mnem, op, nops, ops, ae) \
16198 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16199 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16201 /* Coprocessor, takes either a suffix or a position-3 infix
16202 (for an FPA corner case). */
16203 #define C3E(mnem, op, nops, ops, ae) \
16204 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16205 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16207 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16208 { m1 #m2 m3, OPS##nops ops, \
16209 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16210 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16212 #define CM(m1, m2, op, nops, ops, ae) \
16213 xCM_ (m1, , m2, op, nops, ops, ae), \
16214 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16215 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16216 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16217 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16218 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16219 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16220 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16221 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16222 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16223 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16224 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16225 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16226 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16227 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16228 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16229 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16230 xCM_ (m1, le, m2, op, nops, ops, ae), \
16231 xCM_ (m1, al, m2, op, nops, ops, ae)
16233 #define UE(mnem, op, nops, ops, ae) \
16234 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16236 #define UF(mnem, op, nops, ops, ae) \
16237 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16239 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16240 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16241 use the same encoding function for each. */
16242 #define NUF(mnem, op, nops, ops, enc) \
16243 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16244 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16246 /* Neon data processing, version which indirects through neon_enc_tab for
16247 the various overloaded versions of opcodes. */
16248 #define nUF(mnem, op, nops, ops, enc) \
16249 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16250 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16252 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16254 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16255 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16256 THUMB_VARIANT, do_##enc, do_##enc }
16258 #define NCE(mnem, op, nops, ops, enc) \
16259 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16261 #define NCEF(mnem, op, nops, ops, enc) \
16262 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16264 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16265 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16266 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16267 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16269 #define nCE(mnem, op, nops, ops, enc) \
16270 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16272 #define nCEF(mnem, op, nops, ops, enc) \
16273 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16277 /* Thumb-only, unconditional. */
16278 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16280 static const struct asm_opcode insns
[] =
16282 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16283 #define THUMB_VARIANT &arm_ext_v4t
16284 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16285 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16286 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16287 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16288 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16289 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16290 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16291 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16292 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16293 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16294 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16295 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16296 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16297 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16298 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16299 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16301 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16302 for setting PSR flag bits. They are obsolete in V6 and do not
16303 have Thumb equivalents. */
16304 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16305 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16306 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16307 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16308 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16309 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16310 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16311 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16312 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16314 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16315 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16316 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16317 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16319 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16320 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16321 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16322 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16324 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16325 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16326 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16327 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16328 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16329 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16331 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16332 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16333 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16334 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16337 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16338 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16339 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16341 /* Thumb-compatibility pseudo ops. */
16342 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16343 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16344 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16345 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16346 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16347 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16348 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16349 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16350 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16351 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16352 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16353 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16355 /* These may simplify to neg. */
16356 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16357 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16359 #undef THUMB_VARIANT
16360 #define THUMB_VARIANT & arm_ext_v6
16362 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16364 /* V1 instructions with no Thumb analogue prior to V6T2. */
16365 #undef THUMB_VARIANT
16366 #define THUMB_VARIANT & arm_ext_v6t2
16368 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16369 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16370 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16372 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16373 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16374 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16375 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16377 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16378 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16380 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16381 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16383 /* V1 instructions with no Thumb analogue at all. */
16384 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16385 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16387 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16388 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16389 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16390 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16391 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16392 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16393 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16394 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16397 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16398 #undef THUMB_VARIANT
16399 #define THUMB_VARIANT & arm_ext_v4t
16401 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16402 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16404 #undef THUMB_VARIANT
16405 #define THUMB_VARIANT & arm_ext_v6t2
16407 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16408 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16410 /* Generic coprocessor instructions. */
16411 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16412 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16413 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16414 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16415 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16416 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16417 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16420 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16422 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16423 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16426 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16427 #undef THUMB_VARIANT
16428 #define THUMB_VARIANT & arm_ext_msr
16430 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16431 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16434 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16435 #undef THUMB_VARIANT
16436 #define THUMB_VARIANT & arm_ext_v6t2
16438 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16439 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16440 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16441 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16442 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16443 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16444 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16445 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16448 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16449 #undef THUMB_VARIANT
16450 #define THUMB_VARIANT & arm_ext_v4t
16452 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16453 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16454 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16455 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16456 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16457 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16460 #define ARM_VARIANT & arm_ext_v4t_5
16462 /* ARM Architecture 4T. */
16463 /* Note: bx (and blx) are required on V5, even if the processor does
16464 not support Thumb. */
16465 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16468 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16469 #undef THUMB_VARIANT
16470 #define THUMB_VARIANT & arm_ext_v5t
16472 /* Note: blx has 2 variants; the .value coded here is for
16473 BLX(2). Only this variant has conditional execution. */
16474 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16475 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16477 #undef THUMB_VARIANT
16478 #define THUMB_VARIANT & arm_ext_v6t2
16480 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16481 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16482 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16483 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16484 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16485 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16486 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16487 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16490 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16491 #undef THUMB_VARIANT
16492 #define THUMB_VARIANT &arm_ext_v5exp
16494 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16495 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16496 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16497 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16499 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16500 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16502 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16503 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16504 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16505 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16507 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16508 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16509 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16510 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16512 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16513 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16515 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16516 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16517 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16518 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16521 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16522 #undef THUMB_VARIANT
16523 #define THUMB_VARIANT &arm_ext_v6t2
16525 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16526 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16527 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16529 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16530 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16533 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16535 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16538 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16539 #undef THUMB_VARIANT
16540 #define THUMB_VARIANT & arm_ext_v6
16542 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16543 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16544 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16545 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16546 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16547 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16548 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16549 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16550 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16551 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16553 #undef THUMB_VARIANT
16554 #define THUMB_VARIANT & arm_ext_v6t2
16556 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16557 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16558 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16559 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16561 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16562 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16564 /* ARM V6 not included in V7M. */
16565 #undef THUMB_VARIANT
16566 #define THUMB_VARIANT & arm_ext_v6_notm
16567 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16568 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16569 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16570 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16571 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16572 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16573 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16574 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16575 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16576 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16577 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16578 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16580 /* ARM V6 not included in V7M (eg. integer SIMD). */
16581 #undef THUMB_VARIANT
16582 #define THUMB_VARIANT & arm_ext_v6_dsp
16583 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16584 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16585 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16586 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16587 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16588 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16589 /* Old name for QASX. */
16590 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16591 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16592 /* Old name for QSAX. */
16593 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16594 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16595 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16596 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16597 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16598 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16599 /* Old name for SASX. */
16600 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16601 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16602 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16603 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16604 /* Old name for SHASX. */
16605 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16606 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16607 /* Old name for SHSAX. */
16608 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16609 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16610 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16611 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16612 /* Old name for SSAX. */
16613 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16614 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16615 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16616 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16617 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16618 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16619 /* Old name for UASX. */
16620 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16621 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16622 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16623 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16624 /* Old name for UHASX. */
16625 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16626 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16627 /* Old name for UHSAX. */
16628 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16629 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16630 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16631 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16632 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16633 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16634 /* Old name for UQASX. */
16635 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16636 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16637 /* Old name for UQSAX. */
16638 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16639 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16640 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16641 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16642 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16643 /* Old name for USAX. */
16644 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16645 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16646 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16647 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16648 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16649 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16650 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16651 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16652 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16653 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16654 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16655 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16656 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16657 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16658 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16659 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16660 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16661 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16662 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16663 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16664 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16665 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16666 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16667 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16668 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16669 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16670 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16671 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16672 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16673 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16674 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16675 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16676 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16677 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16680 #define ARM_VARIANT & arm_ext_v6k
16681 #undef THUMB_VARIANT
16682 #define THUMB_VARIANT & arm_ext_v6k
16684 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16685 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16686 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16687 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16689 #undef THUMB_VARIANT
16690 #define THUMB_VARIANT & arm_ext_v6_notm
16692 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16693 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16695 #undef THUMB_VARIANT
16696 #define THUMB_VARIANT & arm_ext_v6t2
16698 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16699 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16700 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16701 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16702 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16705 #define ARM_VARIANT & arm_ext_v6z
16707 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16710 #define ARM_VARIANT & arm_ext_v6t2
16712 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16713 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16714 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16715 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16717 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16718 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16719 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16720 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16722 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16723 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16724 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16725 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16727 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16728 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16730 /* ARM does not really have an IT instruction, so always allow it.
16731 The opcode is copied from Thumb in order to allow warnings in
16732 -mimplicit-it=[never | arm] modes. */
16734 #define ARM_VARIANT & arm_ext_v1
16736 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16737 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16738 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16739 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16740 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16741 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16742 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16743 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16744 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16745 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16746 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16747 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16748 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16749 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16750 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16751 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16752 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16753 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16755 /* Thumb2 only instructions. */
16757 #define ARM_VARIANT NULL
16759 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16760 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16761 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16762 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16763 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16764 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16766 /* Thumb-2 hardware division instructions (R and M profiles only). */
16767 #undef THUMB_VARIANT
16768 #define THUMB_VARIANT & arm_ext_div
16770 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16771 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16773 /* ARM V6M/V7 instructions. */
16775 #define ARM_VARIANT & arm_ext_barrier
16776 #undef THUMB_VARIANT
16777 #define THUMB_VARIANT & arm_ext_barrier
16779 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16780 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16781 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16783 /* ARM V7 instructions. */
16785 #define ARM_VARIANT & arm_ext_v7
16786 #undef THUMB_VARIANT
16787 #define THUMB_VARIANT & arm_ext_v7
16789 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16790 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16793 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16795 cCE("wfs", e200110
, 1, (RR
), rd
),
16796 cCE("rfs", e300110
, 1, (RR
), rd
),
16797 cCE("wfc", e400110
, 1, (RR
), rd
),
16798 cCE("rfc", e500110
, 1, (RR
), rd
),
16800 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16801 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16802 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16803 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16805 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16806 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16807 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16808 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16810 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16811 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16812 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16813 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16814 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16815 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16816 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16817 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16821 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16827 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16828 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16829 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16834 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16840 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16841 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16842 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16847 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16853 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16854 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16855 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16867 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16868 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16880 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16881 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16886 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16892 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16893 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16894 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16899 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16905 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16906 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16907 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16908 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16909 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16910 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16911 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16912 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16914 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16915 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16916 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16917 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16918 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16919 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16920 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16921 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16922 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16923 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16924 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16925 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16927 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16928 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16929 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16930 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16931 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16932 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16933 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16934 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16935 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16936 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16937 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16938 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16940 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16941 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16942 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16943 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16944 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16945 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16946 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16947 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16948 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16949 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16950 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16951 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16953 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16954 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16955 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16956 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16957 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16958 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16959 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16960 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16961 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16962 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16963 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16964 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16966 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16967 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16968 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16969 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16970 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16971 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16972 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16973 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16974 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16975 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16976 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16977 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16979 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16980 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16981 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16982 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16983 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16984 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16985 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16986 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16987 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16988 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16989 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16990 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16992 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16993 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16994 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16995 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16996 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16997 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16998 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16999 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17000 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17001 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17002 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17003 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17005 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17006 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17007 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17008 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17009 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17010 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17011 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17012 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17013 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17014 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17015 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17016 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17018 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17019 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17020 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17021 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17022 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17023 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17024 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17025 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17029 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17035 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17036 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17037 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17042 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17048 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17049 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17050 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17052 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17053 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17054 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17055 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17057 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17058 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17059 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17060 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17061 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17062 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17063 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17068 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17074 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17075 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17076 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17077 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17078 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17079 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17080 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17081 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17083 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17084 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17085 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17086 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17087 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17088 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17089 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17090 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17091 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17092 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17093 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17094 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17096 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17097 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17098 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17099 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17100 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17101 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17102 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17103 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17104 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17105 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17106 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17107 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17109 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17110 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17111 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17112 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17113 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17114 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17115 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17116 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17117 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17118 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17119 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17120 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17122 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17123 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17124 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17125 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17126 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17127 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17128 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17129 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17130 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17131 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17132 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17133 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17135 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17136 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17137 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17138 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17139 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17140 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17141 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17142 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17143 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17144 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17145 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17146 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17148 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17149 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17150 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17151 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17152 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17153 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17154 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17155 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17156 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17157 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17158 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17159 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17161 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17162 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17163 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17164 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17165 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17166 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17167 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17168 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17169 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17170 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17171 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17172 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17174 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17175 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17176 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17177 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17178 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17179 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17180 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17181 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17182 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17183 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17184 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17185 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17187 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17188 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17189 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17190 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17192 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17193 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17194 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17195 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17196 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17197 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17198 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17199 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17200 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17201 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17202 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17203 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17205 /* The implementation of the FIX instruction is broken on some
17206 assemblers, in that it accepts a precision specifier as well as a
17207 rounding specifier, despite the fact that this is meaningless.
17208 To be more compatible, we accept it as well, though of course it
17209 does not set any bits. */
17210 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17211 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17212 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17213 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17214 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17215 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17216 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17217 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17218 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17219 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17220 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17221 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17222 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17224 /* Instructions that were new with the real FPA, call them V2. */
17226 #define ARM_VARIANT & fpu_fpa_ext_v2
17228 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17229 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17230 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17231 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17232 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17233 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17236 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17238 /* Moves and type conversions. */
17239 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17240 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17241 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17242 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17243 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17244 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17245 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17246 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17247 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17248 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17249 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17250 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17251 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17252 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17254 /* Memory operations. */
17255 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17256 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17257 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17258 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17259 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17260 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17261 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17262 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17263 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17264 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17265 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17266 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17267 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17268 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17269 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17270 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17271 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17272 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17274 /* Monadic operations. */
17275 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17276 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17277 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17279 /* Dyadic operations. */
17280 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17281 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17282 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17283 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17284 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17285 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17286 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17287 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17288 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17291 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17292 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17293 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17294 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17296 /* Double precision load/store are still present on single precision
17297 implementations. */
17298 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17299 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17300 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17301 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17302 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17303 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17304 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17305 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17306 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17307 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17310 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17312 /* Moves and type conversions. */
17313 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17314 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17315 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17316 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17317 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17318 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17319 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17320 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17321 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17322 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17323 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17324 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17325 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17327 /* Monadic operations. */
17328 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17329 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17330 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17332 /* Dyadic operations. */
17333 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17334 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17335 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17336 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17337 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17338 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17339 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17340 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17341 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17344 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17345 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17346 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17347 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17350 #define ARM_VARIANT & fpu_vfp_ext_v2
17352 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17353 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17354 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17355 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17357 /* Instructions which may belong to either the Neon or VFP instruction sets.
17358 Individual encoder functions perform additional architecture checks. */
17360 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17361 #undef THUMB_VARIANT
17362 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17364 /* These mnemonics are unique to VFP. */
17365 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17366 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17367 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17368 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17369 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17370 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17371 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17372 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17373 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17374 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17376 /* Mnemonics shared by Neon and VFP. */
17377 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17378 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17379 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17381 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17382 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17384 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17385 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17387 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17388 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17389 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17390 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17391 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17392 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17393 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17394 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17396 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17397 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17398 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17401 /* NOTE: All VMOV encoding is special-cased! */
17402 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17403 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17405 #undef THUMB_VARIANT
17406 #define THUMB_VARIANT & fpu_neon_ext_v1
17408 #define ARM_VARIANT & fpu_neon_ext_v1
17410 /* Data processing with three registers of the same length. */
17411 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17412 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17413 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17414 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17415 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17416 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17417 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17418 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17419 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17420 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17421 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17422 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17423 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17424 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17425 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17426 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17427 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17428 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17429 /* If not immediate, fall back to neon_dyadic_i64_su.
17430 shl_imm should accept I8 I16 I32 I64,
17431 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17432 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17433 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17434 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17435 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17436 /* Logic ops, types optional & ignored. */
17437 nUF(vand
, _vand
, 2, (RNDQ
, NILO
), neon_logic
),
17438 nUF(vandq
, _vand
, 2, (RNQ
, NILO
), neon_logic
),
17439 nUF(vbic
, _vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17440 nUF(vbicq
, _vbic
, 2, (RNQ
, NILO
), neon_logic
),
17441 nUF(vorr
, _vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17442 nUF(vorrq
, _vorr
, 2, (RNQ
, NILO
), neon_logic
),
17443 nUF(vorn
, _vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17444 nUF(vornq
, _vorn
, 2, (RNQ
, NILO
), neon_logic
),
17445 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17446 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17447 /* Bitfield ops, untyped. */
17448 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17449 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17450 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17451 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17452 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17453 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17454 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17455 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17456 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17457 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17458 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17459 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17460 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17461 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17462 back to neon_dyadic_if_su. */
17463 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17464 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17465 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17466 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17467 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17468 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17469 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17470 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17471 /* Comparison. Type I8 I16 I32 F32. */
17472 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17473 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17474 /* As above, D registers only. */
17475 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17476 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17477 /* Int and float variants, signedness unimportant. */
17478 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17479 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17480 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17481 /* Add/sub take types I8 I16 I32 I64 F32. */
17482 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17483 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17484 /* vtst takes sizes 8, 16, 32. */
17485 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17486 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17487 /* VMUL takes I8 I16 I32 F32 P8. */
17488 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17489 /* VQD{R}MULH takes S16 S32. */
17490 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17491 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17492 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17493 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17494 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17495 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17496 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17497 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17498 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17499 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17500 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17501 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17502 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17503 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17504 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17505 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17507 /* Two address, int/float. Types S8 S16 S32 F32. */
17508 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17509 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17511 /* Data processing with two registers and a shift amount. */
17512 /* Right shifts, and variants with rounding.
17513 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17514 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17515 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17516 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17517 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17518 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17519 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17520 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17521 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17522 /* Shift and insert. Sizes accepted 8 16 32 64. */
17523 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17524 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17525 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17526 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17527 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17528 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17529 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17530 /* Right shift immediate, saturating & narrowing, with rounding variants.
17531 Types accepted S16 S32 S64 U16 U32 U64. */
17532 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17533 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17534 /* As above, unsigned. Types accepted S16 S32 S64. */
17535 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17536 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17537 /* Right shift narrowing. Types accepted I16 I32 I64. */
17538 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17539 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17540 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17541 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17542 /* CVT with optional immediate for fixed-point variant. */
17543 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17545 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17546 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17548 /* Data processing, three registers of different lengths. */
17549 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17550 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17551 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17552 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17553 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17554 /* If not scalar, fall back to neon_dyadic_long.
17555 Vector types as above, scalar types S16 S32 U16 U32. */
17556 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17557 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17558 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17559 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17560 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17561 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17562 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17563 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17564 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17565 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17566 /* Saturating doubling multiplies. Types S16 S32. */
17567 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17568 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17569 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17570 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17571 S16 S32 U16 U32. */
17572 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17574 /* Extract. Size 8. */
17575 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17576 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17578 /* Two registers, miscellaneous. */
17579 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17580 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17581 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17582 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17583 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17584 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17585 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17586 /* Vector replicate. Sizes 8 16 32. */
17587 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17588 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17589 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17590 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17591 /* VMOVN. Types I16 I32 I64. */
17592 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17593 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17594 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17595 /* VQMOVUN. Types S16 S32 S64. */
17596 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17597 /* VZIP / VUZP. Sizes 8 16 32. */
17598 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17599 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17600 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17601 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17602 /* VQABS / VQNEG. Types S8 S16 S32. */
17603 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17604 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17605 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17606 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17607 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17608 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17609 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17610 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17611 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17612 /* Reciprocal estimates. Types U32 F32. */
17613 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17614 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17615 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17616 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17617 /* VCLS. Types S8 S16 S32. */
17618 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17619 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17620 /* VCLZ. Types I8 I16 I32. */
17621 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17622 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17623 /* VCNT. Size 8. */
17624 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17625 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17626 /* Two address, untyped. */
17627 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17628 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17629 /* VTRN. Sizes 8 16 32. */
17630 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17631 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17633 /* Table lookup. Size 8. */
17634 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17635 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17637 #undef THUMB_VARIANT
17638 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17640 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17642 /* Neon element/structure load/store. */
17643 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17644 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17645 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17646 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17647 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17648 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17649 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17650 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17652 #undef THUMB_VARIANT
17653 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17655 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17656 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17657 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17658 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17659 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17660 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17661 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17662 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17663 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17664 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17666 #undef THUMB_VARIANT
17667 #define THUMB_VARIANT & fpu_vfp_ext_v3
17669 #define ARM_VARIANT & fpu_vfp_ext_v3
17671 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17672 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17673 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17674 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17675 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17676 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17677 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17678 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17679 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17682 #define ARM_VARIANT &fpu_vfp_ext_fma
17683 #undef THUMB_VARIANT
17684 #define THUMB_VARIANT &fpu_vfp_ext_fma
17685 /* Mnemonics shared by Neon and VFP. These are included in the
17686 VFP FMA variant; NEON and VFP FMA always includes the NEON
17687 FMA instructions. */
17688 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17689 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17690 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17691 the v form should always be used. */
17692 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17693 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17694 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17695 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17696 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17697 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17699 #undef THUMB_VARIANT
17701 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17703 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17704 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17705 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17706 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17707 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17708 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17709 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17710 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17713 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17715 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17716 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17717 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17718 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17719 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17720 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17721 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17722 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17723 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17724 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17725 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17726 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17727 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17728 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17729 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17730 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17731 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17732 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17733 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17734 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17735 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17736 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17737 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17738 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17739 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17740 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17741 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17742 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17743 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17744 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17745 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17746 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17747 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17748 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17749 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17750 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17751 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17752 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17753 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17754 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17755 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17756 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17757 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17758 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17759 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17760 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17761 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17762 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17763 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17764 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17765 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17766 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17767 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17768 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17769 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17770 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17771 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17772 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17773 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17774 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17776 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17777 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17779 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17780 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17781 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17782 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17783 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17784 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17785 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17786 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17787 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17788 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17789 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17790 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17791 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17792 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17793 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17794 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17795 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17796 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17797 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17798 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17799 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17800 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17801 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17802 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17803 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17804 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17805 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17806 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17807 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17808 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17809 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17810 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17811 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17812 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17813 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17814 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17815 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17816 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17817 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17818 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17819 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17820 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17821 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17822 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17823 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17824 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17825 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17826 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17827 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17828 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17829 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17830 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17831 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17832 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17833 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17834 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17835 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17836 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17837 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17838 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17839 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17840 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17841 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17842 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17843 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17844 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17845 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17846 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17847 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17848 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17849 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17850 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17851 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17852 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17853 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17854 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17855 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17856 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17857 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17858 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17859 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17860 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17861 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17862 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17863 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17864 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17865 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17866 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17867 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17868 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17869 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17870 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17871 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17872 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17873 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17874 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17875 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17876 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17879 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17881 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17882 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17883 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17884 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17885 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17886 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17887 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17888 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17889 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17890 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17891 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17892 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17893 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17894 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17895 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17896 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17897 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17898 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17899 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17900 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17901 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17902 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17903 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17904 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17905 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17906 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17907 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17908 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17909 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17910 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17911 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17912 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17913 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17914 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17915 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17916 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17917 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17918 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17919 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17920 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17921 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17922 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17923 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17924 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17925 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17926 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17927 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17928 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17929 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17930 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17931 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17932 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17933 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17934 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17935 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17936 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17937 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17940 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17942 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17943 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17944 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17945 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17946 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17947 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17948 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17949 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17950 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17951 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17952 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17953 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
17954 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
17955 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
17956 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
17957 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
17958 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
17959 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
17960 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17961 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17962 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17963 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17964 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17965 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17966 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17967 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17968 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17969 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17970 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17971 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
17972 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
17973 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
17974 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
17975 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
17976 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
17977 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17978 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17979 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17980 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
17981 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17982 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17983 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17984 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17985 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17986 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17987 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17988 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17989 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17990 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17991 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17992 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
17993 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
17994 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
17995 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
17996 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17997 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17998 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17999 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18000 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18001 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18002 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18003 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18004 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18005 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18006 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18007 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18008 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18009 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18010 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18011 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18012 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18013 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18014 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18015 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18016 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18017 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18020 #undef THUMB_VARIANT
18047 /* MD interface: bits in the object file. */
18049 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18050 for use in the a.out file, and stores them in the array pointed to by buf.
18051 This knows about the endian-ness of the target machine and does
18052 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18053 2 (short) and 4 (long) Floating numbers are put out as a series of
18054 LITTLENUMS (shorts, here at least). */
18057 md_number_to_chars (char * buf
, valueT val
, int n
)
18059 if (target_big_endian
)
18060 number_to_chars_bigendian (buf
, val
, n
);
18062 number_to_chars_littleendian (buf
, val
, n
);
18066 md_chars_to_number (char * buf
, int n
)
18069 unsigned char * where
= (unsigned char *) buf
;
18071 if (target_big_endian
)
18076 result
|= (*where
++ & 255);
18084 result
|= (where
[n
] & 255);
18091 /* MD interface: Sections. */
18093 /* Estimate the size of a frag before relaxing. Assume everything fits in
18097 md_estimate_size_before_relax (fragS
* fragp
,
18098 segT segtype ATTRIBUTE_UNUSED
)
18104 /* Convert a machine dependent frag. */
18107 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18109 unsigned long insn
;
18110 unsigned long old_op
;
18118 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18120 old_op
= bfd_get_16(abfd
, buf
);
18121 if (fragp
->fr_symbol
)
18123 exp
.X_op
= O_symbol
;
18124 exp
.X_add_symbol
= fragp
->fr_symbol
;
18128 exp
.X_op
= O_constant
;
18130 exp
.X_add_number
= fragp
->fr_offset
;
18131 opcode
= fragp
->fr_subtype
;
18134 case T_MNEM_ldr_pc
:
18135 case T_MNEM_ldr_pc2
:
18136 case T_MNEM_ldr_sp
:
18137 case T_MNEM_str_sp
:
18144 if (fragp
->fr_var
== 4)
18146 insn
= THUMB_OP32 (opcode
);
18147 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18149 insn
|= (old_op
& 0x700) << 4;
18153 insn
|= (old_op
& 7) << 12;
18154 insn
|= (old_op
& 0x38) << 13;
18156 insn
|= 0x00000c00;
18157 put_thumb32_insn (buf
, insn
);
18158 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18162 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18164 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18167 if (fragp
->fr_var
== 4)
18169 insn
= THUMB_OP32 (opcode
);
18170 insn
|= (old_op
& 0xf0) << 4;
18171 put_thumb32_insn (buf
, insn
);
18172 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18176 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18177 exp
.X_add_number
-= 4;
18185 if (fragp
->fr_var
== 4)
18187 int r0off
= (opcode
== T_MNEM_mov
18188 || opcode
== T_MNEM_movs
) ? 0 : 8;
18189 insn
= THUMB_OP32 (opcode
);
18190 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18191 insn
|= (old_op
& 0x700) << r0off
;
18192 put_thumb32_insn (buf
, insn
);
18193 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18197 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18202 if (fragp
->fr_var
== 4)
18204 insn
= THUMB_OP32(opcode
);
18205 put_thumb32_insn (buf
, insn
);
18206 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18209 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18213 if (fragp
->fr_var
== 4)
18215 insn
= THUMB_OP32(opcode
);
18216 insn
|= (old_op
& 0xf00) << 14;
18217 put_thumb32_insn (buf
, insn
);
18218 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18221 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18224 case T_MNEM_add_sp
:
18225 case T_MNEM_add_pc
:
18226 case T_MNEM_inc_sp
:
18227 case T_MNEM_dec_sp
:
18228 if (fragp
->fr_var
== 4)
18230 /* ??? Choose between add and addw. */
18231 insn
= THUMB_OP32 (opcode
);
18232 insn
|= (old_op
& 0xf0) << 4;
18233 put_thumb32_insn (buf
, insn
);
18234 if (opcode
== T_MNEM_add_pc
)
18235 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18237 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18240 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18248 if (fragp
->fr_var
== 4)
18250 insn
= THUMB_OP32 (opcode
);
18251 insn
|= (old_op
& 0xf0) << 4;
18252 insn
|= (old_op
& 0xf) << 16;
18253 put_thumb32_insn (buf
, insn
);
18254 if (insn
& (1 << 20))
18255 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18257 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18260 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18266 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18267 (enum bfd_reloc_code_real
) reloc_type
);
18268 fixp
->fx_file
= fragp
->fr_file
;
18269 fixp
->fx_line
= fragp
->fr_line
;
18270 fragp
->fr_fix
+= fragp
->fr_var
;
18273 /* Return the size of a relaxable immediate operand instruction.
18274 SHIFT and SIZE specify the form of the allowable immediate. */
18276 relax_immediate (fragS
*fragp
, int size
, int shift
)
18282 /* ??? Should be able to do better than this. */
18283 if (fragp
->fr_symbol
)
18286 low
= (1 << shift
) - 1;
18287 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18288 offset
= fragp
->fr_offset
;
18289 /* Force misaligned offsets to 32-bit variant. */
18292 if (offset
& ~mask
)
18297 /* Get the address of a symbol during relaxation. */
18299 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18305 sym
= fragp
->fr_symbol
;
18306 sym_frag
= symbol_get_frag (sym
);
18307 know (S_GET_SEGMENT (sym
) != absolute_section
18308 || sym_frag
== &zero_address_frag
);
18309 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18311 /* If frag has yet to be reached on this pass, assume it will
18312 move by STRETCH just as we did. If this is not so, it will
18313 be because some frag between grows, and that will force
18317 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18321 /* Adjust stretch for any alignment frag. Note that if have
18322 been expanding the earlier code, the symbol may be
18323 defined in what appears to be an earlier frag. FIXME:
18324 This doesn't handle the fr_subtype field, which specifies
18325 a maximum number of bytes to skip when doing an
18327 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18329 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18332 stretch
= - ((- stretch
)
18333 & ~ ((1 << (int) f
->fr_offset
) - 1));
18335 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18347 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18350 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18355 /* Assume worst case for symbols not known to be in the same section. */
18356 if (fragp
->fr_symbol
== NULL
18357 || !S_IS_DEFINED (fragp
->fr_symbol
)
18358 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18361 val
= relaxed_symbol_addr (fragp
, stretch
);
18362 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18363 addr
= (addr
+ 4) & ~3;
18364 /* Force misaligned targets to 32-bit variant. */
18368 if (val
< 0 || val
> 1020)
18373 /* Return the size of a relaxable add/sub immediate instruction. */
18375 relax_addsub (fragS
*fragp
, asection
*sec
)
18380 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18381 op
= bfd_get_16(sec
->owner
, buf
);
18382 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18383 return relax_immediate (fragp
, 8, 0);
18385 return relax_immediate (fragp
, 3, 0);
18389 /* Return the size of a relaxable branch instruction. BITS is the
18390 size of the offset field in the narrow instruction. */
18393 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18399 /* Assume worst case for symbols not known to be in the same section. */
18400 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18401 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18405 if (S_IS_DEFINED (fragp
->fr_symbol
)
18406 && ARM_IS_FUNC (fragp
->fr_symbol
))
18410 val
= relaxed_symbol_addr (fragp
, stretch
);
18411 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18414 /* Offset is a signed value *2 */
18416 if (val
>= limit
|| val
< -limit
)
18422 /* Relax a machine dependent frag. This returns the amount by which
18423 the current size of the frag should change. */
18426 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18431 oldsize
= fragp
->fr_var
;
18432 switch (fragp
->fr_subtype
)
18434 case T_MNEM_ldr_pc2
:
18435 newsize
= relax_adr (fragp
, sec
, stretch
);
18437 case T_MNEM_ldr_pc
:
18438 case T_MNEM_ldr_sp
:
18439 case T_MNEM_str_sp
:
18440 newsize
= relax_immediate (fragp
, 8, 2);
18444 newsize
= relax_immediate (fragp
, 5, 2);
18448 newsize
= relax_immediate (fragp
, 5, 1);
18452 newsize
= relax_immediate (fragp
, 5, 0);
18455 newsize
= relax_adr (fragp
, sec
, stretch
);
18461 newsize
= relax_immediate (fragp
, 8, 0);
18464 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18467 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18469 case T_MNEM_add_sp
:
18470 case T_MNEM_add_pc
:
18471 newsize
= relax_immediate (fragp
, 8, 2);
18473 case T_MNEM_inc_sp
:
18474 case T_MNEM_dec_sp
:
18475 newsize
= relax_immediate (fragp
, 7, 2);
18481 newsize
= relax_addsub (fragp
, sec
);
18487 fragp
->fr_var
= newsize
;
18488 /* Freeze wide instructions that are at or before the same location as
18489 in the previous pass. This avoids infinite loops.
18490 Don't freeze them unconditionally because targets may be artificially
18491 misaligned by the expansion of preceding frags. */
18492 if (stretch
<= 0 && newsize
> 2)
18494 md_convert_frag (sec
->owner
, sec
, fragp
);
18498 return newsize
- oldsize
;
18501 /* Round up a section size to the appropriate boundary. */
18504 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18507 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18508 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18510 /* For a.out, force the section size to be aligned. If we don't do
18511 this, BFD will align it for us, but it will not write out the
18512 final bytes of the section. This may be a bug in BFD, but it is
18513 easier to fix it here since that is how the other a.out targets
18517 align
= bfd_get_section_alignment (stdoutput
, segment
);
18518 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18525 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18526 of an rs_align_code fragment. */
18529 arm_handle_align (fragS
* fragP
)
18531 static char const arm_noop
[2][2][4] =
18534 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18535 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18538 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18539 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18542 static char const thumb_noop
[2][2][2] =
18545 {0xc0, 0x46}, /* LE */
18546 {0x46, 0xc0}, /* BE */
18549 {0x00, 0xbf}, /* LE */
18550 {0xbf, 0x00} /* BE */
18553 static char const wide_thumb_noop
[2][4] =
18554 { /* Wide Thumb-2 */
18555 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18556 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18559 unsigned bytes
, fix
, noop_size
;
18562 const char *narrow_noop
= NULL
;
18567 if (fragP
->fr_type
!= rs_align_code
)
18570 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18571 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18574 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18575 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18578 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18581 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18583 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18585 narrow_noop
= thumb_noop
[1][target_big_endian
];
18586 noop
= wide_thumb_noop
[target_big_endian
];
18589 noop
= thumb_noop
[0][target_big_endian
];
18597 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18598 [target_big_endian
];
18605 fragP
->fr_var
= noop_size
;
18607 if (bytes
& (noop_size
- 1))
18609 fix
= bytes
& (noop_size
- 1);
18611 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18613 memset (p
, 0, fix
);
18620 if (bytes
& noop_size
)
18622 /* Insert a narrow noop. */
18623 memcpy (p
, narrow_noop
, noop_size
);
18625 bytes
-= noop_size
;
18629 /* Use wide noops for the remainder */
18633 while (bytes
>= noop_size
)
18635 memcpy (p
, noop
, noop_size
);
18637 bytes
-= noop_size
;
18641 fragP
->fr_fix
+= fix
;
18644 /* Called from md_do_align. Used to create an alignment
18645 frag in a code section. */
18648 arm_frag_align_code (int n
, int max
)
18652 /* We assume that there will never be a requirement
18653 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18654 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18659 _("alignments greater than %d bytes not supported in .text sections."),
18660 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18661 as_fatal ("%s", err_msg
);
18664 p
= frag_var (rs_align_code
,
18665 MAX_MEM_FOR_RS_ALIGN_CODE
,
18667 (relax_substateT
) max
,
18674 /* Perform target specific initialisation of a frag.
18675 Note - despite the name this initialisation is not done when the frag
18676 is created, but only when its type is assigned. A frag can be created
18677 and used a long time before its type is set, so beware of assuming that
18678 this initialisationis performed first. */
18682 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18684 /* Record whether this frag is in an ARM or a THUMB area. */
18685 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
;
18688 #else /* OBJ_ELF is defined. */
18690 arm_init_frag (fragS
* fragP
, int max_chars
)
18692 /* If the current ARM vs THUMB mode has not already
18693 been recorded into this frag then do so now. */
18694 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18696 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18698 /* Record a mapping symbol for alignment frags. We will delete this
18699 later if the alignment ends up empty. */
18700 switch (fragP
->fr_type
)
18703 case rs_align_test
:
18705 mapping_state_2 (MAP_DATA
, max_chars
);
18707 case rs_align_code
:
18708 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18716 /* When we change sections we need to issue a new mapping symbol. */
18719 arm_elf_change_section (void)
18721 /* Link an unlinked unwind index table section to the .text section. */
18722 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18723 && elf_linked_to_section (now_seg
) == NULL
)
18724 elf_linked_to_section (now_seg
) = text_section
;
18728 arm_elf_section_type (const char * str
, size_t len
)
18730 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18731 return SHT_ARM_EXIDX
;
18736 /* Code to deal with unwinding tables. */
18738 static void add_unwind_adjustsp (offsetT
);
18740 /* Generate any deferred unwind frame offset. */
18743 flush_pending_unwind (void)
18747 offset
= unwind
.pending_offset
;
18748 unwind
.pending_offset
= 0;
18750 add_unwind_adjustsp (offset
);
18753 /* Add an opcode to this list for this function. Two-byte opcodes should
18754 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18758 add_unwind_opcode (valueT op
, int length
)
18760 /* Add any deferred stack adjustment. */
18761 if (unwind
.pending_offset
)
18762 flush_pending_unwind ();
18764 unwind
.sp_restored
= 0;
18766 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18768 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18769 if (unwind
.opcodes
)
18770 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18771 unwind
.opcode_alloc
);
18773 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18778 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18780 unwind
.opcode_count
++;
18784 /* Add unwind opcodes to adjust the stack pointer. */
18787 add_unwind_adjustsp (offsetT offset
)
18791 if (offset
> 0x200)
18793 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18798 /* Long form: 0xb2, uleb128. */
18799 /* This might not fit in a word so add the individual bytes,
18800 remembering the list is built in reverse order. */
18801 o
= (valueT
) ((offset
- 0x204) >> 2);
18803 add_unwind_opcode (0, 1);
18805 /* Calculate the uleb128 encoding of the offset. */
18809 bytes
[n
] = o
& 0x7f;
18815 /* Add the insn. */
18817 add_unwind_opcode (bytes
[n
- 1], 1);
18818 add_unwind_opcode (0xb2, 1);
18820 else if (offset
> 0x100)
18822 /* Two short opcodes. */
18823 add_unwind_opcode (0x3f, 1);
18824 op
= (offset
- 0x104) >> 2;
18825 add_unwind_opcode (op
, 1);
18827 else if (offset
> 0)
18829 /* Short opcode. */
18830 op
= (offset
- 4) >> 2;
18831 add_unwind_opcode (op
, 1);
18833 else if (offset
< 0)
18836 while (offset
> 0x100)
18838 add_unwind_opcode (0x7f, 1);
18841 op
= ((offset
- 4) >> 2) | 0x40;
18842 add_unwind_opcode (op
, 1);
18846 /* Finish the list of unwind opcodes for this function. */
18848 finish_unwind_opcodes (void)
18852 if (unwind
.fp_used
)
18854 /* Adjust sp as necessary. */
18855 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18856 flush_pending_unwind ();
18858 /* After restoring sp from the frame pointer. */
18859 op
= 0x90 | unwind
.fp_reg
;
18860 add_unwind_opcode (op
, 1);
18863 flush_pending_unwind ();
18867 /* Start an exception table entry. If idx is nonzero this is an index table
18871 start_unwind_section (const segT text_seg
, int idx
)
18873 const char * text_name
;
18874 const char * prefix
;
18875 const char * prefix_once
;
18876 const char * group_name
;
18880 size_t sec_name_len
;
18887 prefix
= ELF_STRING_ARM_unwind
;
18888 prefix_once
= ELF_STRING_ARM_unwind_once
;
18889 type
= SHT_ARM_EXIDX
;
18893 prefix
= ELF_STRING_ARM_unwind_info
;
18894 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18895 type
= SHT_PROGBITS
;
18898 text_name
= segment_name (text_seg
);
18899 if (streq (text_name
, ".text"))
18902 if (strncmp (text_name
, ".gnu.linkonce.t.",
18903 strlen (".gnu.linkonce.t.")) == 0)
18905 prefix
= prefix_once
;
18906 text_name
+= strlen (".gnu.linkonce.t.");
18909 prefix_len
= strlen (prefix
);
18910 text_len
= strlen (text_name
);
18911 sec_name_len
= prefix_len
+ text_len
;
18912 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18913 memcpy (sec_name
, prefix
, prefix_len
);
18914 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18915 sec_name
[prefix_len
+ text_len
] = '\0';
18921 /* Handle COMDAT group. */
18922 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18924 group_name
= elf_group_name (text_seg
);
18925 if (group_name
== NULL
)
18927 as_bad (_("Group section `%s' has no group signature"),
18928 segment_name (text_seg
));
18929 ignore_rest_of_line ();
18932 flags
|= SHF_GROUP
;
18936 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18938 /* Set the section link for index tables. */
18940 elf_linked_to_section (now_seg
) = text_seg
;
18944 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18945 personality routine data. Returns zero, or the index table value for
18946 and inline entry. */
18949 create_unwind_entry (int have_data
)
18954 /* The current word of data. */
18956 /* The number of bytes left in this word. */
18959 finish_unwind_opcodes ();
18961 /* Remember the current text section. */
18962 unwind
.saved_seg
= now_seg
;
18963 unwind
.saved_subseg
= now_subseg
;
18965 start_unwind_section (now_seg
, 0);
18967 if (unwind
.personality_routine
== NULL
)
18969 if (unwind
.personality_index
== -2)
18972 as_bad (_("handlerdata in cantunwind frame"));
18973 return 1; /* EXIDX_CANTUNWIND. */
18976 /* Use a default personality routine if none is specified. */
18977 if (unwind
.personality_index
== -1)
18979 if (unwind
.opcode_count
> 3)
18980 unwind
.personality_index
= 1;
18982 unwind
.personality_index
= 0;
18985 /* Space for the personality routine entry. */
18986 if (unwind
.personality_index
== 0)
18988 if (unwind
.opcode_count
> 3)
18989 as_bad (_("too many unwind opcodes for personality routine 0"));
18993 /* All the data is inline in the index table. */
18996 while (unwind
.opcode_count
> 0)
18998 unwind
.opcode_count
--;
18999 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19003 /* Pad with "finish" opcodes. */
19005 data
= (data
<< 8) | 0xb0;
19012 /* We get two opcodes "free" in the first word. */
19013 size
= unwind
.opcode_count
- 2;
19016 /* An extra byte is required for the opcode count. */
19017 size
= unwind
.opcode_count
+ 1;
19019 size
= (size
+ 3) >> 2;
19021 as_bad (_("too many unwind opcodes"));
19023 frag_align (2, 0, 0);
19024 record_alignment (now_seg
, 2);
19025 unwind
.table_entry
= expr_build_dot ();
19027 /* Allocate the table entry. */
19028 ptr
= frag_more ((size
<< 2) + 4);
19029 where
= frag_now_fix () - ((size
<< 2) + 4);
19031 switch (unwind
.personality_index
)
19034 /* ??? Should this be a PLT generating relocation? */
19035 /* Custom personality routine. */
19036 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19037 BFD_RELOC_ARM_PREL31
);
19042 /* Set the first byte to the number of additional words. */
19047 /* ABI defined personality routines. */
19049 /* Three opcodes bytes are packed into the first word. */
19056 /* The size and first two opcode bytes go in the first word. */
19057 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19062 /* Should never happen. */
19066 /* Pack the opcodes into words (MSB first), reversing the list at the same
19068 while (unwind
.opcode_count
> 0)
19072 md_number_to_chars (ptr
, data
, 4);
19077 unwind
.opcode_count
--;
19079 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19082 /* Finish off the last word. */
19085 /* Pad with "finish" opcodes. */
19087 data
= (data
<< 8) | 0xb0;
19089 md_number_to_chars (ptr
, data
, 4);
19094 /* Add an empty descriptor if there is no user-specified data. */
19095 ptr
= frag_more (4);
19096 md_number_to_chars (ptr
, 0, 4);
19103 /* Initialize the DWARF-2 unwind information for this procedure. */
19106 tc_arm_frame_initial_instructions (void)
19108 cfi_add_CFA_def_cfa (REG_SP
, 0);
19110 #endif /* OBJ_ELF */
19112 /* Convert REGNAME to a DWARF-2 register number. */
19115 tc_arm_regname_to_dw2regnum (char *regname
)
19117 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19127 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19131 expr
.X_op
= O_secrel
;
19132 expr
.X_add_symbol
= symbol
;
19133 expr
.X_add_number
= 0;
19134 emit_expr (&expr
, size
);
19138 /* MD interface: Symbol and relocation handling. */
19140 /* Return the address within the segment that a PC-relative fixup is
19141 relative to. For ARM, PC-relative fixups applied to instructions
19142 are generally relative to the location of the fixup plus 8 bytes.
19143 Thumb branches are offset by 4, and Thumb loads relative to PC
19144 require special handling. */
19147 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19149 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19151 /* If this is pc-relative and we are going to emit a relocation
19152 then we just want to put out any pipeline compensation that the linker
19153 will need. Otherwise we want to use the calculated base.
19154 For WinCE we skip the bias for externals as well, since this
19155 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19157 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19158 || (arm_force_relocation (fixP
)
19160 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19166 switch (fixP
->fx_r_type
)
19168 /* PC relative addressing on the Thumb is slightly odd as the
19169 bottom two bits of the PC are forced to zero for the
19170 calculation. This happens *after* application of the
19171 pipeline offset. However, Thumb adrl already adjusts for
19172 this, so we need not do it again. */
19173 case BFD_RELOC_ARM_THUMB_ADD
:
19176 case BFD_RELOC_ARM_THUMB_OFFSET
:
19177 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19178 case BFD_RELOC_ARM_T32_ADD_PC12
:
19179 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19180 return (base
+ 4) & ~3;
19182 /* Thumb branches are simply offset by +4. */
19183 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19184 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19185 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19186 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19187 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19190 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19192 && ARM_IS_FUNC (fixP
->fx_addsy
)
19193 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19194 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19197 /* BLX is like branches above, but forces the low two bits of PC to
19199 case BFD_RELOC_THUMB_PCREL_BLX
:
19201 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19202 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19203 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19204 return (base
+ 4) & ~3;
19206 /* ARM mode branches are offset by +8. However, the Windows CE
19207 loader expects the relocation not to take this into account. */
19208 case BFD_RELOC_ARM_PCREL_BLX
:
19210 && ARM_IS_FUNC (fixP
->fx_addsy
)
19211 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19212 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19215 case BFD_RELOC_ARM_PCREL_CALL
:
19217 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19218 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19219 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19222 case BFD_RELOC_ARM_PCREL_BRANCH
:
19223 case BFD_RELOC_ARM_PCREL_JUMP
:
19224 case BFD_RELOC_ARM_PLT32
:
19226 /* When handling fixups immediately, because we have already
19227 discovered the value of a symbol, or the address of the frag involved
19228 we must account for the offset by +8, as the OS loader will never see the reloc.
19229 see fixup_segment() in write.c
19230 The S_IS_EXTERNAL test handles the case of global symbols.
19231 Those need the calculated base, not just the pipe compensation the linker will need. */
19233 && fixP
->fx_addsy
!= NULL
19234 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19235 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19243 /* ARM mode loads relative to PC are also offset by +8. Unlike
19244 branches, the Windows CE loader *does* expect the relocation
19245 to take this into account. */
19246 case BFD_RELOC_ARM_OFFSET_IMM
:
19247 case BFD_RELOC_ARM_OFFSET_IMM8
:
19248 case BFD_RELOC_ARM_HWLITERAL
:
19249 case BFD_RELOC_ARM_LITERAL
:
19250 case BFD_RELOC_ARM_CP_OFF_IMM
:
19254 /* Other PC-relative relocations are un-offset. */
19260 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19261 Otherwise we have no need to default values of symbols. */
19264 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19267 if (name
[0] == '_' && name
[1] == 'G'
19268 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19272 if (symbol_find (name
))
19273 as_bad (_("GOT already in the symbol table"));
19275 GOT_symbol
= symbol_new (name
, undefined_section
,
19276 (valueT
) 0, & zero_address_frag
);
19286 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19287 computed as two separate immediate values, added together. We
19288 already know that this value cannot be computed by just one ARM
19291 static unsigned int
19292 validate_immediate_twopart (unsigned int val
,
19293 unsigned int * highpart
)
19298 for (i
= 0; i
< 32; i
+= 2)
19299 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19305 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19307 else if (a
& 0xff0000)
19309 if (a
& 0xff000000)
19311 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19315 gas_assert (a
& 0xff000000);
19316 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19319 return (a
& 0xff) | (i
<< 7);
19326 validate_offset_imm (unsigned int val
, int hwse
)
19328 if ((hwse
&& val
> 255) || val
> 4095)
19333 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19334 negative immediate constant by altering the instruction. A bit of
19339 by inverting the second operand, and
19342 by negating the second operand. */
19345 negate_data_op (unsigned long * instruction
,
19346 unsigned long value
)
19349 unsigned long negated
, inverted
;
19351 negated
= encode_arm_immediate (-value
);
19352 inverted
= encode_arm_immediate (~value
);
19354 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19357 /* First negates. */
19358 case OPCODE_SUB
: /* ADD <-> SUB */
19359 new_inst
= OPCODE_ADD
;
19364 new_inst
= OPCODE_SUB
;
19368 case OPCODE_CMP
: /* CMP <-> CMN */
19369 new_inst
= OPCODE_CMN
;
19374 new_inst
= OPCODE_CMP
;
19378 /* Now Inverted ops. */
19379 case OPCODE_MOV
: /* MOV <-> MVN */
19380 new_inst
= OPCODE_MVN
;
19385 new_inst
= OPCODE_MOV
;
19389 case OPCODE_AND
: /* AND <-> BIC */
19390 new_inst
= OPCODE_BIC
;
19395 new_inst
= OPCODE_AND
;
19399 case OPCODE_ADC
: /* ADC <-> SBC */
19400 new_inst
= OPCODE_SBC
;
19405 new_inst
= OPCODE_ADC
;
19409 /* We cannot do anything. */
19414 if (value
== (unsigned) FAIL
)
19417 *instruction
&= OPCODE_MASK
;
19418 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19422 /* Like negate_data_op, but for Thumb-2. */
19424 static unsigned int
19425 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19429 unsigned int negated
, inverted
;
19431 negated
= encode_thumb32_immediate (-value
);
19432 inverted
= encode_thumb32_immediate (~value
);
19434 rd
= (*instruction
>> 8) & 0xf;
19435 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19438 /* ADD <-> SUB. Includes CMP <-> CMN. */
19439 case T2_OPCODE_SUB
:
19440 new_inst
= T2_OPCODE_ADD
;
19444 case T2_OPCODE_ADD
:
19445 new_inst
= T2_OPCODE_SUB
;
19449 /* ORR <-> ORN. Includes MOV <-> MVN. */
19450 case T2_OPCODE_ORR
:
19451 new_inst
= T2_OPCODE_ORN
;
19455 case T2_OPCODE_ORN
:
19456 new_inst
= T2_OPCODE_ORR
;
19460 /* AND <-> BIC. TST has no inverted equivalent. */
19461 case T2_OPCODE_AND
:
19462 new_inst
= T2_OPCODE_BIC
;
19469 case T2_OPCODE_BIC
:
19470 new_inst
= T2_OPCODE_AND
;
19475 case T2_OPCODE_ADC
:
19476 new_inst
= T2_OPCODE_SBC
;
19480 case T2_OPCODE_SBC
:
19481 new_inst
= T2_OPCODE_ADC
;
19485 /* We cannot do anything. */
19490 if (value
== (unsigned int)FAIL
)
19493 *instruction
&= T2_OPCODE_MASK
;
19494 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19498 /* Read a 32-bit thumb instruction from buf. */
19499 static unsigned long
19500 get_thumb32_insn (char * buf
)
19502 unsigned long insn
;
19503 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19504 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19510 /* We usually want to set the low bit on the address of thumb function
19511 symbols. In particular .word foo - . should have the low bit set.
19512 Generic code tries to fold the difference of two symbols to
19513 a constant. Prevent this and force a relocation when the first symbols
19514 is a thumb function. */
19517 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19519 if (op
== O_subtract
19520 && l
->X_op
== O_symbol
19521 && r
->X_op
== O_symbol
19522 && THUMB_IS_FUNC (l
->X_add_symbol
))
19524 l
->X_op
= O_subtract
;
19525 l
->X_op_symbol
= r
->X_add_symbol
;
19526 l
->X_add_number
-= r
->X_add_number
;
19530 /* Process as normal. */
19535 md_apply_fix (fixS
* fixP
,
19539 offsetT value
= * valP
;
19541 unsigned int newimm
;
19542 unsigned long temp
;
19544 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19546 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19548 /* Note whether this will delete the relocation. */
19550 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19553 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19554 consistency with the behaviour on 32-bit hosts. Remember value
19556 value
&= 0xffffffff;
19557 value
^= 0x80000000;
19558 value
-= 0x80000000;
19561 fixP
->fx_addnumber
= value
;
19563 /* Same treatment for fixP->fx_offset. */
19564 fixP
->fx_offset
&= 0xffffffff;
19565 fixP
->fx_offset
^= 0x80000000;
19566 fixP
->fx_offset
-= 0x80000000;
19568 switch (fixP
->fx_r_type
)
19570 case BFD_RELOC_NONE
:
19571 /* This will need to go in the object file. */
19575 case BFD_RELOC_ARM_IMMEDIATE
:
19576 /* We claim that this fixup has been processed here,
19577 even if in fact we generate an error because we do
19578 not have a reloc for it, so tc_gen_reloc will reject it. */
19582 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19585 _("undefined symbol %s used as an immediate value"),
19586 S_GET_NAME (fixP
->fx_addsy
));
19591 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19594 _("symbol %s is in a different section"),
19595 S_GET_NAME (fixP
->fx_addsy
));
19599 newimm
= encode_arm_immediate (value
);
19600 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19602 /* If the instruction will fail, see if we can fix things up by
19603 changing the opcode. */
19604 if (newimm
== (unsigned int) FAIL
19605 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19608 _("invalid constant (%lx) after fixup"),
19609 (unsigned long) value
);
19613 newimm
|= (temp
& 0xfffff000);
19614 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19617 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19619 unsigned int highpart
= 0;
19620 unsigned int newinsn
= 0xe1a00000; /* nop. */
19623 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19626 _("undefined symbol %s used as an immediate value"),
19627 S_GET_NAME (fixP
->fx_addsy
));
19632 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19635 _("symbol %s is in a different section"),
19636 S_GET_NAME (fixP
->fx_addsy
));
19640 newimm
= encode_arm_immediate (value
);
19641 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19643 /* If the instruction will fail, see if we can fix things up by
19644 changing the opcode. */
19645 if (newimm
== (unsigned int) FAIL
19646 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19648 /* No ? OK - try using two ADD instructions to generate
19650 newimm
= validate_immediate_twopart (value
, & highpart
);
19652 /* Yes - then make sure that the second instruction is
19654 if (newimm
!= (unsigned int) FAIL
)
19656 /* Still No ? Try using a negated value. */
19657 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19658 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19659 /* Otherwise - give up. */
19662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19663 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19668 /* Replace the first operand in the 2nd instruction (which
19669 is the PC) with the destination register. We have
19670 already added in the PC in the first instruction and we
19671 do not want to do it again. */
19672 newinsn
&= ~ 0xf0000;
19673 newinsn
|= ((newinsn
& 0x0f000) << 4);
19676 newimm
|= (temp
& 0xfffff000);
19677 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19679 highpart
|= (newinsn
& 0xfffff000);
19680 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19684 case BFD_RELOC_ARM_OFFSET_IMM
:
19685 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19688 case BFD_RELOC_ARM_LITERAL
:
19694 if (validate_offset_imm (value
, 0) == FAIL
)
19696 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19698 _("invalid literal constant: pool needs to be closer"));
19700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19701 _("bad immediate value for offset (%ld)"),
19706 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19707 newval
&= 0xff7ff000;
19708 newval
|= value
| (sign
? INDEX_UP
: 0);
19709 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19712 case BFD_RELOC_ARM_OFFSET_IMM8
:
19713 case BFD_RELOC_ARM_HWLITERAL
:
19719 if (validate_offset_imm (value
, 1) == FAIL
)
19721 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19723 _("invalid literal constant: pool needs to be closer"));
19725 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19730 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19731 newval
&= 0xff7ff0f0;
19732 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19733 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19736 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19737 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19739 _("bad immediate value for offset (%ld)"), (long) value
);
19742 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19744 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19747 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19748 /* This is a complicated relocation used for all varieties of Thumb32
19749 load/store instruction with immediate offset:
19751 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19752 *4, optional writeback(W)
19753 (doubleword load/store)
19755 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19756 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19757 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19758 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19759 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19761 Uppercase letters indicate bits that are already encoded at
19762 this point. Lowercase letters are our problem. For the
19763 second block of instructions, the secondary opcode nybble
19764 (bits 8..11) is present, and bit 23 is zero, even if this is
19765 a PC-relative operation. */
19766 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19768 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19770 if ((newval
& 0xf0000000) == 0xe0000000)
19772 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19774 newval
|= (1 << 23);
19777 if (value
% 4 != 0)
19779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19780 _("offset not a multiple of 4"));
19786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19787 _("offset out of range"));
19792 else if ((newval
& 0x000f0000) == 0x000f0000)
19794 /* PC-relative, 12-bit offset. */
19796 newval
|= (1 << 23);
19801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19802 _("offset out of range"));
19807 else if ((newval
& 0x00000100) == 0x00000100)
19809 /* Writeback: 8-bit, +/- offset. */
19811 newval
|= (1 << 9);
19816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19817 _("offset out of range"));
19822 else if ((newval
& 0x00000f00) == 0x00000e00)
19824 /* T-instruction: positive 8-bit offset. */
19825 if (value
< 0 || value
> 0xff)
19827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19828 _("offset out of range"));
19836 /* Positive 12-bit or negative 8-bit offset. */
19840 newval
|= (1 << 23);
19850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19851 _("offset out of range"));
19858 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19859 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19862 case BFD_RELOC_ARM_SHIFT_IMM
:
19863 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19864 if (((unsigned long) value
) > 32
19866 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19869 _("shift expression is too large"));
19874 /* Shifts of zero must be done as lsl. */
19876 else if (value
== 32)
19878 newval
&= 0xfffff07f;
19879 newval
|= (value
& 0x1f) << 7;
19880 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19883 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19884 case BFD_RELOC_ARM_T32_ADD_IMM
:
19885 case BFD_RELOC_ARM_T32_IMM12
:
19886 case BFD_RELOC_ARM_T32_ADD_PC12
:
19887 /* We claim that this fixup has been processed here,
19888 even if in fact we generate an error because we do
19889 not have a reloc for it, so tc_gen_reloc will reject it. */
19893 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19896 _("undefined symbol %s used as an immediate value"),
19897 S_GET_NAME (fixP
->fx_addsy
));
19901 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19903 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19906 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19907 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19909 newimm
= encode_thumb32_immediate (value
);
19910 if (newimm
== (unsigned int) FAIL
)
19911 newimm
= thumb32_negate_data_op (&newval
, value
);
19913 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19914 && newimm
== (unsigned int) FAIL
)
19916 /* Turn add/sum into addw/subw. */
19917 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19918 newval
= (newval
& 0xfeffffff) | 0x02000000;
19920 /* 12 bit immediate for addw/subw. */
19924 newval
^= 0x00a00000;
19927 newimm
= (unsigned int) FAIL
;
19932 if (newimm
== (unsigned int)FAIL
)
19934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19935 _("invalid constant (%lx) after fixup"),
19936 (unsigned long) value
);
19940 newval
|= (newimm
& 0x800) << 15;
19941 newval
|= (newimm
& 0x700) << 4;
19942 newval
|= (newimm
& 0x0ff);
19944 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19945 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19948 case BFD_RELOC_ARM_SMC
:
19949 if (((unsigned long) value
) > 0xffff)
19950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19951 _("invalid smc expression"));
19952 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19953 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19954 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19957 case BFD_RELOC_ARM_SWI
:
19958 if (fixP
->tc_fix_data
!= 0)
19960 if (((unsigned long) value
) > 0xff)
19961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19962 _("invalid swi expression"));
19963 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19965 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19969 if (((unsigned long) value
) > 0x00ffffff)
19970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19971 _("invalid swi expression"));
19972 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19974 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19978 case BFD_RELOC_ARM_MULTI
:
19979 if (((unsigned long) value
) > 0xffff)
19980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19981 _("invalid expression in load/store multiple"));
19982 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19983 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19987 case BFD_RELOC_ARM_PCREL_CALL
:
19989 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19991 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19992 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19993 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19994 /* Flip the bl to blx. This is a simple flip
19995 bit here because we generate PCREL_CALL for
19996 unconditional bls. */
19998 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19999 newval
= newval
| 0x10000000;
20000 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20006 goto arm_branch_common
;
20008 case BFD_RELOC_ARM_PCREL_JUMP
:
20009 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20011 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20012 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20013 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20015 /* This would map to a bl<cond>, b<cond>,
20016 b<always> to a Thumb function. We
20017 need to force a relocation for this particular
20019 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20023 case BFD_RELOC_ARM_PLT32
:
20025 case BFD_RELOC_ARM_PCREL_BRANCH
:
20027 goto arm_branch_common
;
20029 case BFD_RELOC_ARM_PCREL_BLX
:
20032 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20034 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20035 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20036 && ARM_IS_FUNC (fixP
->fx_addsy
))
20038 /* Flip the blx to a bl and warn. */
20039 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20040 newval
= 0xeb000000;
20041 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20042 _("blx to '%s' an ARM ISA state function changed to bl"),
20044 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20050 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20051 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20055 /* We are going to store value (shifted right by two) in the
20056 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20057 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20058 also be be clear. */
20060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20061 _("misaligned branch destination"));
20062 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20063 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20065 _("branch out of range"));
20067 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20069 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20070 newval
|= (value
>> 2) & 0x00ffffff;
20071 /* Set the H bit on BLX instructions. */
20075 newval
|= 0x01000000;
20077 newval
&= ~0x01000000;
20079 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20083 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20084 /* CBZ can only branch forward. */
20086 /* Attempts to use CBZ to branch to the next instruction
20087 (which, strictly speaking, are prohibited) will be turned into
20090 FIXME: It may be better to remove the instruction completely and
20091 perform relaxation. */
20094 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20095 newval
= 0xbf00; /* NOP encoding T1 */
20096 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20102 _("branch out of range"));
20104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20106 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20107 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20108 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20113 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20114 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20116 _("branch out of range"));
20118 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20120 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20121 newval
|= (value
& 0x1ff) >> 1;
20122 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20126 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20127 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20128 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20129 _("branch out of range"));
20131 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20133 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20134 newval
|= (value
& 0xfff) >> 1;
20135 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20139 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20141 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20142 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20143 && S_IS_DEFINED (fixP
->fx_addsy
)
20144 && ARM_IS_FUNC (fixP
->fx_addsy
)
20145 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20147 /* Force a relocation for a branch 20 bits wide. */
20150 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20152 _("conditional branch out of range"));
20154 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20157 addressT S
, J1
, J2
, lo
, hi
;
20159 S
= (value
& 0x00100000) >> 20;
20160 J2
= (value
& 0x00080000) >> 19;
20161 J1
= (value
& 0x00040000) >> 18;
20162 hi
= (value
& 0x0003f000) >> 12;
20163 lo
= (value
& 0x00000ffe) >> 1;
20165 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20166 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20167 newval
|= (S
<< 10) | hi
;
20168 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20170 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20174 case BFD_RELOC_THUMB_PCREL_BLX
:
20176 /* If there is a blx from a thumb state function to
20177 another thumb function flip this to a bl and warn
20181 && S_IS_DEFINED (fixP
->fx_addsy
)
20182 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20183 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20184 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20186 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20187 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20188 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20190 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20191 newval
= newval
| 0x1000;
20192 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20193 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20198 goto thumb_bl_common
;
20200 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20202 /* A bl from Thumb state ISA to an internal ARM state function
20203 is converted to a blx. */
20205 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20206 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20207 && S_IS_DEFINED (fixP
->fx_addsy
)
20208 && ARM_IS_FUNC (fixP
->fx_addsy
)
20209 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20211 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20212 newval
= newval
& ~0x1000;
20213 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20214 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20221 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20222 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20223 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20226 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20228 _("branch out of range"));
20230 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20231 /* For a BLX instruction, make sure that the relocation is rounded up
20232 to a word boundary. This follows the semantics of the instruction
20233 which specifies that bit 1 of the target address will come from bit
20234 1 of the base address. */
20235 value
= (value
+ 1) & ~ 1;
20237 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20241 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20242 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20243 newval
|= (value
& 0x7fffff) >> 12;
20244 newval2
|= (value
& 0xfff) >> 1;
20245 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20246 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20250 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20251 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20253 _("branch out of range"));
20255 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20258 addressT S
, I1
, I2
, lo
, hi
;
20260 S
= (value
& 0x01000000) >> 24;
20261 I1
= (value
& 0x00800000) >> 23;
20262 I2
= (value
& 0x00400000) >> 22;
20263 hi
= (value
& 0x003ff000) >> 12;
20264 lo
= (value
& 0x00000ffe) >> 1;
20269 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20270 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20271 newval
|= (S
<< 10) | hi
;
20272 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
20273 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20274 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20280 md_number_to_chars (buf
, value
, 1);
20284 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20285 md_number_to_chars (buf
, value
, 2);
20289 case BFD_RELOC_ARM_TLS_GD32
:
20290 case BFD_RELOC_ARM_TLS_LE32
:
20291 case BFD_RELOC_ARM_TLS_IE32
:
20292 case BFD_RELOC_ARM_TLS_LDM32
:
20293 case BFD_RELOC_ARM_TLS_LDO32
:
20294 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20297 case BFD_RELOC_ARM_GOT32
:
20298 case BFD_RELOC_ARM_GOTOFF
:
20299 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20300 md_number_to_chars (buf
, 0, 4);
20303 case BFD_RELOC_ARM_TARGET2
:
20304 /* TARGET2 is not partial-inplace, so we need to write the
20305 addend here for REL targets, because it won't be written out
20306 during reloc processing later. */
20307 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20308 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20312 case BFD_RELOC_RVA
:
20314 case BFD_RELOC_ARM_TARGET1
:
20315 case BFD_RELOC_ARM_ROSEGREL32
:
20316 case BFD_RELOC_ARM_SBREL32
:
20317 case BFD_RELOC_32_PCREL
:
20319 case BFD_RELOC_32_SECREL
:
20321 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20323 /* For WinCE we only do this for pcrel fixups. */
20324 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20326 md_number_to_chars (buf
, value
, 4);
20330 case BFD_RELOC_ARM_PREL31
:
20331 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20333 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20334 if ((value
^ (value
>> 1)) & 0x40000000)
20336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20337 _("rel31 relocation overflow"));
20339 newval
|= value
& 0x7fffffff;
20340 md_number_to_chars (buf
, newval
, 4);
20345 case BFD_RELOC_ARM_CP_OFF_IMM
:
20346 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20347 if (value
< -1023 || value
> 1023 || (value
& 3))
20348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20349 _("co-processor offset out of range"));
20354 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20355 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20356 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20358 newval
= get_thumb32_insn (buf
);
20359 newval
&= 0xff7fff00;
20360 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20361 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20362 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20363 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20365 put_thumb32_insn (buf
, newval
);
20368 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20369 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20370 if (value
< -255 || value
> 255)
20371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20372 _("co-processor offset out of range"));
20374 goto cp_off_common
;
20376 case BFD_RELOC_ARM_THUMB_OFFSET
:
20377 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20378 /* Exactly what ranges, and where the offset is inserted depends
20379 on the type of instruction, we can establish this from the
20381 switch (newval
>> 12)
20383 case 4: /* PC load. */
20384 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20385 forced to zero for these loads; md_pcrel_from has already
20386 compensated for this. */
20388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20389 _("invalid offset, target not word aligned (0x%08lX)"),
20390 (((unsigned long) fixP
->fx_frag
->fr_address
20391 + (unsigned long) fixP
->fx_where
) & ~3)
20392 + (unsigned long) value
);
20394 if (value
& ~0x3fc)
20395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20396 _("invalid offset, value too big (0x%08lX)"),
20399 newval
|= value
>> 2;
20402 case 9: /* SP load/store. */
20403 if (value
& ~0x3fc)
20404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20405 _("invalid offset, value too big (0x%08lX)"),
20407 newval
|= value
>> 2;
20410 case 6: /* Word load/store. */
20412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20413 _("invalid offset, value too big (0x%08lX)"),
20415 newval
|= value
<< 4; /* 6 - 2. */
20418 case 7: /* Byte load/store. */
20420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20421 _("invalid offset, value too big (0x%08lX)"),
20423 newval
|= value
<< 6;
20426 case 8: /* Halfword load/store. */
20428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20429 _("invalid offset, value too big (0x%08lX)"),
20431 newval
|= value
<< 5; /* 6 - 1. */
20435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20436 "Unable to process relocation for thumb opcode: %lx",
20437 (unsigned long) newval
);
20440 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20443 case BFD_RELOC_ARM_THUMB_ADD
:
20444 /* This is a complicated relocation, since we use it for all of
20445 the following immediate relocations:
20449 9bit ADD/SUB SP word-aligned
20450 10bit ADD PC/SP word-aligned
20452 The type of instruction being processed is encoded in the
20459 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20461 int rd
= (newval
>> 4) & 0xf;
20462 int rs
= newval
& 0xf;
20463 int subtract
= !!(newval
& 0x8000);
20465 /* Check for HI regs, only very restricted cases allowed:
20466 Adjusting SP, and using PC or SP to get an address. */
20467 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20468 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20470 _("invalid Hi register with immediate"));
20472 /* If value is negative, choose the opposite instruction. */
20476 subtract
= !subtract
;
20478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20479 _("immediate value out of range"));
20484 if (value
& ~0x1fc)
20485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20486 _("invalid immediate for stack address calculation"));
20487 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20488 newval
|= value
>> 2;
20490 else if (rs
== REG_PC
|| rs
== REG_SP
)
20492 if (subtract
|| value
& ~0x3fc)
20493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20494 _("invalid immediate for address calculation (value = 0x%08lX)"),
20495 (unsigned long) value
);
20496 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20498 newval
|= value
>> 2;
20503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20504 _("immediate value out of range"));
20505 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20506 newval
|= (rd
<< 8) | value
;
20511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20512 _("immediate value out of range"));
20513 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20514 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20517 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20520 case BFD_RELOC_ARM_THUMB_IMM
:
20521 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20522 if (value
< 0 || value
> 255)
20523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20524 _("invalid immediate: %ld is out of range"),
20527 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20530 case BFD_RELOC_ARM_THUMB_SHIFT
:
20531 /* 5bit shift value (0..32). LSL cannot take 32. */
20532 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20533 temp
= newval
& 0xf800;
20534 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20536 _("invalid shift value: %ld"), (long) value
);
20537 /* Shifts of zero must be encoded as LSL. */
20539 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20540 /* Shifts of 32 are encoded as zero. */
20541 else if (value
== 32)
20543 newval
|= value
<< 6;
20544 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20547 case BFD_RELOC_VTABLE_INHERIT
:
20548 case BFD_RELOC_VTABLE_ENTRY
:
20552 case BFD_RELOC_ARM_MOVW
:
20553 case BFD_RELOC_ARM_MOVT
:
20554 case BFD_RELOC_ARM_THUMB_MOVW
:
20555 case BFD_RELOC_ARM_THUMB_MOVT
:
20556 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20558 /* REL format relocations are limited to a 16-bit addend. */
20559 if (!fixP
->fx_done
)
20561 if (value
< -0x8000 || value
> 0x7fff)
20562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20563 _("offset out of range"));
20565 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20566 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20571 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20572 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20574 newval
= get_thumb32_insn (buf
);
20575 newval
&= 0xfbf08f00;
20576 newval
|= (value
& 0xf000) << 4;
20577 newval
|= (value
& 0x0800) << 15;
20578 newval
|= (value
& 0x0700) << 4;
20579 newval
|= (value
& 0x00ff);
20580 put_thumb32_insn (buf
, newval
);
20584 newval
= md_chars_to_number (buf
, 4);
20585 newval
&= 0xfff0f000;
20586 newval
|= value
& 0x0fff;
20587 newval
|= (value
& 0xf000) << 4;
20588 md_number_to_chars (buf
, newval
, 4);
20593 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20594 case BFD_RELOC_ARM_ALU_PC_G0
:
20595 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20596 case BFD_RELOC_ARM_ALU_PC_G1
:
20597 case BFD_RELOC_ARM_ALU_PC_G2
:
20598 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20599 case BFD_RELOC_ARM_ALU_SB_G0
:
20600 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20601 case BFD_RELOC_ARM_ALU_SB_G1
:
20602 case BFD_RELOC_ARM_ALU_SB_G2
:
20603 gas_assert (!fixP
->fx_done
);
20604 if (!seg
->use_rela_p
)
20607 bfd_vma encoded_addend
;
20608 bfd_vma addend_abs
= abs (value
);
20610 /* Check that the absolute value of the addend can be
20611 expressed as an 8-bit constant plus a rotation. */
20612 encoded_addend
= encode_arm_immediate (addend_abs
);
20613 if (encoded_addend
== (unsigned int) FAIL
)
20614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20615 _("the offset 0x%08lX is not representable"),
20616 (unsigned long) addend_abs
);
20618 /* Extract the instruction. */
20619 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20621 /* If the addend is positive, use an ADD instruction.
20622 Otherwise use a SUB. Take care not to destroy the S bit. */
20623 insn
&= 0xff1fffff;
20629 /* Place the encoded addend into the first 12 bits of the
20631 insn
&= 0xfffff000;
20632 insn
|= encoded_addend
;
20634 /* Update the instruction. */
20635 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20639 case BFD_RELOC_ARM_LDR_PC_G0
:
20640 case BFD_RELOC_ARM_LDR_PC_G1
:
20641 case BFD_RELOC_ARM_LDR_PC_G2
:
20642 case BFD_RELOC_ARM_LDR_SB_G0
:
20643 case BFD_RELOC_ARM_LDR_SB_G1
:
20644 case BFD_RELOC_ARM_LDR_SB_G2
:
20645 gas_assert (!fixP
->fx_done
);
20646 if (!seg
->use_rela_p
)
20649 bfd_vma addend_abs
= abs (value
);
20651 /* Check that the absolute value of the addend can be
20652 encoded in 12 bits. */
20653 if (addend_abs
>= 0x1000)
20654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20655 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20656 (unsigned long) addend_abs
);
20658 /* Extract the instruction. */
20659 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20661 /* If the addend is negative, clear bit 23 of the instruction.
20662 Otherwise set it. */
20664 insn
&= ~(1 << 23);
20668 /* Place the absolute value of the addend into the first 12 bits
20669 of the instruction. */
20670 insn
&= 0xfffff000;
20671 insn
|= addend_abs
;
20673 /* Update the instruction. */
20674 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20678 case BFD_RELOC_ARM_LDRS_PC_G0
:
20679 case BFD_RELOC_ARM_LDRS_PC_G1
:
20680 case BFD_RELOC_ARM_LDRS_PC_G2
:
20681 case BFD_RELOC_ARM_LDRS_SB_G0
:
20682 case BFD_RELOC_ARM_LDRS_SB_G1
:
20683 case BFD_RELOC_ARM_LDRS_SB_G2
:
20684 gas_assert (!fixP
->fx_done
);
20685 if (!seg
->use_rela_p
)
20688 bfd_vma addend_abs
= abs (value
);
20690 /* Check that the absolute value of the addend can be
20691 encoded in 8 bits. */
20692 if (addend_abs
>= 0x100)
20693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20694 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20695 (unsigned long) addend_abs
);
20697 /* Extract the instruction. */
20698 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20700 /* If the addend is negative, clear bit 23 of the instruction.
20701 Otherwise set it. */
20703 insn
&= ~(1 << 23);
20707 /* Place the first four bits of the absolute value of the addend
20708 into the first 4 bits of the instruction, and the remaining
20709 four into bits 8 .. 11. */
20710 insn
&= 0xfffff0f0;
20711 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20713 /* Update the instruction. */
20714 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20718 case BFD_RELOC_ARM_LDC_PC_G0
:
20719 case BFD_RELOC_ARM_LDC_PC_G1
:
20720 case BFD_RELOC_ARM_LDC_PC_G2
:
20721 case BFD_RELOC_ARM_LDC_SB_G0
:
20722 case BFD_RELOC_ARM_LDC_SB_G1
:
20723 case BFD_RELOC_ARM_LDC_SB_G2
:
20724 gas_assert (!fixP
->fx_done
);
20725 if (!seg
->use_rela_p
)
20728 bfd_vma addend_abs
= abs (value
);
20730 /* Check that the absolute value of the addend is a multiple of
20731 four and, when divided by four, fits in 8 bits. */
20732 if (addend_abs
& 0x3)
20733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20734 _("bad offset 0x%08lX (must be word-aligned)"),
20735 (unsigned long) addend_abs
);
20737 if ((addend_abs
>> 2) > 0xff)
20738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20739 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20740 (unsigned long) addend_abs
);
20742 /* Extract the instruction. */
20743 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20745 /* If the addend is negative, clear bit 23 of the instruction.
20746 Otherwise set it. */
20748 insn
&= ~(1 << 23);
20752 /* Place the addend (divided by four) into the first eight
20753 bits of the instruction. */
20754 insn
&= 0xfffffff0;
20755 insn
|= addend_abs
>> 2;
20757 /* Update the instruction. */
20758 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20762 case BFD_RELOC_ARM_V4BX
:
20763 /* This will need to go in the object file. */
20767 case BFD_RELOC_UNUSED
:
20769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20770 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20774 /* Translate internal representation of relocation info to BFD target
20778 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20781 bfd_reloc_code_real_type code
;
20783 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20785 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20786 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20787 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20789 if (fixp
->fx_pcrel
)
20791 if (section
->use_rela_p
)
20792 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20794 fixp
->fx_offset
= reloc
->address
;
20796 reloc
->addend
= fixp
->fx_offset
;
20798 switch (fixp
->fx_r_type
)
20801 if (fixp
->fx_pcrel
)
20803 code
= BFD_RELOC_8_PCREL
;
20808 if (fixp
->fx_pcrel
)
20810 code
= BFD_RELOC_16_PCREL
;
20815 if (fixp
->fx_pcrel
)
20817 code
= BFD_RELOC_32_PCREL
;
20821 case BFD_RELOC_ARM_MOVW
:
20822 if (fixp
->fx_pcrel
)
20824 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20828 case BFD_RELOC_ARM_MOVT
:
20829 if (fixp
->fx_pcrel
)
20831 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20835 case BFD_RELOC_ARM_THUMB_MOVW
:
20836 if (fixp
->fx_pcrel
)
20838 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20842 case BFD_RELOC_ARM_THUMB_MOVT
:
20843 if (fixp
->fx_pcrel
)
20845 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20849 case BFD_RELOC_NONE
:
20850 case BFD_RELOC_ARM_PCREL_BRANCH
:
20851 case BFD_RELOC_ARM_PCREL_BLX
:
20852 case BFD_RELOC_RVA
:
20853 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20854 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20855 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20856 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20857 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20858 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20859 case BFD_RELOC_VTABLE_ENTRY
:
20860 case BFD_RELOC_VTABLE_INHERIT
:
20862 case BFD_RELOC_32_SECREL
:
20864 code
= fixp
->fx_r_type
;
20867 case BFD_RELOC_THUMB_PCREL_BLX
:
20869 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20870 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20873 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20876 case BFD_RELOC_ARM_LITERAL
:
20877 case BFD_RELOC_ARM_HWLITERAL
:
20878 /* If this is called then the a literal has
20879 been referenced across a section boundary. */
20880 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20881 _("literal referenced across section boundary"));
20885 case BFD_RELOC_ARM_GOT32
:
20886 case BFD_RELOC_ARM_GOTOFF
:
20887 case BFD_RELOC_ARM_PLT32
:
20888 case BFD_RELOC_ARM_TARGET1
:
20889 case BFD_RELOC_ARM_ROSEGREL32
:
20890 case BFD_RELOC_ARM_SBREL32
:
20891 case BFD_RELOC_ARM_PREL31
:
20892 case BFD_RELOC_ARM_TARGET2
:
20893 case BFD_RELOC_ARM_TLS_LE32
:
20894 case BFD_RELOC_ARM_TLS_LDO32
:
20895 case BFD_RELOC_ARM_PCREL_CALL
:
20896 case BFD_RELOC_ARM_PCREL_JUMP
:
20897 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20898 case BFD_RELOC_ARM_ALU_PC_G0
:
20899 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20900 case BFD_RELOC_ARM_ALU_PC_G1
:
20901 case BFD_RELOC_ARM_ALU_PC_G2
:
20902 case BFD_RELOC_ARM_LDR_PC_G0
:
20903 case BFD_RELOC_ARM_LDR_PC_G1
:
20904 case BFD_RELOC_ARM_LDR_PC_G2
:
20905 case BFD_RELOC_ARM_LDRS_PC_G0
:
20906 case BFD_RELOC_ARM_LDRS_PC_G1
:
20907 case BFD_RELOC_ARM_LDRS_PC_G2
:
20908 case BFD_RELOC_ARM_LDC_PC_G0
:
20909 case BFD_RELOC_ARM_LDC_PC_G1
:
20910 case BFD_RELOC_ARM_LDC_PC_G2
:
20911 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20912 case BFD_RELOC_ARM_ALU_SB_G0
:
20913 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20914 case BFD_RELOC_ARM_ALU_SB_G1
:
20915 case BFD_RELOC_ARM_ALU_SB_G2
:
20916 case BFD_RELOC_ARM_LDR_SB_G0
:
20917 case BFD_RELOC_ARM_LDR_SB_G1
:
20918 case BFD_RELOC_ARM_LDR_SB_G2
:
20919 case BFD_RELOC_ARM_LDRS_SB_G0
:
20920 case BFD_RELOC_ARM_LDRS_SB_G1
:
20921 case BFD_RELOC_ARM_LDRS_SB_G2
:
20922 case BFD_RELOC_ARM_LDC_SB_G0
:
20923 case BFD_RELOC_ARM_LDC_SB_G1
:
20924 case BFD_RELOC_ARM_LDC_SB_G2
:
20925 case BFD_RELOC_ARM_V4BX
:
20926 code
= fixp
->fx_r_type
;
20929 case BFD_RELOC_ARM_TLS_GD32
:
20930 case BFD_RELOC_ARM_TLS_IE32
:
20931 case BFD_RELOC_ARM_TLS_LDM32
:
20932 /* BFD will include the symbol's address in the addend.
20933 But we don't want that, so subtract it out again here. */
20934 if (!S_IS_COMMON (fixp
->fx_addsy
))
20935 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20936 code
= fixp
->fx_r_type
;
20940 case BFD_RELOC_ARM_IMMEDIATE
:
20941 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20942 _("internal relocation (type: IMMEDIATE) not fixed up"));
20945 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20946 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20947 _("ADRL used for a symbol not defined in the same file"));
20950 case BFD_RELOC_ARM_OFFSET_IMM
:
20951 if (section
->use_rela_p
)
20953 code
= fixp
->fx_r_type
;
20957 if (fixp
->fx_addsy
!= NULL
20958 && !S_IS_DEFINED (fixp
->fx_addsy
)
20959 && S_IS_LOCAL (fixp
->fx_addsy
))
20961 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20962 _("undefined local label `%s'"),
20963 S_GET_NAME (fixp
->fx_addsy
));
20967 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20968 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20975 switch (fixp
->fx_r_type
)
20977 case BFD_RELOC_NONE
: type
= "NONE"; break;
20978 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20979 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20980 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20981 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20982 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20983 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20984 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20985 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20986 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20987 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20988 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20989 default: type
= _("<unknown>"); break;
20991 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20992 _("cannot represent %s relocation in this object file format"),
20999 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21001 && fixp
->fx_addsy
== GOT_symbol
)
21003 code
= BFD_RELOC_ARM_GOTPC
;
21004 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21008 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21010 if (reloc
->howto
== NULL
)
21012 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21013 _("cannot represent %s relocation in this object file format"),
21014 bfd_get_reloc_code_name (code
));
21018 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21019 vtable entry to be used in the relocation's section offset. */
21020 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21021 reloc
->address
= fixp
->fx_offset
;
21026 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21029 cons_fix_new_arm (fragS
* frag
,
21034 bfd_reloc_code_real_type type
;
21038 FIXME: @@ Should look at CPU word size. */
21042 type
= BFD_RELOC_8
;
21045 type
= BFD_RELOC_16
;
21049 type
= BFD_RELOC_32
;
21052 type
= BFD_RELOC_64
;
21057 if (exp
->X_op
== O_secrel
)
21059 exp
->X_op
= O_symbol
;
21060 type
= BFD_RELOC_32_SECREL
;
21064 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21067 #if defined (OBJ_COFF)
21069 arm_validate_fix (fixS
* fixP
)
21071 /* If the destination of the branch is a defined symbol which does not have
21072 the THUMB_FUNC attribute, then we must be calling a function which has
21073 the (interfacearm) attribute. We look for the Thumb entry point to that
21074 function and change the branch to refer to that function instead. */
21075 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21076 && fixP
->fx_addsy
!= NULL
21077 && S_IS_DEFINED (fixP
->fx_addsy
)
21078 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21080 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21087 arm_force_relocation (struct fix
* fixp
)
21089 #if defined (OBJ_COFF) && defined (TE_PE)
21090 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21094 /* In case we have a call or a branch to a function in ARM ISA mode from
21095 a thumb function or vice-versa force the relocation. These relocations
21096 are cleared off for some cores that might have blx and simple transformations
21100 switch (fixp
->fx_r_type
)
21102 case BFD_RELOC_ARM_PCREL_JUMP
:
21103 case BFD_RELOC_ARM_PCREL_CALL
:
21104 case BFD_RELOC_THUMB_PCREL_BLX
:
21105 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21109 case BFD_RELOC_ARM_PCREL_BLX
:
21110 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21111 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21112 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21113 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21122 /* Resolve these relocations even if the symbol is extern or weak. */
21123 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21124 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21125 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21126 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21127 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21128 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21129 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21132 /* Always leave these relocations for the linker. */
21133 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21134 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21135 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21138 /* Always generate relocations against function symbols. */
21139 if (fixp
->fx_r_type
== BFD_RELOC_32
21141 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21144 return generic_force_reloc (fixp
);
21147 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21148 /* Relocations against function names must be left unadjusted,
21149 so that the linker can use this information to generate interworking
21150 stubs. The MIPS version of this function
21151 also prevents relocations that are mips-16 specific, but I do not
21152 know why it does this.
21155 There is one other problem that ought to be addressed here, but
21156 which currently is not: Taking the address of a label (rather
21157 than a function) and then later jumping to that address. Such
21158 addresses also ought to have their bottom bit set (assuming that
21159 they reside in Thumb code), but at the moment they will not. */
21162 arm_fix_adjustable (fixS
* fixP
)
21164 if (fixP
->fx_addsy
== NULL
)
21167 /* Preserve relocations against symbols with function type. */
21168 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21171 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21172 && fixP
->fx_subsy
== NULL
)
21175 /* We need the symbol name for the VTABLE entries. */
21176 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21177 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21180 /* Don't allow symbols to be discarded on GOT related relocs. */
21181 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21182 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21183 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21184 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21185 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21186 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21187 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21188 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21189 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21192 /* Similarly for group relocations. */
21193 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21194 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21195 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21198 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21199 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21200 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21201 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21202 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21203 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21204 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21205 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21206 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21211 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21216 elf32_arm_target_format (void)
21219 return (target_big_endian
21220 ? "elf32-bigarm-symbian"
21221 : "elf32-littlearm-symbian");
21222 #elif defined (TE_VXWORKS)
21223 return (target_big_endian
21224 ? "elf32-bigarm-vxworks"
21225 : "elf32-littlearm-vxworks");
21227 if (target_big_endian
)
21228 return "elf32-bigarm";
21230 return "elf32-littlearm";
21235 armelf_frob_symbol (symbolS
* symp
,
21238 elf_frob_symbol (symp
, puntp
);
21242 /* MD interface: Finalization. */
21247 literal_pool
* pool
;
21249 /* Ensure that all the IT blocks are properly closed. */
21250 check_it_blocks_finished ();
21252 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21254 /* Put it at the end of the relevant section. */
21255 subseg_set (pool
->section
, pool
->sub_section
);
21257 arm_elf_change_section ();
21264 /* Remove any excess mapping symbols generated for alignment frags in
21265 SEC. We may have created a mapping symbol before a zero byte
21266 alignment; remove it if there's a mapping symbol after the
21269 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21270 void *dummy ATTRIBUTE_UNUSED
)
21272 segment_info_type
*seginfo
= seg_info (sec
);
21275 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21278 for (fragp
= seginfo
->frchainP
->frch_root
;
21280 fragp
= fragp
->fr_next
)
21282 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21283 fragS
*next
= fragp
->fr_next
;
21285 /* Variable-sized frags have been converted to fixed size by
21286 this point. But if this was variable-sized to start with,
21287 there will be a fixed-size frag after it. So don't handle
21289 if (sym
== NULL
|| next
== NULL
)
21292 if (S_GET_VALUE (sym
) < next
->fr_address
)
21293 /* Not at the end of this frag. */
21295 know (S_GET_VALUE (sym
) == next
->fr_address
);
21299 if (next
->tc_frag_data
.first_map
!= NULL
)
21301 /* Next frag starts with a mapping symbol. Discard this
21303 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21307 if (next
->fr_next
== NULL
)
21309 /* This mapping symbol is at the end of the section. Discard
21311 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21312 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21316 /* As long as we have empty frags without any mapping symbols,
21318 /* If the next frag is non-empty and does not start with a
21319 mapping symbol, then this mapping symbol is required. */
21320 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21323 next
= next
->fr_next
;
21325 while (next
!= NULL
);
21330 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21334 arm_adjust_symtab (void)
21339 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21341 if (ARM_IS_THUMB (sym
))
21343 if (THUMB_IS_FUNC (sym
))
21345 /* Mark the symbol as a Thumb function. */
21346 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21347 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21348 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21350 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21351 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21353 as_bad (_("%s: unexpected function type: %d"),
21354 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21356 else switch (S_GET_STORAGE_CLASS (sym
))
21359 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21362 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21365 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21373 if (ARM_IS_INTERWORK (sym
))
21374 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21381 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21383 if (ARM_IS_THUMB (sym
))
21385 elf_symbol_type
* elf_sym
;
21387 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21388 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21390 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21391 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21393 /* If it's a .thumb_func, declare it as so,
21394 otherwise tag label as .code 16. */
21395 if (THUMB_IS_FUNC (sym
))
21396 elf_sym
->internal_elf_sym
.st_info
=
21397 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21398 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21399 elf_sym
->internal_elf_sym
.st_info
=
21400 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21405 /* Remove any overlapping mapping symbols generated by alignment frags. */
21406 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21410 /* MD interface: Initialization. */
21413 set_constant_flonums (void)
21417 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21418 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21422 /* Auto-select Thumb mode if it's the only available instruction set for the
21423 given architecture. */
21426 autoselect_thumb_from_cpu_variant (void)
21428 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21429 opcode_select (16);
21438 if ( (arm_ops_hsh
= hash_new ()) == NULL
21439 || (arm_cond_hsh
= hash_new ()) == NULL
21440 || (arm_shift_hsh
= hash_new ()) == NULL
21441 || (arm_psr_hsh
= hash_new ()) == NULL
21442 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21443 || (arm_reg_hsh
= hash_new ()) == NULL
21444 || (arm_reloc_hsh
= hash_new ()) == NULL
21445 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21446 as_fatal (_("virtual memory exhausted"));
21448 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21449 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21450 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21451 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21452 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21453 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21454 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21455 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21456 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21457 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21458 (void *) (v7m_psrs
+ i
));
21459 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21460 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21462 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21464 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21465 (void *) (barrier_opt_names
+ i
));
21467 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21468 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21471 set_constant_flonums ();
21473 /* Set the cpu variant based on the command-line options. We prefer
21474 -mcpu= over -march= if both are set (as for GCC); and we prefer
21475 -mfpu= over any other way of setting the floating point unit.
21476 Use of legacy options with new options are faulted. */
21479 if (mcpu_cpu_opt
|| march_cpu_opt
)
21480 as_bad (_("use of old and new-style options to set CPU type"));
21482 mcpu_cpu_opt
= legacy_cpu
;
21484 else if (!mcpu_cpu_opt
)
21485 mcpu_cpu_opt
= march_cpu_opt
;
21490 as_bad (_("use of old and new-style options to set FPU type"));
21492 mfpu_opt
= legacy_fpu
;
21494 else if (!mfpu_opt
)
21496 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21497 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21498 /* Some environments specify a default FPU. If they don't, infer it
21499 from the processor. */
21501 mfpu_opt
= mcpu_fpu_opt
;
21503 mfpu_opt
= march_fpu_opt
;
21505 mfpu_opt
= &fpu_default
;
21511 if (mcpu_cpu_opt
!= NULL
)
21512 mfpu_opt
= &fpu_default
;
21513 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21514 mfpu_opt
= &fpu_arch_vfp_v2
;
21516 mfpu_opt
= &fpu_arch_fpa
;
21522 mcpu_cpu_opt
= &cpu_default
;
21523 selected_cpu
= cpu_default
;
21527 selected_cpu
= *mcpu_cpu_opt
;
21529 mcpu_cpu_opt
= &arm_arch_any
;
21532 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21534 autoselect_thumb_from_cpu_variant ();
21536 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21538 #if defined OBJ_COFF || defined OBJ_ELF
21540 unsigned int flags
= 0;
21542 #if defined OBJ_ELF
21543 flags
= meabi_flags
;
21545 switch (meabi_flags
)
21547 case EF_ARM_EABI_UNKNOWN
:
21549 /* Set the flags in the private structure. */
21550 if (uses_apcs_26
) flags
|= F_APCS26
;
21551 if (support_interwork
) flags
|= F_INTERWORK
;
21552 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21553 if (pic_code
) flags
|= F_PIC
;
21554 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21555 flags
|= F_SOFT_FLOAT
;
21557 switch (mfloat_abi_opt
)
21559 case ARM_FLOAT_ABI_SOFT
:
21560 case ARM_FLOAT_ABI_SOFTFP
:
21561 flags
|= F_SOFT_FLOAT
;
21564 case ARM_FLOAT_ABI_HARD
:
21565 if (flags
& F_SOFT_FLOAT
)
21566 as_bad (_("hard-float conflicts with specified fpu"));
21570 /* Using pure-endian doubles (even if soft-float). */
21571 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21572 flags
|= F_VFP_FLOAT
;
21574 #if defined OBJ_ELF
21575 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21576 flags
|= EF_ARM_MAVERICK_FLOAT
;
21579 case EF_ARM_EABI_VER4
:
21580 case EF_ARM_EABI_VER5
:
21581 /* No additional flags to set. */
21588 bfd_set_private_flags (stdoutput
, flags
);
21590 /* We have run out flags in the COFF header to encode the
21591 status of ATPCS support, so instead we create a dummy,
21592 empty, debug section called .arm.atpcs. */
21597 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21601 bfd_set_section_flags
21602 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21603 bfd_set_section_size (stdoutput
, sec
, 0);
21604 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21610 /* Record the CPU type as well. */
21611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21612 mach
= bfd_mach_arm_iWMMXt2
;
21613 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21614 mach
= bfd_mach_arm_iWMMXt
;
21615 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21616 mach
= bfd_mach_arm_XScale
;
21617 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21618 mach
= bfd_mach_arm_ep9312
;
21619 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21620 mach
= bfd_mach_arm_5TE
;
21621 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21623 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21624 mach
= bfd_mach_arm_5T
;
21626 mach
= bfd_mach_arm_5
;
21628 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21630 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21631 mach
= bfd_mach_arm_4T
;
21633 mach
= bfd_mach_arm_4
;
21635 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21636 mach
= bfd_mach_arm_3M
;
21637 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21638 mach
= bfd_mach_arm_3
;
21639 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21640 mach
= bfd_mach_arm_2a
;
21641 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21642 mach
= bfd_mach_arm_2
;
21644 mach
= bfd_mach_arm_unknown
;
21646 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21649 /* Command line processing. */
21652 Invocation line includes a switch not recognized by the base assembler.
21653 See if it's a processor-specific option.
21655 This routine is somewhat complicated by the need for backwards
21656 compatibility (since older releases of gcc can't be changed).
21657 The new options try to make the interface as compatible as
21660 New options (supported) are:
21662 -mcpu=<cpu name> Assemble for selected processor
21663 -march=<architecture name> Assemble for selected architecture
21664 -mfpu=<fpu architecture> Assemble for selected FPU.
21665 -EB/-mbig-endian Big-endian
21666 -EL/-mlittle-endian Little-endian
21667 -k Generate PIC code
21668 -mthumb Start in Thumb mode
21669 -mthumb-interwork Code supports ARM/Thumb interworking
21671 -m[no-]warn-deprecated Warn about deprecated features
21673 For now we will also provide support for:
21675 -mapcs-32 32-bit Program counter
21676 -mapcs-26 26-bit Program counter
21677 -macps-float Floats passed in FP registers
21678 -mapcs-reentrant Reentrant code
21680 (sometime these will probably be replaced with -mapcs=<list of options>
21681 and -matpcs=<list of options>)
21683 The remaining options are only supported for back-wards compatibility.
21684 Cpu variants, the arm part is optional:
21685 -m[arm]1 Currently not supported.
21686 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21687 -m[arm]3 Arm 3 processor
21688 -m[arm]6[xx], Arm 6 processors
21689 -m[arm]7[xx][t][[d]m] Arm 7 processors
21690 -m[arm]8[10] Arm 8 processors
21691 -m[arm]9[20][tdmi] Arm 9 processors
21692 -mstrongarm[110[0]] StrongARM processors
21693 -mxscale XScale processors
21694 -m[arm]v[2345[t[e]]] Arm architectures
21695 -mall All (except the ARM1)
21697 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21698 -mfpe-old (No float load/store multiples)
21699 -mvfpxd VFP Single precision
21701 -mno-fpu Disable all floating point instructions
21703 The following CPU names are recognized:
21704 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21705 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21706 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21707 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21708 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21709 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21710 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21714 const char * md_shortopts
= "m:k";
21716 #ifdef ARM_BI_ENDIAN
21717 #define OPTION_EB (OPTION_MD_BASE + 0)
21718 #define OPTION_EL (OPTION_MD_BASE + 1)
21720 #if TARGET_BYTES_BIG_ENDIAN
21721 #define OPTION_EB (OPTION_MD_BASE + 0)
21723 #define OPTION_EL (OPTION_MD_BASE + 1)
21726 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21728 struct option md_longopts
[] =
21731 {"EB", no_argument
, NULL
, OPTION_EB
},
21734 {"EL", no_argument
, NULL
, OPTION_EL
},
21736 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21737 {NULL
, no_argument
, NULL
, 0}
21740 size_t md_longopts_size
= sizeof (md_longopts
);
21742 struct arm_option_table
21744 char *option
; /* Option name to match. */
21745 char *help
; /* Help information. */
21746 int *var
; /* Variable to change. */
21747 int value
; /* What to change it to. */
21748 char *deprecated
; /* If non-null, print this message. */
21751 struct arm_option_table arm_opts
[] =
21753 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21754 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21755 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21756 &support_interwork
, 1, NULL
},
21757 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21758 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21759 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21761 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21762 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21763 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21764 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21767 /* These are recognized by the assembler, but have no affect on code. */
21768 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21769 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21771 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21772 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21773 &warn_on_deprecated
, 0, NULL
},
21774 {NULL
, NULL
, NULL
, 0, NULL
}
21777 struct arm_legacy_option_table
21779 char *option
; /* Option name to match. */
21780 const arm_feature_set
**var
; /* Variable to change. */
21781 const arm_feature_set value
; /* What to change it to. */
21782 char *deprecated
; /* If non-null, print this message. */
21785 const struct arm_legacy_option_table arm_legacy_opts
[] =
21787 /* DON'T add any new processors to this list -- we want the whole list
21788 to go away... Add them to the processors table instead. */
21789 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21790 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21791 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21792 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21793 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21794 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21795 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21796 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21797 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21798 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21799 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21800 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21801 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21802 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21803 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21804 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21805 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21806 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21807 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21808 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21809 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21810 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21811 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21812 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21813 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21814 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21815 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21816 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21817 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21818 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21819 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21820 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21821 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21822 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21823 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21824 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21825 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21826 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21827 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21828 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21829 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21830 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21831 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21832 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21833 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21834 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21835 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21836 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21837 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21838 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21839 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21840 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21841 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21842 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21843 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21844 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21845 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21846 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21847 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21848 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21849 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21850 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21851 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21852 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21853 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21854 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21855 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21856 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21857 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21858 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21859 N_("use -mcpu=strongarm110")},
21860 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21861 N_("use -mcpu=strongarm1100")},
21862 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21863 N_("use -mcpu=strongarm1110")},
21864 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21865 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21866 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21868 /* Architecture variants -- don't add any more to this list either. */
21869 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21870 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21871 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21872 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21873 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21874 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21875 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21876 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21877 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21878 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21879 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21880 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21881 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21882 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21883 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21884 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21885 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21886 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21888 /* Floating point variants -- don't add any more to this list either. */
21889 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21890 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21891 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21892 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21893 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21895 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21898 struct arm_cpu_option_table
21901 const arm_feature_set value
;
21902 /* For some CPUs we assume an FPU unless the user explicitly sets
21904 const arm_feature_set default_fpu
;
21905 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21907 const char *canonical_name
;
21910 /* This list should, at a minimum, contain all the cpu names
21911 recognized by GCC. */
21912 static const struct arm_cpu_option_table arm_cpus
[] =
21914 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21915 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21916 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21917 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21918 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21919 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21920 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21921 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21922 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21923 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21924 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21925 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21926 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21927 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21928 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21929 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21930 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21931 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21932 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21933 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21934 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21935 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21936 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21937 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21938 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21939 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21940 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21941 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21942 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21943 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21944 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21945 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21946 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21947 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21948 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21949 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21950 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21951 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21952 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21953 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21954 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21955 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21956 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21957 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21958 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21959 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21960 /* For V5 or later processors we default to using VFP; but the user
21961 should really set the FPU type explicitly. */
21962 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21963 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21964 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21965 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21966 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21967 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21968 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21969 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21970 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21971 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21972 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21973 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21974 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21975 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21976 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21977 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21978 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21979 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21980 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21981 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21982 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21983 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21984 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21985 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21986 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21987 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21988 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21989 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21990 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21991 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21992 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21993 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21994 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21995 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
21996 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21997 | FPU_NEON_EXT_V1
),
21999 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22000 | FPU_NEON_EXT_V1
),
22002 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22003 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22004 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22005 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22006 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22007 /* ??? XSCALE is really an architecture. */
22008 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22009 /* ??? iwmmxt is not a processor. */
22010 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22011 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22012 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22014 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22015 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22018 struct arm_arch_option_table
22021 const arm_feature_set value
;
22022 const arm_feature_set default_fpu
;
22025 /* This list should, at a minimum, contain all the architecture names
22026 recognized by GCC. */
22027 static const struct arm_arch_option_table arm_archs
[] =
22029 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22030 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22031 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22032 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22033 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22034 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22035 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22036 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22037 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22038 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22039 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22040 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22041 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22042 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22043 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22044 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22045 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22046 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22047 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22048 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22049 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22050 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22051 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22052 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22053 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22054 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22055 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22056 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22057 /* The official spelling of the ARMv7 profile variants is the dashed form.
22058 Accept the non-dashed form for compatibility with old toolchains. */
22059 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22060 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22061 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22062 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22063 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22064 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22065 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22066 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22067 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22068 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22069 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22072 /* ISA extensions in the co-processor space. */
22073 struct arm_option_cpu_value_table
22076 const arm_feature_set value
;
22079 static const struct arm_option_cpu_value_table arm_extensions
[] =
22081 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22082 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22083 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22084 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22085 {NULL
, ARM_ARCH_NONE
}
22088 /* This list should, at a minimum, contain all the fpu names
22089 recognized by GCC. */
22090 static const struct arm_option_cpu_value_table arm_fpus
[] =
22092 {"softfpa", FPU_NONE
},
22093 {"fpe", FPU_ARCH_FPE
},
22094 {"fpe2", FPU_ARCH_FPE
},
22095 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22096 {"fpa", FPU_ARCH_FPA
},
22097 {"fpa10", FPU_ARCH_FPA
},
22098 {"fpa11", FPU_ARCH_FPA
},
22099 {"arm7500fe", FPU_ARCH_FPA
},
22100 {"softvfp", FPU_ARCH_VFP
},
22101 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22102 {"vfp", FPU_ARCH_VFP_V2
},
22103 {"vfp9", FPU_ARCH_VFP_V2
},
22104 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22105 {"vfp10", FPU_ARCH_VFP_V2
},
22106 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22107 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22108 {"vfpv2", FPU_ARCH_VFP_V2
},
22109 {"vfpv3", FPU_ARCH_VFP_V3
},
22110 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22111 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22112 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22113 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22114 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22115 {"arm1020t", FPU_ARCH_VFP_V1
},
22116 {"arm1020e", FPU_ARCH_VFP_V2
},
22117 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22118 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22119 {"maverick", FPU_ARCH_MAVERICK
},
22120 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22121 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22122 {"vfpv4", FPU_ARCH_VFP_V4
},
22123 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22124 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22125 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22126 {NULL
, ARM_ARCH_NONE
}
22129 struct arm_option_value_table
22135 static const struct arm_option_value_table arm_float_abis
[] =
22137 {"hard", ARM_FLOAT_ABI_HARD
},
22138 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22139 {"soft", ARM_FLOAT_ABI_SOFT
},
22144 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22145 static const struct arm_option_value_table arm_eabis
[] =
22147 {"gnu", EF_ARM_EABI_UNKNOWN
},
22148 {"4", EF_ARM_EABI_VER4
},
22149 {"5", EF_ARM_EABI_VER5
},
22154 struct arm_long_option_table
22156 char * option
; /* Substring to match. */
22157 char * help
; /* Help information. */
22158 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22159 char * deprecated
; /* If non-null, print this message. */
22163 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22165 arm_feature_set
*ext_set
= (arm_feature_set
*)
22166 xmalloc (sizeof (arm_feature_set
));
22168 /* Copy the feature set, so that we can modify it. */
22169 *ext_set
= **opt_p
;
22172 while (str
!= NULL
&& *str
!= 0)
22174 const struct arm_option_cpu_value_table
* opt
;
22180 as_bad (_("invalid architectural extension"));
22185 ext
= strchr (str
, '+');
22188 optlen
= ext
- str
;
22190 optlen
= strlen (str
);
22194 as_bad (_("missing architectural extension"));
22198 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22199 if (strncmp (opt
->name
, str
, optlen
) == 0)
22201 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22205 if (opt
->name
== NULL
)
22207 as_bad (_("unknown architectural extension `%s'"), str
);
22218 arm_parse_cpu (char * str
)
22220 const struct arm_cpu_option_table
* opt
;
22221 char * ext
= strchr (str
, '+');
22225 optlen
= ext
- str
;
22227 optlen
= strlen (str
);
22231 as_bad (_("missing cpu name `%s'"), str
);
22235 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22236 if (strncmp (opt
->name
, str
, optlen
) == 0)
22238 mcpu_cpu_opt
= &opt
->value
;
22239 mcpu_fpu_opt
= &opt
->default_fpu
;
22240 if (opt
->canonical_name
)
22241 strcpy (selected_cpu_name
, opt
->canonical_name
);
22246 for (i
= 0; i
< optlen
; i
++)
22247 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22248 selected_cpu_name
[i
] = 0;
22252 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22257 as_bad (_("unknown cpu `%s'"), str
);
22262 arm_parse_arch (char * str
)
22264 const struct arm_arch_option_table
*opt
;
22265 char *ext
= strchr (str
, '+');
22269 optlen
= ext
- str
;
22271 optlen
= strlen (str
);
22275 as_bad (_("missing architecture name `%s'"), str
);
22279 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22280 if (streq (opt
->name
, str
))
22282 march_cpu_opt
= &opt
->value
;
22283 march_fpu_opt
= &opt
->default_fpu
;
22284 strcpy (selected_cpu_name
, opt
->name
);
22287 return arm_parse_extension (ext
, &march_cpu_opt
);
22292 as_bad (_("unknown architecture `%s'\n"), str
);
22297 arm_parse_fpu (char * str
)
22299 const struct arm_option_cpu_value_table
* opt
;
22301 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22302 if (streq (opt
->name
, str
))
22304 mfpu_opt
= &opt
->value
;
22308 as_bad (_("unknown floating point format `%s'\n"), str
);
22313 arm_parse_float_abi (char * str
)
22315 const struct arm_option_value_table
* opt
;
22317 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22318 if (streq (opt
->name
, str
))
22320 mfloat_abi_opt
= opt
->value
;
22324 as_bad (_("unknown floating point abi `%s'\n"), str
);
22330 arm_parse_eabi (char * str
)
22332 const struct arm_option_value_table
*opt
;
22334 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22335 if (streq (opt
->name
, str
))
22337 meabi_flags
= opt
->value
;
22340 as_bad (_("unknown EABI `%s'\n"), str
);
22346 arm_parse_it_mode (char * str
)
22348 bfd_boolean ret
= TRUE
;
22350 if (streq ("arm", str
))
22351 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22352 else if (streq ("thumb", str
))
22353 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22354 else if (streq ("always", str
))
22355 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22356 else if (streq ("never", str
))
22357 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22360 as_bad (_("unknown implicit IT mode `%s', should be "\
22361 "arm, thumb, always, or never."), str
);
22368 struct arm_long_option_table arm_long_opts
[] =
22370 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22371 arm_parse_cpu
, NULL
},
22372 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22373 arm_parse_arch
, NULL
},
22374 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22375 arm_parse_fpu
, NULL
},
22376 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22377 arm_parse_float_abi
, NULL
},
22379 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22380 arm_parse_eabi
, NULL
},
22382 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22383 arm_parse_it_mode
, NULL
},
22384 {NULL
, NULL
, 0, NULL
}
22388 md_parse_option (int c
, char * arg
)
22390 struct arm_option_table
*opt
;
22391 const struct arm_legacy_option_table
*fopt
;
22392 struct arm_long_option_table
*lopt
;
22398 target_big_endian
= 1;
22404 target_big_endian
= 0;
22408 case OPTION_FIX_V4BX
:
22413 /* Listing option. Just ignore these, we don't support additional
22418 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22420 if (c
== opt
->option
[0]
22421 && ((arg
== NULL
&& opt
->option
[1] == 0)
22422 || streq (arg
, opt
->option
+ 1)))
22424 /* If the option is deprecated, tell the user. */
22425 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22426 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22427 arg
? arg
: "", _(opt
->deprecated
));
22429 if (opt
->var
!= NULL
)
22430 *opt
->var
= opt
->value
;
22436 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22438 if (c
== fopt
->option
[0]
22439 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22440 || streq (arg
, fopt
->option
+ 1)))
22442 /* If the option is deprecated, tell the user. */
22443 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22444 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22445 arg
? arg
: "", _(fopt
->deprecated
));
22447 if (fopt
->var
!= NULL
)
22448 *fopt
->var
= &fopt
->value
;
22454 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22456 /* These options are expected to have an argument. */
22457 if (c
== lopt
->option
[0]
22459 && strncmp (arg
, lopt
->option
+ 1,
22460 strlen (lopt
->option
+ 1)) == 0)
22462 /* If the option is deprecated, tell the user. */
22463 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22464 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22465 _(lopt
->deprecated
));
22467 /* Call the sup-option parser. */
22468 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22479 md_show_usage (FILE * fp
)
22481 struct arm_option_table
*opt
;
22482 struct arm_long_option_table
*lopt
;
22484 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22486 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22487 if (opt
->help
!= NULL
)
22488 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22490 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22491 if (lopt
->help
!= NULL
)
22492 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22496 -EB assemble code for a big-endian cpu\n"));
22501 -EL assemble code for a little-endian cpu\n"));
22505 --fix-v4bx Allow BX in ARMv4 code\n"));
22513 arm_feature_set flags
;
22514 } cpu_arch_ver_table
;
22516 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22517 least features first. */
22518 static const cpu_arch_ver_table cpu_arch_ver
[] =
22524 {4, ARM_ARCH_V5TE
},
22525 {5, ARM_ARCH_V5TEJ
},
22529 {11, ARM_ARCH_V6M
},
22530 {8, ARM_ARCH_V6T2
},
22531 {10, ARM_ARCH_V7A
},
22532 {10, ARM_ARCH_V7R
},
22533 {10, ARM_ARCH_V7M
},
22537 /* Set an attribute if it has not already been set by the user. */
22539 aeabi_set_attribute_int (int tag
, int value
)
22542 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22543 || !attributes_set_explicitly
[tag
])
22544 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22548 aeabi_set_attribute_string (int tag
, const char *value
)
22551 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22552 || !attributes_set_explicitly
[tag
])
22553 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22556 /* Set the public EABI object attributes. */
22558 aeabi_set_public_attributes (void)
22561 arm_feature_set flags
;
22562 arm_feature_set tmp
;
22563 const cpu_arch_ver_table
*p
;
22565 /* Choose the architecture based on the capabilities of the requested cpu
22566 (if any) and/or the instructions actually used. */
22567 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22568 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22569 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22570 /*Allow the user to override the reported architecture. */
22573 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22574 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22579 for (p
= cpu_arch_ver
; p
->val
; p
++)
22581 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22584 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22588 /* The table lookup above finds the last architecture to contribute
22589 a new feature. Unfortunately, Tag13 is a subset of the union of
22590 v6T2 and v7-M, so it is never seen as contributing a new feature.
22591 We can not search for the last entry which is entirely used,
22592 because if no CPU is specified we build up only those flags
22593 actually used. Perhaps we should separate out the specified
22594 and implicit cases. Avoid taking this path for -march=all by
22595 checking for contradictory v7-A / v7-M features. */
22597 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22598 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22599 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22602 /* Tag_CPU_name. */
22603 if (selected_cpu_name
[0])
22607 p
= selected_cpu_name
;
22608 if (strncmp (p
, "armv", 4) == 0)
22613 for (i
= 0; p
[i
]; i
++)
22614 p
[i
] = TOUPPER (p
[i
]);
22616 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22619 /* Tag_CPU_arch. */
22620 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22622 /* Tag_CPU_arch_profile. */
22623 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22624 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22625 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22626 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22627 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22628 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22630 /* Tag_ARM_ISA_use. */
22631 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22633 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22635 /* Tag_THUMB_ISA_use. */
22636 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22638 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22639 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22641 /* Tag_VFP_arch. */
22642 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22643 aeabi_set_attribute_int (Tag_VFP_arch
,
22644 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22646 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22647 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22648 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22649 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22650 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22651 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22652 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22653 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22654 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22656 /* Tag_WMMX_arch. */
22657 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22658 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22659 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22660 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22662 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22663 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22664 aeabi_set_attribute_int
22665 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22668 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22669 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22670 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22673 /* Add the default contents for the .ARM.attributes section. */
22677 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22680 aeabi_set_public_attributes ();
22682 #endif /* OBJ_ELF */
22685 /* Parse a .cpu directive. */
22688 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22690 const struct arm_cpu_option_table
*opt
;
22694 name
= input_line_pointer
;
22695 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22696 input_line_pointer
++;
22697 saved_char
= *input_line_pointer
;
22698 *input_line_pointer
= 0;
22700 /* Skip the first "all" entry. */
22701 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22702 if (streq (opt
->name
, name
))
22704 mcpu_cpu_opt
= &opt
->value
;
22705 selected_cpu
= opt
->value
;
22706 if (opt
->canonical_name
)
22707 strcpy (selected_cpu_name
, opt
->canonical_name
);
22711 for (i
= 0; opt
->name
[i
]; i
++)
22712 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22713 selected_cpu_name
[i
] = 0;
22715 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22716 *input_line_pointer
= saved_char
;
22717 demand_empty_rest_of_line ();
22720 as_bad (_("unknown cpu `%s'"), name
);
22721 *input_line_pointer
= saved_char
;
22722 ignore_rest_of_line ();
22726 /* Parse a .arch directive. */
22729 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22731 const struct arm_arch_option_table
*opt
;
22735 name
= input_line_pointer
;
22736 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22737 input_line_pointer
++;
22738 saved_char
= *input_line_pointer
;
22739 *input_line_pointer
= 0;
22741 /* Skip the first "all" entry. */
22742 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22743 if (streq (opt
->name
, name
))
22745 mcpu_cpu_opt
= &opt
->value
;
22746 selected_cpu
= opt
->value
;
22747 strcpy (selected_cpu_name
, opt
->name
);
22748 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22749 *input_line_pointer
= saved_char
;
22750 demand_empty_rest_of_line ();
22754 as_bad (_("unknown architecture `%s'\n"), name
);
22755 *input_line_pointer
= saved_char
;
22756 ignore_rest_of_line ();
22760 /* Parse a .object_arch directive. */
22763 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22765 const struct arm_arch_option_table
*opt
;
22769 name
= input_line_pointer
;
22770 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22771 input_line_pointer
++;
22772 saved_char
= *input_line_pointer
;
22773 *input_line_pointer
= 0;
22775 /* Skip the first "all" entry. */
22776 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22777 if (streq (opt
->name
, name
))
22779 object_arch
= &opt
->value
;
22780 *input_line_pointer
= saved_char
;
22781 demand_empty_rest_of_line ();
22785 as_bad (_("unknown architecture `%s'\n"), name
);
22786 *input_line_pointer
= saved_char
;
22787 ignore_rest_of_line ();
22790 /* Parse a .fpu directive. */
22793 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22795 const struct arm_option_cpu_value_table
*opt
;
22799 name
= input_line_pointer
;
22800 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22801 input_line_pointer
++;
22802 saved_char
= *input_line_pointer
;
22803 *input_line_pointer
= 0;
22805 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22806 if (streq (opt
->name
, name
))
22808 mfpu_opt
= &opt
->value
;
22809 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22810 *input_line_pointer
= saved_char
;
22811 demand_empty_rest_of_line ();
22815 as_bad (_("unknown floating point format `%s'\n"), name
);
22816 *input_line_pointer
= saved_char
;
22817 ignore_rest_of_line ();
22820 /* Copy symbol information. */
22823 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22825 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22829 /* Given a symbolic attribute NAME, return the proper integer value.
22830 Returns -1 if the attribute is not known. */
22833 arm_convert_symbolic_attribute (const char *name
)
22835 static const struct
22840 attribute_table
[] =
22842 /* When you modify this table you should
22843 also modify the list in doc/c-arm.texi. */
22844 #define T(tag) {#tag, tag}
22845 T (Tag_CPU_raw_name
),
22848 T (Tag_CPU_arch_profile
),
22849 T (Tag_ARM_ISA_use
),
22850 T (Tag_THUMB_ISA_use
),
22853 T (Tag_Advanced_SIMD_arch
),
22854 T (Tag_PCS_config
),
22855 T (Tag_ABI_PCS_R9_use
),
22856 T (Tag_ABI_PCS_RW_data
),
22857 T (Tag_ABI_PCS_RO_data
),
22858 T (Tag_ABI_PCS_GOT_use
),
22859 T (Tag_ABI_PCS_wchar_t
),
22860 T (Tag_ABI_FP_rounding
),
22861 T (Tag_ABI_FP_denormal
),
22862 T (Tag_ABI_FP_exceptions
),
22863 T (Tag_ABI_FP_user_exceptions
),
22864 T (Tag_ABI_FP_number_model
),
22865 T (Tag_ABI_align8_needed
),
22866 T (Tag_ABI_align8_preserved
),
22867 T (Tag_ABI_enum_size
),
22868 T (Tag_ABI_HardFP_use
),
22869 T (Tag_ABI_VFP_args
),
22870 T (Tag_ABI_WMMX_args
),
22871 T (Tag_ABI_optimization_goals
),
22872 T (Tag_ABI_FP_optimization_goals
),
22873 T (Tag_compatibility
),
22874 T (Tag_CPU_unaligned_access
),
22875 T (Tag_VFP_HP_extension
),
22876 T (Tag_ABI_FP_16bit_format
),
22877 T (Tag_nodefaults
),
22878 T (Tag_also_compatible_with
),
22879 T (Tag_conformance
),
22881 T (Tag_Virtualization_use
),
22882 T (Tag_MPextension_use
)
22890 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22891 if (streq (name
, attribute_table
[i
].name
))
22892 return attribute_table
[i
].tag
;
22898 /* Apply sym value for relocations only in the case that
22899 they are for local symbols and you have the respective
22900 architectural feature for blx and simple switches. */
22902 arm_apply_sym_value (struct fix
* fixP
)
22905 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22906 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22908 switch (fixP
->fx_r_type
)
22910 case BFD_RELOC_ARM_PCREL_BLX
:
22911 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22912 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22916 case BFD_RELOC_ARM_PCREL_CALL
:
22917 case BFD_RELOC_THUMB_PCREL_BLX
:
22918 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22929 #endif /* OBJ_ELF */