1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
237 static const arm_feature_set arm_ext_v8_3
=
238 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
240 static const arm_feature_set arm_arch_any
= ARM_ANY
;
241 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
242 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
243 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
245 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
248 static const arm_feature_set arm_cext_iwmmxt2
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
250 static const arm_feature_set arm_cext_iwmmxt
=
251 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
252 static const arm_feature_set arm_cext_xscale
=
253 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
254 static const arm_feature_set arm_cext_maverick
=
255 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
256 static const arm_feature_set fpu_fpa_ext_v1
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
258 static const arm_feature_set fpu_fpa_ext_v2
=
259 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
260 static const arm_feature_set fpu_vfp_ext_v1xd
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
262 static const arm_feature_set fpu_vfp_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
264 static const arm_feature_set fpu_vfp_ext_v2
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
266 static const arm_feature_set fpu_vfp_ext_v3xd
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
268 static const arm_feature_set fpu_vfp_ext_v3
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
270 static const arm_feature_set fpu_vfp_ext_d32
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
272 static const arm_feature_set fpu_neon_ext_v1
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
274 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
275 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
277 static const arm_feature_set fpu_vfp_fp16
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
279 static const arm_feature_set fpu_neon_ext_fma
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
284 static const arm_feature_set fpu_vfp_ext_armv8
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
286 static const arm_feature_set fpu_vfp_ext_armv8xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
288 static const arm_feature_set fpu_neon_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
290 static const arm_feature_set fpu_crypto_ext_armv8
=
291 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
292 static const arm_feature_set crc_ext_armv8
=
293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
294 static const arm_feature_set fpu_neon_ext_v8_1
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static int mfloat_abi_opt
= -1;
298 /* Record user cpu selection for object attributes. */
299 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
300 /* Must be long enough to hold any of the names in arm_cpus. */
301 static char selected_cpu_name
[20];
303 extern FLONUM_TYPE generic_floating_point_number
;
305 /* Return if no cpu was selected on command-line. */
307 no_cpu_selected (void)
309 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
314 static int meabi_flags
= EABI_DEFAULT
;
316 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
319 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
324 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
330 symbolS
* GOT_symbol
;
333 /* 0: assemble for ARM,
334 1: assemble for Thumb,
335 2: assemble for Thumb even though target CPU does not support thumb
337 static int thumb_mode
= 0;
338 /* A value distinct from the possible values for thumb_mode that we
339 can use to record whether thumb_mode has been copied into the
340 tc_frag_data field of a frag. */
341 #define MODE_RECORDED (1 << 4)
343 /* Specifies the intrinsic IT insn behavior mode. */
344 enum implicit_it_mode
346 IMPLICIT_IT_MODE_NEVER
= 0x00,
347 IMPLICIT_IT_MODE_ARM
= 0x01,
348 IMPLICIT_IT_MODE_THUMB
= 0x02,
349 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
351 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
353 /* If unified_syntax is true, we are processing the new unified
354 ARM/Thumb syntax. Important differences from the old ARM mode:
356 - Immediate operands do not require a # prefix.
357 - Conditional affixes always appear at the end of the
358 instruction. (For backward compatibility, those instructions
359 that formerly had them in the middle, continue to accept them
361 - The IT instruction may appear, and if it does is validated
362 against subsequent conditional affixes. It does not generate
365 Important differences from the old Thumb mode:
367 - Immediate operands do not require a # prefix.
368 - Most of the V6T2 instructions are only available in unified mode.
369 - The .N and .W suffixes are recognized and honored (it is an error
370 if they cannot be honored).
371 - All instructions set the flags if and only if they have an 's' affix.
372 - Conditional affixes may be used. They are validated against
373 preceding IT instructions. Unlike ARM mode, you cannot use a
374 conditional affix except in the scope of an IT instruction. */
376 static bfd_boolean unified_syntax
= FALSE
;
378 /* An immediate operand can start with #, and ld*, st*, pld operands
379 can contain [ and ]. We need to tell APP not to elide whitespace
380 before a [, which can appear as the first operand for pld.
381 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
382 const char arm_symbol_chars
[] = "#[]{}";
397 enum neon_el_type type
;
401 #define NEON_MAX_TYPE_ELS 4
405 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
409 enum it_instruction_type
414 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
415 if inside, should be the last one. */
416 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
417 i.e. BKPT and NOP. */
418 IT_INSN
/* The IT insn has been parsed. */
421 /* The maximum number of operands we need. */
422 #define ARM_IT_MAX_OPERANDS 6
427 unsigned long instruction
;
431 /* "uncond_value" is set to the value in place of the conditional field in
432 unconditional versions of the instruction, or -1 if nothing is
435 struct neon_type vectype
;
436 /* This does not indicate an actual NEON instruction, only that
437 the mnemonic accepts neon-style type suffixes. */
439 /* Set to the opcode if the instruction needs relaxation.
440 Zero if the instruction is not relaxed. */
444 bfd_reloc_code_real_type type
;
449 enum it_instruction_type it_insn_type
;
455 struct neon_type_el vectype
;
456 unsigned present
: 1; /* Operand present. */
457 unsigned isreg
: 1; /* Operand was a register. */
458 unsigned immisreg
: 1; /* .imm field is a second register. */
459 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
460 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
461 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
462 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 instructions. This allows us to disambiguate ARM <-> vector insns. */
464 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
465 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
466 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
467 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
468 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
469 unsigned writeback
: 1; /* Operand has trailing ! */
470 unsigned preind
: 1; /* Preindexed address. */
471 unsigned postind
: 1; /* Postindexed address. */
472 unsigned negative
: 1; /* Index register was negated. */
473 unsigned shifted
: 1; /* Shift applied to operation. */
474 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
475 } operands
[ARM_IT_MAX_OPERANDS
];
478 static struct arm_it inst
;
480 #define NUM_FLOAT_VALS 8
482 const char * fp_const
[] =
484 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
487 /* Number of littlenums required to hold an extended precision number. */
488 #define MAX_LITTLENUMS 6
490 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
500 #define CP_T_X 0x00008000
501 #define CP_T_Y 0x00400000
503 #define CONDS_BIT 0x00100000
504 #define LOAD_BIT 0x00100000
506 #define DOUBLE_LOAD_FLAG 0x00000001
510 const char * template_name
;
514 #define COND_ALWAYS 0xE
518 const char * template_name
;
522 struct asm_barrier_opt
524 const char * template_name
;
526 const arm_feature_set arch
;
529 /* The bit that distinguishes CPSR and SPSR. */
530 #define SPSR_BIT (1 << 22)
532 /* The individual PSR flag bits. */
533 #define PSR_c (1 << 16)
534 #define PSR_x (1 << 17)
535 #define PSR_s (1 << 18)
536 #define PSR_f (1 << 19)
541 bfd_reloc_code_real_type reloc
;
546 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
547 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
552 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
555 /* Bits for DEFINED field in neon_typed_alias. */
556 #define NTA_HASTYPE 1
557 #define NTA_HASINDEX 2
559 struct neon_typed_alias
561 unsigned char defined
;
563 struct neon_type_el eltype
;
566 /* ARM register categories. This includes coprocessor numbers and various
567 architecture extensions' registers. */
594 /* Structure for a hash table entry for a register.
595 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
596 information which states whether a vector type or index is specified (for a
597 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
603 unsigned char builtin
;
604 struct neon_typed_alias
* neon
;
607 /* Diagnostics used when we don't get a register of the expected type. */
608 const char * const reg_expected_msgs
[] =
610 N_("ARM register expected"),
611 N_("bad or missing co-processor number"),
612 N_("co-processor register expected"),
613 N_("FPA register expected"),
614 N_("VFP single precision register expected"),
615 N_("VFP/Neon double precision register expected"),
616 N_("Neon quad precision register expected"),
617 N_("VFP single or double precision register expected"),
618 N_("Neon double or quad precision register expected"),
619 N_("VFP single, double or Neon quad precision register expected"),
620 N_("VFP system register expected"),
621 N_("Maverick MVF register expected"),
622 N_("Maverick MVD register expected"),
623 N_("Maverick MVFX register expected"),
624 N_("Maverick MVDX register expected"),
625 N_("Maverick MVAX register expected"),
626 N_("Maverick DSPSC register expected"),
627 N_("iWMMXt data register expected"),
628 N_("iWMMXt control register expected"),
629 N_("iWMMXt scalar register expected"),
630 N_("XScale accumulator register expected"),
633 /* Some well known registers that we refer to directly elsewhere. */
639 /* ARM instructions take 4bytes in the object file, Thumb instructions
645 /* Basic string to match. */
646 const char * template_name
;
648 /* Parameters to instruction. */
649 unsigned int operands
[8];
651 /* Conditional tag - see opcode_lookup. */
652 unsigned int tag
: 4;
654 /* Basic instruction code. */
655 unsigned int avalue
: 28;
657 /* Thumb-format instruction code. */
660 /* Which architecture variant provides this instruction. */
661 const arm_feature_set
* avariant
;
662 const arm_feature_set
* tvariant
;
664 /* Function to call to encode instruction in ARM format. */
665 void (* aencode
) (void);
667 /* Function to call to encode instruction in Thumb format. */
668 void (* tencode
) (void);
671 /* Defines for various bits that we will want to toggle. */
672 #define INST_IMMEDIATE 0x02000000
673 #define OFFSET_REG 0x02000000
674 #define HWOFFSET_IMM 0x00400000
675 #define SHIFT_BY_REG 0x00000010
676 #define PRE_INDEX 0x01000000
677 #define INDEX_UP 0x00800000
678 #define WRITE_BACK 0x00200000
679 #define LDM_TYPE_2_OR_3 0x00400000
680 #define CPSI_MMOD 0x00020000
682 #define LITERAL_MASK 0xf000f000
683 #define OPCODE_MASK 0xfe1fffff
684 #define V4_STR_BIT 0x00000020
685 #define VLDR_VMOV_SAME 0x0040f000
687 #define T2_SUBS_PC_LR 0xf3de8f00
689 #define DATA_OP_SHIFT 21
690 #define SBIT_SHIFT 20
692 #define T2_OPCODE_MASK 0xfe1fffff
693 #define T2_DATA_OP_SHIFT 21
694 #define T2_SBIT_SHIFT 20
696 #define A_COND_MASK 0xf0000000
697 #define A_PUSH_POP_OP_MASK 0x0fff0000
699 /* Opcodes for pushing/poping registers to/from the stack. */
700 #define A1_OPCODE_PUSH 0x092d0000
701 #define A2_OPCODE_PUSH 0x052d0004
702 #define A2_OPCODE_POP 0x049d0004
704 /* Codes to distinguish the arithmetic instructions. */
715 #define OPCODE_CMP 10
716 #define OPCODE_CMN 11
717 #define OPCODE_ORR 12
718 #define OPCODE_MOV 13
719 #define OPCODE_BIC 14
720 #define OPCODE_MVN 15
722 #define T2_OPCODE_AND 0
723 #define T2_OPCODE_BIC 1
724 #define T2_OPCODE_ORR 2
725 #define T2_OPCODE_ORN 3
726 #define T2_OPCODE_EOR 4
727 #define T2_OPCODE_ADD 8
728 #define T2_OPCODE_ADC 10
729 #define T2_OPCODE_SBC 11
730 #define T2_OPCODE_SUB 13
731 #define T2_OPCODE_RSB 14
733 #define T_OPCODE_MUL 0x4340
734 #define T_OPCODE_TST 0x4200
735 #define T_OPCODE_CMN 0x42c0
736 #define T_OPCODE_NEG 0x4240
737 #define T_OPCODE_MVN 0x43c0
739 #define T_OPCODE_ADD_R3 0x1800
740 #define T_OPCODE_SUB_R3 0x1a00
741 #define T_OPCODE_ADD_HI 0x4400
742 #define T_OPCODE_ADD_ST 0xb000
743 #define T_OPCODE_SUB_ST 0xb080
744 #define T_OPCODE_ADD_SP 0xa800
745 #define T_OPCODE_ADD_PC 0xa000
746 #define T_OPCODE_ADD_I8 0x3000
747 #define T_OPCODE_SUB_I8 0x3800
748 #define T_OPCODE_ADD_I3 0x1c00
749 #define T_OPCODE_SUB_I3 0x1e00
751 #define T_OPCODE_ASR_R 0x4100
752 #define T_OPCODE_LSL_R 0x4080
753 #define T_OPCODE_LSR_R 0x40c0
754 #define T_OPCODE_ROR_R 0x41c0
755 #define T_OPCODE_ASR_I 0x1000
756 #define T_OPCODE_LSL_I 0x0000
757 #define T_OPCODE_LSR_I 0x0800
759 #define T_OPCODE_MOV_I8 0x2000
760 #define T_OPCODE_CMP_I8 0x2800
761 #define T_OPCODE_CMP_LR 0x4280
762 #define T_OPCODE_MOV_HR 0x4600
763 #define T_OPCODE_CMP_HR 0x4500
765 #define T_OPCODE_LDR_PC 0x4800
766 #define T_OPCODE_LDR_SP 0x9800
767 #define T_OPCODE_STR_SP 0x9000
768 #define T_OPCODE_LDR_IW 0x6800
769 #define T_OPCODE_STR_IW 0x6000
770 #define T_OPCODE_LDR_IH 0x8800
771 #define T_OPCODE_STR_IH 0x8000
772 #define T_OPCODE_LDR_IB 0x7800
773 #define T_OPCODE_STR_IB 0x7000
774 #define T_OPCODE_LDR_RW 0x5800
775 #define T_OPCODE_STR_RW 0x5000
776 #define T_OPCODE_LDR_RH 0x5a00
777 #define T_OPCODE_STR_RH 0x5200
778 #define T_OPCODE_LDR_RB 0x5c00
779 #define T_OPCODE_STR_RB 0x5400
781 #define T_OPCODE_PUSH 0xb400
782 #define T_OPCODE_POP 0xbc00
784 #define T_OPCODE_BRANCH 0xe000
786 #define THUMB_SIZE 2 /* Size of thumb instruction. */
787 #define THUMB_PP_PC_LR 0x0100
788 #define THUMB_LOAD_BIT 0x0800
789 #define THUMB2_LOAD_BIT 0x00100000
791 #define BAD_ARGS _("bad arguments to instruction")
792 #define BAD_SP _("r13 not allowed here")
793 #define BAD_PC _("r15 not allowed here")
794 #define BAD_COND _("instruction cannot be conditional")
795 #define BAD_OVERLAP _("registers may not be the same")
796 #define BAD_HIREG _("lo register required")
797 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
798 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
799 #define BAD_BRANCH _("branch must be last instruction in IT block")
800 #define BAD_NOT_IT _("instruction not allowed in IT block")
801 #define BAD_FPU _("selected FPU does not support instruction")
802 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
803 #define BAD_IT_COND _("incorrect condition in IT block")
804 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
805 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
806 #define BAD_PC_ADDRESSING \
807 _("cannot use register index with PC-relative addressing")
808 #define BAD_PC_WRITEBACK \
809 _("cannot use writeback with PC-relative addressing")
810 #define BAD_RANGE _("branch out of range")
811 #define BAD_FP16 _("selected processor does not support fp16 instruction")
812 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
813 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
815 static struct hash_control
* arm_ops_hsh
;
816 static struct hash_control
* arm_cond_hsh
;
817 static struct hash_control
* arm_shift_hsh
;
818 static struct hash_control
* arm_psr_hsh
;
819 static struct hash_control
* arm_v7m_psr_hsh
;
820 static struct hash_control
* arm_reg_hsh
;
821 static struct hash_control
* arm_reloc_hsh
;
822 static struct hash_control
* arm_barrier_opt_hsh
;
824 /* Stuff needed to resolve the label ambiguity
833 symbolS
* last_label_seen
;
834 static int label_is_thumb_function_name
= FALSE
;
836 /* Literal pool structure. Held on a per-section
837 and per-sub-section basis. */
839 #define MAX_LITERAL_POOL_SIZE 1024
840 typedef struct literal_pool
842 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
843 unsigned int next_free_entry
;
849 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
851 struct literal_pool
* next
;
852 unsigned int alignment
;
855 /* Pointer to a linked list of literal pools. */
856 literal_pool
* list_of_pools
= NULL
;
858 typedef enum asmfunc_states
861 WAITING_ASMFUNC_NAME
,
865 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
868 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
870 static struct current_it now_it
;
874 now_it_compatible (int cond
)
876 return (cond
& ~1) == (now_it
.cc
& ~1);
880 conditional_insn (void)
882 return inst
.cond
!= COND_ALWAYS
;
885 static int in_it_block (void);
887 static int handle_it_state (void);
889 static void force_automatic_it_block_close (void);
891 static void it_fsm_post_encode (void);
893 #define set_it_insn_type(type) \
896 inst.it_insn_type = type; \
897 if (handle_it_state () == FAIL) \
902 #define set_it_insn_type_nonvoid(type, failret) \
905 inst.it_insn_type = type; \
906 if (handle_it_state () == FAIL) \
911 #define set_it_insn_type_last() \
914 if (inst.cond == COND_ALWAYS) \
915 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
917 set_it_insn_type (INSIDE_IT_LAST_INSN); \
923 /* This array holds the chars that always start a comment. If the
924 pre-processor is disabled, these aren't very useful. */
925 char arm_comment_chars
[] = "@";
927 /* This array holds the chars that only start a comment at the beginning of
928 a line. If the line seems to have the form '# 123 filename'
929 .line and .file directives will appear in the pre-processed output. */
930 /* Note that input_file.c hand checks for '#' at the beginning of the
931 first line of the input file. This is because the compiler outputs
932 #NO_APP at the beginning of its output. */
933 /* Also note that comments like this one will always work. */
934 const char line_comment_chars
[] = "#";
936 char arm_line_separator_chars
[] = ";";
938 /* Chars that can be used to separate mant
939 from exp in floating point numbers. */
940 const char EXP_CHARS
[] = "eE";
942 /* Chars that mean this number is a floating point constant. */
946 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
948 /* Prefix characters that indicate the start of an immediate
950 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
952 /* Separator character handling. */
954 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
957 skip_past_char (char ** str
, char c
)
959 /* PR gas/14987: Allow for whitespace before the expected character. */
960 skip_whitespace (*str
);
971 #define skip_past_comma(str) skip_past_char (str, ',')
973 /* Arithmetic expressions (possibly involving symbols). */
975 /* Return TRUE if anything in the expression is a bignum. */
978 walk_no_bignums (symbolS
* sp
)
980 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
983 if (symbol_get_value_expression (sp
)->X_add_symbol
)
985 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
986 || (symbol_get_value_expression (sp
)->X_op_symbol
987 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
993 static int in_my_get_expression
= 0;
995 /* Third argument to my_get_expression. */
996 #define GE_NO_PREFIX 0
997 #define GE_IMM_PREFIX 1
998 #define GE_OPT_PREFIX 2
999 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1000 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1001 #define GE_OPT_PREFIX_BIG 3
1004 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1009 /* In unified syntax, all prefixes are optional. */
1011 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1014 switch (prefix_mode
)
1016 case GE_NO_PREFIX
: break;
1018 if (!is_immediate_prefix (**str
))
1020 inst
.error
= _("immediate expression requires a # prefix");
1026 case GE_OPT_PREFIX_BIG
:
1027 if (is_immediate_prefix (**str
))
1033 memset (ep
, 0, sizeof (expressionS
));
1035 save_in
= input_line_pointer
;
1036 input_line_pointer
= *str
;
1037 in_my_get_expression
= 1;
1038 seg
= expression (ep
);
1039 in_my_get_expression
= 0;
1041 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1043 /* We found a bad or missing expression in md_operand(). */
1044 *str
= input_line_pointer
;
1045 input_line_pointer
= save_in
;
1046 if (inst
.error
== NULL
)
1047 inst
.error
= (ep
->X_op
== O_absent
1048 ? _("missing expression") :_("bad expression"));
1053 if (seg
!= absolute_section
1054 && seg
!= text_section
1055 && seg
!= data_section
1056 && seg
!= bss_section
1057 && seg
!= undefined_section
)
1059 inst
.error
= _("bad segment");
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1068 /* Get rid of any bignums now, so that we don't generate an error for which
1069 we can't establish a line number later on. Big numbers are never valid
1070 in instructions, which is where this routine is always called. */
1071 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1072 && (ep
->X_op
== O_big
1073 || (ep
->X_add_symbol
1074 && (walk_no_bignums (ep
->X_add_symbol
)
1076 && walk_no_bignums (ep
->X_op_symbol
))))))
1078 inst
.error
= _("invalid constant");
1079 *str
= input_line_pointer
;
1080 input_line_pointer
= save_in
;
1084 *str
= input_line_pointer
;
1085 input_line_pointer
= save_in
;
1089 /* Turn a string in input_line_pointer into a floating point constant
1090 of type TYPE, and store the appropriate bytes in *LITP. The number
1091 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1092 returned, or NULL on OK.
1094 Note that fp constants aren't represent in the normal way on the ARM.
1095 In big endian mode, things are as expected. However, in little endian
1096 mode fp constants are big-endian word-wise, and little-endian byte-wise
1097 within the words. For example, (double) 1.1 in big endian mode is
1098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1099 the byte sequence 99 99 f1 3f 9a 99 99 99.
1101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1104 md_atof (int type
, char * litP
, int * sizeP
)
1107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1139 return _("Unrecognized or unsupported floating point constant");
1142 t
= atof_ieee (input_line_pointer
, type
, words
);
1144 input_line_pointer
= t
;
1145 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1147 if (target_big_endian
)
1149 for (i
= 0; i
< prec
; i
++)
1151 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1152 litP
+= sizeof (LITTLENUM_TYPE
);
1157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1158 for (i
= prec
- 1; i
>= 0; i
--)
1160 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1161 litP
+= sizeof (LITTLENUM_TYPE
);
1164 /* For a 4 byte float the order of elements in `words' is 1 0.
1165 For an 8 byte float the order is 1 0 3 2. */
1166 for (i
= 0; i
< prec
; i
+= 2)
1168 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1169 sizeof (LITTLENUM_TYPE
));
1170 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1171 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1172 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1179 /* We handle all bad expressions here, so that we can report the faulty
1180 instruction in the error message. */
1182 md_operand (expressionS
* exp
)
1184 if (in_my_get_expression
)
1185 exp
->X_op
= O_illegal
;
1188 /* Immediate values. */
1190 /* Generic immediate-value read function for use in directives.
1191 Accepts anything that 'expression' can fold to a constant.
1192 *val receives the number. */
1195 immediate_for_directive (int *val
)
1198 exp
.X_op
= O_illegal
;
1200 if (is_immediate_prefix (*input_line_pointer
))
1202 input_line_pointer
++;
1206 if (exp
.X_op
!= O_constant
)
1208 as_bad (_("expected #constant"));
1209 ignore_rest_of_line ();
1212 *val
= exp
.X_add_number
;
1217 /* Register parsing. */
1219 /* Generic register parser. CCP points to what should be the
1220 beginning of a register name. If it is indeed a valid register
1221 name, advance CCP over it and return the reg_entry structure;
1222 otherwise return NULL. Does not issue diagnostics. */
1224 static struct reg_entry
*
1225 arm_reg_parse_multi (char **ccp
)
1229 struct reg_entry
*reg
;
1231 skip_whitespace (start
);
1233 #ifdef REGISTER_PREFIX
1234 if (*start
!= REGISTER_PREFIX
)
1238 #ifdef OPTIONAL_REGISTER_PREFIX
1239 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1244 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1249 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1251 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1261 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1262 enum arm_reg_type type
)
1264 /* Alternative syntaxes are accepted for a few register classes. */
1271 /* Generic coprocessor register names are allowed for these. */
1272 if (reg
&& reg
->type
== REG_TYPE_CN
)
1277 /* For backward compatibility, a bare number is valid here. */
1279 unsigned long processor
= strtoul (start
, ccp
, 10);
1280 if (*ccp
!= start
&& processor
<= 15)
1285 case REG_TYPE_MMXWC
:
1286 /* WC includes WCG. ??? I'm not sure this is true for all
1287 instructions that take WC registers. */
1288 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1299 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1300 return value is the register number or FAIL. */
1303 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1306 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1309 /* Do not allow a scalar (reg+index) to parse as a register. */
1310 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1313 if (reg
&& reg
->type
== type
)
1316 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1323 /* Parse a Neon type specifier. *STR should point at the leading '.'
1324 character. Does no verification at this stage that the type fits the opcode
1331 Can all be legally parsed by this function.
1333 Fills in neon_type struct pointer with parsed information, and updates STR
1334 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1335 type, FAIL if not. */
1338 parse_neon_type (struct neon_type
*type
, char **str
)
1345 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1347 enum neon_el_type thistype
= NT_untyped
;
1348 unsigned thissize
= -1u;
1355 /* Just a size without an explicit type. */
1359 switch (TOLOWER (*ptr
))
1361 case 'i': thistype
= NT_integer
; break;
1362 case 'f': thistype
= NT_float
; break;
1363 case 'p': thistype
= NT_poly
; break;
1364 case 's': thistype
= NT_signed
; break;
1365 case 'u': thistype
= NT_unsigned
; break;
1367 thistype
= NT_float
;
1372 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1378 /* .f is an abbreviation for .f32. */
1379 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1384 thissize
= strtoul (ptr
, &ptr
, 10);
1386 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1389 as_bad (_("bad size %d in type specifier"), thissize
);
1397 type
->el
[type
->elems
].type
= thistype
;
1398 type
->el
[type
->elems
].size
= thissize
;
1403 /* Empty/missing type is not a successful parse. */
1404 if (type
->elems
== 0)
1412 /* Errors may be set multiple times during parsing or bit encoding
1413 (particularly in the Neon bits), but usually the earliest error which is set
1414 will be the most meaningful. Avoid overwriting it with later (cascading)
1415 errors by calling this function. */
1418 first_error (const char *err
)
1424 /* Parse a single type, e.g. ".s32", leading period included. */
1426 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1429 struct neon_type optype
;
1433 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1435 if (optype
.elems
== 1)
1436 *vectype
= optype
.el
[0];
1439 first_error (_("only one type should be specified for operand"));
1445 first_error (_("vector type expected"));
1457 /* Special meanings for indices (which have a range of 0-7), which will fit into
1460 #define NEON_ALL_LANES 15
1461 #define NEON_INTERLEAVE_LANES 14
1463 /* Parse either a register or a scalar, with an optional type. Return the
1464 register number, and optionally fill in the actual type of the register
1465 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1466 type/index information in *TYPEINFO. */
1469 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1470 enum arm_reg_type
*rtype
,
1471 struct neon_typed_alias
*typeinfo
)
1474 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1475 struct neon_typed_alias atype
;
1476 struct neon_type_el parsetype
;
1480 atype
.eltype
.type
= NT_invtype
;
1481 atype
.eltype
.size
= -1;
1483 /* Try alternate syntax for some types of register. Note these are mutually
1484 exclusive with the Neon syntax extensions. */
1487 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1495 /* Undo polymorphism when a set of register types may be accepted. */
1496 if ((type
== REG_TYPE_NDQ
1497 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1498 || (type
== REG_TYPE_VFSD
1499 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1500 || (type
== REG_TYPE_NSDQ
1501 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1502 || reg
->type
== REG_TYPE_NQ
))
1503 || (type
== REG_TYPE_MMXWC
1504 && (reg
->type
== REG_TYPE_MMXWCG
)))
1505 type
= (enum arm_reg_type
) reg
->type
;
1507 if (type
!= reg
->type
)
1513 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1515 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1517 first_error (_("can't redefine type for operand"));
1520 atype
.defined
|= NTA_HASTYPE
;
1521 atype
.eltype
= parsetype
;
1524 if (skip_past_char (&str
, '[') == SUCCESS
)
1526 if (type
!= REG_TYPE_VFD
)
1528 first_error (_("only D registers may be indexed"));
1532 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1534 first_error (_("can't change index for operand"));
1538 atype
.defined
|= NTA_HASINDEX
;
1540 if (skip_past_char (&str
, ']') == SUCCESS
)
1541 atype
.index
= NEON_ALL_LANES
;
1546 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1548 if (exp
.X_op
!= O_constant
)
1550 first_error (_("constant expression required"));
1554 if (skip_past_char (&str
, ']') == FAIL
)
1557 atype
.index
= exp
.X_add_number
;
1572 /* Like arm_reg_parse, but allow allow the following extra features:
1573 - If RTYPE is non-zero, return the (possibly restricted) type of the
1574 register (e.g. Neon double or quad reg when either has been requested).
1575 - If this is a Neon vector type with additional type information, fill
1576 in the struct pointed to by VECTYPE (if non-NULL).
1577 This function will fault on encountering a scalar. */
1580 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1581 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1583 struct neon_typed_alias atype
;
1585 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1590 /* Do not allow regname(... to parse as a register. */
1594 /* Do not allow a scalar (reg+index) to parse as a register. */
1595 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1597 first_error (_("register operand expected, but got scalar"));
1602 *vectype
= atype
.eltype
;
1609 #define NEON_SCALAR_REG(X) ((X) >> 4)
1610 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1612 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1613 have enough information to be able to do a good job bounds-checking. So, we
1614 just do easy checks here, and do further checks later. */
1617 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1621 struct neon_typed_alias atype
;
1623 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1625 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1628 if (atype
.index
== NEON_ALL_LANES
)
1630 first_error (_("scalar must have an index"));
1633 else if (atype
.index
>= 64 / elsize
)
1635 first_error (_("scalar index out of range"));
1640 *type
= atype
.eltype
;
1644 return reg
* 16 + atype
.index
;
1647 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1650 parse_reg_list (char ** strp
)
1652 char * str
= * strp
;
1656 /* We come back here if we get ranges concatenated by '+' or '|'. */
1659 skip_whitespace (str
);
1673 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1675 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1685 first_error (_("bad range in register list"));
1689 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1691 if (range
& (1 << i
))
1693 (_("Warning: duplicated register (r%d) in register list"),
1701 if (range
& (1 << reg
))
1702 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1704 else if (reg
<= cur_reg
)
1705 as_tsktsk (_("Warning: register range not in ascending order"));
1710 while (skip_past_comma (&str
) != FAIL
1711 || (in_range
= 1, *str
++ == '-'));
1714 if (skip_past_char (&str
, '}') == FAIL
)
1716 first_error (_("missing `}'"));
1724 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1727 if (exp
.X_op
== O_constant
)
1729 if (exp
.X_add_number
1730 != (exp
.X_add_number
& 0x0000ffff))
1732 inst
.error
= _("invalid register mask");
1736 if ((range
& exp
.X_add_number
) != 0)
1738 int regno
= range
& exp
.X_add_number
;
1741 regno
= (1 << regno
) - 1;
1743 (_("Warning: duplicated register (r%d) in register list"),
1747 range
|= exp
.X_add_number
;
1751 if (inst
.reloc
.type
!= 0)
1753 inst
.error
= _("expression too complex");
1757 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1758 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1759 inst
.reloc
.pc_rel
= 0;
1763 if (*str
== '|' || *str
== '+')
1769 while (another_range
);
1775 /* Types of registers in a list. */
1784 /* Parse a VFP register list. If the string is invalid return FAIL.
1785 Otherwise return the number of registers, and set PBASE to the first
1786 register. Parses registers of type ETYPE.
1787 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1788 - Q registers can be used to specify pairs of D registers
1789 - { } can be omitted from around a singleton register list
1790 FIXME: This is not implemented, as it would require backtracking in
1793 This could be done (the meaning isn't really ambiguous), but doesn't
1794 fit in well with the current parsing framework.
1795 - 32 D registers may be used (also true for VFPv3).
1796 FIXME: Types are ignored in these register lists, which is probably a
1800 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1805 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1809 unsigned long mask
= 0;
1812 if (skip_past_char (&str
, '{') == FAIL
)
1814 inst
.error
= _("expecting {");
1821 regtype
= REG_TYPE_VFS
;
1826 regtype
= REG_TYPE_VFD
;
1829 case REGLIST_NEON_D
:
1830 regtype
= REG_TYPE_NDQ
;
1834 if (etype
!= REGLIST_VFP_S
)
1836 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1841 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1844 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1851 base_reg
= max_regs
;
1855 int setmask
= 1, addregs
= 1;
1857 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1859 if (new_base
== FAIL
)
1861 first_error (_(reg_expected_msgs
[regtype
]));
1865 if (new_base
>= max_regs
)
1867 first_error (_("register out of range in list"));
1871 /* Note: a value of 2 * n is returned for the register Q<n>. */
1872 if (regtype
== REG_TYPE_NQ
)
1878 if (new_base
< base_reg
)
1879 base_reg
= new_base
;
1881 if (mask
& (setmask
<< new_base
))
1883 first_error (_("invalid register list"));
1887 if ((mask
>> new_base
) != 0 && ! warned
)
1889 as_tsktsk (_("register list not in ascending order"));
1893 mask
|= setmask
<< new_base
;
1896 if (*str
== '-') /* We have the start of a range expression */
1902 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1905 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1909 if (high_range
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 if (regtype
== REG_TYPE_NQ
)
1916 high_range
= high_range
+ 1;
1918 if (high_range
<= new_base
)
1920 inst
.error
= _("register range not in ascending order");
1924 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1926 if (mask
& (setmask
<< new_base
))
1928 inst
.error
= _("invalid register list");
1932 mask
|= setmask
<< new_base
;
1937 while (skip_past_comma (&str
) != FAIL
);
1941 /* Sanity check -- should have raised a parse error above. */
1942 if (count
== 0 || count
> max_regs
)
1947 /* Final test -- the registers must be consecutive. */
1949 for (i
= 0; i
< count
; i
++)
1951 if ((mask
& (1u << i
)) == 0)
1953 inst
.error
= _("non-contiguous register range");
1963 /* True if two alias types are the same. */
1966 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1974 if (a
->defined
!= b
->defined
)
1977 if ((a
->defined
& NTA_HASTYPE
) != 0
1978 && (a
->eltype
.type
!= b
->eltype
.type
1979 || a
->eltype
.size
!= b
->eltype
.size
))
1982 if ((a
->defined
& NTA_HASINDEX
) != 0
1983 && (a
->index
!= b
->index
))
1989 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1990 The base register is put in *PBASE.
1991 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1993 The register stride (minus one) is put in bit 4 of the return value.
1994 Bits [6:5] encode the list length (minus one).
1995 The type of the list elements is put in *ELTYPE, if non-NULL. */
1997 #define NEON_LANE(X) ((X) & 0xf)
1998 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1999 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2002 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2003 struct neon_type_el
*eltype
)
2010 int leading_brace
= 0;
2011 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2012 const char *const incr_error
= _("register stride must be 1 or 2");
2013 const char *const type_error
= _("mismatched element/structure types in list");
2014 struct neon_typed_alias firsttype
;
2015 firsttype
.defined
= 0;
2016 firsttype
.eltype
.type
= NT_invtype
;
2017 firsttype
.eltype
.size
= -1;
2018 firsttype
.index
= -1;
2020 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2025 struct neon_typed_alias atype
;
2026 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2030 first_error (_(reg_expected_msgs
[rtype
]));
2037 if (rtype
== REG_TYPE_NQ
)
2043 else if (reg_incr
== -1)
2045 reg_incr
= getreg
- base_reg
;
2046 if (reg_incr
< 1 || reg_incr
> 2)
2048 first_error (_(incr_error
));
2052 else if (getreg
!= base_reg
+ reg_incr
* count
)
2054 first_error (_(incr_error
));
2058 if (! neon_alias_types_same (&atype
, &firsttype
))
2060 first_error (_(type_error
));
2064 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2068 struct neon_typed_alias htype
;
2069 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2071 lane
= NEON_INTERLEAVE_LANES
;
2072 else if (lane
!= NEON_INTERLEAVE_LANES
)
2074 first_error (_(type_error
));
2079 else if (reg_incr
!= 1)
2081 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2085 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2088 first_error (_(reg_expected_msgs
[rtype
]));
2091 if (! neon_alias_types_same (&htype
, &firsttype
))
2093 first_error (_(type_error
));
2096 count
+= hireg
+ dregs
- getreg
;
2100 /* If we're using Q registers, we can't use [] or [n] syntax. */
2101 if (rtype
== REG_TYPE_NQ
)
2107 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2111 else if (lane
!= atype
.index
)
2113 first_error (_(type_error
));
2117 else if (lane
== -1)
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2128 /* No lane set by [x]. We must be interleaving structures. */
2130 lane
= NEON_INTERLEAVE_LANES
;
2133 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2134 || (count
> 1 && reg_incr
== -1))
2136 first_error (_("error parsing element/structure list"));
2140 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2142 first_error (_("expected }"));
2150 *eltype
= firsttype
.eltype
;
2155 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2158 /* Parse an explicit relocation suffix on an expression. This is
2159 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2160 arm_reloc_hsh contains no entries, so this function can only
2161 succeed if there is no () after the word. Returns -1 on error,
2162 BFD_RELOC_UNUSED if there wasn't any suffix. */
2165 parse_reloc (char **str
)
2167 struct reloc_entry
*r
;
2171 return BFD_RELOC_UNUSED
;
2176 while (*q
&& *q
!= ')' && *q
!= ',')
2181 if ((r
= (struct reloc_entry
*)
2182 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2189 /* Directives: register aliases. */
2191 static struct reg_entry
*
2192 insert_reg_alias (char *str
, unsigned number
, int type
)
2194 struct reg_entry
*new_reg
;
2197 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2199 if (new_reg
->builtin
)
2200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2202 /* Only warn about a redefinition if it's not defined as the
2204 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2205 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2210 name
= xstrdup (str
);
2211 new_reg
= XNEW (struct reg_entry
);
2213 new_reg
->name
= name
;
2214 new_reg
->number
= number
;
2215 new_reg
->type
= type
;
2216 new_reg
->builtin
= FALSE
;
2217 new_reg
->neon
= NULL
;
2219 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2226 insert_neon_reg_alias (char *str
, int number
, int type
,
2227 struct neon_typed_alias
*atype
)
2229 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2233 first_error (_("attempt to redefine typed alias"));
2239 reg
->neon
= XNEW (struct neon_typed_alias
);
2240 *reg
->neon
= *atype
;
2244 /* Look for the .req directive. This is of the form:
2246 new_register_name .req existing_register_name
2248 If we find one, or if it looks sufficiently like one that we want to
2249 handle any error here, return TRUE. Otherwise return FALSE. */
2252 create_register_alias (char * newname
, char *p
)
2254 struct reg_entry
*old
;
2255 char *oldname
, *nbuf
;
2258 /* The input scrubber ensures that whitespace after the mnemonic is
2259 collapsed to single spaces. */
2261 if (strncmp (oldname
, " .req ", 6) != 0)
2265 if (*oldname
== '\0')
2268 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2271 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2275 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2276 the desired alias name, and p points to its end. If not, then
2277 the desired alias name is in the global original_case_string. */
2278 #ifdef TC_CASE_SENSITIVE
2281 newname
= original_case_string
;
2282 nlen
= strlen (newname
);
2285 nbuf
= xmemdup0 (newname
, nlen
);
2287 /* Create aliases under the new name as stated; an all-lowercase
2288 version of the new name; and an all-uppercase version of the new
2290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2292 for (p
= nbuf
; *p
; p
++)
2295 if (strncmp (nbuf
, newname
, nlen
))
2297 /* If this attempt to create an additional alias fails, do not bother
2298 trying to create the all-lower case alias. We will fail and issue
2299 a second, duplicate error message. This situation arises when the
2300 programmer does something like:
2303 The second .req creates the "Foo" alias but then fails to create
2304 the artificial FOO alias because it has already been created by the
2306 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2313 for (p
= nbuf
; *p
; p
++)
2316 if (strncmp (nbuf
, newname
, nlen
))
2317 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2324 /* Create a Neon typed/indexed register alias using directives, e.g.:
2329 These typed registers can be used instead of the types specified after the
2330 Neon mnemonic, so long as all operands given have types. Types can also be
2331 specified directly, e.g.:
2332 vadd d0.s32, d1.s32, d2.s32 */
2335 create_neon_reg_alias (char *newname
, char *p
)
2337 enum arm_reg_type basetype
;
2338 struct reg_entry
*basereg
;
2339 struct reg_entry mybasereg
;
2340 struct neon_type ntype
;
2341 struct neon_typed_alias typeinfo
;
2342 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2345 typeinfo
.defined
= 0;
2346 typeinfo
.eltype
.type
= NT_invtype
;
2347 typeinfo
.eltype
.size
= -1;
2348 typeinfo
.index
= -1;
2352 if (strncmp (p
, " .dn ", 5) == 0)
2353 basetype
= REG_TYPE_VFD
;
2354 else if (strncmp (p
, " .qn ", 5) == 0)
2355 basetype
= REG_TYPE_NQ
;
2364 basereg
= arm_reg_parse_multi (&p
);
2366 if (basereg
&& basereg
->type
!= basetype
)
2368 as_bad (_("bad type for register"));
2372 if (basereg
== NULL
)
2375 /* Try parsing as an integer. */
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2377 if (exp
.X_op
!= O_constant
)
2379 as_bad (_("expression must be constant"));
2382 basereg
= &mybasereg
;
2383 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2389 typeinfo
= *basereg
->neon
;
2391 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2393 /* We got a type. */
2394 if (typeinfo
.defined
& NTA_HASTYPE
)
2396 as_bad (_("can't redefine the type of a register alias"));
2400 typeinfo
.defined
|= NTA_HASTYPE
;
2401 if (ntype
.elems
!= 1)
2403 as_bad (_("you must specify a single type only"));
2406 typeinfo
.eltype
= ntype
.el
[0];
2409 if (skip_past_char (&p
, '[') == SUCCESS
)
2412 /* We got a scalar index. */
2414 if (typeinfo
.defined
& NTA_HASINDEX
)
2416 as_bad (_("can't redefine the index of a scalar alias"));
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2422 if (exp
.X_op
!= O_constant
)
2424 as_bad (_("scalar index must be constant"));
2428 typeinfo
.defined
|= NTA_HASINDEX
;
2429 typeinfo
.index
= exp
.X_add_number
;
2431 if (skip_past_char (&p
, ']') == FAIL
)
2433 as_bad (_("expecting ]"));
2438 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2439 the desired alias name, and p points to its end. If not, then
2440 the desired alias name is in the global original_case_string. */
2441 #ifdef TC_CASE_SENSITIVE
2442 namelen
= nameend
- newname
;
2444 newname
= original_case_string
;
2445 namelen
= strlen (newname
);
2448 namebuf
= xmemdup0 (newname
, namelen
);
2450 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2451 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Insert name in all uppercase. */
2454 for (p
= namebuf
; *p
; p
++)
2457 if (strncmp (namebuf
, newname
, namelen
))
2458 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2459 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2461 /* Insert name in all lowercase. */
2462 for (p
= namebuf
; *p
; p
++)
2465 if (strncmp (namebuf
, newname
, namelen
))
2466 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2467 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2473 /* Should never be called, as .req goes between the alias and the
2474 register name, not at the beginning of the line. */
2477 s_req (int a ATTRIBUTE_UNUSED
)
2479 as_bad (_("invalid syntax for .req directive"));
2483 s_dn (int a ATTRIBUTE_UNUSED
)
2485 as_bad (_("invalid syntax for .dn directive"));
2489 s_qn (int a ATTRIBUTE_UNUSED
)
2491 as_bad (_("invalid syntax for .qn directive"));
2494 /* The .unreq directive deletes an alias which was previously defined
2495 by .req. For example:
2501 s_unreq (int a ATTRIBUTE_UNUSED
)
2506 name
= input_line_pointer
;
2508 while (*input_line_pointer
!= 0
2509 && *input_line_pointer
!= ' '
2510 && *input_line_pointer
!= '\n')
2511 ++input_line_pointer
;
2513 saved_char
= *input_line_pointer
;
2514 *input_line_pointer
= 0;
2517 as_bad (_("invalid syntax for .unreq directive"));
2520 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2524 as_bad (_("unknown register alias '%s'"), name
);
2525 else if (reg
->builtin
)
2526 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2533 hash_delete (arm_reg_hsh
, name
, FALSE
);
2534 free ((char *) reg
->name
);
2539 /* Also locate the all upper case and all lower case versions.
2540 Do not complain if we cannot find one or the other as it
2541 was probably deleted above. */
2543 nbuf
= strdup (name
);
2544 for (p
= nbuf
; *p
; p
++)
2546 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2549 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2550 free ((char *) reg
->name
);
2556 for (p
= nbuf
; *p
; p
++)
2558 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2561 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2562 free ((char *) reg
->name
);
2572 *input_line_pointer
= saved_char
;
2573 demand_empty_rest_of_line ();
2576 /* Directives: Instruction set selection. */
2579 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2580 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2581 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2582 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2584 /* Create a new mapping symbol for the transition to STATE. */
2587 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2590 const char * symname
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2605 type
= BSF_NO_FLAGS
;
2611 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2612 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2617 THUMB_SET_FUNC (symbolP
, 0);
2618 ARM_SET_THUMB (symbolP
, 0);
2619 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2623 THUMB_SET_FUNC (symbolP
, 1);
2624 ARM_SET_THUMB (symbolP
, 1);
2625 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2633 /* Save the mapping symbols for future reference. Also check that
2634 we do not place two mapping symbols at the same offset within a
2635 frag. We'll handle overlap between frags in
2636 check_mapping_symbols.
2638 If .fill or other data filling directive generates zero sized data,
2639 the mapping symbol for the following code will have the same value
2640 as the one generated for the data filling directive. In this case,
2641 we replace the old symbol with the new one at the same address. */
2644 if (frag
->tc_frag_data
.first_map
!= NULL
)
2646 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2647 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2649 frag
->tc_frag_data
.first_map
= symbolP
;
2651 if (frag
->tc_frag_data
.last_map
!= NULL
)
2653 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2654 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2655 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2657 frag
->tc_frag_data
.last_map
= symbolP
;
2660 /* We must sometimes convert a region marked as code to data during
2661 code alignment, if an odd number of bytes have to be padded. The
2662 code mapping symbol is pushed to an aligned address. */
2665 insert_data_mapping_symbol (enum mstate state
,
2666 valueT value
, fragS
*frag
, offsetT bytes
)
2668 /* If there was already a mapping symbol, remove it. */
2669 if (frag
->tc_frag_data
.last_map
!= NULL
2670 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2672 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2676 know (frag
->tc_frag_data
.first_map
== symp
);
2677 frag
->tc_frag_data
.first_map
= NULL
;
2679 frag
->tc_frag_data
.last_map
= NULL
;
2680 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2683 make_mapping_symbol (MAP_DATA
, value
, frag
);
2684 make_mapping_symbol (state
, value
+ bytes
, frag
);
2687 static void mapping_state_2 (enum mstate state
, int max_chars
);
2689 /* Set the mapping state to STATE. Only call this when about to
2690 emit some STATE bytes to the file. */
2692 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2694 mapping_state (enum mstate state
)
2696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2698 if (mapstate
== state
)
2699 /* The mapping symbol has already been emitted.
2700 There is nothing else to do. */
2703 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2705 All ARM instructions require 4-byte alignment.
2706 (Almost) all Thumb instructions require 2-byte alignment.
2708 When emitting instructions into any section, mark the section
2711 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2712 but themselves require 2-byte alignment; this applies to some
2713 PC- relative forms. However, these cases will involve implicit
2714 literal pool generation or an explicit .align >=2, both of
2715 which will cause the section to me marked with sufficient
2716 alignment. Thus, we don't handle those cases here. */
2717 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2719 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2720 /* This case will be evaluated later. */
2723 mapping_state_2 (state
, 0);
2726 /* Same as mapping_state, but MAX_CHARS bytes have already been
2727 allocated. Put the mapping symbol that far back. */
2730 mapping_state_2 (enum mstate state
, int max_chars
)
2732 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2734 if (!SEG_NORMAL (now_seg
))
2737 if (mapstate
== state
)
2738 /* The mapping symbol has already been emitted.
2739 There is nothing else to do. */
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2743 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2745 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2746 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2749 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2752 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2753 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2757 #define mapping_state(x) ((void)0)
2758 #define mapping_state_2(x, y) ((void)0)
2761 /* Find the real, Thumb encoded start of a Thumb function. */
2765 find_real_start (symbolS
* symbolP
)
2768 const char * name
= S_GET_NAME (symbolP
);
2769 symbolS
* new_target
;
2771 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2772 #define STUB_NAME ".real_start_of"
2777 /* The compiler may generate BL instructions to local labels because
2778 it needs to perform a branch to a far away location. These labels
2779 do not have a corresponding ".real_start_of" label. We check
2780 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2781 the ".real_start_of" convention for nonlocal branches. */
2782 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2785 real_start
= concat (STUB_NAME
, name
, NULL
);
2786 new_target
= symbol_find (real_start
);
2789 if (new_target
== NULL
)
2791 as_warn (_("Failed to find real start of function: %s\n"), name
);
2792 new_target
= symbolP
;
2800 opcode_select (int width
)
2807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2808 as_bad (_("selected processor does not support THUMB opcodes"));
2811 /* No need to force the alignment, since we will have been
2812 coming from ARM mode, which is word-aligned. */
2813 record_alignment (now_seg
, 1);
2820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2821 as_bad (_("selected processor does not support ARM opcodes"));
2826 frag_align (2, 0, 0);
2828 record_alignment (now_seg
, 1);
2833 as_bad (_("invalid instruction size selected (%d)"), width
);
2838 s_arm (int ignore ATTRIBUTE_UNUSED
)
2841 demand_empty_rest_of_line ();
2845 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 demand_empty_rest_of_line ();
2852 s_code (int unused ATTRIBUTE_UNUSED
)
2856 temp
= get_absolute_expression ();
2861 opcode_select (temp
);
2865 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2870 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2872 /* If we are not already in thumb mode go into it, EVEN if
2873 the target processor does not support thumb instructions.
2874 This is used by gcc/config/arm/lib1funcs.asm for example
2875 to compile interworking support functions even if the
2876 target processor should not support interworking. */
2880 record_alignment (now_seg
, 1);
2883 demand_empty_rest_of_line ();
2887 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2891 /* The following label is the name/address of the start of a Thumb function.
2892 We need to know this for the interworking support. */
2893 label_is_thumb_function_name
= TRUE
;
2896 /* Perform a .set directive, but also mark the alias as
2897 being a thumb function. */
2900 s_thumb_set (int equiv
)
2902 /* XXX the following is a duplicate of the code for s_set() in read.c
2903 We cannot just call that code as we need to get at the symbol that
2910 /* Especial apologies for the random logic:
2911 This just grew, and could be parsed much more simply!
2913 delim
= get_symbol_name (& name
);
2914 end_name
= input_line_pointer
;
2915 (void) restore_line_pointer (delim
);
2917 if (*input_line_pointer
!= ',')
2920 as_bad (_("expected comma after name \"%s\""), name
);
2922 ignore_rest_of_line ();
2926 input_line_pointer
++;
2929 if (name
[0] == '.' && name
[1] == '\0')
2931 /* XXX - this should not happen to .thumb_set. */
2935 if ((symbolP
= symbol_find (name
)) == NULL
2936 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2939 /* When doing symbol listings, play games with dummy fragments living
2940 outside the normal fragment chain to record the file and line info
2942 if (listing
& LISTING_SYMBOLS
)
2944 extern struct list_info_struct
* listing_tail
;
2945 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2947 memset (dummy_frag
, 0, sizeof (fragS
));
2948 dummy_frag
->fr_type
= rs_fill
;
2949 dummy_frag
->line
= listing_tail
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2951 dummy_frag
->fr_symbol
= symbolP
;
2955 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2958 /* "set" symbols are local unless otherwise specified. */
2959 SF_SET_LOCAL (symbolP
);
2960 #endif /* OBJ_COFF */
2961 } /* Make a new symbol. */
2963 symbol_table_insert (symbolP
);
2968 && S_IS_DEFINED (symbolP
)
2969 && S_GET_SEGMENT (symbolP
) != reg_section
)
2970 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2972 pseudo_set (symbolP
);
2974 demand_empty_rest_of_line ();
2976 /* XXX Now we come to the Thumb specific bit of code. */
2978 THUMB_SET_FUNC (symbolP
, 1);
2979 ARM_SET_THUMB (symbolP
, 1);
2980 #if defined OBJ_ELF || defined OBJ_COFF
2981 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2985 /* Directives: Mode selection. */
2987 /* .syntax [unified|divided] - choose the new unified syntax
2988 (same for Arm and Thumb encoding, modulo slight differences in what
2989 can be represented) or the old divergent syntax for each mode. */
2991 s_syntax (int unused ATTRIBUTE_UNUSED
)
2995 delim
= get_symbol_name (& name
);
2997 if (!strcasecmp (name
, "unified"))
2998 unified_syntax
= TRUE
;
2999 else if (!strcasecmp (name
, "divided"))
3000 unified_syntax
= FALSE
;
3003 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3006 (void) restore_line_pointer (delim
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: sectioning and alignment. */
3013 s_bss (int ignore ATTRIBUTE_UNUSED
)
3015 /* We don't support putting frags in the BSS segment, we fake it by
3016 marking in_bss, then looking at s_skip for clues. */
3017 subseg_set (bss_section
, 0);
3018 demand_empty_rest_of_line ();
3020 #ifdef md_elf_section_change_hook
3021 md_elf_section_change_hook ();
3026 s_even (int ignore ATTRIBUTE_UNUSED
)
3028 /* Never make frag if expect extra pass. */
3030 frag_align (1, 0, 0);
3032 record_alignment (now_seg
, 1);
3034 demand_empty_rest_of_line ();
3037 /* Directives: CodeComposer Studio. */
3039 /* .ref (for CodeComposer Studio syntax only). */
3041 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3043 if (codecomposer_syntax
)
3044 ignore_rest_of_line ();
3046 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3049 /* If name is not NULL, then it is used for marking the beginning of a
3050 function, whereas if it is NULL then it means the function end. */
3052 asmfunc_debug (const char * name
)
3054 static const char * last_name
= NULL
;
3058 gas_assert (last_name
== NULL
);
3061 if (debug_type
== DEBUG_STABS
)
3062 stabs_generate_asm_func (name
, name
);
3066 gas_assert (last_name
!= NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_endfunc (last_name
, last_name
);
3076 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3078 if (codecomposer_syntax
)
3080 switch (asmfunc_state
)
3082 case OUTSIDE_ASMFUNC
:
3083 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3086 case WAITING_ASMFUNC_NAME
:
3087 as_bad (_(".asmfunc repeated."));
3090 case WAITING_ENDASMFUNC
:
3091 as_bad (_(".asmfunc without function."));
3094 demand_empty_rest_of_line ();
3097 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3101 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3103 if (codecomposer_syntax
)
3105 switch (asmfunc_state
)
3107 case OUTSIDE_ASMFUNC
:
3108 as_bad (_(".endasmfunc without a .asmfunc."));
3111 case WAITING_ASMFUNC_NAME
:
3112 as_bad (_(".endasmfunc without function."));
3115 case WAITING_ENDASMFUNC
:
3116 asmfunc_state
= OUTSIDE_ASMFUNC
;
3117 asmfunc_debug (NULL
);
3120 demand_empty_rest_of_line ();
3123 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3127 s_ccs_def (int name
)
3129 if (codecomposer_syntax
)
3132 as_bad (_(".def pseudo-op only available with -mccs flag."));
3135 /* Directives: Literal pools. */
3137 static literal_pool
*
3138 find_literal_pool (void)
3140 literal_pool
* pool
;
3142 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3144 if (pool
->section
== now_seg
3145 && pool
->sub_section
== now_subseg
)
3152 static literal_pool
*
3153 find_or_make_literal_pool (void)
3155 /* Next literal pool ID number. */
3156 static unsigned int latest_pool_num
= 1;
3157 literal_pool
* pool
;
3159 pool
= find_literal_pool ();
3163 /* Create a new pool. */
3164 pool
= XNEW (literal_pool
);
3168 pool
->next_free_entry
= 0;
3169 pool
->section
= now_seg
;
3170 pool
->sub_section
= now_subseg
;
3171 pool
->next
= list_of_pools
;
3172 pool
->symbol
= NULL
;
3173 pool
->alignment
= 2;
3175 /* Add it to the list. */
3176 list_of_pools
= pool
;
3179 /* New pools, and emptied pools, will have a NULL symbol. */
3180 if (pool
->symbol
== NULL
)
3182 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3183 (valueT
) 0, &zero_address_frag
);
3184 pool
->id
= latest_pool_num
++;
3191 /* Add the literal in the global 'inst'
3192 structure to the relevant literal pool. */
3195 add_to_lit_pool (unsigned int nbytes
)
3197 #define PADDING_SLOT 0x1
3198 #define LIT_ENTRY_SIZE_MASK 0xFF
3199 literal_pool
* pool
;
3200 unsigned int entry
, pool_size
= 0;
3201 bfd_boolean padding_slot_p
= FALSE
;
3207 imm1
= inst
.operands
[1].imm
;
3208 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3209 : inst
.reloc
.exp
.X_unsigned
? 0
3210 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3211 if (target_big_endian
)
3214 imm2
= inst
.operands
[1].imm
;
3218 pool
= find_or_make_literal_pool ();
3220 /* Check if this literal value is already in the pool. */
3221 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_constant
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_md
== nbytes
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3235 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3236 && (pool
->literals
[entry
].X_add_number
3237 == inst
.reloc
.exp
.X_add_number
)
3238 && (pool
->literals
[entry
].X_add_symbol
3239 == inst
.reloc
.exp
.X_add_symbol
)
3240 && (pool
->literals
[entry
].X_op_symbol
3241 == inst
.reloc
.exp
.X_op_symbol
)
3242 && (pool
->literals
[entry
].X_md
== nbytes
))
3245 else if ((nbytes
== 8)
3246 && !(pool_size
& 0x7)
3247 && ((entry
+ 1) != pool
->next_free_entry
)
3248 && (pool
->literals
[entry
].X_op
== O_constant
)
3249 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3250 && (pool
->literals
[entry
].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
)
3252 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3253 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3254 && (pool
->literals
[entry
+ 1].X_unsigned
3255 == inst
.reloc
.exp
.X_unsigned
))
3258 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3259 if (padding_slot_p
&& (nbytes
== 4))
3265 /* Do we need to create a new entry? */
3266 if (entry
== pool
->next_free_entry
)
3268 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3270 inst
.error
= _("literal pool overflow");
3276 /* For 8-byte entries, we align to an 8-byte boundary,
3277 and split it into two 4-byte entries, because on 32-bit
3278 host, 8-byte constants are treated as big num, thus
3279 saved in "generic_bignum" which will be overwritten
3280 by later assignments.
3282 We also need to make sure there is enough space for
3285 We also check to make sure the literal operand is a
3287 if (!(inst
.reloc
.exp
.X_op
== O_constant
3288 || inst
.reloc
.exp
.X_op
== O_big
))
3290 inst
.error
= _("invalid type for literal pool");
3293 else if (pool_size
& 0x7)
3295 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3297 inst
.error
= _("literal pool overflow");
3301 pool
->literals
[entry
] = inst
.reloc
.exp
;
3302 pool
->literals
[entry
].X_op
= O_constant
;
3303 pool
->literals
[entry
].X_add_number
= 0;
3304 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3305 pool
->next_free_entry
+= 1;
3308 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm1
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
++].X_md
= 4;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= imm2
;
3322 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3323 pool
->literals
[entry
].X_md
= 4;
3324 pool
->alignment
= 3;
3325 pool
->next_free_entry
+= 1;
3329 pool
->literals
[entry
] = inst
.reloc
.exp
;
3330 pool
->literals
[entry
].X_md
= 4;
3334 /* PR ld/12974: Record the location of the first source line to reference
3335 this entry in the literal pool. If it turns out during linking that the
3336 symbol does not exist we will be able to give an accurate line number for
3337 the (first use of the) missing reference. */
3338 if (debug_type
== DEBUG_DWARF2
)
3339 dwarf2_where (pool
->locs
+ entry
);
3341 pool
->next_free_entry
+= 1;
3343 else if (padding_slot_p
)
3345 pool
->literals
[entry
] = inst
.reloc
.exp
;
3346 pool
->literals
[entry
].X_md
= nbytes
;
3349 inst
.reloc
.exp
.X_op
= O_symbol
;
3350 inst
.reloc
.exp
.X_add_number
= pool_size
;
3351 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3357 tc_start_label_without_colon (void)
3359 bfd_boolean ret
= TRUE
;
3361 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3363 const char *label
= input_line_pointer
;
3365 while (!is_end_of_line
[(int) label
[-1]])
3370 as_bad (_("Invalid label '%s'"), label
);
3374 asmfunc_debug (label
);
3376 asmfunc_state
= WAITING_ENDASMFUNC
;
3382 /* Can't use symbol_new here, so have to create a symbol and then at
3383 a later date assign it a value. That's what these functions do. */
3386 symbol_locate (symbolS
* symbolP
,
3387 const char * name
, /* It is copied, the caller can modify. */
3388 segT segment
, /* Segment identifier (SEG_<something>). */
3389 valueT valu
, /* Symbol value. */
3390 fragS
* frag
) /* Associated fragment. */
3393 char * preserved_copy_of_name
;
3395 name_length
= strlen (name
) + 1; /* +1 for \0. */
3396 obstack_grow (¬es
, name
, name_length
);
3397 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3399 #ifdef tc_canonicalize_symbol_name
3400 preserved_copy_of_name
=
3401 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3404 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3406 S_SET_SEGMENT (symbolP
, segment
);
3407 S_SET_VALUE (symbolP
, valu
);
3408 symbol_clear_list_pointers (symbolP
);
3410 symbol_set_frag (symbolP
, frag
);
3412 /* Link to end of symbol chain. */
3414 extern int symbol_table_frozen
;
3416 if (symbol_table_frozen
)
3420 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3422 obj_symbol_new_hook (symbolP
);
3424 #ifdef tc_symbol_new_hook
3425 tc_symbol_new_hook (symbolP
);
3429 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3430 #endif /* DEBUG_SYMS */
3434 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3437 literal_pool
* pool
;
3440 pool
= find_literal_pool ();
3442 || pool
->symbol
== NULL
3443 || pool
->next_free_entry
== 0)
3446 /* Align pool as you have word accesses.
3447 Only make a frag if we have to. */
3449 frag_align (pool
->alignment
, 0, 0);
3451 record_alignment (now_seg
, 2);
3454 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3455 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3457 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3459 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3460 (valueT
) frag_now_fix (), frag_now
);
3461 symbol_table_insert (pool
->symbol
);
3463 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3465 #if defined OBJ_COFF || defined OBJ_ELF
3466 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3469 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3472 if (debug_type
== DEBUG_DWARF2
)
3473 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3475 /* First output the expression in the instruction to the pool. */
3476 emit_expr (&(pool
->literals
[entry
]),
3477 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3480 /* Mark the pool as empty. */
3481 pool
->next_free_entry
= 0;
3482 pool
->symbol
= NULL
;
3486 /* Forward declarations for functions below, in the MD interface
3488 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3489 static valueT
create_unwind_entry (int);
3490 static void start_unwind_section (const segT
, int);
3491 static void add_unwind_opcode (valueT
, int);
3492 static void flush_pending_unwind (void);
3494 /* Directives: Data. */
3497 s_arm_elf_cons (int nbytes
)
3501 #ifdef md_flush_pending_output
3502 md_flush_pending_output ();
3505 if (is_it_end_of_statement ())
3507 demand_empty_rest_of_line ();
3511 #ifdef md_cons_align
3512 md_cons_align (nbytes
);
3515 mapping_state (MAP_DATA
);
3519 char *base
= input_line_pointer
;
3523 if (exp
.X_op
!= O_symbol
)
3524 emit_expr (&exp
, (unsigned int) nbytes
);
3527 char *before_reloc
= input_line_pointer
;
3528 reloc
= parse_reloc (&input_line_pointer
);
3531 as_bad (_("unrecognized relocation suffix"));
3532 ignore_rest_of_line ();
3535 else if (reloc
== BFD_RELOC_UNUSED
)
3536 emit_expr (&exp
, (unsigned int) nbytes
);
3539 reloc_howto_type
*howto
= (reloc_howto_type
*)
3540 bfd_reloc_type_lookup (stdoutput
,
3541 (bfd_reloc_code_real_type
) reloc
);
3542 int size
= bfd_get_reloc_size (howto
);
3544 if (reloc
== BFD_RELOC_ARM_PLT32
)
3546 as_bad (_("(plt) is only valid on branch targets"));
3547 reloc
= BFD_RELOC_UNUSED
;
3552 as_bad (_("%s relocations do not fit in %d bytes"),
3553 howto
->name
, nbytes
);
3556 /* We've parsed an expression stopping at O_symbol.
3557 But there may be more expression left now that we
3558 have parsed the relocation marker. Parse it again.
3559 XXX Surely there is a cleaner way to do this. */
3560 char *p
= input_line_pointer
;
3562 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3564 memcpy (save_buf
, base
, input_line_pointer
- base
);
3565 memmove (base
+ (input_line_pointer
- before_reloc
),
3566 base
, before_reloc
- base
);
3568 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3570 memcpy (base
, save_buf
, p
- base
);
3572 offset
= nbytes
- size
;
3573 p
= frag_more (nbytes
);
3574 memset (p
, 0, nbytes
);
3575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3576 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3582 while (*input_line_pointer
++ == ',');
3584 /* Put terminator back into stream. */
3585 input_line_pointer
--;
3586 demand_empty_rest_of_line ();
3589 /* Emit an expression containing a 32-bit thumb instruction.
3590 Implementation based on put_thumb32_insn. */
3593 emit_thumb32_expr (expressionS
* exp
)
3595 expressionS exp_high
= *exp
;
3597 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3598 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3599 exp
->X_add_number
&= 0xffff;
3600 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3603 /* Guess the instruction size based on the opcode. */
3606 thumb_insn_size (int opcode
)
3608 if ((unsigned int) opcode
< 0xe800u
)
3610 else if ((unsigned int) opcode
>= 0xe8000000u
)
3617 emit_insn (expressionS
*exp
, int nbytes
)
3621 if (exp
->X_op
== O_constant
)
3626 size
= thumb_insn_size (exp
->X_add_number
);
3630 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3632 as_bad (_(".inst.n operand too big. "\
3633 "Use .inst.w instead"));
3638 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3639 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3641 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3643 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3644 emit_thumb32_expr (exp
);
3646 emit_expr (exp
, (unsigned int) size
);
3648 it_fsm_post_encode ();
3652 as_bad (_("cannot determine Thumb instruction size. " \
3653 "Use .inst.n/.inst.w instead"));
3656 as_bad (_("constant expression required"));
3661 /* Like s_arm_elf_cons but do not use md_cons_align and
3662 set the mapping state to MAP_ARM/MAP_THUMB. */
3665 s_arm_elf_inst (int nbytes
)
3667 if (is_it_end_of_statement ())
3669 demand_empty_rest_of_line ();
3673 /* Calling mapping_state () here will not change ARM/THUMB,
3674 but will ensure not to be in DATA state. */
3677 mapping_state (MAP_THUMB
);
3682 as_bad (_("width suffixes are invalid in ARM mode"));
3683 ignore_rest_of_line ();
3689 mapping_state (MAP_ARM
);
3698 if (! emit_insn (& exp
, nbytes
))
3700 ignore_rest_of_line ();
3704 while (*input_line_pointer
++ == ',');
3706 /* Put terminator back into stream. */
3707 input_line_pointer
--;
3708 demand_empty_rest_of_line ();
3711 /* Parse a .rel31 directive. */
3714 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3721 if (*input_line_pointer
== '1')
3722 highbit
= 0x80000000;
3723 else if (*input_line_pointer
!= '0')
3724 as_bad (_("expected 0 or 1"));
3726 input_line_pointer
++;
3727 if (*input_line_pointer
!= ',')
3728 as_bad (_("missing comma"));
3729 input_line_pointer
++;
3731 #ifdef md_flush_pending_output
3732 md_flush_pending_output ();
3735 #ifdef md_cons_align
3739 mapping_state (MAP_DATA
);
3744 md_number_to_chars (p
, highbit
, 4);
3745 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3746 BFD_RELOC_ARM_PREL31
);
3748 demand_empty_rest_of_line ();
3751 /* Directives: AEABI stack-unwind tables. */
3753 /* Parse an unwind_fnstart directive. Simply records the current location. */
3756 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3758 demand_empty_rest_of_line ();
3759 if (unwind
.proc_start
)
3761 as_bad (_("duplicate .fnstart directive"));
3765 /* Mark the start of the function. */
3766 unwind
.proc_start
= expr_build_dot ();
3768 /* Reset the rest of the unwind info. */
3769 unwind
.opcode_count
= 0;
3770 unwind
.table_entry
= NULL
;
3771 unwind
.personality_routine
= NULL
;
3772 unwind
.personality_index
= -1;
3773 unwind
.frame_size
= 0;
3774 unwind
.fp_offset
= 0;
3775 unwind
.fp_reg
= REG_SP
;
3777 unwind
.sp_restored
= 0;
3781 /* Parse a handlerdata directive. Creates the exception handling table entry
3782 for the function. */
3785 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3787 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3789 as_bad (MISSING_FNSTART
);
3791 if (unwind
.table_entry
)
3792 as_bad (_("duplicate .handlerdata directive"));
3794 create_unwind_entry (1);
3797 /* Parse an unwind_fnend directive. Generates the index table entry. */
3800 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3805 unsigned int marked_pr_dependency
;
3807 demand_empty_rest_of_line ();
3809 if (!unwind
.proc_start
)
3811 as_bad (_(".fnend directive without .fnstart"));
3815 /* Add eh table entry. */
3816 if (unwind
.table_entry
== NULL
)
3817 val
= create_unwind_entry (0);
3821 /* Add index table entry. This is two words. */
3822 start_unwind_section (unwind
.saved_seg
, 1);
3823 frag_align (2, 0, 0);
3824 record_alignment (now_seg
, 2);
3826 ptr
= frag_more (8);
3828 where
= frag_now_fix () - 8;
3830 /* Self relative offset of the function start. */
3831 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3832 BFD_RELOC_ARM_PREL31
);
3834 /* Indicate dependency on EHABI-defined personality routines to the
3835 linker, if it hasn't been done already. */
3836 marked_pr_dependency
3837 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3838 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3839 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3841 static const char *const name
[] =
3843 "__aeabi_unwind_cpp_pr0",
3844 "__aeabi_unwind_cpp_pr1",
3845 "__aeabi_unwind_cpp_pr2"
3847 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3848 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3849 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3850 |= 1 << unwind
.personality_index
;
3854 /* Inline exception table entry. */
3855 md_number_to_chars (ptr
+ 4, val
, 4);
3857 /* Self relative offset of the table entry. */
3858 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3859 BFD_RELOC_ARM_PREL31
);
3861 /* Restore the original section. */
3862 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3864 unwind
.proc_start
= NULL
;
3868 /* Parse an unwind_cantunwind directive. */
3871 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3873 demand_empty_rest_of_line ();
3874 if (!unwind
.proc_start
)
3875 as_bad (MISSING_FNSTART
);
3877 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3878 as_bad (_("personality routine specified for cantunwind frame"));
3880 unwind
.personality_index
= -2;
3884 /* Parse a personalityindex directive. */
3887 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3895 as_bad (_("duplicate .personalityindex directive"));
3899 if (exp
.X_op
!= O_constant
3900 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3902 as_bad (_("bad personality routine number"));
3903 ignore_rest_of_line ();
3907 unwind
.personality_index
= exp
.X_add_number
;
3909 demand_empty_rest_of_line ();
3913 /* Parse a personality directive. */
3916 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("duplicate .personality directive"));
3926 c
= get_symbol_name (& name
);
3927 p
= input_line_pointer
;
3929 ++ input_line_pointer
;
3930 unwind
.personality_routine
= symbol_find_or_make (name
);
3932 demand_empty_rest_of_line ();
3936 /* Parse a directive saving core registers. */
3939 s_arm_unwind_save_core (void)
3945 range
= parse_reg_list (&input_line_pointer
);
3948 as_bad (_("expected register list"));
3949 ignore_rest_of_line ();
3953 demand_empty_rest_of_line ();
3955 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3956 into .unwind_save {..., sp...}. We aren't bothered about the value of
3957 ip because it is clobbered by calls. */
3958 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3959 && (range
& 0x3000) == 0x1000)
3961 unwind
.opcode_count
--;
3962 unwind
.sp_restored
= 0;
3963 range
= (range
| 0x2000) & ~0x1000;
3964 unwind
.pending_offset
= 0;
3970 /* See if we can use the short opcodes. These pop a block of up to 8
3971 registers starting with r4, plus maybe r14. */
3972 for (n
= 0; n
< 8; n
++)
3974 /* Break at the first non-saved register. */
3975 if ((range
& (1 << (n
+ 4))) == 0)
3978 /* See if there are any other bits set. */
3979 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3981 /* Use the long form. */
3982 op
= 0x8000 | ((range
>> 4) & 0xfff);
3983 add_unwind_opcode (op
, 2);
3987 /* Use the short form. */
3989 op
= 0xa8; /* Pop r14. */
3991 op
= 0xa0; /* Do not pop r14. */
3993 add_unwind_opcode (op
, 1);
4000 op
= 0xb100 | (range
& 0xf);
4001 add_unwind_opcode (op
, 2);
4004 /* Record the number of bytes pushed. */
4005 for (n
= 0; n
< 16; n
++)
4007 if (range
& (1 << n
))
4008 unwind
.frame_size
+= 4;
4013 /* Parse a directive saving FPA registers. */
4016 s_arm_unwind_save_fpa (int reg
)
4022 /* Get Number of registers to transfer. */
4023 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4026 exp
.X_op
= O_illegal
;
4028 if (exp
.X_op
!= O_constant
)
4030 as_bad (_("expected , <constant>"));
4031 ignore_rest_of_line ();
4035 num_regs
= exp
.X_add_number
;
4037 if (num_regs
< 1 || num_regs
> 4)
4039 as_bad (_("number of registers must be in the range [1:4]"));
4040 ignore_rest_of_line ();
4044 demand_empty_rest_of_line ();
4049 op
= 0xb4 | (num_regs
- 1);
4050 add_unwind_opcode (op
, 1);
4055 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4056 add_unwind_opcode (op
, 2);
4058 unwind
.frame_size
+= num_regs
* 12;
4062 /* Parse a directive saving VFP registers for ARMv6 and above. */
4065 s_arm_unwind_save_vfp_armv6 (void)
4070 int num_vfpv3_regs
= 0;
4071 int num_regs_below_16
;
4073 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4076 as_bad (_("expected register list"));
4077 ignore_rest_of_line ();
4081 demand_empty_rest_of_line ();
4083 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4084 than FSTMX/FLDMX-style ones). */
4086 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4088 num_vfpv3_regs
= count
;
4089 else if (start
+ count
> 16)
4090 num_vfpv3_regs
= start
+ count
- 16;
4092 if (num_vfpv3_regs
> 0)
4094 int start_offset
= start
> 16 ? start
- 16 : 0;
4095 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4096 add_unwind_opcode (op
, 2);
4099 /* Generate opcode for registers numbered in the range 0 .. 15. */
4100 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4101 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4102 if (num_regs_below_16
> 0)
4104 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4105 add_unwind_opcode (op
, 2);
4108 unwind
.frame_size
+= count
* 8;
4112 /* Parse a directive saving VFP registers for pre-ARMv6. */
4115 s_arm_unwind_save_vfp (void)
4121 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4124 as_bad (_("expected register list"));
4125 ignore_rest_of_line ();
4129 demand_empty_rest_of_line ();
4134 op
= 0xb8 | (count
- 1);
4135 add_unwind_opcode (op
, 1);
4140 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4141 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8 + 4;
4147 /* Parse a directive saving iWMMXt data registers. */
4150 s_arm_unwind_save_mmxwr (void)
4158 if (*input_line_pointer
== '{')
4159 input_line_pointer
++;
4163 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4167 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4172 as_tsktsk (_("register list not in ascending order"));
4175 if (*input_line_pointer
== '-')
4177 input_line_pointer
++;
4178 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4181 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4184 else if (reg
>= hi_reg
)
4186 as_bad (_("bad register range"));
4189 for (; reg
< hi_reg
; reg
++)
4193 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4195 skip_past_char (&input_line_pointer
, '}');
4197 demand_empty_rest_of_line ();
4199 /* Generate any deferred opcodes because we're going to be looking at
4201 flush_pending_unwind ();
4203 for (i
= 0; i
< 16; i
++)
4205 if (mask
& (1 << i
))
4206 unwind
.frame_size
+= 8;
4209 /* Attempt to combine with a previous opcode. We do this because gcc
4210 likes to output separate unwind directives for a single block of
4212 if (unwind
.opcode_count
> 0)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4215 if ((i
& 0xf8) == 0xc0)
4218 /* Only merge if the blocks are contiguous. */
4221 if ((mask
& 0xfe00) == (1 << 9))
4223 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4224 unwind
.opcode_count
--;
4227 else if (i
== 6 && unwind
.opcode_count
>= 2)
4229 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4233 op
= 0xffff << (reg
- 1);
4235 && ((mask
& op
) == (1u << (reg
- 1))))
4237 op
= (1 << (reg
+ i
+ 1)) - 1;
4238 op
&= ~((1 << reg
) - 1);
4240 unwind
.opcode_count
-= 2;
4247 /* We want to generate opcodes in the order the registers have been
4248 saved, ie. descending order. */
4249 for (reg
= 15; reg
>= -1; reg
--)
4251 /* Save registers in blocks. */
4253 || !(mask
& (1 << reg
)))
4255 /* We found an unsaved reg. Generate opcodes to save the
4262 op
= 0xc0 | (hi_reg
- 10);
4263 add_unwind_opcode (op
, 1);
4268 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4269 add_unwind_opcode (op
, 2);
4278 ignore_rest_of_line ();
4282 s_arm_unwind_save_mmxwcg (void)
4289 if (*input_line_pointer
== '{')
4290 input_line_pointer
++;
4292 skip_whitespace (input_line_pointer
);
4296 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4306 as_tsktsk (_("register list not in ascending order"));
4309 if (*input_line_pointer
== '-')
4311 input_line_pointer
++;
4312 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4318 else if (reg
>= hi_reg
)
4320 as_bad (_("bad register range"));
4323 for (; reg
< hi_reg
; reg
++)
4327 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4329 skip_past_char (&input_line_pointer
, '}');
4331 demand_empty_rest_of_line ();
4333 /* Generate any deferred opcodes because we're going to be looking at
4335 flush_pending_unwind ();
4337 for (reg
= 0; reg
< 16; reg
++)
4339 if (mask
& (1 << reg
))
4340 unwind
.frame_size
+= 4;
4343 add_unwind_opcode (op
, 2);
4346 ignore_rest_of_line ();
4350 /* Parse an unwind_save directive.
4351 If the argument is non-zero, this is a .vsave directive. */
4354 s_arm_unwind_save (int arch_v6
)
4357 struct reg_entry
*reg
;
4358 bfd_boolean had_brace
= FALSE
;
4360 if (!unwind
.proc_start
)
4361 as_bad (MISSING_FNSTART
);
4363 /* Figure out what sort of save we have. */
4364 peek
= input_line_pointer
;
4372 reg
= arm_reg_parse_multi (&peek
);
4376 as_bad (_("register expected"));
4377 ignore_rest_of_line ();
4386 as_bad (_("FPA .unwind_save does not take a register list"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
= peek
;
4391 s_arm_unwind_save_fpa (reg
->number
);
4395 s_arm_unwind_save_core ();
4400 s_arm_unwind_save_vfp_armv6 ();
4402 s_arm_unwind_save_vfp ();
4405 case REG_TYPE_MMXWR
:
4406 s_arm_unwind_save_mmxwr ();
4409 case REG_TYPE_MMXWCG
:
4410 s_arm_unwind_save_mmxwcg ();
4414 as_bad (_(".unwind_save does not support this kind of register"));
4415 ignore_rest_of_line ();
4420 /* Parse an unwind_movsp directive. */
4423 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4429 if (!unwind
.proc_start
)
4430 as_bad (MISSING_FNSTART
);
4432 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4435 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4436 ignore_rest_of_line ();
4440 /* Optional constant. */
4441 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4443 if (immediate_for_directive (&offset
) == FAIL
)
4449 demand_empty_rest_of_line ();
4451 if (reg
== REG_SP
|| reg
== REG_PC
)
4453 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4457 if (unwind
.fp_reg
!= REG_SP
)
4458 as_bad (_("unexpected .unwind_movsp directive"));
4460 /* Generate opcode to restore the value. */
4462 add_unwind_opcode (op
, 1);
4464 /* Record the information for later. */
4465 unwind
.fp_reg
= reg
;
4466 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4467 unwind
.sp_restored
= 1;
4470 /* Parse an unwind_pad directive. */
4473 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4477 if (!unwind
.proc_start
)
4478 as_bad (MISSING_FNSTART
);
4480 if (immediate_for_directive (&offset
) == FAIL
)
4485 as_bad (_("stack increment must be multiple of 4"));
4486 ignore_rest_of_line ();
4490 /* Don't generate any opcodes, just record the details for later. */
4491 unwind
.frame_size
+= offset
;
4492 unwind
.pending_offset
+= offset
;
4494 demand_empty_rest_of_line ();
4497 /* Parse an unwind_setfp directive. */
4500 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4506 if (!unwind
.proc_start
)
4507 as_bad (MISSING_FNSTART
);
4509 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4513 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4517 as_bad (_("expected <reg>, <reg>"));
4518 ignore_rest_of_line ();
4522 /* Optional constant. */
4523 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4525 if (immediate_for_directive (&offset
) == FAIL
)
4531 demand_empty_rest_of_line ();
4533 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4535 as_bad (_("register must be either sp or set by a previous"
4536 "unwind_movsp directive"));
4540 /* Don't generate any opcodes, just record the information for later. */
4541 unwind
.fp_reg
= fp_reg
;
4543 if (sp_reg
== REG_SP
)
4544 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4546 unwind
.fp_offset
-= offset
;
4549 /* Parse an unwind_raw directive. */
4552 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4555 /* This is an arbitrary limit. */
4556 unsigned char op
[16];
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4563 if (exp
.X_op
== O_constant
4564 && skip_past_comma (&input_line_pointer
) != FAIL
)
4566 unwind
.frame_size
+= exp
.X_add_number
;
4570 exp
.X_op
= O_illegal
;
4572 if (exp
.X_op
!= O_constant
)
4574 as_bad (_("expected <offset>, <opcode>"));
4575 ignore_rest_of_line ();
4581 /* Parse the opcode. */
4586 as_bad (_("unwind opcode too long"));
4587 ignore_rest_of_line ();
4589 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4591 as_bad (_("invalid unwind opcode"));
4592 ignore_rest_of_line ();
4595 op
[count
++] = exp
.X_add_number
;
4597 /* Parse the next byte. */
4598 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4604 /* Add the opcode bytes in reverse order. */
4606 add_unwind_opcode (op
[count
], 1);
4608 demand_empty_rest_of_line ();
4612 /* Parse a .eabi_attribute directive. */
4615 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4617 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4619 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4620 attributes_set_explicitly
[tag
] = 1;
4623 /* Emit a tls fix for the symbol. */
4626 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4630 #ifdef md_flush_pending_output
4631 md_flush_pending_output ();
4634 #ifdef md_cons_align
4638 /* Since we're just labelling the code, there's no need to define a
4641 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4642 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4643 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4644 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4646 #endif /* OBJ_ELF */
4648 static void s_arm_arch (int);
4649 static void s_arm_object_arch (int);
4650 static void s_arm_cpu (int);
4651 static void s_arm_fpu (int);
4652 static void s_arm_arch_extension (int);
4657 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4664 if (exp
.X_op
== O_symbol
)
4665 exp
.X_op
= O_secrel
;
4667 emit_expr (&exp
, 4);
4669 while (*input_line_pointer
++ == ',');
4671 input_line_pointer
--;
4672 demand_empty_rest_of_line ();
4676 /* This table describes all the machine specific pseudo-ops the assembler
4677 has to support. The fields are:
4678 pseudo-op name without dot
4679 function to call to execute this pseudo-op
4680 Integer arg to pass to the function. */
4682 const pseudo_typeS md_pseudo_table
[] =
4684 /* Never called because '.req' does not start a line. */
4685 { "req", s_req
, 0 },
4686 /* Following two are likewise never called. */
4689 { "unreq", s_unreq
, 0 },
4690 { "bss", s_bss
, 0 },
4691 { "align", s_align_ptwo
, 2 },
4692 { "arm", s_arm
, 0 },
4693 { "thumb", s_thumb
, 0 },
4694 { "code", s_code
, 0 },
4695 { "force_thumb", s_force_thumb
, 0 },
4696 { "thumb_func", s_thumb_func
, 0 },
4697 { "thumb_set", s_thumb_set
, 0 },
4698 { "even", s_even
, 0 },
4699 { "ltorg", s_ltorg
, 0 },
4700 { "pool", s_ltorg
, 0 },
4701 { "syntax", s_syntax
, 0 },
4702 { "cpu", s_arm_cpu
, 0 },
4703 { "arch", s_arm_arch
, 0 },
4704 { "object_arch", s_arm_object_arch
, 0 },
4705 { "fpu", s_arm_fpu
, 0 },
4706 { "arch_extension", s_arm_arch_extension
, 0 },
4708 { "word", s_arm_elf_cons
, 4 },
4709 { "long", s_arm_elf_cons
, 4 },
4710 { "inst.n", s_arm_elf_inst
, 2 },
4711 { "inst.w", s_arm_elf_inst
, 4 },
4712 { "inst", s_arm_elf_inst
, 0 },
4713 { "rel31", s_arm_rel31
, 0 },
4714 { "fnstart", s_arm_unwind_fnstart
, 0 },
4715 { "fnend", s_arm_unwind_fnend
, 0 },
4716 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4717 { "personality", s_arm_unwind_personality
, 0 },
4718 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4719 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4720 { "save", s_arm_unwind_save
, 0 },
4721 { "vsave", s_arm_unwind_save
, 1 },
4722 { "movsp", s_arm_unwind_movsp
, 0 },
4723 { "pad", s_arm_unwind_pad
, 0 },
4724 { "setfp", s_arm_unwind_setfp
, 0 },
4725 { "unwind_raw", s_arm_unwind_raw
, 0 },
4726 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4727 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4731 /* These are used for dwarf. */
4735 /* These are used for dwarf2. */
4736 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4737 { "loc", dwarf2_directive_loc
, 0 },
4738 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4740 { "extend", float_cons
, 'x' },
4741 { "ldouble", float_cons
, 'x' },
4742 { "packed", float_cons
, 'p' },
4744 {"secrel32", pe_directive_secrel
, 0},
4747 /* These are for compatibility with CodeComposer Studio. */
4748 {"ref", s_ccs_ref
, 0},
4749 {"def", s_ccs_def
, 0},
4750 {"asmfunc", s_ccs_asmfunc
, 0},
4751 {"endasmfunc", s_ccs_endasmfunc
, 0},
4756 /* Parser functions used exclusively in instruction operands. */
4758 /* Generic immediate-value read function for use in insn parsing.
4759 STR points to the beginning of the immediate (the leading #);
4760 VAL receives the value; if the value is outside [MIN, MAX]
4761 issue an error. PREFIX_OPT is true if the immediate prefix is
4765 parse_immediate (char **str
, int *val
, int min
, int max
,
4766 bfd_boolean prefix_opt
)
4769 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4770 if (exp
.X_op
!= O_constant
)
4772 inst
.error
= _("constant expression required");
4776 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4778 inst
.error
= _("immediate value out of range");
4782 *val
= exp
.X_add_number
;
4786 /* Less-generic immediate-value read function with the possibility of loading a
4787 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4788 instructions. Puts the result directly in inst.operands[i]. */
4791 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4792 bfd_boolean allow_symbol_p
)
4795 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4798 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4800 if (exp_p
->X_op
== O_constant
)
4802 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4803 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4804 O_constant. We have to be careful not to break compilation for
4805 32-bit X_add_number, though. */
4806 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4808 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4809 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4811 inst
.operands
[i
].regisimm
= 1;
4814 else if (exp_p
->X_op
== O_big
4815 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4817 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4819 /* Bignums have their least significant bits in
4820 generic_bignum[0]. Make sure we put 32 bits in imm and
4821 32 bits in reg, in a (hopefully) portable way. */
4822 gas_assert (parts
!= 0);
4824 /* Make sure that the number is not too big.
4825 PR 11972: Bignums can now be sign-extended to the
4826 size of a .octa so check that the out of range bits
4827 are all zero or all one. */
4828 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4830 LITTLENUM_TYPE m
= -1;
4832 if (generic_bignum
[parts
* 2] != 0
4833 && generic_bignum
[parts
* 2] != m
)
4836 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4837 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4841 inst
.operands
[i
].imm
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].reg
= 0;
4846 for (j
= 0; j
< parts
; j
++, idx
++)
4847 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4848 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4849 inst
.operands
[i
].regisimm
= 1;
4851 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4859 /* Returns the pseudo-register number of an FPA immediate constant,
4860 or FAIL if there isn't a valid constant here. */
4863 parse_fpa_immediate (char ** str
)
4865 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4871 /* First try and match exact strings, this is to guarantee
4872 that some formats will work even for cross assembly. */
4874 for (i
= 0; fp_const
[i
]; i
++)
4876 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4880 *str
+= strlen (fp_const
[i
]);
4881 if (is_end_of_line
[(unsigned char) **str
])
4887 /* Just because we didn't get a match doesn't mean that the constant
4888 isn't valid, just that it is in a format that we don't
4889 automatically recognize. Try parsing it with the standard
4890 expression routines. */
4892 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4894 /* Look for a raw floating point number. */
4895 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4896 && is_end_of_line
[(unsigned char) *save_in
])
4898 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4900 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4902 if (words
[j
] != fp_values
[i
][j
])
4906 if (j
== MAX_LITTLENUMS
)
4914 /* Try and parse a more complex expression, this will probably fail
4915 unless the code uses a floating point prefix (eg "0f"). */
4916 save_in
= input_line_pointer
;
4917 input_line_pointer
= *str
;
4918 if (expression (&exp
) == absolute_section
4919 && exp
.X_op
== O_big
4920 && exp
.X_add_number
< 0)
4922 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4924 #define X_PRECISION 5
4925 #define E_PRECISION 15L
4926 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4930 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4932 if (words
[j
] != fp_values
[i
][j
])
4936 if (j
== MAX_LITTLENUMS
)
4938 *str
= input_line_pointer
;
4939 input_line_pointer
= save_in
;
4946 *str
= input_line_pointer
;
4947 input_line_pointer
= save_in
;
4948 inst
.error
= _("invalid FPA immediate expression");
4952 /* Returns 1 if a number has "quarter-precision" float format
4953 0baBbbbbbc defgh000 00000000 00000000. */
4956 is_quarter_float (unsigned imm
)
4958 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4959 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4963 /* Detect the presence of a floating point or integer zero constant,
4967 parse_ifimm_zero (char **in
)
4971 if (!is_immediate_prefix (**in
))
4973 /* In unified syntax, all prefixes are optional. */
4974 if (!unified_syntax
)
4980 /* Accept #0x0 as a synonym for #0. */
4981 if (strncmp (*in
, "0x", 2) == 0)
4984 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4989 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4990 &generic_floating_point_number
);
4993 && generic_floating_point_number
.sign
== '+'
4994 && (generic_floating_point_number
.low
4995 > generic_floating_point_number
.leader
))
5001 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5002 0baBbbbbbc defgh000 00000000 00000000.
5003 The zero and minus-zero cases need special handling, since they can't be
5004 encoded in the "quarter-precision" float format, but can nonetheless be
5005 loaded as integer constants. */
5008 parse_qfloat_immediate (char **ccp
, int *immed
)
5012 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5013 int found_fpchar
= 0;
5015 skip_past_char (&str
, '#');
5017 /* We must not accidentally parse an integer as a floating-point number. Make
5018 sure that the value we parse is not an integer by checking for special
5019 characters '.' or 'e'.
5020 FIXME: This is a horrible hack, but doing better is tricky because type
5021 information isn't in a very usable state at parse time. */
5023 skip_whitespace (fpnum
);
5025 if (strncmp (fpnum
, "0x", 2) == 0)
5029 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5030 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5040 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5042 unsigned fpword
= 0;
5045 /* Our FP word must be 32 bits (single-precision FP). */
5046 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5048 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5052 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5065 /* Shift operands. */
5068 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5071 struct asm_shift_name
5074 enum shift_kind kind
;
5077 /* Third argument to parse_shift. */
5078 enum parse_shift_mode
5080 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5081 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5082 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5083 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5084 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5087 /* Parse a <shift> specifier on an ARM data processing instruction.
5088 This has three forms:
5090 (LSL|LSR|ASL|ASR|ROR) Rs
5091 (LSL|LSR|ASL|ASR|ROR) #imm
5094 Note that ASL is assimilated to LSL in the instruction encoding, and
5095 RRX to ROR #0 (which cannot be written as such). */
5098 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5100 const struct asm_shift_name
*shift_name
;
5101 enum shift_kind shift
;
5106 for (p
= *str
; ISALPHA (*p
); p
++)
5111 inst
.error
= _("shift expression expected");
5115 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5118 if (shift_name
== NULL
)
5120 inst
.error
= _("shift expression expected");
5124 shift
= shift_name
->kind
;
5128 case NO_SHIFT_RESTRICT
:
5129 case SHIFT_IMMEDIATE
: break;
5131 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5132 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5134 inst
.error
= _("'LSL' or 'ASR' required");
5139 case SHIFT_LSL_IMMEDIATE
:
5140 if (shift
!= SHIFT_LSL
)
5142 inst
.error
= _("'LSL' required");
5147 case SHIFT_ASR_IMMEDIATE
:
5148 if (shift
!= SHIFT_ASR
)
5150 inst
.error
= _("'ASR' required");
5158 if (shift
!= SHIFT_RRX
)
5160 /* Whitespace can appear here if the next thing is a bare digit. */
5161 skip_whitespace (p
);
5163 if (mode
== NO_SHIFT_RESTRICT
5164 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5166 inst
.operands
[i
].imm
= reg
;
5167 inst
.operands
[i
].immisreg
= 1;
5169 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5172 inst
.operands
[i
].shift_kind
= shift
;
5173 inst
.operands
[i
].shifted
= 1;
5178 /* Parse a <shifter_operand> for an ARM data processing instruction:
5181 #<immediate>, <rotate>
5185 where <shift> is defined by parse_shift above, and <rotate> is a
5186 multiple of 2 between 0 and 30. Validation of immediate operands
5187 is deferred to md_apply_fix. */
5190 parse_shifter_operand (char **str
, int i
)
5195 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5197 inst
.operands
[i
].reg
= value
;
5198 inst
.operands
[i
].isreg
= 1;
5200 /* parse_shift will override this if appropriate */
5201 inst
.reloc
.exp
.X_op
= O_constant
;
5202 inst
.reloc
.exp
.X_add_number
= 0;
5204 if (skip_past_comma (str
) == FAIL
)
5207 /* Shift operation on register. */
5208 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5211 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5214 if (skip_past_comma (str
) == SUCCESS
)
5216 /* #x, y -- ie explicit rotation by Y. */
5217 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5220 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5222 inst
.error
= _("constant expression expected");
5226 value
= exp
.X_add_number
;
5227 if (value
< 0 || value
> 30 || value
% 2 != 0)
5229 inst
.error
= _("invalid rotation");
5232 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5234 inst
.error
= _("invalid constant");
5238 /* Encode as specified. */
5239 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5243 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5244 inst
.reloc
.pc_rel
= 0;
5248 /* Group relocation information. Each entry in the table contains the
5249 textual name of the relocation as may appear in assembler source
5250 and must end with a colon.
5251 Along with this textual name are the relocation codes to be used if
5252 the corresponding instruction is an ALU instruction (ADD or SUB only),
5253 an LDR, an LDRS, or an LDC. */
5255 struct group_reloc_table_entry
5266 /* Varieties of non-ALU group relocation. */
5273 static struct group_reloc_table_entry group_reloc_table
[] =
5274 { /* Program counter relative: */
5276 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5281 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5282 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5286 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5291 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5292 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5293 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5294 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5296 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5297 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5298 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5299 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5300 /* Section base relative */
5302 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5307 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5308 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5312 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5318 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5323 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5326 /* Absolute thumb alu relocations. */
5328 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5333 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5338 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5343 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5348 /* Given the address of a pointer pointing to the textual name of a group
5349 relocation as may appear in assembler source, attempt to find its details
5350 in group_reloc_table. The pointer will be updated to the character after
5351 the trailing colon. On failure, FAIL will be returned; SUCCESS
5352 otherwise. On success, *entry will be updated to point at the relevant
5353 group_reloc_table entry. */
5356 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5359 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5361 int length
= strlen (group_reloc_table
[i
].name
);
5363 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5364 && (*str
)[length
] == ':')
5366 *out
= &group_reloc_table
[i
];
5367 *str
+= (length
+ 1);
5375 /* Parse a <shifter_operand> for an ARM data processing instruction
5376 (as for parse_shifter_operand) where group relocations are allowed:
5379 #<immediate>, <rotate>
5380 #:<group_reloc>:<expression>
5384 where <group_reloc> is one of the strings defined in group_reloc_table.
5385 The hashes are optional.
5387 Everything else is as for parse_shifter_operand. */
5389 static parse_operand_result
5390 parse_shifter_operand_group_reloc (char **str
, int i
)
5392 /* Determine if we have the sequence of characters #: or just :
5393 coming next. If we do, then we check for a group relocation.
5394 If we don't, punt the whole lot to parse_shifter_operand. */
5396 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5397 || (*str
)[0] == ':')
5399 struct group_reloc_table_entry
*entry
;
5401 if ((*str
)[0] == '#')
5406 /* Try to parse a group relocation. Anything else is an error. */
5407 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5409 inst
.error
= _("unknown group relocation");
5410 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5413 /* We now have the group relocation table entry corresponding to
5414 the name in the assembler source. Next, we parse the expression. */
5415 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5416 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5418 /* Record the relocation type (always the ALU variant here). */
5419 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5420 gas_assert (inst
.reloc
.type
!= 0);
5422 return PARSE_OPERAND_SUCCESS
;
5425 return parse_shifter_operand (str
, i
) == SUCCESS
5426 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5428 /* Never reached. */
5431 /* Parse a Neon alignment expression. Information is written to
5432 inst.operands[i]. We assume the initial ':' has been skipped.
5434 align .imm = align << 8, .immisalign=1, .preind=0 */
5435 static parse_operand_result
5436 parse_neon_alignment (char **str
, int i
)
5441 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5443 if (exp
.X_op
!= O_constant
)
5445 inst
.error
= _("alignment must be constant");
5446 return PARSE_OPERAND_FAIL
;
5449 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5450 inst
.operands
[i
].immisalign
= 1;
5451 /* Alignments are not pre-indexes. */
5452 inst
.operands
[i
].preind
= 0;
5455 return PARSE_OPERAND_SUCCESS
;
5458 /* Parse all forms of an ARM address expression. Information is written
5459 to inst.operands[i] and/or inst.reloc.
5461 Preindexed addressing (.preind=1):
5463 [Rn, #offset] .reg=Rn .reloc.exp=offset
5464 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5465 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 .shift_kind=shift .reloc.exp=shift_imm
5468 These three may have a trailing ! which causes .writeback to be set also.
5470 Postindexed addressing (.postind=1, .writeback=1):
5472 [Rn], #offset .reg=Rn .reloc.exp=offset
5473 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5474 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5475 .shift_kind=shift .reloc.exp=shift_imm
5477 Unindexed addressing (.preind=0, .postind=0):
5479 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5483 [Rn]{!} shorthand for [Rn,#0]{!}
5484 =immediate .isreg=0 .reloc.exp=immediate
5485 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5487 It is the caller's responsibility to check for addressing modes not
5488 supported by the instruction, and to set inst.reloc.type. */
5490 static parse_operand_result
5491 parse_address_main (char **str
, int i
, int group_relocations
,
5492 group_reloc_type group_type
)
5497 if (skip_past_char (&p
, '[') == FAIL
)
5499 if (skip_past_char (&p
, '=') == FAIL
)
5501 /* Bare address - translate to PC-relative offset. */
5502 inst
.reloc
.pc_rel
= 1;
5503 inst
.operands
[i
].reg
= REG_PC
;
5504 inst
.operands
[i
].isreg
= 1;
5505 inst
.operands
[i
].preind
= 1;
5507 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5508 return PARSE_OPERAND_FAIL
;
5510 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5511 /*allow_symbol_p=*/TRUE
))
5512 return PARSE_OPERAND_FAIL
;
5515 return PARSE_OPERAND_SUCCESS
;
5518 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5519 skip_whitespace (p
);
5521 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5523 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5524 return PARSE_OPERAND_FAIL
;
5526 inst
.operands
[i
].reg
= reg
;
5527 inst
.operands
[i
].isreg
= 1;
5529 if (skip_past_comma (&p
) == SUCCESS
)
5531 inst
.operands
[i
].preind
= 1;
5534 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5536 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5538 inst
.operands
[i
].imm
= reg
;
5539 inst
.operands
[i
].immisreg
= 1;
5541 if (skip_past_comma (&p
) == SUCCESS
)
5542 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5543 return PARSE_OPERAND_FAIL
;
5545 else if (skip_past_char (&p
, ':') == SUCCESS
)
5547 /* FIXME: '@' should be used here, but it's filtered out by generic
5548 code before we get to see it here. This may be subject to
5550 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5552 if (result
!= PARSE_OPERAND_SUCCESS
)
5557 if (inst
.operands
[i
].negative
)
5559 inst
.operands
[i
].negative
= 0;
5563 if (group_relocations
5564 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5566 struct group_reloc_table_entry
*entry
;
5568 /* Skip over the #: or : sequence. */
5574 /* Try to parse a group relocation. Anything else is an
5576 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5578 inst
.error
= _("unknown group relocation");
5579 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5582 /* We now have the group relocation table entry corresponding to
5583 the name in the assembler source. Next, we parse the
5585 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5586 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5588 /* Record the relocation type. */
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5596 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5600 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5607 if (inst
.reloc
.type
== 0)
5609 inst
.error
= _("this group relocation is not allowed on this instruction");
5610 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5616 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5617 return PARSE_OPERAND_FAIL
;
5618 /* If the offset is 0, find out if it's a +0 or -0. */
5619 if (inst
.reloc
.exp
.X_op
== O_constant
5620 && inst
.reloc
.exp
.X_add_number
== 0)
5622 skip_whitespace (q
);
5626 skip_whitespace (q
);
5629 inst
.operands
[i
].negative
= 1;
5634 else if (skip_past_char (&p
, ':') == SUCCESS
)
5636 /* FIXME: '@' should be used here, but it's filtered out by generic code
5637 before we get to see it here. This may be subject to change. */
5638 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5640 if (result
!= PARSE_OPERAND_SUCCESS
)
5644 if (skip_past_char (&p
, ']') == FAIL
)
5646 inst
.error
= _("']' expected");
5647 return PARSE_OPERAND_FAIL
;
5650 if (skip_past_char (&p
, '!') == SUCCESS
)
5651 inst
.operands
[i
].writeback
= 1;
5653 else if (skip_past_comma (&p
) == SUCCESS
)
5655 if (skip_past_char (&p
, '{') == SUCCESS
)
5657 /* [Rn], {expr} - unindexed, with option */
5658 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5659 0, 255, TRUE
) == FAIL
)
5660 return PARSE_OPERAND_FAIL
;
5662 if (skip_past_char (&p
, '}') == FAIL
)
5664 inst
.error
= _("'}' expected at end of 'option' field");
5665 return PARSE_OPERAND_FAIL
;
5667 if (inst
.operands
[i
].preind
)
5669 inst
.error
= _("cannot combine index with option");
5670 return PARSE_OPERAND_FAIL
;
5673 return PARSE_OPERAND_SUCCESS
;
5677 inst
.operands
[i
].postind
= 1;
5678 inst
.operands
[i
].writeback
= 1;
5680 if (inst
.operands
[i
].preind
)
5682 inst
.error
= _("cannot combine pre- and post-indexing");
5683 return PARSE_OPERAND_FAIL
;
5687 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5689 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5691 /* We might be using the immediate for alignment already. If we
5692 are, OR the register number into the low-order bits. */
5693 if (inst
.operands
[i
].immisalign
)
5694 inst
.operands
[i
].imm
|= reg
;
5696 inst
.operands
[i
].imm
= reg
;
5697 inst
.operands
[i
].immisreg
= 1;
5699 if (skip_past_comma (&p
) == SUCCESS
)
5700 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5701 return PARSE_OPERAND_FAIL
;
5706 if (inst
.operands
[i
].negative
)
5708 inst
.operands
[i
].negative
= 0;
5711 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5712 return PARSE_OPERAND_FAIL
;
5713 /* If the offset is 0, find out if it's a +0 or -0. */
5714 if (inst
.reloc
.exp
.X_op
== O_constant
5715 && inst
.reloc
.exp
.X_add_number
== 0)
5717 skip_whitespace (q
);
5721 skip_whitespace (q
);
5724 inst
.operands
[i
].negative
= 1;
5730 /* If at this point neither .preind nor .postind is set, we have a
5731 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5732 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5734 inst
.operands
[i
].preind
= 1;
5735 inst
.reloc
.exp
.X_op
= O_constant
;
5736 inst
.reloc
.exp
.X_add_number
= 0;
5739 return PARSE_OPERAND_SUCCESS
;
5743 parse_address (char **str
, int i
)
5745 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5749 static parse_operand_result
5750 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5752 return parse_address_main (str
, i
, 1, type
);
5755 /* Parse an operand for a MOVW or MOVT instruction. */
5757 parse_half (char **str
)
5762 skip_past_char (&p
, '#');
5763 if (strncasecmp (p
, ":lower16:", 9) == 0)
5764 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5765 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5766 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5768 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5771 skip_whitespace (p
);
5774 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5777 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5779 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5781 inst
.error
= _("constant expression expected");
5784 if (inst
.reloc
.exp
.X_add_number
< 0
5785 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5787 inst
.error
= _("immediate value out of range");
5795 /* Miscellaneous. */
5797 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5798 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5800 parse_psr (char **str
, bfd_boolean lhs
)
5803 unsigned long psr_field
;
5804 const struct asm_psr
*psr
;
5806 bfd_boolean is_apsr
= FALSE
;
5807 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5809 /* PR gas/12698: If the user has specified -march=all then m_profile will
5810 be TRUE, but we want to ignore it in this case as we are building for any
5811 CPU type, including non-m variants. */
5812 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5815 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5816 feature for ease of use and backwards compatibility. */
5818 if (strncasecmp (p
, "SPSR", 4) == 0)
5821 goto unsupported_psr
;
5823 psr_field
= SPSR_BIT
;
5825 else if (strncasecmp (p
, "CPSR", 4) == 0)
5828 goto unsupported_psr
;
5832 else if (strncasecmp (p
, "APSR", 4) == 0)
5834 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5835 and ARMv7-R architecture CPUs. */
5844 while (ISALNUM (*p
) || *p
== '_');
5846 if (strncasecmp (start
, "iapsr", 5) == 0
5847 || strncasecmp (start
, "eapsr", 5) == 0
5848 || strncasecmp (start
, "xpsr", 4) == 0
5849 || strncasecmp (start
, "psr", 3) == 0)
5850 p
= start
+ strcspn (start
, "rR") + 1;
5852 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5858 /* If APSR is being written, a bitfield may be specified. Note that
5859 APSR itself is handled above. */
5860 if (psr
->field
<= 3)
5862 psr_field
= psr
->field
;
5868 /* M-profile MSR instructions have the mask field set to "10", except
5869 *PSR variants which modify APSR, which may use a different mask (and
5870 have been handled already). Do that by setting the PSR_f field
5872 return psr
->field
| (lhs
? PSR_f
: 0);
5875 goto unsupported_psr
;
5881 /* A suffix follows. */
5887 while (ISALNUM (*p
) || *p
== '_');
5891 /* APSR uses a notation for bits, rather than fields. */
5892 unsigned int nzcvq_bits
= 0;
5893 unsigned int g_bit
= 0;
5896 for (bit
= start
; bit
!= p
; bit
++)
5898 switch (TOLOWER (*bit
))
5901 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5913 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5917 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5921 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5925 inst
.error
= _("unexpected bit specified after APSR");
5930 if (nzcvq_bits
== 0x1f)
5935 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5937 inst
.error
= _("selected processor does not "
5938 "support DSP extension");
5945 if ((nzcvq_bits
& 0x20) != 0
5946 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5947 || (g_bit
& 0x2) != 0)
5949 inst
.error
= _("bad bitmask specified after APSR");
5955 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5960 psr_field
|= psr
->field
;
5966 goto error
; /* Garbage after "[CS]PSR". */
5968 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5969 is deprecated, but allow it anyway. */
5973 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5976 else if (!m_profile
)
5977 /* These bits are never right for M-profile devices: don't set them
5978 (only code paths which read/write APSR reach here). */
5979 psr_field
|= (PSR_c
| PSR_f
);
5985 inst
.error
= _("selected processor does not support requested special "
5986 "purpose register");
5990 inst
.error
= _("flag for {c}psr instruction expected");
5994 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5995 value suitable for splatting into the AIF field of the instruction. */
5998 parse_cps_flags (char **str
)
6007 case '\0': case ',':
6010 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6011 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6012 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6015 inst
.error
= _("unrecognized CPS flag");
6020 if (saw_a_flag
== 0)
6022 inst
.error
= _("missing CPS flags");
6030 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6031 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6034 parse_endian_specifier (char **str
)
6039 if (strncasecmp (s
, "BE", 2))
6041 else if (strncasecmp (s
, "LE", 2))
6045 inst
.error
= _("valid endian specifiers are be or le");
6049 if (ISALNUM (s
[2]) || s
[2] == '_')
6051 inst
.error
= _("valid endian specifiers are be or le");
6056 return little_endian
;
6059 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6060 value suitable for poking into the rotate field of an sxt or sxta
6061 instruction, or FAIL on error. */
6064 parse_ror (char **str
)
6069 if (strncasecmp (s
, "ROR", 3) == 0)
6073 inst
.error
= _("missing rotation field after comma");
6077 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6082 case 0: *str
= s
; return 0x0;
6083 case 8: *str
= s
; return 0x1;
6084 case 16: *str
= s
; return 0x2;
6085 case 24: *str
= s
; return 0x3;
6088 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6093 /* Parse a conditional code (from conds[] below). The value returned is in the
6094 range 0 .. 14, or FAIL. */
6096 parse_cond (char **str
)
6099 const struct asm_cond
*c
;
6101 /* Condition codes are always 2 characters, so matching up to
6102 3 characters is sufficient. */
6107 while (ISALPHA (*q
) && n
< 3)
6109 cond
[n
] = TOLOWER (*q
);
6114 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6117 inst
.error
= _("condition required");
6125 /* Record a use of the given feature. */
6127 record_feature_use (const arm_feature_set
*feature
)
6130 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6132 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6135 /* If the given feature available in the selected CPU, mark it as used.
6136 Returns TRUE iff feature is available. */
6138 mark_feature_used (const arm_feature_set
*feature
)
6140 /* Ensure the option is valid on the current architecture. */
6141 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6144 /* Add the appropriate architecture feature for the barrier option used.
6146 record_feature_use (feature
);
6151 /* Parse an option for a barrier instruction. Returns the encoding for the
6154 parse_barrier (char **str
)
6157 const struct asm_barrier_opt
*o
;
6160 while (ISALPHA (*q
))
6163 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6168 if (!mark_feature_used (&o
->arch
))
6175 /* Parse the operands of a table branch instruction. Similar to a memory
6178 parse_tb (char **str
)
6183 if (skip_past_char (&p
, '[') == FAIL
)
6185 inst
.error
= _("'[' expected");
6189 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6191 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6194 inst
.operands
[0].reg
= reg
;
6196 if (skip_past_comma (&p
) == FAIL
)
6198 inst
.error
= _("',' expected");
6202 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6204 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6207 inst
.operands
[0].imm
= reg
;
6209 if (skip_past_comma (&p
) == SUCCESS
)
6211 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6213 if (inst
.reloc
.exp
.X_add_number
!= 1)
6215 inst
.error
= _("invalid shift");
6218 inst
.operands
[0].shifted
= 1;
6221 if (skip_past_char (&p
, ']') == FAIL
)
6223 inst
.error
= _("']' expected");
6230 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6231 information on the types the operands can take and how they are encoded.
6232 Up to four operands may be read; this function handles setting the
6233 ".present" field for each read operand itself.
6234 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6235 else returns FAIL. */
6238 parse_neon_mov (char **str
, int *which_operand
)
6240 int i
= *which_operand
, val
;
6241 enum arm_reg_type rtype
;
6243 struct neon_type_el optype
;
6245 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6247 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6248 inst
.operands
[i
].reg
= val
;
6249 inst
.operands
[i
].isscalar
= 1;
6250 inst
.operands
[i
].vectype
= optype
;
6251 inst
.operands
[i
++].present
= 1;
6253 if (skip_past_comma (&ptr
) == FAIL
)
6256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6259 inst
.operands
[i
].reg
= val
;
6260 inst
.operands
[i
].isreg
= 1;
6261 inst
.operands
[i
].present
= 1;
6263 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6266 /* Cases 0, 1, 2, 3, 5 (D only). */
6267 if (skip_past_comma (&ptr
) == FAIL
)
6270 inst
.operands
[i
].reg
= val
;
6271 inst
.operands
[i
].isreg
= 1;
6272 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6273 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6274 inst
.operands
[i
].isvec
= 1;
6275 inst
.operands
[i
].vectype
= optype
;
6276 inst
.operands
[i
++].present
= 1;
6278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6280 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6281 Case 13: VMOV <Sd>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].present
= 1;
6286 if (rtype
== REG_TYPE_NQ
)
6288 first_error (_("can't use Neon quad register here"));
6291 else if (rtype
!= REG_TYPE_VFS
)
6294 if (skip_past_comma (&ptr
) == FAIL
)
6296 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
].present
= 1;
6303 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6306 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6307 Case 1: VMOV<c><q> <Dd>, <Dm>
6308 Case 8: VMOV.F32 <Sd>, <Sm>
6309 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6314 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6315 inst
.operands
[i
].isvec
= 1;
6316 inst
.operands
[i
].vectype
= optype
;
6317 inst
.operands
[i
].present
= 1;
6319 if (skip_past_comma (&ptr
) == SUCCESS
)
6324 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6327 inst
.operands
[i
].reg
= val
;
6328 inst
.operands
[i
].isreg
= 1;
6329 inst
.operands
[i
++].present
= 1;
6331 if (skip_past_comma (&ptr
) == FAIL
)
6334 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6337 inst
.operands
[i
].reg
= val
;
6338 inst
.operands
[i
].isreg
= 1;
6339 inst
.operands
[i
].present
= 1;
6342 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6343 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6344 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6345 Case 10: VMOV.F32 <Sd>, #<imm>
6346 Case 11: VMOV.F64 <Dd>, #<imm> */
6347 inst
.operands
[i
].immisfloat
= 1;
6348 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6350 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6351 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6355 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6359 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6362 inst
.operands
[i
].reg
= val
;
6363 inst
.operands
[i
].isreg
= 1;
6364 inst
.operands
[i
++].present
= 1;
6366 if (skip_past_comma (&ptr
) == FAIL
)
6369 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6371 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isscalar
= 1;
6374 inst
.operands
[i
].present
= 1;
6375 inst
.operands
[i
].vectype
= optype
;
6377 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6379 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6380 inst
.operands
[i
].reg
= val
;
6381 inst
.operands
[i
].isreg
= 1;
6382 inst
.operands
[i
++].present
= 1;
6384 if (skip_past_comma (&ptr
) == FAIL
)
6387 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6390 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6394 inst
.operands
[i
].reg
= val
;
6395 inst
.operands
[i
].isreg
= 1;
6396 inst
.operands
[i
].isvec
= 1;
6397 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6398 inst
.operands
[i
].vectype
= optype
;
6399 inst
.operands
[i
].present
= 1;
6401 if (rtype
== REG_TYPE_VFS
)
6405 if (skip_past_comma (&ptr
) == FAIL
)
6407 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6410 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6413 inst
.operands
[i
].reg
= val
;
6414 inst
.operands
[i
].isreg
= 1;
6415 inst
.operands
[i
].isvec
= 1;
6416 inst
.operands
[i
].issingle
= 1;
6417 inst
.operands
[i
].vectype
= optype
;
6418 inst
.operands
[i
].present
= 1;
6421 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6425 inst
.operands
[i
].reg
= val
;
6426 inst
.operands
[i
].isreg
= 1;
6427 inst
.operands
[i
].isvec
= 1;
6428 inst
.operands
[i
].issingle
= 1;
6429 inst
.operands
[i
].vectype
= optype
;
6430 inst
.operands
[i
].present
= 1;
6435 first_error (_("parse error"));
6439 /* Successfully parsed the operands. Update args. */
6445 first_error (_("expected comma"));
6449 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6453 /* Use this macro when the operand constraints are different
6454 for ARM and THUMB (e.g. ldrd). */
6455 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6456 ((arm_operand) | ((thumb_operand) << 16))
6458 /* Matcher codes for parse_operands. */
6459 enum operand_parse_code
6461 OP_stop
, /* end of line */
6463 OP_RR
, /* ARM register */
6464 OP_RRnpc
, /* ARM register, not r15 */
6465 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6466 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6467 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6468 optional trailing ! */
6469 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6470 OP_RCP
, /* Coprocessor number */
6471 OP_RCN
, /* Coprocessor register */
6472 OP_RF
, /* FPA register */
6473 OP_RVS
, /* VFP single precision register */
6474 OP_RVD
, /* VFP double precision register (0..15) */
6475 OP_RND
, /* Neon double precision register (0..31) */
6476 OP_RNQ
, /* Neon quad precision register */
6477 OP_RVSD
, /* VFP single or double precision register */
6478 OP_RNDQ
, /* Neon double or quad precision register */
6479 OP_RNSDQ
, /* Neon single, double or quad precision register */
6480 OP_RNSC
, /* Neon scalar D[X] */
6481 OP_RVC
, /* VFP control register */
6482 OP_RMF
, /* Maverick F register */
6483 OP_RMD
, /* Maverick D register */
6484 OP_RMFX
, /* Maverick FX register */
6485 OP_RMDX
, /* Maverick DX register */
6486 OP_RMAX
, /* Maverick AX register */
6487 OP_RMDS
, /* Maverick DSPSC register */
6488 OP_RIWR
, /* iWMMXt wR register */
6489 OP_RIWC
, /* iWMMXt wC register */
6490 OP_RIWG
, /* iWMMXt wCG register */
6491 OP_RXA
, /* XScale accumulator register */
6493 OP_REGLST
, /* ARM register list */
6494 OP_VRSLST
, /* VFP single-precision register list */
6495 OP_VRDLST
, /* VFP double-precision register list */
6496 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6497 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6498 OP_NSTRLST
, /* Neon element/structure list */
6500 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6501 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6502 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6503 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6504 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6505 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6506 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6507 OP_VMOV
, /* Neon VMOV operands. */
6508 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6509 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6510 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6512 OP_I0
, /* immediate zero */
6513 OP_I7
, /* immediate value 0 .. 7 */
6514 OP_I15
, /* 0 .. 15 */
6515 OP_I16
, /* 1 .. 16 */
6516 OP_I16z
, /* 0 .. 16 */
6517 OP_I31
, /* 0 .. 31 */
6518 OP_I31w
, /* 0 .. 31, optional trailing ! */
6519 OP_I32
, /* 1 .. 32 */
6520 OP_I32z
, /* 0 .. 32 */
6521 OP_I63
, /* 0 .. 63 */
6522 OP_I63s
, /* -64 .. 63 */
6523 OP_I64
, /* 1 .. 64 */
6524 OP_I64z
, /* 0 .. 64 */
6525 OP_I255
, /* 0 .. 255 */
6527 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6528 OP_I7b
, /* 0 .. 7 */
6529 OP_I15b
, /* 0 .. 15 */
6530 OP_I31b
, /* 0 .. 31 */
6532 OP_SH
, /* shifter operand */
6533 OP_SHG
, /* shifter operand with possible group relocation */
6534 OP_ADDR
, /* Memory address expression (any mode) */
6535 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6536 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6537 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6538 OP_EXP
, /* arbitrary expression */
6539 OP_EXPi
, /* same, with optional immediate prefix */
6540 OP_EXPr
, /* same, with optional relocation suffix */
6541 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6542 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6543 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6545 OP_CPSF
, /* CPS flags */
6546 OP_ENDI
, /* Endianness specifier */
6547 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6548 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6549 OP_COND
, /* conditional code */
6550 OP_TB
, /* Table branch. */
6552 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6554 OP_RRnpc_I0
, /* ARM register or literal 0 */
6555 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6556 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6557 OP_RF_IF
, /* FPA register or immediate */
6558 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6559 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6561 /* Optional operands. */
6562 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6563 OP_oI31b
, /* 0 .. 31 */
6564 OP_oI32b
, /* 1 .. 32 */
6565 OP_oI32z
, /* 0 .. 32 */
6566 OP_oIffffb
, /* 0 .. 65535 */
6567 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6569 OP_oRR
, /* ARM register */
6570 OP_oRRnpc
, /* ARM register, not the PC */
6571 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6572 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6573 OP_oRND
, /* Optional Neon double precision register */
6574 OP_oRNQ
, /* Optional Neon quad precision register */
6575 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6576 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6577 OP_oSHll
, /* LSL immediate */
6578 OP_oSHar
, /* ASR immediate */
6579 OP_oSHllar
, /* LSL or ASR immediate */
6580 OP_oROR
, /* ROR 0/8/16/24 */
6581 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6583 /* Some pre-defined mixed (ARM/THUMB) operands. */
6584 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6585 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6586 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6588 OP_FIRST_OPTIONAL
= OP_oI7b
6591 /* Generic instruction operand parser. This does no encoding and no
6592 semantic validation; it merely squirrels values away in the inst
6593 structure. Returns SUCCESS or FAIL depending on whether the
6594 specified grammar matched. */
6596 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6598 unsigned const int *upat
= pattern
;
6599 char *backtrack_pos
= 0;
6600 const char *backtrack_error
= 0;
6601 int i
, val
= 0, backtrack_index
= 0;
6602 enum arm_reg_type rtype
;
6603 parse_operand_result result
;
6604 unsigned int op_parse_code
;
6606 #define po_char_or_fail(chr) \
6609 if (skip_past_char (&str, chr) == FAIL) \
6614 #define po_reg_or_fail(regtype) \
6617 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6618 & inst.operands[i].vectype); \
6621 first_error (_(reg_expected_msgs[regtype])); \
6624 inst.operands[i].reg = val; \
6625 inst.operands[i].isreg = 1; \
6626 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6627 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6628 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6629 || rtype == REG_TYPE_VFD \
6630 || rtype == REG_TYPE_NQ); \
6634 #define po_reg_or_goto(regtype, label) \
6637 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6638 & inst.operands[i].vectype); \
6642 inst.operands[i].reg = val; \
6643 inst.operands[i].isreg = 1; \
6644 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6645 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6646 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6647 || rtype == REG_TYPE_VFD \
6648 || rtype == REG_TYPE_NQ); \
6652 #define po_imm_or_fail(min, max, popt) \
6655 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6657 inst.operands[i].imm = val; \
6661 #define po_scalar_or_goto(elsz, label) \
6664 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6667 inst.operands[i].reg = val; \
6668 inst.operands[i].isscalar = 1; \
6672 #define po_misc_or_fail(expr) \
6680 #define po_misc_or_fail_no_backtrack(expr) \
6684 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6685 backtrack_pos = 0; \
6686 if (result != PARSE_OPERAND_SUCCESS) \
6691 #define po_barrier_or_imm(str) \
6694 val = parse_barrier (&str); \
6695 if (val == FAIL && ! ISALPHA (*str)) \
6698 /* ISB can only take SY as an option. */ \
6699 || ((inst.instruction & 0xf0) == 0x60 \
6702 inst.error = _("invalid barrier type"); \
6703 backtrack_pos = 0; \
6709 skip_whitespace (str
);
6711 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6713 op_parse_code
= upat
[i
];
6714 if (op_parse_code
>= 1<<16)
6715 op_parse_code
= thumb
? (op_parse_code
>> 16)
6716 : (op_parse_code
& ((1<<16)-1));
6718 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6720 /* Remember where we are in case we need to backtrack. */
6721 gas_assert (!backtrack_pos
);
6722 backtrack_pos
= str
;
6723 backtrack_error
= inst
.error
;
6724 backtrack_index
= i
;
6727 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6728 po_char_or_fail (',');
6730 switch (op_parse_code
)
6738 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6739 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6740 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6741 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6742 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6743 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6745 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6747 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6749 /* Also accept generic coprocessor regs for unknown registers. */
6751 po_reg_or_fail (REG_TYPE_CN
);
6753 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6754 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6755 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6756 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6757 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6758 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6759 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6760 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6761 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6762 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6764 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6766 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6767 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6769 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6771 /* Neon scalar. Using an element size of 8 means that some invalid
6772 scalars are accepted here, so deal with those in later code. */
6773 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6777 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6780 po_imm_or_fail (0, 0, TRUE
);
6785 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6790 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6793 if (parse_ifimm_zero (&str
))
6794 inst
.operands
[i
].imm
= 0;
6798 = _("only floating point zero is allowed as immediate value");
6806 po_scalar_or_goto (8, try_rr
);
6809 po_reg_or_fail (REG_TYPE_RN
);
6815 po_scalar_or_goto (8, try_nsdq
);
6818 po_reg_or_fail (REG_TYPE_NSDQ
);
6824 po_scalar_or_goto (8, try_ndq
);
6827 po_reg_or_fail (REG_TYPE_NDQ
);
6833 po_scalar_or_goto (8, try_vfd
);
6836 po_reg_or_fail (REG_TYPE_VFD
);
6841 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6842 not careful then bad things might happen. */
6843 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6848 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6851 /* There's a possibility of getting a 64-bit immediate here, so
6852 we need special handling. */
6853 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6856 inst
.error
= _("immediate value is out of range");
6864 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6867 po_imm_or_fail (0, 63, TRUE
);
6872 po_char_or_fail ('[');
6873 po_reg_or_fail (REG_TYPE_RN
);
6874 po_char_or_fail (']');
6880 po_reg_or_fail (REG_TYPE_RN
);
6881 if (skip_past_char (&str
, '!') == SUCCESS
)
6882 inst
.operands
[i
].writeback
= 1;
6886 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6887 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6888 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6889 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6890 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6891 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6892 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6893 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6894 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6895 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6896 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6897 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6899 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6901 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6902 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6904 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6905 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6906 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6907 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6909 /* Immediate variants */
6911 po_char_or_fail ('{');
6912 po_imm_or_fail (0, 255, TRUE
);
6913 po_char_or_fail ('}');
6917 /* The expression parser chokes on a trailing !, so we have
6918 to find it first and zap it. */
6921 while (*s
&& *s
!= ',')
6926 inst
.operands
[i
].writeback
= 1;
6928 po_imm_or_fail (0, 31, TRUE
);
6936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6941 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6946 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6948 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6950 val
= parse_reloc (&str
);
6953 inst
.error
= _("unrecognized relocation suffix");
6956 else if (val
!= BFD_RELOC_UNUSED
)
6958 inst
.operands
[i
].imm
= val
;
6959 inst
.operands
[i
].hasreloc
= 1;
6964 /* Operand for MOVW or MOVT. */
6966 po_misc_or_fail (parse_half (&str
));
6969 /* Register or expression. */
6970 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6971 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6973 /* Register or immediate. */
6974 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6975 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6977 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6979 if (!is_immediate_prefix (*str
))
6982 val
= parse_fpa_immediate (&str
);
6985 /* FPA immediates are encoded as registers 8-15.
6986 parse_fpa_immediate has already applied the offset. */
6987 inst
.operands
[i
].reg
= val
;
6988 inst
.operands
[i
].isreg
= 1;
6991 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6992 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6994 /* Two kinds of register. */
6997 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6999 || (rege
->type
!= REG_TYPE_MMXWR
7000 && rege
->type
!= REG_TYPE_MMXWC
7001 && rege
->type
!= REG_TYPE_MMXWCG
))
7003 inst
.error
= _("iWMMXt data or control register expected");
7006 inst
.operands
[i
].reg
= rege
->number
;
7007 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7013 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7015 || (rege
->type
!= REG_TYPE_MMXWC
7016 && rege
->type
!= REG_TYPE_MMXWCG
))
7018 inst
.error
= _("iWMMXt control register expected");
7021 inst
.operands
[i
].reg
= rege
->number
;
7022 inst
.operands
[i
].isreg
= 1;
7027 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7028 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7029 case OP_oROR
: val
= parse_ror (&str
); break;
7030 case OP_COND
: val
= parse_cond (&str
); break;
7031 case OP_oBARRIER_I15
:
7032 po_barrier_or_imm (str
); break;
7034 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7040 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7041 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7043 inst
.error
= _("Banked registers are not available with this "
7049 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7053 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7056 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7058 if (strncasecmp (str
, "APSR_", 5) == 0)
7065 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7066 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7067 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7068 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7069 default: found
= 16;
7073 inst
.operands
[i
].isvec
= 1;
7074 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7075 inst
.operands
[i
].reg
= REG_PC
;
7082 po_misc_or_fail (parse_tb (&str
));
7085 /* Register lists. */
7087 val
= parse_reg_list (&str
);
7090 inst
.operands
[i
].writeback
= 1;
7096 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7104 /* Allow Q registers too. */
7105 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7110 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7112 inst
.operands
[i
].issingle
= 1;
7117 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7122 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7123 &inst
.operands
[i
].vectype
);
7126 /* Addressing modes */
7128 po_misc_or_fail (parse_address (&str
, i
));
7132 po_misc_or_fail_no_backtrack (
7133 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7137 po_misc_or_fail_no_backtrack (
7138 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7142 po_misc_or_fail_no_backtrack (
7143 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7147 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7151 po_misc_or_fail_no_backtrack (
7152 parse_shifter_operand_group_reloc (&str
, i
));
7156 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7160 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7164 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7168 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7171 /* Various value-based sanity checks and shared operations. We
7172 do not signal immediate failures for the register constraints;
7173 this allows a syntax error to take precedence. */
7174 switch (op_parse_code
)
7182 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7183 inst
.error
= BAD_PC
;
7188 if (inst
.operands
[i
].isreg
)
7190 if (inst
.operands
[i
].reg
== REG_PC
)
7191 inst
.error
= BAD_PC
;
7192 else if (inst
.operands
[i
].reg
== REG_SP
)
7193 inst
.error
= BAD_SP
;
7198 if (inst
.operands
[i
].isreg
7199 && inst
.operands
[i
].reg
== REG_PC
7200 && (inst
.operands
[i
].writeback
|| thumb
))
7201 inst
.error
= BAD_PC
;
7210 case OP_oBARRIER_I15
:
7219 inst
.operands
[i
].imm
= val
;
7226 /* If we get here, this operand was successfully parsed. */
7227 inst
.operands
[i
].present
= 1;
7231 inst
.error
= BAD_ARGS
;
7236 /* The parse routine should already have set inst.error, but set a
7237 default here just in case. */
7239 inst
.error
= _("syntax error");
7243 /* Do not backtrack over a trailing optional argument that
7244 absorbed some text. We will only fail again, with the
7245 'garbage following instruction' error message, which is
7246 probably less helpful than the current one. */
7247 if (backtrack_index
== i
&& backtrack_pos
!= str
7248 && upat
[i
+1] == OP_stop
)
7251 inst
.error
= _("syntax error");
7255 /* Try again, skipping the optional argument at backtrack_pos. */
7256 str
= backtrack_pos
;
7257 inst
.error
= backtrack_error
;
7258 inst
.operands
[backtrack_index
].present
= 0;
7259 i
= backtrack_index
;
7263 /* Check that we have parsed all the arguments. */
7264 if (*str
!= '\0' && !inst
.error
)
7265 inst
.error
= _("garbage following instruction");
7267 return inst
.error
? FAIL
: SUCCESS
;
7270 #undef po_char_or_fail
7271 #undef po_reg_or_fail
7272 #undef po_reg_or_goto
7273 #undef po_imm_or_fail
7274 #undef po_scalar_or_fail
7275 #undef po_barrier_or_imm
7277 /* Shorthand macro for instruction encoding functions issuing errors. */
7278 #define constraint(expr, err) \
7289 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7290 instructions are unpredictable if these registers are used. This
7291 is the BadReg predicate in ARM's Thumb-2 documentation. */
7292 #define reject_bad_reg(reg) \
7294 if (reg == REG_SP || reg == REG_PC) \
7296 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7301 /* If REG is R13 (the stack pointer), warn that its use is
7303 #define warn_deprecated_sp(reg) \
7305 if (warn_on_deprecated && reg == REG_SP) \
7306 as_tsktsk (_("use of r13 is deprecated")); \
7309 /* Functions for operand encoding. ARM, then Thumb. */
7311 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7313 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7315 The only binary encoding difference is the Coprocessor number. Coprocessor
7316 9 is used for half-precision calculations or conversions. The format of the
7317 instruction is the same as the equivalent Coprocessor 10 instruction that
7318 exists for Single-Precision operation. */
7321 do_scalar_fp16_v82_encode (void)
7323 if (inst
.cond
!= COND_ALWAYS
)
7324 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7325 " the behaviour is UNPREDICTABLE"));
7326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7329 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7330 mark_feature_used (&arm_ext_fp16
);
7333 /* If VAL can be encoded in the immediate field of an ARM instruction,
7334 return the encoded form. Otherwise, return FAIL. */
7337 encode_arm_immediate (unsigned int val
)
7344 for (i
= 2; i
< 32; i
+= 2)
7345 if ((a
= rotate_left (val
, i
)) <= 0xff)
7346 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7351 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7352 return the encoded form. Otherwise, return FAIL. */
7354 encode_thumb32_immediate (unsigned int val
)
7361 for (i
= 1; i
<= 24; i
++)
7364 if ((val
& ~(0xff << i
)) == 0)
7365 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7369 if (val
== ((a
<< 16) | a
))
7371 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7375 if (val
== ((a
<< 16) | a
))
7376 return 0x200 | (a
>> 8);
7380 /* Encode a VFP SP or DP register number into inst.instruction. */
7383 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7385 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7391 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7394 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7399 first_error (_("D register out of range for selected VFP version"));
7407 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7411 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7415 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7419 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7423 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7427 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7435 /* Encode a <shift> in an ARM-format instruction. The immediate,
7436 if any, is handled by md_apply_fix. */
7438 encode_arm_shift (int i
)
7440 /* register-shifted register. */
7441 if (inst
.operands
[i
].immisreg
)
7444 for (op_index
= 0; op_index
<= i
; ++op_index
)
7446 /* Check the operand only when it's presented. In pre-UAL syntax,
7447 if the destination register is the same as the first operand, two
7448 register form of the instruction can be used. */
7449 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7450 && inst
.operands
[op_index
].reg
== REG_PC
)
7451 as_warn (UNPRED_REG ("r15"));
7454 if (inst
.operands
[i
].imm
== REG_PC
)
7455 as_warn (UNPRED_REG ("r15"));
7458 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7459 inst
.instruction
|= SHIFT_ROR
<< 5;
7462 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7463 if (inst
.operands
[i
].immisreg
)
7465 inst
.instruction
|= SHIFT_BY_REG
;
7466 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7469 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7474 encode_arm_shifter_operand (int i
)
7476 if (inst
.operands
[i
].isreg
)
7478 inst
.instruction
|= inst
.operands
[i
].reg
;
7479 encode_arm_shift (i
);
7483 inst
.instruction
|= INST_IMMEDIATE
;
7484 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7485 inst
.instruction
|= inst
.operands
[i
].imm
;
7489 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7491 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7494 Generate an error if the operand is not a register. */
7495 constraint (!inst
.operands
[i
].isreg
,
7496 _("Instruction does not support =N addresses"));
7498 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7500 if (inst
.operands
[i
].preind
)
7504 inst
.error
= _("instruction does not accept preindexed addressing");
7507 inst
.instruction
|= PRE_INDEX
;
7508 if (inst
.operands
[i
].writeback
)
7509 inst
.instruction
|= WRITE_BACK
;
7512 else if (inst
.operands
[i
].postind
)
7514 gas_assert (inst
.operands
[i
].writeback
);
7516 inst
.instruction
|= WRITE_BACK
;
7518 else /* unindexed - only for coprocessor */
7520 inst
.error
= _("instruction does not accept unindexed addressing");
7524 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7525 && (((inst
.instruction
& 0x000f0000) >> 16)
7526 == ((inst
.instruction
& 0x0000f000) >> 12)))
7527 as_warn ((inst
.instruction
& LOAD_BIT
)
7528 ? _("destination register same as write-back base")
7529 : _("source register same as write-back base"));
7532 /* inst.operands[i] was set up by parse_address. Encode it into an
7533 ARM-format mode 2 load or store instruction. If is_t is true,
7534 reject forms that cannot be used with a T instruction (i.e. not
7537 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7539 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7541 encode_arm_addr_mode_common (i
, is_t
);
7543 if (inst
.operands
[i
].immisreg
)
7545 constraint ((inst
.operands
[i
].imm
== REG_PC
7546 || (is_pc
&& inst
.operands
[i
].writeback
)),
7548 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7549 inst
.instruction
|= inst
.operands
[i
].imm
;
7550 if (!inst
.operands
[i
].negative
)
7551 inst
.instruction
|= INDEX_UP
;
7552 if (inst
.operands
[i
].shifted
)
7554 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7555 inst
.instruction
|= SHIFT_ROR
<< 5;
7558 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7559 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7563 else /* immediate offset in inst.reloc */
7565 if (is_pc
&& !inst
.reloc
.pc_rel
)
7567 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7569 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7570 cannot use PC in addressing.
7571 PC cannot be used in writeback addressing, either. */
7572 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7575 /* Use of PC in str is deprecated for ARMv7. */
7576 if (warn_on_deprecated
7578 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7579 as_tsktsk (_("use of PC in this instruction is deprecated"));
7582 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7584 /* Prefer + for zero encoded value. */
7585 if (!inst
.operands
[i
].negative
)
7586 inst
.instruction
|= INDEX_UP
;
7587 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7592 /* inst.operands[i] was set up by parse_address. Encode it into an
7593 ARM-format mode 3 load or store instruction. Reject forms that
7594 cannot be used with such instructions. If is_t is true, reject
7595 forms that cannot be used with a T instruction (i.e. not
7598 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7600 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7602 inst
.error
= _("instruction does not accept scaled register index");
7606 encode_arm_addr_mode_common (i
, is_t
);
7608 if (inst
.operands
[i
].immisreg
)
7610 constraint ((inst
.operands
[i
].imm
== REG_PC
7611 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7613 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7615 inst
.instruction
|= inst
.operands
[i
].imm
;
7616 if (!inst
.operands
[i
].negative
)
7617 inst
.instruction
|= INDEX_UP
;
7619 else /* immediate offset in inst.reloc */
7621 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7622 && inst
.operands
[i
].writeback
),
7624 inst
.instruction
|= HWOFFSET_IMM
;
7625 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7627 /* Prefer + for zero encoded value. */
7628 if (!inst
.operands
[i
].negative
)
7629 inst
.instruction
|= INDEX_UP
;
7631 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7636 /* Write immediate bits [7:0] to the following locations:
7638 |28/24|23 19|18 16|15 4|3 0|
7639 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7641 This function is used by VMOV/VMVN/VORR/VBIC. */
7644 neon_write_immbits (unsigned immbits
)
7646 inst
.instruction
|= immbits
& 0xf;
7647 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7648 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7651 /* Invert low-order SIZE bits of XHI:XLO. */
7654 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7656 unsigned immlo
= xlo
? *xlo
: 0;
7657 unsigned immhi
= xhi
? *xhi
: 0;
7662 immlo
= (~immlo
) & 0xff;
7666 immlo
= (~immlo
) & 0xffff;
7670 immhi
= (~immhi
) & 0xffffffff;
7674 immlo
= (~immlo
) & 0xffffffff;
7688 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7692 neon_bits_same_in_bytes (unsigned imm
)
7694 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7695 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7696 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7697 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7700 /* For immediate of above form, return 0bABCD. */
7703 neon_squash_bits (unsigned imm
)
7705 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7706 | ((imm
& 0x01000000) >> 21);
7709 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7712 neon_qfloat_bits (unsigned imm
)
7714 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7717 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7718 the instruction. *OP is passed as the initial value of the op field, and
7719 may be set to a different value depending on the constant (i.e.
7720 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7721 MVN). If the immediate looks like a repeated pattern then also
7722 try smaller element sizes. */
7725 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7726 unsigned *immbits
, int *op
, int size
,
7727 enum neon_el_type type
)
7729 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7731 if (type
== NT_float
&& !float_p
)
7734 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7736 if (size
!= 32 || *op
== 1)
7738 *immbits
= neon_qfloat_bits (immlo
);
7744 if (neon_bits_same_in_bytes (immhi
)
7745 && neon_bits_same_in_bytes (immlo
))
7749 *immbits
= (neon_squash_bits (immhi
) << 4)
7750 | neon_squash_bits (immlo
);
7761 if (immlo
== (immlo
& 0x000000ff))
7766 else if (immlo
== (immlo
& 0x0000ff00))
7768 *immbits
= immlo
>> 8;
7771 else if (immlo
== (immlo
& 0x00ff0000))
7773 *immbits
= immlo
>> 16;
7776 else if (immlo
== (immlo
& 0xff000000))
7778 *immbits
= immlo
>> 24;
7781 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7783 *immbits
= (immlo
>> 8) & 0xff;
7786 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7788 *immbits
= (immlo
>> 16) & 0xff;
7792 if ((immlo
& 0xffff) != (immlo
>> 16))
7799 if (immlo
== (immlo
& 0x000000ff))
7804 else if (immlo
== (immlo
& 0x0000ff00))
7806 *immbits
= immlo
>> 8;
7810 if ((immlo
& 0xff) != (immlo
>> 8))
7815 if (immlo
== (immlo
& 0x000000ff))
7817 /* Don't allow MVN with 8-bit immediate. */
7827 #if defined BFD_HOST_64_BIT
7828 /* Returns TRUE if double precision value V may be cast
7829 to single precision without loss of accuracy. */
7832 is_double_a_single (bfd_int64_t v
)
7834 int exp
= (int)((v
>> 52) & 0x7FF);
7835 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7837 return (exp
== 0 || exp
== 0x7FF
7838 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7839 && (mantissa
& 0x1FFFFFFFl
) == 0;
7842 /* Returns a double precision value casted to single precision
7843 (ignoring the least significant bits in exponent and mantissa). */
7846 double_to_single (bfd_int64_t v
)
7848 int sign
= (int) ((v
>> 63) & 1l);
7849 int exp
= (int) ((v
>> 52) & 0x7FF);
7850 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7856 exp
= exp
- 1023 + 127;
7865 /* No denormalized numbers. */
7871 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7873 #endif /* BFD_HOST_64_BIT */
7882 static void do_vfp_nsyn_opcode (const char *);
7884 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7885 Determine whether it can be performed with a move instruction; if
7886 it can, convert inst.instruction to that move instruction and
7887 return TRUE; if it can't, convert inst.instruction to a literal-pool
7888 load and return FALSE. If this is not a valid thing to do in the
7889 current context, set inst.error and return TRUE.
7891 inst.operands[i] describes the destination register. */
7894 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7897 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7898 bfd_boolean arm_p
= (t
== CONST_ARM
);
7901 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7905 if ((inst
.instruction
& tbit
) == 0)
7907 inst
.error
= _("invalid pseudo operation");
7911 if (inst
.reloc
.exp
.X_op
!= O_constant
7912 && inst
.reloc
.exp
.X_op
!= O_symbol
7913 && inst
.reloc
.exp
.X_op
!= O_big
)
7915 inst
.error
= _("constant expression expected");
7919 if (inst
.reloc
.exp
.X_op
== O_constant
7920 || inst
.reloc
.exp
.X_op
== O_big
)
7922 #if defined BFD_HOST_64_BIT
7927 if (inst
.reloc
.exp
.X_op
== O_big
)
7929 LITTLENUM_TYPE w
[X_PRECISION
];
7932 if (inst
.reloc
.exp
.X_add_number
== -1)
7934 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7936 /* FIXME: Should we check words w[2..5] ? */
7941 #if defined BFD_HOST_64_BIT
7943 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7944 << LITTLENUM_NUMBER_OF_BITS
)
7945 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7946 << LITTLENUM_NUMBER_OF_BITS
)
7947 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7948 << LITTLENUM_NUMBER_OF_BITS
)
7949 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7951 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7952 | (l
[0] & LITTLENUM_MASK
);
7956 v
= inst
.reloc
.exp
.X_add_number
;
7958 if (!inst
.operands
[i
].issingle
)
7962 /* LDR should not use lead in a flag-setting instruction being
7963 chosen so we do not check whether movs can be used. */
7965 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7966 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7967 && inst
.operands
[i
].reg
!= 13
7968 && inst
.operands
[i
].reg
!= 15)
7970 /* Check if on thumb2 it can be done with a mov.w, mvn or
7971 movw instruction. */
7972 unsigned int newimm
;
7973 bfd_boolean isNegated
;
7975 newimm
= encode_thumb32_immediate (v
);
7976 if (newimm
!= (unsigned int) FAIL
)
7980 newimm
= encode_thumb32_immediate (~v
);
7981 if (newimm
!= (unsigned int) FAIL
)
7985 /* The number can be loaded with a mov.w or mvn
7987 if (newimm
!= (unsigned int) FAIL
7988 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7990 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7991 | (inst
.operands
[i
].reg
<< 8));
7992 /* Change to MOVN. */
7993 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7994 inst
.instruction
|= (newimm
& 0x800) << 15;
7995 inst
.instruction
|= (newimm
& 0x700) << 4;
7996 inst
.instruction
|= (newimm
& 0x0ff);
7999 /* The number can be loaded with a movw instruction. */
8000 else if ((v
& ~0xFFFF) == 0
8001 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8003 int imm
= v
& 0xFFFF;
8005 inst
.instruction
= 0xf2400000; /* MOVW. */
8006 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8007 inst
.instruction
|= (imm
& 0xf000) << 4;
8008 inst
.instruction
|= (imm
& 0x0800) << 15;
8009 inst
.instruction
|= (imm
& 0x0700) << 4;
8010 inst
.instruction
|= (imm
& 0x00ff);
8017 int value
= encode_arm_immediate (v
);
8021 /* This can be done with a mov instruction. */
8022 inst
.instruction
&= LITERAL_MASK
;
8023 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8024 inst
.instruction
|= value
& 0xfff;
8028 value
= encode_arm_immediate (~ v
);
8031 /* This can be done with a mvn instruction. */
8032 inst
.instruction
&= LITERAL_MASK
;
8033 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8034 inst
.instruction
|= value
& 0xfff;
8038 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8041 unsigned immbits
= 0;
8042 unsigned immlo
= inst
.operands
[1].imm
;
8043 unsigned immhi
= inst
.operands
[1].regisimm
8044 ? inst
.operands
[1].reg
8045 : inst
.reloc
.exp
.X_unsigned
8047 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8048 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8049 &op
, 64, NT_invtype
);
8053 neon_invert_size (&immlo
, &immhi
, 64);
8055 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8056 &op
, 64, NT_invtype
);
8061 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8067 /* Fill other bits in vmov encoding for both thumb and arm. */
8069 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8071 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8072 neon_write_immbits (immbits
);
8080 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8081 if (inst
.operands
[i
].issingle
8082 && is_quarter_float (inst
.operands
[1].imm
)
8083 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8085 inst
.operands
[1].imm
=
8086 neon_qfloat_bits (v
);
8087 do_vfp_nsyn_opcode ("fconsts");
8091 /* If our host does not support a 64-bit type then we cannot perform
8092 the following optimization. This mean that there will be a
8093 discrepancy between the output produced by an assembler built for
8094 a 32-bit-only host and the output produced from a 64-bit host, but
8095 this cannot be helped. */
8096 #if defined BFD_HOST_64_BIT
8097 else if (!inst
.operands
[1].issingle
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8100 if (is_double_a_single (v
)
8101 && is_quarter_float (double_to_single (v
)))
8103 inst
.operands
[1].imm
=
8104 neon_qfloat_bits (double_to_single (v
));
8105 do_vfp_nsyn_opcode ("fconstd");
8113 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8114 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8117 inst
.operands
[1].reg
= REG_PC
;
8118 inst
.operands
[1].isreg
= 1;
8119 inst
.operands
[1].preind
= 1;
8120 inst
.reloc
.pc_rel
= 1;
8121 inst
.reloc
.type
= (thumb_p
8122 ? BFD_RELOC_ARM_THUMB_OFFSET
8124 ? BFD_RELOC_ARM_HWLITERAL
8125 : BFD_RELOC_ARM_LITERAL
));
8129 /* inst.operands[i] was set up by parse_address. Encode it into an
8130 ARM-format instruction. Reject all forms which cannot be encoded
8131 into a coprocessor load/store instruction. If wb_ok is false,
8132 reject use of writeback; if unind_ok is false, reject use of
8133 unindexed addressing. If reloc_override is not 0, use it instead
8134 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8135 (in which case it is preserved). */
8138 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8140 if (!inst
.operands
[i
].isreg
)
8143 if (! inst
.operands
[0].isvec
)
8145 inst
.error
= _("invalid co-processor operand");
8148 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8152 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8154 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8156 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8158 gas_assert (!inst
.operands
[i
].writeback
);
8161 inst
.error
= _("instruction does not support unindexed addressing");
8164 inst
.instruction
|= inst
.operands
[i
].imm
;
8165 inst
.instruction
|= INDEX_UP
;
8169 if (inst
.operands
[i
].preind
)
8170 inst
.instruction
|= PRE_INDEX
;
8172 if (inst
.operands
[i
].writeback
)
8174 if (inst
.operands
[i
].reg
== REG_PC
)
8176 inst
.error
= _("pc may not be used with write-back");
8181 inst
.error
= _("instruction does not support writeback");
8184 inst
.instruction
|= WRITE_BACK
;
8188 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8189 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8190 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8191 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8194 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8196 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8199 /* Prefer + for zero encoded value. */
8200 if (!inst
.operands
[i
].negative
)
8201 inst
.instruction
|= INDEX_UP
;
8206 /* Functions for instruction encoding, sorted by sub-architecture.
8207 First some generics; their names are taken from the conventional
8208 bit positions for register arguments in ARM format instructions. */
8218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8224 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8231 inst
.instruction
|= inst
.operands
[1].reg
;
8237 inst
.instruction
|= inst
.operands
[0].reg
;
8238 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8251 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8252 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8258 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8263 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8265 if (ARM_CPU_IS_ANY (cpu_variant
))
8267 as_tsktsk ("%s", msg
);
8270 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8282 unsigned Rn
= inst
.operands
[2].reg
;
8283 /* Enforce restrictions on SWP instruction. */
8284 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8286 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8287 _("Rn must not overlap other operands"));
8289 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8291 if (!check_obsolete (&arm_ext_v8
,
8292 _("swp{b} use is obsoleted for ARMv8 and later"))
8293 && warn_on_deprecated
8294 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8295 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8298 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8299 inst
.instruction
|= inst
.operands
[1].reg
;
8300 inst
.instruction
|= Rn
<< 16;
8306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8308 inst
.instruction
|= inst
.operands
[2].reg
;
8314 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8315 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8316 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8317 || inst
.reloc
.exp
.X_add_number
!= 0),
8319 inst
.instruction
|= inst
.operands
[0].reg
;
8320 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8327 inst
.instruction
|= inst
.operands
[0].imm
;
8333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8334 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8337 /* ARM instructions, in alphabetical order by function name (except
8338 that wrapper functions appear immediately after the function they
8341 /* This is a pseudo-op of the form "adr rd, label" to be converted
8342 into a relative address of the form "add rd, pc, #label-.-8". */
8347 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8349 /* Frag hacking will turn this into a sub instruction if the offset turns
8350 out to be negative. */
8351 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8352 inst
.reloc
.pc_rel
= 1;
8353 inst
.reloc
.exp
.X_add_number
-= 8;
8355 if (inst
.reloc
.exp
.X_op
== O_symbol
8356 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8357 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8358 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8359 inst
.reloc
.exp
.X_add_number
+= 1;
8362 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8363 into a relative address of the form:
8364 add rd, pc, #low(label-.-8)"
8365 add rd, rd, #high(label-.-8)" */
8370 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8372 /* Frag hacking will turn this into a sub instruction if the offset turns
8373 out to be negative. */
8374 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8375 inst
.reloc
.pc_rel
= 1;
8376 inst
.size
= INSN_SIZE
* 2;
8377 inst
.reloc
.exp
.X_add_number
-= 8;
8379 if (inst
.reloc
.exp
.X_op
== O_symbol
8380 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8381 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8382 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8383 inst
.reloc
.exp
.X_add_number
+= 1;
8389 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8390 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8392 if (!inst
.operands
[1].present
)
8393 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8395 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8396 encode_arm_shifter_operand (2);
8402 if (inst
.operands
[0].present
)
8403 inst
.instruction
|= inst
.operands
[0].imm
;
8405 inst
.instruction
|= 0xf;
8411 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8412 constraint (msb
> 32, _("bit-field extends past end of register"));
8413 /* The instruction encoding stores the LSB and MSB,
8414 not the LSB and width. */
8415 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8416 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8417 inst
.instruction
|= (msb
- 1) << 16;
8425 /* #0 in second position is alternative syntax for bfc, which is
8426 the same instruction but with REG_PC in the Rm field. */
8427 if (!inst
.operands
[1].isreg
)
8428 inst
.operands
[1].reg
= REG_PC
;
8430 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8431 constraint (msb
> 32, _("bit-field extends past end of register"));
8432 /* The instruction encoding stores the LSB and MSB,
8433 not the LSB and width. */
8434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8435 inst
.instruction
|= inst
.operands
[1].reg
;
8436 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8437 inst
.instruction
|= (msb
- 1) << 16;
8443 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8444 _("bit-field extends past end of register"));
8445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8446 inst
.instruction
|= inst
.operands
[1].reg
;
8447 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8448 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8451 /* ARM V5 breakpoint instruction (argument parse)
8452 BKPT <16 bit unsigned immediate>
8453 Instruction is not conditional.
8454 The bit pattern given in insns[] has the COND_ALWAYS condition,
8455 and it is an error if the caller tried to override that. */
8460 /* Top 12 of 16 bits to bits 19:8. */
8461 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8463 /* Bottom 4 of 16 bits to bits 3:0. */
8464 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8468 encode_branch (int default_reloc
)
8470 if (inst
.operands
[0].hasreloc
)
8472 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8473 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8474 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8475 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8476 ? BFD_RELOC_ARM_PLT32
8477 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8480 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8481 inst
.reloc
.pc_rel
= 1;
8488 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8489 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8492 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8499 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8501 if (inst
.cond
== COND_ALWAYS
)
8502 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8504 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8508 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8511 /* ARM V5 branch-link-exchange instruction (argument parse)
8512 BLX <target_addr> ie BLX(1)
8513 BLX{<condition>} <Rm> ie BLX(2)
8514 Unfortunately, there are two different opcodes for this mnemonic.
8515 So, the insns[].value is not used, and the code here zaps values
8516 into inst.instruction.
8517 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8522 if (inst
.operands
[0].isreg
)
8524 /* Arg is a register; the opcode provided by insns[] is correct.
8525 It is not illegal to do "blx pc", just useless. */
8526 if (inst
.operands
[0].reg
== REG_PC
)
8527 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8529 inst
.instruction
|= inst
.operands
[0].reg
;
8533 /* Arg is an address; this instruction cannot be executed
8534 conditionally, and the opcode must be adjusted.
8535 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8536 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8537 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8538 inst
.instruction
= 0xfa000000;
8539 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8546 bfd_boolean want_reloc
;
8548 if (inst
.operands
[0].reg
== REG_PC
)
8549 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8551 inst
.instruction
|= inst
.operands
[0].reg
;
8552 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8553 it is for ARMv4t or earlier. */
8554 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8555 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8559 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8564 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8568 /* ARM v5TEJ. Jump to Jazelle code. */
8573 if (inst
.operands
[0].reg
== REG_PC
)
8574 as_tsktsk (_("use of r15 in bxj is not really useful"));
8576 inst
.instruction
|= inst
.operands
[0].reg
;
8579 /* Co-processor data operation:
8580 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8581 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8585 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8586 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8587 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8588 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8589 inst
.instruction
|= inst
.operands
[4].reg
;
8590 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8596 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8597 encode_arm_shifter_operand (1);
8600 /* Transfer between coprocessor and ARM registers.
8601 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8606 No special properties. */
8608 struct deprecated_coproc_regs_s
8615 arm_feature_set deprecated
;
8616 arm_feature_set obsoleted
;
8617 const char *dep_msg
;
8618 const char *obs_msg
;
8621 #define DEPR_ACCESS_V8 \
8622 N_("This coprocessor register access is deprecated in ARMv8")
8624 /* Table of all deprecated coprocessor registers. */
8625 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8627 {15, 0, 7, 10, 5, /* CP15DMB. */
8628 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8629 DEPR_ACCESS_V8
, NULL
},
8630 {15, 0, 7, 10, 4, /* CP15DSB. */
8631 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8632 DEPR_ACCESS_V8
, NULL
},
8633 {15, 0, 7, 5, 4, /* CP15ISB. */
8634 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8635 DEPR_ACCESS_V8
, NULL
},
8636 {14, 6, 1, 0, 0, /* TEEHBR. */
8637 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8638 DEPR_ACCESS_V8
, NULL
},
8639 {14, 6, 0, 0, 0, /* TEECR. */
8640 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8641 DEPR_ACCESS_V8
, NULL
},
8644 #undef DEPR_ACCESS_V8
8646 static const size_t deprecated_coproc_reg_count
=
8647 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8655 Rd
= inst
.operands
[2].reg
;
8658 if (inst
.instruction
== 0xee000010
8659 || inst
.instruction
== 0xfe000010)
8661 reject_bad_reg (Rd
);
8664 constraint (Rd
== REG_SP
, BAD_SP
);
8669 if (inst
.instruction
== 0xe000010)
8670 constraint (Rd
== REG_PC
, BAD_PC
);
8673 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8675 const struct deprecated_coproc_regs_s
*r
=
8676 deprecated_coproc_regs
+ i
;
8678 if (inst
.operands
[0].reg
== r
->cp
8679 && inst
.operands
[1].imm
== r
->opc1
8680 && inst
.operands
[3].reg
== r
->crn
8681 && inst
.operands
[4].reg
== r
->crm
8682 && inst
.operands
[5].imm
== r
->opc2
)
8684 if (! ARM_CPU_IS_ANY (cpu_variant
)
8685 && warn_on_deprecated
8686 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8687 as_tsktsk ("%s", r
->dep_msg
);
8691 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8692 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8693 inst
.instruction
|= Rd
<< 12;
8694 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8695 inst
.instruction
|= inst
.operands
[4].reg
;
8696 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8699 /* Transfer between coprocessor register and pair of ARM registers.
8700 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8705 Two XScale instructions are special cases of these:
8707 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8708 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8710 Result unpredictable if Rd or Rn is R15. */
8717 Rd
= inst
.operands
[2].reg
;
8718 Rn
= inst
.operands
[3].reg
;
8722 reject_bad_reg (Rd
);
8723 reject_bad_reg (Rn
);
8727 constraint (Rd
== REG_PC
, BAD_PC
);
8728 constraint (Rn
== REG_PC
, BAD_PC
);
8731 /* Only check the MRRC{2} variants. */
8732 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8734 /* If Rd == Rn, error that the operation is
8735 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8736 constraint (Rd
== Rn
, BAD_OVERLAP
);
8739 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8740 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8741 inst
.instruction
|= Rd
<< 12;
8742 inst
.instruction
|= Rn
<< 16;
8743 inst
.instruction
|= inst
.operands
[4].reg
;
8749 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8750 if (inst
.operands
[1].present
)
8752 inst
.instruction
|= CPSI_MMOD
;
8753 inst
.instruction
|= inst
.operands
[1].imm
;
8760 inst
.instruction
|= inst
.operands
[0].imm
;
8766 unsigned Rd
, Rn
, Rm
;
8768 Rd
= inst
.operands
[0].reg
;
8769 Rn
= (inst
.operands
[1].present
8770 ? inst
.operands
[1].reg
: Rd
);
8771 Rm
= inst
.operands
[2].reg
;
8773 constraint ((Rd
== REG_PC
), BAD_PC
);
8774 constraint ((Rn
== REG_PC
), BAD_PC
);
8775 constraint ((Rm
== REG_PC
), BAD_PC
);
8777 inst
.instruction
|= Rd
<< 16;
8778 inst
.instruction
|= Rn
<< 0;
8779 inst
.instruction
|= Rm
<< 8;
8785 /* There is no IT instruction in ARM mode. We
8786 process it to do the validation as if in
8787 thumb mode, just in case the code gets
8788 assembled for thumb using the unified syntax. */
8793 set_it_insn_type (IT_INSN
);
8794 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8795 now_it
.cc
= inst
.operands
[0].imm
;
8799 /* If there is only one register in the register list,
8800 then return its register number. Otherwise return -1. */
8802 only_one_reg_in_list (int range
)
8804 int i
= ffs (range
) - 1;
8805 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8809 encode_ldmstm(int from_push_pop_mnem
)
8811 int base_reg
= inst
.operands
[0].reg
;
8812 int range
= inst
.operands
[1].imm
;
8815 inst
.instruction
|= base_reg
<< 16;
8816 inst
.instruction
|= range
;
8818 if (inst
.operands
[1].writeback
)
8819 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8821 if (inst
.operands
[0].writeback
)
8823 inst
.instruction
|= WRITE_BACK
;
8824 /* Check for unpredictable uses of writeback. */
8825 if (inst
.instruction
& LOAD_BIT
)
8827 /* Not allowed in LDM type 2. */
8828 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8829 && ((range
& (1 << REG_PC
)) == 0))
8830 as_warn (_("writeback of base register is UNPREDICTABLE"));
8831 /* Only allowed if base reg not in list for other types. */
8832 else if (range
& (1 << base_reg
))
8833 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8837 /* Not allowed for type 2. */
8838 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8839 as_warn (_("writeback of base register is UNPREDICTABLE"));
8840 /* Only allowed if base reg not in list, or first in list. */
8841 else if ((range
& (1 << base_reg
))
8842 && (range
& ((1 << base_reg
) - 1)))
8843 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8847 /* If PUSH/POP has only one register, then use the A2 encoding. */
8848 one_reg
= only_one_reg_in_list (range
);
8849 if (from_push_pop_mnem
&& one_reg
>= 0)
8851 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8853 inst
.instruction
&= A_COND_MASK
;
8854 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8855 inst
.instruction
|= one_reg
<< 12;
8862 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8865 /* ARMv5TE load-consecutive (argument parse)
8874 constraint (inst
.operands
[0].reg
% 2 != 0,
8875 _("first transfer register must be even"));
8876 constraint (inst
.operands
[1].present
8877 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8878 _("can only transfer two consecutive registers"));
8879 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8880 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8882 if (!inst
.operands
[1].present
)
8883 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8885 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8886 register and the first register written; we have to diagnose
8887 overlap between the base and the second register written here. */
8889 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8890 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8891 as_warn (_("base register written back, and overlaps "
8892 "second transfer register"));
8894 if (!(inst
.instruction
& V4_STR_BIT
))
8896 /* For an index-register load, the index register must not overlap the
8897 destination (even if not write-back). */
8898 if (inst
.operands
[2].immisreg
8899 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8900 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8901 as_warn (_("index register overlaps transfer register"));
8903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8904 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8910 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8911 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8912 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8913 || inst
.operands
[1].negative
8914 /* This can arise if the programmer has written
8916 or if they have mistakenly used a register name as the last
8919 It is very difficult to distinguish between these two cases
8920 because "rX" might actually be a label. ie the register
8921 name has been occluded by a symbol of the same name. So we
8922 just generate a general 'bad addressing mode' type error
8923 message and leave it up to the programmer to discover the
8924 true cause and fix their mistake. */
8925 || (inst
.operands
[1].reg
== REG_PC
),
8928 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8929 || inst
.reloc
.exp
.X_add_number
!= 0,
8930 _("offset must be zero in ARM encoding"));
8932 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8935 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8936 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8942 constraint (inst
.operands
[0].reg
% 2 != 0,
8943 _("even register required"));
8944 constraint (inst
.operands
[1].present
8945 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8946 _("can only load two consecutive registers"));
8947 /* If op 1 were present and equal to PC, this function wouldn't
8948 have been called in the first place. */
8949 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8952 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8955 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8956 which is not a multiple of four is UNPREDICTABLE. */
8958 check_ldr_r15_aligned (void)
8960 constraint (!(inst
.operands
[1].immisreg
)
8961 && (inst
.operands
[0].reg
== REG_PC
8962 && inst
.operands
[1].reg
== REG_PC
8963 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8964 _("ldr to register 15 must be 4-byte alligned"));
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8971 if (!inst
.operands
[1].isreg
)
8972 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8974 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8975 check_ldr_r15_aligned ();
8981 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8983 if (inst
.operands
[1].preind
)
8985 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8986 || inst
.reloc
.exp
.X_add_number
!= 0,
8987 _("this instruction requires a post-indexed address"));
8989 inst
.operands
[1].preind
= 0;
8990 inst
.operands
[1].postind
= 1;
8991 inst
.operands
[1].writeback
= 1;
8993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8994 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8997 /* Halfword and signed-byte load/store operations. */
9002 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9004 if (!inst
.operands
[1].isreg
)
9005 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9007 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9013 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9015 if (inst
.operands
[1].preind
)
9017 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9018 || inst
.reloc
.exp
.X_add_number
!= 0,
9019 _("this instruction requires a post-indexed address"));
9021 inst
.operands
[1].preind
= 0;
9022 inst
.operands
[1].postind
= 1;
9023 inst
.operands
[1].writeback
= 1;
9025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9026 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9029 /* Co-processor register load/store.
9030 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9034 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9035 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9036 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9042 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9043 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9044 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9045 && !(inst
.instruction
& 0x00400000))
9046 as_tsktsk (_("Rd and Rm should be different in mla"));
9048 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9049 inst
.instruction
|= inst
.operands
[1].reg
;
9050 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9051 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9057 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9058 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9061 encode_arm_shifter_operand (1);
9064 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9071 top
= (inst
.instruction
& 0x00400000) != 0;
9072 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9073 _(":lower16: not allowed in this instruction"));
9074 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9075 _(":upper16: not allowed in this instruction"));
9076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9077 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9079 imm
= inst
.reloc
.exp
.X_add_number
;
9080 /* The value is in two pieces: 0:11, 16:19. */
9081 inst
.instruction
|= (imm
& 0x00000fff);
9082 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9087 do_vfp_nsyn_mrs (void)
9089 if (inst
.operands
[0].isvec
)
9091 if (inst
.operands
[1].reg
!= 1)
9092 first_error (_("operand 1 must be FPSCR"));
9093 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9094 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9095 do_vfp_nsyn_opcode ("fmstat");
9097 else if (inst
.operands
[1].isvec
)
9098 do_vfp_nsyn_opcode ("fmrx");
9106 do_vfp_nsyn_msr (void)
9108 if (inst
.operands
[0].isvec
)
9109 do_vfp_nsyn_opcode ("fmxr");
9119 unsigned Rt
= inst
.operands
[0].reg
;
9121 if (thumb_mode
&& Rt
== REG_SP
)
9123 inst
.error
= BAD_SP
;
9127 /* APSR_ sets isvec. All other refs to PC are illegal. */
9128 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9130 inst
.error
= BAD_PC
;
9134 /* If we get through parsing the register name, we just insert the number
9135 generated into the instruction without further validation. */
9136 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9137 inst
.instruction
|= (Rt
<< 12);
9143 unsigned Rt
= inst
.operands
[1].reg
;
9146 reject_bad_reg (Rt
);
9147 else if (Rt
== REG_PC
)
9149 inst
.error
= BAD_PC
;
9153 /* If we get through parsing the register name, we just insert the number
9154 generated into the instruction without further validation. */
9155 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9156 inst
.instruction
|= (Rt
<< 12);
9164 if (do_vfp_nsyn_mrs () == SUCCESS
)
9167 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9168 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9170 if (inst
.operands
[1].isreg
)
9172 br
= inst
.operands
[1].reg
;
9173 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9174 as_bad (_("bad register for mrs"));
9178 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9179 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9181 _("'APSR', 'CPSR' or 'SPSR' expected"));
9182 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9185 inst
.instruction
|= br
;
9188 /* Two possible forms:
9189 "{C|S}PSR_<field>, Rm",
9190 "{C|S}PSR_f, #expression". */
9195 if (do_vfp_nsyn_msr () == SUCCESS
)
9198 inst
.instruction
|= inst
.operands
[0].imm
;
9199 if (inst
.operands
[1].isreg
)
9200 inst
.instruction
|= inst
.operands
[1].reg
;
9203 inst
.instruction
|= INST_IMMEDIATE
;
9204 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9205 inst
.reloc
.pc_rel
= 0;
9212 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9214 if (!inst
.operands
[2].present
)
9215 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9216 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9217 inst
.instruction
|= inst
.operands
[1].reg
;
9218 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9220 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9221 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9222 as_tsktsk (_("Rd and Rm should be different in mul"));
9225 /* Long Multiply Parser
9226 UMULL RdLo, RdHi, Rm, Rs
9227 SMULL RdLo, RdHi, Rm, Rs
9228 UMLAL RdLo, RdHi, Rm, Rs
9229 SMLAL RdLo, RdHi, Rm, Rs. */
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9236 inst
.instruction
|= inst
.operands
[2].reg
;
9237 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9239 /* rdhi and rdlo must be different. */
9240 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9241 as_tsktsk (_("rdhi and rdlo must be different"));
9243 /* rdhi, rdlo and rm must all be different before armv6. */
9244 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9245 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9246 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9247 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9253 if (inst
.operands
[0].present
9254 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9256 /* Architectural NOP hints are CPSR sets with no bits selected. */
9257 inst
.instruction
&= 0xf0000000;
9258 inst
.instruction
|= 0x0320f000;
9259 if (inst
.operands
[0].present
)
9260 inst
.instruction
|= inst
.operands
[0].imm
;
9264 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9265 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9266 Condition defaults to COND_ALWAYS.
9267 Error if Rd, Rn or Rm are R15. */
9272 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9273 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9274 inst
.instruction
|= inst
.operands
[2].reg
;
9275 if (inst
.operands
[3].present
)
9276 encode_arm_shift (3);
9279 /* ARM V6 PKHTB (Argument Parse). */
9284 if (!inst
.operands
[3].present
)
9286 /* If the shift specifier is omitted, turn the instruction
9287 into pkhbt rd, rm, rn. */
9288 inst
.instruction
&= 0xfff00010;
9289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9290 inst
.instruction
|= inst
.operands
[1].reg
;
9291 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9297 inst
.instruction
|= inst
.operands
[2].reg
;
9298 encode_arm_shift (3);
9302 /* ARMv5TE: Preload-Cache
9303 MP Extensions: Preload for write
9307 Syntactically, like LDR with B=1, W=0, L=1. */
9312 constraint (!inst
.operands
[0].isreg
,
9313 _("'[' expected after PLD mnemonic"));
9314 constraint (inst
.operands
[0].postind
,
9315 _("post-indexed expression used in preload instruction"));
9316 constraint (inst
.operands
[0].writeback
,
9317 _("writeback used in preload instruction"));
9318 constraint (!inst
.operands
[0].preind
,
9319 _("unindexed addressing used in preload instruction"));
9320 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9323 /* ARMv7: PLI <addr_mode> */
9327 constraint (!inst
.operands
[0].isreg
,
9328 _("'[' expected after PLI mnemonic"));
9329 constraint (inst
.operands
[0].postind
,
9330 _("post-indexed expression used in preload instruction"));
9331 constraint (inst
.operands
[0].writeback
,
9332 _("writeback used in preload instruction"));
9333 constraint (!inst
.operands
[0].preind
,
9334 _("unindexed addressing used in preload instruction"));
9335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9336 inst
.instruction
&= ~PRE_INDEX
;
9342 constraint (inst
.operands
[0].writeback
,
9343 _("push/pop do not support {reglist}^"));
9344 inst
.operands
[1] = inst
.operands
[0];
9345 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9346 inst
.operands
[0].isreg
= 1;
9347 inst
.operands
[0].writeback
= 1;
9348 inst
.operands
[0].reg
= REG_SP
;
9349 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9352 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9353 word at the specified address and the following word
9355 Unconditionally executed.
9356 Error if Rn is R15. */
9361 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9362 if (inst
.operands
[0].writeback
)
9363 inst
.instruction
|= WRITE_BACK
;
9366 /* ARM V6 ssat (argument parse). */
9371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9372 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9373 inst
.instruction
|= inst
.operands
[2].reg
;
9375 if (inst
.operands
[3].present
)
9376 encode_arm_shift (3);
9379 /* ARM V6 usat (argument parse). */
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9385 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9386 inst
.instruction
|= inst
.operands
[2].reg
;
9388 if (inst
.operands
[3].present
)
9389 encode_arm_shift (3);
9392 /* ARM V6 ssat16 (argument parse). */
9397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9398 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9399 inst
.instruction
|= inst
.operands
[2].reg
;
9405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9406 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9407 inst
.instruction
|= inst
.operands
[2].reg
;
9410 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9411 preserving the other bits.
9413 setend <endian_specifier>, where <endian_specifier> is either
9419 if (warn_on_deprecated
9420 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9421 as_tsktsk (_("setend use is deprecated for ARMv8"));
9423 if (inst
.operands
[0].imm
)
9424 inst
.instruction
|= 0x200;
9430 unsigned int Rm
= (inst
.operands
[1].present
9431 ? inst
.operands
[1].reg
9432 : inst
.operands
[0].reg
);
9434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9435 inst
.instruction
|= Rm
;
9436 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9438 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9439 inst
.instruction
|= SHIFT_BY_REG
;
9440 /* PR 12854: Error on extraneous shifts. */
9441 constraint (inst
.operands
[2].shifted
,
9442 _("extraneous shift as part of operand to shift insn"));
9445 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9451 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9452 inst
.reloc
.pc_rel
= 0;
9458 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9459 inst
.reloc
.pc_rel
= 0;
9465 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9466 inst
.reloc
.pc_rel
= 0;
9472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9473 _("selected processor does not support SETPAN instruction"));
9475 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9481 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9482 _("selected processor does not support SETPAN instruction"));
9484 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9487 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9488 SMLAxy{cond} Rd,Rm,Rs,Rn
9489 SMLAWy{cond} Rd,Rm,Rs,Rn
9490 Error if any register is R15. */
9495 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9496 inst
.instruction
|= inst
.operands
[1].reg
;
9497 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9498 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9501 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9502 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9503 Error if any register is R15.
9504 Warning if Rdlo == Rdhi. */
9509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9510 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9511 inst
.instruction
|= inst
.operands
[2].reg
;
9512 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9514 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9515 as_tsktsk (_("rdhi and rdlo must be different"));
9518 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9519 SMULxy{cond} Rd,Rm,Rs
9520 Error if any register is R15. */
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9526 inst
.instruction
|= inst
.operands
[1].reg
;
9527 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9530 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9531 the same for both ARM and Thumb-2. */
9538 if (inst
.operands
[0].present
)
9540 reg
= inst
.operands
[0].reg
;
9541 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9546 inst
.instruction
|= reg
<< 16;
9547 inst
.instruction
|= inst
.operands
[1].imm
;
9548 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9549 inst
.instruction
|= WRITE_BACK
;
9552 /* ARM V6 strex (argument parse). */
9557 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9558 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9559 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9560 || inst
.operands
[2].negative
9561 /* See comment in do_ldrex(). */
9562 || (inst
.operands
[2].reg
== REG_PC
),
9565 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9566 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9568 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9569 || inst
.reloc
.exp
.X_add_number
!= 0,
9570 _("offset must be zero in ARM encoding"));
9572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9573 inst
.instruction
|= inst
.operands
[1].reg
;
9574 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9575 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9581 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9582 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9583 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9584 || inst
.operands
[2].negative
,
9587 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9588 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9596 constraint (inst
.operands
[1].reg
% 2 != 0,
9597 _("even register required"));
9598 constraint (inst
.operands
[2].present
9599 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9600 _("can only store two consecutive registers"));
9601 /* If op 2 were present and equal to PC, this function wouldn't
9602 have been called in the first place. */
9603 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9605 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9606 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9607 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9611 inst
.instruction
|= inst
.operands
[1].reg
;
9612 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9619 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9620 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9628 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9629 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9634 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9635 extends it to 32-bits, and adds the result to a value in another
9636 register. You can specify a rotation by 0, 8, 16, or 24 bits
9637 before extracting the 16-bit value.
9638 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9639 Condition defaults to COND_ALWAYS.
9640 Error if any register uses R15. */
9645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9646 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9647 inst
.instruction
|= inst
.operands
[2].reg
;
9648 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9653 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9654 Condition defaults to COND_ALWAYS.
9655 Error if any register uses R15. */
9660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9661 inst
.instruction
|= inst
.operands
[1].reg
;
9662 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9665 /* VFP instructions. In a logical order: SP variant first, monad
9666 before dyad, arithmetic then move then load/store. */
9669 do_vfp_sp_monadic (void)
9671 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9672 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9676 do_vfp_sp_dyadic (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9679 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9680 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9684 do_vfp_sp_compare_z (void)
9686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9690 do_vfp_dp_sp_cvt (void)
9692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9697 do_vfp_sp_dp_cvt (void)
9699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9700 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9704 do_vfp_reg_from_sp (void)
9706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9707 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9711 do_vfp_reg2_from_sp2 (void)
9713 constraint (inst
.operands
[2].imm
!= 2,
9714 _("only two consecutive VFP SP registers allowed here"));
9715 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9716 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9717 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9721 do_vfp_sp_from_reg (void)
9723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9724 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9728 do_vfp_sp2_from_reg2 (void)
9730 constraint (inst
.operands
[0].imm
!= 2,
9731 _("only two consecutive VFP SP registers allowed here"));
9732 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9733 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9734 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9738 do_vfp_sp_ldst (void)
9740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9741 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9745 do_vfp_dp_ldst (void)
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9748 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9753 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9755 if (inst
.operands
[0].writeback
)
9756 inst
.instruction
|= WRITE_BACK
;
9758 constraint (ldstm_type
!= VFP_LDSTMIA
,
9759 _("this addressing mode requires base-register writeback"));
9760 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9761 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9762 inst
.instruction
|= inst
.operands
[1].imm
;
9766 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9770 if (inst
.operands
[0].writeback
)
9771 inst
.instruction
|= WRITE_BACK
;
9773 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9774 _("this addressing mode requires base-register writeback"));
9776 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9777 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9779 count
= inst
.operands
[1].imm
<< 1;
9780 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9783 inst
.instruction
|= count
;
9787 do_vfp_sp_ldstmia (void)
9789 vfp_sp_ldstm (VFP_LDSTMIA
);
9793 do_vfp_sp_ldstmdb (void)
9795 vfp_sp_ldstm (VFP_LDSTMDB
);
9799 do_vfp_dp_ldstmia (void)
9801 vfp_dp_ldstm (VFP_LDSTMIA
);
9805 do_vfp_dp_ldstmdb (void)
9807 vfp_dp_ldstm (VFP_LDSTMDB
);
9811 do_vfp_xp_ldstmia (void)
9813 vfp_dp_ldstm (VFP_LDSTMIAX
);
9817 do_vfp_xp_ldstmdb (void)
9819 vfp_dp_ldstm (VFP_LDSTMDBX
);
9823 do_vfp_dp_rd_rm (void)
9825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9826 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9830 do_vfp_dp_rn_rd (void)
9832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9833 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9837 do_vfp_dp_rd_rn (void)
9839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9844 do_vfp_dp_rd_rn_rm (void)
9846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9847 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9848 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9858 do_vfp_dp_rm_rd_rn (void)
9860 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9861 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9862 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9865 /* VFPv3 instructions. */
9867 do_vfp_sp_const (void)
9869 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9870 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9871 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9875 do_vfp_dp_const (void)
9877 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9878 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9879 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9883 vfp_conv (int srcsize
)
9885 int immbits
= srcsize
- inst
.operands
[1].imm
;
9887 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9889 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9890 i.e. immbits must be in range 0 - 16. */
9891 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9894 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9896 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9897 i.e. immbits must be in range 0 - 31. */
9898 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9902 inst
.instruction
|= (immbits
& 1) << 5;
9903 inst
.instruction
|= (immbits
>> 1);
9907 do_vfp_sp_conv_16 (void)
9909 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9914 do_vfp_dp_conv_16 (void)
9916 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9921 do_vfp_sp_conv_32 (void)
9923 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9928 do_vfp_dp_conv_32 (void)
9930 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9934 /* FPA instructions. Also in a logical order. */
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9940 inst
.instruction
|= inst
.operands
[1].reg
;
9944 do_fpa_ldmstm (void)
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 switch (inst
.operands
[1].imm
)
9949 case 1: inst
.instruction
|= CP_T_X
; break;
9950 case 2: inst
.instruction
|= CP_T_Y
; break;
9951 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9956 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9958 /* The instruction specified "ea" or "fd", so we can only accept
9959 [Rn]{!}. The instruction does not really support stacking or
9960 unstacking, so we have to emulate these by setting appropriate
9961 bits and offsets. */
9962 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9963 || inst
.reloc
.exp
.X_add_number
!= 0,
9964 _("this instruction does not support indexing"));
9966 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9967 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9969 if (!(inst
.instruction
& INDEX_UP
))
9970 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9972 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9974 inst
.operands
[2].preind
= 0;
9975 inst
.operands
[2].postind
= 1;
9979 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9982 /* iWMMXt instructions: strictly in alphabetical order. */
9985 do_iwmmxt_tandorc (void)
9987 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9991 do_iwmmxt_textrc (void)
9993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9994 inst
.instruction
|= inst
.operands
[1].imm
;
9998 do_iwmmxt_textrm (void)
10000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10001 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10002 inst
.instruction
|= inst
.operands
[2].imm
;
10006 do_iwmmxt_tinsr (void)
10008 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10009 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10010 inst
.instruction
|= inst
.operands
[2].imm
;
10014 do_iwmmxt_tmia (void)
10016 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10017 inst
.instruction
|= inst
.operands
[1].reg
;
10018 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10022 do_iwmmxt_waligni (void)
10024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10025 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10026 inst
.instruction
|= inst
.operands
[2].reg
;
10027 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10031 do_iwmmxt_wmerge (void)
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10035 inst
.instruction
|= inst
.operands
[2].reg
;
10036 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10040 do_iwmmxt_wmov (void)
10042 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10045 inst
.instruction
|= inst
.operands
[1].reg
;
10049 do_iwmmxt_wldstbh (void)
10052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10056 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10057 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10061 do_iwmmxt_wldstw (void)
10063 /* RIWR_RIWC clears .isreg for a control register. */
10064 if (!inst
.operands
[0].isreg
)
10066 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10067 inst
.instruction
|= 0xf0000000;
10070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10071 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10075 do_iwmmxt_wldstd (void)
10077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10078 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10079 && inst
.operands
[1].immisreg
)
10081 inst
.instruction
&= ~0x1a000ff;
10082 inst
.instruction
|= (0xfU
<< 28);
10083 if (inst
.operands
[1].preind
)
10084 inst
.instruction
|= PRE_INDEX
;
10085 if (!inst
.operands
[1].negative
)
10086 inst
.instruction
|= INDEX_UP
;
10087 if (inst
.operands
[1].writeback
)
10088 inst
.instruction
|= WRITE_BACK
;
10089 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10090 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10091 inst
.instruction
|= inst
.operands
[1].imm
;
10094 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10098 do_iwmmxt_wshufh (void)
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10102 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10103 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10107 do_iwmmxt_wzero (void)
10109 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10110 inst
.instruction
|= inst
.operands
[0].reg
;
10111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10112 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10116 do_iwmmxt_wrwrwr_or_imm5 (void)
10118 if (inst
.operands
[2].isreg
)
10121 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10122 _("immediate operand requires iWMMXt2"));
10124 if (inst
.operands
[2].imm
== 0)
10126 switch ((inst
.instruction
>> 20) & 0xf)
10132 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10133 inst
.operands
[2].imm
= 16;
10134 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10140 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10141 inst
.operands
[2].imm
= 32;
10142 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10149 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10151 wrn
= (inst
.instruction
>> 16) & 0xf;
10152 inst
.instruction
&= 0xff0fff0f;
10153 inst
.instruction
|= wrn
;
10154 /* Bail out here; the instruction is now assembled. */
10159 /* Map 32 -> 0, etc. */
10160 inst
.operands
[2].imm
&= 0x1f;
10161 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10165 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10166 operations first, then control, shift, and load/store. */
10168 /* Insns like "foo X,Y,Z". */
10171 do_mav_triple (void)
10173 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10174 inst
.instruction
|= inst
.operands
[1].reg
;
10175 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10178 /* Insns like "foo W,X,Y,Z".
10179 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10184 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10187 inst
.instruction
|= inst
.operands
[3].reg
;
10190 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10192 do_mav_dspsc (void)
10194 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10197 /* Maverick shift immediate instructions.
10198 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10199 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10202 do_mav_shift (void)
10204 int imm
= inst
.operands
[2].imm
;
10206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10209 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10210 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10211 Bit 4 should be 0. */
10212 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10214 inst
.instruction
|= imm
;
10217 /* XScale instructions. Also sorted arithmetic before move. */
10219 /* Xscale multiply-accumulate (argument parse)
10222 MIAxycc acc0,Rm,Rs. */
10227 inst
.instruction
|= inst
.operands
[1].reg
;
10228 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10231 /* Xscale move-accumulator-register (argument parse)
10233 MARcc acc0,RdLo,RdHi. */
10238 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10239 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10242 /* Xscale move-register-accumulator (argument parse)
10244 MRAcc RdLo,RdHi,acc0. */
10249 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10254 /* Encoding functions relevant only to Thumb. */
10256 /* inst.operands[i] is a shifted-register operand; encode
10257 it into inst.instruction in the format used by Thumb32. */
10260 encode_thumb32_shifted_operand (int i
)
10262 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10263 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10265 constraint (inst
.operands
[i
].immisreg
,
10266 _("shift by register not allowed in thumb mode"));
10267 inst
.instruction
|= inst
.operands
[i
].reg
;
10268 if (shift
== SHIFT_RRX
)
10269 inst
.instruction
|= SHIFT_ROR
<< 4;
10272 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10273 _("expression too complex"));
10275 constraint (value
> 32
10276 || (value
== 32 && (shift
== SHIFT_LSL
10277 || shift
== SHIFT_ROR
)),
10278 _("shift expression is too large"));
10282 else if (value
== 32)
10285 inst
.instruction
|= shift
<< 4;
10286 inst
.instruction
|= (value
& 0x1c) << 10;
10287 inst
.instruction
|= (value
& 0x03) << 6;
10292 /* inst.operands[i] was set up by parse_address. Encode it into a
10293 Thumb32 format load or store instruction. Reject forms that cannot
10294 be used with such instructions. If is_t is true, reject forms that
10295 cannot be used with a T instruction; if is_d is true, reject forms
10296 that cannot be used with a D instruction. If it is a store insn,
10297 reject PC in Rn. */
10300 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10302 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10304 constraint (!inst
.operands
[i
].isreg
,
10305 _("Instruction does not support =N addresses"));
10307 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10308 if (inst
.operands
[i
].immisreg
)
10310 constraint (is_pc
, BAD_PC_ADDRESSING
);
10311 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10312 constraint (inst
.operands
[i
].negative
,
10313 _("Thumb does not support negative register indexing"));
10314 constraint (inst
.operands
[i
].postind
,
10315 _("Thumb does not support register post-indexing"));
10316 constraint (inst
.operands
[i
].writeback
,
10317 _("Thumb does not support register indexing with writeback"));
10318 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10319 _("Thumb supports only LSL in shifted register indexing"));
10321 inst
.instruction
|= inst
.operands
[i
].imm
;
10322 if (inst
.operands
[i
].shifted
)
10324 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10325 _("expression too complex"));
10326 constraint (inst
.reloc
.exp
.X_add_number
< 0
10327 || inst
.reloc
.exp
.X_add_number
> 3,
10328 _("shift out of range"));
10329 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10331 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10333 else if (inst
.operands
[i
].preind
)
10335 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10336 constraint (is_t
&& inst
.operands
[i
].writeback
,
10337 _("cannot use writeback with this instruction"));
10338 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10339 BAD_PC_ADDRESSING
);
10343 inst
.instruction
|= 0x01000000;
10344 if (inst
.operands
[i
].writeback
)
10345 inst
.instruction
|= 0x00200000;
10349 inst
.instruction
|= 0x00000c00;
10350 if (inst
.operands
[i
].writeback
)
10351 inst
.instruction
|= 0x00000100;
10353 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10355 else if (inst
.operands
[i
].postind
)
10357 gas_assert (inst
.operands
[i
].writeback
);
10358 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10359 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10362 inst
.instruction
|= 0x00200000;
10364 inst
.instruction
|= 0x00000900;
10365 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10367 else /* unindexed - only for coprocessor */
10368 inst
.error
= _("instruction does not accept unindexed addressing");
10371 /* Table of Thumb instructions which exist in both 16- and 32-bit
10372 encodings (the latter only in post-V6T2 cores). The index is the
10373 value used in the insns table below. When there is more than one
10374 possible 16-bit encoding for the instruction, this table always
10376 Also contains several pseudo-instructions used during relaxation. */
10377 #define T16_32_TAB \
10378 X(_adc, 4140, eb400000), \
10379 X(_adcs, 4140, eb500000), \
10380 X(_add, 1c00, eb000000), \
10381 X(_adds, 1c00, eb100000), \
10382 X(_addi, 0000, f1000000), \
10383 X(_addis, 0000, f1100000), \
10384 X(_add_pc,000f, f20f0000), \
10385 X(_add_sp,000d, f10d0000), \
10386 X(_adr, 000f, f20f0000), \
10387 X(_and, 4000, ea000000), \
10388 X(_ands, 4000, ea100000), \
10389 X(_asr, 1000, fa40f000), \
10390 X(_asrs, 1000, fa50f000), \
10391 X(_b, e000, f000b000), \
10392 X(_bcond, d000, f0008000), \
10393 X(_bic, 4380, ea200000), \
10394 X(_bics, 4380, ea300000), \
10395 X(_cmn, 42c0, eb100f00), \
10396 X(_cmp, 2800, ebb00f00), \
10397 X(_cpsie, b660, f3af8400), \
10398 X(_cpsid, b670, f3af8600), \
10399 X(_cpy, 4600, ea4f0000), \
10400 X(_dec_sp,80dd, f1ad0d00), \
10401 X(_eor, 4040, ea800000), \
10402 X(_eors, 4040, ea900000), \
10403 X(_inc_sp,00dd, f10d0d00), \
10404 X(_ldmia, c800, e8900000), \
10405 X(_ldr, 6800, f8500000), \
10406 X(_ldrb, 7800, f8100000), \
10407 X(_ldrh, 8800, f8300000), \
10408 X(_ldrsb, 5600, f9100000), \
10409 X(_ldrsh, 5e00, f9300000), \
10410 X(_ldr_pc,4800, f85f0000), \
10411 X(_ldr_pc2,4800, f85f0000), \
10412 X(_ldr_sp,9800, f85d0000), \
10413 X(_lsl, 0000, fa00f000), \
10414 X(_lsls, 0000, fa10f000), \
10415 X(_lsr, 0800, fa20f000), \
10416 X(_lsrs, 0800, fa30f000), \
10417 X(_mov, 2000, ea4f0000), \
10418 X(_movs, 2000, ea5f0000), \
10419 X(_mul, 4340, fb00f000), \
10420 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10421 X(_mvn, 43c0, ea6f0000), \
10422 X(_mvns, 43c0, ea7f0000), \
10423 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10424 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10425 X(_orr, 4300, ea400000), \
10426 X(_orrs, 4300, ea500000), \
10427 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10428 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10429 X(_rev, ba00, fa90f080), \
10430 X(_rev16, ba40, fa90f090), \
10431 X(_revsh, bac0, fa90f0b0), \
10432 X(_ror, 41c0, fa60f000), \
10433 X(_rors, 41c0, fa70f000), \
10434 X(_sbc, 4180, eb600000), \
10435 X(_sbcs, 4180, eb700000), \
10436 X(_stmia, c000, e8800000), \
10437 X(_str, 6000, f8400000), \
10438 X(_strb, 7000, f8000000), \
10439 X(_strh, 8000, f8200000), \
10440 X(_str_sp,9000, f84d0000), \
10441 X(_sub, 1e00, eba00000), \
10442 X(_subs, 1e00, ebb00000), \
10443 X(_subi, 8000, f1a00000), \
10444 X(_subis, 8000, f1b00000), \
10445 X(_sxtb, b240, fa4ff080), \
10446 X(_sxth, b200, fa0ff080), \
10447 X(_tst, 4200, ea100f00), \
10448 X(_uxtb, b2c0, fa5ff080), \
10449 X(_uxth, b280, fa1ff080), \
10450 X(_nop, bf00, f3af8000), \
10451 X(_yield, bf10, f3af8001), \
10452 X(_wfe, bf20, f3af8002), \
10453 X(_wfi, bf30, f3af8003), \
10454 X(_sev, bf40, f3af8004), \
10455 X(_sevl, bf50, f3af8005), \
10456 X(_udf, de00, f7f0a000)
10458 /* To catch errors in encoding functions, the codes are all offset by
10459 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10460 as 16-bit instructions. */
10461 #define X(a,b,c) T_MNEM##a
10462 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10465 #define X(a,b,c) 0x##b
10466 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10467 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10470 #define X(a,b,c) 0x##c
10471 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10472 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10473 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10477 /* Thumb instruction encoders, in alphabetical order. */
10479 /* ADDW or SUBW. */
10482 do_t_add_sub_w (void)
10486 Rd
= inst
.operands
[0].reg
;
10487 Rn
= inst
.operands
[1].reg
;
10489 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10490 is the SP-{plus,minus}-immediate form of the instruction. */
10492 constraint (Rd
== REG_PC
, BAD_PC
);
10494 reject_bad_reg (Rd
);
10496 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10497 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10500 /* Parse an add or subtract instruction. We get here with inst.instruction
10501 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10504 do_t_add_sub (void)
10508 Rd
= inst
.operands
[0].reg
;
10509 Rs
= (inst
.operands
[1].present
10510 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10511 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10514 set_it_insn_type_last ();
10516 if (unified_syntax
)
10519 bfd_boolean narrow
;
10522 flags
= (inst
.instruction
== T_MNEM_adds
10523 || inst
.instruction
== T_MNEM_subs
);
10525 narrow
= !in_it_block ();
10527 narrow
= in_it_block ();
10528 if (!inst
.operands
[2].isreg
)
10532 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10534 add
= (inst
.instruction
== T_MNEM_add
10535 || inst
.instruction
== T_MNEM_adds
);
10537 if (inst
.size_req
!= 4)
10539 /* Attempt to use a narrow opcode, with relaxation if
10541 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10542 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10543 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10544 opcode
= T_MNEM_add_sp
;
10545 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10546 opcode
= T_MNEM_add_pc
;
10547 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10550 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10552 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10556 inst
.instruction
= THUMB_OP16(opcode
);
10557 inst
.instruction
|= (Rd
<< 4) | Rs
;
10558 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10559 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10561 if (inst
.size_req
== 2)
10562 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10564 inst
.relax
= opcode
;
10568 constraint (inst
.size_req
== 2, BAD_HIREG
);
10570 if (inst
.size_req
== 4
10571 || (inst
.size_req
!= 2 && !opcode
))
10573 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10574 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10575 THUMB1_RELOC_ONLY
);
10578 constraint (add
, BAD_PC
);
10579 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10580 _("only SUBS PC, LR, #const allowed"));
10581 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10582 _("expression too complex"));
10583 constraint (inst
.reloc
.exp
.X_add_number
< 0
10584 || inst
.reloc
.exp
.X_add_number
> 0xff,
10585 _("immediate value out of range"));
10586 inst
.instruction
= T2_SUBS_PC_LR
10587 | inst
.reloc
.exp
.X_add_number
;
10588 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10591 else if (Rs
== REG_PC
)
10593 /* Always use addw/subw. */
10594 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10595 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10599 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10600 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10603 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10605 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10607 inst
.instruction
|= Rd
<< 8;
10608 inst
.instruction
|= Rs
<< 16;
10613 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10614 unsigned int shift
= inst
.operands
[2].shift_kind
;
10616 Rn
= inst
.operands
[2].reg
;
10617 /* See if we can do this with a 16-bit instruction. */
10618 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10620 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10625 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10626 || inst
.instruction
== T_MNEM_add
)
10628 : T_OPCODE_SUB_R3
);
10629 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10633 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10635 /* Thumb-1 cores (except v6-M) require at least one high
10636 register in a narrow non flag setting add. */
10637 if (Rd
> 7 || Rn
> 7
10638 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10639 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10646 inst
.instruction
= T_OPCODE_ADD_HI
;
10647 inst
.instruction
|= (Rd
& 8) << 4;
10648 inst
.instruction
|= (Rd
& 7);
10649 inst
.instruction
|= Rn
<< 3;
10655 constraint (Rd
== REG_PC
, BAD_PC
);
10656 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10657 constraint (Rs
== REG_PC
, BAD_PC
);
10658 reject_bad_reg (Rn
);
10660 /* If we get here, it can't be done in 16 bits. */
10661 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10662 _("shift must be constant"));
10663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10664 inst
.instruction
|= Rd
<< 8;
10665 inst
.instruction
|= Rs
<< 16;
10666 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10667 _("shift value over 3 not allowed in thumb mode"));
10668 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10669 _("only LSL shift allowed in thumb mode"));
10670 encode_thumb32_shifted_operand (2);
10675 constraint (inst
.instruction
== T_MNEM_adds
10676 || inst
.instruction
== T_MNEM_subs
,
10679 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10681 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10682 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10685 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10686 ? 0x0000 : 0x8000);
10687 inst
.instruction
|= (Rd
<< 4) | Rs
;
10688 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10692 Rn
= inst
.operands
[2].reg
;
10693 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10695 /* We now have Rd, Rs, and Rn set to registers. */
10696 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10698 /* Can't do this for SUB. */
10699 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10700 inst
.instruction
= T_OPCODE_ADD_HI
;
10701 inst
.instruction
|= (Rd
& 8) << 4;
10702 inst
.instruction
|= (Rd
& 7);
10704 inst
.instruction
|= Rn
<< 3;
10706 inst
.instruction
|= Rs
<< 3;
10708 constraint (1, _("dest must overlap one source register"));
10712 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10713 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10714 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10724 Rd
= inst
.operands
[0].reg
;
10725 reject_bad_reg (Rd
);
10727 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10729 /* Defer to section relaxation. */
10730 inst
.relax
= inst
.instruction
;
10731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10732 inst
.instruction
|= Rd
<< 4;
10734 else if (unified_syntax
&& inst
.size_req
!= 2)
10736 /* Generate a 32-bit opcode. */
10737 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10738 inst
.instruction
|= Rd
<< 8;
10739 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10740 inst
.reloc
.pc_rel
= 1;
10744 /* Generate a 16-bit opcode. */
10745 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10746 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10747 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10748 inst
.reloc
.pc_rel
= 1;
10749 inst
.instruction
|= Rd
<< 4;
10752 if (inst
.reloc
.exp
.X_op
== O_symbol
10753 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10754 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10755 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10756 inst
.reloc
.exp
.X_add_number
+= 1;
10759 /* Arithmetic instructions for which there is just one 16-bit
10760 instruction encoding, and it allows only two low registers.
10761 For maximal compatibility with ARM syntax, we allow three register
10762 operands even when Thumb-32 instructions are not available, as long
10763 as the first two are identical. For instance, both "sbc r0,r1" and
10764 "sbc r0,r0,r1" are allowed. */
10770 Rd
= inst
.operands
[0].reg
;
10771 Rs
= (inst
.operands
[1].present
10772 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10773 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10774 Rn
= inst
.operands
[2].reg
;
10776 reject_bad_reg (Rd
);
10777 reject_bad_reg (Rs
);
10778 if (inst
.operands
[2].isreg
)
10779 reject_bad_reg (Rn
);
10781 if (unified_syntax
)
10783 if (!inst
.operands
[2].isreg
)
10785 /* For an immediate, we always generate a 32-bit opcode;
10786 section relaxation will shrink it later if possible. */
10787 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10788 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10789 inst
.instruction
|= Rd
<< 8;
10790 inst
.instruction
|= Rs
<< 16;
10791 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10795 bfd_boolean narrow
;
10797 /* See if we can do this with a 16-bit instruction. */
10798 if (THUMB_SETS_FLAGS (inst
.instruction
))
10799 narrow
= !in_it_block ();
10801 narrow
= in_it_block ();
10803 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10805 if (inst
.operands
[2].shifted
)
10807 if (inst
.size_req
== 4)
10813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10814 inst
.instruction
|= Rd
;
10815 inst
.instruction
|= Rn
<< 3;
10819 /* If we get here, it can't be done in 16 bits. */
10820 constraint (inst
.operands
[2].shifted
10821 && inst
.operands
[2].immisreg
,
10822 _("shift must be constant"));
10823 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10824 inst
.instruction
|= Rd
<< 8;
10825 inst
.instruction
|= Rs
<< 16;
10826 encode_thumb32_shifted_operand (2);
10831 /* On its face this is a lie - the instruction does set the
10832 flags. However, the only supported mnemonic in this mode
10833 says it doesn't. */
10834 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10836 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10837 _("unshifted register required"));
10838 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10839 constraint (Rd
!= Rs
,
10840 _("dest and source1 must be the same register"));
10842 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10843 inst
.instruction
|= Rd
;
10844 inst
.instruction
|= Rn
<< 3;
10848 /* Similarly, but for instructions where the arithmetic operation is
10849 commutative, so we can allow either of them to be different from
10850 the destination operand in a 16-bit instruction. For instance, all
10851 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10858 Rd
= inst
.operands
[0].reg
;
10859 Rs
= (inst
.operands
[1].present
10860 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10861 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10862 Rn
= inst
.operands
[2].reg
;
10864 reject_bad_reg (Rd
);
10865 reject_bad_reg (Rs
);
10866 if (inst
.operands
[2].isreg
)
10867 reject_bad_reg (Rn
);
10869 if (unified_syntax
)
10871 if (!inst
.operands
[2].isreg
)
10873 /* For an immediate, we always generate a 32-bit opcode;
10874 section relaxation will shrink it later if possible. */
10875 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10876 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10877 inst
.instruction
|= Rd
<< 8;
10878 inst
.instruction
|= Rs
<< 16;
10879 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10883 bfd_boolean narrow
;
10885 /* See if we can do this with a 16-bit instruction. */
10886 if (THUMB_SETS_FLAGS (inst
.instruction
))
10887 narrow
= !in_it_block ();
10889 narrow
= in_it_block ();
10891 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10893 if (inst
.operands
[2].shifted
)
10895 if (inst
.size_req
== 4)
10902 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10903 inst
.instruction
|= Rd
;
10904 inst
.instruction
|= Rn
<< 3;
10909 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10910 inst
.instruction
|= Rd
;
10911 inst
.instruction
|= Rs
<< 3;
10916 /* If we get here, it can't be done in 16 bits. */
10917 constraint (inst
.operands
[2].shifted
10918 && inst
.operands
[2].immisreg
,
10919 _("shift must be constant"));
10920 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10921 inst
.instruction
|= Rd
<< 8;
10922 inst
.instruction
|= Rs
<< 16;
10923 encode_thumb32_shifted_operand (2);
10928 /* On its face this is a lie - the instruction does set the
10929 flags. However, the only supported mnemonic in this mode
10930 says it doesn't. */
10931 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10933 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10934 _("unshifted register required"));
10935 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 inst
.instruction
|= Rd
;
10941 inst
.instruction
|= Rn
<< 3;
10943 inst
.instruction
|= Rs
<< 3;
10945 constraint (1, _("dest must overlap one source register"));
10953 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10954 constraint (msb
> 32, _("bit-field extends past end of register"));
10955 /* The instruction encoding stores the LSB and MSB,
10956 not the LSB and width. */
10957 Rd
= inst
.operands
[0].reg
;
10958 reject_bad_reg (Rd
);
10959 inst
.instruction
|= Rd
<< 8;
10960 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10961 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10962 inst
.instruction
|= msb
- 1;
10971 Rd
= inst
.operands
[0].reg
;
10972 reject_bad_reg (Rd
);
10974 /* #0 in second position is alternative syntax for bfc, which is
10975 the same instruction but with REG_PC in the Rm field. */
10976 if (!inst
.operands
[1].isreg
)
10980 Rn
= inst
.operands
[1].reg
;
10981 reject_bad_reg (Rn
);
10984 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10985 constraint (msb
> 32, _("bit-field extends past end of register"));
10986 /* The instruction encoding stores the LSB and MSB,
10987 not the LSB and width. */
10988 inst
.instruction
|= Rd
<< 8;
10989 inst
.instruction
|= Rn
<< 16;
10990 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10991 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10992 inst
.instruction
|= msb
- 1;
11000 Rd
= inst
.operands
[0].reg
;
11001 Rn
= inst
.operands
[1].reg
;
11003 reject_bad_reg (Rd
);
11004 reject_bad_reg (Rn
);
11006 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11007 _("bit-field extends past end of register"));
11008 inst
.instruction
|= Rd
<< 8;
11009 inst
.instruction
|= Rn
<< 16;
11010 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11011 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11012 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11015 /* ARM V5 Thumb BLX (argument parse)
11016 BLX <target_addr> which is BLX(1)
11017 BLX <Rm> which is BLX(2)
11018 Unfortunately, there are two different opcodes for this mnemonic.
11019 So, the insns[].value is not used, and the code here zaps values
11020 into inst.instruction.
11022 ??? How to take advantage of the additional two bits of displacement
11023 available in Thumb32 mode? Need new relocation? */
11028 set_it_insn_type_last ();
11030 if (inst
.operands
[0].isreg
)
11032 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11033 /* We have a register, so this is BLX(2). */
11034 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11038 /* No register. This must be BLX(1). */
11039 inst
.instruction
= 0xf000e800;
11040 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11049 bfd_reloc_code_real_type reloc
;
11052 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11054 if (in_it_block ())
11056 /* Conditional branches inside IT blocks are encoded as unconditional
11058 cond
= COND_ALWAYS
;
11063 if (cond
!= COND_ALWAYS
)
11064 opcode
= T_MNEM_bcond
;
11066 opcode
= inst
.instruction
;
11069 && (inst
.size_req
== 4
11070 || (inst
.size_req
!= 2
11071 && (inst
.operands
[0].hasreloc
11072 || inst
.reloc
.exp
.X_op
== O_constant
))))
11074 inst
.instruction
= THUMB_OP32(opcode
);
11075 if (cond
== COND_ALWAYS
)
11076 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11079 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11080 _("selected architecture does not support "
11081 "wide conditional branch instruction"));
11083 gas_assert (cond
!= 0xF);
11084 inst
.instruction
|= cond
<< 22;
11085 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11090 inst
.instruction
= THUMB_OP16(opcode
);
11091 if (cond
== COND_ALWAYS
)
11092 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11095 inst
.instruction
|= cond
<< 8;
11096 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11098 /* Allow section relaxation. */
11099 if (unified_syntax
&& inst
.size_req
!= 2)
11100 inst
.relax
= opcode
;
11102 inst
.reloc
.type
= reloc
;
11103 inst
.reloc
.pc_rel
= 1;
11106 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11107 between the two is the maximum immediate allowed - which is passed in
11110 do_t_bkpt_hlt1 (int range
)
11112 constraint (inst
.cond
!= COND_ALWAYS
,
11113 _("instruction is always unconditional"));
11114 if (inst
.operands
[0].present
)
11116 constraint (inst
.operands
[0].imm
> range
,
11117 _("immediate value out of range"));
11118 inst
.instruction
|= inst
.operands
[0].imm
;
11121 set_it_insn_type (NEUTRAL_IT_INSN
);
11127 do_t_bkpt_hlt1 (63);
11133 do_t_bkpt_hlt1 (255);
11137 do_t_branch23 (void)
11139 set_it_insn_type_last ();
11140 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11142 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11143 this file. We used to simply ignore the PLT reloc type here --
11144 the branch encoding is now needed to deal with TLSCALL relocs.
11145 So if we see a PLT reloc now, put it back to how it used to be to
11146 keep the preexisting behaviour. */
11147 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11148 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11150 #if defined(OBJ_COFF)
11151 /* If the destination of the branch is a defined symbol which does not have
11152 the THUMB_FUNC attribute, then we must be calling a function which has
11153 the (interfacearm) attribute. We look for the Thumb entry point to that
11154 function and change the branch to refer to that function instead. */
11155 if ( inst
.reloc
.exp
.X_op
== O_symbol
11156 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11157 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11158 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11159 inst
.reloc
.exp
.X_add_symbol
=
11160 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11167 set_it_insn_type_last ();
11168 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11169 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11170 should cause the alignment to be checked once it is known. This is
11171 because BX PC only works if the instruction is word aligned. */
11179 set_it_insn_type_last ();
11180 Rm
= inst
.operands
[0].reg
;
11181 reject_bad_reg (Rm
);
11182 inst
.instruction
|= Rm
<< 16;
11191 Rd
= inst
.operands
[0].reg
;
11192 Rm
= inst
.operands
[1].reg
;
11194 reject_bad_reg (Rd
);
11195 reject_bad_reg (Rm
);
11197 inst
.instruction
|= Rd
<< 8;
11198 inst
.instruction
|= Rm
<< 16;
11199 inst
.instruction
|= Rm
;
11205 set_it_insn_type (OUTSIDE_IT_INSN
);
11206 inst
.instruction
|= inst
.operands
[0].imm
;
11212 set_it_insn_type (OUTSIDE_IT_INSN
);
11214 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11215 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11217 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11218 inst
.instruction
= 0xf3af8000;
11219 inst
.instruction
|= imod
<< 9;
11220 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11221 if (inst
.operands
[1].present
)
11222 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11226 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11227 && (inst
.operands
[0].imm
& 4),
11228 _("selected processor does not support 'A' form "
11229 "of this instruction"));
11230 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11231 _("Thumb does not support the 2-argument "
11232 "form of this instruction"));
11233 inst
.instruction
|= inst
.operands
[0].imm
;
11237 /* THUMB CPY instruction (argument parse). */
11242 if (inst
.size_req
== 4)
11244 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11245 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11246 inst
.instruction
|= inst
.operands
[1].reg
;
11250 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11251 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11252 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11259 set_it_insn_type (OUTSIDE_IT_INSN
);
11260 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11261 inst
.instruction
|= inst
.operands
[0].reg
;
11262 inst
.reloc
.pc_rel
= 1;
11263 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11269 inst
.instruction
|= inst
.operands
[0].imm
;
11275 unsigned Rd
, Rn
, Rm
;
11277 Rd
= inst
.operands
[0].reg
;
11278 Rn
= (inst
.operands
[1].present
11279 ? inst
.operands
[1].reg
: Rd
);
11280 Rm
= inst
.operands
[2].reg
;
11282 reject_bad_reg (Rd
);
11283 reject_bad_reg (Rn
);
11284 reject_bad_reg (Rm
);
11286 inst
.instruction
|= Rd
<< 8;
11287 inst
.instruction
|= Rn
<< 16;
11288 inst
.instruction
|= Rm
;
11294 if (unified_syntax
&& inst
.size_req
== 4)
11295 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11297 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11303 unsigned int cond
= inst
.operands
[0].imm
;
11305 set_it_insn_type (IT_INSN
);
11306 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11308 now_it
.warn_deprecated
= FALSE
;
11310 /* If the condition is a negative condition, invert the mask. */
11311 if ((cond
& 0x1) == 0x0)
11313 unsigned int mask
= inst
.instruction
& 0x000f;
11315 if ((mask
& 0x7) == 0)
11317 /* No conversion needed. */
11318 now_it
.block_length
= 1;
11320 else if ((mask
& 0x3) == 0)
11323 now_it
.block_length
= 2;
11325 else if ((mask
& 0x1) == 0)
11328 now_it
.block_length
= 3;
11333 now_it
.block_length
= 4;
11336 inst
.instruction
&= 0xfff0;
11337 inst
.instruction
|= mask
;
11340 inst
.instruction
|= cond
<< 4;
11343 /* Helper function used for both push/pop and ldm/stm. */
11345 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11349 load
= (inst
.instruction
& (1 << 20)) != 0;
11351 if (mask
& (1 << 13))
11352 inst
.error
= _("SP not allowed in register list");
11354 if ((mask
& (1 << base
)) != 0
11356 inst
.error
= _("having the base register in the register list when "
11357 "using write back is UNPREDICTABLE");
11361 if (mask
& (1 << 15))
11363 if (mask
& (1 << 14))
11364 inst
.error
= _("LR and PC should not both be in register list");
11366 set_it_insn_type_last ();
11371 if (mask
& (1 << 15))
11372 inst
.error
= _("PC not allowed in register list");
11375 if ((mask
& (mask
- 1)) == 0)
11377 /* Single register transfers implemented as str/ldr. */
11380 if (inst
.instruction
& (1 << 23))
11381 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11383 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11387 if (inst
.instruction
& (1 << 23))
11388 inst
.instruction
= 0x00800000; /* ia -> [base] */
11390 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11393 inst
.instruction
|= 0xf8400000;
11395 inst
.instruction
|= 0x00100000;
11397 mask
= ffs (mask
) - 1;
11400 else if (writeback
)
11401 inst
.instruction
|= WRITE_BACK
;
11403 inst
.instruction
|= mask
;
11404 inst
.instruction
|= base
<< 16;
11410 /* This really doesn't seem worth it. */
11411 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11412 _("expression too complex"));
11413 constraint (inst
.operands
[1].writeback
,
11414 _("Thumb load/store multiple does not support {reglist}^"));
11416 if (unified_syntax
)
11418 bfd_boolean narrow
;
11422 /* See if we can use a 16-bit instruction. */
11423 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11424 && inst
.size_req
!= 4
11425 && !(inst
.operands
[1].imm
& ~0xff))
11427 mask
= 1 << inst
.operands
[0].reg
;
11429 if (inst
.operands
[0].reg
<= 7)
11431 if (inst
.instruction
== T_MNEM_stmia
11432 ? inst
.operands
[0].writeback
11433 : (inst
.operands
[0].writeback
11434 == !(inst
.operands
[1].imm
& mask
)))
11436 if (inst
.instruction
== T_MNEM_stmia
11437 && (inst
.operands
[1].imm
& mask
)
11438 && (inst
.operands
[1].imm
& (mask
- 1)))
11439 as_warn (_("value stored for r%d is UNKNOWN"),
11440 inst
.operands
[0].reg
);
11442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11443 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11444 inst
.instruction
|= inst
.operands
[1].imm
;
11447 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11449 /* This means 1 register in reg list one of 3 situations:
11450 1. Instruction is stmia, but without writeback.
11451 2. lmdia without writeback, but with Rn not in
11453 3. ldmia with writeback, but with Rn in reglist.
11454 Case 3 is UNPREDICTABLE behaviour, so we handle
11455 case 1 and 2 which can be converted into a 16-bit
11456 str or ldr. The SP cases are handled below. */
11457 unsigned long opcode
;
11458 /* First, record an error for Case 3. */
11459 if (inst
.operands
[1].imm
& mask
11460 && inst
.operands
[0].writeback
)
11462 _("having the base register in the register list when "
11463 "using write back is UNPREDICTABLE");
11465 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11467 inst
.instruction
= THUMB_OP16 (opcode
);
11468 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11469 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11473 else if (inst
.operands
[0] .reg
== REG_SP
)
11475 if (inst
.operands
[0].writeback
)
11478 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11479 ? T_MNEM_push
: T_MNEM_pop
);
11480 inst
.instruction
|= inst
.operands
[1].imm
;
11483 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11486 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11487 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11488 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11496 if (inst
.instruction
< 0xffff)
11497 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11499 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11500 inst
.operands
[0].writeback
);
11505 constraint (inst
.operands
[0].reg
> 7
11506 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11507 constraint (inst
.instruction
!= T_MNEM_ldmia
11508 && inst
.instruction
!= T_MNEM_stmia
,
11509 _("Thumb-2 instruction only valid in unified syntax"));
11510 if (inst
.instruction
== T_MNEM_stmia
)
11512 if (!inst
.operands
[0].writeback
)
11513 as_warn (_("this instruction will write back the base register"));
11514 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11515 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11516 as_warn (_("value stored for r%d is UNKNOWN"),
11517 inst
.operands
[0].reg
);
11521 if (!inst
.operands
[0].writeback
11522 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11523 as_warn (_("this instruction will write back the base register"));
11524 else if (inst
.operands
[0].writeback
11525 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11526 as_warn (_("this instruction will not write back the base register"));
11529 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11530 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11531 inst
.instruction
|= inst
.operands
[1].imm
;
11538 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11539 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11540 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11541 || inst
.operands
[1].negative
,
11544 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11546 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11547 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11548 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11554 if (!inst
.operands
[1].present
)
11556 constraint (inst
.operands
[0].reg
== REG_LR
,
11557 _("r14 not allowed as first register "
11558 "when second register is omitted"));
11559 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11561 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11565 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11566 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11572 unsigned long opcode
;
11575 if (inst
.operands
[0].isreg
11576 && !inst
.operands
[0].preind
11577 && inst
.operands
[0].reg
== REG_PC
)
11578 set_it_insn_type_last ();
11580 opcode
= inst
.instruction
;
11581 if (unified_syntax
)
11583 if (!inst
.operands
[1].isreg
)
11585 if (opcode
<= 0xffff)
11586 inst
.instruction
= THUMB_OP32 (opcode
);
11587 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11590 if (inst
.operands
[1].isreg
11591 && !inst
.operands
[1].writeback
11592 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11593 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11594 && opcode
<= 0xffff
11595 && inst
.size_req
!= 4)
11597 /* Insn may have a 16-bit form. */
11598 Rn
= inst
.operands
[1].reg
;
11599 if (inst
.operands
[1].immisreg
)
11601 inst
.instruction
= THUMB_OP16 (opcode
);
11603 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11605 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11606 reject_bad_reg (inst
.operands
[1].imm
);
11608 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11609 && opcode
!= T_MNEM_ldrsb
)
11610 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11611 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11618 if (inst
.reloc
.pc_rel
)
11619 opcode
= T_MNEM_ldr_pc2
;
11621 opcode
= T_MNEM_ldr_pc
;
11625 if (opcode
== T_MNEM_ldr
)
11626 opcode
= T_MNEM_ldr_sp
;
11628 opcode
= T_MNEM_str_sp
;
11630 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11634 inst
.instruction
= inst
.operands
[0].reg
;
11635 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11637 inst
.instruction
|= THUMB_OP16 (opcode
);
11638 if (inst
.size_req
== 2)
11639 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11641 inst
.relax
= opcode
;
11645 /* Definitely a 32-bit variant. */
11647 /* Warning for Erratum 752419. */
11648 if (opcode
== T_MNEM_ldr
11649 && inst
.operands
[0].reg
== REG_SP
11650 && inst
.operands
[1].writeback
== 1
11651 && !inst
.operands
[1].immisreg
)
11653 if (no_cpu_selected ()
11654 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11655 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11656 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11657 as_warn (_("This instruction may be unpredictable "
11658 "if executed on M-profile cores "
11659 "with interrupts enabled."));
11662 /* Do some validations regarding addressing modes. */
11663 if (inst
.operands
[1].immisreg
)
11664 reject_bad_reg (inst
.operands
[1].imm
);
11666 constraint (inst
.operands
[1].writeback
== 1
11667 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11670 inst
.instruction
= THUMB_OP32 (opcode
);
11671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11672 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11673 check_ldr_r15_aligned ();
11677 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11679 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11681 /* Only [Rn,Rm] is acceptable. */
11682 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11683 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11684 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11685 || inst
.operands
[1].negative
,
11686 _("Thumb does not support this addressing mode"));
11687 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11692 if (!inst
.operands
[1].isreg
)
11693 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11696 constraint (!inst
.operands
[1].preind
11697 || inst
.operands
[1].shifted
11698 || inst
.operands
[1].writeback
,
11699 _("Thumb does not support this addressing mode"));
11700 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11702 constraint (inst
.instruction
& 0x0600,
11703 _("byte or halfword not valid for base register"));
11704 constraint (inst
.operands
[1].reg
== REG_PC
11705 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11706 _("r15 based store not allowed"));
11707 constraint (inst
.operands
[1].immisreg
,
11708 _("invalid base register for register offset"));
11710 if (inst
.operands
[1].reg
== REG_PC
)
11711 inst
.instruction
= T_OPCODE_LDR_PC
;
11712 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11713 inst
.instruction
= T_OPCODE_LDR_SP
;
11715 inst
.instruction
= T_OPCODE_STR_SP
;
11717 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11718 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11722 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11723 if (!inst
.operands
[1].immisreg
)
11725 /* Immediate offset. */
11726 inst
.instruction
|= inst
.operands
[0].reg
;
11727 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11728 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11732 /* Register offset. */
11733 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11734 constraint (inst
.operands
[1].negative
,
11735 _("Thumb does not support this addressing mode"));
11738 switch (inst
.instruction
)
11740 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11741 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11742 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11743 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11744 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11745 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11746 case 0x5600 /* ldrsb */:
11747 case 0x5e00 /* ldrsh */: break;
11751 inst
.instruction
|= inst
.operands
[0].reg
;
11752 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11753 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11759 if (!inst
.operands
[1].present
)
11761 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11762 constraint (inst
.operands
[0].reg
== REG_LR
,
11763 _("r14 not allowed here"));
11764 constraint (inst
.operands
[0].reg
== REG_R12
,
11765 _("r12 not allowed here"));
11768 if (inst
.operands
[2].writeback
11769 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11770 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11771 as_warn (_("base register written back, and overlaps "
11772 "one of transfer registers"));
11774 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11775 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11776 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11783 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11789 unsigned Rd
, Rn
, Rm
, Ra
;
11791 Rd
= inst
.operands
[0].reg
;
11792 Rn
= inst
.operands
[1].reg
;
11793 Rm
= inst
.operands
[2].reg
;
11794 Ra
= inst
.operands
[3].reg
;
11796 reject_bad_reg (Rd
);
11797 reject_bad_reg (Rn
);
11798 reject_bad_reg (Rm
);
11799 reject_bad_reg (Ra
);
11801 inst
.instruction
|= Rd
<< 8;
11802 inst
.instruction
|= Rn
<< 16;
11803 inst
.instruction
|= Rm
;
11804 inst
.instruction
|= Ra
<< 12;
11810 unsigned RdLo
, RdHi
, Rn
, Rm
;
11812 RdLo
= inst
.operands
[0].reg
;
11813 RdHi
= inst
.operands
[1].reg
;
11814 Rn
= inst
.operands
[2].reg
;
11815 Rm
= inst
.operands
[3].reg
;
11817 reject_bad_reg (RdLo
);
11818 reject_bad_reg (RdHi
);
11819 reject_bad_reg (Rn
);
11820 reject_bad_reg (Rm
);
11822 inst
.instruction
|= RdLo
<< 12;
11823 inst
.instruction
|= RdHi
<< 8;
11824 inst
.instruction
|= Rn
<< 16;
11825 inst
.instruction
|= Rm
;
11829 do_t_mov_cmp (void)
11833 Rn
= inst
.operands
[0].reg
;
11834 Rm
= inst
.operands
[1].reg
;
11837 set_it_insn_type_last ();
11839 if (unified_syntax
)
11841 int r0off
= (inst
.instruction
== T_MNEM_mov
11842 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11843 unsigned long opcode
;
11844 bfd_boolean narrow
;
11845 bfd_boolean low_regs
;
11847 low_regs
= (Rn
<= 7 && Rm
<= 7);
11848 opcode
= inst
.instruction
;
11849 if (in_it_block ())
11850 narrow
= opcode
!= T_MNEM_movs
;
11852 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11853 if (inst
.size_req
== 4
11854 || inst
.operands
[1].shifted
)
11857 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11858 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11859 && !inst
.operands
[1].shifted
11863 inst
.instruction
= T2_SUBS_PC_LR
;
11867 if (opcode
== T_MNEM_cmp
)
11869 constraint (Rn
== REG_PC
, BAD_PC
);
11872 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11874 warn_deprecated_sp (Rm
);
11875 /* R15 was documented as a valid choice for Rm in ARMv6,
11876 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11877 tools reject R15, so we do too. */
11878 constraint (Rm
== REG_PC
, BAD_PC
);
11881 reject_bad_reg (Rm
);
11883 else if (opcode
== T_MNEM_mov
11884 || opcode
== T_MNEM_movs
)
11886 if (inst
.operands
[1].isreg
)
11888 if (opcode
== T_MNEM_movs
)
11890 reject_bad_reg (Rn
);
11891 reject_bad_reg (Rm
);
11895 /* This is mov.n. */
11896 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11897 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11899 as_tsktsk (_("Use of r%u as a source register is "
11900 "deprecated when r%u is the destination "
11901 "register."), Rm
, Rn
);
11906 /* This is mov.w. */
11907 constraint (Rn
== REG_PC
, BAD_PC
);
11908 constraint (Rm
== REG_PC
, BAD_PC
);
11909 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11913 reject_bad_reg (Rn
);
11916 if (!inst
.operands
[1].isreg
)
11918 /* Immediate operand. */
11919 if (!in_it_block () && opcode
== T_MNEM_mov
)
11921 if (low_regs
&& narrow
)
11923 inst
.instruction
= THUMB_OP16 (opcode
);
11924 inst
.instruction
|= Rn
<< 8;
11925 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11926 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11928 if (inst
.size_req
== 2)
11929 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11931 inst
.relax
= opcode
;
11936 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11937 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11938 THUMB1_RELOC_ONLY
);
11940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11941 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11942 inst
.instruction
|= Rn
<< r0off
;
11943 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11946 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11947 && (inst
.instruction
== T_MNEM_mov
11948 || inst
.instruction
== T_MNEM_movs
))
11950 /* Register shifts are encoded as separate shift instructions. */
11951 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11953 if (in_it_block ())
11958 if (inst
.size_req
== 4)
11961 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11967 switch (inst
.operands
[1].shift_kind
)
11970 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11973 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11976 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11979 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11985 inst
.instruction
= opcode
;
11988 inst
.instruction
|= Rn
;
11989 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11994 inst
.instruction
|= CONDS_BIT
;
11996 inst
.instruction
|= Rn
<< 8;
11997 inst
.instruction
|= Rm
<< 16;
11998 inst
.instruction
|= inst
.operands
[1].imm
;
12003 /* Some mov with immediate shift have narrow variants.
12004 Register shifts are handled above. */
12005 if (low_regs
&& inst
.operands
[1].shifted
12006 && (inst
.instruction
== T_MNEM_mov
12007 || inst
.instruction
== T_MNEM_movs
))
12009 if (in_it_block ())
12010 narrow
= (inst
.instruction
== T_MNEM_mov
);
12012 narrow
= (inst
.instruction
== T_MNEM_movs
);
12017 switch (inst
.operands
[1].shift_kind
)
12019 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12020 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12021 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12022 default: narrow
= FALSE
; break;
12028 inst
.instruction
|= Rn
;
12029 inst
.instruction
|= Rm
<< 3;
12030 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12034 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12035 inst
.instruction
|= Rn
<< r0off
;
12036 encode_thumb32_shifted_operand (1);
12040 switch (inst
.instruction
)
12043 /* In v4t or v5t a move of two lowregs produces unpredictable
12044 results. Don't allow this. */
12047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12048 "MOV Rd, Rs with two low registers is not "
12049 "permitted on this architecture");
12050 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12054 inst
.instruction
= T_OPCODE_MOV_HR
;
12055 inst
.instruction
|= (Rn
& 0x8) << 4;
12056 inst
.instruction
|= (Rn
& 0x7);
12057 inst
.instruction
|= Rm
<< 3;
12061 /* We know we have low registers at this point.
12062 Generate LSLS Rd, Rs, #0. */
12063 inst
.instruction
= T_OPCODE_LSL_I
;
12064 inst
.instruction
|= Rn
;
12065 inst
.instruction
|= Rm
<< 3;
12071 inst
.instruction
= T_OPCODE_CMP_LR
;
12072 inst
.instruction
|= Rn
;
12073 inst
.instruction
|= Rm
<< 3;
12077 inst
.instruction
= T_OPCODE_CMP_HR
;
12078 inst
.instruction
|= (Rn
& 0x8) << 4;
12079 inst
.instruction
|= (Rn
& 0x7);
12080 inst
.instruction
|= Rm
<< 3;
12087 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12089 /* PR 10443: Do not silently ignore shifted operands. */
12090 constraint (inst
.operands
[1].shifted
,
12091 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12093 if (inst
.operands
[1].isreg
)
12095 if (Rn
< 8 && Rm
< 8)
12097 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12098 since a MOV instruction produces unpredictable results. */
12099 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12100 inst
.instruction
= T_OPCODE_ADD_I3
;
12102 inst
.instruction
= T_OPCODE_CMP_LR
;
12104 inst
.instruction
|= Rn
;
12105 inst
.instruction
|= Rm
<< 3;
12109 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12110 inst
.instruction
= T_OPCODE_MOV_HR
;
12112 inst
.instruction
= T_OPCODE_CMP_HR
;
12118 constraint (Rn
> 7,
12119 _("only lo regs allowed with immediate"));
12120 inst
.instruction
|= Rn
<< 8;
12121 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12132 top
= (inst
.instruction
& 0x00800000) != 0;
12133 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12135 constraint (top
, _(":lower16: not allowed in this instruction"));
12136 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12138 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12140 constraint (!top
, _(":upper16: not allowed in this instruction"));
12141 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12144 Rd
= inst
.operands
[0].reg
;
12145 reject_bad_reg (Rd
);
12147 inst
.instruction
|= Rd
<< 8;
12148 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12150 imm
= inst
.reloc
.exp
.X_add_number
;
12151 inst
.instruction
|= (imm
& 0xf000) << 4;
12152 inst
.instruction
|= (imm
& 0x0800) << 15;
12153 inst
.instruction
|= (imm
& 0x0700) << 4;
12154 inst
.instruction
|= (imm
& 0x00ff);
12159 do_t_mvn_tst (void)
12163 Rn
= inst
.operands
[0].reg
;
12164 Rm
= inst
.operands
[1].reg
;
12166 if (inst
.instruction
== T_MNEM_cmp
12167 || inst
.instruction
== T_MNEM_cmn
)
12168 constraint (Rn
== REG_PC
, BAD_PC
);
12170 reject_bad_reg (Rn
);
12171 reject_bad_reg (Rm
);
12173 if (unified_syntax
)
12175 int r0off
= (inst
.instruction
== T_MNEM_mvn
12176 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12177 bfd_boolean narrow
;
12179 if (inst
.size_req
== 4
12180 || inst
.instruction
> 0xffff
12181 || inst
.operands
[1].shifted
12182 || Rn
> 7 || Rm
> 7)
12184 else if (inst
.instruction
== T_MNEM_cmn
12185 || inst
.instruction
== T_MNEM_tst
)
12187 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12188 narrow
= !in_it_block ();
12190 narrow
= in_it_block ();
12192 if (!inst
.operands
[1].isreg
)
12194 /* For an immediate, we always generate a 32-bit opcode;
12195 section relaxation will shrink it later if possible. */
12196 if (inst
.instruction
< 0xffff)
12197 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12198 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12199 inst
.instruction
|= Rn
<< r0off
;
12200 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12204 /* See if we can do this with a 16-bit instruction. */
12207 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12208 inst
.instruction
|= Rn
;
12209 inst
.instruction
|= Rm
<< 3;
12213 constraint (inst
.operands
[1].shifted
12214 && inst
.operands
[1].immisreg
,
12215 _("shift must be constant"));
12216 if (inst
.instruction
< 0xffff)
12217 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12218 inst
.instruction
|= Rn
<< r0off
;
12219 encode_thumb32_shifted_operand (1);
12225 constraint (inst
.instruction
> 0xffff
12226 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12227 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12228 _("unshifted register required"));
12229 constraint (Rn
> 7 || Rm
> 7,
12232 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12233 inst
.instruction
|= Rn
;
12234 inst
.instruction
|= Rm
<< 3;
12243 if (do_vfp_nsyn_mrs () == SUCCESS
)
12246 Rd
= inst
.operands
[0].reg
;
12247 reject_bad_reg (Rd
);
12248 inst
.instruction
|= Rd
<< 8;
12250 if (inst
.operands
[1].isreg
)
12252 unsigned br
= inst
.operands
[1].reg
;
12253 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12254 as_bad (_("bad register for mrs"));
12256 inst
.instruction
|= br
& (0xf << 16);
12257 inst
.instruction
|= (br
& 0x300) >> 4;
12258 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12262 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12264 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12266 /* PR gas/12698: The constraint is only applied for m_profile.
12267 If the user has specified -march=all, we want to ignore it as
12268 we are building for any CPU type, including non-m variants. */
12269 bfd_boolean m_profile
=
12270 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12271 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12272 "not support requested special purpose register"));
12275 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12277 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12278 _("'APSR', 'CPSR' or 'SPSR' expected"));
12280 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12281 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12282 inst
.instruction
|= 0xf0000;
12292 if (do_vfp_nsyn_msr () == SUCCESS
)
12295 constraint (!inst
.operands
[1].isreg
,
12296 _("Thumb encoding does not support an immediate here"));
12298 if (inst
.operands
[0].isreg
)
12299 flags
= (int)(inst
.operands
[0].reg
);
12301 flags
= inst
.operands
[0].imm
;
12303 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12305 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12307 /* PR gas/12698: The constraint is only applied for m_profile.
12308 If the user has specified -march=all, we want to ignore it as
12309 we are building for any CPU type, including non-m variants. */
12310 bfd_boolean m_profile
=
12311 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12312 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12313 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12314 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12315 && bits
!= PSR_f
)) && m_profile
,
12316 _("selected processor does not support requested special "
12317 "purpose register"));
12320 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12321 "requested special purpose register"));
12323 Rn
= inst
.operands
[1].reg
;
12324 reject_bad_reg (Rn
);
12326 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12327 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12328 inst
.instruction
|= (flags
& 0x300) >> 4;
12329 inst
.instruction
|= (flags
& 0xff);
12330 inst
.instruction
|= Rn
<< 16;
12336 bfd_boolean narrow
;
12337 unsigned Rd
, Rn
, Rm
;
12339 if (!inst
.operands
[2].present
)
12340 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12342 Rd
= inst
.operands
[0].reg
;
12343 Rn
= inst
.operands
[1].reg
;
12344 Rm
= inst
.operands
[2].reg
;
12346 if (unified_syntax
)
12348 if (inst
.size_req
== 4
12354 else if (inst
.instruction
== T_MNEM_muls
)
12355 narrow
= !in_it_block ();
12357 narrow
= in_it_block ();
12361 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12362 constraint (Rn
> 7 || Rm
> 7,
12369 /* 16-bit MULS/Conditional MUL. */
12370 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12371 inst
.instruction
|= Rd
;
12374 inst
.instruction
|= Rm
<< 3;
12376 inst
.instruction
|= Rn
<< 3;
12378 constraint (1, _("dest must overlap one source register"));
12382 constraint (inst
.instruction
!= T_MNEM_mul
,
12383 _("Thumb-2 MUL must not set flags"));
12385 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12386 inst
.instruction
|= Rd
<< 8;
12387 inst
.instruction
|= Rn
<< 16;
12388 inst
.instruction
|= Rm
<< 0;
12390 reject_bad_reg (Rd
);
12391 reject_bad_reg (Rn
);
12392 reject_bad_reg (Rm
);
12399 unsigned RdLo
, RdHi
, Rn
, Rm
;
12401 RdLo
= inst
.operands
[0].reg
;
12402 RdHi
= inst
.operands
[1].reg
;
12403 Rn
= inst
.operands
[2].reg
;
12404 Rm
= inst
.operands
[3].reg
;
12406 reject_bad_reg (RdLo
);
12407 reject_bad_reg (RdHi
);
12408 reject_bad_reg (Rn
);
12409 reject_bad_reg (Rm
);
12411 inst
.instruction
|= RdLo
<< 12;
12412 inst
.instruction
|= RdHi
<< 8;
12413 inst
.instruction
|= Rn
<< 16;
12414 inst
.instruction
|= Rm
;
12417 as_tsktsk (_("rdhi and rdlo must be different"));
12423 set_it_insn_type (NEUTRAL_IT_INSN
);
12425 if (unified_syntax
)
12427 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12429 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12430 inst
.instruction
|= inst
.operands
[0].imm
;
12434 /* PR9722: Check for Thumb2 availability before
12435 generating a thumb2 nop instruction. */
12436 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12438 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12439 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12442 inst
.instruction
= 0x46c0;
12447 constraint (inst
.operands
[0].present
,
12448 _("Thumb does not support NOP with hints"));
12449 inst
.instruction
= 0x46c0;
12456 if (unified_syntax
)
12458 bfd_boolean narrow
;
12460 if (THUMB_SETS_FLAGS (inst
.instruction
))
12461 narrow
= !in_it_block ();
12463 narrow
= in_it_block ();
12464 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12466 if (inst
.size_req
== 4)
12471 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12472 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12473 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12477 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12478 inst
.instruction
|= inst
.operands
[0].reg
;
12479 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12484 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12486 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12488 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12489 inst
.instruction
|= inst
.operands
[0].reg
;
12490 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12499 Rd
= inst
.operands
[0].reg
;
12500 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12502 reject_bad_reg (Rd
);
12503 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12504 reject_bad_reg (Rn
);
12506 inst
.instruction
|= Rd
<< 8;
12507 inst
.instruction
|= Rn
<< 16;
12509 if (!inst
.operands
[2].isreg
)
12511 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12512 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12518 Rm
= inst
.operands
[2].reg
;
12519 reject_bad_reg (Rm
);
12521 constraint (inst
.operands
[2].shifted
12522 && inst
.operands
[2].immisreg
,
12523 _("shift must be constant"));
12524 encode_thumb32_shifted_operand (2);
12531 unsigned Rd
, Rn
, Rm
;
12533 Rd
= inst
.operands
[0].reg
;
12534 Rn
= inst
.operands
[1].reg
;
12535 Rm
= inst
.operands
[2].reg
;
12537 reject_bad_reg (Rd
);
12538 reject_bad_reg (Rn
);
12539 reject_bad_reg (Rm
);
12541 inst
.instruction
|= Rd
<< 8;
12542 inst
.instruction
|= Rn
<< 16;
12543 inst
.instruction
|= Rm
;
12544 if (inst
.operands
[3].present
)
12546 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12547 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12548 _("expression too complex"));
12549 inst
.instruction
|= (val
& 0x1c) << 10;
12550 inst
.instruction
|= (val
& 0x03) << 6;
12557 if (!inst
.operands
[3].present
)
12561 inst
.instruction
&= ~0x00000020;
12563 /* PR 10168. Swap the Rm and Rn registers. */
12564 Rtmp
= inst
.operands
[1].reg
;
12565 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12566 inst
.operands
[2].reg
= Rtmp
;
12574 if (inst
.operands
[0].immisreg
)
12575 reject_bad_reg (inst
.operands
[0].imm
);
12577 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12581 do_t_push_pop (void)
12585 constraint (inst
.operands
[0].writeback
,
12586 _("push/pop do not support {reglist}^"));
12587 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12588 _("expression too complex"));
12590 mask
= inst
.operands
[0].imm
;
12591 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12592 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12593 else if (inst
.size_req
!= 4
12594 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12595 ? REG_LR
: REG_PC
)))
12597 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12598 inst
.instruction
|= THUMB_PP_PC_LR
;
12599 inst
.instruction
|= mask
& 0xff;
12601 else if (unified_syntax
)
12603 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12604 encode_thumb2_ldmstm (13, mask
, TRUE
);
12608 inst
.error
= _("invalid register list to push/pop instruction");
12618 Rd
= inst
.operands
[0].reg
;
12619 Rm
= inst
.operands
[1].reg
;
12621 reject_bad_reg (Rd
);
12622 reject_bad_reg (Rm
);
12624 inst
.instruction
|= Rd
<< 8;
12625 inst
.instruction
|= Rm
<< 16;
12626 inst
.instruction
|= Rm
;
12634 Rd
= inst
.operands
[0].reg
;
12635 Rm
= inst
.operands
[1].reg
;
12637 reject_bad_reg (Rd
);
12638 reject_bad_reg (Rm
);
12640 if (Rd
<= 7 && Rm
<= 7
12641 && inst
.size_req
!= 4)
12643 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12644 inst
.instruction
|= Rd
;
12645 inst
.instruction
|= Rm
<< 3;
12647 else if (unified_syntax
)
12649 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12650 inst
.instruction
|= Rd
<< 8;
12651 inst
.instruction
|= Rm
<< 16;
12652 inst
.instruction
|= Rm
;
12655 inst
.error
= BAD_HIREG
;
12663 Rd
= inst
.operands
[0].reg
;
12664 Rm
= inst
.operands
[1].reg
;
12666 reject_bad_reg (Rd
);
12667 reject_bad_reg (Rm
);
12669 inst
.instruction
|= Rd
<< 8;
12670 inst
.instruction
|= Rm
;
12678 Rd
= inst
.operands
[0].reg
;
12679 Rs
= (inst
.operands
[1].present
12680 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12681 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12683 reject_bad_reg (Rd
);
12684 reject_bad_reg (Rs
);
12685 if (inst
.operands
[2].isreg
)
12686 reject_bad_reg (inst
.operands
[2].reg
);
12688 inst
.instruction
|= Rd
<< 8;
12689 inst
.instruction
|= Rs
<< 16;
12690 if (!inst
.operands
[2].isreg
)
12692 bfd_boolean narrow
;
12694 if ((inst
.instruction
& 0x00100000) != 0)
12695 narrow
= !in_it_block ();
12697 narrow
= in_it_block ();
12699 if (Rd
> 7 || Rs
> 7)
12702 if (inst
.size_req
== 4 || !unified_syntax
)
12705 if (inst
.reloc
.exp
.X_op
!= O_constant
12706 || inst
.reloc
.exp
.X_add_number
!= 0)
12709 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12710 relaxation, but it doesn't seem worth the hassle. */
12713 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12714 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12715 inst
.instruction
|= Rs
<< 3;
12716 inst
.instruction
|= Rd
;
12720 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12721 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12725 encode_thumb32_shifted_operand (2);
12731 if (warn_on_deprecated
12732 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12733 as_tsktsk (_("setend use is deprecated for ARMv8"));
12735 set_it_insn_type (OUTSIDE_IT_INSN
);
12736 if (inst
.operands
[0].imm
)
12737 inst
.instruction
|= 0x8;
12743 if (!inst
.operands
[1].present
)
12744 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12746 if (unified_syntax
)
12748 bfd_boolean narrow
;
12751 switch (inst
.instruction
)
12754 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12756 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12758 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12760 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12764 if (THUMB_SETS_FLAGS (inst
.instruction
))
12765 narrow
= !in_it_block ();
12767 narrow
= in_it_block ();
12768 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12770 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12772 if (inst
.operands
[2].isreg
12773 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12774 || inst
.operands
[2].reg
> 7))
12776 if (inst
.size_req
== 4)
12779 reject_bad_reg (inst
.operands
[0].reg
);
12780 reject_bad_reg (inst
.operands
[1].reg
);
12784 if (inst
.operands
[2].isreg
)
12786 reject_bad_reg (inst
.operands
[2].reg
);
12787 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12788 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12789 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12790 inst
.instruction
|= inst
.operands
[2].reg
;
12792 /* PR 12854: Error on extraneous shifts. */
12793 constraint (inst
.operands
[2].shifted
,
12794 _("extraneous shift as part of operand to shift insn"));
12798 inst
.operands
[1].shifted
= 1;
12799 inst
.operands
[1].shift_kind
= shift_kind
;
12800 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12801 ? T_MNEM_movs
: T_MNEM_mov
);
12802 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12803 encode_thumb32_shifted_operand (1);
12804 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12805 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12810 if (inst
.operands
[2].isreg
)
12812 switch (shift_kind
)
12814 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12815 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12816 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12817 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12821 inst
.instruction
|= inst
.operands
[0].reg
;
12822 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12824 /* PR 12854: Error on extraneous shifts. */
12825 constraint (inst
.operands
[2].shifted
,
12826 _("extraneous shift as part of operand to shift insn"));
12830 switch (shift_kind
)
12832 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12833 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12834 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12837 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12838 inst
.instruction
|= inst
.operands
[0].reg
;
12839 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12845 constraint (inst
.operands
[0].reg
> 7
12846 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12847 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12849 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12851 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12852 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12853 _("source1 and dest must be same register"));
12855 switch (inst
.instruction
)
12857 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12858 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12859 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12860 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12864 inst
.instruction
|= inst
.operands
[0].reg
;
12865 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12867 /* PR 12854: Error on extraneous shifts. */
12868 constraint (inst
.operands
[2].shifted
,
12869 _("extraneous shift as part of operand to shift insn"));
12873 switch (inst
.instruction
)
12875 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12876 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12877 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12878 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12881 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12882 inst
.instruction
|= inst
.operands
[0].reg
;
12883 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12891 unsigned Rd
, Rn
, Rm
;
12893 Rd
= inst
.operands
[0].reg
;
12894 Rn
= inst
.operands
[1].reg
;
12895 Rm
= inst
.operands
[2].reg
;
12897 reject_bad_reg (Rd
);
12898 reject_bad_reg (Rn
);
12899 reject_bad_reg (Rm
);
12901 inst
.instruction
|= Rd
<< 8;
12902 inst
.instruction
|= Rn
<< 16;
12903 inst
.instruction
|= Rm
;
12909 unsigned Rd
, Rn
, Rm
;
12911 Rd
= inst
.operands
[0].reg
;
12912 Rm
= inst
.operands
[1].reg
;
12913 Rn
= inst
.operands
[2].reg
;
12915 reject_bad_reg (Rd
);
12916 reject_bad_reg (Rn
);
12917 reject_bad_reg (Rm
);
12919 inst
.instruction
|= Rd
<< 8;
12920 inst
.instruction
|= Rn
<< 16;
12921 inst
.instruction
|= Rm
;
12927 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12928 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12929 _("SMC is not permitted on this architecture"));
12930 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12931 _("expression too complex"));
12932 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12933 inst
.instruction
|= (value
& 0xf000) >> 12;
12934 inst
.instruction
|= (value
& 0x0ff0);
12935 inst
.instruction
|= (value
& 0x000f) << 16;
12936 /* PR gas/15623: SMC instructions must be last in an IT block. */
12937 set_it_insn_type_last ();
12943 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12945 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12946 inst
.instruction
|= (value
& 0x0fff);
12947 inst
.instruction
|= (value
& 0xf000) << 4;
12951 do_t_ssat_usat (int bias
)
12955 Rd
= inst
.operands
[0].reg
;
12956 Rn
= inst
.operands
[2].reg
;
12958 reject_bad_reg (Rd
);
12959 reject_bad_reg (Rn
);
12961 inst
.instruction
|= Rd
<< 8;
12962 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12963 inst
.instruction
|= Rn
<< 16;
12965 if (inst
.operands
[3].present
)
12967 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12969 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12971 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12972 _("expression too complex"));
12974 if (shift_amount
!= 0)
12976 constraint (shift_amount
> 31,
12977 _("shift expression is too large"));
12979 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12980 inst
.instruction
|= 0x00200000; /* sh bit. */
12982 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12983 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12991 do_t_ssat_usat (1);
12999 Rd
= inst
.operands
[0].reg
;
13000 Rn
= inst
.operands
[2].reg
;
13002 reject_bad_reg (Rd
);
13003 reject_bad_reg (Rn
);
13005 inst
.instruction
|= Rd
<< 8;
13006 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13007 inst
.instruction
|= Rn
<< 16;
13013 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13014 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13015 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13016 || inst
.operands
[2].negative
,
13019 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13021 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13022 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13023 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13024 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13030 if (!inst
.operands
[2].present
)
13031 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13033 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13034 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13035 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13038 inst
.instruction
|= inst
.operands
[0].reg
;
13039 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13040 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13041 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13047 unsigned Rd
, Rn
, Rm
;
13049 Rd
= inst
.operands
[0].reg
;
13050 Rn
= inst
.operands
[1].reg
;
13051 Rm
= inst
.operands
[2].reg
;
13053 reject_bad_reg (Rd
);
13054 reject_bad_reg (Rn
);
13055 reject_bad_reg (Rm
);
13057 inst
.instruction
|= Rd
<< 8;
13058 inst
.instruction
|= Rn
<< 16;
13059 inst
.instruction
|= Rm
;
13060 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13068 Rd
= inst
.operands
[0].reg
;
13069 Rm
= inst
.operands
[1].reg
;
13071 reject_bad_reg (Rd
);
13072 reject_bad_reg (Rm
);
13074 if (inst
.instruction
<= 0xffff
13075 && inst
.size_req
!= 4
13076 && Rd
<= 7 && Rm
<= 7
13077 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13079 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13080 inst
.instruction
|= Rd
;
13081 inst
.instruction
|= Rm
<< 3;
13083 else if (unified_syntax
)
13085 if (inst
.instruction
<= 0xffff)
13086 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13087 inst
.instruction
|= Rd
<< 8;
13088 inst
.instruction
|= Rm
;
13089 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13093 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13094 _("Thumb encoding does not support rotation"));
13095 constraint (1, BAD_HIREG
);
13102 /* We have to do the following check manually as ARM_EXT_OS only applies
13104 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13106 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13107 /* This only applies to the v6m however, not later architectures. */
13108 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13109 as_bad (_("SVC is not permitted on this architecture"));
13110 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13113 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13122 half
= (inst
.instruction
& 0x10) != 0;
13123 set_it_insn_type_last ();
13124 constraint (inst
.operands
[0].immisreg
,
13125 _("instruction requires register index"));
13127 Rn
= inst
.operands
[0].reg
;
13128 Rm
= inst
.operands
[0].imm
;
13130 constraint (Rn
== REG_SP
, BAD_SP
);
13131 reject_bad_reg (Rm
);
13133 constraint (!half
&& inst
.operands
[0].shifted
,
13134 _("instruction does not allow shifted index"));
13135 inst
.instruction
|= (Rn
<< 16) | Rm
;
13141 if (!inst
.operands
[0].present
)
13142 inst
.operands
[0].imm
= 0;
13144 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13146 constraint (inst
.size_req
== 2,
13147 _("immediate value out of range"));
13148 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13149 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13150 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13154 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13155 inst
.instruction
|= inst
.operands
[0].imm
;
13158 set_it_insn_type (NEUTRAL_IT_INSN
);
13165 do_t_ssat_usat (0);
13173 Rd
= inst
.operands
[0].reg
;
13174 Rn
= inst
.operands
[2].reg
;
13176 reject_bad_reg (Rd
);
13177 reject_bad_reg (Rn
);
13179 inst
.instruction
|= Rd
<< 8;
13180 inst
.instruction
|= inst
.operands
[1].imm
;
13181 inst
.instruction
|= Rn
<< 16;
13184 /* Neon instruction encoder helpers. */
13186 /* Encodings for the different types for various Neon opcodes. */
13188 /* An "invalid" code for the following tables. */
13191 struct neon_tab_entry
13194 unsigned float_or_poly
;
13195 unsigned scalar_or_imm
;
13198 /* Map overloaded Neon opcodes to their respective encodings. */
13199 #define NEON_ENC_TAB \
13200 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13201 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13202 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13203 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13204 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13205 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13206 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13207 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13208 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13209 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13210 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13211 /* Register variants of the following two instructions are encoded as
13212 vcge / vcgt with the operands reversed. */ \
13213 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13214 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13215 X(vfma, N_INV, 0x0000c10, N_INV), \
13216 X(vfms, N_INV, 0x0200c10, N_INV), \
13217 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13218 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13219 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13220 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13221 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13222 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13223 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13224 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13225 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13226 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13227 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13228 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13229 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13230 X(vshl, 0x0000400, N_INV, 0x0800510), \
13231 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13232 X(vand, 0x0000110, N_INV, 0x0800030), \
13233 X(vbic, 0x0100110, N_INV, 0x0800030), \
13234 X(veor, 0x1000110, N_INV, N_INV), \
13235 X(vorn, 0x0300110, N_INV, 0x0800010), \
13236 X(vorr, 0x0200110, N_INV, 0x0800010), \
13237 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13238 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13239 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13240 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13241 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13242 X(vst1, 0x0000000, 0x0800000, N_INV), \
13243 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13244 X(vst2, 0x0000100, 0x0800100, N_INV), \
13245 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13246 X(vst3, 0x0000200, 0x0800200, N_INV), \
13247 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13248 X(vst4, 0x0000300, 0x0800300, N_INV), \
13249 X(vmovn, 0x1b20200, N_INV, N_INV), \
13250 X(vtrn, 0x1b20080, N_INV, N_INV), \
13251 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13252 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13253 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13254 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13255 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13256 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13257 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13258 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13259 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13260 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13261 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13262 X(vseleq, 0xe000a00, N_INV, N_INV), \
13263 X(vselvs, 0xe100a00, N_INV, N_INV), \
13264 X(vselge, 0xe200a00, N_INV, N_INV), \
13265 X(vselgt, 0xe300a00, N_INV, N_INV), \
13266 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13267 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13268 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13269 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13270 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13271 X(aes, 0x3b00300, N_INV, N_INV), \
13272 X(sha3op, 0x2000c00, N_INV, N_INV), \
13273 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13274 X(sha2op, 0x3ba0380, N_INV, N_INV)
13278 #define X(OPC,I,F,S) N_MNEM_##OPC
13283 static const struct neon_tab_entry neon_enc_tab
[] =
13285 #define X(OPC,I,F,S) { (I), (F), (S) }
13290 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13291 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13292 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13293 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13294 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13295 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13296 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13297 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13298 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13299 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13300 #define NEON_ENC_SINGLE_(X) \
13301 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13302 #define NEON_ENC_DOUBLE_(X) \
13303 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13304 #define NEON_ENC_FPV8_(X) \
13305 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13307 #define NEON_ENCODE(type, inst) \
13310 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13311 inst.is_neon = 1; \
13315 #define check_neon_suffixes \
13318 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13320 as_bad (_("invalid neon suffix for non neon instruction")); \
13326 /* Define shapes for instruction operands. The following mnemonic characters
13327 are used in this table:
13329 F - VFP S<n> register
13330 D - Neon D<n> register
13331 Q - Neon Q<n> register
13335 L - D<n> register list
13337 This table is used to generate various data:
13338 - enumerations of the form NS_DDR to be used as arguments to
13340 - a table classifying shapes into single, double, quad, mixed.
13341 - a table used to drive neon_select_shape. */
13343 #define NEON_SHAPE_DEF \
13344 X(3, (D, D, D), DOUBLE), \
13345 X(3, (Q, Q, Q), QUAD), \
13346 X(3, (D, D, I), DOUBLE), \
13347 X(3, (Q, Q, I), QUAD), \
13348 X(3, (D, D, S), DOUBLE), \
13349 X(3, (Q, Q, S), QUAD), \
13350 X(2, (D, D), DOUBLE), \
13351 X(2, (Q, Q), QUAD), \
13352 X(2, (D, S), DOUBLE), \
13353 X(2, (Q, S), QUAD), \
13354 X(2, (D, R), DOUBLE), \
13355 X(2, (Q, R), QUAD), \
13356 X(2, (D, I), DOUBLE), \
13357 X(2, (Q, I), QUAD), \
13358 X(3, (D, L, D), DOUBLE), \
13359 X(2, (D, Q), MIXED), \
13360 X(2, (Q, D), MIXED), \
13361 X(3, (D, Q, I), MIXED), \
13362 X(3, (Q, D, I), MIXED), \
13363 X(3, (Q, D, D), MIXED), \
13364 X(3, (D, Q, Q), MIXED), \
13365 X(3, (Q, Q, D), MIXED), \
13366 X(3, (Q, D, S), MIXED), \
13367 X(3, (D, Q, S), MIXED), \
13368 X(4, (D, D, D, I), DOUBLE), \
13369 X(4, (Q, Q, Q, I), QUAD), \
13370 X(4, (D, D, S, I), DOUBLE), \
13371 X(4, (Q, Q, S, I), QUAD), \
13372 X(2, (F, F), SINGLE), \
13373 X(3, (F, F, F), SINGLE), \
13374 X(2, (F, I), SINGLE), \
13375 X(2, (F, D), MIXED), \
13376 X(2, (D, F), MIXED), \
13377 X(3, (F, F, I), MIXED), \
13378 X(4, (R, R, F, F), SINGLE), \
13379 X(4, (F, F, R, R), SINGLE), \
13380 X(3, (D, R, R), DOUBLE), \
13381 X(3, (R, R, D), DOUBLE), \
13382 X(2, (S, R), SINGLE), \
13383 X(2, (R, S), SINGLE), \
13384 X(2, (F, R), SINGLE), \
13385 X(2, (R, F), SINGLE), \
13386 /* Half float shape supported so far. */\
13387 X (2, (H, D), MIXED), \
13388 X (2, (D, H), MIXED), \
13389 X (2, (H, F), MIXED), \
13390 X (2, (F, H), MIXED), \
13391 X (2, (H, H), HALF), \
13392 X (2, (H, R), HALF), \
13393 X (2, (R, H), HALF), \
13394 X (2, (H, I), HALF), \
13395 X (3, (H, H, H), HALF), \
13396 X (3, (H, F, I), MIXED), \
13397 X (3, (F, H, I), MIXED)
13399 #define S2(A,B) NS_##A##B
13400 #define S3(A,B,C) NS_##A##B##C
13401 #define S4(A,B,C,D) NS_##A##B##C##D
13403 #define X(N, L, C) S##N L
13416 enum neon_shape_class
13425 #define X(N, L, C) SC_##C
13427 static enum neon_shape_class neon_shape_class
[] =
13446 /* Register widths of above. */
13447 static unsigned neon_shape_el_size
[] =
13459 struct neon_shape_info
13462 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13465 #define S2(A,B) { SE_##A, SE_##B }
13466 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13467 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13469 #define X(N, L, C) { N, S##N L }
13471 static struct neon_shape_info neon_shape_tab
[] =
13481 /* Bit masks used in type checking given instructions.
13482 'N_EQK' means the type must be the same as (or based on in some way) the key
13483 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13484 set, various other bits can be set as well in order to modify the meaning of
13485 the type constraint. */
13487 enum neon_type_mask
13511 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13512 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13513 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13514 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13515 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13516 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13517 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13518 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13519 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13520 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13521 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13523 N_MAX_NONSPECIAL
= N_P64
13526 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13528 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13529 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13530 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13531 #define N_S_32 (N_S8 | N_S16 | N_S32)
13532 #define N_F_16_32 (N_F16 | N_F32)
13533 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13534 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13535 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13536 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13538 /* Pass this as the first type argument to neon_check_type to ignore types
13540 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13542 /* Select a "shape" for the current instruction (describing register types or
13543 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13544 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13545 function of operand parsing, so this function doesn't need to be called.
13546 Shapes should be listed in order of decreasing length. */
13548 static enum neon_shape
13549 neon_select_shape (enum neon_shape shape
, ...)
13552 enum neon_shape first_shape
= shape
;
13554 /* Fix missing optional operands. FIXME: we don't know at this point how
13555 many arguments we should have, so this makes the assumption that we have
13556 > 1. This is true of all current Neon opcodes, I think, but may not be
13557 true in the future. */
13558 if (!inst
.operands
[1].present
)
13559 inst
.operands
[1] = inst
.operands
[0];
13561 va_start (ap
, shape
);
13563 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13568 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13570 if (!inst
.operands
[j
].present
)
13576 switch (neon_shape_tab
[shape
].el
[j
])
13578 /* If a .f16, .16, .u16, .s16 type specifier is given over
13579 a VFP single precision register operand, it's essentially
13580 means only half of the register is used.
13582 If the type specifier is given after the mnemonics, the
13583 information is stored in inst.vectype. If the type specifier
13584 is given after register operand, the information is stored
13585 in inst.operands[].vectype.
13587 When there is only one type specifier, and all the register
13588 operands are the same type of hardware register, the type
13589 specifier applies to all register operands.
13591 If no type specifier is given, the shape is inferred from
13592 operand information.
13595 vadd.f16 s0, s1, s2: NS_HHH
13596 vabs.f16 s0, s1: NS_HH
13597 vmov.f16 s0, r1: NS_HR
13598 vmov.f16 r0, s1: NS_RH
13599 vcvt.f16 r0, s1: NS_RH
13600 vcvt.f16.s32 s2, s2, #29: NS_HFI
13601 vcvt.f16.s32 s2, s2: NS_HF
13604 if (!(inst
.operands
[j
].isreg
13605 && inst
.operands
[j
].isvec
13606 && inst
.operands
[j
].issingle
13607 && !inst
.operands
[j
].isquad
13608 && ((inst
.vectype
.elems
== 1
13609 && inst
.vectype
.el
[0].size
== 16)
13610 || (inst
.vectype
.elems
> 1
13611 && inst
.vectype
.el
[j
].size
== 16)
13612 || (inst
.vectype
.elems
== 0
13613 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13614 && inst
.operands
[j
].vectype
.size
== 16))))
13619 if (!(inst
.operands
[j
].isreg
13620 && inst
.operands
[j
].isvec
13621 && inst
.operands
[j
].issingle
13622 && !inst
.operands
[j
].isquad
13623 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13624 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13625 || (inst
.vectype
.elems
== 0
13626 && (inst
.operands
[j
].vectype
.size
== 32
13627 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13632 if (!(inst
.operands
[j
].isreg
13633 && inst
.operands
[j
].isvec
13634 && !inst
.operands
[j
].isquad
13635 && !inst
.operands
[j
].issingle
))
13640 if (!(inst
.operands
[j
].isreg
13641 && !inst
.operands
[j
].isvec
))
13646 if (!(inst
.operands
[j
].isreg
13647 && inst
.operands
[j
].isvec
13648 && inst
.operands
[j
].isquad
13649 && !inst
.operands
[j
].issingle
))
13654 if (!(!inst
.operands
[j
].isreg
13655 && !inst
.operands
[j
].isscalar
))
13660 if (!(!inst
.operands
[j
].isreg
13661 && inst
.operands
[j
].isscalar
))
13671 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13672 /* We've matched all the entries in the shape table, and we don't
13673 have any left over operands which have not been matched. */
13679 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13680 first_error (_("invalid instruction shape"));
13685 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13686 means the Q bit should be set). */
13689 neon_quad (enum neon_shape shape
)
13691 return neon_shape_class
[shape
] == SC_QUAD
;
13695 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13698 /* Allow modification to be made to types which are constrained to be
13699 based on the key element, based on bits set alongside N_EQK. */
13700 if ((typebits
& N_EQK
) != 0)
13702 if ((typebits
& N_HLF
) != 0)
13704 else if ((typebits
& N_DBL
) != 0)
13706 if ((typebits
& N_SGN
) != 0)
13707 *g_type
= NT_signed
;
13708 else if ((typebits
& N_UNS
) != 0)
13709 *g_type
= NT_unsigned
;
13710 else if ((typebits
& N_INT
) != 0)
13711 *g_type
= NT_integer
;
13712 else if ((typebits
& N_FLT
) != 0)
13713 *g_type
= NT_float
;
13714 else if ((typebits
& N_SIZ
) != 0)
13715 *g_type
= NT_untyped
;
13719 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13720 operand type, i.e. the single type specified in a Neon instruction when it
13721 is the only one given. */
13723 static struct neon_type_el
13724 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13726 struct neon_type_el dest
= *key
;
13728 gas_assert ((thisarg
& N_EQK
) != 0);
13730 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13735 /* Convert Neon type and size into compact bitmask representation. */
13737 static enum neon_type_mask
13738 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13745 case 8: return N_8
;
13746 case 16: return N_16
;
13747 case 32: return N_32
;
13748 case 64: return N_64
;
13756 case 8: return N_I8
;
13757 case 16: return N_I16
;
13758 case 32: return N_I32
;
13759 case 64: return N_I64
;
13767 case 16: return N_F16
;
13768 case 32: return N_F32
;
13769 case 64: return N_F64
;
13777 case 8: return N_P8
;
13778 case 16: return N_P16
;
13779 case 64: return N_P64
;
13787 case 8: return N_S8
;
13788 case 16: return N_S16
;
13789 case 32: return N_S32
;
13790 case 64: return N_S64
;
13798 case 8: return N_U8
;
13799 case 16: return N_U16
;
13800 case 32: return N_U32
;
13801 case 64: return N_U64
;
13812 /* Convert compact Neon bitmask type representation to a type and size. Only
13813 handles the case where a single bit is set in the mask. */
13816 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13817 enum neon_type_mask mask
)
13819 if ((mask
& N_EQK
) != 0)
13822 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13824 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13826 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13828 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13833 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13835 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13836 *type
= NT_unsigned
;
13837 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13838 *type
= NT_integer
;
13839 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13840 *type
= NT_untyped
;
13841 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13843 else if ((mask
& (N_F_ALL
)) != 0)
13851 /* Modify a bitmask of allowed types. This is only needed for type
13855 modify_types_allowed (unsigned allowed
, unsigned mods
)
13858 enum neon_el_type type
;
13864 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13866 if (el_type_of_type_chk (&type
, &size
,
13867 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13869 neon_modify_type_size (mods
, &type
, &size
);
13870 destmask
|= type_chk_of_el_type (type
, size
);
13877 /* Check type and return type classification.
13878 The manual states (paraphrase): If one datatype is given, it indicates the
13880 - the second operand, if there is one
13881 - the operand, if there is no second operand
13882 - the result, if there are no operands.
13883 This isn't quite good enough though, so we use a concept of a "key" datatype
13884 which is set on a per-instruction basis, which is the one which matters when
13885 only one data type is written.
13886 Note: this function has side-effects (e.g. filling in missing operands). All
13887 Neon instructions should call it before performing bit encoding. */
13889 static struct neon_type_el
13890 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13893 unsigned i
, pass
, key_el
= 0;
13894 unsigned types
[NEON_MAX_TYPE_ELS
];
13895 enum neon_el_type k_type
= NT_invtype
;
13896 unsigned k_size
= -1u;
13897 struct neon_type_el badtype
= {NT_invtype
, -1};
13898 unsigned key_allowed
= 0;
13900 /* Optional registers in Neon instructions are always (not) in operand 1.
13901 Fill in the missing operand here, if it was omitted. */
13902 if (els
> 1 && !inst
.operands
[1].present
)
13903 inst
.operands
[1] = inst
.operands
[0];
13905 /* Suck up all the varargs. */
13907 for (i
= 0; i
< els
; i
++)
13909 unsigned thisarg
= va_arg (ap
, unsigned);
13910 if (thisarg
== N_IGNORE_TYPE
)
13915 types
[i
] = thisarg
;
13916 if ((thisarg
& N_KEY
) != 0)
13921 if (inst
.vectype
.elems
> 0)
13922 for (i
= 0; i
< els
; i
++)
13923 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13925 first_error (_("types specified in both the mnemonic and operands"));
13929 /* Duplicate inst.vectype elements here as necessary.
13930 FIXME: No idea if this is exactly the same as the ARM assembler,
13931 particularly when an insn takes one register and one non-register
13933 if (inst
.vectype
.elems
== 1 && els
> 1)
13936 inst
.vectype
.elems
= els
;
13937 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13938 for (j
= 0; j
< els
; j
++)
13940 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13943 else if (inst
.vectype
.elems
== 0 && els
> 0)
13946 /* No types were given after the mnemonic, so look for types specified
13947 after each operand. We allow some flexibility here; as long as the
13948 "key" operand has a type, we can infer the others. */
13949 for (j
= 0; j
< els
; j
++)
13950 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13951 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13953 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13955 for (j
= 0; j
< els
; j
++)
13956 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13957 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13962 first_error (_("operand types can't be inferred"));
13966 else if (inst
.vectype
.elems
!= els
)
13968 first_error (_("type specifier has the wrong number of parts"));
13972 for (pass
= 0; pass
< 2; pass
++)
13974 for (i
= 0; i
< els
; i
++)
13976 unsigned thisarg
= types
[i
];
13977 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13978 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13979 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13980 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13982 /* Decay more-specific signed & unsigned types to sign-insensitive
13983 integer types if sign-specific variants are unavailable. */
13984 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13985 && (types_allowed
& N_SU_ALL
) == 0)
13986 g_type
= NT_integer
;
13988 /* If only untyped args are allowed, decay any more specific types to
13989 them. Some instructions only care about signs for some element
13990 sizes, so handle that properly. */
13991 if (((types_allowed
& N_UNT
) == 0)
13992 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13993 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13994 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13995 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13996 g_type
= NT_untyped
;
14000 if ((thisarg
& N_KEY
) != 0)
14004 key_allowed
= thisarg
& ~N_KEY
;
14006 /* Check architecture constraint on FP16 extension. */
14008 && k_type
== NT_float
14009 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14011 inst
.error
= _(BAD_FP16
);
14018 if ((thisarg
& N_VFP
) != 0)
14020 enum neon_shape_el regshape
;
14021 unsigned regwidth
, match
;
14023 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14026 first_error (_("invalid instruction shape"));
14029 regshape
= neon_shape_tab
[ns
].el
[i
];
14030 regwidth
= neon_shape_el_size
[regshape
];
14032 /* In VFP mode, operands must match register widths. If we
14033 have a key operand, use its width, else use the width of
14034 the current operand. */
14040 /* FP16 will use a single precision register. */
14041 if (regwidth
== 32 && match
== 16)
14043 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14047 inst
.error
= _(BAD_FP16
);
14052 if (regwidth
!= match
)
14054 first_error (_("operand size must match register width"));
14059 if ((thisarg
& N_EQK
) == 0)
14061 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14063 if ((given_type
& types_allowed
) == 0)
14065 first_error (_("bad type in Neon instruction"));
14071 enum neon_el_type mod_k_type
= k_type
;
14072 unsigned mod_k_size
= k_size
;
14073 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14074 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14076 first_error (_("inconsistent types in Neon instruction"));
14084 return inst
.vectype
.el
[key_el
];
14087 /* Neon-style VFP instruction forwarding. */
14089 /* Thumb VFP instructions have 0xE in the condition field. */
14092 do_vfp_cond_or_thumb (void)
14097 inst
.instruction
|= 0xe0000000;
14099 inst
.instruction
|= inst
.cond
<< 28;
14102 /* Look up and encode a simple mnemonic, for use as a helper function for the
14103 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14104 etc. It is assumed that operand parsing has already been done, and that the
14105 operands are in the form expected by the given opcode (this isn't necessarily
14106 the same as the form in which they were parsed, hence some massaging must
14107 take place before this function is called).
14108 Checks current arch version against that in the looked-up opcode. */
14111 do_vfp_nsyn_opcode (const char *opname
)
14113 const struct asm_opcode
*opcode
;
14115 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14120 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14121 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14128 inst
.instruction
= opcode
->tvalue
;
14129 opcode
->tencode ();
14133 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14134 opcode
->aencode ();
14139 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14141 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14143 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14146 do_vfp_nsyn_opcode ("fadds");
14148 do_vfp_nsyn_opcode ("fsubs");
14150 /* ARMv8.2 fp16 instruction. */
14152 do_scalar_fp16_v82_encode ();
14157 do_vfp_nsyn_opcode ("faddd");
14159 do_vfp_nsyn_opcode ("fsubd");
14163 /* Check operand types to see if this is a VFP instruction, and if so call
14167 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14169 enum neon_shape rs
;
14170 struct neon_type_el et
;
14175 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14176 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14180 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14181 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14182 N_F_ALL
| N_KEY
| N_VFP
);
14189 if (et
.type
!= NT_invtype
)
14200 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14202 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14204 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14207 do_vfp_nsyn_opcode ("fmacs");
14209 do_vfp_nsyn_opcode ("fnmacs");
14211 /* ARMv8.2 fp16 instruction. */
14213 do_scalar_fp16_v82_encode ();
14218 do_vfp_nsyn_opcode ("fmacd");
14220 do_vfp_nsyn_opcode ("fnmacd");
14225 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14227 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14229 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14232 do_vfp_nsyn_opcode ("ffmas");
14234 do_vfp_nsyn_opcode ("ffnmas");
14236 /* ARMv8.2 fp16 instruction. */
14238 do_scalar_fp16_v82_encode ();
14243 do_vfp_nsyn_opcode ("ffmad");
14245 do_vfp_nsyn_opcode ("ffnmad");
14250 do_vfp_nsyn_mul (enum neon_shape rs
)
14252 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14254 do_vfp_nsyn_opcode ("fmuls");
14256 /* ARMv8.2 fp16 instruction. */
14258 do_scalar_fp16_v82_encode ();
14261 do_vfp_nsyn_opcode ("fmuld");
14265 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14267 int is_neg
= (inst
.instruction
& 0x80) != 0;
14268 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14270 if (rs
== NS_FF
|| rs
== NS_HH
)
14273 do_vfp_nsyn_opcode ("fnegs");
14275 do_vfp_nsyn_opcode ("fabss");
14277 /* ARMv8.2 fp16 instruction. */
14279 do_scalar_fp16_v82_encode ();
14284 do_vfp_nsyn_opcode ("fnegd");
14286 do_vfp_nsyn_opcode ("fabsd");
14290 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14291 insns belong to Neon, and are handled elsewhere. */
14294 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14296 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14300 do_vfp_nsyn_opcode ("fldmdbs");
14302 do_vfp_nsyn_opcode ("fldmias");
14307 do_vfp_nsyn_opcode ("fstmdbs");
14309 do_vfp_nsyn_opcode ("fstmias");
14314 do_vfp_nsyn_sqrt (void)
14316 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14317 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14319 if (rs
== NS_FF
|| rs
== NS_HH
)
14321 do_vfp_nsyn_opcode ("fsqrts");
14323 /* ARMv8.2 fp16 instruction. */
14325 do_scalar_fp16_v82_encode ();
14328 do_vfp_nsyn_opcode ("fsqrtd");
14332 do_vfp_nsyn_div (void)
14334 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14335 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14336 N_F_ALL
| N_KEY
| N_VFP
);
14338 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14340 do_vfp_nsyn_opcode ("fdivs");
14342 /* ARMv8.2 fp16 instruction. */
14344 do_scalar_fp16_v82_encode ();
14347 do_vfp_nsyn_opcode ("fdivd");
14351 do_vfp_nsyn_nmul (void)
14353 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14354 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14355 N_F_ALL
| N_KEY
| N_VFP
);
14357 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14359 NEON_ENCODE (SINGLE
, inst
);
14360 do_vfp_sp_dyadic ();
14362 /* ARMv8.2 fp16 instruction. */
14364 do_scalar_fp16_v82_encode ();
14368 NEON_ENCODE (DOUBLE
, inst
);
14369 do_vfp_dp_rd_rn_rm ();
14371 do_vfp_cond_or_thumb ();
14376 do_vfp_nsyn_cmp (void)
14378 enum neon_shape rs
;
14379 if (inst
.operands
[1].isreg
)
14381 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14382 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14384 if (rs
== NS_FF
|| rs
== NS_HH
)
14386 NEON_ENCODE (SINGLE
, inst
);
14387 do_vfp_sp_monadic ();
14391 NEON_ENCODE (DOUBLE
, inst
);
14392 do_vfp_dp_rd_rm ();
14397 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14398 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14400 switch (inst
.instruction
& 0x0fffffff)
14403 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14406 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14412 if (rs
== NS_FI
|| rs
== NS_HI
)
14414 NEON_ENCODE (SINGLE
, inst
);
14415 do_vfp_sp_compare_z ();
14419 NEON_ENCODE (DOUBLE
, inst
);
14423 do_vfp_cond_or_thumb ();
14425 /* ARMv8.2 fp16 instruction. */
14426 if (rs
== NS_HI
|| rs
== NS_HH
)
14427 do_scalar_fp16_v82_encode ();
14431 nsyn_insert_sp (void)
14433 inst
.operands
[1] = inst
.operands
[0];
14434 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14435 inst
.operands
[0].reg
= REG_SP
;
14436 inst
.operands
[0].isreg
= 1;
14437 inst
.operands
[0].writeback
= 1;
14438 inst
.operands
[0].present
= 1;
14442 do_vfp_nsyn_push (void)
14446 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14447 _("register list must contain at least 1 and at most 16 "
14450 if (inst
.operands
[1].issingle
)
14451 do_vfp_nsyn_opcode ("fstmdbs");
14453 do_vfp_nsyn_opcode ("fstmdbd");
14457 do_vfp_nsyn_pop (void)
14461 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14462 _("register list must contain at least 1 and at most 16 "
14465 if (inst
.operands
[1].issingle
)
14466 do_vfp_nsyn_opcode ("fldmias");
14468 do_vfp_nsyn_opcode ("fldmiad");
14471 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14472 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14475 neon_dp_fixup (struct arm_it
* insn
)
14477 unsigned int i
= insn
->instruction
;
14482 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14493 insn
->instruction
= i
;
14496 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14500 neon_logbits (unsigned x
)
14502 return ffs (x
) - 4;
14505 #define LOW4(R) ((R) & 0xf)
14506 #define HI1(R) (((R) >> 4) & 1)
14508 /* Encode insns with bit pattern:
14510 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14511 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14513 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14514 different meaning for some instruction. */
14517 neon_three_same (int isquad
, int ubit
, int size
)
14519 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14520 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14521 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14522 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14523 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14524 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14525 inst
.instruction
|= (isquad
!= 0) << 6;
14526 inst
.instruction
|= (ubit
!= 0) << 24;
14528 inst
.instruction
|= neon_logbits (size
) << 20;
14530 neon_dp_fixup (&inst
);
14533 /* Encode instructions of the form:
14535 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14536 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14538 Don't write size if SIZE == -1. */
14541 neon_two_same (int qbit
, int ubit
, int size
)
14543 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14544 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14545 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14546 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14547 inst
.instruction
|= (qbit
!= 0) << 6;
14548 inst
.instruction
|= (ubit
!= 0) << 24;
14551 inst
.instruction
|= neon_logbits (size
) << 18;
14553 neon_dp_fixup (&inst
);
14556 /* Neon instruction encoders, in approximate order of appearance. */
14559 do_neon_dyadic_i_su (void)
14561 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14562 struct neon_type_el et
= neon_check_type (3, rs
,
14563 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14564 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14568 do_neon_dyadic_i64_su (void)
14570 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14571 struct neon_type_el et
= neon_check_type (3, rs
,
14572 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14573 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14577 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14580 unsigned size
= et
.size
>> 3;
14581 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14582 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14583 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14584 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14585 inst
.instruction
|= (isquad
!= 0) << 6;
14586 inst
.instruction
|= immbits
<< 16;
14587 inst
.instruction
|= (size
>> 3) << 7;
14588 inst
.instruction
|= (size
& 0x7) << 19;
14590 inst
.instruction
|= (uval
!= 0) << 24;
14592 neon_dp_fixup (&inst
);
14596 do_neon_shl_imm (void)
14598 if (!inst
.operands
[2].isreg
)
14600 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14601 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14602 int imm
= inst
.operands
[2].imm
;
14604 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14605 _("immediate out of range for shift"));
14606 NEON_ENCODE (IMMED
, inst
);
14607 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14611 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14612 struct neon_type_el et
= neon_check_type (3, rs
,
14613 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14616 /* VSHL/VQSHL 3-register variants have syntax such as:
14618 whereas other 3-register operations encoded by neon_three_same have
14621 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14623 tmp
= inst
.operands
[2].reg
;
14624 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14625 inst
.operands
[1].reg
= tmp
;
14626 NEON_ENCODE (INTEGER
, inst
);
14627 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14632 do_neon_qshl_imm (void)
14634 if (!inst
.operands
[2].isreg
)
14636 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14637 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14638 int imm
= inst
.operands
[2].imm
;
14640 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14641 _("immediate out of range for shift"));
14642 NEON_ENCODE (IMMED
, inst
);
14643 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14647 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14648 struct neon_type_el et
= neon_check_type (3, rs
,
14649 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14652 /* See note in do_neon_shl_imm. */
14653 tmp
= inst
.operands
[2].reg
;
14654 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14655 inst
.operands
[1].reg
= tmp
;
14656 NEON_ENCODE (INTEGER
, inst
);
14657 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14662 do_neon_rshl (void)
14664 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14665 struct neon_type_el et
= neon_check_type (3, rs
,
14666 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14669 tmp
= inst
.operands
[2].reg
;
14670 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14671 inst
.operands
[1].reg
= tmp
;
14672 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14676 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14678 /* Handle .I8 pseudo-instructions. */
14681 /* Unfortunately, this will make everything apart from zero out-of-range.
14682 FIXME is this the intended semantics? There doesn't seem much point in
14683 accepting .I8 if so. */
14684 immediate
|= immediate
<< 8;
14690 if (immediate
== (immediate
& 0x000000ff))
14692 *immbits
= immediate
;
14695 else if (immediate
== (immediate
& 0x0000ff00))
14697 *immbits
= immediate
>> 8;
14700 else if (immediate
== (immediate
& 0x00ff0000))
14702 *immbits
= immediate
>> 16;
14705 else if (immediate
== (immediate
& 0xff000000))
14707 *immbits
= immediate
>> 24;
14710 if ((immediate
& 0xffff) != (immediate
>> 16))
14711 goto bad_immediate
;
14712 immediate
&= 0xffff;
14715 if (immediate
== (immediate
& 0x000000ff))
14717 *immbits
= immediate
;
14720 else if (immediate
== (immediate
& 0x0000ff00))
14722 *immbits
= immediate
>> 8;
14727 first_error (_("immediate value out of range"));
14732 do_neon_logic (void)
14734 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14736 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14737 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14738 /* U bit and size field were set as part of the bitmask. */
14739 NEON_ENCODE (INTEGER
, inst
);
14740 neon_three_same (neon_quad (rs
), 0, -1);
14744 const int three_ops_form
= (inst
.operands
[2].present
14745 && !inst
.operands
[2].isreg
);
14746 const int immoperand
= (three_ops_form
? 2 : 1);
14747 enum neon_shape rs
= (three_ops_form
14748 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14749 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14750 struct neon_type_el et
= neon_check_type (2, rs
,
14751 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14752 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14756 if (et
.type
== NT_invtype
)
14759 if (three_ops_form
)
14760 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14761 _("first and second operands shall be the same register"));
14763 NEON_ENCODE (IMMED
, inst
);
14765 immbits
= inst
.operands
[immoperand
].imm
;
14768 /* .i64 is a pseudo-op, so the immediate must be a repeating
14770 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14771 inst
.operands
[immoperand
].reg
: 0))
14773 /* Set immbits to an invalid constant. */
14774 immbits
= 0xdeadbeef;
14781 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14785 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14789 /* Pseudo-instruction for VBIC. */
14790 neon_invert_size (&immbits
, 0, et
.size
);
14791 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14795 /* Pseudo-instruction for VORR. */
14796 neon_invert_size (&immbits
, 0, et
.size
);
14797 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14807 inst
.instruction
|= neon_quad (rs
) << 6;
14808 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14809 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14810 inst
.instruction
|= cmode
<< 8;
14811 neon_write_immbits (immbits
);
14813 neon_dp_fixup (&inst
);
14818 do_neon_bitfield (void)
14820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14821 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14822 neon_three_same (neon_quad (rs
), 0, -1);
14826 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14829 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14830 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14832 if (et
.type
== NT_float
)
14834 NEON_ENCODE (FLOAT
, inst
);
14835 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14839 NEON_ENCODE (INTEGER
, inst
);
14840 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14845 do_neon_dyadic_if_su (void)
14847 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14851 do_neon_dyadic_if_su_d (void)
14853 /* This version only allow D registers, but that constraint is enforced during
14854 operand parsing so we don't need to do anything extra here. */
14855 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14859 do_neon_dyadic_if_i_d (void)
14861 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14862 affected if we specify unsigned args. */
14863 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14866 enum vfp_or_neon_is_neon_bits
14869 NEON_CHECK_ARCH
= 2,
14870 NEON_CHECK_ARCH8
= 4
14873 /* Call this function if an instruction which may have belonged to the VFP or
14874 Neon instruction sets, but turned out to be a Neon instruction (due to the
14875 operand types involved, etc.). We have to check and/or fix-up a couple of
14878 - Make sure the user hasn't attempted to make a Neon instruction
14880 - Alter the value in the condition code field if necessary.
14881 - Make sure that the arch supports Neon instructions.
14883 Which of these operations take place depends on bits from enum
14884 vfp_or_neon_is_neon_bits.
14886 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14887 current instruction's condition is COND_ALWAYS, the condition field is
14888 changed to inst.uncond_value. This is necessary because instructions shared
14889 between VFP and Neon may be conditional for the VFP variants only, and the
14890 unconditional Neon version must have, e.g., 0xF in the condition field. */
14893 vfp_or_neon_is_neon (unsigned check
)
14895 /* Conditions are always legal in Thumb mode (IT blocks). */
14896 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14898 if (inst
.cond
!= COND_ALWAYS
)
14900 first_error (_(BAD_COND
));
14903 if (inst
.uncond_value
!= -1)
14904 inst
.instruction
|= inst
.uncond_value
<< 28;
14907 if ((check
& NEON_CHECK_ARCH
)
14908 && !mark_feature_used (&fpu_neon_ext_v1
))
14910 first_error (_(BAD_FPU
));
14914 if ((check
& NEON_CHECK_ARCH8
)
14915 && !mark_feature_used (&fpu_neon_ext_armv8
))
14917 first_error (_(BAD_FPU
));
14925 do_neon_addsub_if_i (void)
14927 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14930 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14933 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14934 affected if we specify unsigned args. */
14935 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14938 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14940 V<op> A,B (A is operand 0, B is operand 2)
14945 so handle that case specially. */
14948 neon_exchange_operands (void)
14950 if (inst
.operands
[1].present
)
14952 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14954 /* Swap operands[1] and operands[2]. */
14955 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14956 inst
.operands
[1] = inst
.operands
[2];
14957 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14962 inst
.operands
[1] = inst
.operands
[2];
14963 inst
.operands
[2] = inst
.operands
[0];
14968 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14970 if (inst
.operands
[2].isreg
)
14973 neon_exchange_operands ();
14974 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14978 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14979 struct neon_type_el et
= neon_check_type (2, rs
,
14980 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14982 NEON_ENCODE (IMMED
, inst
);
14983 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14984 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14985 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14986 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14987 inst
.instruction
|= neon_quad (rs
) << 6;
14988 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14989 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14991 neon_dp_fixup (&inst
);
14998 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15002 do_neon_cmp_inv (void)
15004 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15010 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15013 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15014 scalars, which are encoded in 5 bits, M : Rm.
15015 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15016 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15020 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15022 unsigned regno
= NEON_SCALAR_REG (scalar
);
15023 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15028 if (regno
> 7 || elno
> 3)
15030 return regno
| (elno
<< 3);
15033 if (regno
> 15 || elno
> 1)
15035 return regno
| (elno
<< 4);
15039 first_error (_("scalar out of range for multiply instruction"));
15045 /* Encode multiply / multiply-accumulate scalar instructions. */
15048 neon_mul_mac (struct neon_type_el et
, int ubit
)
15052 /* Give a more helpful error message if we have an invalid type. */
15053 if (et
.type
== NT_invtype
)
15056 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15057 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15061 inst
.instruction
|= LOW4 (scalar
);
15062 inst
.instruction
|= HI1 (scalar
) << 5;
15063 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15064 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15065 inst
.instruction
|= (ubit
!= 0) << 24;
15067 neon_dp_fixup (&inst
);
15071 do_neon_mac_maybe_scalar (void)
15073 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15076 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15079 if (inst
.operands
[2].isscalar
)
15081 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15082 struct neon_type_el et
= neon_check_type (3, rs
,
15083 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15084 NEON_ENCODE (SCALAR
, inst
);
15085 neon_mul_mac (et
, neon_quad (rs
));
15089 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15090 affected if we specify unsigned args. */
15091 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15096 do_neon_fmac (void)
15098 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15101 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15104 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15110 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15111 struct neon_type_el et
= neon_check_type (3, rs
,
15112 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15113 neon_three_same (neon_quad (rs
), 0, et
.size
);
15116 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15117 same types as the MAC equivalents. The polynomial type for this instruction
15118 is encoded the same as the integer type. */
15123 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15126 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15129 if (inst
.operands
[2].isscalar
)
15130 do_neon_mac_maybe_scalar ();
15132 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15136 do_neon_qdmulh (void)
15138 if (inst
.operands
[2].isscalar
)
15140 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15141 struct neon_type_el et
= neon_check_type (3, rs
,
15142 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15143 NEON_ENCODE (SCALAR
, inst
);
15144 neon_mul_mac (et
, neon_quad (rs
));
15148 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15149 struct neon_type_el et
= neon_check_type (3, rs
,
15150 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15151 NEON_ENCODE (INTEGER
, inst
);
15152 /* The U bit (rounding) comes from bit mask. */
15153 neon_three_same (neon_quad (rs
), 0, et
.size
);
15158 do_neon_qrdmlah (void)
15160 /* Check we're on the correct architecture. */
15161 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15163 _("instruction form not available on this architecture.");
15164 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15166 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15167 record_feature_use (&fpu_neon_ext_v8_1
);
15170 if (inst
.operands
[2].isscalar
)
15172 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15173 struct neon_type_el et
= neon_check_type (3, rs
,
15174 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15175 NEON_ENCODE (SCALAR
, inst
);
15176 neon_mul_mac (et
, neon_quad (rs
));
15180 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15181 struct neon_type_el et
= neon_check_type (3, rs
,
15182 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15183 NEON_ENCODE (INTEGER
, inst
);
15184 /* The U bit (rounding) comes from bit mask. */
15185 neon_three_same (neon_quad (rs
), 0, et
.size
);
15190 do_neon_fcmp_absolute (void)
15192 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15193 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15194 N_F_16_32
| N_KEY
);
15195 /* Size field comes from bit mask. */
15196 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15200 do_neon_fcmp_absolute_inv (void)
15202 neon_exchange_operands ();
15203 do_neon_fcmp_absolute ();
15207 do_neon_step (void)
15209 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15210 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15211 N_F_16_32
| N_KEY
);
15212 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15216 do_neon_abs_neg (void)
15218 enum neon_shape rs
;
15219 struct neon_type_el et
;
15221 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15224 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15227 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15228 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15230 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15231 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15232 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15233 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15234 inst
.instruction
|= neon_quad (rs
) << 6;
15235 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15236 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15238 neon_dp_fixup (&inst
);
15244 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15245 struct neon_type_el et
= neon_check_type (2, rs
,
15246 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15247 int imm
= inst
.operands
[2].imm
;
15248 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15249 _("immediate out of range for insert"));
15250 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15256 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15257 struct neon_type_el et
= neon_check_type (2, rs
,
15258 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15259 int imm
= inst
.operands
[2].imm
;
15260 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15261 _("immediate out of range for insert"));
15262 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15266 do_neon_qshlu_imm (void)
15268 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15269 struct neon_type_el et
= neon_check_type (2, rs
,
15270 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15271 int imm
= inst
.operands
[2].imm
;
15272 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15273 _("immediate out of range for shift"));
15274 /* Only encodes the 'U present' variant of the instruction.
15275 In this case, signed types have OP (bit 8) set to 0.
15276 Unsigned types have OP set to 1. */
15277 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15278 /* The rest of the bits are the same as other immediate shifts. */
15279 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15283 do_neon_qmovn (void)
15285 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15286 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15287 /* Saturating move where operands can be signed or unsigned, and the
15288 destination has the same signedness. */
15289 NEON_ENCODE (INTEGER
, inst
);
15290 if (et
.type
== NT_unsigned
)
15291 inst
.instruction
|= 0xc0;
15293 inst
.instruction
|= 0x80;
15294 neon_two_same (0, 1, et
.size
/ 2);
15298 do_neon_qmovun (void)
15300 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15301 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15302 /* Saturating move with unsigned results. Operands must be signed. */
15303 NEON_ENCODE (INTEGER
, inst
);
15304 neon_two_same (0, 1, et
.size
/ 2);
15308 do_neon_rshift_sat_narrow (void)
15310 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15311 or unsigned. If operands are unsigned, results must also be unsigned. */
15312 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15313 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15314 int imm
= inst
.operands
[2].imm
;
15315 /* This gets the bounds check, size encoding and immediate bits calculation
15319 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15320 VQMOVN.I<size> <Dd>, <Qm>. */
15323 inst
.operands
[2].present
= 0;
15324 inst
.instruction
= N_MNEM_vqmovn
;
15329 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15330 _("immediate out of range"));
15331 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15335 do_neon_rshift_sat_narrow_u (void)
15337 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15338 or unsigned. If operands are unsigned, results must also be unsigned. */
15339 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15340 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15341 int imm
= inst
.operands
[2].imm
;
15342 /* This gets the bounds check, size encoding and immediate bits calculation
15346 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15347 VQMOVUN.I<size> <Dd>, <Qm>. */
15350 inst
.operands
[2].present
= 0;
15351 inst
.instruction
= N_MNEM_vqmovun
;
15356 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15357 _("immediate out of range"));
15358 /* FIXME: The manual is kind of unclear about what value U should have in
15359 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15361 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15365 do_neon_movn (void)
15367 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15368 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15369 NEON_ENCODE (INTEGER
, inst
);
15370 neon_two_same (0, 1, et
.size
/ 2);
15374 do_neon_rshift_narrow (void)
15376 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15377 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15378 int imm
= inst
.operands
[2].imm
;
15379 /* This gets the bounds check, size encoding and immediate bits calculation
15383 /* If immediate is zero then we are a pseudo-instruction for
15384 VMOVN.I<size> <Dd>, <Qm> */
15387 inst
.operands
[2].present
= 0;
15388 inst
.instruction
= N_MNEM_vmovn
;
15393 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15394 _("immediate out of range for narrowing operation"));
15395 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15399 do_neon_shll (void)
15401 /* FIXME: Type checking when lengthening. */
15402 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15403 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15404 unsigned imm
= inst
.operands
[2].imm
;
15406 if (imm
== et
.size
)
15408 /* Maximum shift variant. */
15409 NEON_ENCODE (INTEGER
, inst
);
15410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15411 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15412 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15413 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15414 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15416 neon_dp_fixup (&inst
);
15420 /* A more-specific type check for non-max versions. */
15421 et
= neon_check_type (2, NS_QDI
,
15422 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15423 NEON_ENCODE (IMMED
, inst
);
15424 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15428 /* Check the various types for the VCVT instruction, and return which version
15429 the current instruction is. */
15431 #define CVT_FLAVOUR_VAR \
15432 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15433 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15434 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15435 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15436 /* Half-precision conversions. */ \
15437 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15438 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15439 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15440 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15441 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15442 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15443 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15444 Compared with single/double precision variants, only the co-processor \
15445 field is different, so the encoding flow is reused here. */ \
15446 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15447 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15448 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15449 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15450 /* VFP instructions. */ \
15451 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15452 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15453 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15454 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15455 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15456 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15457 /* VFP instructions with bitshift. */ \
15458 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15459 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15460 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15461 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15462 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15463 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15464 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15465 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15467 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15468 neon_cvt_flavour_##C,
15470 /* The different types of conversions we can do. */
15471 enum neon_cvt_flavour
15474 neon_cvt_flavour_invalid
,
15475 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15480 static enum neon_cvt_flavour
15481 get_neon_cvt_flavour (enum neon_shape rs
)
15483 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15484 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15485 if (et.type != NT_invtype) \
15487 inst.error = NULL; \
15488 return (neon_cvt_flavour_##C); \
15491 struct neon_type_el et
;
15492 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15493 || rs
== NS_FF
) ? N_VFP
: 0;
15494 /* The instruction versions which take an immediate take one register
15495 argument, which is extended to the width of the full register. Thus the
15496 "source" and "destination" registers must have the same width. Hack that
15497 here by making the size equal to the key (wider, in this case) operand. */
15498 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15502 return neon_cvt_flavour_invalid
;
15517 /* Neon-syntax VFP conversions. */
15520 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15522 const char *opname
= 0;
15524 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15525 || rs
== NS_FHI
|| rs
== NS_HFI
)
15527 /* Conversions with immediate bitshift. */
15528 const char *enc
[] =
15530 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15536 if (flavour
< (int) ARRAY_SIZE (enc
))
15538 opname
= enc
[flavour
];
15539 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15540 _("operands 0 and 1 must be the same register"));
15541 inst
.operands
[1] = inst
.operands
[2];
15542 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15547 /* Conversions without bitshift. */
15548 const char *enc
[] =
15550 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15556 if (flavour
< (int) ARRAY_SIZE (enc
))
15557 opname
= enc
[flavour
];
15561 do_vfp_nsyn_opcode (opname
);
15563 /* ARMv8.2 fp16 VCVT instruction. */
15564 if (flavour
== neon_cvt_flavour_s32_f16
15565 || flavour
== neon_cvt_flavour_u32_f16
15566 || flavour
== neon_cvt_flavour_f16_u32
15567 || flavour
== neon_cvt_flavour_f16_s32
)
15568 do_scalar_fp16_v82_encode ();
15572 do_vfp_nsyn_cvtz (void)
15574 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15575 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15576 const char *enc
[] =
15578 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15584 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15585 do_vfp_nsyn_opcode (enc
[flavour
]);
15589 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15590 enum neon_cvt_mode mode
)
15595 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15596 D register operands. */
15597 if (flavour
== neon_cvt_flavour_s32_f64
15598 || flavour
== neon_cvt_flavour_u32_f64
)
15599 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15602 if (flavour
== neon_cvt_flavour_s32_f16
15603 || flavour
== neon_cvt_flavour_u32_f16
)
15604 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15607 set_it_insn_type (OUTSIDE_IT_INSN
);
15611 case neon_cvt_flavour_s32_f64
:
15615 case neon_cvt_flavour_s32_f32
:
15619 case neon_cvt_flavour_s32_f16
:
15623 case neon_cvt_flavour_u32_f64
:
15627 case neon_cvt_flavour_u32_f32
:
15631 case neon_cvt_flavour_u32_f16
:
15636 first_error (_("invalid instruction shape"));
15642 case neon_cvt_mode_a
: rm
= 0; break;
15643 case neon_cvt_mode_n
: rm
= 1; break;
15644 case neon_cvt_mode_p
: rm
= 2; break;
15645 case neon_cvt_mode_m
: rm
= 3; break;
15646 default: first_error (_("invalid rounding mode")); return;
15649 NEON_ENCODE (FPV8
, inst
);
15650 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15651 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15652 inst
.instruction
|= sz
<< 8;
15654 /* ARMv8.2 fp16 VCVT instruction. */
15655 if (flavour
== neon_cvt_flavour_s32_f16
15656 ||flavour
== neon_cvt_flavour_u32_f16
)
15657 do_scalar_fp16_v82_encode ();
15658 inst
.instruction
|= op
<< 7;
15659 inst
.instruction
|= rm
<< 16;
15660 inst
.instruction
|= 0xf0000000;
15661 inst
.is_neon
= TRUE
;
15665 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15667 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15668 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15669 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15671 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15673 if (flavour
== neon_cvt_flavour_invalid
)
15676 /* PR11109: Handle round-to-zero for VCVT conversions. */
15677 if (mode
== neon_cvt_mode_z
15678 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15679 && (flavour
== neon_cvt_flavour_s16_f16
15680 || flavour
== neon_cvt_flavour_u16_f16
15681 || flavour
== neon_cvt_flavour_s32_f32
15682 || flavour
== neon_cvt_flavour_u32_f32
15683 || flavour
== neon_cvt_flavour_s32_f64
15684 || flavour
== neon_cvt_flavour_u32_f64
)
15685 && (rs
== NS_FD
|| rs
== NS_FF
))
15687 do_vfp_nsyn_cvtz ();
15691 /* ARMv8.2 fp16 VCVT conversions. */
15692 if (mode
== neon_cvt_mode_z
15693 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15694 && (flavour
== neon_cvt_flavour_s32_f16
15695 || flavour
== neon_cvt_flavour_u32_f16
)
15698 do_vfp_nsyn_cvtz ();
15699 do_scalar_fp16_v82_encode ();
15703 /* VFP rather than Neon conversions. */
15704 if (flavour
>= neon_cvt_flavour_first_fp
)
15706 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15707 do_vfp_nsyn_cvt (rs
, flavour
);
15709 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15720 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15721 0x0000100, 0x1000100, 0x0, 0x1000000};
15723 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15726 /* Fixed-point conversion with #0 immediate is encoded as an
15727 integer conversion. */
15728 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15730 NEON_ENCODE (IMMED
, inst
);
15731 if (flavour
!= neon_cvt_flavour_invalid
)
15732 inst
.instruction
|= enctab
[flavour
];
15733 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15734 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15735 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15736 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15737 inst
.instruction
|= neon_quad (rs
) << 6;
15738 inst
.instruction
|= 1 << 21;
15739 if (flavour
< neon_cvt_flavour_s16_f16
)
15741 inst
.instruction
|= 1 << 21;
15742 immbits
= 32 - inst
.operands
[2].imm
;
15743 inst
.instruction
|= immbits
<< 16;
15747 inst
.instruction
|= 3 << 20;
15748 immbits
= 16 - inst
.operands
[2].imm
;
15749 inst
.instruction
|= immbits
<< 16;
15750 inst
.instruction
&= ~(1 << 9);
15753 neon_dp_fixup (&inst
);
15759 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15761 NEON_ENCODE (FLOAT
, inst
);
15762 set_it_insn_type (OUTSIDE_IT_INSN
);
15764 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15767 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15768 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15769 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15770 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15771 inst
.instruction
|= neon_quad (rs
) << 6;
15772 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15773 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15774 inst
.instruction
|= mode
<< 8;
15775 if (flavour
== neon_cvt_flavour_u16_f16
15776 || flavour
== neon_cvt_flavour_s16_f16
)
15777 /* Mask off the original size bits and reencode them. */
15778 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15781 inst
.instruction
|= 0xfc000000;
15783 inst
.instruction
|= 0xf0000000;
15789 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15790 0x100, 0x180, 0x0, 0x080};
15792 NEON_ENCODE (INTEGER
, inst
);
15794 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15797 if (flavour
!= neon_cvt_flavour_invalid
)
15798 inst
.instruction
|= enctab
[flavour
];
15800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15801 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15802 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15803 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15804 inst
.instruction
|= neon_quad (rs
) << 6;
15805 if (flavour
>= neon_cvt_flavour_s16_f16
15806 && flavour
<= neon_cvt_flavour_f16_u16
)
15807 /* Half precision. */
15808 inst
.instruction
|= 1 << 18;
15810 inst
.instruction
|= 2 << 18;
15812 neon_dp_fixup (&inst
);
15817 /* Half-precision conversions for Advanced SIMD -- neon. */
15822 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15824 as_bad (_("operand size must match register width"));
15829 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15831 as_bad (_("operand size must match register width"));
15836 inst
.instruction
= 0x3b60600;
15838 inst
.instruction
= 0x3b60700;
15840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15843 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15844 neon_dp_fixup (&inst
);
15848 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15849 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15850 do_vfp_nsyn_cvt (rs
, flavour
);
15852 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15857 do_neon_cvtr (void)
15859 do_neon_cvt_1 (neon_cvt_mode_x
);
15865 do_neon_cvt_1 (neon_cvt_mode_z
);
15869 do_neon_cvta (void)
15871 do_neon_cvt_1 (neon_cvt_mode_a
);
15875 do_neon_cvtn (void)
15877 do_neon_cvt_1 (neon_cvt_mode_n
);
15881 do_neon_cvtp (void)
15883 do_neon_cvt_1 (neon_cvt_mode_p
);
15887 do_neon_cvtm (void)
15889 do_neon_cvt_1 (neon_cvt_mode_m
);
15893 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15896 mark_feature_used (&fpu_vfp_ext_armv8
);
15898 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15899 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15900 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15901 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15902 inst
.instruction
|= to
? 0x10000 : 0;
15903 inst
.instruction
|= t
? 0x80 : 0;
15904 inst
.instruction
|= is_double
? 0x100 : 0;
15905 do_vfp_cond_or_thumb ();
15909 do_neon_cvttb_1 (bfd_boolean t
)
15911 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15912 NS_DF
, NS_DH
, NS_NULL
);
15916 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15919 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15921 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15924 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15926 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15928 /* The VCVTB and VCVTT instructions with D-register operands
15929 don't work for SP only targets. */
15930 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15934 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15936 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15938 /* The VCVTB and VCVTT instructions with D-register operands
15939 don't work for SP only targets. */
15940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15944 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15951 do_neon_cvtb (void)
15953 do_neon_cvttb_1 (FALSE
);
15958 do_neon_cvtt (void)
15960 do_neon_cvttb_1 (TRUE
);
15964 neon_move_immediate (void)
15966 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15967 struct neon_type_el et
= neon_check_type (2, rs
,
15968 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15969 unsigned immlo
, immhi
= 0, immbits
;
15970 int op
, cmode
, float_p
;
15972 constraint (et
.type
== NT_invtype
,
15973 _("operand size must be specified for immediate VMOV"));
15975 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15976 op
= (inst
.instruction
& (1 << 5)) != 0;
15978 immlo
= inst
.operands
[1].imm
;
15979 if (inst
.operands
[1].regisimm
)
15980 immhi
= inst
.operands
[1].reg
;
15982 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15983 _("immediate has bits set outside the operand size"));
15985 float_p
= inst
.operands
[1].immisfloat
;
15987 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15988 et
.size
, et
.type
)) == FAIL
)
15990 /* Invert relevant bits only. */
15991 neon_invert_size (&immlo
, &immhi
, et
.size
);
15992 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15993 with one or the other; those cases are caught by
15994 neon_cmode_for_move_imm. */
15996 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15997 &op
, et
.size
, et
.type
)) == FAIL
)
15999 first_error (_("immediate out of range"));
16004 inst
.instruction
&= ~(1 << 5);
16005 inst
.instruction
|= op
<< 5;
16007 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16009 inst
.instruction
|= neon_quad (rs
) << 6;
16010 inst
.instruction
|= cmode
<< 8;
16012 neon_write_immbits (immbits
);
16018 if (inst
.operands
[1].isreg
)
16020 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16022 NEON_ENCODE (INTEGER
, inst
);
16023 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16024 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16025 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16026 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16027 inst
.instruction
|= neon_quad (rs
) << 6;
16031 NEON_ENCODE (IMMED
, inst
);
16032 neon_move_immediate ();
16035 neon_dp_fixup (&inst
);
16038 /* Encode instructions of form:
16040 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16041 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16044 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16046 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16047 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16048 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16049 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16050 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16051 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16052 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16053 inst
.instruction
|= neon_logbits (size
) << 20;
16055 neon_dp_fixup (&inst
);
16059 do_neon_dyadic_long (void)
16061 /* FIXME: Type checking for lengthening op. */
16062 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16063 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16064 neon_mixed_length (et
, et
.size
);
16068 do_neon_abal (void)
16070 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16071 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16072 neon_mixed_length (et
, et
.size
);
16076 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16078 if (inst
.operands
[2].isscalar
)
16080 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16081 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16082 NEON_ENCODE (SCALAR
, inst
);
16083 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16087 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16088 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16089 NEON_ENCODE (INTEGER
, inst
);
16090 neon_mixed_length (et
, et
.size
);
16095 do_neon_mac_maybe_scalar_long (void)
16097 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16101 do_neon_dyadic_wide (void)
16103 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16104 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16105 neon_mixed_length (et
, et
.size
);
16109 do_neon_dyadic_narrow (void)
16111 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16112 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16113 /* Operand sign is unimportant, and the U bit is part of the opcode,
16114 so force the operand type to integer. */
16115 et
.type
= NT_integer
;
16116 neon_mixed_length (et
, et
.size
/ 2);
16120 do_neon_mul_sat_scalar_long (void)
16122 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16126 do_neon_vmull (void)
16128 if (inst
.operands
[2].isscalar
)
16129 do_neon_mac_maybe_scalar_long ();
16132 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16133 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16135 if (et
.type
== NT_poly
)
16136 NEON_ENCODE (POLY
, inst
);
16138 NEON_ENCODE (INTEGER
, inst
);
16140 /* For polynomial encoding the U bit must be zero, and the size must
16141 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16142 obviously, as 0b10). */
16145 /* Check we're on the correct architecture. */
16146 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16148 _("Instruction form not available on this architecture.");
16153 neon_mixed_length (et
, et
.size
);
16160 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16161 struct neon_type_el et
= neon_check_type (3, rs
,
16162 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16163 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16165 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16166 _("shift out of range"));
16167 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16168 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16169 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16170 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16171 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16172 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16173 inst
.instruction
|= neon_quad (rs
) << 6;
16174 inst
.instruction
|= imm
<< 8;
16176 neon_dp_fixup (&inst
);
16182 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16183 struct neon_type_el et
= neon_check_type (2, rs
,
16184 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16185 unsigned op
= (inst
.instruction
>> 7) & 3;
16186 /* N (width of reversed regions) is encoded as part of the bitmask. We
16187 extract it here to check the elements to be reversed are smaller.
16188 Otherwise we'd get a reserved instruction. */
16189 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16190 gas_assert (elsize
!= 0);
16191 constraint (et
.size
>= elsize
,
16192 _("elements must be smaller than reversal region"));
16193 neon_two_same (neon_quad (rs
), 1, et
.size
);
16199 if (inst
.operands
[1].isscalar
)
16201 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16202 struct neon_type_el et
= neon_check_type (2, rs
,
16203 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16204 unsigned sizebits
= et
.size
>> 3;
16205 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16206 int logsize
= neon_logbits (et
.size
);
16207 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16209 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16212 NEON_ENCODE (SCALAR
, inst
);
16213 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16214 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16215 inst
.instruction
|= LOW4 (dm
);
16216 inst
.instruction
|= HI1 (dm
) << 5;
16217 inst
.instruction
|= neon_quad (rs
) << 6;
16218 inst
.instruction
|= x
<< 17;
16219 inst
.instruction
|= sizebits
<< 16;
16221 neon_dp_fixup (&inst
);
16225 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16226 struct neon_type_el et
= neon_check_type (2, rs
,
16227 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16228 /* Duplicate ARM register to lanes of vector. */
16229 NEON_ENCODE (ARMREG
, inst
);
16232 case 8: inst
.instruction
|= 0x400000; break;
16233 case 16: inst
.instruction
|= 0x000020; break;
16234 case 32: inst
.instruction
|= 0x000000; break;
16237 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16240 inst
.instruction
|= neon_quad (rs
) << 21;
16241 /* The encoding for this instruction is identical for the ARM and Thumb
16242 variants, except for the condition field. */
16243 do_vfp_cond_or_thumb ();
16247 /* VMOV has particularly many variations. It can be one of:
16248 0. VMOV<c><q> <Qd>, <Qm>
16249 1. VMOV<c><q> <Dd>, <Dm>
16250 (Register operations, which are VORR with Rm = Rn.)
16251 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16252 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16254 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16255 (ARM register to scalar.)
16256 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16257 (Two ARM registers to vector.)
16258 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16259 (Scalar to ARM register.)
16260 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16261 (Vector to two ARM registers.)
16262 8. VMOV.F32 <Sd>, <Sm>
16263 9. VMOV.F64 <Dd>, <Dm>
16264 (VFP register moves.)
16265 10. VMOV.F32 <Sd>, #imm
16266 11. VMOV.F64 <Dd>, #imm
16267 (VFP float immediate load.)
16268 12. VMOV <Rd>, <Sm>
16269 (VFP single to ARM reg.)
16270 13. VMOV <Sd>, <Rm>
16271 (ARM reg to VFP single.)
16272 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16273 (Two ARM regs to two VFP singles.)
16274 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16275 (Two VFP singles to two ARM regs.)
16277 These cases can be disambiguated using neon_select_shape, except cases 1/9
16278 and 3/11 which depend on the operand type too.
16280 All the encoded bits are hardcoded by this function.
16282 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16283 Cases 5, 7 may be used with VFPv2 and above.
16285 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16286 can specify a type where it doesn't make sense to, and is ignored). */
16291 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16292 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16293 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16294 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16295 struct neon_type_el et
;
16296 const char *ldconst
= 0;
16300 case NS_DD
: /* case 1/9. */
16301 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16302 /* It is not an error here if no type is given. */
16304 if (et
.type
== NT_float
&& et
.size
== 64)
16306 do_vfp_nsyn_opcode ("fcpyd");
16309 /* fall through. */
16311 case NS_QQ
: /* case 0/1. */
16313 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16315 /* The architecture manual I have doesn't explicitly state which
16316 value the U bit should have for register->register moves, but
16317 the equivalent VORR instruction has U = 0, so do that. */
16318 inst
.instruction
= 0x0200110;
16319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16321 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16322 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16323 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16324 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16325 inst
.instruction
|= neon_quad (rs
) << 6;
16327 neon_dp_fixup (&inst
);
16331 case NS_DI
: /* case 3/11. */
16332 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16334 if (et
.type
== NT_float
&& et
.size
== 64)
16336 /* case 11 (fconstd). */
16337 ldconst
= "fconstd";
16338 goto encode_fconstd
;
16340 /* fall through. */
16342 case NS_QI
: /* case 2/3. */
16343 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16345 inst
.instruction
= 0x0800010;
16346 neon_move_immediate ();
16347 neon_dp_fixup (&inst
);
16350 case NS_SR
: /* case 4. */
16352 unsigned bcdebits
= 0;
16354 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16355 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16357 /* .<size> is optional here, defaulting to .32. */
16358 if (inst
.vectype
.elems
== 0
16359 && inst
.operands
[0].vectype
.type
== NT_invtype
16360 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16362 inst
.vectype
.el
[0].type
= NT_untyped
;
16363 inst
.vectype
.el
[0].size
= 32;
16364 inst
.vectype
.elems
= 1;
16367 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16368 logsize
= neon_logbits (et
.size
);
16370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16372 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16373 && et
.size
!= 32, _(BAD_FPU
));
16374 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16375 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16379 case 8: bcdebits
= 0x8; break;
16380 case 16: bcdebits
= 0x1; break;
16381 case 32: bcdebits
= 0x0; break;
16385 bcdebits
|= x
<< logsize
;
16387 inst
.instruction
= 0xe000b10;
16388 do_vfp_cond_or_thumb ();
16389 inst
.instruction
|= LOW4 (dn
) << 16;
16390 inst
.instruction
|= HI1 (dn
) << 7;
16391 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16392 inst
.instruction
|= (bcdebits
& 3) << 5;
16393 inst
.instruction
|= (bcdebits
>> 2) << 21;
16397 case NS_DRR
: /* case 5 (fmdrr). */
16398 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16401 inst
.instruction
= 0xc400b10;
16402 do_vfp_cond_or_thumb ();
16403 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16405 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16406 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16409 case NS_RS
: /* case 6. */
16412 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16413 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16414 unsigned abcdebits
= 0;
16416 /* .<dt> is optional here, defaulting to .32. */
16417 if (inst
.vectype
.elems
== 0
16418 && inst
.operands
[0].vectype
.type
== NT_invtype
16419 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16421 inst
.vectype
.el
[0].type
= NT_untyped
;
16422 inst
.vectype
.el
[0].size
= 32;
16423 inst
.vectype
.elems
= 1;
16426 et
= neon_check_type (2, NS_NULL
,
16427 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16428 logsize
= neon_logbits (et
.size
);
16430 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16433 && et
.size
!= 32, _(BAD_FPU
));
16434 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16435 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16439 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16440 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16441 case 32: abcdebits
= 0x00; break;
16445 abcdebits
|= x
<< logsize
;
16446 inst
.instruction
= 0xe100b10;
16447 do_vfp_cond_or_thumb ();
16448 inst
.instruction
|= LOW4 (dn
) << 16;
16449 inst
.instruction
|= HI1 (dn
) << 7;
16450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16451 inst
.instruction
|= (abcdebits
& 3) << 5;
16452 inst
.instruction
|= (abcdebits
>> 2) << 21;
16456 case NS_RRD
: /* case 7 (fmrrd). */
16457 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16460 inst
.instruction
= 0xc500b10;
16461 do_vfp_cond_or_thumb ();
16462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16463 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16464 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16465 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16468 case NS_FF
: /* case 8 (fcpys). */
16469 do_vfp_nsyn_opcode ("fcpys");
16473 case NS_FI
: /* case 10 (fconsts). */
16474 ldconst
= "fconsts";
16476 if (is_quarter_float (inst
.operands
[1].imm
))
16478 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16479 do_vfp_nsyn_opcode (ldconst
);
16481 /* ARMv8.2 fp16 vmov.f16 instruction. */
16483 do_scalar_fp16_v82_encode ();
16486 first_error (_("immediate out of range"));
16490 case NS_RF
: /* case 12 (fmrs). */
16491 do_vfp_nsyn_opcode ("fmrs");
16492 /* ARMv8.2 fp16 vmov.f16 instruction. */
16494 do_scalar_fp16_v82_encode ();
16498 case NS_FR
: /* case 13 (fmsr). */
16499 do_vfp_nsyn_opcode ("fmsr");
16500 /* ARMv8.2 fp16 vmov.f16 instruction. */
16502 do_scalar_fp16_v82_encode ();
16505 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16506 (one of which is a list), but we have parsed four. Do some fiddling to
16507 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16509 case NS_RRFF
: /* case 14 (fmrrs). */
16510 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16511 _("VFP registers must be adjacent"));
16512 inst
.operands
[2].imm
= 2;
16513 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16514 do_vfp_nsyn_opcode ("fmrrs");
16517 case NS_FFRR
: /* case 15 (fmsrr). */
16518 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16519 _("VFP registers must be adjacent"));
16520 inst
.operands
[1] = inst
.operands
[2];
16521 inst
.operands
[2] = inst
.operands
[3];
16522 inst
.operands
[0].imm
= 2;
16523 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16524 do_vfp_nsyn_opcode ("fmsrr");
16528 /* neon_select_shape has determined that the instruction
16529 shape is wrong and has already set the error message. */
16538 do_neon_rshift_round_imm (void)
16540 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16541 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16542 int imm
= inst
.operands
[2].imm
;
16544 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16547 inst
.operands
[2].present
= 0;
16552 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16553 _("immediate out of range for shift"));
16554 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16559 do_neon_movhf (void)
16561 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16562 constraint (rs
!= NS_HH
, _("invalid suffix"));
16564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16567 do_vfp_sp_monadic ();
16570 inst
.instruction
|= 0xf0000000;
16574 do_neon_movl (void)
16576 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16577 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16578 unsigned sizebits
= et
.size
>> 3;
16579 inst
.instruction
|= sizebits
<< 19;
16580 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16587 struct neon_type_el et
= neon_check_type (2, rs
,
16588 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16589 NEON_ENCODE (INTEGER
, inst
);
16590 neon_two_same (neon_quad (rs
), 1, et
.size
);
16594 do_neon_zip_uzp (void)
16596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16597 struct neon_type_el et
= neon_check_type (2, rs
,
16598 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16599 if (rs
== NS_DD
&& et
.size
== 32)
16601 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16602 inst
.instruction
= N_MNEM_vtrn
;
16606 neon_two_same (neon_quad (rs
), 1, et
.size
);
16610 do_neon_sat_abs_neg (void)
16612 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16613 struct neon_type_el et
= neon_check_type (2, rs
,
16614 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16615 neon_two_same (neon_quad (rs
), 1, et
.size
);
16619 do_neon_pair_long (void)
16621 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16622 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16623 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16624 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16625 neon_two_same (neon_quad (rs
), 1, et
.size
);
16629 do_neon_recip_est (void)
16631 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16632 struct neon_type_el et
= neon_check_type (2, rs
,
16633 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16634 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16635 neon_two_same (neon_quad (rs
), 1, et
.size
);
16641 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16642 struct neon_type_el et
= neon_check_type (2, rs
,
16643 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16644 neon_two_same (neon_quad (rs
), 1, et
.size
);
16650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16651 struct neon_type_el et
= neon_check_type (2, rs
,
16652 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16653 neon_two_same (neon_quad (rs
), 1, et
.size
);
16659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16660 struct neon_type_el et
= neon_check_type (2, rs
,
16661 N_EQK
| N_INT
, N_8
| N_KEY
);
16662 neon_two_same (neon_quad (rs
), 1, et
.size
);
16668 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16669 neon_two_same (neon_quad (rs
), 1, -1);
16673 do_neon_tbl_tbx (void)
16675 unsigned listlenbits
;
16676 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16678 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16680 first_error (_("bad list length for table lookup"));
16684 listlenbits
= inst
.operands
[1].imm
- 1;
16685 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16686 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16687 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16688 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16689 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16690 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16691 inst
.instruction
|= listlenbits
<< 8;
16693 neon_dp_fixup (&inst
);
16697 do_neon_ldm_stm (void)
16699 /* P, U and L bits are part of bitmask. */
16700 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16701 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16703 if (inst
.operands
[1].issingle
)
16705 do_vfp_nsyn_ldm_stm (is_dbmode
);
16709 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16710 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16712 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16713 _("register list must contain at least 1 and at most 16 "
16716 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16717 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16719 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16721 inst
.instruction
|= offsetbits
;
16723 do_vfp_cond_or_thumb ();
16727 do_neon_ldr_str (void)
16729 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16731 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16732 And is UNPREDICTABLE in thumb mode. */
16734 && inst
.operands
[1].reg
== REG_PC
16735 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16738 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16739 else if (warn_on_deprecated
)
16740 as_tsktsk (_("Use of PC here is deprecated"));
16743 if (inst
.operands
[0].issingle
)
16746 do_vfp_nsyn_opcode ("flds");
16748 do_vfp_nsyn_opcode ("fsts");
16750 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16751 if (inst
.vectype
.el
[0].size
== 16)
16752 do_scalar_fp16_v82_encode ();
16757 do_vfp_nsyn_opcode ("fldd");
16759 do_vfp_nsyn_opcode ("fstd");
16763 /* "interleave" version also handles non-interleaving register VLD1/VST1
16767 do_neon_ld_st_interleave (void)
16769 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16770 N_8
| N_16
| N_32
| N_64
);
16771 unsigned alignbits
= 0;
16773 /* The bits in this table go:
16774 0: register stride of one (0) or two (1)
16775 1,2: register list length, minus one (1, 2, 3, 4).
16776 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16777 We use -1 for invalid entries. */
16778 const int typetable
[] =
16780 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16781 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16782 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16783 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16787 if (et
.type
== NT_invtype
)
16790 if (inst
.operands
[1].immisalign
)
16791 switch (inst
.operands
[1].imm
>> 8)
16793 case 64: alignbits
= 1; break;
16795 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16796 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16797 goto bad_alignment
;
16801 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16802 goto bad_alignment
;
16807 first_error (_("bad alignment"));
16811 inst
.instruction
|= alignbits
<< 4;
16812 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16814 /* Bits [4:6] of the immediate in a list specifier encode register stride
16815 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16816 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16817 up the right value for "type" in a table based on this value and the given
16818 list style, then stick it back. */
16819 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16820 | (((inst
.instruction
>> 8) & 3) << 3);
16822 typebits
= typetable
[idx
];
16824 constraint (typebits
== -1, _("bad list type for instruction"));
16825 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16826 _("bad element type for instruction"));
16828 inst
.instruction
&= ~0xf00;
16829 inst
.instruction
|= typebits
<< 8;
16832 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16833 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16834 otherwise. The variable arguments are a list of pairs of legal (size, align)
16835 values, terminated with -1. */
16838 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16841 int result
= FAIL
, thissize
, thisalign
;
16843 if (!inst
.operands
[1].immisalign
)
16849 va_start (ap
, do_alignment
);
16853 thissize
= va_arg (ap
, int);
16854 if (thissize
== -1)
16856 thisalign
= va_arg (ap
, int);
16858 if (size
== thissize
&& align
== thisalign
)
16861 while (result
!= SUCCESS
);
16865 if (result
== SUCCESS
)
16868 first_error (_("unsupported alignment for instruction"));
16874 do_neon_ld_st_lane (void)
16876 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16877 int align_good
, do_alignment
= 0;
16878 int logsize
= neon_logbits (et
.size
);
16879 int align
= inst
.operands
[1].imm
>> 8;
16880 int n
= (inst
.instruction
>> 8) & 3;
16881 int max_el
= 64 / et
.size
;
16883 if (et
.type
== NT_invtype
)
16886 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16887 _("bad list length"));
16888 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16889 _("scalar index out of range"));
16890 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16892 _("stride of 2 unavailable when element size is 8"));
16896 case 0: /* VLD1 / VST1. */
16897 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16899 if (align_good
== FAIL
)
16903 unsigned alignbits
= 0;
16906 case 16: alignbits
= 0x1; break;
16907 case 32: alignbits
= 0x3; break;
16910 inst
.instruction
|= alignbits
<< 4;
16914 case 1: /* VLD2 / VST2. */
16915 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16916 16, 32, 32, 64, -1);
16917 if (align_good
== FAIL
)
16920 inst
.instruction
|= 1 << 4;
16923 case 2: /* VLD3 / VST3. */
16924 constraint (inst
.operands
[1].immisalign
,
16925 _("can't use alignment with this instruction"));
16928 case 3: /* VLD4 / VST4. */
16929 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16930 16, 64, 32, 64, 32, 128, -1);
16931 if (align_good
== FAIL
)
16935 unsigned alignbits
= 0;
16938 case 8: alignbits
= 0x1; break;
16939 case 16: alignbits
= 0x1; break;
16940 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16943 inst
.instruction
|= alignbits
<< 4;
16950 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16951 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16952 inst
.instruction
|= 1 << (4 + logsize
);
16954 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16955 inst
.instruction
|= logsize
<< 10;
16958 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16961 do_neon_ld_dup (void)
16963 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16964 int align_good
, do_alignment
= 0;
16966 if (et
.type
== NT_invtype
)
16969 switch ((inst
.instruction
>> 8) & 3)
16971 case 0: /* VLD1. */
16972 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16973 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16974 &do_alignment
, 16, 16, 32, 32, -1);
16975 if (align_good
== FAIL
)
16977 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16980 case 2: inst
.instruction
|= 1 << 5; break;
16981 default: first_error (_("bad list length")); return;
16983 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16986 case 1: /* VLD2. */
16987 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16988 &do_alignment
, 8, 16, 16, 32, 32, 64,
16990 if (align_good
== FAIL
)
16992 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16993 _("bad list length"));
16994 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16995 inst
.instruction
|= 1 << 5;
16996 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16999 case 2: /* VLD3. */
17000 constraint (inst
.operands
[1].immisalign
,
17001 _("can't use alignment with this instruction"));
17002 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17003 _("bad list length"));
17004 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17005 inst
.instruction
|= 1 << 5;
17006 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17009 case 3: /* VLD4. */
17011 int align
= inst
.operands
[1].imm
>> 8;
17012 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17013 16, 64, 32, 64, 32, 128, -1);
17014 if (align_good
== FAIL
)
17016 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17017 _("bad list length"));
17018 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17019 inst
.instruction
|= 1 << 5;
17020 if (et
.size
== 32 && align
== 128)
17021 inst
.instruction
|= 0x3 << 6;
17023 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17030 inst
.instruction
|= do_alignment
<< 4;
17033 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17034 apart from bits [11:4]. */
17037 do_neon_ldx_stx (void)
17039 if (inst
.operands
[1].isreg
)
17040 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17042 switch (NEON_LANE (inst
.operands
[0].imm
))
17044 case NEON_INTERLEAVE_LANES
:
17045 NEON_ENCODE (INTERLV
, inst
);
17046 do_neon_ld_st_interleave ();
17049 case NEON_ALL_LANES
:
17050 NEON_ENCODE (DUP
, inst
);
17051 if (inst
.instruction
== N_INV
)
17053 first_error ("only loads support such operands");
17060 NEON_ENCODE (LANE
, inst
);
17061 do_neon_ld_st_lane ();
17064 /* L bit comes from bit mask. */
17065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17067 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17069 if (inst
.operands
[1].postind
)
17071 int postreg
= inst
.operands
[1].imm
& 0xf;
17072 constraint (!inst
.operands
[1].immisreg
,
17073 _("post-index must be a register"));
17074 constraint (postreg
== 0xd || postreg
== 0xf,
17075 _("bad register for post-index"));
17076 inst
.instruction
|= postreg
;
17080 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17081 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17082 || inst
.reloc
.exp
.X_add_number
!= 0,
17085 if (inst
.operands
[1].writeback
)
17087 inst
.instruction
|= 0xd;
17090 inst
.instruction
|= 0xf;
17094 inst
.instruction
|= 0xf9000000;
17096 inst
.instruction
|= 0xf4000000;
17101 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17103 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17104 D register operands. */
17105 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17106 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17109 NEON_ENCODE (FPV8
, inst
);
17111 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17113 do_vfp_sp_dyadic ();
17115 /* ARMv8.2 fp16 instruction. */
17117 do_scalar_fp16_v82_encode ();
17120 do_vfp_dp_rd_rn_rm ();
17123 inst
.instruction
|= 0x100;
17125 inst
.instruction
|= 0xf0000000;
17131 set_it_insn_type (OUTSIDE_IT_INSN
);
17133 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17134 first_error (_("invalid instruction shape"));
17140 set_it_insn_type (OUTSIDE_IT_INSN
);
17142 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17145 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17148 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17152 do_vrint_1 (enum neon_cvt_mode mode
)
17154 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17155 struct neon_type_el et
;
17160 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17161 D register operands. */
17162 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17166 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17168 if (et
.type
!= NT_invtype
)
17170 /* VFP encodings. */
17171 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17172 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17173 set_it_insn_type (OUTSIDE_IT_INSN
);
17175 NEON_ENCODE (FPV8
, inst
);
17176 if (rs
== NS_FF
|| rs
== NS_HH
)
17177 do_vfp_sp_monadic ();
17179 do_vfp_dp_rd_rm ();
17183 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17184 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17185 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17186 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17187 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17188 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17189 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17193 inst
.instruction
|= (rs
== NS_DD
) << 8;
17194 do_vfp_cond_or_thumb ();
17196 /* ARMv8.2 fp16 vrint instruction. */
17198 do_scalar_fp16_v82_encode ();
17202 /* Neon encodings (or something broken...). */
17204 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17206 if (et
.type
== NT_invtype
)
17209 set_it_insn_type (OUTSIDE_IT_INSN
);
17210 NEON_ENCODE (FLOAT
, inst
);
17212 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17215 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17216 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17217 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17218 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17219 inst
.instruction
|= neon_quad (rs
) << 6;
17220 /* Mask off the original size bits and reencode them. */
17221 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17222 | neon_logbits (et
.size
) << 18);
17226 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17227 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17228 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17229 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17230 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17231 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17232 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17237 inst
.instruction
|= 0xfc000000;
17239 inst
.instruction
|= 0xf0000000;
17246 do_vrint_1 (neon_cvt_mode_x
);
17252 do_vrint_1 (neon_cvt_mode_z
);
17258 do_vrint_1 (neon_cvt_mode_r
);
17264 do_vrint_1 (neon_cvt_mode_a
);
17270 do_vrint_1 (neon_cvt_mode_n
);
17276 do_vrint_1 (neon_cvt_mode_p
);
17282 do_vrint_1 (neon_cvt_mode_m
);
17286 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17288 unsigned regno
= NEON_SCALAR_REG (opnd
);
17289 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17291 if (elsize
== 16 && elno
< 2 && regno
< 16)
17292 return regno
| (elno
<< 4);
17293 else if (elsize
== 32 && elno
== 0)
17296 first_error (_("scalar out of range"));
17303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17305 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17306 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17307 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17308 _("immediate out of range"));
17310 if (inst
.operands
[2].isscalar
)
17312 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17313 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17314 N_KEY
| N_F16
| N_F32
).size
;
17315 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17317 inst
.instruction
= 0xfe000800;
17318 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17319 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17320 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17321 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17322 inst
.instruction
|= LOW4 (m
);
17323 inst
.instruction
|= HI1 (m
) << 5;
17324 inst
.instruction
|= neon_quad (rs
) << 6;
17325 inst
.instruction
|= rot
<< 20;
17326 inst
.instruction
|= (size
== 32) << 23;
17330 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17331 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17332 N_KEY
| N_F16
| N_F32
).size
;
17333 neon_three_same (neon_quad (rs
), 0, -1);
17334 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17335 inst
.instruction
|= 0xfc200800;
17336 inst
.instruction
|= rot
<< 23;
17337 inst
.instruction
|= (size
== 32) << 20;
17344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17346 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17347 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17348 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17349 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17350 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17351 N_KEY
| N_F16
| N_F32
).size
;
17352 neon_three_same (neon_quad (rs
), 0, -1);
17353 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17354 inst
.instruction
|= 0xfc800800;
17355 inst
.instruction
|= (rot
== 270) << 24;
17356 inst
.instruction
|= (size
== 32) << 20;
17359 /* Crypto v1 instructions. */
17361 do_crypto_2op_1 (unsigned elttype
, int op
)
17363 set_it_insn_type (OUTSIDE_IT_INSN
);
17365 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17371 NEON_ENCODE (INTEGER
, inst
);
17372 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17374 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17375 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17377 inst
.instruction
|= op
<< 6;
17380 inst
.instruction
|= 0xfc000000;
17382 inst
.instruction
|= 0xf0000000;
17386 do_crypto_3op_1 (int u
, int op
)
17388 set_it_insn_type (OUTSIDE_IT_INSN
);
17390 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17391 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17396 NEON_ENCODE (INTEGER
, inst
);
17397 neon_three_same (1, u
, 8 << op
);
17403 do_crypto_2op_1 (N_8
, 0);
17409 do_crypto_2op_1 (N_8
, 1);
17415 do_crypto_2op_1 (N_8
, 2);
17421 do_crypto_2op_1 (N_8
, 3);
17427 do_crypto_3op_1 (0, 0);
17433 do_crypto_3op_1 (0, 1);
17439 do_crypto_3op_1 (0, 2);
17445 do_crypto_3op_1 (0, 3);
17451 do_crypto_3op_1 (1, 0);
17457 do_crypto_3op_1 (1, 1);
17461 do_sha256su1 (void)
17463 do_crypto_3op_1 (1, 2);
17469 do_crypto_2op_1 (N_32
, -1);
17475 do_crypto_2op_1 (N_32
, 0);
17479 do_sha256su0 (void)
17481 do_crypto_2op_1 (N_32
, 1);
17485 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17487 unsigned int Rd
= inst
.operands
[0].reg
;
17488 unsigned int Rn
= inst
.operands
[1].reg
;
17489 unsigned int Rm
= inst
.operands
[2].reg
;
17491 set_it_insn_type (OUTSIDE_IT_INSN
);
17492 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17493 inst
.instruction
|= LOW4 (Rn
) << 16;
17494 inst
.instruction
|= LOW4 (Rm
);
17495 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17496 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17498 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17499 as_warn (UNPRED_REG ("r15"));
17500 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17501 as_warn (UNPRED_REG ("r13"));
17543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17545 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17546 do_vfp_sp_dp_cvt ();
17547 do_vfp_cond_or_thumb ();
17551 /* Overall per-instruction processing. */
17553 /* We need to be able to fix up arbitrary expressions in some statements.
17554 This is so that we can handle symbols that are an arbitrary distance from
17555 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17556 which returns part of an address in a form which will be valid for
17557 a data instruction. We do this by pushing the expression into a symbol
17558 in the expr_section, and creating a fix for that. */
17561 fix_new_arm (fragS
* frag
,
17575 /* Create an absolute valued symbol, so we have something to
17576 refer to in the object file. Unfortunately for us, gas's
17577 generic expression parsing will already have folded out
17578 any use of .set foo/.type foo %function that may have
17579 been used to set type information of the target location,
17580 that's being specified symbolically. We have to presume
17581 the user knows what they are doing. */
17585 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17587 symbol
= symbol_find_or_make (name
);
17588 S_SET_SEGMENT (symbol
, absolute_section
);
17589 symbol_set_frag (symbol
, &zero_address_frag
);
17590 S_SET_VALUE (symbol
, exp
->X_add_number
);
17591 exp
->X_op
= O_symbol
;
17592 exp
->X_add_symbol
= symbol
;
17593 exp
->X_add_number
= 0;
17599 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17600 (enum bfd_reloc_code_real
) reloc
);
17604 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17605 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17609 /* Mark whether the fix is to a THUMB instruction, or an ARM
17611 new_fix
->tc_fix_data
= thumb_mode
;
17614 /* Create a frg for an instruction requiring relaxation. */
17616 output_relax_insn (void)
17622 /* The size of the instruction is unknown, so tie the debug info to the
17623 start of the instruction. */
17624 dwarf2_emit_insn (0);
17626 switch (inst
.reloc
.exp
.X_op
)
17629 sym
= inst
.reloc
.exp
.X_add_symbol
;
17630 offset
= inst
.reloc
.exp
.X_add_number
;
17634 offset
= inst
.reloc
.exp
.X_add_number
;
17637 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17641 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17642 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17643 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17646 /* Write a 32-bit thumb instruction to buf. */
17648 put_thumb32_insn (char * buf
, unsigned long insn
)
17650 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17651 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17655 output_inst (const char * str
)
17661 as_bad ("%s -- `%s'", inst
.error
, str
);
17666 output_relax_insn ();
17669 if (inst
.size
== 0)
17672 to
= frag_more (inst
.size
);
17673 /* PR 9814: Record the thumb mode into the current frag so that we know
17674 what type of NOP padding to use, if necessary. We override any previous
17675 setting so that if the mode has changed then the NOPS that we use will
17676 match the encoding of the last instruction in the frag. */
17677 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17679 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17681 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17682 put_thumb32_insn (to
, inst
.instruction
);
17684 else if (inst
.size
> INSN_SIZE
)
17686 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17687 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17688 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17691 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17693 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17694 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17695 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17698 dwarf2_emit_insn (inst
.size
);
17702 output_it_inst (int cond
, int mask
, char * to
)
17704 unsigned long instruction
= 0xbf00;
17707 instruction
|= mask
;
17708 instruction
|= cond
<< 4;
17712 to
= frag_more (2);
17714 dwarf2_emit_insn (2);
17718 md_number_to_chars (to
, instruction
, 2);
17723 /* Tag values used in struct asm_opcode's tag field. */
17726 OT_unconditional
, /* Instruction cannot be conditionalized.
17727 The ARM condition field is still 0xE. */
17728 OT_unconditionalF
, /* Instruction cannot be conditionalized
17729 and carries 0xF in its ARM condition field. */
17730 OT_csuffix
, /* Instruction takes a conditional suffix. */
17731 OT_csuffixF
, /* Some forms of the instruction take a conditional
17732 suffix, others place 0xF where the condition field
17734 OT_cinfix3
, /* Instruction takes a conditional infix,
17735 beginning at character index 3. (In
17736 unified mode, it becomes a suffix.) */
17737 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17738 tsts, cmps, cmns, and teqs. */
17739 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17740 character index 3, even in unified mode. Used for
17741 legacy instructions where suffix and infix forms
17742 may be ambiguous. */
17743 OT_csuf_or_in3
, /* Instruction takes either a conditional
17744 suffix or an infix at character index 3. */
17745 OT_odd_infix_unc
, /* This is the unconditional variant of an
17746 instruction that takes a conditional infix
17747 at an unusual position. In unified mode,
17748 this variant will accept a suffix. */
17749 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17750 are the conditional variants of instructions that
17751 take conditional infixes in unusual positions.
17752 The infix appears at character index
17753 (tag - OT_odd_infix_0). These are not accepted
17754 in unified mode. */
17757 /* Subroutine of md_assemble, responsible for looking up the primary
17758 opcode from the mnemonic the user wrote. STR points to the
17759 beginning of the mnemonic.
17761 This is not simply a hash table lookup, because of conditional
17762 variants. Most instructions have conditional variants, which are
17763 expressed with a _conditional affix_ to the mnemonic. If we were
17764 to encode each conditional variant as a literal string in the opcode
17765 table, it would have approximately 20,000 entries.
17767 Most mnemonics take this affix as a suffix, and in unified syntax,
17768 'most' is upgraded to 'all'. However, in the divided syntax, some
17769 instructions take the affix as an infix, notably the s-variants of
17770 the arithmetic instructions. Of those instructions, all but six
17771 have the infix appear after the third character of the mnemonic.
17773 Accordingly, the algorithm for looking up primary opcodes given
17776 1. Look up the identifier in the opcode table.
17777 If we find a match, go to step U.
17779 2. Look up the last two characters of the identifier in the
17780 conditions table. If we find a match, look up the first N-2
17781 characters of the identifier in the opcode table. If we
17782 find a match, go to step CE.
17784 3. Look up the fourth and fifth characters of the identifier in
17785 the conditions table. If we find a match, extract those
17786 characters from the identifier, and look up the remaining
17787 characters in the opcode table. If we find a match, go
17792 U. Examine the tag field of the opcode structure, in case this is
17793 one of the six instructions with its conditional infix in an
17794 unusual place. If it is, the tag tells us where to find the
17795 infix; look it up in the conditions table and set inst.cond
17796 accordingly. Otherwise, this is an unconditional instruction.
17797 Again set inst.cond accordingly. Return the opcode structure.
17799 CE. Examine the tag field to make sure this is an instruction that
17800 should receive a conditional suffix. If it is not, fail.
17801 Otherwise, set inst.cond from the suffix we already looked up,
17802 and return the opcode structure.
17804 CM. Examine the tag field to make sure this is an instruction that
17805 should receive a conditional infix after the third character.
17806 If it is not, fail. Otherwise, undo the edits to the current
17807 line of input and proceed as for case CE. */
17809 static const struct asm_opcode
*
17810 opcode_lookup (char **str
)
17814 const struct asm_opcode
*opcode
;
17815 const struct asm_cond
*cond
;
17818 /* Scan up to the end of the mnemonic, which must end in white space,
17819 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17820 for (base
= end
= *str
; *end
!= '\0'; end
++)
17821 if (*end
== ' ' || *end
== '.')
17827 /* Handle a possible width suffix and/or Neon type suffix. */
17832 /* The .w and .n suffixes are only valid if the unified syntax is in
17834 if (unified_syntax
&& end
[1] == 'w')
17836 else if (unified_syntax
&& end
[1] == 'n')
17841 inst
.vectype
.elems
= 0;
17843 *str
= end
+ offset
;
17845 if (end
[offset
] == '.')
17847 /* See if we have a Neon type suffix (possible in either unified or
17848 non-unified ARM syntax mode). */
17849 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17852 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17858 /* Look for unaffixed or special-case affixed mnemonic. */
17859 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17864 if (opcode
->tag
< OT_odd_infix_0
)
17866 inst
.cond
= COND_ALWAYS
;
17870 if (warn_on_deprecated
&& unified_syntax
)
17871 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17872 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17873 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17876 inst
.cond
= cond
->value
;
17880 /* Cannot have a conditional suffix on a mnemonic of less than two
17882 if (end
- base
< 3)
17885 /* Look for suffixed mnemonic. */
17887 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17888 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17890 if (opcode
&& cond
)
17893 switch (opcode
->tag
)
17895 case OT_cinfix3_legacy
:
17896 /* Ignore conditional suffixes matched on infix only mnemonics. */
17900 case OT_cinfix3_deprecated
:
17901 case OT_odd_infix_unc
:
17902 if (!unified_syntax
)
17904 /* Fall through. */
17908 case OT_csuf_or_in3
:
17909 inst
.cond
= cond
->value
;
17912 case OT_unconditional
:
17913 case OT_unconditionalF
:
17915 inst
.cond
= cond
->value
;
17918 /* Delayed diagnostic. */
17919 inst
.error
= BAD_COND
;
17920 inst
.cond
= COND_ALWAYS
;
17929 /* Cannot have a usual-position infix on a mnemonic of less than
17930 six characters (five would be a suffix). */
17931 if (end
- base
< 6)
17934 /* Look for infixed mnemonic in the usual position. */
17936 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17940 memcpy (save
, affix
, 2);
17941 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17942 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17944 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17945 memcpy (affix
, save
, 2);
17948 && (opcode
->tag
== OT_cinfix3
17949 || opcode
->tag
== OT_cinfix3_deprecated
17950 || opcode
->tag
== OT_csuf_or_in3
17951 || opcode
->tag
== OT_cinfix3_legacy
))
17954 if (warn_on_deprecated
&& unified_syntax
17955 && (opcode
->tag
== OT_cinfix3
17956 || opcode
->tag
== OT_cinfix3_deprecated
))
17957 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17959 inst
.cond
= cond
->value
;
17966 /* This function generates an initial IT instruction, leaving its block
17967 virtually open for the new instructions. Eventually,
17968 the mask will be updated by now_it_add_mask () each time
17969 a new instruction needs to be included in the IT block.
17970 Finally, the block is closed with close_automatic_it_block ().
17971 The block closure can be requested either from md_assemble (),
17972 a tencode (), or due to a label hook. */
17975 new_automatic_it_block (int cond
)
17977 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17978 now_it
.mask
= 0x18;
17980 now_it
.block_length
= 1;
17981 mapping_state (MAP_THUMB
);
17982 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17983 now_it
.warn_deprecated
= FALSE
;
17984 now_it
.insn_cond
= TRUE
;
17987 /* Close an automatic IT block.
17988 See comments in new_automatic_it_block (). */
17991 close_automatic_it_block (void)
17993 now_it
.mask
= 0x10;
17994 now_it
.block_length
= 0;
17997 /* Update the mask of the current automatically-generated IT
17998 instruction. See comments in new_automatic_it_block (). */
18001 now_it_add_mask (int cond
)
18003 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18004 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18005 | ((bitvalue) << (nbit)))
18006 const int resulting_bit
= (cond
& 1);
18008 now_it
.mask
&= 0xf;
18009 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18011 (5 - now_it
.block_length
));
18012 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18014 ((5 - now_it
.block_length
) - 1) );
18015 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18018 #undef SET_BIT_VALUE
18021 /* The IT blocks handling machinery is accessed through the these functions:
18022 it_fsm_pre_encode () from md_assemble ()
18023 set_it_insn_type () optional, from the tencode functions
18024 set_it_insn_type_last () ditto
18025 in_it_block () ditto
18026 it_fsm_post_encode () from md_assemble ()
18027 force_automatic_it_block_close () from label handling functions
18030 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18031 initializing the IT insn type with a generic initial value depending
18032 on the inst.condition.
18033 2) During the tencode function, two things may happen:
18034 a) The tencode function overrides the IT insn type by
18035 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18036 b) The tencode function queries the IT block state by
18037 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18039 Both set_it_insn_type and in_it_block run the internal FSM state
18040 handling function (handle_it_state), because: a) setting the IT insn
18041 type may incur in an invalid state (exiting the function),
18042 and b) querying the state requires the FSM to be updated.
18043 Specifically we want to avoid creating an IT block for conditional
18044 branches, so it_fsm_pre_encode is actually a guess and we can't
18045 determine whether an IT block is required until the tencode () routine
18046 has decided what type of instruction this actually it.
18047 Because of this, if set_it_insn_type and in_it_block have to be used,
18048 set_it_insn_type has to be called first.
18050 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18051 determines the insn IT type depending on the inst.cond code.
18052 When a tencode () routine encodes an instruction that can be
18053 either outside an IT block, or, in the case of being inside, has to be
18054 the last one, set_it_insn_type_last () will determine the proper
18055 IT instruction type based on the inst.cond code. Otherwise,
18056 set_it_insn_type can be called for overriding that logic or
18057 for covering other cases.
18059 Calling handle_it_state () may not transition the IT block state to
18060 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18061 still queried. Instead, if the FSM determines that the state should
18062 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18063 after the tencode () function: that's what it_fsm_post_encode () does.
18065 Since in_it_block () calls the state handling function to get an
18066 updated state, an error may occur (due to invalid insns combination).
18067 In that case, inst.error is set.
18068 Therefore, inst.error has to be checked after the execution of
18069 the tencode () routine.
18071 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18072 any pending state change (if any) that didn't take place in
18073 handle_it_state () as explained above. */
18076 it_fsm_pre_encode (void)
18078 if (inst
.cond
!= COND_ALWAYS
)
18079 inst
.it_insn_type
= INSIDE_IT_INSN
;
18081 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18083 now_it
.state_handled
= 0;
18086 /* IT state FSM handling function. */
18089 handle_it_state (void)
18091 now_it
.state_handled
= 1;
18092 now_it
.insn_cond
= FALSE
;
18094 switch (now_it
.state
)
18096 case OUTSIDE_IT_BLOCK
:
18097 switch (inst
.it_insn_type
)
18099 case OUTSIDE_IT_INSN
:
18102 case INSIDE_IT_INSN
:
18103 case INSIDE_IT_LAST_INSN
:
18104 if (thumb_mode
== 0)
18107 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18108 as_tsktsk (_("Warning: conditional outside an IT block"\
18113 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18114 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18116 /* Automatically generate the IT instruction. */
18117 new_automatic_it_block (inst
.cond
);
18118 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18119 close_automatic_it_block ();
18123 inst
.error
= BAD_OUT_IT
;
18129 case IF_INSIDE_IT_LAST_INSN
:
18130 case NEUTRAL_IT_INSN
:
18134 now_it
.state
= MANUAL_IT_BLOCK
;
18135 now_it
.block_length
= 0;
18140 case AUTOMATIC_IT_BLOCK
:
18141 /* Three things may happen now:
18142 a) We should increment current it block size;
18143 b) We should close current it block (closing insn or 4 insns);
18144 c) We should close current it block and start a new one (due
18145 to incompatible conditions or
18146 4 insns-length block reached). */
18148 switch (inst
.it_insn_type
)
18150 case OUTSIDE_IT_INSN
:
18151 /* The closure of the block shall happen immediately,
18152 so any in_it_block () call reports the block as closed. */
18153 force_automatic_it_block_close ();
18156 case INSIDE_IT_INSN
:
18157 case INSIDE_IT_LAST_INSN
:
18158 case IF_INSIDE_IT_LAST_INSN
:
18159 now_it
.block_length
++;
18161 if (now_it
.block_length
> 4
18162 || !now_it_compatible (inst
.cond
))
18164 force_automatic_it_block_close ();
18165 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18166 new_automatic_it_block (inst
.cond
);
18170 now_it
.insn_cond
= TRUE
;
18171 now_it_add_mask (inst
.cond
);
18174 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18175 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18176 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18177 close_automatic_it_block ();
18180 case NEUTRAL_IT_INSN
:
18181 now_it
.block_length
++;
18182 now_it
.insn_cond
= TRUE
;
18184 if (now_it
.block_length
> 4)
18185 force_automatic_it_block_close ();
18187 now_it_add_mask (now_it
.cc
& 1);
18191 close_automatic_it_block ();
18192 now_it
.state
= MANUAL_IT_BLOCK
;
18197 case MANUAL_IT_BLOCK
:
18199 /* Check conditional suffixes. */
18200 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18203 now_it
.mask
&= 0x1f;
18204 is_last
= (now_it
.mask
== 0x10);
18205 now_it
.insn_cond
= TRUE
;
18207 switch (inst
.it_insn_type
)
18209 case OUTSIDE_IT_INSN
:
18210 inst
.error
= BAD_NOT_IT
;
18213 case INSIDE_IT_INSN
:
18214 if (cond
!= inst
.cond
)
18216 inst
.error
= BAD_IT_COND
;
18221 case INSIDE_IT_LAST_INSN
:
18222 case IF_INSIDE_IT_LAST_INSN
:
18223 if (cond
!= inst
.cond
)
18225 inst
.error
= BAD_IT_COND
;
18230 inst
.error
= BAD_BRANCH
;
18235 case NEUTRAL_IT_INSN
:
18236 /* The BKPT instruction is unconditional even in an IT block. */
18240 inst
.error
= BAD_IT_IT
;
18250 struct depr_insn_mask
18252 unsigned long pattern
;
18253 unsigned long mask
;
18254 const char* description
;
18257 /* List of 16-bit instruction patterns deprecated in an IT block in
18259 static const struct depr_insn_mask depr_it_insns
[] = {
18260 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18261 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18262 { 0xa000, 0xb800, N_("ADR") },
18263 { 0x4800, 0xf800, N_("Literal loads") },
18264 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18265 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18266 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18267 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18268 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18273 it_fsm_post_encode (void)
18277 if (!now_it
.state_handled
)
18278 handle_it_state ();
18280 if (now_it
.insn_cond
18281 && !now_it
.warn_deprecated
18282 && warn_on_deprecated
18283 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18285 if (inst
.instruction
>= 0x10000)
18287 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18288 "deprecated in ARMv8"));
18289 now_it
.warn_deprecated
= TRUE
;
18293 const struct depr_insn_mask
*p
= depr_it_insns
;
18295 while (p
->mask
!= 0)
18297 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18299 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18300 "of the following class are deprecated in ARMv8: "
18301 "%s"), p
->description
);
18302 now_it
.warn_deprecated
= TRUE
;
18310 if (now_it
.block_length
> 1)
18312 as_tsktsk (_("IT blocks containing more than one conditional "
18313 "instruction are deprecated in ARMv8"));
18314 now_it
.warn_deprecated
= TRUE
;
18318 is_last
= (now_it
.mask
== 0x10);
18321 now_it
.state
= OUTSIDE_IT_BLOCK
;
18327 force_automatic_it_block_close (void)
18329 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18331 close_automatic_it_block ();
18332 now_it
.state
= OUTSIDE_IT_BLOCK
;
18340 if (!now_it
.state_handled
)
18341 handle_it_state ();
18343 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18346 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18347 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18348 here, hence the "known" in the function name. */
18351 known_t32_only_insn (const struct asm_opcode
*opcode
)
18353 /* Original Thumb-1 wide instruction. */
18354 if (opcode
->tencode
== do_t_blx
18355 || opcode
->tencode
== do_t_branch23
18356 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18357 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18360 /* Wide-only instruction added to ARMv8-M Baseline. */
18361 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18362 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18363 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18364 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18370 /* Whether wide instruction variant can be used if available for a valid OPCODE
18374 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18376 if (known_t32_only_insn (opcode
))
18379 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18380 of variant T3 of B.W is checked in do_t_branch. */
18381 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18382 && opcode
->tencode
== do_t_branch
)
18385 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18386 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18387 && opcode
->tencode
== do_t_mov_cmp
18388 /* Make sure CMP instruction is not affected. */
18389 && opcode
->aencode
== do_mov
)
18392 /* Wide instruction variants of all instructions with narrow *and* wide
18393 variants become available with ARMv6t2. Other opcodes are either
18394 narrow-only or wide-only and are thus available if OPCODE is valid. */
18395 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18398 /* OPCODE with narrow only instruction variant or wide variant not
18404 md_assemble (char *str
)
18407 const struct asm_opcode
* opcode
;
18409 /* Align the previous label if needed. */
18410 if (last_label_seen
!= NULL
)
18412 symbol_set_frag (last_label_seen
, frag_now
);
18413 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18414 S_SET_SEGMENT (last_label_seen
, now_seg
);
18417 memset (&inst
, '\0', sizeof (inst
));
18418 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18420 opcode
= opcode_lookup (&p
);
18423 /* It wasn't an instruction, but it might be a register alias of
18424 the form alias .req reg, or a Neon .dn/.qn directive. */
18425 if (! create_register_alias (str
, p
)
18426 && ! create_neon_reg_alias (str
, p
))
18427 as_bad (_("bad instruction `%s'"), str
);
18432 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18433 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18435 /* The value which unconditional instructions should have in place of the
18436 condition field. */
18437 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18441 arm_feature_set variant
;
18443 variant
= cpu_variant
;
18444 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18445 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18446 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18447 /* Check that this instruction is supported for this CPU. */
18448 if (!opcode
->tvariant
18449 || (thumb_mode
== 1
18450 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18452 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18455 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18456 && opcode
->tencode
!= do_t_branch
)
18458 as_bad (_("Thumb does not support conditional execution"));
18462 /* Two things are addressed here:
18463 1) Implicit require narrow instructions on Thumb-1.
18464 This avoids relaxation accidentally introducing Thumb-2
18466 2) Reject wide instructions in non Thumb-2 cores.
18468 Only instructions with narrow and wide variants need to be handled
18469 but selecting all non wide-only instructions is easier. */
18470 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18471 && !t32_insn_ok (variant
, opcode
))
18473 if (inst
.size_req
== 0)
18475 else if (inst
.size_req
== 4)
18477 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18478 as_bad (_("selected processor does not support 32bit wide "
18479 "variant of instruction `%s'"), str
);
18481 as_bad (_("selected processor does not support `%s' in "
18482 "Thumb-2 mode"), str
);
18487 inst
.instruction
= opcode
->tvalue
;
18489 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18491 /* Prepare the it_insn_type for those encodings that don't set
18493 it_fsm_pre_encode ();
18495 opcode
->tencode ();
18497 it_fsm_post_encode ();
18500 if (!(inst
.error
|| inst
.relax
))
18502 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18503 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18504 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18506 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18511 /* Something has gone badly wrong if we try to relax a fixed size
18513 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18515 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18516 *opcode
->tvariant
);
18517 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18518 set those bits when Thumb-2 32-bit instructions are seen. The impact
18519 of relaxable instructions will be considered later after we finish all
18521 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18522 variant
= arm_arch_none
;
18524 variant
= cpu_variant
;
18525 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18526 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18529 check_neon_suffixes
;
18533 mapping_state (MAP_THUMB
);
18536 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18540 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18541 is_bx
= (opcode
->aencode
== do_bx
);
18543 /* Check that this instruction is supported for this CPU. */
18544 if (!(is_bx
&& fix_v4bx
)
18545 && !(opcode
->avariant
&&
18546 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18548 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18553 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18557 inst
.instruction
= opcode
->avalue
;
18558 if (opcode
->tag
== OT_unconditionalF
)
18559 inst
.instruction
|= 0xFU
<< 28;
18561 inst
.instruction
|= inst
.cond
<< 28;
18562 inst
.size
= INSN_SIZE
;
18563 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18565 it_fsm_pre_encode ();
18566 opcode
->aencode ();
18567 it_fsm_post_encode ();
18569 /* Arm mode bx is marked as both v4T and v5 because it's still required
18570 on a hypothetical non-thumb v5 core. */
18572 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18574 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18575 *opcode
->avariant
);
18577 check_neon_suffixes
;
18581 mapping_state (MAP_ARM
);
18586 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18594 check_it_blocks_finished (void)
18599 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18600 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18601 == MANUAL_IT_BLOCK
)
18603 as_warn (_("section '%s' finished with an open IT block."),
18607 if (now_it
.state
== MANUAL_IT_BLOCK
)
18608 as_warn (_("file finished with an open IT block."));
18612 /* Various frobbings of labels and their addresses. */
18615 arm_start_line_hook (void)
18617 last_label_seen
= NULL
;
18621 arm_frob_label (symbolS
* sym
)
18623 last_label_seen
= sym
;
18625 ARM_SET_THUMB (sym
, thumb_mode
);
18627 #if defined OBJ_COFF || defined OBJ_ELF
18628 ARM_SET_INTERWORK (sym
, support_interwork
);
18631 force_automatic_it_block_close ();
18633 /* Note - do not allow local symbols (.Lxxx) to be labelled
18634 as Thumb functions. This is because these labels, whilst
18635 they exist inside Thumb code, are not the entry points for
18636 possible ARM->Thumb calls. Also, these labels can be used
18637 as part of a computed goto or switch statement. eg gcc
18638 can generate code that looks like this:
18640 ldr r2, [pc, .Laaa]
18650 The first instruction loads the address of the jump table.
18651 The second instruction converts a table index into a byte offset.
18652 The third instruction gets the jump address out of the table.
18653 The fourth instruction performs the jump.
18655 If the address stored at .Laaa is that of a symbol which has the
18656 Thumb_Func bit set, then the linker will arrange for this address
18657 to have the bottom bit set, which in turn would mean that the
18658 address computation performed by the third instruction would end
18659 up with the bottom bit set. Since the ARM is capable of unaligned
18660 word loads, the instruction would then load the incorrect address
18661 out of the jump table, and chaos would ensue. */
18662 if (label_is_thumb_function_name
18663 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18664 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18666 /* When the address of a Thumb function is taken the bottom
18667 bit of that address should be set. This will allow
18668 interworking between Arm and Thumb functions to work
18671 THUMB_SET_FUNC (sym
, 1);
18673 label_is_thumb_function_name
= FALSE
;
18676 dwarf2_emit_label (sym
);
18680 arm_data_in_code (void)
18682 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18684 *input_line_pointer
= '/';
18685 input_line_pointer
+= 5;
18686 *input_line_pointer
= 0;
18694 arm_canonicalize_symbol_name (char * name
)
18698 if (thumb_mode
&& (len
= strlen (name
)) > 5
18699 && streq (name
+ len
- 5, "/data"))
18700 *(name
+ len
- 5) = 0;
18705 /* Table of all register names defined by default. The user can
18706 define additional names with .req. Note that all register names
18707 should appear in both upper and lowercase variants. Some registers
18708 also have mixed-case names. */
18710 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18711 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18712 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18713 #define REGSET(p,t) \
18714 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18715 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18716 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18717 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18718 #define REGSETH(p,t) \
18719 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18720 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18721 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18722 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18723 #define REGSET2(p,t) \
18724 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18725 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18726 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18727 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18728 #define SPLRBANK(base,bank,t) \
18729 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18730 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18731 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18732 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18733 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18734 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18736 static const struct reg_entry reg_names
[] =
18738 /* ARM integer registers. */
18739 REGSET(r
, RN
), REGSET(R
, RN
),
18741 /* ATPCS synonyms. */
18742 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18743 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18744 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18746 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18747 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18748 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18750 /* Well-known aliases. */
18751 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18752 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18754 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18755 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18757 /* Coprocessor numbers. */
18758 REGSET(p
, CP
), REGSET(P
, CP
),
18760 /* Coprocessor register numbers. The "cr" variants are for backward
18762 REGSET(c
, CN
), REGSET(C
, CN
),
18763 REGSET(cr
, CN
), REGSET(CR
, CN
),
18765 /* ARM banked registers. */
18766 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18767 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18768 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18769 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18770 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18771 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18772 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18774 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18775 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18776 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18777 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18778 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18779 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18780 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18781 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18783 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18784 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18785 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18786 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18787 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18788 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18789 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18790 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18791 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18793 /* FPA registers. */
18794 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18795 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18797 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18798 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18800 /* VFP SP registers. */
18801 REGSET(s
,VFS
), REGSET(S
,VFS
),
18802 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18804 /* VFP DP Registers. */
18805 REGSET(d
,VFD
), REGSET(D
,VFD
),
18806 /* Extra Neon DP registers. */
18807 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18809 /* Neon QP registers. */
18810 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18812 /* VFP control registers. */
18813 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18814 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18815 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18816 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18817 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18818 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18820 /* Maverick DSP coprocessor registers. */
18821 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18822 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18824 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18825 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18826 REGDEF(dspsc
,0,DSPSC
),
18828 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18829 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18830 REGDEF(DSPSC
,0,DSPSC
),
18832 /* iWMMXt data registers - p0, c0-15. */
18833 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18835 /* iWMMXt control registers - p1, c0-3. */
18836 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18837 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18838 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18839 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18841 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18842 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18843 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18844 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18845 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18847 /* XScale accumulator registers. */
18848 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18854 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18855 within psr_required_here. */
18856 static const struct asm_psr psrs
[] =
18858 /* Backward compatibility notation. Note that "all" is no longer
18859 truly all possible PSR bits. */
18860 {"all", PSR_c
| PSR_f
},
18864 /* Individual flags. */
18870 /* Combinations of flags. */
18871 {"fs", PSR_f
| PSR_s
},
18872 {"fx", PSR_f
| PSR_x
},
18873 {"fc", PSR_f
| PSR_c
},
18874 {"sf", PSR_s
| PSR_f
},
18875 {"sx", PSR_s
| PSR_x
},
18876 {"sc", PSR_s
| PSR_c
},
18877 {"xf", PSR_x
| PSR_f
},
18878 {"xs", PSR_x
| PSR_s
},
18879 {"xc", PSR_x
| PSR_c
},
18880 {"cf", PSR_c
| PSR_f
},
18881 {"cs", PSR_c
| PSR_s
},
18882 {"cx", PSR_c
| PSR_x
},
18883 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18884 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18885 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18886 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18887 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18888 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18889 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18890 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18891 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18892 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18893 {"scf", PSR_s
| PSR_c
| PSR_f
},
18894 {"scx", PSR_s
| PSR_c
| PSR_x
},
18895 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18896 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18897 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18898 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18899 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18900 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18901 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18902 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18903 {"csf", PSR_c
| PSR_s
| PSR_f
},
18904 {"csx", PSR_c
| PSR_s
| PSR_x
},
18905 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18906 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18907 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18908 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18909 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18910 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18911 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18912 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18913 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18914 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18915 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18916 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18917 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18918 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18919 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18920 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18921 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18922 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18923 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18924 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18925 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18926 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18927 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18928 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18929 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18930 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18933 /* Table of V7M psr names. */
18934 static const struct asm_psr v7m_psrs
[] =
18936 {"apsr", 0x0 }, {"APSR", 0x0 },
18937 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18938 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18939 {"psr", 0x3 }, {"PSR", 0x3 },
18940 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18941 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18942 {"epsr", 0x6 }, {"EPSR", 0x6 },
18943 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18944 {"msp", 0x8 }, {"MSP", 0x8 },
18945 {"psp", 0x9 }, {"PSP", 0x9 },
18946 {"msplim", 0xa }, {"MSPLIM", 0xa },
18947 {"psplim", 0xb }, {"PSPLIM", 0xb },
18948 {"primask", 0x10}, {"PRIMASK", 0x10},
18949 {"basepri", 0x11}, {"BASEPRI", 0x11},
18950 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18951 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18952 {"control", 0x14}, {"CONTROL", 0x14},
18953 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18954 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18955 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18956 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18957 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18958 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18959 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18960 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18961 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18964 /* Table of all shift-in-operand names. */
18965 static const struct asm_shift_name shift_names
[] =
18967 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18968 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18969 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18970 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18971 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18972 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18975 /* Table of all explicit relocation names. */
18977 static struct reloc_entry reloc_names
[] =
18979 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18980 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18981 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18982 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18983 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18984 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18985 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18986 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18987 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18988 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18989 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18990 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18991 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18992 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18993 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18994 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18995 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18996 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19000 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19001 static const struct asm_cond conds
[] =
19005 {"cs", 0x2}, {"hs", 0x2},
19006 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19020 #define UL_BARRIER(L,U,CODE,FEAT) \
19021 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19022 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19024 static struct asm_barrier_opt barrier_opt_names
[] =
19026 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19027 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19028 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19029 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19030 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19031 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19032 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19033 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19034 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19035 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19036 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19037 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19038 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19039 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19040 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19041 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19046 /* Table of ARM-format instructions. */
19048 /* Macros for gluing together operand strings. N.B. In all cases
19049 other than OPS0, the trailing OP_stop comes from default
19050 zero-initialization of the unspecified elements of the array. */
19051 #define OPS0() { OP_stop, }
19052 #define OPS1(a) { OP_##a, }
19053 #define OPS2(a,b) { OP_##a,OP_##b, }
19054 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19055 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19056 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19057 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19059 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19060 This is useful when mixing operands for ARM and THUMB, i.e. using the
19061 MIX_ARM_THUMB_OPERANDS macro.
19062 In order to use these macros, prefix the number of operands with _
19064 #define OPS_1(a) { a, }
19065 #define OPS_2(a,b) { a,b, }
19066 #define OPS_3(a,b,c) { a,b,c, }
19067 #define OPS_4(a,b,c,d) { a,b,c,d, }
19068 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19069 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19071 /* These macros abstract out the exact format of the mnemonic table and
19072 save some repeated characters. */
19074 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19075 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19076 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19077 THUMB_VARIANT, do_##ae, do_##te }
19079 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19080 a T_MNEM_xyz enumerator. */
19081 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19082 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19083 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19084 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19086 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19087 infix after the third character. */
19088 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19089 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19090 THUMB_VARIANT, do_##ae, do_##te }
19091 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19092 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19093 THUMB_VARIANT, do_##ae, do_##te }
19094 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19095 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19096 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19097 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19098 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19099 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19100 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19101 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19103 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19104 field is still 0xE. Many of the Thumb variants can be executed
19105 conditionally, so this is checked separately. */
19106 #define TUE(mnem, op, top, nops, ops, ae, te) \
19107 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19108 THUMB_VARIANT, do_##ae, do_##te }
19110 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19111 Used by mnemonics that have very minimal differences in the encoding for
19112 ARM and Thumb variants and can be handled in a common function. */
19113 #define TUEc(mnem, op, top, nops, ops, en) \
19114 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19115 THUMB_VARIANT, do_##en, do_##en }
19117 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19118 condition code field. */
19119 #define TUF(mnem, op, top, nops, ops, ae, te) \
19120 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19121 THUMB_VARIANT, do_##ae, do_##te }
19123 /* ARM-only variants of all the above. */
19124 #define CE(mnem, op, nops, ops, ae) \
19125 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19127 #define C3(mnem, op, nops, ops, ae) \
19128 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19130 /* Legacy mnemonics that always have conditional infix after the third
19132 #define CL(mnem, op, nops, ops, ae) \
19133 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19134 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19136 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19137 #define cCE(mnem, op, nops, ops, ae) \
19138 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19140 /* Legacy coprocessor instructions where conditional infix and conditional
19141 suffix are ambiguous. For consistency this includes all FPA instructions,
19142 not just the potentially ambiguous ones. */
19143 #define cCL(mnem, op, nops, ops, ae) \
19144 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19145 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19147 /* Coprocessor, takes either a suffix or a position-3 infix
19148 (for an FPA corner case). */
19149 #define C3E(mnem, op, nops, ops, ae) \
19150 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19151 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19153 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19154 { m1 #m2 m3, OPS##nops ops, \
19155 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19156 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19158 #define CM(m1, m2, op, nops, ops, ae) \
19159 xCM_ (m1, , m2, op, nops, ops, ae), \
19160 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19161 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19162 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19163 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19164 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19165 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19166 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19167 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19168 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19169 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19170 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19171 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19172 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19173 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19174 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19175 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19176 xCM_ (m1, le, m2, op, nops, ops, ae), \
19177 xCM_ (m1, al, m2, op, nops, ops, ae)
19179 #define UE(mnem, op, nops, ops, ae) \
19180 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19182 #define UF(mnem, op, nops, ops, ae) \
19183 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19185 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19186 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19187 use the same encoding function for each. */
19188 #define NUF(mnem, op, nops, ops, enc) \
19189 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19190 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19192 /* Neon data processing, version which indirects through neon_enc_tab for
19193 the various overloaded versions of opcodes. */
19194 #define nUF(mnem, op, nops, ops, enc) \
19195 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19196 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19198 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19200 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19201 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19202 THUMB_VARIANT, do_##enc, do_##enc }
19204 #define NCE(mnem, op, nops, ops, enc) \
19205 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19207 #define NCEF(mnem, op, nops, ops, enc) \
19208 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19210 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19211 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19212 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19213 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19215 #define nCE(mnem, op, nops, ops, enc) \
19216 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19218 #define nCEF(mnem, op, nops, ops, enc) \
19219 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19223 static const struct asm_opcode insns
[] =
19225 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19226 #define THUMB_VARIANT & arm_ext_v4t
19227 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19228 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19229 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19230 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19231 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19232 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19233 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19234 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19235 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19236 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19237 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19238 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19239 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19240 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19241 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19242 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19244 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19245 for setting PSR flag bits. They are obsolete in V6 and do not
19246 have Thumb equivalents. */
19247 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19248 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19249 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19250 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19251 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19252 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19253 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19254 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19255 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19257 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19258 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19259 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19260 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19262 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19263 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19264 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19266 OP_ADDRGLDR
),ldst
, t_ldst
),
19267 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19269 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19270 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19271 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19272 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19273 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19274 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19276 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19277 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19278 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19279 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19282 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19283 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19284 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19285 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19287 /* Thumb-compatibility pseudo ops. */
19288 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19289 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19290 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19291 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19292 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19293 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19294 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19295 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19296 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19297 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19298 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19299 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19301 /* These may simplify to neg. */
19302 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19303 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19305 #undef THUMB_VARIANT
19306 #define THUMB_VARIANT & arm_ext_v6
19308 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19310 /* V1 instructions with no Thumb analogue prior to V6T2. */
19311 #undef THUMB_VARIANT
19312 #define THUMB_VARIANT & arm_ext_v6t2
19314 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19315 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19316 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19318 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19319 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19320 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19321 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19323 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19324 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19326 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19327 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19329 /* V1 instructions with no Thumb analogue at all. */
19330 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19331 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19333 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19334 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19335 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19336 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19337 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19338 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19339 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19340 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19343 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19344 #undef THUMB_VARIANT
19345 #define THUMB_VARIANT & arm_ext_v4t
19347 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19348 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19350 #undef THUMB_VARIANT
19351 #define THUMB_VARIANT & arm_ext_v6t2
19353 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19354 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19356 /* Generic coprocessor instructions. */
19357 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19358 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19359 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19360 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19361 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19362 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19363 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19366 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19368 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19369 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19372 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19373 #undef THUMB_VARIANT
19374 #define THUMB_VARIANT & arm_ext_msr
19376 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19377 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19380 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19381 #undef THUMB_VARIANT
19382 #define THUMB_VARIANT & arm_ext_v6t2
19384 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19385 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19386 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19387 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19388 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19389 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19390 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19391 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19394 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19395 #undef THUMB_VARIANT
19396 #define THUMB_VARIANT & arm_ext_v4t
19398 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19399 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19400 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19401 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19402 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19403 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19406 #define ARM_VARIANT & arm_ext_v4t_5
19408 /* ARM Architecture 4T. */
19409 /* Note: bx (and blx) are required on V5, even if the processor does
19410 not support Thumb. */
19411 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19414 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19415 #undef THUMB_VARIANT
19416 #define THUMB_VARIANT & arm_ext_v5t
19418 /* Note: blx has 2 variants; the .value coded here is for
19419 BLX(2). Only this variant has conditional execution. */
19420 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19421 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19423 #undef THUMB_VARIANT
19424 #define THUMB_VARIANT & arm_ext_v6t2
19426 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19427 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19428 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19429 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19430 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19431 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19432 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19433 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19436 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19437 #undef THUMB_VARIANT
19438 #define THUMB_VARIANT & arm_ext_v5exp
19440 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19441 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19442 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19443 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19445 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19446 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19448 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19449 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19450 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19451 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19453 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19454 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19455 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19456 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19458 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19459 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19461 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19462 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19463 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19464 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19467 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19468 #undef THUMB_VARIANT
19469 #define THUMB_VARIANT & arm_ext_v6t2
19471 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19472 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19474 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19475 ADDRGLDRS
), ldrd
, t_ldstd
),
19477 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19478 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19481 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19483 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19486 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19487 #undef THUMB_VARIANT
19488 #define THUMB_VARIANT & arm_ext_v6
19490 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19491 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19492 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19493 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19494 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19495 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19496 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19497 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19498 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19499 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19504 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19505 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19507 #undef THUMB_VARIANT
19508 #define THUMB_VARIANT & arm_ext_v6t2
19510 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19511 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19513 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19514 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19516 /* ARM V6 not included in V7M. */
19517 #undef THUMB_VARIANT
19518 #define THUMB_VARIANT & arm_ext_v6_notm
19519 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19520 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19521 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19522 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19523 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19524 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19525 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19526 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19527 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19528 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19529 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19530 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19531 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19532 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19533 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19534 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19535 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19536 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19537 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19539 /* ARM V6 not included in V7M (eg. integer SIMD). */
19540 #undef THUMB_VARIANT
19541 #define THUMB_VARIANT & arm_ext_v6_dsp
19542 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19543 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19544 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19545 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19546 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19547 /* Old name for QASX. */
19548 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19549 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19550 /* Old name for QSAX. */
19551 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19552 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19553 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19554 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19555 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19556 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19557 /* Old name for SASX. */
19558 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19559 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19560 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19561 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19562 /* Old name for SHASX. */
19563 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19564 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19565 /* Old name for SHSAX. */
19566 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19567 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19569 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19570 /* Old name for SSAX. */
19571 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19572 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19573 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19574 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19576 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19577 /* Old name for UASX. */
19578 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19579 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19580 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19582 /* Old name for UHASX. */
19583 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19585 /* Old name for UHSAX. */
19586 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19587 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19588 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19589 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19590 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19591 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19592 /* Old name for UQASX. */
19593 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19594 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19595 /* Old name for UQSAX. */
19596 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19597 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19598 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19599 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19600 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19601 /* Old name for USAX. */
19602 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19603 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19604 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19605 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19606 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19607 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19608 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19609 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19610 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19611 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19612 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19613 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19614 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19615 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19616 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19617 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19618 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19619 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19620 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19621 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19622 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19623 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19624 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19625 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19626 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19627 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19628 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19629 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19630 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19631 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19632 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19633 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19634 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19635 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19638 #define ARM_VARIANT & arm_ext_v6k
19639 #undef THUMB_VARIANT
19640 #define THUMB_VARIANT & arm_ext_v6k
19642 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19643 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19644 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19645 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19647 #undef THUMB_VARIANT
19648 #define THUMB_VARIANT & arm_ext_v6_notm
19649 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19651 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19652 RRnpcb
), strexd
, t_strexd
),
19654 #undef THUMB_VARIANT
19655 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19656 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19658 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19660 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19662 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19664 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19667 #define ARM_VARIANT & arm_ext_sec
19668 #undef THUMB_VARIANT
19669 #define THUMB_VARIANT & arm_ext_sec
19671 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19674 #define ARM_VARIANT & arm_ext_virt
19675 #undef THUMB_VARIANT
19676 #define THUMB_VARIANT & arm_ext_virt
19678 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19679 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19682 #define ARM_VARIANT & arm_ext_pan
19683 #undef THUMB_VARIANT
19684 #define THUMB_VARIANT & arm_ext_pan
19686 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19689 #define ARM_VARIANT & arm_ext_v6t2
19690 #undef THUMB_VARIANT
19691 #define THUMB_VARIANT & arm_ext_v6t2
19693 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19694 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19695 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19696 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19698 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19699 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19701 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19702 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19703 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19704 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19706 #undef THUMB_VARIANT
19707 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19708 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19709 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19711 /* Thumb-only instructions. */
19713 #define ARM_VARIANT NULL
19714 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19715 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19717 /* ARM does not really have an IT instruction, so always allow it.
19718 The opcode is copied from Thumb in order to allow warnings in
19719 -mimplicit-it=[never | arm] modes. */
19721 #define ARM_VARIANT & arm_ext_v1
19722 #undef THUMB_VARIANT
19723 #define THUMB_VARIANT & arm_ext_v6t2
19725 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19726 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19727 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19728 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19729 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19730 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19731 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19732 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19733 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19734 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19735 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19736 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19737 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19738 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19739 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19740 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19741 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19742 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19744 /* Thumb2 only instructions. */
19746 #define ARM_VARIANT NULL
19748 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19749 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19750 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19751 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19752 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19753 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19755 /* Hardware division instructions. */
19757 #define ARM_VARIANT & arm_ext_adiv
19758 #undef THUMB_VARIANT
19759 #define THUMB_VARIANT & arm_ext_div
19761 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19762 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19764 /* ARM V6M/V7 instructions. */
19766 #define ARM_VARIANT & arm_ext_barrier
19767 #undef THUMB_VARIANT
19768 #define THUMB_VARIANT & arm_ext_barrier
19770 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19771 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19772 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19774 /* ARM V7 instructions. */
19776 #define ARM_VARIANT & arm_ext_v7
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_v7
19780 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19781 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19784 #define ARM_VARIANT & arm_ext_mp
19785 #undef THUMB_VARIANT
19786 #define THUMB_VARIANT & arm_ext_mp
19788 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19790 /* AArchv8 instructions. */
19792 #define ARM_VARIANT & arm_ext_v8
19794 /* Instructions shared between armv8-a and armv8-m. */
19795 #undef THUMB_VARIANT
19796 #define THUMB_VARIANT & arm_ext_atomics
19798 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19799 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19800 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19801 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19802 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19803 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19804 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19805 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19806 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19807 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19809 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19811 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19813 #undef THUMB_VARIANT
19814 #define THUMB_VARIANT & arm_ext_v8
19816 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19817 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19818 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19820 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19822 /* ARMv8 T32 only. */
19824 #define ARM_VARIANT NULL
19825 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19826 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19827 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19829 /* FP for ARMv8. */
19831 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19832 #undef THUMB_VARIANT
19833 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19835 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19836 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19837 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19838 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19839 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19840 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19841 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19842 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19843 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19844 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19845 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19846 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19847 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19848 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19849 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19850 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19851 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19853 /* Crypto v1 extensions. */
19855 #define ARM_VARIANT & fpu_crypto_ext_armv8
19856 #undef THUMB_VARIANT
19857 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19859 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19860 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19861 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19862 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19863 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19864 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19865 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19866 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19867 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19868 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19869 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19870 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19871 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19872 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19875 #define ARM_VARIANT & crc_ext_armv8
19876 #undef THUMB_VARIANT
19877 #define THUMB_VARIANT & crc_ext_armv8
19878 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19879 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19880 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19881 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19882 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19883 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19885 /* ARMv8.2 RAS extension. */
19887 #define ARM_VARIANT & arm_ext_ras
19888 #undef THUMB_VARIANT
19889 #define THUMB_VARIANT & arm_ext_ras
19890 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19893 #define ARM_VARIANT & arm_ext_v8_3
19894 #undef THUMB_VARIANT
19895 #define THUMB_VARIANT & arm_ext_v8_3
19896 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19897 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19898 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19901 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19902 #undef THUMB_VARIANT
19903 #define THUMB_VARIANT NULL
19905 cCE("wfs", e200110
, 1, (RR
), rd
),
19906 cCE("rfs", e300110
, 1, (RR
), rd
),
19907 cCE("wfc", e400110
, 1, (RR
), rd
),
19908 cCE("rfc", e500110
, 1, (RR
), rd
),
19910 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19911 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19912 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19913 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19915 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19916 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19917 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19918 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19920 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20115 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20116 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20117 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20118 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20119 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20120 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20121 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20122 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20123 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20124 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20125 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20126 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20128 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20130 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20134 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20136 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20141 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20201 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20206 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20208 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20211 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20214 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20219 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20221 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20224 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20227 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20232 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20284 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20285 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20286 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20287 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20288 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20289 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20290 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20291 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20292 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20293 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20294 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20295 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20297 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20298 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20299 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20300 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20302 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20303 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20304 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20305 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20306 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20307 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20308 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20309 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20310 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20311 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20312 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20313 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20315 /* The implementation of the FIX instruction is broken on some
20316 assemblers, in that it accepts a precision specifier as well as a
20317 rounding specifier, despite the fact that this is meaningless.
20318 To be more compatible, we accept it as well, though of course it
20319 does not set any bits. */
20320 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20321 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20322 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20323 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20324 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20325 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20326 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20327 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20328 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20329 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20330 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20331 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20332 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20334 /* Instructions that were new with the real FPA, call them V2. */
20336 #define ARM_VARIANT & fpu_fpa_ext_v2
20338 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20339 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20340 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20341 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20342 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20343 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20346 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20348 /* Moves and type conversions. */
20349 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20350 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20351 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20352 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20353 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20354 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20355 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20356 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20357 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20358 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20359 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20360 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20361 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20362 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20364 /* Memory operations. */
20365 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20366 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20367 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20368 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20369 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20370 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20371 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20372 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20373 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20374 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20375 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20376 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20377 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20378 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20379 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20380 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20381 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20382 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20384 /* Monadic operations. */
20385 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20386 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20387 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20389 /* Dyadic operations. */
20390 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20391 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20392 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20393 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20394 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20395 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20396 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20397 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20398 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20401 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20402 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20403 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20404 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20406 /* Double precision load/store are still present on single precision
20407 implementations. */
20408 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20409 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20410 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20411 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20412 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20413 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20414 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20415 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20416 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20417 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20420 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20422 /* Moves and type conversions. */
20423 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20424 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20425 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20426 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20427 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20428 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20429 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20430 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20431 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20432 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20433 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20434 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20435 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20437 /* Monadic operations. */
20438 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20439 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20440 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20442 /* Dyadic operations. */
20443 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20444 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20445 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20446 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20447 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20448 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20449 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20450 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20451 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20454 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20455 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20456 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20457 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20460 #define ARM_VARIANT & fpu_vfp_ext_v2
20462 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20463 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20464 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20465 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20467 /* Instructions which may belong to either the Neon or VFP instruction sets.
20468 Individual encoder functions perform additional architecture checks. */
20470 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20471 #undef THUMB_VARIANT
20472 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20474 /* These mnemonics are unique to VFP. */
20475 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20476 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20477 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20478 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20479 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20480 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20481 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20482 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20483 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20484 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20486 /* Mnemonics shared by Neon and VFP. */
20487 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20488 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20489 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20491 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20492 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20494 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20495 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20497 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20498 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20499 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20500 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20501 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20502 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20503 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20504 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20506 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20507 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20508 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20509 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20512 /* NOTE: All VMOV encoding is special-cased! */
20513 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20514 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20517 #define ARM_VARIANT & arm_ext_fp16
20518 #undef THUMB_VARIANT
20519 #define THUMB_VARIANT & arm_ext_fp16
20520 /* New instructions added from v8.2, allowing the extraction and insertion of
20521 the upper 16 bits of a 32-bit vector register. */
20522 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20523 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20525 #undef THUMB_VARIANT
20526 #define THUMB_VARIANT & fpu_neon_ext_v1
20528 #define ARM_VARIANT & fpu_neon_ext_v1
20530 /* Data processing with three registers of the same length. */
20531 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20532 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20533 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20534 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20535 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20536 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20537 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20538 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20539 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20540 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20541 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20542 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20543 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20544 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20545 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20546 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20547 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20548 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20549 /* If not immediate, fall back to neon_dyadic_i64_su.
20550 shl_imm should accept I8 I16 I32 I64,
20551 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20552 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20553 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20554 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20555 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20556 /* Logic ops, types optional & ignored. */
20557 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20558 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20559 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20560 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20561 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20562 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20563 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20564 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20565 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20566 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20567 /* Bitfield ops, untyped. */
20568 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20569 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20570 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20571 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20572 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20573 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20574 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20575 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20576 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20577 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20578 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20579 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20580 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20581 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20582 back to neon_dyadic_if_su. */
20583 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20584 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20585 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20586 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20587 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20588 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20589 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20590 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20591 /* Comparison. Type I8 I16 I32 F32. */
20592 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20593 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20594 /* As above, D registers only. */
20595 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20596 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20597 /* Int and float variants, signedness unimportant. */
20598 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20599 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20600 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20601 /* Add/sub take types I8 I16 I32 I64 F32. */
20602 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20603 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20604 /* vtst takes sizes 8, 16, 32. */
20605 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20606 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20607 /* VMUL takes I8 I16 I32 F32 P8. */
20608 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20609 /* VQD{R}MULH takes S16 S32. */
20610 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20611 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20612 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20613 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20614 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20615 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20616 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20617 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20618 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20619 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20620 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20621 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20622 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20623 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20624 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20625 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20626 /* ARM v8.1 extension. */
20627 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20628 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20629 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20630 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20632 /* Two address, int/float. Types S8 S16 S32 F32. */
20633 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20634 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20636 /* Data processing with two registers and a shift amount. */
20637 /* Right shifts, and variants with rounding.
20638 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20639 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20640 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20641 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20642 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20643 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20644 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20645 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20646 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20647 /* Shift and insert. Sizes accepted 8 16 32 64. */
20648 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20649 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20650 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20651 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20652 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20653 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20654 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20655 /* Right shift immediate, saturating & narrowing, with rounding variants.
20656 Types accepted S16 S32 S64 U16 U32 U64. */
20657 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20658 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20659 /* As above, unsigned. Types accepted S16 S32 S64. */
20660 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20661 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20662 /* Right shift narrowing. Types accepted I16 I32 I64. */
20663 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20664 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20665 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20666 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20667 /* CVT with optional immediate for fixed-point variant. */
20668 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20670 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20671 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20673 /* Data processing, three registers of different lengths. */
20674 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20675 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20676 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20677 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20678 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20679 /* If not scalar, fall back to neon_dyadic_long.
20680 Vector types as above, scalar types S16 S32 U16 U32. */
20681 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20682 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20683 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20684 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20685 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20686 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20687 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20688 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20689 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20690 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20691 /* Saturating doubling multiplies. Types S16 S32. */
20692 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20693 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20694 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20695 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20696 S16 S32 U16 U32. */
20697 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20699 /* Extract. Size 8. */
20700 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20701 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20703 /* Two registers, miscellaneous. */
20704 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20705 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20706 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20707 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20708 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20709 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20710 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20711 /* Vector replicate. Sizes 8 16 32. */
20712 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20713 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20714 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20715 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20716 /* VMOVN. Types I16 I32 I64. */
20717 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20718 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20719 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20720 /* VQMOVUN. Types S16 S32 S64. */
20721 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20722 /* VZIP / VUZP. Sizes 8 16 32. */
20723 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20724 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20725 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20726 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20727 /* VQABS / VQNEG. Types S8 S16 S32. */
20728 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20729 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20730 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20731 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20732 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20733 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20734 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20735 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20736 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20737 /* Reciprocal estimates. Types U32 F16 F32. */
20738 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20739 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20740 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20741 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20742 /* VCLS. Types S8 S16 S32. */
20743 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20744 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20745 /* VCLZ. Types I8 I16 I32. */
20746 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20747 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20748 /* VCNT. Size 8. */
20749 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20750 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20751 /* Two address, untyped. */
20752 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20753 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20754 /* VTRN. Sizes 8 16 32. */
20755 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20756 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20758 /* Table lookup. Size 8. */
20759 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20760 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20762 #undef THUMB_VARIANT
20763 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20765 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20767 /* Neon element/structure load/store. */
20768 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20769 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20770 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20771 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20772 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20773 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20774 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20775 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20777 #undef THUMB_VARIANT
20778 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20780 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20781 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20782 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20783 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20784 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20785 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20786 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20787 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20788 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20789 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20791 #undef THUMB_VARIANT
20792 #define THUMB_VARIANT & fpu_vfp_ext_v3
20794 #define ARM_VARIANT & fpu_vfp_ext_v3
20796 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20797 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20798 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20799 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20800 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20801 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20802 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20803 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20804 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20807 #define ARM_VARIANT & fpu_vfp_ext_fma
20808 #undef THUMB_VARIANT
20809 #define THUMB_VARIANT & fpu_vfp_ext_fma
20810 /* Mnemonics shared by Neon and VFP. These are included in the
20811 VFP FMA variant; NEON and VFP FMA always includes the NEON
20812 FMA instructions. */
20813 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20814 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20815 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20816 the v form should always be used. */
20817 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20818 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20819 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20820 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20821 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20822 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20824 #undef THUMB_VARIANT
20826 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20828 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20829 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20830 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20831 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20832 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20833 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20834 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20835 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20838 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20840 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20841 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20842 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20843 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20844 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20845 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20846 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20847 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20848 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20849 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20850 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20851 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20852 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20853 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20854 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20855 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20856 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20857 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20858 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20859 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20860 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20861 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20862 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20863 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20864 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20865 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20866 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20867 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20868 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20869 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20870 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20871 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20872 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20873 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20874 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20875 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20876 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20877 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20887 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20891 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20907 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20908 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20909 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20910 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20924 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20926 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20928 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20929 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20938 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20939 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20940 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20941 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20942 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20943 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20944 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20945 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20946 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20947 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20948 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20949 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20950 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20951 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20952 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20953 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20954 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20955 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20956 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20957 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20958 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20959 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20960 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20961 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20962 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20963 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20964 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20965 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20966 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20967 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20968 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20969 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20970 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20971 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20972 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20973 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20974 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20975 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20976 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20977 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20978 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20979 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20980 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20981 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20982 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20983 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20984 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20985 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20986 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20987 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20988 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20989 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20990 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20991 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20992 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20993 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20994 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20995 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20996 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20997 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20999 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21004 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21006 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21007 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21008 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21009 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21010 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21011 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21012 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21013 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21014 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21021 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21022 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21023 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21024 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21025 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21026 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21027 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21046 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21050 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21051 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21053 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21054 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21055 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21056 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21057 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21058 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21059 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21060 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21061 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21062 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21065 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21067 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21068 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21069 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21070 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21071 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21072 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21073 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21074 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21075 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21076 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21077 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21078 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21079 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21080 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21081 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21082 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21083 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21084 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21085 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21086 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21087 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21088 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21089 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21090 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21091 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21092 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21093 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21094 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21095 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21096 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21097 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21098 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21099 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21100 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21101 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21102 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21103 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21104 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21105 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21106 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21107 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21108 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21109 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21110 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21111 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21112 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21113 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21114 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21115 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21116 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21117 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21118 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21119 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21120 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21121 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21122 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21123 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21124 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21125 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21126 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21127 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21128 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21129 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21130 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21131 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21132 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21133 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21134 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21135 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21136 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21137 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21138 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21139 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21140 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21141 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21142 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21144 /* ARMv8-M instructions. */
21146 #define ARM_VARIANT NULL
21147 #undef THUMB_VARIANT
21148 #define THUMB_VARIANT & arm_ext_v8m
21149 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21150 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21151 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21152 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21153 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21154 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21155 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21157 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21158 instructions behave as nop if no VFP is present. */
21159 #undef THUMB_VARIANT
21160 #define THUMB_VARIANT & arm_ext_v8m_main
21161 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21162 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21165 #undef THUMB_VARIANT
21191 /* MD interface: bits in the object file. */
21193 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21194 for use in the a.out file, and stores them in the array pointed to by buf.
21195 This knows about the endian-ness of the target machine and does
21196 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21197 2 (short) and 4 (long) Floating numbers are put out as a series of
21198 LITTLENUMS (shorts, here at least). */
21201 md_number_to_chars (char * buf
, valueT val
, int n
)
21203 if (target_big_endian
)
21204 number_to_chars_bigendian (buf
, val
, n
);
21206 number_to_chars_littleendian (buf
, val
, n
);
21210 md_chars_to_number (char * buf
, int n
)
21213 unsigned char * where
= (unsigned char *) buf
;
21215 if (target_big_endian
)
21220 result
|= (*where
++ & 255);
21228 result
|= (where
[n
] & 255);
21235 /* MD interface: Sections. */
21237 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21238 that an rs_machine_dependent frag may reach. */
21241 arm_frag_max_var (fragS
*fragp
)
21243 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21244 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21246 Note that we generate relaxable instructions even for cases that don't
21247 really need it, like an immediate that's a trivial constant. So we're
21248 overestimating the instruction size for some of those cases. Rather
21249 than putting more intelligence here, it would probably be better to
21250 avoid generating a relaxation frag in the first place when it can be
21251 determined up front that a short instruction will suffice. */
21253 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21257 /* Estimate the size of a frag before relaxing. Assume everything fits in
21261 md_estimate_size_before_relax (fragS
* fragp
,
21262 segT segtype ATTRIBUTE_UNUSED
)
21268 /* Convert a machine dependent frag. */
21271 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21273 unsigned long insn
;
21274 unsigned long old_op
;
21282 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21284 old_op
= bfd_get_16(abfd
, buf
);
21285 if (fragp
->fr_symbol
)
21287 exp
.X_op
= O_symbol
;
21288 exp
.X_add_symbol
= fragp
->fr_symbol
;
21292 exp
.X_op
= O_constant
;
21294 exp
.X_add_number
= fragp
->fr_offset
;
21295 opcode
= fragp
->fr_subtype
;
21298 case T_MNEM_ldr_pc
:
21299 case T_MNEM_ldr_pc2
:
21300 case T_MNEM_ldr_sp
:
21301 case T_MNEM_str_sp
:
21308 if (fragp
->fr_var
== 4)
21310 insn
= THUMB_OP32 (opcode
);
21311 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21313 insn
|= (old_op
& 0x700) << 4;
21317 insn
|= (old_op
& 7) << 12;
21318 insn
|= (old_op
& 0x38) << 13;
21320 insn
|= 0x00000c00;
21321 put_thumb32_insn (buf
, insn
);
21322 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21326 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21328 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21331 if (fragp
->fr_var
== 4)
21333 insn
= THUMB_OP32 (opcode
);
21334 insn
|= (old_op
& 0xf0) << 4;
21335 put_thumb32_insn (buf
, insn
);
21336 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21340 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21341 exp
.X_add_number
-= 4;
21349 if (fragp
->fr_var
== 4)
21351 int r0off
= (opcode
== T_MNEM_mov
21352 || opcode
== T_MNEM_movs
) ? 0 : 8;
21353 insn
= THUMB_OP32 (opcode
);
21354 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21355 insn
|= (old_op
& 0x700) << r0off
;
21356 put_thumb32_insn (buf
, insn
);
21357 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21361 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21366 if (fragp
->fr_var
== 4)
21368 insn
= THUMB_OP32(opcode
);
21369 put_thumb32_insn (buf
, insn
);
21370 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21373 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21377 if (fragp
->fr_var
== 4)
21379 insn
= THUMB_OP32(opcode
);
21380 insn
|= (old_op
& 0xf00) << 14;
21381 put_thumb32_insn (buf
, insn
);
21382 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21385 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21388 case T_MNEM_add_sp
:
21389 case T_MNEM_add_pc
:
21390 case T_MNEM_inc_sp
:
21391 case T_MNEM_dec_sp
:
21392 if (fragp
->fr_var
== 4)
21394 /* ??? Choose between add and addw. */
21395 insn
= THUMB_OP32 (opcode
);
21396 insn
|= (old_op
& 0xf0) << 4;
21397 put_thumb32_insn (buf
, insn
);
21398 if (opcode
== T_MNEM_add_pc
)
21399 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21401 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21404 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21412 if (fragp
->fr_var
== 4)
21414 insn
= THUMB_OP32 (opcode
);
21415 insn
|= (old_op
& 0xf0) << 4;
21416 insn
|= (old_op
& 0xf) << 16;
21417 put_thumb32_insn (buf
, insn
);
21418 if (insn
& (1 << 20))
21419 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21421 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21424 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21430 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21431 (enum bfd_reloc_code_real
) reloc_type
);
21432 fixp
->fx_file
= fragp
->fr_file
;
21433 fixp
->fx_line
= fragp
->fr_line
;
21434 fragp
->fr_fix
+= fragp
->fr_var
;
21436 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21437 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21438 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21439 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21442 /* Return the size of a relaxable immediate operand instruction.
21443 SHIFT and SIZE specify the form of the allowable immediate. */
21445 relax_immediate (fragS
*fragp
, int size
, int shift
)
21451 /* ??? Should be able to do better than this. */
21452 if (fragp
->fr_symbol
)
21455 low
= (1 << shift
) - 1;
21456 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21457 offset
= fragp
->fr_offset
;
21458 /* Force misaligned offsets to 32-bit variant. */
21461 if (offset
& ~mask
)
21466 /* Get the address of a symbol during relaxation. */
21468 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21474 sym
= fragp
->fr_symbol
;
21475 sym_frag
= symbol_get_frag (sym
);
21476 know (S_GET_SEGMENT (sym
) != absolute_section
21477 || sym_frag
== &zero_address_frag
);
21478 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21480 /* If frag has yet to be reached on this pass, assume it will
21481 move by STRETCH just as we did. If this is not so, it will
21482 be because some frag between grows, and that will force
21486 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21490 /* Adjust stretch for any alignment frag. Note that if have
21491 been expanding the earlier code, the symbol may be
21492 defined in what appears to be an earlier frag. FIXME:
21493 This doesn't handle the fr_subtype field, which specifies
21494 a maximum number of bytes to skip when doing an
21496 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21498 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21501 stretch
= - ((- stretch
)
21502 & ~ ((1 << (int) f
->fr_offset
) - 1));
21504 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21516 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21519 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21524 /* Assume worst case for symbols not known to be in the same section. */
21525 if (fragp
->fr_symbol
== NULL
21526 || !S_IS_DEFINED (fragp
->fr_symbol
)
21527 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21528 || S_IS_WEAK (fragp
->fr_symbol
))
21531 val
= relaxed_symbol_addr (fragp
, stretch
);
21532 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21533 addr
= (addr
+ 4) & ~3;
21534 /* Force misaligned targets to 32-bit variant. */
21538 if (val
< 0 || val
> 1020)
21543 /* Return the size of a relaxable add/sub immediate instruction. */
21545 relax_addsub (fragS
*fragp
, asection
*sec
)
21550 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21551 op
= bfd_get_16(sec
->owner
, buf
);
21552 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21553 return relax_immediate (fragp
, 8, 0);
21555 return relax_immediate (fragp
, 3, 0);
21558 /* Return TRUE iff the definition of symbol S could be pre-empted
21559 (overridden) at link or load time. */
21561 symbol_preemptible (symbolS
*s
)
21563 /* Weak symbols can always be pre-empted. */
21567 /* Non-global symbols cannot be pre-empted. */
21568 if (! S_IS_EXTERNAL (s
))
21572 /* In ELF, a global symbol can be marked protected, or private. In that
21573 case it can't be pre-empted (other definitions in the same link unit
21574 would violate the ODR). */
21575 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21579 /* Other global symbols might be pre-empted. */
21583 /* Return the size of a relaxable branch instruction. BITS is the
21584 size of the offset field in the narrow instruction. */
21587 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21593 /* Assume worst case for symbols not known to be in the same section. */
21594 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21595 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21596 || S_IS_WEAK (fragp
->fr_symbol
))
21600 /* A branch to a function in ARM state will require interworking. */
21601 if (S_IS_DEFINED (fragp
->fr_symbol
)
21602 && ARM_IS_FUNC (fragp
->fr_symbol
))
21606 if (symbol_preemptible (fragp
->fr_symbol
))
21609 val
= relaxed_symbol_addr (fragp
, stretch
);
21610 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21613 /* Offset is a signed value *2 */
21615 if (val
>= limit
|| val
< -limit
)
21621 /* Relax a machine dependent frag. This returns the amount by which
21622 the current size of the frag should change. */
21625 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21630 oldsize
= fragp
->fr_var
;
21631 switch (fragp
->fr_subtype
)
21633 case T_MNEM_ldr_pc2
:
21634 newsize
= relax_adr (fragp
, sec
, stretch
);
21636 case T_MNEM_ldr_pc
:
21637 case T_MNEM_ldr_sp
:
21638 case T_MNEM_str_sp
:
21639 newsize
= relax_immediate (fragp
, 8, 2);
21643 newsize
= relax_immediate (fragp
, 5, 2);
21647 newsize
= relax_immediate (fragp
, 5, 1);
21651 newsize
= relax_immediate (fragp
, 5, 0);
21654 newsize
= relax_adr (fragp
, sec
, stretch
);
21660 newsize
= relax_immediate (fragp
, 8, 0);
21663 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21666 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21668 case T_MNEM_add_sp
:
21669 case T_MNEM_add_pc
:
21670 newsize
= relax_immediate (fragp
, 8, 2);
21672 case T_MNEM_inc_sp
:
21673 case T_MNEM_dec_sp
:
21674 newsize
= relax_immediate (fragp
, 7, 2);
21680 newsize
= relax_addsub (fragp
, sec
);
21686 fragp
->fr_var
= newsize
;
21687 /* Freeze wide instructions that are at or before the same location as
21688 in the previous pass. This avoids infinite loops.
21689 Don't freeze them unconditionally because targets may be artificially
21690 misaligned by the expansion of preceding frags. */
21691 if (stretch
<= 0 && newsize
> 2)
21693 md_convert_frag (sec
->owner
, sec
, fragp
);
21697 return newsize
- oldsize
;
21700 /* Round up a section size to the appropriate boundary. */
21703 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21706 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21707 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21709 /* For a.out, force the section size to be aligned. If we don't do
21710 this, BFD will align it for us, but it will not write out the
21711 final bytes of the section. This may be a bug in BFD, but it is
21712 easier to fix it here since that is how the other a.out targets
21716 align
= bfd_get_section_alignment (stdoutput
, segment
);
21717 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21724 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21725 of an rs_align_code fragment. */
21728 arm_handle_align (fragS
* fragP
)
21730 static unsigned char const arm_noop
[2][2][4] =
21733 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21734 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21737 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21738 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21741 static unsigned char const thumb_noop
[2][2][2] =
21744 {0xc0, 0x46}, /* LE */
21745 {0x46, 0xc0}, /* BE */
21748 {0x00, 0xbf}, /* LE */
21749 {0xbf, 0x00} /* BE */
21752 static unsigned char const wide_thumb_noop
[2][4] =
21753 { /* Wide Thumb-2 */
21754 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21755 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21758 unsigned bytes
, fix
, noop_size
;
21760 const unsigned char * noop
;
21761 const unsigned char *narrow_noop
= NULL
;
21766 if (fragP
->fr_type
!= rs_align_code
)
21769 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21770 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21773 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21774 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21776 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21778 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21780 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21781 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21783 narrow_noop
= thumb_noop
[1][target_big_endian
];
21784 noop
= wide_thumb_noop
[target_big_endian
];
21787 noop
= thumb_noop
[0][target_big_endian
];
21795 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21796 ? selected_cpu
: arm_arch_none
,
21798 [target_big_endian
];
21805 fragP
->fr_var
= noop_size
;
21807 if (bytes
& (noop_size
- 1))
21809 fix
= bytes
& (noop_size
- 1);
21811 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21813 memset (p
, 0, fix
);
21820 if (bytes
& noop_size
)
21822 /* Insert a narrow noop. */
21823 memcpy (p
, narrow_noop
, noop_size
);
21825 bytes
-= noop_size
;
21829 /* Use wide noops for the remainder */
21833 while (bytes
>= noop_size
)
21835 memcpy (p
, noop
, noop_size
);
21837 bytes
-= noop_size
;
21841 fragP
->fr_fix
+= fix
;
21844 /* Called from md_do_align. Used to create an alignment
21845 frag in a code section. */
21848 arm_frag_align_code (int n
, int max
)
21852 /* We assume that there will never be a requirement
21853 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21854 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21859 _("alignments greater than %d bytes not supported in .text sections."),
21860 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21861 as_fatal ("%s", err_msg
);
21864 p
= frag_var (rs_align_code
,
21865 MAX_MEM_FOR_RS_ALIGN_CODE
,
21867 (relax_substateT
) max
,
21874 /* Perform target specific initialisation of a frag.
21875 Note - despite the name this initialisation is not done when the frag
21876 is created, but only when its type is assigned. A frag can be created
21877 and used a long time before its type is set, so beware of assuming that
21878 this initialisation is performed first. */
21882 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21884 /* Record whether this frag is in an ARM or a THUMB area. */
21885 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21888 #else /* OBJ_ELF is defined. */
21890 arm_init_frag (fragS
* fragP
, int max_chars
)
21892 int frag_thumb_mode
;
21894 /* If the current ARM vs THUMB mode has not already
21895 been recorded into this frag then do so now. */
21896 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21897 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21899 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21901 /* Record a mapping symbol for alignment frags. We will delete this
21902 later if the alignment ends up empty. */
21903 switch (fragP
->fr_type
)
21906 case rs_align_test
:
21908 mapping_state_2 (MAP_DATA
, max_chars
);
21910 case rs_align_code
:
21911 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21918 /* When we change sections we need to issue a new mapping symbol. */
21921 arm_elf_change_section (void)
21923 /* Link an unlinked unwind index table section to the .text section. */
21924 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21925 && elf_linked_to_section (now_seg
) == NULL
)
21926 elf_linked_to_section (now_seg
) = text_section
;
21930 arm_elf_section_type (const char * str
, size_t len
)
21932 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21933 return SHT_ARM_EXIDX
;
21938 /* Code to deal with unwinding tables. */
21940 static void add_unwind_adjustsp (offsetT
);
21942 /* Generate any deferred unwind frame offset. */
21945 flush_pending_unwind (void)
21949 offset
= unwind
.pending_offset
;
21950 unwind
.pending_offset
= 0;
21952 add_unwind_adjustsp (offset
);
21955 /* Add an opcode to this list for this function. Two-byte opcodes should
21956 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21960 add_unwind_opcode (valueT op
, int length
)
21962 /* Add any deferred stack adjustment. */
21963 if (unwind
.pending_offset
)
21964 flush_pending_unwind ();
21966 unwind
.sp_restored
= 0;
21968 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21970 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21971 if (unwind
.opcodes
)
21972 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21973 unwind
.opcode_alloc
);
21975 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21980 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21982 unwind
.opcode_count
++;
21986 /* Add unwind opcodes to adjust the stack pointer. */
21989 add_unwind_adjustsp (offsetT offset
)
21993 if (offset
> 0x200)
21995 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22000 /* Long form: 0xb2, uleb128. */
22001 /* This might not fit in a word so add the individual bytes,
22002 remembering the list is built in reverse order. */
22003 o
= (valueT
) ((offset
- 0x204) >> 2);
22005 add_unwind_opcode (0, 1);
22007 /* Calculate the uleb128 encoding of the offset. */
22011 bytes
[n
] = o
& 0x7f;
22017 /* Add the insn. */
22019 add_unwind_opcode (bytes
[n
- 1], 1);
22020 add_unwind_opcode (0xb2, 1);
22022 else if (offset
> 0x100)
22024 /* Two short opcodes. */
22025 add_unwind_opcode (0x3f, 1);
22026 op
= (offset
- 0x104) >> 2;
22027 add_unwind_opcode (op
, 1);
22029 else if (offset
> 0)
22031 /* Short opcode. */
22032 op
= (offset
- 4) >> 2;
22033 add_unwind_opcode (op
, 1);
22035 else if (offset
< 0)
22038 while (offset
> 0x100)
22040 add_unwind_opcode (0x7f, 1);
22043 op
= ((offset
- 4) >> 2) | 0x40;
22044 add_unwind_opcode (op
, 1);
22048 /* Finish the list of unwind opcodes for this function. */
22050 finish_unwind_opcodes (void)
22054 if (unwind
.fp_used
)
22056 /* Adjust sp as necessary. */
22057 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22058 flush_pending_unwind ();
22060 /* After restoring sp from the frame pointer. */
22061 op
= 0x90 | unwind
.fp_reg
;
22062 add_unwind_opcode (op
, 1);
22065 flush_pending_unwind ();
22069 /* Start an exception table entry. If idx is nonzero this is an index table
22073 start_unwind_section (const segT text_seg
, int idx
)
22075 const char * text_name
;
22076 const char * prefix
;
22077 const char * prefix_once
;
22078 const char * group_name
;
22086 prefix
= ELF_STRING_ARM_unwind
;
22087 prefix_once
= ELF_STRING_ARM_unwind_once
;
22088 type
= SHT_ARM_EXIDX
;
22092 prefix
= ELF_STRING_ARM_unwind_info
;
22093 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22094 type
= SHT_PROGBITS
;
22097 text_name
= segment_name (text_seg
);
22098 if (streq (text_name
, ".text"))
22101 if (strncmp (text_name
, ".gnu.linkonce.t.",
22102 strlen (".gnu.linkonce.t.")) == 0)
22104 prefix
= prefix_once
;
22105 text_name
+= strlen (".gnu.linkonce.t.");
22108 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22114 /* Handle COMDAT group. */
22115 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22117 group_name
= elf_group_name (text_seg
);
22118 if (group_name
== NULL
)
22120 as_bad (_("Group section `%s' has no group signature"),
22121 segment_name (text_seg
));
22122 ignore_rest_of_line ();
22125 flags
|= SHF_GROUP
;
22129 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22132 /* Set the section link for index tables. */
22134 elf_linked_to_section (now_seg
) = text_seg
;
22138 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22139 personality routine data. Returns zero, or the index table value for
22140 an inline entry. */
22143 create_unwind_entry (int have_data
)
22148 /* The current word of data. */
22150 /* The number of bytes left in this word. */
22153 finish_unwind_opcodes ();
22155 /* Remember the current text section. */
22156 unwind
.saved_seg
= now_seg
;
22157 unwind
.saved_subseg
= now_subseg
;
22159 start_unwind_section (now_seg
, 0);
22161 if (unwind
.personality_routine
== NULL
)
22163 if (unwind
.personality_index
== -2)
22166 as_bad (_("handlerdata in cantunwind frame"));
22167 return 1; /* EXIDX_CANTUNWIND. */
22170 /* Use a default personality routine if none is specified. */
22171 if (unwind
.personality_index
== -1)
22173 if (unwind
.opcode_count
> 3)
22174 unwind
.personality_index
= 1;
22176 unwind
.personality_index
= 0;
22179 /* Space for the personality routine entry. */
22180 if (unwind
.personality_index
== 0)
22182 if (unwind
.opcode_count
> 3)
22183 as_bad (_("too many unwind opcodes for personality routine 0"));
22187 /* All the data is inline in the index table. */
22190 while (unwind
.opcode_count
> 0)
22192 unwind
.opcode_count
--;
22193 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22197 /* Pad with "finish" opcodes. */
22199 data
= (data
<< 8) | 0xb0;
22206 /* We get two opcodes "free" in the first word. */
22207 size
= unwind
.opcode_count
- 2;
22211 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22212 if (unwind
.personality_index
!= -1)
22214 as_bad (_("attempt to recreate an unwind entry"));
22218 /* An extra byte is required for the opcode count. */
22219 size
= unwind
.opcode_count
+ 1;
22222 size
= (size
+ 3) >> 2;
22224 as_bad (_("too many unwind opcodes"));
22226 frag_align (2, 0, 0);
22227 record_alignment (now_seg
, 2);
22228 unwind
.table_entry
= expr_build_dot ();
22230 /* Allocate the table entry. */
22231 ptr
= frag_more ((size
<< 2) + 4);
22232 /* PR 13449: Zero the table entries in case some of them are not used. */
22233 memset (ptr
, 0, (size
<< 2) + 4);
22234 where
= frag_now_fix () - ((size
<< 2) + 4);
22236 switch (unwind
.personality_index
)
22239 /* ??? Should this be a PLT generating relocation? */
22240 /* Custom personality routine. */
22241 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22242 BFD_RELOC_ARM_PREL31
);
22247 /* Set the first byte to the number of additional words. */
22248 data
= size
> 0 ? size
- 1 : 0;
22252 /* ABI defined personality routines. */
22254 /* Three opcodes bytes are packed into the first word. */
22261 /* The size and first two opcode bytes go in the first word. */
22262 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22267 /* Should never happen. */
22271 /* Pack the opcodes into words (MSB first), reversing the list at the same
22273 while (unwind
.opcode_count
> 0)
22277 md_number_to_chars (ptr
, data
, 4);
22282 unwind
.opcode_count
--;
22284 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22287 /* Finish off the last word. */
22290 /* Pad with "finish" opcodes. */
22292 data
= (data
<< 8) | 0xb0;
22294 md_number_to_chars (ptr
, data
, 4);
22299 /* Add an empty descriptor if there is no user-specified data. */
22300 ptr
= frag_more (4);
22301 md_number_to_chars (ptr
, 0, 4);
22308 /* Initialize the DWARF-2 unwind information for this procedure. */
22311 tc_arm_frame_initial_instructions (void)
22313 cfi_add_CFA_def_cfa (REG_SP
, 0);
22315 #endif /* OBJ_ELF */
22317 /* Convert REGNAME to a DWARF-2 register number. */
22320 tc_arm_regname_to_dw2regnum (char *regname
)
22322 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22326 /* PR 16694: Allow VFP registers as well. */
22327 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22331 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22340 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22344 exp
.X_op
= O_secrel
;
22345 exp
.X_add_symbol
= symbol
;
22346 exp
.X_add_number
= 0;
22347 emit_expr (&exp
, size
);
22351 /* MD interface: Symbol and relocation handling. */
22353 /* Return the address within the segment that a PC-relative fixup is
22354 relative to. For ARM, PC-relative fixups applied to instructions
22355 are generally relative to the location of the fixup plus 8 bytes.
22356 Thumb branches are offset by 4, and Thumb loads relative to PC
22357 require special handling. */
22360 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22362 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22364 /* If this is pc-relative and we are going to emit a relocation
22365 then we just want to put out any pipeline compensation that the linker
22366 will need. Otherwise we want to use the calculated base.
22367 For WinCE we skip the bias for externals as well, since this
22368 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22370 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22371 || (arm_force_relocation (fixP
)
22373 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22379 switch (fixP
->fx_r_type
)
22381 /* PC relative addressing on the Thumb is slightly odd as the
22382 bottom two bits of the PC are forced to zero for the
22383 calculation. This happens *after* application of the
22384 pipeline offset. However, Thumb adrl already adjusts for
22385 this, so we need not do it again. */
22386 case BFD_RELOC_ARM_THUMB_ADD
:
22389 case BFD_RELOC_ARM_THUMB_OFFSET
:
22390 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22391 case BFD_RELOC_ARM_T32_ADD_PC12
:
22392 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22393 return (base
+ 4) & ~3;
22395 /* Thumb branches are simply offset by +4. */
22396 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22397 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22398 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22399 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22400 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22403 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22405 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22406 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22407 && ARM_IS_FUNC (fixP
->fx_addsy
)
22408 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22409 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22412 /* BLX is like branches above, but forces the low two bits of PC to
22414 case BFD_RELOC_THUMB_PCREL_BLX
:
22416 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22417 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22418 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22419 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22420 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22421 return (base
+ 4) & ~3;
22423 /* ARM mode branches are offset by +8. However, the Windows CE
22424 loader expects the relocation not to take this into account. */
22425 case BFD_RELOC_ARM_PCREL_BLX
:
22427 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22428 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22429 && ARM_IS_FUNC (fixP
->fx_addsy
)
22430 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22431 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22434 case BFD_RELOC_ARM_PCREL_CALL
:
22436 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22437 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22438 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22439 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22440 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22443 case BFD_RELOC_ARM_PCREL_BRANCH
:
22444 case BFD_RELOC_ARM_PCREL_JUMP
:
22445 case BFD_RELOC_ARM_PLT32
:
22447 /* When handling fixups immediately, because we have already
22448 discovered the value of a symbol, or the address of the frag involved
22449 we must account for the offset by +8, as the OS loader will never see the reloc.
22450 see fixup_segment() in write.c
22451 The S_IS_EXTERNAL test handles the case of global symbols.
22452 Those need the calculated base, not just the pipe compensation the linker will need. */
22454 && fixP
->fx_addsy
!= NULL
22455 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22456 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22464 /* ARM mode loads relative to PC are also offset by +8. Unlike
22465 branches, the Windows CE loader *does* expect the relocation
22466 to take this into account. */
22467 case BFD_RELOC_ARM_OFFSET_IMM
:
22468 case BFD_RELOC_ARM_OFFSET_IMM8
:
22469 case BFD_RELOC_ARM_HWLITERAL
:
22470 case BFD_RELOC_ARM_LITERAL
:
22471 case BFD_RELOC_ARM_CP_OFF_IMM
:
22475 /* Other PC-relative relocations are un-offset. */
22481 static bfd_boolean flag_warn_syms
= TRUE
;
22484 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22486 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22487 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22488 does mean that the resulting code might be very confusing to the reader.
22489 Also this warning can be triggered if the user omits an operand before
22490 an immediate address, eg:
22494 GAS treats this as an assignment of the value of the symbol foo to a
22495 symbol LDR, and so (without this code) it will not issue any kind of
22496 warning or error message.
22498 Note - ARM instructions are case-insensitive but the strings in the hash
22499 table are all stored in lower case, so we must first ensure that name is
22501 if (flag_warn_syms
&& arm_ops_hsh
)
22503 char * nbuf
= strdup (name
);
22506 for (p
= nbuf
; *p
; p
++)
22508 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22510 static struct hash_control
* already_warned
= NULL
;
22512 if (already_warned
== NULL
)
22513 already_warned
= hash_new ();
22514 /* Only warn about the symbol once. To keep the code
22515 simple we let hash_insert do the lookup for us. */
22516 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22517 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22526 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22527 Otherwise we have no need to default values of symbols. */
22530 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22533 if (name
[0] == '_' && name
[1] == 'G'
22534 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22538 if (symbol_find (name
))
22539 as_bad (_("GOT already in the symbol table"));
22541 GOT_symbol
= symbol_new (name
, undefined_section
,
22542 (valueT
) 0, & zero_address_frag
);
22552 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22553 computed as two separate immediate values, added together. We
22554 already know that this value cannot be computed by just one ARM
22557 static unsigned int
22558 validate_immediate_twopart (unsigned int val
,
22559 unsigned int * highpart
)
22564 for (i
= 0; i
< 32; i
+= 2)
22565 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22571 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22573 else if (a
& 0xff0000)
22575 if (a
& 0xff000000)
22577 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22581 gas_assert (a
& 0xff000000);
22582 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22585 return (a
& 0xff) | (i
<< 7);
22592 validate_offset_imm (unsigned int val
, int hwse
)
22594 if ((hwse
&& val
> 255) || val
> 4095)
22599 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22600 negative immediate constant by altering the instruction. A bit of
22605 by inverting the second operand, and
22608 by negating the second operand. */
22611 negate_data_op (unsigned long * instruction
,
22612 unsigned long value
)
22615 unsigned long negated
, inverted
;
22617 negated
= encode_arm_immediate (-value
);
22618 inverted
= encode_arm_immediate (~value
);
22620 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22623 /* First negates. */
22624 case OPCODE_SUB
: /* ADD <-> SUB */
22625 new_inst
= OPCODE_ADD
;
22630 new_inst
= OPCODE_SUB
;
22634 case OPCODE_CMP
: /* CMP <-> CMN */
22635 new_inst
= OPCODE_CMN
;
22640 new_inst
= OPCODE_CMP
;
22644 /* Now Inverted ops. */
22645 case OPCODE_MOV
: /* MOV <-> MVN */
22646 new_inst
= OPCODE_MVN
;
22651 new_inst
= OPCODE_MOV
;
22655 case OPCODE_AND
: /* AND <-> BIC */
22656 new_inst
= OPCODE_BIC
;
22661 new_inst
= OPCODE_AND
;
22665 case OPCODE_ADC
: /* ADC <-> SBC */
22666 new_inst
= OPCODE_SBC
;
22671 new_inst
= OPCODE_ADC
;
22675 /* We cannot do anything. */
22680 if (value
== (unsigned) FAIL
)
22683 *instruction
&= OPCODE_MASK
;
22684 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22688 /* Like negate_data_op, but for Thumb-2. */
22690 static unsigned int
22691 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22695 unsigned int negated
, inverted
;
22697 negated
= encode_thumb32_immediate (-value
);
22698 inverted
= encode_thumb32_immediate (~value
);
22700 rd
= (*instruction
>> 8) & 0xf;
22701 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22704 /* ADD <-> SUB. Includes CMP <-> CMN. */
22705 case T2_OPCODE_SUB
:
22706 new_inst
= T2_OPCODE_ADD
;
22710 case T2_OPCODE_ADD
:
22711 new_inst
= T2_OPCODE_SUB
;
22715 /* ORR <-> ORN. Includes MOV <-> MVN. */
22716 case T2_OPCODE_ORR
:
22717 new_inst
= T2_OPCODE_ORN
;
22721 case T2_OPCODE_ORN
:
22722 new_inst
= T2_OPCODE_ORR
;
22726 /* AND <-> BIC. TST has no inverted equivalent. */
22727 case T2_OPCODE_AND
:
22728 new_inst
= T2_OPCODE_BIC
;
22735 case T2_OPCODE_BIC
:
22736 new_inst
= T2_OPCODE_AND
;
22741 case T2_OPCODE_ADC
:
22742 new_inst
= T2_OPCODE_SBC
;
22746 case T2_OPCODE_SBC
:
22747 new_inst
= T2_OPCODE_ADC
;
22751 /* We cannot do anything. */
22756 if (value
== (unsigned int)FAIL
)
22759 *instruction
&= T2_OPCODE_MASK
;
22760 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22764 /* Read a 32-bit thumb instruction from buf. */
22765 static unsigned long
22766 get_thumb32_insn (char * buf
)
22768 unsigned long insn
;
22769 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22770 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22776 /* We usually want to set the low bit on the address of thumb function
22777 symbols. In particular .word foo - . should have the low bit set.
22778 Generic code tries to fold the difference of two symbols to
22779 a constant. Prevent this and force a relocation when the first symbols
22780 is a thumb function. */
22783 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22785 if (op
== O_subtract
22786 && l
->X_op
== O_symbol
22787 && r
->X_op
== O_symbol
22788 && THUMB_IS_FUNC (l
->X_add_symbol
))
22790 l
->X_op
= O_subtract
;
22791 l
->X_op_symbol
= r
->X_add_symbol
;
22792 l
->X_add_number
-= r
->X_add_number
;
22796 /* Process as normal. */
22800 /* Encode Thumb2 unconditional branches and calls. The encoding
22801 for the 2 are identical for the immediate values. */
22804 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22806 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22809 addressT S
, I1
, I2
, lo
, hi
;
22811 S
= (value
>> 24) & 0x01;
22812 I1
= (value
>> 23) & 0x01;
22813 I2
= (value
>> 22) & 0x01;
22814 hi
= (value
>> 12) & 0x3ff;
22815 lo
= (value
>> 1) & 0x7ff;
22816 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22817 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22818 newval
|= (S
<< 10) | hi
;
22819 newval2
&= ~T2I1I2MASK
;
22820 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22821 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22822 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22826 md_apply_fix (fixS
* fixP
,
22830 offsetT value
= * valP
;
22832 unsigned int newimm
;
22833 unsigned long temp
;
22835 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22837 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22839 /* Note whether this will delete the relocation. */
22841 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22844 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22845 consistency with the behaviour on 32-bit hosts. Remember value
22847 value
&= 0xffffffff;
22848 value
^= 0x80000000;
22849 value
-= 0x80000000;
22852 fixP
->fx_addnumber
= value
;
22854 /* Same treatment for fixP->fx_offset. */
22855 fixP
->fx_offset
&= 0xffffffff;
22856 fixP
->fx_offset
^= 0x80000000;
22857 fixP
->fx_offset
-= 0x80000000;
22859 switch (fixP
->fx_r_type
)
22861 case BFD_RELOC_NONE
:
22862 /* This will need to go in the object file. */
22866 case BFD_RELOC_ARM_IMMEDIATE
:
22867 /* We claim that this fixup has been processed here,
22868 even if in fact we generate an error because we do
22869 not have a reloc for it, so tc_gen_reloc will reject it. */
22872 if (fixP
->fx_addsy
)
22874 const char *msg
= 0;
22876 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22877 msg
= _("undefined symbol %s used as an immediate value");
22878 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22879 msg
= _("symbol %s is in a different section");
22880 else if (S_IS_WEAK (fixP
->fx_addsy
))
22881 msg
= _("symbol %s is weak and may be overridden later");
22885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22886 msg
, S_GET_NAME (fixP
->fx_addsy
));
22891 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22893 /* If the offset is negative, we should use encoding A2 for ADR. */
22894 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22895 newimm
= negate_data_op (&temp
, value
);
22898 newimm
= encode_arm_immediate (value
);
22900 /* If the instruction will fail, see if we can fix things up by
22901 changing the opcode. */
22902 if (newimm
== (unsigned int) FAIL
)
22903 newimm
= negate_data_op (&temp
, value
);
22904 /* MOV accepts both ARM modified immediate (A1 encoding) and
22905 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22906 When disassembling, MOV is preferred when there is no encoding
22908 if (newimm
== (unsigned int) FAIL
22909 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22910 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22911 && !((temp
>> SBIT_SHIFT
) & 0x1)
22912 && value
>= 0 && value
<= 0xffff)
22914 /* Clear bits[23:20] to change encoding from A1 to A2. */
22915 temp
&= 0xff0fffff;
22916 /* Encoding high 4bits imm. Code below will encode the remaining
22918 temp
|= (value
& 0x0000f000) << 4;
22919 newimm
= value
& 0x00000fff;
22923 if (newimm
== (unsigned int) FAIL
)
22925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22926 _("invalid constant (%lx) after fixup"),
22927 (unsigned long) value
);
22931 newimm
|= (temp
& 0xfffff000);
22932 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22935 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22937 unsigned int highpart
= 0;
22938 unsigned int newinsn
= 0xe1a00000; /* nop. */
22940 if (fixP
->fx_addsy
)
22942 const char *msg
= 0;
22944 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22945 msg
= _("undefined symbol %s used as an immediate value");
22946 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22947 msg
= _("symbol %s is in a different section");
22948 else if (S_IS_WEAK (fixP
->fx_addsy
))
22949 msg
= _("symbol %s is weak and may be overridden later");
22953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22954 msg
, S_GET_NAME (fixP
->fx_addsy
));
22959 newimm
= encode_arm_immediate (value
);
22960 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22962 /* If the instruction will fail, see if we can fix things up by
22963 changing the opcode. */
22964 if (newimm
== (unsigned int) FAIL
22965 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22967 /* No ? OK - try using two ADD instructions to generate
22969 newimm
= validate_immediate_twopart (value
, & highpart
);
22971 /* Yes - then make sure that the second instruction is
22973 if (newimm
!= (unsigned int) FAIL
)
22975 /* Still No ? Try using a negated value. */
22976 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22977 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22978 /* Otherwise - give up. */
22981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22982 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22987 /* Replace the first operand in the 2nd instruction (which
22988 is the PC) with the destination register. We have
22989 already added in the PC in the first instruction and we
22990 do not want to do it again. */
22991 newinsn
&= ~ 0xf0000;
22992 newinsn
|= ((newinsn
& 0x0f000) << 4);
22995 newimm
|= (temp
& 0xfffff000);
22996 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22998 highpart
|= (newinsn
& 0xfffff000);
22999 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23003 case BFD_RELOC_ARM_OFFSET_IMM
:
23004 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23006 /* Fall through. */
23008 case BFD_RELOC_ARM_LITERAL
:
23014 if (validate_offset_imm (value
, 0) == FAIL
)
23016 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23018 _("invalid literal constant: pool needs to be closer"));
23020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23021 _("bad immediate value for offset (%ld)"),
23026 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23028 newval
&= 0xfffff000;
23031 newval
&= 0xff7ff000;
23032 newval
|= value
| (sign
? INDEX_UP
: 0);
23034 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23037 case BFD_RELOC_ARM_OFFSET_IMM8
:
23038 case BFD_RELOC_ARM_HWLITERAL
:
23044 if (validate_offset_imm (value
, 1) == FAIL
)
23046 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23048 _("invalid literal constant: pool needs to be closer"));
23050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23051 _("bad immediate value for 8-bit offset (%ld)"),
23056 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23058 newval
&= 0xfffff0f0;
23061 newval
&= 0xff7ff0f0;
23062 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23064 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23067 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23068 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23070 _("bad immediate value for offset (%ld)"), (long) value
);
23073 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23075 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23078 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23079 /* This is a complicated relocation used for all varieties of Thumb32
23080 load/store instruction with immediate offset:
23082 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23083 *4, optional writeback(W)
23084 (doubleword load/store)
23086 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23087 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23088 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23089 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23090 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23092 Uppercase letters indicate bits that are already encoded at
23093 this point. Lowercase letters are our problem. For the
23094 second block of instructions, the secondary opcode nybble
23095 (bits 8..11) is present, and bit 23 is zero, even if this is
23096 a PC-relative operation. */
23097 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23099 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23101 if ((newval
& 0xf0000000) == 0xe0000000)
23103 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23105 newval
|= (1 << 23);
23108 if (value
% 4 != 0)
23110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23111 _("offset not a multiple of 4"));
23117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23118 _("offset out of range"));
23123 else if ((newval
& 0x000f0000) == 0x000f0000)
23125 /* PC-relative, 12-bit offset. */
23127 newval
|= (1 << 23);
23132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23133 _("offset out of range"));
23138 else if ((newval
& 0x00000100) == 0x00000100)
23140 /* Writeback: 8-bit, +/- offset. */
23142 newval
|= (1 << 9);
23147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23148 _("offset out of range"));
23153 else if ((newval
& 0x00000f00) == 0x00000e00)
23155 /* T-instruction: positive 8-bit offset. */
23156 if (value
< 0 || value
> 0xff)
23158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23159 _("offset out of range"));
23167 /* Positive 12-bit or negative 8-bit offset. */
23171 newval
|= (1 << 23);
23181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23182 _("offset out of range"));
23189 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23190 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23193 case BFD_RELOC_ARM_SHIFT_IMM
:
23194 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23195 if (((unsigned long) value
) > 32
23197 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23200 _("shift expression is too large"));
23205 /* Shifts of zero must be done as lsl. */
23207 else if (value
== 32)
23209 newval
&= 0xfffff07f;
23210 newval
|= (value
& 0x1f) << 7;
23211 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23214 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23215 case BFD_RELOC_ARM_T32_ADD_IMM
:
23216 case BFD_RELOC_ARM_T32_IMM12
:
23217 case BFD_RELOC_ARM_T32_ADD_PC12
:
23218 /* We claim that this fixup has been processed here,
23219 even if in fact we generate an error because we do
23220 not have a reloc for it, so tc_gen_reloc will reject it. */
23224 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23227 _("undefined symbol %s used as an immediate value"),
23228 S_GET_NAME (fixP
->fx_addsy
));
23232 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23234 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23237 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23238 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23239 Thumb2 modified immediate encoding (T2). */
23240 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23241 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23243 newimm
= encode_thumb32_immediate (value
);
23244 if (newimm
== (unsigned int) FAIL
)
23245 newimm
= thumb32_negate_data_op (&newval
, value
);
23247 if (newimm
== (unsigned int) FAIL
)
23249 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23251 /* Turn add/sum into addw/subw. */
23252 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23253 newval
= (newval
& 0xfeffffff) | 0x02000000;
23254 /* No flat 12-bit imm encoding for addsw/subsw. */
23255 if ((newval
& 0x00100000) == 0)
23257 /* 12 bit immediate for addw/subw. */
23261 newval
^= 0x00a00000;
23264 newimm
= (unsigned int) FAIL
;
23271 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23272 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23273 disassembling, MOV is preferred when there is no encoding
23275 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23276 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23277 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23278 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23279 && value
>= 0 && value
<=0xffff)
23281 /* Toggle bit[25] to change encoding from T2 to T3. */
23283 /* Clear bits[19:16]. */
23284 newval
&= 0xfff0ffff;
23285 /* Encoding high 4bits imm. Code below will encode the
23286 remaining low 12bits. */
23287 newval
|= (value
& 0x0000f000) << 4;
23288 newimm
= value
& 0x00000fff;
23293 if (newimm
== (unsigned int)FAIL
)
23295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23296 _("invalid constant (%lx) after fixup"),
23297 (unsigned long) value
);
23301 newval
|= (newimm
& 0x800) << 15;
23302 newval
|= (newimm
& 0x700) << 4;
23303 newval
|= (newimm
& 0x0ff);
23305 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23306 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23309 case BFD_RELOC_ARM_SMC
:
23310 if (((unsigned long) value
) > 0xffff)
23311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23312 _("invalid smc expression"));
23313 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23314 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23315 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23318 case BFD_RELOC_ARM_HVC
:
23319 if (((unsigned long) value
) > 0xffff)
23320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23321 _("invalid hvc expression"));
23322 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23323 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23324 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23327 case BFD_RELOC_ARM_SWI
:
23328 if (fixP
->tc_fix_data
!= 0)
23330 if (((unsigned long) value
) > 0xff)
23331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23332 _("invalid swi expression"));
23333 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23335 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23339 if (((unsigned long) value
) > 0x00ffffff)
23340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23341 _("invalid swi expression"));
23342 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23344 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23348 case BFD_RELOC_ARM_MULTI
:
23349 if (((unsigned long) value
) > 0xffff)
23350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23351 _("invalid expression in load/store multiple"));
23352 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23353 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23357 case BFD_RELOC_ARM_PCREL_CALL
:
23359 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23361 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23362 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23363 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23364 /* Flip the bl to blx. This is a simple flip
23365 bit here because we generate PCREL_CALL for
23366 unconditional bls. */
23368 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23369 newval
= newval
| 0x10000000;
23370 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23376 goto arm_branch_common
;
23378 case BFD_RELOC_ARM_PCREL_JUMP
:
23379 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23381 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23382 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23383 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23385 /* This would map to a bl<cond>, b<cond>,
23386 b<always> to a Thumb function. We
23387 need to force a relocation for this particular
23389 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23392 /* Fall through. */
23394 case BFD_RELOC_ARM_PLT32
:
23396 case BFD_RELOC_ARM_PCREL_BRANCH
:
23398 goto arm_branch_common
;
23400 case BFD_RELOC_ARM_PCREL_BLX
:
23403 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23405 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23406 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23407 && ARM_IS_FUNC (fixP
->fx_addsy
))
23409 /* Flip the blx to a bl and warn. */
23410 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23411 newval
= 0xeb000000;
23412 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23413 _("blx to '%s' an ARM ISA state function changed to bl"),
23415 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23421 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23422 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23426 /* We are going to store value (shifted right by two) in the
23427 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23428 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23429 also be be clear. */
23431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23432 _("misaligned branch destination"));
23433 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23434 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23437 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23439 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23440 newval
|= (value
>> 2) & 0x00ffffff;
23441 /* Set the H bit on BLX instructions. */
23445 newval
|= 0x01000000;
23447 newval
&= ~0x01000000;
23449 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23453 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23454 /* CBZ can only branch forward. */
23456 /* Attempts to use CBZ to branch to the next instruction
23457 (which, strictly speaking, are prohibited) will be turned into
23460 FIXME: It may be better to remove the instruction completely and
23461 perform relaxation. */
23464 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23465 newval
= 0xbf00; /* NOP encoding T1 */
23466 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23473 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23475 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23476 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23477 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23482 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23483 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23486 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23488 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23489 newval
|= (value
& 0x1ff) >> 1;
23490 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23494 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23495 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23498 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23500 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23501 newval
|= (value
& 0xfff) >> 1;
23502 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23506 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23508 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23509 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23510 && ARM_IS_FUNC (fixP
->fx_addsy
)
23511 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23513 /* Force a relocation for a branch 20 bits wide. */
23516 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23518 _("conditional branch out of range"));
23520 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23523 addressT S
, J1
, J2
, lo
, hi
;
23525 S
= (value
& 0x00100000) >> 20;
23526 J2
= (value
& 0x00080000) >> 19;
23527 J1
= (value
& 0x00040000) >> 18;
23528 hi
= (value
& 0x0003f000) >> 12;
23529 lo
= (value
& 0x00000ffe) >> 1;
23531 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23532 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23533 newval
|= (S
<< 10) | hi
;
23534 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23535 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23536 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23540 case BFD_RELOC_THUMB_PCREL_BLX
:
23541 /* If there is a blx from a thumb state function to
23542 another thumb function flip this to a bl and warn
23546 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23547 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23548 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23550 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23551 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23552 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23554 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23555 newval
= newval
| 0x1000;
23556 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23557 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23562 goto thumb_bl_common
;
23564 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23565 /* A bl from Thumb state ISA to an internal ARM state function
23566 is converted to a blx. */
23568 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23569 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23570 && ARM_IS_FUNC (fixP
->fx_addsy
)
23571 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23573 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23574 newval
= newval
& ~0x1000;
23575 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23576 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23582 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23583 /* For a BLX instruction, make sure that the relocation is rounded up
23584 to a word boundary. This follows the semantics of the instruction
23585 which specifies that bit 1 of the target address will come from bit
23586 1 of the base address. */
23587 value
= (value
+ 3) & ~ 3;
23590 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23591 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23592 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23595 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23597 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23599 else if ((value
& ~0x1ffffff)
23600 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23602 _("Thumb2 branch out of range"));
23605 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23606 encode_thumb2_b_bl_offset (buf
, value
);
23610 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23611 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23614 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23615 encode_thumb2_b_bl_offset (buf
, value
);
23620 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23625 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23626 md_number_to_chars (buf
, value
, 2);
23630 case BFD_RELOC_ARM_TLS_CALL
:
23631 case BFD_RELOC_ARM_THM_TLS_CALL
:
23632 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23633 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23634 case BFD_RELOC_ARM_TLS_GOTDESC
:
23635 case BFD_RELOC_ARM_TLS_GD32
:
23636 case BFD_RELOC_ARM_TLS_LE32
:
23637 case BFD_RELOC_ARM_TLS_IE32
:
23638 case BFD_RELOC_ARM_TLS_LDM32
:
23639 case BFD_RELOC_ARM_TLS_LDO32
:
23640 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23643 case BFD_RELOC_ARM_GOT32
:
23644 case BFD_RELOC_ARM_GOTOFF
:
23647 case BFD_RELOC_ARM_GOT_PREL
:
23648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23649 md_number_to_chars (buf
, value
, 4);
23652 case BFD_RELOC_ARM_TARGET2
:
23653 /* TARGET2 is not partial-inplace, so we need to write the
23654 addend here for REL targets, because it won't be written out
23655 during reloc processing later. */
23656 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23657 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23661 case BFD_RELOC_RVA
:
23663 case BFD_RELOC_ARM_TARGET1
:
23664 case BFD_RELOC_ARM_ROSEGREL32
:
23665 case BFD_RELOC_ARM_SBREL32
:
23666 case BFD_RELOC_32_PCREL
:
23668 case BFD_RELOC_32_SECREL
:
23670 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23672 /* For WinCE we only do this for pcrel fixups. */
23673 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23675 md_number_to_chars (buf
, value
, 4);
23679 case BFD_RELOC_ARM_PREL31
:
23680 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23682 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23683 if ((value
^ (value
>> 1)) & 0x40000000)
23685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23686 _("rel31 relocation overflow"));
23688 newval
|= value
& 0x7fffffff;
23689 md_number_to_chars (buf
, newval
, 4);
23694 case BFD_RELOC_ARM_CP_OFF_IMM
:
23695 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23696 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23697 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23699 newval
= get_thumb32_insn (buf
);
23700 if ((newval
& 0x0f200f00) == 0x0d000900)
23702 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23703 has permitted values that are multiples of 2, in the range 0
23705 if (value
< -510 || value
> 510 || (value
& 1))
23706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23707 _("co-processor offset out of range"));
23709 else if (value
< -1023 || value
> 1023 || (value
& 3))
23710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23711 _("co-processor offset out of range"));
23716 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23717 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23718 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23720 newval
= get_thumb32_insn (buf
);
23722 newval
&= 0xffffff00;
23725 newval
&= 0xff7fff00;
23726 if ((newval
& 0x0f200f00) == 0x0d000900)
23728 /* This is a fp16 vstr/vldr.
23730 It requires the immediate offset in the instruction is shifted
23731 left by 1 to be a half-word offset.
23733 Here, left shift by 1 first, and later right shift by 2
23734 should get the right offset. */
23737 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23739 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23740 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23741 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23743 put_thumb32_insn (buf
, newval
);
23746 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23747 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23748 if (value
< -255 || value
> 255)
23749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23750 _("co-processor offset out of range"));
23752 goto cp_off_common
;
23754 case BFD_RELOC_ARM_THUMB_OFFSET
:
23755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23756 /* Exactly what ranges, and where the offset is inserted depends
23757 on the type of instruction, we can establish this from the
23759 switch (newval
>> 12)
23761 case 4: /* PC load. */
23762 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23763 forced to zero for these loads; md_pcrel_from has already
23764 compensated for this. */
23766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23767 _("invalid offset, target not word aligned (0x%08lX)"),
23768 (((unsigned long) fixP
->fx_frag
->fr_address
23769 + (unsigned long) fixP
->fx_where
) & ~3)
23770 + (unsigned long) value
);
23772 if (value
& ~0x3fc)
23773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23774 _("invalid offset, value too big (0x%08lX)"),
23777 newval
|= value
>> 2;
23780 case 9: /* SP load/store. */
23781 if (value
& ~0x3fc)
23782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23783 _("invalid offset, value too big (0x%08lX)"),
23785 newval
|= value
>> 2;
23788 case 6: /* Word load/store. */
23790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23791 _("invalid offset, value too big (0x%08lX)"),
23793 newval
|= value
<< 4; /* 6 - 2. */
23796 case 7: /* Byte load/store. */
23798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23799 _("invalid offset, value too big (0x%08lX)"),
23801 newval
|= value
<< 6;
23804 case 8: /* Halfword load/store. */
23806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23807 _("invalid offset, value too big (0x%08lX)"),
23809 newval
|= value
<< 5; /* 6 - 1. */
23813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23814 "Unable to process relocation for thumb opcode: %lx",
23815 (unsigned long) newval
);
23818 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23821 case BFD_RELOC_ARM_THUMB_ADD
:
23822 /* This is a complicated relocation, since we use it for all of
23823 the following immediate relocations:
23827 9bit ADD/SUB SP word-aligned
23828 10bit ADD PC/SP word-aligned
23830 The type of instruction being processed is encoded in the
23837 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23839 int rd
= (newval
>> 4) & 0xf;
23840 int rs
= newval
& 0xf;
23841 int subtract
= !!(newval
& 0x8000);
23843 /* Check for HI regs, only very restricted cases allowed:
23844 Adjusting SP, and using PC or SP to get an address. */
23845 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23846 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23848 _("invalid Hi register with immediate"));
23850 /* If value is negative, choose the opposite instruction. */
23854 subtract
= !subtract
;
23856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23857 _("immediate value out of range"));
23862 if (value
& ~0x1fc)
23863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23864 _("invalid immediate for stack address calculation"));
23865 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23866 newval
|= value
>> 2;
23868 else if (rs
== REG_PC
|| rs
== REG_SP
)
23870 /* PR gas/18541. If the addition is for a defined symbol
23871 within range of an ADR instruction then accept it. */
23874 && fixP
->fx_addsy
!= NULL
)
23878 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23879 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23880 || S_IS_WEAK (fixP
->fx_addsy
))
23882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23883 _("address calculation needs a strongly defined nearby symbol"));
23887 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23889 /* Round up to the next 4-byte boundary. */
23894 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23899 _("symbol too far away"));
23909 if (subtract
|| value
& ~0x3fc)
23910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23911 _("invalid immediate for address calculation (value = 0x%08lX)"),
23912 (unsigned long) (subtract
? - value
: value
));
23913 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23915 newval
|= value
>> 2;
23920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23921 _("immediate value out of range"));
23922 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23923 newval
|= (rd
<< 8) | value
;
23928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23929 _("immediate value out of range"));
23930 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23931 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23934 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23937 case BFD_RELOC_ARM_THUMB_IMM
:
23938 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23939 if (value
< 0 || value
> 255)
23940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23941 _("invalid immediate: %ld is out of range"),
23944 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23947 case BFD_RELOC_ARM_THUMB_SHIFT
:
23948 /* 5bit shift value (0..32). LSL cannot take 32. */
23949 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23950 temp
= newval
& 0xf800;
23951 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23953 _("invalid shift value: %ld"), (long) value
);
23954 /* Shifts of zero must be encoded as LSL. */
23956 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23957 /* Shifts of 32 are encoded as zero. */
23958 else if (value
== 32)
23960 newval
|= value
<< 6;
23961 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23964 case BFD_RELOC_VTABLE_INHERIT
:
23965 case BFD_RELOC_VTABLE_ENTRY
:
23969 case BFD_RELOC_ARM_MOVW
:
23970 case BFD_RELOC_ARM_MOVT
:
23971 case BFD_RELOC_ARM_THUMB_MOVW
:
23972 case BFD_RELOC_ARM_THUMB_MOVT
:
23973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23975 /* REL format relocations are limited to a 16-bit addend. */
23976 if (!fixP
->fx_done
)
23978 if (value
< -0x8000 || value
> 0x7fff)
23979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23980 _("offset out of range"));
23982 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23983 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23988 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23989 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23991 newval
= get_thumb32_insn (buf
);
23992 newval
&= 0xfbf08f00;
23993 newval
|= (value
& 0xf000) << 4;
23994 newval
|= (value
& 0x0800) << 15;
23995 newval
|= (value
& 0x0700) << 4;
23996 newval
|= (value
& 0x00ff);
23997 put_thumb32_insn (buf
, newval
);
24001 newval
= md_chars_to_number (buf
, 4);
24002 newval
&= 0xfff0f000;
24003 newval
|= value
& 0x0fff;
24004 newval
|= (value
& 0xf000) << 4;
24005 md_number_to_chars (buf
, newval
, 4);
24010 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24011 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24012 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24013 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24014 gas_assert (!fixP
->fx_done
);
24017 bfd_boolean is_mov
;
24018 bfd_vma encoded_addend
= value
;
24020 /* Check that addend can be encoded in instruction. */
24021 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24023 _("the offset 0x%08lX is not representable"),
24024 (unsigned long) encoded_addend
);
24026 /* Extract the instruction. */
24027 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24028 is_mov
= (insn
& 0xf800) == 0x2000;
24033 if (!seg
->use_rela_p
)
24034 insn
|= encoded_addend
;
24040 /* Extract the instruction. */
24041 /* Encoding is the following
24046 /* The following conditions must be true :
24051 rd
= (insn
>> 4) & 0xf;
24053 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24055 _("Unable to process relocation for thumb opcode: %lx"),
24056 (unsigned long) insn
);
24058 /* Encode as ADD immediate8 thumb 1 code. */
24059 insn
= 0x3000 | (rd
<< 8);
24061 /* Place the encoded addend into the first 8 bits of the
24063 if (!seg
->use_rela_p
)
24064 insn
|= encoded_addend
;
24067 /* Update the instruction. */
24068 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24072 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24073 case BFD_RELOC_ARM_ALU_PC_G0
:
24074 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24075 case BFD_RELOC_ARM_ALU_PC_G1
:
24076 case BFD_RELOC_ARM_ALU_PC_G2
:
24077 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24078 case BFD_RELOC_ARM_ALU_SB_G0
:
24079 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24080 case BFD_RELOC_ARM_ALU_SB_G1
:
24081 case BFD_RELOC_ARM_ALU_SB_G2
:
24082 gas_assert (!fixP
->fx_done
);
24083 if (!seg
->use_rela_p
)
24086 bfd_vma encoded_addend
;
24087 bfd_vma addend_abs
= abs (value
);
24089 /* Check that the absolute value of the addend can be
24090 expressed as an 8-bit constant plus a rotation. */
24091 encoded_addend
= encode_arm_immediate (addend_abs
);
24092 if (encoded_addend
== (unsigned int) FAIL
)
24093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24094 _("the offset 0x%08lX is not representable"),
24095 (unsigned long) addend_abs
);
24097 /* Extract the instruction. */
24098 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24100 /* If the addend is positive, use an ADD instruction.
24101 Otherwise use a SUB. Take care not to destroy the S bit. */
24102 insn
&= 0xff1fffff;
24108 /* Place the encoded addend into the first 12 bits of the
24110 insn
&= 0xfffff000;
24111 insn
|= encoded_addend
;
24113 /* Update the instruction. */
24114 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24118 case BFD_RELOC_ARM_LDR_PC_G0
:
24119 case BFD_RELOC_ARM_LDR_PC_G1
:
24120 case BFD_RELOC_ARM_LDR_PC_G2
:
24121 case BFD_RELOC_ARM_LDR_SB_G0
:
24122 case BFD_RELOC_ARM_LDR_SB_G1
:
24123 case BFD_RELOC_ARM_LDR_SB_G2
:
24124 gas_assert (!fixP
->fx_done
);
24125 if (!seg
->use_rela_p
)
24128 bfd_vma addend_abs
= abs (value
);
24130 /* Check that the absolute value of the addend can be
24131 encoded in 12 bits. */
24132 if (addend_abs
>= 0x1000)
24133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24134 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24135 (unsigned long) addend_abs
);
24137 /* Extract the instruction. */
24138 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24140 /* If the addend is negative, clear bit 23 of the instruction.
24141 Otherwise set it. */
24143 insn
&= ~(1 << 23);
24147 /* Place the absolute value of the addend into the first 12 bits
24148 of the instruction. */
24149 insn
&= 0xfffff000;
24150 insn
|= addend_abs
;
24152 /* Update the instruction. */
24153 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24157 case BFD_RELOC_ARM_LDRS_PC_G0
:
24158 case BFD_RELOC_ARM_LDRS_PC_G1
:
24159 case BFD_RELOC_ARM_LDRS_PC_G2
:
24160 case BFD_RELOC_ARM_LDRS_SB_G0
:
24161 case BFD_RELOC_ARM_LDRS_SB_G1
:
24162 case BFD_RELOC_ARM_LDRS_SB_G2
:
24163 gas_assert (!fixP
->fx_done
);
24164 if (!seg
->use_rela_p
)
24167 bfd_vma addend_abs
= abs (value
);
24169 /* Check that the absolute value of the addend can be
24170 encoded in 8 bits. */
24171 if (addend_abs
>= 0x100)
24172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24173 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24174 (unsigned long) addend_abs
);
24176 /* Extract the instruction. */
24177 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24179 /* If the addend is negative, clear bit 23 of the instruction.
24180 Otherwise set it. */
24182 insn
&= ~(1 << 23);
24186 /* Place the first four bits of the absolute value of the addend
24187 into the first 4 bits of the instruction, and the remaining
24188 four into bits 8 .. 11. */
24189 insn
&= 0xfffff0f0;
24190 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24192 /* Update the instruction. */
24193 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24197 case BFD_RELOC_ARM_LDC_PC_G0
:
24198 case BFD_RELOC_ARM_LDC_PC_G1
:
24199 case BFD_RELOC_ARM_LDC_PC_G2
:
24200 case BFD_RELOC_ARM_LDC_SB_G0
:
24201 case BFD_RELOC_ARM_LDC_SB_G1
:
24202 case BFD_RELOC_ARM_LDC_SB_G2
:
24203 gas_assert (!fixP
->fx_done
);
24204 if (!seg
->use_rela_p
)
24207 bfd_vma addend_abs
= abs (value
);
24209 /* Check that the absolute value of the addend is a multiple of
24210 four and, when divided by four, fits in 8 bits. */
24211 if (addend_abs
& 0x3)
24212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24213 _("bad offset 0x%08lX (must be word-aligned)"),
24214 (unsigned long) addend_abs
);
24216 if ((addend_abs
>> 2) > 0xff)
24217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24218 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24219 (unsigned long) addend_abs
);
24221 /* Extract the instruction. */
24222 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24224 /* If the addend is negative, clear bit 23 of the instruction.
24225 Otherwise set it. */
24227 insn
&= ~(1 << 23);
24231 /* Place the addend (divided by four) into the first eight
24232 bits of the instruction. */
24233 insn
&= 0xfffffff0;
24234 insn
|= addend_abs
>> 2;
24236 /* Update the instruction. */
24237 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24241 case BFD_RELOC_ARM_V4BX
:
24242 /* This will need to go in the object file. */
24246 case BFD_RELOC_UNUSED
:
24248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24249 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24253 /* Translate internal representation of relocation info to BFD target
24257 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24260 bfd_reloc_code_real_type code
;
24262 reloc
= XNEW (arelent
);
24264 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24265 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24266 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24268 if (fixp
->fx_pcrel
)
24270 if (section
->use_rela_p
)
24271 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24273 fixp
->fx_offset
= reloc
->address
;
24275 reloc
->addend
= fixp
->fx_offset
;
24277 switch (fixp
->fx_r_type
)
24280 if (fixp
->fx_pcrel
)
24282 code
= BFD_RELOC_8_PCREL
;
24285 /* Fall through. */
24288 if (fixp
->fx_pcrel
)
24290 code
= BFD_RELOC_16_PCREL
;
24293 /* Fall through. */
24296 if (fixp
->fx_pcrel
)
24298 code
= BFD_RELOC_32_PCREL
;
24301 /* Fall through. */
24303 case BFD_RELOC_ARM_MOVW
:
24304 if (fixp
->fx_pcrel
)
24306 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24309 /* Fall through. */
24311 case BFD_RELOC_ARM_MOVT
:
24312 if (fixp
->fx_pcrel
)
24314 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24317 /* Fall through. */
24319 case BFD_RELOC_ARM_THUMB_MOVW
:
24320 if (fixp
->fx_pcrel
)
24322 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24325 /* Fall through. */
24327 case BFD_RELOC_ARM_THUMB_MOVT
:
24328 if (fixp
->fx_pcrel
)
24330 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24333 /* Fall through. */
24335 case BFD_RELOC_NONE
:
24336 case BFD_RELOC_ARM_PCREL_BRANCH
:
24337 case BFD_RELOC_ARM_PCREL_BLX
:
24338 case BFD_RELOC_RVA
:
24339 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24340 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24341 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24342 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24343 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24344 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24345 case BFD_RELOC_VTABLE_ENTRY
:
24346 case BFD_RELOC_VTABLE_INHERIT
:
24348 case BFD_RELOC_32_SECREL
:
24350 code
= fixp
->fx_r_type
;
24353 case BFD_RELOC_THUMB_PCREL_BLX
:
24355 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24356 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24359 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24362 case BFD_RELOC_ARM_LITERAL
:
24363 case BFD_RELOC_ARM_HWLITERAL
:
24364 /* If this is called then the a literal has
24365 been referenced across a section boundary. */
24366 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24367 _("literal referenced across section boundary"));
24371 case BFD_RELOC_ARM_TLS_CALL
:
24372 case BFD_RELOC_ARM_THM_TLS_CALL
:
24373 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24374 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24375 case BFD_RELOC_ARM_GOT32
:
24376 case BFD_RELOC_ARM_GOTOFF
:
24377 case BFD_RELOC_ARM_GOT_PREL
:
24378 case BFD_RELOC_ARM_PLT32
:
24379 case BFD_RELOC_ARM_TARGET1
:
24380 case BFD_RELOC_ARM_ROSEGREL32
:
24381 case BFD_RELOC_ARM_SBREL32
:
24382 case BFD_RELOC_ARM_PREL31
:
24383 case BFD_RELOC_ARM_TARGET2
:
24384 case BFD_RELOC_ARM_TLS_LDO32
:
24385 case BFD_RELOC_ARM_PCREL_CALL
:
24386 case BFD_RELOC_ARM_PCREL_JUMP
:
24387 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24388 case BFD_RELOC_ARM_ALU_PC_G0
:
24389 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24390 case BFD_RELOC_ARM_ALU_PC_G1
:
24391 case BFD_RELOC_ARM_ALU_PC_G2
:
24392 case BFD_RELOC_ARM_LDR_PC_G0
:
24393 case BFD_RELOC_ARM_LDR_PC_G1
:
24394 case BFD_RELOC_ARM_LDR_PC_G2
:
24395 case BFD_RELOC_ARM_LDRS_PC_G0
:
24396 case BFD_RELOC_ARM_LDRS_PC_G1
:
24397 case BFD_RELOC_ARM_LDRS_PC_G2
:
24398 case BFD_RELOC_ARM_LDC_PC_G0
:
24399 case BFD_RELOC_ARM_LDC_PC_G1
:
24400 case BFD_RELOC_ARM_LDC_PC_G2
:
24401 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24402 case BFD_RELOC_ARM_ALU_SB_G0
:
24403 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24404 case BFD_RELOC_ARM_ALU_SB_G1
:
24405 case BFD_RELOC_ARM_ALU_SB_G2
:
24406 case BFD_RELOC_ARM_LDR_SB_G0
:
24407 case BFD_RELOC_ARM_LDR_SB_G1
:
24408 case BFD_RELOC_ARM_LDR_SB_G2
:
24409 case BFD_RELOC_ARM_LDRS_SB_G0
:
24410 case BFD_RELOC_ARM_LDRS_SB_G1
:
24411 case BFD_RELOC_ARM_LDRS_SB_G2
:
24412 case BFD_RELOC_ARM_LDC_SB_G0
:
24413 case BFD_RELOC_ARM_LDC_SB_G1
:
24414 case BFD_RELOC_ARM_LDC_SB_G2
:
24415 case BFD_RELOC_ARM_V4BX
:
24416 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24417 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24418 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24419 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24420 code
= fixp
->fx_r_type
;
24423 case BFD_RELOC_ARM_TLS_GOTDESC
:
24424 case BFD_RELOC_ARM_TLS_GD32
:
24425 case BFD_RELOC_ARM_TLS_LE32
:
24426 case BFD_RELOC_ARM_TLS_IE32
:
24427 case BFD_RELOC_ARM_TLS_LDM32
:
24428 /* BFD will include the symbol's address in the addend.
24429 But we don't want that, so subtract it out again here. */
24430 if (!S_IS_COMMON (fixp
->fx_addsy
))
24431 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24432 code
= fixp
->fx_r_type
;
24436 case BFD_RELOC_ARM_IMMEDIATE
:
24437 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24438 _("internal relocation (type: IMMEDIATE) not fixed up"));
24441 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24442 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24443 _("ADRL used for a symbol not defined in the same file"));
24446 case BFD_RELOC_ARM_OFFSET_IMM
:
24447 if (section
->use_rela_p
)
24449 code
= fixp
->fx_r_type
;
24453 if (fixp
->fx_addsy
!= NULL
24454 && !S_IS_DEFINED (fixp
->fx_addsy
)
24455 && S_IS_LOCAL (fixp
->fx_addsy
))
24457 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24458 _("undefined local label `%s'"),
24459 S_GET_NAME (fixp
->fx_addsy
));
24463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24464 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24471 switch (fixp
->fx_r_type
)
24473 case BFD_RELOC_NONE
: type
= "NONE"; break;
24474 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24475 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24476 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24477 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24478 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24479 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24480 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24481 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24482 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24483 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24484 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24485 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24486 default: type
= _("<unknown>"); break;
24488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24489 _("cannot represent %s relocation in this object file format"),
24496 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24498 && fixp
->fx_addsy
== GOT_symbol
)
24500 code
= BFD_RELOC_ARM_GOTPC
;
24501 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24505 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24507 if (reloc
->howto
== NULL
)
24509 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24510 _("cannot represent %s relocation in this object file format"),
24511 bfd_get_reloc_code_name (code
));
24515 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24516 vtable entry to be used in the relocation's section offset. */
24517 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24518 reloc
->address
= fixp
->fx_offset
;
24523 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24526 cons_fix_new_arm (fragS
* frag
,
24530 bfd_reloc_code_real_type reloc
)
24535 FIXME: @@ Should look at CPU word size. */
24539 reloc
= BFD_RELOC_8
;
24542 reloc
= BFD_RELOC_16
;
24546 reloc
= BFD_RELOC_32
;
24549 reloc
= BFD_RELOC_64
;
24554 if (exp
->X_op
== O_secrel
)
24556 exp
->X_op
= O_symbol
;
24557 reloc
= BFD_RELOC_32_SECREL
;
24561 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24564 #if defined (OBJ_COFF)
24566 arm_validate_fix (fixS
* fixP
)
24568 /* If the destination of the branch is a defined symbol which does not have
24569 the THUMB_FUNC attribute, then we must be calling a function which has
24570 the (interfacearm) attribute. We look for the Thumb entry point to that
24571 function and change the branch to refer to that function instead. */
24572 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24573 && fixP
->fx_addsy
!= NULL
24574 && S_IS_DEFINED (fixP
->fx_addsy
)
24575 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24577 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24584 arm_force_relocation (struct fix
* fixp
)
24586 #if defined (OBJ_COFF) && defined (TE_PE)
24587 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24591 /* In case we have a call or a branch to a function in ARM ISA mode from
24592 a thumb function or vice-versa force the relocation. These relocations
24593 are cleared off for some cores that might have blx and simple transformations
24597 switch (fixp
->fx_r_type
)
24599 case BFD_RELOC_ARM_PCREL_JUMP
:
24600 case BFD_RELOC_ARM_PCREL_CALL
:
24601 case BFD_RELOC_THUMB_PCREL_BLX
:
24602 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24606 case BFD_RELOC_ARM_PCREL_BLX
:
24607 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24608 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24609 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24610 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24619 /* Resolve these relocations even if the symbol is extern or weak.
24620 Technically this is probably wrong due to symbol preemption.
24621 In practice these relocations do not have enough range to be useful
24622 at dynamic link time, and some code (e.g. in the Linux kernel)
24623 expects these references to be resolved. */
24624 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24625 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24626 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24627 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24628 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24629 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24630 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24631 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24632 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24633 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24634 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24635 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24636 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24637 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24640 /* Always leave these relocations for the linker. */
24641 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24642 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24643 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24646 /* Always generate relocations against function symbols. */
24647 if (fixp
->fx_r_type
== BFD_RELOC_32
24649 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24652 return generic_force_reloc (fixp
);
24655 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24656 /* Relocations against function names must be left unadjusted,
24657 so that the linker can use this information to generate interworking
24658 stubs. The MIPS version of this function
24659 also prevents relocations that are mips-16 specific, but I do not
24660 know why it does this.
24663 There is one other problem that ought to be addressed here, but
24664 which currently is not: Taking the address of a label (rather
24665 than a function) and then later jumping to that address. Such
24666 addresses also ought to have their bottom bit set (assuming that
24667 they reside in Thumb code), but at the moment they will not. */
24670 arm_fix_adjustable (fixS
* fixP
)
24672 if (fixP
->fx_addsy
== NULL
)
24675 /* Preserve relocations against symbols with function type. */
24676 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24679 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24680 && fixP
->fx_subsy
== NULL
)
24683 /* We need the symbol name for the VTABLE entries. */
24684 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24685 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24688 /* Don't allow symbols to be discarded on GOT related relocs. */
24689 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24690 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24691 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24692 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24693 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24694 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24695 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24696 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24697 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24698 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24699 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24700 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24701 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24702 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24705 /* Similarly for group relocations. */
24706 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24707 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24708 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24711 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24712 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24713 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24714 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24715 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24716 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24717 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24718 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24719 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24722 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24723 offsets, so keep these symbols. */
24724 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24725 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24730 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24734 elf32_arm_target_format (void)
24737 return (target_big_endian
24738 ? "elf32-bigarm-symbian"
24739 : "elf32-littlearm-symbian");
24740 #elif defined (TE_VXWORKS)
24741 return (target_big_endian
24742 ? "elf32-bigarm-vxworks"
24743 : "elf32-littlearm-vxworks");
24744 #elif defined (TE_NACL)
24745 return (target_big_endian
24746 ? "elf32-bigarm-nacl"
24747 : "elf32-littlearm-nacl");
24749 if (target_big_endian
)
24750 return "elf32-bigarm";
24752 return "elf32-littlearm";
24757 armelf_frob_symbol (symbolS
* symp
,
24760 elf_frob_symbol (symp
, puntp
);
24764 /* MD interface: Finalization. */
24769 literal_pool
* pool
;
24771 /* Ensure that all the IT blocks are properly closed. */
24772 check_it_blocks_finished ();
24774 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24776 /* Put it at the end of the relevant section. */
24777 subseg_set (pool
->section
, pool
->sub_section
);
24779 arm_elf_change_section ();
24786 /* Remove any excess mapping symbols generated for alignment frags in
24787 SEC. We may have created a mapping symbol before a zero byte
24788 alignment; remove it if there's a mapping symbol after the
24791 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24792 void *dummy ATTRIBUTE_UNUSED
)
24794 segment_info_type
*seginfo
= seg_info (sec
);
24797 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24800 for (fragp
= seginfo
->frchainP
->frch_root
;
24802 fragp
= fragp
->fr_next
)
24804 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24805 fragS
*next
= fragp
->fr_next
;
24807 /* Variable-sized frags have been converted to fixed size by
24808 this point. But if this was variable-sized to start with,
24809 there will be a fixed-size frag after it. So don't handle
24811 if (sym
== NULL
|| next
== NULL
)
24814 if (S_GET_VALUE (sym
) < next
->fr_address
)
24815 /* Not at the end of this frag. */
24817 know (S_GET_VALUE (sym
) == next
->fr_address
);
24821 if (next
->tc_frag_data
.first_map
!= NULL
)
24823 /* Next frag starts with a mapping symbol. Discard this
24825 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24829 if (next
->fr_next
== NULL
)
24831 /* This mapping symbol is at the end of the section. Discard
24833 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24834 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24838 /* As long as we have empty frags without any mapping symbols,
24840 /* If the next frag is non-empty and does not start with a
24841 mapping symbol, then this mapping symbol is required. */
24842 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24845 next
= next
->fr_next
;
24847 while (next
!= NULL
);
24852 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24856 arm_adjust_symtab (void)
24861 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24863 if (ARM_IS_THUMB (sym
))
24865 if (THUMB_IS_FUNC (sym
))
24867 /* Mark the symbol as a Thumb function. */
24868 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24869 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24870 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24872 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24873 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24875 as_bad (_("%s: unexpected function type: %d"),
24876 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24878 else switch (S_GET_STORAGE_CLASS (sym
))
24881 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24884 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24887 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24895 if (ARM_IS_INTERWORK (sym
))
24896 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24903 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24905 if (ARM_IS_THUMB (sym
))
24907 elf_symbol_type
* elf_sym
;
24909 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24910 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24912 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24913 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24915 /* If it's a .thumb_func, declare it as so,
24916 otherwise tag label as .code 16. */
24917 if (THUMB_IS_FUNC (sym
))
24918 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24919 ST_BRANCH_TO_THUMB
);
24920 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24921 elf_sym
->internal_elf_sym
.st_info
=
24922 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24927 /* Remove any overlapping mapping symbols generated by alignment frags. */
24928 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24929 /* Now do generic ELF adjustments. */
24930 elf_adjust_symtab ();
24934 /* MD interface: Initialization. */
24937 set_constant_flonums (void)
24941 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24942 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24946 /* Auto-select Thumb mode if it's the only available instruction set for the
24947 given architecture. */
24950 autoselect_thumb_from_cpu_variant (void)
24952 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24953 opcode_select (16);
24962 if ( (arm_ops_hsh
= hash_new ()) == NULL
24963 || (arm_cond_hsh
= hash_new ()) == NULL
24964 || (arm_shift_hsh
= hash_new ()) == NULL
24965 || (arm_psr_hsh
= hash_new ()) == NULL
24966 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24967 || (arm_reg_hsh
= hash_new ()) == NULL
24968 || (arm_reloc_hsh
= hash_new ()) == NULL
24969 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24970 as_fatal (_("virtual memory exhausted"));
24972 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24973 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24974 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24975 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24976 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24977 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24978 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24979 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24980 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24981 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24982 (void *) (v7m_psrs
+ i
));
24983 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24984 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24986 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24988 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24989 (void *) (barrier_opt_names
+ i
));
24991 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24993 struct reloc_entry
* entry
= reloc_names
+ i
;
24995 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24996 /* This makes encode_branch() use the EABI versions of this relocation. */
24997 entry
->reloc
= BFD_RELOC_UNUSED
;
24999 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25003 set_constant_flonums ();
25005 /* Set the cpu variant based on the command-line options. We prefer
25006 -mcpu= over -march= if both are set (as for GCC); and we prefer
25007 -mfpu= over any other way of setting the floating point unit.
25008 Use of legacy options with new options are faulted. */
25011 if (mcpu_cpu_opt
|| march_cpu_opt
)
25012 as_bad (_("use of old and new-style options to set CPU type"));
25014 mcpu_cpu_opt
= legacy_cpu
;
25016 else if (!mcpu_cpu_opt
)
25017 mcpu_cpu_opt
= march_cpu_opt
;
25022 as_bad (_("use of old and new-style options to set FPU type"));
25024 mfpu_opt
= legacy_fpu
;
25026 else if (!mfpu_opt
)
25028 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25029 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25030 /* Some environments specify a default FPU. If they don't, infer it
25031 from the processor. */
25033 mfpu_opt
= mcpu_fpu_opt
;
25035 mfpu_opt
= march_fpu_opt
;
25037 mfpu_opt
= &fpu_default
;
25043 if (mcpu_cpu_opt
!= NULL
)
25044 mfpu_opt
= &fpu_default
;
25045 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25046 mfpu_opt
= &fpu_arch_vfp_v2
;
25048 mfpu_opt
= &fpu_arch_fpa
;
25054 mcpu_cpu_opt
= &cpu_default
;
25055 selected_cpu
= cpu_default
;
25058 selected_cpu
= *mcpu_cpu_opt
;
25061 selected_cpu
= *mcpu_cpu_opt
;
25063 mcpu_cpu_opt
= &arm_arch_any
;
25066 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25068 autoselect_thumb_from_cpu_variant ();
25070 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25072 #if defined OBJ_COFF || defined OBJ_ELF
25074 unsigned int flags
= 0;
25076 #if defined OBJ_ELF
25077 flags
= meabi_flags
;
25079 switch (meabi_flags
)
25081 case EF_ARM_EABI_UNKNOWN
:
25083 /* Set the flags in the private structure. */
25084 if (uses_apcs_26
) flags
|= F_APCS26
;
25085 if (support_interwork
) flags
|= F_INTERWORK
;
25086 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25087 if (pic_code
) flags
|= F_PIC
;
25088 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25089 flags
|= F_SOFT_FLOAT
;
25091 switch (mfloat_abi_opt
)
25093 case ARM_FLOAT_ABI_SOFT
:
25094 case ARM_FLOAT_ABI_SOFTFP
:
25095 flags
|= F_SOFT_FLOAT
;
25098 case ARM_FLOAT_ABI_HARD
:
25099 if (flags
& F_SOFT_FLOAT
)
25100 as_bad (_("hard-float conflicts with specified fpu"));
25104 /* Using pure-endian doubles (even if soft-float). */
25105 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25106 flags
|= F_VFP_FLOAT
;
25108 #if defined OBJ_ELF
25109 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25110 flags
|= EF_ARM_MAVERICK_FLOAT
;
25113 case EF_ARM_EABI_VER4
:
25114 case EF_ARM_EABI_VER5
:
25115 /* No additional flags to set. */
25122 bfd_set_private_flags (stdoutput
, flags
);
25124 /* We have run out flags in the COFF header to encode the
25125 status of ATPCS support, so instead we create a dummy,
25126 empty, debug section called .arm.atpcs. */
25131 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25135 bfd_set_section_flags
25136 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25137 bfd_set_section_size (stdoutput
, sec
, 0);
25138 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25144 /* Record the CPU type as well. */
25145 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25146 mach
= bfd_mach_arm_iWMMXt2
;
25147 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25148 mach
= bfd_mach_arm_iWMMXt
;
25149 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25150 mach
= bfd_mach_arm_XScale
;
25151 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25152 mach
= bfd_mach_arm_ep9312
;
25153 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25154 mach
= bfd_mach_arm_5TE
;
25155 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25158 mach
= bfd_mach_arm_5T
;
25160 mach
= bfd_mach_arm_5
;
25162 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25164 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25165 mach
= bfd_mach_arm_4T
;
25167 mach
= bfd_mach_arm_4
;
25169 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25170 mach
= bfd_mach_arm_3M
;
25171 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25172 mach
= bfd_mach_arm_3
;
25173 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25174 mach
= bfd_mach_arm_2a
;
25175 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25176 mach
= bfd_mach_arm_2
;
25178 mach
= bfd_mach_arm_unknown
;
25180 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25183 /* Command line processing. */
25186 Invocation line includes a switch not recognized by the base assembler.
25187 See if it's a processor-specific option.
25189 This routine is somewhat complicated by the need for backwards
25190 compatibility (since older releases of gcc can't be changed).
25191 The new options try to make the interface as compatible as
25194 New options (supported) are:
25196 -mcpu=<cpu name> Assemble for selected processor
25197 -march=<architecture name> Assemble for selected architecture
25198 -mfpu=<fpu architecture> Assemble for selected FPU.
25199 -EB/-mbig-endian Big-endian
25200 -EL/-mlittle-endian Little-endian
25201 -k Generate PIC code
25202 -mthumb Start in Thumb mode
25203 -mthumb-interwork Code supports ARM/Thumb interworking
25205 -m[no-]warn-deprecated Warn about deprecated features
25206 -m[no-]warn-syms Warn when symbols match instructions
25208 For now we will also provide support for:
25210 -mapcs-32 32-bit Program counter
25211 -mapcs-26 26-bit Program counter
25212 -macps-float Floats passed in FP registers
25213 -mapcs-reentrant Reentrant code
25215 (sometime these will probably be replaced with -mapcs=<list of options>
25216 and -matpcs=<list of options>)
25218 The remaining options are only supported for back-wards compatibility.
25219 Cpu variants, the arm part is optional:
25220 -m[arm]1 Currently not supported.
25221 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25222 -m[arm]3 Arm 3 processor
25223 -m[arm]6[xx], Arm 6 processors
25224 -m[arm]7[xx][t][[d]m] Arm 7 processors
25225 -m[arm]8[10] Arm 8 processors
25226 -m[arm]9[20][tdmi] Arm 9 processors
25227 -mstrongarm[110[0]] StrongARM processors
25228 -mxscale XScale processors
25229 -m[arm]v[2345[t[e]]] Arm architectures
25230 -mall All (except the ARM1)
25232 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25233 -mfpe-old (No float load/store multiples)
25234 -mvfpxd VFP Single precision
25236 -mno-fpu Disable all floating point instructions
25238 The following CPU names are recognized:
25239 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25240 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25241 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25242 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25243 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25244 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25245 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25249 const char * md_shortopts
= "m:k";
25251 #ifdef ARM_BI_ENDIAN
25252 #define OPTION_EB (OPTION_MD_BASE + 0)
25253 #define OPTION_EL (OPTION_MD_BASE + 1)
25255 #if TARGET_BYTES_BIG_ENDIAN
25256 #define OPTION_EB (OPTION_MD_BASE + 0)
25258 #define OPTION_EL (OPTION_MD_BASE + 1)
25261 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25263 struct option md_longopts
[] =
25266 {"EB", no_argument
, NULL
, OPTION_EB
},
25269 {"EL", no_argument
, NULL
, OPTION_EL
},
25271 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25272 {NULL
, no_argument
, NULL
, 0}
25276 size_t md_longopts_size
= sizeof (md_longopts
);
25278 struct arm_option_table
25280 const char *option
; /* Option name to match. */
25281 const char *help
; /* Help information. */
25282 int *var
; /* Variable to change. */
25283 int value
; /* What to change it to. */
25284 const char *deprecated
; /* If non-null, print this message. */
25287 struct arm_option_table arm_opts
[] =
25289 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25290 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25291 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25292 &support_interwork
, 1, NULL
},
25293 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25294 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25295 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25297 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25298 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25299 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25300 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25303 /* These are recognized by the assembler, but have no affect on code. */
25304 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25305 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25307 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25308 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25309 &warn_on_deprecated
, 0, NULL
},
25310 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25311 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25312 {NULL
, NULL
, NULL
, 0, NULL
}
25315 struct arm_legacy_option_table
25317 const char *option
; /* Option name to match. */
25318 const arm_feature_set
**var
; /* Variable to change. */
25319 const arm_feature_set value
; /* What to change it to. */
25320 const char *deprecated
; /* If non-null, print this message. */
25323 const struct arm_legacy_option_table arm_legacy_opts
[] =
25325 /* DON'T add any new processors to this list -- we want the whole list
25326 to go away... Add them to the processors table instead. */
25327 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25328 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25329 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25330 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25331 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25332 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25333 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25334 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25335 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25336 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25337 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25338 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25339 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25340 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25341 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25342 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25343 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25344 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25345 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25346 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25347 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25348 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25349 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25350 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25351 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25352 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25353 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25354 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25355 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25356 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25357 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25358 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25359 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25360 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25361 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25362 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25363 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25364 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25365 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25366 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25367 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25368 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25369 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25370 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25371 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25372 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25373 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25374 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25375 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25376 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25377 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25378 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25379 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25380 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25381 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25382 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25383 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25384 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25385 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25386 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25387 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25388 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25389 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25390 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25391 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25392 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25393 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25394 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25395 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25396 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25397 N_("use -mcpu=strongarm110")},
25398 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25399 N_("use -mcpu=strongarm1100")},
25400 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25401 N_("use -mcpu=strongarm1110")},
25402 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25403 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25404 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25406 /* Architecture variants -- don't add any more to this list either. */
25407 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25408 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25409 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25410 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25411 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25412 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25413 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25414 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25415 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25416 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25417 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25418 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25419 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25420 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25421 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25422 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25423 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25424 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25426 /* Floating point variants -- don't add any more to this list either. */
25427 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25428 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25429 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25430 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25431 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25433 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25436 struct arm_cpu_option_table
25440 const arm_feature_set value
;
25441 /* For some CPUs we assume an FPU unless the user explicitly sets
25443 const arm_feature_set default_fpu
;
25444 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25446 const char *canonical_name
;
25449 /* This list should, at a minimum, contain all the cpu names
25450 recognized by GCC. */
25451 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25452 static const struct arm_cpu_option_table arm_cpus
[] =
25454 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25455 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25456 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25457 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25458 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25459 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25460 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25461 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25462 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25463 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25464 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25465 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25466 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25467 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25468 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25469 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25470 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25471 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25472 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25473 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25474 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25475 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25476 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25477 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25478 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25479 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25480 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25481 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25482 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25483 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25484 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25485 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25486 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25487 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25488 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25489 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25490 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25491 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25492 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25493 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25494 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25495 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25496 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25497 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25498 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25499 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25500 /* For V5 or later processors we default to using VFP; but the user
25501 should really set the FPU type explicitly. */
25502 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25503 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25504 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25505 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25506 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25507 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25508 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25509 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25510 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25511 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25512 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25513 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25514 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25515 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25516 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25517 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25518 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25519 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25520 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25521 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25523 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25524 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25525 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25526 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25527 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25528 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25529 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25530 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25531 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25533 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25534 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25535 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25536 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25537 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25538 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25539 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25540 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25541 FPU_NONE
, "Cortex-A5"),
25542 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25544 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25545 ARM_FEATURE_COPROC (FPU_VFP_V3
25546 | FPU_NEON_EXT_V1
),
25548 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25549 ARM_FEATURE_COPROC (FPU_VFP_V3
25550 | FPU_NEON_EXT_V1
),
25552 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25554 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25556 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25558 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25560 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25562 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25564 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25566 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25568 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25570 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25571 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25573 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25574 FPU_NONE
, "Cortex-R5"),
25575 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25576 FPU_ARCH_VFP_V3D16
,
25578 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25579 FPU_ARCH_VFP_V3D16
,
25581 ARM_CPU_OPT ("cortex-m33", ARM_ARCH_V8M_MAIN_DSP
,
25582 FPU_NONE
, "Cortex-M33"),
25583 ARM_CPU_OPT ("cortex-m23", ARM_ARCH_V8M_BASE
,
25584 FPU_NONE
, "Cortex-M23"),
25585 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25586 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25587 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25588 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25589 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25590 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25591 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25594 ARM_CPU_OPT ("falkor", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25597 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25601 /* ??? XSCALE is really an architecture. */
25602 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25603 /* ??? iwmmxt is not a processor. */
25604 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25605 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25606 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25608 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25609 FPU_ARCH_MAVERICK
, "ARM920T"),
25610 /* Marvell processors. */
25611 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25613 ARM_EXT2_V6T2_V8M
),
25614 FPU_ARCH_VFP_V3D16
, NULL
),
25615 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25617 ARM_EXT2_V6T2_V8M
),
25618 FPU_ARCH_NEON_VFP_V4
, NULL
),
25619 /* APM X-Gene family. */
25620 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25622 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25625 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25629 struct arm_arch_option_table
25633 const arm_feature_set value
;
25634 const arm_feature_set default_fpu
;
25637 /* This list should, at a minimum, contain all the architecture names
25638 recognized by GCC. */
25639 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25640 static const struct arm_arch_option_table arm_archs
[] =
25642 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25643 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25644 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25645 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25646 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25647 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25648 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25649 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25650 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25651 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25652 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25653 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25654 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25655 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25656 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25657 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25658 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25659 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25660 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25661 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25662 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25663 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25664 kept to preserve existing behaviour. */
25665 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25666 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25667 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25668 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25669 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25670 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25671 kept to preserve existing behaviour. */
25672 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25673 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25674 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25675 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25676 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25677 /* The official spelling of the ARMv7 profile variants is the dashed form.
25678 Accept the non-dashed form for compatibility with old toolchains. */
25679 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25680 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25681 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25682 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25683 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25684 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25685 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25686 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25687 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25688 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25689 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25690 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25691 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25692 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25693 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25694 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25695 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25696 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25698 #undef ARM_ARCH_OPT
25700 /* ISA extensions in the co-processor and main instruction set space. */
25701 struct arm_option_extension_value_table
25705 const arm_feature_set merge_value
;
25706 const arm_feature_set clear_value
;
25707 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25708 indicates that an extension is available for all architectures while
25709 ARM_ANY marks an empty entry. */
25710 const arm_feature_set allowed_archs
[2];
25713 /* The following table must be in alphabetical order with a NULL last entry.
25715 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25716 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25717 static const struct arm_option_extension_value_table arm_extensions
[] =
25719 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25720 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25721 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25722 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25723 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25724 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25725 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25726 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25727 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25728 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25729 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25730 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25732 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25733 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25734 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25735 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25736 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25737 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25738 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25739 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25740 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25741 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25742 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25743 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25744 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25745 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25746 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25747 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25748 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25749 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25750 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25751 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25752 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25753 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25754 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25755 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25756 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25757 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25758 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25759 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25760 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25761 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25762 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25763 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25764 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25765 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25767 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25768 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25769 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25770 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25771 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25775 /* ISA floating-point and Advanced SIMD extensions. */
25776 struct arm_option_fpu_value_table
25779 const arm_feature_set value
;
25782 /* This list should, at a minimum, contain all the fpu names
25783 recognized by GCC. */
25784 static const struct arm_option_fpu_value_table arm_fpus
[] =
25786 {"softfpa", FPU_NONE
},
25787 {"fpe", FPU_ARCH_FPE
},
25788 {"fpe2", FPU_ARCH_FPE
},
25789 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25790 {"fpa", FPU_ARCH_FPA
},
25791 {"fpa10", FPU_ARCH_FPA
},
25792 {"fpa11", FPU_ARCH_FPA
},
25793 {"arm7500fe", FPU_ARCH_FPA
},
25794 {"softvfp", FPU_ARCH_VFP
},
25795 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25796 {"vfp", FPU_ARCH_VFP_V2
},
25797 {"vfp9", FPU_ARCH_VFP_V2
},
25798 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
25799 {"vfp10", FPU_ARCH_VFP_V2
},
25800 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25801 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25802 {"vfpv2", FPU_ARCH_VFP_V2
},
25803 {"vfpv3", FPU_ARCH_VFP_V3
},
25804 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25805 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25806 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25807 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25808 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25809 {"arm1020t", FPU_ARCH_VFP_V1
},
25810 {"arm1020e", FPU_ARCH_VFP_V2
},
25811 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
25812 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25813 {"maverick", FPU_ARCH_MAVERICK
},
25814 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25815 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25816 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25817 {"vfpv4", FPU_ARCH_VFP_V4
},
25818 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25819 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25820 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25821 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25822 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25823 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25824 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25825 {"crypto-neon-fp-armv8",
25826 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25827 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25828 {"crypto-neon-fp-armv8.1",
25829 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25830 {NULL
, ARM_ARCH_NONE
}
25833 struct arm_option_value_table
25839 static const struct arm_option_value_table arm_float_abis
[] =
25841 {"hard", ARM_FLOAT_ABI_HARD
},
25842 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25843 {"soft", ARM_FLOAT_ABI_SOFT
},
25848 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25849 static const struct arm_option_value_table arm_eabis
[] =
25851 {"gnu", EF_ARM_EABI_UNKNOWN
},
25852 {"4", EF_ARM_EABI_VER4
},
25853 {"5", EF_ARM_EABI_VER5
},
25858 struct arm_long_option_table
25860 const char * option
; /* Substring to match. */
25861 const char * help
; /* Help information. */
25862 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25863 const char * deprecated
; /* If non-null, print this message. */
25867 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25869 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25871 /* We insist on extensions being specified in alphabetical order, and with
25872 extensions being added before being removed. We achieve this by having
25873 the global ARM_EXTENSIONS table in alphabetical order, and using the
25874 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25875 or removing it (0) and only allowing it to change in the order
25877 const struct arm_option_extension_value_table
* opt
= NULL
;
25878 const arm_feature_set arm_any
= ARM_ANY
;
25879 int adding_value
= -1;
25881 /* Copy the feature set, so that we can modify it. */
25882 *ext_set
= **opt_p
;
25885 while (str
!= NULL
&& *str
!= 0)
25892 as_bad (_("invalid architectural extension"));
25897 ext
= strchr (str
, '+');
25902 len
= strlen (str
);
25904 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25906 if (adding_value
!= 0)
25909 opt
= arm_extensions
;
25917 if (adding_value
== -1)
25920 opt
= arm_extensions
;
25922 else if (adding_value
!= 1)
25924 as_bad (_("must specify extensions to add before specifying "
25925 "those to remove"));
25932 as_bad (_("missing architectural extension"));
25936 gas_assert (adding_value
!= -1);
25937 gas_assert (opt
!= NULL
);
25939 /* Scan over the options table trying to find an exact match. */
25940 for (; opt
->name
!= NULL
; opt
++)
25941 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25943 int i
, nb_allowed_archs
=
25944 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25945 /* Check we can apply the extension to this architecture. */
25946 for (i
= 0; i
< nb_allowed_archs
; i
++)
25949 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25951 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25954 if (i
== nb_allowed_archs
)
25956 as_bad (_("extension does not apply to the base architecture"));
25960 /* Add or remove the extension. */
25962 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25964 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25969 if (opt
->name
== NULL
)
25971 /* Did we fail to find an extension because it wasn't specified in
25972 alphabetical order, or because it does not exist? */
25974 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25975 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25978 if (opt
->name
== NULL
)
25979 as_bad (_("unknown architectural extension `%s'"), str
);
25981 as_bad (_("architectural extensions must be specified in "
25982 "alphabetical order"));
25988 /* We should skip the extension we've just matched the next time
26000 arm_parse_cpu (const char *str
)
26002 const struct arm_cpu_option_table
*opt
;
26003 const char *ext
= strchr (str
, '+');
26009 len
= strlen (str
);
26013 as_bad (_("missing cpu name `%s'"), str
);
26017 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26018 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26020 mcpu_cpu_opt
= &opt
->value
;
26021 mcpu_fpu_opt
= &opt
->default_fpu
;
26022 if (opt
->canonical_name
)
26024 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26025 strcpy (selected_cpu_name
, opt
->canonical_name
);
26031 if (len
>= sizeof selected_cpu_name
)
26032 len
= (sizeof selected_cpu_name
) - 1;
26034 for (i
= 0; i
< len
; i
++)
26035 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26036 selected_cpu_name
[i
] = 0;
26040 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
26045 as_bad (_("unknown cpu `%s'"), str
);
26050 arm_parse_arch (const char *str
)
26052 const struct arm_arch_option_table
*opt
;
26053 const char *ext
= strchr (str
, '+');
26059 len
= strlen (str
);
26063 as_bad (_("missing architecture name `%s'"), str
);
26067 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26068 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26070 march_cpu_opt
= &opt
->value
;
26071 march_fpu_opt
= &opt
->default_fpu
;
26072 strcpy (selected_cpu_name
, opt
->name
);
26075 return arm_parse_extension (ext
, &march_cpu_opt
);
26080 as_bad (_("unknown architecture `%s'\n"), str
);
26085 arm_parse_fpu (const char * str
)
26087 const struct arm_option_fpu_value_table
* opt
;
26089 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26090 if (streq (opt
->name
, str
))
26092 mfpu_opt
= &opt
->value
;
26096 as_bad (_("unknown floating point format `%s'\n"), str
);
26101 arm_parse_float_abi (const char * str
)
26103 const struct arm_option_value_table
* opt
;
26105 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26106 if (streq (opt
->name
, str
))
26108 mfloat_abi_opt
= opt
->value
;
26112 as_bad (_("unknown floating point abi `%s'\n"), str
);
26118 arm_parse_eabi (const char * str
)
26120 const struct arm_option_value_table
*opt
;
26122 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26123 if (streq (opt
->name
, str
))
26125 meabi_flags
= opt
->value
;
26128 as_bad (_("unknown EABI `%s'\n"), str
);
26134 arm_parse_it_mode (const char * str
)
26136 bfd_boolean ret
= TRUE
;
26138 if (streq ("arm", str
))
26139 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26140 else if (streq ("thumb", str
))
26141 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26142 else if (streq ("always", str
))
26143 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26144 else if (streq ("never", str
))
26145 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26148 as_bad (_("unknown implicit IT mode `%s', should be "\
26149 "arm, thumb, always, or never."), str
);
26157 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26159 codecomposer_syntax
= TRUE
;
26160 arm_comment_chars
[0] = ';';
26161 arm_line_separator_chars
[0] = 0;
26165 struct arm_long_option_table arm_long_opts
[] =
26167 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26168 arm_parse_cpu
, NULL
},
26169 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26170 arm_parse_arch
, NULL
},
26171 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26172 arm_parse_fpu
, NULL
},
26173 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26174 arm_parse_float_abi
, NULL
},
26176 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26177 arm_parse_eabi
, NULL
},
26179 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26180 arm_parse_it_mode
, NULL
},
26181 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26182 arm_ccs_mode
, NULL
},
26183 {NULL
, NULL
, 0, NULL
}
26187 md_parse_option (int c
, const char * arg
)
26189 struct arm_option_table
*opt
;
26190 const struct arm_legacy_option_table
*fopt
;
26191 struct arm_long_option_table
*lopt
;
26197 target_big_endian
= 1;
26203 target_big_endian
= 0;
26207 case OPTION_FIX_V4BX
:
26212 /* Listing option. Just ignore these, we don't support additional
26217 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26219 if (c
== opt
->option
[0]
26220 && ((arg
== NULL
&& opt
->option
[1] == 0)
26221 || streq (arg
, opt
->option
+ 1)))
26223 /* If the option is deprecated, tell the user. */
26224 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26225 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26226 arg
? arg
: "", _(opt
->deprecated
));
26228 if (opt
->var
!= NULL
)
26229 *opt
->var
= opt
->value
;
26235 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26237 if (c
== fopt
->option
[0]
26238 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26239 || streq (arg
, fopt
->option
+ 1)))
26241 /* If the option is deprecated, tell the user. */
26242 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26243 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26244 arg
? arg
: "", _(fopt
->deprecated
));
26246 if (fopt
->var
!= NULL
)
26247 *fopt
->var
= &fopt
->value
;
26253 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26255 /* These options are expected to have an argument. */
26256 if (c
== lopt
->option
[0]
26258 && strncmp (arg
, lopt
->option
+ 1,
26259 strlen (lopt
->option
+ 1)) == 0)
26261 /* If the option is deprecated, tell the user. */
26262 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26263 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26264 _(lopt
->deprecated
));
26266 /* Call the sup-option parser. */
26267 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26278 md_show_usage (FILE * fp
)
26280 struct arm_option_table
*opt
;
26281 struct arm_long_option_table
*lopt
;
26283 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26285 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26286 if (opt
->help
!= NULL
)
26287 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26289 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26290 if (lopt
->help
!= NULL
)
26291 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26295 -EB assemble code for a big-endian cpu\n"));
26300 -EL assemble code for a little-endian cpu\n"));
26304 --fix-v4bx Allow BX in ARMv4 code\n"));
26312 arm_feature_set flags
;
26313 } cpu_arch_ver_table
;
26315 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26316 must be sorted least features first but some reordering is needed, eg. for
26317 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26318 static const cpu_arch_ver_table cpu_arch_ver
[] =
26324 {4, ARM_ARCH_V5TE
},
26325 {5, ARM_ARCH_V5TEJ
},
26329 {11, ARM_ARCH_V6M
},
26330 {12, ARM_ARCH_V6SM
},
26331 {8, ARM_ARCH_V6T2
},
26332 {10, ARM_ARCH_V7VE
},
26333 {10, ARM_ARCH_V7R
},
26334 {10, ARM_ARCH_V7M
},
26335 {14, ARM_ARCH_V8A
},
26336 {16, ARM_ARCH_V8M_BASE
},
26337 {17, ARM_ARCH_V8M_MAIN
},
26341 /* Set an attribute if it has not already been set by the user. */
26343 aeabi_set_attribute_int (int tag
, int value
)
26346 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26347 || !attributes_set_explicitly
[tag
])
26348 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26352 aeabi_set_attribute_string (int tag
, const char *value
)
26355 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26356 || !attributes_set_explicitly
[tag
])
26357 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26360 /* Set the public EABI object attributes. */
26362 aeabi_set_public_attributes (void)
26367 int fp16_optional
= 0;
26368 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26369 arm_feature_set flags
;
26370 arm_feature_set tmp
;
26371 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26372 const cpu_arch_ver_table
*p
;
26374 /* Choose the architecture based on the capabilities of the requested cpu
26375 (if any) and/or the instructions actually used. */
26376 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26377 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26378 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26380 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26381 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26383 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26384 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26386 selected_cpu
= flags
;
26388 /* Allow the user to override the reported architecture. */
26391 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26392 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26395 /* We need to make sure that the attributes do not identify us as v6S-M
26396 when the only v6S-M feature in use is the Operating System Extensions. */
26397 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26398 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26399 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26403 for (p
= cpu_arch_ver
; p
->val
; p
++)
26405 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26408 arm_arch
= p
->flags
;
26409 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26413 /* The table lookup above finds the last architecture to contribute
26414 a new feature. Unfortunately, Tag13 is a subset of the union of
26415 v6T2 and v7-M, so it is never seen as contributing a new feature.
26416 We can not search for the last entry which is entirely used,
26417 because if no CPU is specified we build up only those flags
26418 actually used. Perhaps we should separate out the specified
26419 and implicit cases. Avoid taking this path for -march=all by
26420 checking for contradictory v7-A / v7-M features. */
26421 if (arch
== TAG_CPU_ARCH_V7
26422 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26423 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26424 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26426 arch
= TAG_CPU_ARCH_V7E_M
;
26427 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26430 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26431 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26433 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26434 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26437 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26438 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26439 ARMv8-M, -march=all must be detected as ARMv8-A. */
26440 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26441 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26443 arch
= TAG_CPU_ARCH_V8
;
26444 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26447 /* Tag_CPU_name. */
26448 if (selected_cpu_name
[0])
26452 q
= selected_cpu_name
;
26453 if (strncmp (q
, "armv", 4) == 0)
26458 for (i
= 0; q
[i
]; i
++)
26459 q
[i
] = TOUPPER (q
[i
]);
26461 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26464 /* Tag_CPU_arch. */
26465 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26467 /* Tag_CPU_arch_profile. */
26468 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26469 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26470 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26471 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26473 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26475 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26480 if (profile
!= '\0')
26481 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26483 /* Tag_DSP_extension. */
26484 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26486 arm_feature_set ext
;
26488 /* DSP instructions not in architecture. */
26489 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26490 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26491 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26494 /* Tag_ARM_ISA_use. */
26495 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26497 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26499 /* Tag_THUMB_ISA_use. */
26500 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26505 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26506 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26508 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26512 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26515 /* Tag_VFP_arch. */
26516 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26517 aeabi_set_attribute_int (Tag_VFP_arch
,
26518 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26520 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26521 aeabi_set_attribute_int (Tag_VFP_arch
,
26522 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26524 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26527 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26529 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26531 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26534 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26535 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26536 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26537 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26538 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26540 /* Tag_ABI_HardFP_use. */
26541 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26542 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26543 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26545 /* Tag_WMMX_arch. */
26546 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26547 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26548 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26549 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26551 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26552 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26553 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26554 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26555 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26556 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26558 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26560 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26564 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26569 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26570 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26571 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26575 We set Tag_DIV_use to two when integer divide instructions have been used
26576 in ARM state, or when Thumb integer divide instructions have been used,
26577 but we have no architecture profile set, nor have we any ARM instructions.
26579 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26580 by the base architecture.
26582 For new architectures we will have to check these tests. */
26583 gas_assert (arch
<= TAG_CPU_ARCH_V8
26584 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26585 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26586 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26587 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26588 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26589 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26590 || (profile
== '\0'
26591 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26592 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26593 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26595 /* Tag_MP_extension_use. */
26596 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26597 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26599 /* Tag Virtualization_use. */
26600 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26602 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26605 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26608 /* Add the default contents for the .ARM.attributes section. */
26612 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26615 aeabi_set_public_attributes ();
26617 #endif /* OBJ_ELF */
26620 /* Parse a .cpu directive. */
26623 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26625 const struct arm_cpu_option_table
*opt
;
26629 name
= input_line_pointer
;
26630 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26631 input_line_pointer
++;
26632 saved_char
= *input_line_pointer
;
26633 *input_line_pointer
= 0;
26635 /* Skip the first "all" entry. */
26636 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26637 if (streq (opt
->name
, name
))
26639 mcpu_cpu_opt
= &opt
->value
;
26640 selected_cpu
= opt
->value
;
26641 if (opt
->canonical_name
)
26642 strcpy (selected_cpu_name
, opt
->canonical_name
);
26646 for (i
= 0; opt
->name
[i
]; i
++)
26647 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26649 selected_cpu_name
[i
] = 0;
26651 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26652 *input_line_pointer
= saved_char
;
26653 demand_empty_rest_of_line ();
26656 as_bad (_("unknown cpu `%s'"), name
);
26657 *input_line_pointer
= saved_char
;
26658 ignore_rest_of_line ();
26662 /* Parse a .arch directive. */
26665 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26667 const struct arm_arch_option_table
*opt
;
26671 name
= input_line_pointer
;
26672 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26673 input_line_pointer
++;
26674 saved_char
= *input_line_pointer
;
26675 *input_line_pointer
= 0;
26677 /* Skip the first "all" entry. */
26678 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26679 if (streq (opt
->name
, name
))
26681 mcpu_cpu_opt
= &opt
->value
;
26682 selected_cpu
= opt
->value
;
26683 strcpy (selected_cpu_name
, opt
->name
);
26684 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26685 *input_line_pointer
= saved_char
;
26686 demand_empty_rest_of_line ();
26690 as_bad (_("unknown architecture `%s'\n"), name
);
26691 *input_line_pointer
= saved_char
;
26692 ignore_rest_of_line ();
26696 /* Parse a .object_arch directive. */
26699 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26701 const struct arm_arch_option_table
*opt
;
26705 name
= input_line_pointer
;
26706 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26707 input_line_pointer
++;
26708 saved_char
= *input_line_pointer
;
26709 *input_line_pointer
= 0;
26711 /* Skip the first "all" entry. */
26712 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26713 if (streq (opt
->name
, name
))
26715 object_arch
= &opt
->value
;
26716 *input_line_pointer
= saved_char
;
26717 demand_empty_rest_of_line ();
26721 as_bad (_("unknown architecture `%s'\n"), name
);
26722 *input_line_pointer
= saved_char
;
26723 ignore_rest_of_line ();
26726 /* Parse a .arch_extension directive. */
26729 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26731 const struct arm_option_extension_value_table
*opt
;
26732 const arm_feature_set arm_any
= ARM_ANY
;
26735 int adding_value
= 1;
26737 name
= input_line_pointer
;
26738 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26739 input_line_pointer
++;
26740 saved_char
= *input_line_pointer
;
26741 *input_line_pointer
= 0;
26743 if (strlen (name
) >= 2
26744 && strncmp (name
, "no", 2) == 0)
26750 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26751 if (streq (opt
->name
, name
))
26753 int i
, nb_allowed_archs
=
26754 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26755 for (i
= 0; i
< nb_allowed_archs
; i
++)
26758 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26760 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26764 if (i
== nb_allowed_archs
)
26766 as_bad (_("architectural extension `%s' is not allowed for the "
26767 "current base architecture"), name
);
26772 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26775 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26777 mcpu_cpu_opt
= &selected_cpu
;
26778 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26779 *input_line_pointer
= saved_char
;
26780 demand_empty_rest_of_line ();
26784 if (opt
->name
== NULL
)
26785 as_bad (_("unknown architecture extension `%s'\n"), name
);
26787 *input_line_pointer
= saved_char
;
26788 ignore_rest_of_line ();
26791 /* Parse a .fpu directive. */
26794 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26796 const struct arm_option_fpu_value_table
*opt
;
26800 name
= input_line_pointer
;
26801 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26802 input_line_pointer
++;
26803 saved_char
= *input_line_pointer
;
26804 *input_line_pointer
= 0;
26806 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26807 if (streq (opt
->name
, name
))
26809 mfpu_opt
= &opt
->value
;
26810 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26811 *input_line_pointer
= saved_char
;
26812 demand_empty_rest_of_line ();
26816 as_bad (_("unknown floating point format `%s'\n"), name
);
26817 *input_line_pointer
= saved_char
;
26818 ignore_rest_of_line ();
26821 /* Copy symbol information. */
26824 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26826 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26830 /* Given a symbolic attribute NAME, return the proper integer value.
26831 Returns -1 if the attribute is not known. */
26834 arm_convert_symbolic_attribute (const char *name
)
26836 static const struct
26841 attribute_table
[] =
26843 /* When you modify this table you should
26844 also modify the list in doc/c-arm.texi. */
26845 #define T(tag) {#tag, tag}
26846 T (Tag_CPU_raw_name
),
26849 T (Tag_CPU_arch_profile
),
26850 T (Tag_ARM_ISA_use
),
26851 T (Tag_THUMB_ISA_use
),
26855 T (Tag_Advanced_SIMD_arch
),
26856 T (Tag_PCS_config
),
26857 T (Tag_ABI_PCS_R9_use
),
26858 T (Tag_ABI_PCS_RW_data
),
26859 T (Tag_ABI_PCS_RO_data
),
26860 T (Tag_ABI_PCS_GOT_use
),
26861 T (Tag_ABI_PCS_wchar_t
),
26862 T (Tag_ABI_FP_rounding
),
26863 T (Tag_ABI_FP_denormal
),
26864 T (Tag_ABI_FP_exceptions
),
26865 T (Tag_ABI_FP_user_exceptions
),
26866 T (Tag_ABI_FP_number_model
),
26867 T (Tag_ABI_align_needed
),
26868 T (Tag_ABI_align8_needed
),
26869 T (Tag_ABI_align_preserved
),
26870 T (Tag_ABI_align8_preserved
),
26871 T (Tag_ABI_enum_size
),
26872 T (Tag_ABI_HardFP_use
),
26873 T (Tag_ABI_VFP_args
),
26874 T (Tag_ABI_WMMX_args
),
26875 T (Tag_ABI_optimization_goals
),
26876 T (Tag_ABI_FP_optimization_goals
),
26877 T (Tag_compatibility
),
26878 T (Tag_CPU_unaligned_access
),
26879 T (Tag_FP_HP_extension
),
26880 T (Tag_VFP_HP_extension
),
26881 T (Tag_ABI_FP_16bit_format
),
26882 T (Tag_MPextension_use
),
26884 T (Tag_nodefaults
),
26885 T (Tag_also_compatible_with
),
26886 T (Tag_conformance
),
26888 T (Tag_Virtualization_use
),
26889 T (Tag_DSP_extension
),
26890 /* We deliberately do not include Tag_MPextension_use_legacy. */
26898 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26899 if (streq (name
, attribute_table
[i
].name
))
26900 return attribute_table
[i
].tag
;
26906 /* Apply sym value for relocations only in the case that they are for
26907 local symbols in the same segment as the fixup and you have the
26908 respective architectural feature for blx and simple switches. */
26910 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26913 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26914 /* PR 17444: If the local symbol is in a different section then a reloc
26915 will always be generated for it, so applying the symbol value now
26916 will result in a double offset being stored in the relocation. */
26917 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26918 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26920 switch (fixP
->fx_r_type
)
26922 case BFD_RELOC_ARM_PCREL_BLX
:
26923 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26924 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26928 case BFD_RELOC_ARM_PCREL_CALL
:
26929 case BFD_RELOC_THUMB_PCREL_BLX
:
26930 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26941 #endif /* OBJ_ELF */