1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
247 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
252 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
253 symbolS
* GOT_symbol
;
256 /* 0: assemble for ARM,
257 1: assemble for Thumb,
258 2: assemble for Thumb even though target CPU does not support thumb
260 static int thumb_mode
= 0;
262 /* If unified_syntax is true, we are processing the new unified
263 ARM/Thumb syntax. Important differences from the old ARM mode:
265 - Immediate operands do not require a # prefix.
266 - Conditional affixes always appear at the end of the
267 instruction. (For backward compatibility, those instructions
268 that formerly had them in the middle, continue to accept them
270 - The IT instruction may appear, and if it does is validated
271 against subsequent conditional affixes. It does not generate
274 Important differences from the old Thumb mode:
276 - Immediate operands do not require a # prefix.
277 - Most of the V6T2 instructions are only available in unified mode.
278 - The .N and .W suffixes are recognized and honored (it is an error
279 if they cannot be honored).
280 - All instructions set the flags if and only if they have an 's' affix.
281 - Conditional affixes may be used. They are validated against
282 preceding IT instructions. Unlike ARM mode, you cannot use a
283 conditional affix except in the scope of an IT instruction. */
285 static bfd_boolean unified_syntax
= FALSE
;
300 enum neon_el_type type
;
304 #define NEON_MAX_TYPE_ELS 4
308 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
315 unsigned long instruction
;
319 /* "uncond_value" is set to the value in place of the conditional field in
320 unconditional versions of the instruction, or -1 if nothing is
323 struct neon_type vectype
;
324 /* Set to the opcode if the instruction needs relaxation.
325 Zero if the instruction is not relaxed. */
329 bfd_reloc_code_real_type type
;
338 struct neon_type_el vectype
;
339 unsigned present
: 1; /* Operand present. */
340 unsigned isreg
: 1; /* Operand was a register. */
341 unsigned immisreg
: 1; /* .imm field is a second register. */
342 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
343 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
344 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
345 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
346 instructions. This allows us to disambiguate ARM <-> vector insns. */
347 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
348 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
349 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
350 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
351 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
352 unsigned writeback
: 1; /* Operand has trailing ! */
353 unsigned preind
: 1; /* Preindexed address. */
354 unsigned postind
: 1; /* Postindexed address. */
355 unsigned negative
: 1; /* Index register was negated. */
356 unsigned shifted
: 1; /* Shift applied to operation. */
357 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
361 static struct arm_it inst
;
363 #define NUM_FLOAT_VALS 8
365 const char * fp_const
[] =
367 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
370 /* Number of littlenums required to hold an extended precision number. */
371 #define MAX_LITTLENUMS 6
373 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
383 #define CP_T_X 0x00008000
384 #define CP_T_Y 0x00400000
386 #define CONDS_BIT 0x00100000
387 #define LOAD_BIT 0x00100000
389 #define DOUBLE_LOAD_FLAG 0x00000001
393 const char * template;
397 #define COND_ALWAYS 0xE
401 const char *template;
405 struct asm_barrier_opt
407 const char *template;
411 /* The bit that distinguishes CPSR and SPSR. */
412 #define SPSR_BIT (1 << 22)
414 /* The individual PSR flag bits. */
415 #define PSR_c (1 << 16)
416 #define PSR_x (1 << 17)
417 #define PSR_s (1 << 18)
418 #define PSR_f (1 << 19)
423 bfd_reloc_code_real_type reloc
;
428 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
429 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
434 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
437 /* Bits for DEFINED field in neon_typed_alias. */
438 #define NTA_HASTYPE 1
439 #define NTA_HASINDEX 2
441 struct neon_typed_alias
443 unsigned char defined
;
445 struct neon_type_el eltype
;
448 /* ARM register categories. This includes coprocessor numbers and various
449 architecture extensions' registers. */
475 /* Structure for a hash table entry for a register.
476 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
477 information which states whether a vector type or index is specified (for a
478 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
482 unsigned char number
;
484 unsigned char builtin
;
485 struct neon_typed_alias
*neon
;
488 /* Diagnostics used when we don't get a register of the expected type. */
489 const char *const reg_expected_msgs
[] =
491 N_("ARM register expected"),
492 N_("bad or missing co-processor number"),
493 N_("co-processor register expected"),
494 N_("FPA register expected"),
495 N_("VFP single precision register expected"),
496 N_("VFP/Neon double precision register expected"),
497 N_("Neon quad precision register expected"),
498 N_("VFP single or double precision register expected"),
499 N_("Neon double or quad precision register expected"),
500 N_("VFP single, double or Neon quad precision register expected"),
501 N_("VFP system register expected"),
502 N_("Maverick MVF register expected"),
503 N_("Maverick MVD register expected"),
504 N_("Maverick MVFX register expected"),
505 N_("Maverick MVDX register expected"),
506 N_("Maverick MVAX register expected"),
507 N_("Maverick DSPSC register expected"),
508 N_("iWMMXt data register expected"),
509 N_("iWMMXt control register expected"),
510 N_("iWMMXt scalar register expected"),
511 N_("XScale accumulator register expected"),
514 /* Some well known registers that we refer to directly elsewhere. */
519 /* ARM instructions take 4bytes in the object file, Thumb instructions
525 /* Basic string to match. */
526 const char *template;
528 /* Parameters to instruction. */
529 unsigned char operands
[8];
531 /* Conditional tag - see opcode_lookup. */
532 unsigned int tag
: 4;
534 /* Basic instruction code. */
535 unsigned int avalue
: 28;
537 /* Thumb-format instruction code. */
540 /* Which architecture variant provides this instruction. */
541 const arm_feature_set
*avariant
;
542 const arm_feature_set
*tvariant
;
544 /* Function to call to encode instruction in ARM format. */
545 void (* aencode
) (void);
547 /* Function to call to encode instruction in Thumb format. */
548 void (* tencode
) (void);
551 /* Defines for various bits that we will want to toggle. */
552 #define INST_IMMEDIATE 0x02000000
553 #define OFFSET_REG 0x02000000
554 #define HWOFFSET_IMM 0x00400000
555 #define SHIFT_BY_REG 0x00000010
556 #define PRE_INDEX 0x01000000
557 #define INDEX_UP 0x00800000
558 #define WRITE_BACK 0x00200000
559 #define LDM_TYPE_2_OR_3 0x00400000
560 #define CPSI_MMOD 0x00020000
562 #define LITERAL_MASK 0xf000f000
563 #define OPCODE_MASK 0xfe1fffff
564 #define V4_STR_BIT 0x00000020
566 #define T2_SUBS_PC_LR 0xf3de8f00
568 #define DATA_OP_SHIFT 21
570 #define T2_OPCODE_MASK 0xfe1fffff
571 #define T2_DATA_OP_SHIFT 21
573 /* Codes to distinguish the arithmetic instructions. */
584 #define OPCODE_CMP 10
585 #define OPCODE_CMN 11
586 #define OPCODE_ORR 12
587 #define OPCODE_MOV 13
588 #define OPCODE_BIC 14
589 #define OPCODE_MVN 15
591 #define T2_OPCODE_AND 0
592 #define T2_OPCODE_BIC 1
593 #define T2_OPCODE_ORR 2
594 #define T2_OPCODE_ORN 3
595 #define T2_OPCODE_EOR 4
596 #define T2_OPCODE_ADD 8
597 #define T2_OPCODE_ADC 10
598 #define T2_OPCODE_SBC 11
599 #define T2_OPCODE_SUB 13
600 #define T2_OPCODE_RSB 14
602 #define T_OPCODE_MUL 0x4340
603 #define T_OPCODE_TST 0x4200
604 #define T_OPCODE_CMN 0x42c0
605 #define T_OPCODE_NEG 0x4240
606 #define T_OPCODE_MVN 0x43c0
608 #define T_OPCODE_ADD_R3 0x1800
609 #define T_OPCODE_SUB_R3 0x1a00
610 #define T_OPCODE_ADD_HI 0x4400
611 #define T_OPCODE_ADD_ST 0xb000
612 #define T_OPCODE_SUB_ST 0xb080
613 #define T_OPCODE_ADD_SP 0xa800
614 #define T_OPCODE_ADD_PC 0xa000
615 #define T_OPCODE_ADD_I8 0x3000
616 #define T_OPCODE_SUB_I8 0x3800
617 #define T_OPCODE_ADD_I3 0x1c00
618 #define T_OPCODE_SUB_I3 0x1e00
620 #define T_OPCODE_ASR_R 0x4100
621 #define T_OPCODE_LSL_R 0x4080
622 #define T_OPCODE_LSR_R 0x40c0
623 #define T_OPCODE_ROR_R 0x41c0
624 #define T_OPCODE_ASR_I 0x1000
625 #define T_OPCODE_LSL_I 0x0000
626 #define T_OPCODE_LSR_I 0x0800
628 #define T_OPCODE_MOV_I8 0x2000
629 #define T_OPCODE_CMP_I8 0x2800
630 #define T_OPCODE_CMP_LR 0x4280
631 #define T_OPCODE_MOV_HR 0x4600
632 #define T_OPCODE_CMP_HR 0x4500
634 #define T_OPCODE_LDR_PC 0x4800
635 #define T_OPCODE_LDR_SP 0x9800
636 #define T_OPCODE_STR_SP 0x9000
637 #define T_OPCODE_LDR_IW 0x6800
638 #define T_OPCODE_STR_IW 0x6000
639 #define T_OPCODE_LDR_IH 0x8800
640 #define T_OPCODE_STR_IH 0x8000
641 #define T_OPCODE_LDR_IB 0x7800
642 #define T_OPCODE_STR_IB 0x7000
643 #define T_OPCODE_LDR_RW 0x5800
644 #define T_OPCODE_STR_RW 0x5000
645 #define T_OPCODE_LDR_RH 0x5a00
646 #define T_OPCODE_STR_RH 0x5200
647 #define T_OPCODE_LDR_RB 0x5c00
648 #define T_OPCODE_STR_RB 0x5400
650 #define T_OPCODE_PUSH 0xb400
651 #define T_OPCODE_POP 0xbc00
653 #define T_OPCODE_BRANCH 0xe000
655 #define THUMB_SIZE 2 /* Size of thumb instruction. */
656 #define THUMB_PP_PC_LR 0x0100
657 #define THUMB_LOAD_BIT 0x0800
658 #define THUMB2_LOAD_BIT 0x00100000
660 #define BAD_ARGS _("bad arguments to instruction")
661 #define BAD_PC _("r15 not allowed here")
662 #define BAD_COND _("instruction cannot be conditional")
663 #define BAD_OVERLAP _("registers may not be the same")
664 #define BAD_HIREG _("lo register required")
665 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
666 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
667 #define BAD_BRANCH _("branch must be last instruction in IT block")
668 #define BAD_NOT_IT _("instruction not allowed in IT block")
669 #define BAD_FPU _("selected FPU does not support instruction")
671 static struct hash_control
*arm_ops_hsh
;
672 static struct hash_control
*arm_cond_hsh
;
673 static struct hash_control
*arm_shift_hsh
;
674 static struct hash_control
*arm_psr_hsh
;
675 static struct hash_control
*arm_v7m_psr_hsh
;
676 static struct hash_control
*arm_reg_hsh
;
677 static struct hash_control
*arm_reloc_hsh
;
678 static struct hash_control
*arm_barrier_opt_hsh
;
680 /* Stuff needed to resolve the label ambiguity
689 symbolS
* last_label_seen
;
690 static int label_is_thumb_function_name
= FALSE
;
692 /* Literal pool structure. Held on a per-section
693 and per-sub-section basis. */
695 #define MAX_LITERAL_POOL_SIZE 1024
696 typedef struct literal_pool
698 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
699 unsigned int next_free_entry
;
704 struct literal_pool
* next
;
707 /* Pointer to a linked list of literal pools. */
708 literal_pool
* list_of_pools
= NULL
;
710 /* State variables for IT block handling. */
711 static bfd_boolean current_it_mask
= 0;
712 static int current_cc
;
716 /* This array holds the chars that always start a comment. If the
717 pre-processor is disabled, these aren't very useful. */
718 const char comment_chars
[] = "@";
720 /* This array holds the chars that only start a comment at the beginning of
721 a line. If the line seems to have the form '# 123 filename'
722 .line and .file directives will appear in the pre-processed output. */
723 /* Note that input_file.c hand checks for '#' at the beginning of the
724 first line of the input file. This is because the compiler outputs
725 #NO_APP at the beginning of its output. */
726 /* Also note that comments like this one will always work. */
727 const char line_comment_chars
[] = "#";
729 const char line_separator_chars
[] = ";";
731 /* Chars that can be used to separate mant
732 from exp in floating point numbers. */
733 const char EXP_CHARS
[] = "eE";
735 /* Chars that mean this number is a floating point constant. */
739 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
741 /* Prefix characters that indicate the start of an immediate
743 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
745 /* Separator character handling. */
747 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
750 skip_past_char (char ** str
, char c
)
760 #define skip_past_comma(str) skip_past_char (str, ',')
762 /* Arithmetic expressions (possibly involving symbols). */
764 /* Return TRUE if anything in the expression is a bignum. */
767 walk_no_bignums (symbolS
* sp
)
769 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
772 if (symbol_get_value_expression (sp
)->X_add_symbol
)
774 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
775 || (symbol_get_value_expression (sp
)->X_op_symbol
776 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
782 static int in_my_get_expression
= 0;
784 /* Third argument to my_get_expression. */
785 #define GE_NO_PREFIX 0
786 #define GE_IMM_PREFIX 1
787 #define GE_OPT_PREFIX 2
788 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
789 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
790 #define GE_OPT_PREFIX_BIG 3
793 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
798 /* In unified syntax, all prefixes are optional. */
800 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
805 case GE_NO_PREFIX
: break;
807 if (!is_immediate_prefix (**str
))
809 inst
.error
= _("immediate expression requires a # prefix");
815 case GE_OPT_PREFIX_BIG
:
816 if (is_immediate_prefix (**str
))
822 memset (ep
, 0, sizeof (expressionS
));
824 save_in
= input_line_pointer
;
825 input_line_pointer
= *str
;
826 in_my_get_expression
= 1;
827 seg
= expression (ep
);
828 in_my_get_expression
= 0;
830 if (ep
->X_op
== O_illegal
)
832 /* We found a bad expression in md_operand(). */
833 *str
= input_line_pointer
;
834 input_line_pointer
= save_in
;
835 if (inst
.error
== NULL
)
836 inst
.error
= _("bad expression");
841 if (seg
!= absolute_section
842 && seg
!= text_section
843 && seg
!= data_section
844 && seg
!= bss_section
845 && seg
!= undefined_section
)
847 inst
.error
= _("bad segment");
848 *str
= input_line_pointer
;
849 input_line_pointer
= save_in
;
854 /* Get rid of any bignums now, so that we don't generate an error for which
855 we can't establish a line number later on. Big numbers are never valid
856 in instructions, which is where this routine is always called. */
857 if (prefix_mode
!= GE_OPT_PREFIX_BIG
858 && (ep
->X_op
== O_big
860 && (walk_no_bignums (ep
->X_add_symbol
)
862 && walk_no_bignums (ep
->X_op_symbol
))))))
864 inst
.error
= _("invalid constant");
865 *str
= input_line_pointer
;
866 input_line_pointer
= save_in
;
870 *str
= input_line_pointer
;
871 input_line_pointer
= save_in
;
875 /* Turn a string in input_line_pointer into a floating point constant
876 of type TYPE, and store the appropriate bytes in *LITP. The number
877 of LITTLENUMS emitted is stored in *SIZEP. An error message is
878 returned, or NULL on OK.
880 Note that fp constants aren't represent in the normal way on the ARM.
881 In big endian mode, things are as expected. However, in little endian
882 mode fp constants are big-endian word-wise, and little-endian byte-wise
883 within the words. For example, (double) 1.1 in big endian mode is
884 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
885 the byte sequence 99 99 f1 3f 9a 99 99 99.
887 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
890 md_atof (int type
, char * litP
, int * sizeP
)
893 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
925 return _("Unrecognized or unsupported floating point constant");
928 t
= atof_ieee (input_line_pointer
, type
, words
);
930 input_line_pointer
= t
;
931 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
933 if (target_big_endian
)
935 for (i
= 0; i
< prec
; i
++)
937 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
938 litP
+= sizeof (LITTLENUM_TYPE
);
943 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
944 for (i
= prec
- 1; i
>= 0; i
--)
946 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
947 litP
+= sizeof (LITTLENUM_TYPE
);
950 /* For a 4 byte float the order of elements in `words' is 1 0.
951 For an 8 byte float the order is 1 0 3 2. */
952 for (i
= 0; i
< prec
; i
+= 2)
954 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
955 sizeof (LITTLENUM_TYPE
));
956 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
957 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
958 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
965 /* We handle all bad expressions here, so that we can report the faulty
966 instruction in the error message. */
968 md_operand (expressionS
* expr
)
970 if (in_my_get_expression
)
971 expr
->X_op
= O_illegal
;
974 /* Immediate values. */
976 /* Generic immediate-value read function for use in directives.
977 Accepts anything that 'expression' can fold to a constant.
978 *val receives the number. */
981 immediate_for_directive (int *val
)
984 exp
.X_op
= O_illegal
;
986 if (is_immediate_prefix (*input_line_pointer
))
988 input_line_pointer
++;
992 if (exp
.X_op
!= O_constant
)
994 as_bad (_("expected #constant"));
995 ignore_rest_of_line ();
998 *val
= exp
.X_add_number
;
1003 /* Register parsing. */
1005 /* Generic register parser. CCP points to what should be the
1006 beginning of a register name. If it is indeed a valid register
1007 name, advance CCP over it and return the reg_entry structure;
1008 otherwise return NULL. Does not issue diagnostics. */
1010 static struct reg_entry
*
1011 arm_reg_parse_multi (char **ccp
)
1015 struct reg_entry
*reg
;
1017 #ifdef REGISTER_PREFIX
1018 if (*start
!= REGISTER_PREFIX
)
1022 #ifdef OPTIONAL_REGISTER_PREFIX
1023 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1028 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1033 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1035 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1045 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1046 enum arm_reg_type type
)
1048 /* Alternative syntaxes are accepted for a few register classes. */
1055 /* Generic coprocessor register names are allowed for these. */
1056 if (reg
&& reg
->type
== REG_TYPE_CN
)
1061 /* For backward compatibility, a bare number is valid here. */
1063 unsigned long processor
= strtoul (start
, ccp
, 10);
1064 if (*ccp
!= start
&& processor
<= 15)
1068 case REG_TYPE_MMXWC
:
1069 /* WC includes WCG. ??? I'm not sure this is true for all
1070 instructions that take WC registers. */
1071 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1082 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1083 return value is the register number or FAIL. */
1086 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1089 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1092 /* Do not allow a scalar (reg+index) to parse as a register. */
1093 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1096 if (reg
&& reg
->type
== type
)
1099 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1106 /* Parse a Neon type specifier. *STR should point at the leading '.'
1107 character. Does no verification at this stage that the type fits the opcode
1114 Can all be legally parsed by this function.
1116 Fills in neon_type struct pointer with parsed information, and updates STR
1117 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1118 type, FAIL if not. */
1121 parse_neon_type (struct neon_type
*type
, char **str
)
1128 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1130 enum neon_el_type thistype
= NT_untyped
;
1131 unsigned thissize
= -1u;
1138 /* Just a size without an explicit type. */
1142 switch (TOLOWER (*ptr
))
1144 case 'i': thistype
= NT_integer
; break;
1145 case 'f': thistype
= NT_float
; break;
1146 case 'p': thistype
= NT_poly
; break;
1147 case 's': thistype
= NT_signed
; break;
1148 case 'u': thistype
= NT_unsigned
; break;
1150 thistype
= NT_float
;
1155 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1161 /* .f is an abbreviation for .f32. */
1162 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1167 thissize
= strtoul (ptr
, &ptr
, 10);
1169 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1172 as_bad (_("bad size %d in type specifier"), thissize
);
1180 type
->el
[type
->elems
].type
= thistype
;
1181 type
->el
[type
->elems
].size
= thissize
;
1186 /* Empty/missing type is not a successful parse. */
1187 if (type
->elems
== 0)
1195 /* Errors may be set multiple times during parsing or bit encoding
1196 (particularly in the Neon bits), but usually the earliest error which is set
1197 will be the most meaningful. Avoid overwriting it with later (cascading)
1198 errors by calling this function. */
1201 first_error (const char *err
)
1207 /* Parse a single type, e.g. ".s32", leading period included. */
1209 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1212 struct neon_type optype
;
1216 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1218 if (optype
.elems
== 1)
1219 *vectype
= optype
.el
[0];
1222 first_error (_("only one type should be specified for operand"));
1228 first_error (_("vector type expected"));
1240 /* Special meanings for indices (which have a range of 0-7), which will fit into
1243 #define NEON_ALL_LANES 15
1244 #define NEON_INTERLEAVE_LANES 14
1246 /* Parse either a register or a scalar, with an optional type. Return the
1247 register number, and optionally fill in the actual type of the register
1248 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1249 type/index information in *TYPEINFO. */
1252 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1253 enum arm_reg_type
*rtype
,
1254 struct neon_typed_alias
*typeinfo
)
1257 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1258 struct neon_typed_alias atype
;
1259 struct neon_type_el parsetype
;
1263 atype
.eltype
.type
= NT_invtype
;
1264 atype
.eltype
.size
= -1;
1266 /* Try alternate syntax for some types of register. Note these are mutually
1267 exclusive with the Neon syntax extensions. */
1270 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1278 /* Undo polymorphism when a set of register types may be accepted. */
1279 if ((type
== REG_TYPE_NDQ
1280 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1281 || (type
== REG_TYPE_VFSD
1282 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1283 || (type
== REG_TYPE_NSDQ
1284 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1285 || reg
->type
== REG_TYPE_NQ
))
1286 || (type
== REG_TYPE_MMXWC
1287 && (reg
->type
== REG_TYPE_MMXWCG
)))
1290 if (type
!= reg
->type
)
1296 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1298 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1300 first_error (_("can't redefine type for operand"));
1303 atype
.defined
|= NTA_HASTYPE
;
1304 atype
.eltype
= parsetype
;
1307 if (skip_past_char (&str
, '[') == SUCCESS
)
1309 if (type
!= REG_TYPE_VFD
)
1311 first_error (_("only D registers may be indexed"));
1315 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1317 first_error (_("can't change index for operand"));
1321 atype
.defined
|= NTA_HASINDEX
;
1323 if (skip_past_char (&str
, ']') == SUCCESS
)
1324 atype
.index
= NEON_ALL_LANES
;
1329 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1331 if (exp
.X_op
!= O_constant
)
1333 first_error (_("constant expression required"));
1337 if (skip_past_char (&str
, ']') == FAIL
)
1340 atype
.index
= exp
.X_add_number
;
1355 /* Like arm_reg_parse, but allow allow the following extra features:
1356 - If RTYPE is non-zero, return the (possibly restricted) type of the
1357 register (e.g. Neon double or quad reg when either has been requested).
1358 - If this is a Neon vector type with additional type information, fill
1359 in the struct pointed to by VECTYPE (if non-NULL).
1360 This function will fault on encountering a scalar. */
1363 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1366 struct neon_typed_alias atype
;
1368 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1373 /* Do not allow a scalar (reg+index) to parse as a register. */
1374 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1376 first_error (_("register operand expected, but got scalar"));
1381 *vectype
= atype
.eltype
;
1388 #define NEON_SCALAR_REG(X) ((X) >> 4)
1389 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1391 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1392 have enough information to be able to do a good job bounds-checking. So, we
1393 just do easy checks here, and do further checks later. */
1396 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1400 struct neon_typed_alias atype
;
1402 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1404 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1407 if (atype
.index
== NEON_ALL_LANES
)
1409 first_error (_("scalar must have an index"));
1412 else if (atype
.index
>= 64 / elsize
)
1414 first_error (_("scalar index out of range"));
1419 *type
= atype
.eltype
;
1423 return reg
* 16 + atype
.index
;
1426 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1428 parse_reg_list (char ** strp
)
1430 char * str
= * strp
;
1434 /* We come back here if we get ranges concatenated by '+' or '|'. */
1449 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1451 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1461 first_error (_("bad range in register list"));
1465 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1467 if (range
& (1 << i
))
1469 (_("Warning: duplicated register (r%d) in register list"),
1477 if (range
& (1 << reg
))
1478 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1480 else if (reg
<= cur_reg
)
1481 as_tsktsk (_("Warning: register range not in ascending order"));
1486 while (skip_past_comma (&str
) != FAIL
1487 || (in_range
= 1, *str
++ == '-'));
1492 first_error (_("missing `}'"));
1500 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1503 if (expr
.X_op
== O_constant
)
1505 if (expr
.X_add_number
1506 != (expr
.X_add_number
& 0x0000ffff))
1508 inst
.error
= _("invalid register mask");
1512 if ((range
& expr
.X_add_number
) != 0)
1514 int regno
= range
& expr
.X_add_number
;
1517 regno
= (1 << regno
) - 1;
1519 (_("Warning: duplicated register (r%d) in register list"),
1523 range
|= expr
.X_add_number
;
1527 if (inst
.reloc
.type
!= 0)
1529 inst
.error
= _("expression too complex");
1533 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1534 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1535 inst
.reloc
.pc_rel
= 0;
1539 if (*str
== '|' || *str
== '+')
1545 while (another_range
);
1551 /* Types of registers in a list. */
1560 /* Parse a VFP register list. If the string is invalid return FAIL.
1561 Otherwise return the number of registers, and set PBASE to the first
1562 register. Parses registers of type ETYPE.
1563 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1564 - Q registers can be used to specify pairs of D registers
1565 - { } can be omitted from around a singleton register list
1566 FIXME: This is not implemented, as it would require backtracking in
1569 This could be done (the meaning isn't really ambiguous), but doesn't
1570 fit in well with the current parsing framework.
1571 - 32 D registers may be used (also true for VFPv3).
1572 FIXME: Types are ignored in these register lists, which is probably a
1576 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1581 enum arm_reg_type regtype
= 0;
1585 unsigned long mask
= 0;
1590 inst
.error
= _("expecting {");
1599 regtype
= REG_TYPE_VFS
;
1604 regtype
= REG_TYPE_VFD
;
1607 case REGLIST_NEON_D
:
1608 regtype
= REG_TYPE_NDQ
;
1612 if (etype
!= REGLIST_VFP_S
)
1614 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1615 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1619 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1622 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1629 base_reg
= max_regs
;
1633 int setmask
= 1, addregs
= 1;
1635 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1637 if (new_base
== FAIL
)
1639 first_error (_(reg_expected_msgs
[regtype
]));
1643 if (new_base
>= max_regs
)
1645 first_error (_("register out of range in list"));
1649 /* Note: a value of 2 * n is returned for the register Q<n>. */
1650 if (regtype
== REG_TYPE_NQ
)
1656 if (new_base
< base_reg
)
1657 base_reg
= new_base
;
1659 if (mask
& (setmask
<< new_base
))
1661 first_error (_("invalid register list"));
1665 if ((mask
>> new_base
) != 0 && ! warned
)
1667 as_tsktsk (_("register list not in ascending order"));
1671 mask
|= setmask
<< new_base
;
1674 if (*str
== '-') /* We have the start of a range expression */
1680 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1683 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1687 if (high_range
>= max_regs
)
1689 first_error (_("register out of range in list"));
1693 if (regtype
== REG_TYPE_NQ
)
1694 high_range
= high_range
+ 1;
1696 if (high_range
<= new_base
)
1698 inst
.error
= _("register range not in ascending order");
1702 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1704 if (mask
& (setmask
<< new_base
))
1706 inst
.error
= _("invalid register list");
1710 mask
|= setmask
<< new_base
;
1715 while (skip_past_comma (&str
) != FAIL
);
1719 /* Sanity check -- should have raised a parse error above. */
1720 if (count
== 0 || count
> max_regs
)
1725 /* Final test -- the registers must be consecutive. */
1727 for (i
= 0; i
< count
; i
++)
1729 if ((mask
& (1u << i
)) == 0)
1731 inst
.error
= _("non-contiguous register range");
1741 /* True if two alias types are the same. */
1744 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1752 if (a
->defined
!= b
->defined
)
1755 if ((a
->defined
& NTA_HASTYPE
) != 0
1756 && (a
->eltype
.type
!= b
->eltype
.type
1757 || a
->eltype
.size
!= b
->eltype
.size
))
1760 if ((a
->defined
& NTA_HASINDEX
) != 0
1761 && (a
->index
!= b
->index
))
1767 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1768 The base register is put in *PBASE.
1769 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1771 The register stride (minus one) is put in bit 4 of the return value.
1772 Bits [6:5] encode the list length (minus one).
1773 The type of the list elements is put in *ELTYPE, if non-NULL. */
1775 #define NEON_LANE(X) ((X) & 0xf)
1776 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1777 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1780 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1781 struct neon_type_el
*eltype
)
1788 int leading_brace
= 0;
1789 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1791 const char *const incr_error
= "register stride must be 1 or 2";
1792 const char *const type_error
= "mismatched element/structure types in list";
1793 struct neon_typed_alias firsttype
;
1795 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1800 struct neon_typed_alias atype
;
1801 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1805 first_error (_(reg_expected_msgs
[rtype
]));
1812 if (rtype
== REG_TYPE_NQ
)
1819 else if (reg_incr
== -1)
1821 reg_incr
= getreg
- base_reg
;
1822 if (reg_incr
< 1 || reg_incr
> 2)
1824 first_error (_(incr_error
));
1828 else if (getreg
!= base_reg
+ reg_incr
* count
)
1830 first_error (_(incr_error
));
1834 if (!neon_alias_types_same (&atype
, &firsttype
))
1836 first_error (_(type_error
));
1840 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1844 struct neon_typed_alias htype
;
1845 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1847 lane
= NEON_INTERLEAVE_LANES
;
1848 else if (lane
!= NEON_INTERLEAVE_LANES
)
1850 first_error (_(type_error
));
1855 else if (reg_incr
!= 1)
1857 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1861 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1864 first_error (_(reg_expected_msgs
[rtype
]));
1867 if (!neon_alias_types_same (&htype
, &firsttype
))
1869 first_error (_(type_error
));
1872 count
+= hireg
+ dregs
- getreg
;
1876 /* If we're using Q registers, we can't use [] or [n] syntax. */
1877 if (rtype
== REG_TYPE_NQ
)
1883 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1887 else if (lane
!= atype
.index
)
1889 first_error (_(type_error
));
1893 else if (lane
== -1)
1894 lane
= NEON_INTERLEAVE_LANES
;
1895 else if (lane
!= NEON_INTERLEAVE_LANES
)
1897 first_error (_(type_error
));
1902 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1904 /* No lane set by [x]. We must be interleaving structures. */
1906 lane
= NEON_INTERLEAVE_LANES
;
1909 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1910 || (count
> 1 && reg_incr
== -1))
1912 first_error (_("error parsing element/structure list"));
1916 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1918 first_error (_("expected }"));
1926 *eltype
= firsttype
.eltype
;
1931 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1934 /* Parse an explicit relocation suffix on an expression. This is
1935 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1936 arm_reloc_hsh contains no entries, so this function can only
1937 succeed if there is no () after the word. Returns -1 on error,
1938 BFD_RELOC_UNUSED if there wasn't any suffix. */
1940 parse_reloc (char **str
)
1942 struct reloc_entry
*r
;
1946 return BFD_RELOC_UNUSED
;
1951 while (*q
&& *q
!= ')' && *q
!= ',')
1956 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1963 /* Directives: register aliases. */
1965 static struct reg_entry
*
1966 insert_reg_alias (char *str
, int number
, int type
)
1968 struct reg_entry
*new;
1971 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1974 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1976 /* Only warn about a redefinition if it's not defined as the
1978 else if (new->number
!= number
|| new->type
!= type
)
1979 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1984 name
= xstrdup (str
);
1985 new = xmalloc (sizeof (struct reg_entry
));
1988 new->number
= number
;
1990 new->builtin
= FALSE
;
1993 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2000 insert_neon_reg_alias (char *str
, int number
, int type
,
2001 struct neon_typed_alias
*atype
)
2003 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2007 first_error (_("attempt to redefine typed alias"));
2013 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2014 *reg
->neon
= *atype
;
2018 /* Look for the .req directive. This is of the form:
2020 new_register_name .req existing_register_name
2022 If we find one, or if it looks sufficiently like one that we want to
2023 handle any error here, return TRUE. Otherwise return FALSE. */
2026 create_register_alias (char * newname
, char *p
)
2028 struct reg_entry
*old
;
2029 char *oldname
, *nbuf
;
2032 /* The input scrubber ensures that whitespace after the mnemonic is
2033 collapsed to single spaces. */
2035 if (strncmp (oldname
, " .req ", 6) != 0)
2039 if (*oldname
== '\0')
2042 old
= hash_find (arm_reg_hsh
, oldname
);
2045 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2049 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2050 the desired alias name, and p points to its end. If not, then
2051 the desired alias name is in the global original_case_string. */
2052 #ifdef TC_CASE_SENSITIVE
2055 newname
= original_case_string
;
2056 nlen
= strlen (newname
);
2059 nbuf
= alloca (nlen
+ 1);
2060 memcpy (nbuf
, newname
, nlen
);
2063 /* Create aliases under the new name as stated; an all-lowercase
2064 version of the new name; and an all-uppercase version of the new
2066 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2068 for (p
= nbuf
; *p
; p
++)
2071 if (strncmp (nbuf
, newname
, nlen
))
2073 /* If this attempt to create an additional alias fails, do not bother
2074 trying to create the all-lower case alias. We will fail and issue
2075 a second, duplicate error message. This situation arises when the
2076 programmer does something like:
2079 The second .req creates the "Foo" alias but then fails to create
2080 the artificial FOO alias because it has already been created by the
2082 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2086 for (p
= nbuf
; *p
; p
++)
2089 if (strncmp (nbuf
, newname
, nlen
))
2090 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2096 /* Create a Neon typed/indexed register alias using directives, e.g.:
2101 These typed registers can be used instead of the types specified after the
2102 Neon mnemonic, so long as all operands given have types. Types can also be
2103 specified directly, e.g.:
2104 vadd d0.s32, d1.s32, d2.s32 */
2107 create_neon_reg_alias (char *newname
, char *p
)
2109 enum arm_reg_type basetype
;
2110 struct reg_entry
*basereg
;
2111 struct reg_entry mybasereg
;
2112 struct neon_type ntype
;
2113 struct neon_typed_alias typeinfo
;
2114 char *namebuf
, *nameend
;
2117 typeinfo
.defined
= 0;
2118 typeinfo
.eltype
.type
= NT_invtype
;
2119 typeinfo
.eltype
.size
= -1;
2120 typeinfo
.index
= -1;
2124 if (strncmp (p
, " .dn ", 5) == 0)
2125 basetype
= REG_TYPE_VFD
;
2126 else if (strncmp (p
, " .qn ", 5) == 0)
2127 basetype
= REG_TYPE_NQ
;
2136 basereg
= arm_reg_parse_multi (&p
);
2138 if (basereg
&& basereg
->type
!= basetype
)
2140 as_bad (_("bad type for register"));
2144 if (basereg
== NULL
)
2147 /* Try parsing as an integer. */
2148 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2149 if (exp
.X_op
!= O_constant
)
2151 as_bad (_("expression must be constant"));
2154 basereg
= &mybasereg
;
2155 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2161 typeinfo
= *basereg
->neon
;
2163 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2165 /* We got a type. */
2166 if (typeinfo
.defined
& NTA_HASTYPE
)
2168 as_bad (_("can't redefine the type of a register alias"));
2172 typeinfo
.defined
|= NTA_HASTYPE
;
2173 if (ntype
.elems
!= 1)
2175 as_bad (_("you must specify a single type only"));
2178 typeinfo
.eltype
= ntype
.el
[0];
2181 if (skip_past_char (&p
, '[') == SUCCESS
)
2184 /* We got a scalar index. */
2186 if (typeinfo
.defined
& NTA_HASINDEX
)
2188 as_bad (_("can't redefine the index of a scalar alias"));
2192 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2194 if (exp
.X_op
!= O_constant
)
2196 as_bad (_("scalar index must be constant"));
2200 typeinfo
.defined
|= NTA_HASINDEX
;
2201 typeinfo
.index
= exp
.X_add_number
;
2203 if (skip_past_char (&p
, ']') == FAIL
)
2205 as_bad (_("expecting ]"));
2210 namelen
= nameend
- newname
;
2211 namebuf
= alloca (namelen
+ 1);
2212 strncpy (namebuf
, newname
, namelen
);
2213 namebuf
[namelen
] = '\0';
2215 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2216 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2218 /* Insert name in all uppercase. */
2219 for (p
= namebuf
; *p
; p
++)
2222 if (strncmp (namebuf
, newname
, namelen
))
2223 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2224 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2226 /* Insert name in all lowercase. */
2227 for (p
= namebuf
; *p
; p
++)
2230 if (strncmp (namebuf
, newname
, namelen
))
2231 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2232 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2237 /* Should never be called, as .req goes between the alias and the
2238 register name, not at the beginning of the line. */
2240 s_req (int a ATTRIBUTE_UNUSED
)
2242 as_bad (_("invalid syntax for .req directive"));
2246 s_dn (int a ATTRIBUTE_UNUSED
)
2248 as_bad (_("invalid syntax for .dn directive"));
2252 s_qn (int a ATTRIBUTE_UNUSED
)
2254 as_bad (_("invalid syntax for .qn directive"));
2257 /* The .unreq directive deletes an alias which was previously defined
2258 by .req. For example:
2264 s_unreq (int a ATTRIBUTE_UNUSED
)
2269 name
= input_line_pointer
;
2271 while (*input_line_pointer
!= 0
2272 && *input_line_pointer
!= ' '
2273 && *input_line_pointer
!= '\n')
2274 ++input_line_pointer
;
2276 saved_char
= *input_line_pointer
;
2277 *input_line_pointer
= 0;
2280 as_bad (_("invalid syntax for .unreq directive"));
2283 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2286 as_bad (_("unknown register alias '%s'"), name
);
2287 else if (reg
->builtin
)
2288 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2295 hash_delete (arm_reg_hsh
, name
, FALSE
);
2296 free ((char *) reg
->name
);
2301 /* Also locate the all upper case and all lower case versions.
2302 Do not complain if we cannot find one or the other as it
2303 was probably deleted above. */
2305 nbuf
= strdup (name
);
2306 for (p
= nbuf
; *p
; p
++)
2308 reg
= hash_find (arm_reg_hsh
, nbuf
);
2311 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2312 free ((char *) reg
->name
);
2318 for (p
= nbuf
; *p
; p
++)
2320 reg
= hash_find (arm_reg_hsh
, nbuf
);
2323 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2324 free ((char *) reg
->name
);
2334 *input_line_pointer
= saved_char
;
2335 demand_empty_rest_of_line ();
2338 /* Directives: Instruction set selection. */
2341 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2342 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2343 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2344 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2346 static enum mstate mapstate
= MAP_UNDEFINED
;
2349 mapping_state (enum mstate state
)
2352 const char * symname
;
2355 if (mapstate
== state
)
2356 /* The mapping symbol has already been emitted.
2357 There is nothing else to do. */
2366 type
= BSF_NO_FLAGS
;
2370 type
= BSF_NO_FLAGS
;
2374 type
= BSF_NO_FLAGS
;
2382 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2384 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2385 symbol_table_insert (symbolP
);
2386 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2391 THUMB_SET_FUNC (symbolP
, 0);
2392 ARM_SET_THUMB (symbolP
, 0);
2393 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2397 THUMB_SET_FUNC (symbolP
, 1);
2398 ARM_SET_THUMB (symbolP
, 1);
2399 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2408 #define mapping_state(x) /* nothing */
2411 /* Find the real, Thumb encoded start of a Thumb function. */
2414 find_real_start (symbolS
* symbolP
)
2417 const char * name
= S_GET_NAME (symbolP
);
2418 symbolS
* new_target
;
2420 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2421 #define STUB_NAME ".real_start_of"
2426 /* The compiler may generate BL instructions to local labels because
2427 it needs to perform a branch to a far away location. These labels
2428 do not have a corresponding ".real_start_of" label. We check
2429 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2430 the ".real_start_of" convention for nonlocal branches. */
2431 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2434 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2435 new_target
= symbol_find (real_start
);
2437 if (new_target
== NULL
)
2439 as_warn (_("Failed to find real start of function: %s\n"), name
);
2440 new_target
= symbolP
;
2447 opcode_select (int width
)
2454 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2455 as_bad (_("selected processor does not support THUMB opcodes"));
2458 /* No need to force the alignment, since we will have been
2459 coming from ARM mode, which is word-aligned. */
2460 record_alignment (now_seg
, 1);
2462 mapping_state (MAP_THUMB
);
2468 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2469 as_bad (_("selected processor does not support ARM opcodes"));
2474 frag_align (2, 0, 0);
2476 record_alignment (now_seg
, 1);
2478 mapping_state (MAP_ARM
);
2482 as_bad (_("invalid instruction size selected (%d)"), width
);
2487 s_arm (int ignore ATTRIBUTE_UNUSED
)
2490 demand_empty_rest_of_line ();
2494 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2497 demand_empty_rest_of_line ();
2501 s_code (int unused ATTRIBUTE_UNUSED
)
2505 temp
= get_absolute_expression ();
2510 opcode_select (temp
);
2514 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2519 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2521 /* If we are not already in thumb mode go into it, EVEN if
2522 the target processor does not support thumb instructions.
2523 This is used by gcc/config/arm/lib1funcs.asm for example
2524 to compile interworking support functions even if the
2525 target processor should not support interworking. */
2529 record_alignment (now_seg
, 1);
2532 demand_empty_rest_of_line ();
2536 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2540 /* The following label is the name/address of the start of a Thumb function.
2541 We need to know this for the interworking support. */
2542 label_is_thumb_function_name
= TRUE
;
2545 /* Perform a .set directive, but also mark the alias as
2546 being a thumb function. */
2549 s_thumb_set (int equiv
)
2551 /* XXX the following is a duplicate of the code for s_set() in read.c
2552 We cannot just call that code as we need to get at the symbol that
2559 /* Especial apologies for the random logic:
2560 This just grew, and could be parsed much more simply!
2562 name
= input_line_pointer
;
2563 delim
= get_symbol_end ();
2564 end_name
= input_line_pointer
;
2567 if (*input_line_pointer
!= ',')
2570 as_bad (_("expected comma after name \"%s\""), name
);
2572 ignore_rest_of_line ();
2576 input_line_pointer
++;
2579 if (name
[0] == '.' && name
[1] == '\0')
2581 /* XXX - this should not happen to .thumb_set. */
2585 if ((symbolP
= symbol_find (name
)) == NULL
2586 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2589 /* When doing symbol listings, play games with dummy fragments living
2590 outside the normal fragment chain to record the file and line info
2592 if (listing
& LISTING_SYMBOLS
)
2594 extern struct list_info_struct
* listing_tail
;
2595 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2597 memset (dummy_frag
, 0, sizeof (fragS
));
2598 dummy_frag
->fr_type
= rs_fill
;
2599 dummy_frag
->line
= listing_tail
;
2600 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2601 dummy_frag
->fr_symbol
= symbolP
;
2605 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2608 /* "set" symbols are local unless otherwise specified. */
2609 SF_SET_LOCAL (symbolP
);
2610 #endif /* OBJ_COFF */
2611 } /* Make a new symbol. */
2613 symbol_table_insert (symbolP
);
2618 && S_IS_DEFINED (symbolP
)
2619 && S_GET_SEGMENT (symbolP
) != reg_section
)
2620 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2622 pseudo_set (symbolP
);
2624 demand_empty_rest_of_line ();
2626 /* XXX Now we come to the Thumb specific bit of code. */
2628 THUMB_SET_FUNC (symbolP
, 1);
2629 ARM_SET_THUMB (symbolP
, 1);
2630 #if defined OBJ_ELF || defined OBJ_COFF
2631 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2635 /* Directives: Mode selection. */
2637 /* .syntax [unified|divided] - choose the new unified syntax
2638 (same for Arm and Thumb encoding, modulo slight differences in what
2639 can be represented) or the old divergent syntax for each mode. */
2641 s_syntax (int unused ATTRIBUTE_UNUSED
)
2645 name
= input_line_pointer
;
2646 delim
= get_symbol_end ();
2648 if (!strcasecmp (name
, "unified"))
2649 unified_syntax
= TRUE
;
2650 else if (!strcasecmp (name
, "divided"))
2651 unified_syntax
= FALSE
;
2654 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2657 *input_line_pointer
= delim
;
2658 demand_empty_rest_of_line ();
2661 /* Directives: sectioning and alignment. */
2663 /* Same as s_align_ptwo but align 0 => align 2. */
2666 s_align (int unused ATTRIBUTE_UNUSED
)
2671 long max_alignment
= 15;
2673 temp
= get_absolute_expression ();
2674 if (temp
> max_alignment
)
2675 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2678 as_bad (_("alignment negative. 0 assumed."));
2682 if (*input_line_pointer
== ',')
2684 input_line_pointer
++;
2685 temp_fill
= get_absolute_expression ();
2697 /* Only make a frag if we HAVE to. */
2698 if (temp
&& !need_pass_2
)
2700 if (!fill_p
&& subseg_text_p (now_seg
))
2701 frag_align_code (temp
, 0);
2703 frag_align (temp
, (int) temp_fill
, 0);
2705 demand_empty_rest_of_line ();
2707 record_alignment (now_seg
, temp
);
2711 s_bss (int ignore ATTRIBUTE_UNUSED
)
2713 /* We don't support putting frags in the BSS segment, we fake it by
2714 marking in_bss, then looking at s_skip for clues. */
2715 subseg_set (bss_section
, 0);
2716 demand_empty_rest_of_line ();
2717 mapping_state (MAP_DATA
);
2721 s_even (int ignore ATTRIBUTE_UNUSED
)
2723 /* Never make frag if expect extra pass. */
2725 frag_align (1, 0, 0);
2727 record_alignment (now_seg
, 1);
2729 demand_empty_rest_of_line ();
2732 /* Directives: Literal pools. */
2734 static literal_pool
*
2735 find_literal_pool (void)
2737 literal_pool
* pool
;
2739 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2741 if (pool
->section
== now_seg
2742 && pool
->sub_section
== now_subseg
)
2749 static literal_pool
*
2750 find_or_make_literal_pool (void)
2752 /* Next literal pool ID number. */
2753 static unsigned int latest_pool_num
= 1;
2754 literal_pool
* pool
;
2756 pool
= find_literal_pool ();
2760 /* Create a new pool. */
2761 pool
= xmalloc (sizeof (* pool
));
2765 pool
->next_free_entry
= 0;
2766 pool
->section
= now_seg
;
2767 pool
->sub_section
= now_subseg
;
2768 pool
->next
= list_of_pools
;
2769 pool
->symbol
= NULL
;
2771 /* Add it to the list. */
2772 list_of_pools
= pool
;
2775 /* New pools, and emptied pools, will have a NULL symbol. */
2776 if (pool
->symbol
== NULL
)
2778 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2779 (valueT
) 0, &zero_address_frag
);
2780 pool
->id
= latest_pool_num
++;
2787 /* Add the literal in the global 'inst'
2788 structure to the relevant literal pool. */
2791 add_to_lit_pool (void)
2793 literal_pool
* pool
;
2796 pool
= find_or_make_literal_pool ();
2798 /* Check if this literal value is already in the pool. */
2799 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2801 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2802 && (inst
.reloc
.exp
.X_op
== O_constant
)
2803 && (pool
->literals
[entry
].X_add_number
2804 == inst
.reloc
.exp
.X_add_number
)
2805 && (pool
->literals
[entry
].X_unsigned
2806 == inst
.reloc
.exp
.X_unsigned
))
2809 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2810 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2811 && (pool
->literals
[entry
].X_add_number
2812 == inst
.reloc
.exp
.X_add_number
)
2813 && (pool
->literals
[entry
].X_add_symbol
2814 == inst
.reloc
.exp
.X_add_symbol
)
2815 && (pool
->literals
[entry
].X_op_symbol
2816 == inst
.reloc
.exp
.X_op_symbol
))
2820 /* Do we need to create a new entry? */
2821 if (entry
== pool
->next_free_entry
)
2823 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2825 inst
.error
= _("literal pool overflow");
2829 pool
->literals
[entry
] = inst
.reloc
.exp
;
2830 pool
->next_free_entry
+= 1;
2833 inst
.reloc
.exp
.X_op
= O_symbol
;
2834 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2835 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2840 /* Can't use symbol_new here, so have to create a symbol and then at
2841 a later date assign it a value. Thats what these functions do. */
2844 symbol_locate (symbolS
* symbolP
,
2845 const char * name
, /* It is copied, the caller can modify. */
2846 segT segment
, /* Segment identifier (SEG_<something>). */
2847 valueT valu
, /* Symbol value. */
2848 fragS
* frag
) /* Associated fragment. */
2850 unsigned int name_length
;
2851 char * preserved_copy_of_name
;
2853 name_length
= strlen (name
) + 1; /* +1 for \0. */
2854 obstack_grow (¬es
, name
, name_length
);
2855 preserved_copy_of_name
= obstack_finish (¬es
);
2857 #ifdef tc_canonicalize_symbol_name
2858 preserved_copy_of_name
=
2859 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2862 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2864 S_SET_SEGMENT (symbolP
, segment
);
2865 S_SET_VALUE (symbolP
, valu
);
2866 symbol_clear_list_pointers (symbolP
);
2868 symbol_set_frag (symbolP
, frag
);
2870 /* Link to end of symbol chain. */
2872 extern int symbol_table_frozen
;
2874 if (symbol_table_frozen
)
2878 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2880 obj_symbol_new_hook (symbolP
);
2882 #ifdef tc_symbol_new_hook
2883 tc_symbol_new_hook (symbolP
);
2887 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2888 #endif /* DEBUG_SYMS */
2893 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2896 literal_pool
* pool
;
2899 pool
= find_literal_pool ();
2901 || pool
->symbol
== NULL
2902 || pool
->next_free_entry
== 0)
2905 mapping_state (MAP_DATA
);
2907 /* Align pool as you have word accesses.
2908 Only make a frag if we have to. */
2910 frag_align (2, 0, 0);
2912 record_alignment (now_seg
, 2);
2914 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2916 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2917 (valueT
) frag_now_fix (), frag_now
);
2918 symbol_table_insert (pool
->symbol
);
2920 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2922 #if defined OBJ_COFF || defined OBJ_ELF
2923 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2926 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2927 /* First output the expression in the instruction to the pool. */
2928 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2930 /* Mark the pool as empty. */
2931 pool
->next_free_entry
= 0;
2932 pool
->symbol
= NULL
;
2936 /* Forward declarations for functions below, in the MD interface
2938 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2939 static valueT
create_unwind_entry (int);
2940 static void start_unwind_section (const segT
, int);
2941 static void add_unwind_opcode (valueT
, int);
2942 static void flush_pending_unwind (void);
2944 /* Directives: Data. */
2947 s_arm_elf_cons (int nbytes
)
2951 #ifdef md_flush_pending_output
2952 md_flush_pending_output ();
2955 if (is_it_end_of_statement ())
2957 demand_empty_rest_of_line ();
2961 #ifdef md_cons_align
2962 md_cons_align (nbytes
);
2965 mapping_state (MAP_DATA
);
2969 char *base
= input_line_pointer
;
2973 if (exp
.X_op
!= O_symbol
)
2974 emit_expr (&exp
, (unsigned int) nbytes
);
2977 char *before_reloc
= input_line_pointer
;
2978 reloc
= parse_reloc (&input_line_pointer
);
2981 as_bad (_("unrecognized relocation suffix"));
2982 ignore_rest_of_line ();
2985 else if (reloc
== BFD_RELOC_UNUSED
)
2986 emit_expr (&exp
, (unsigned int) nbytes
);
2989 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2990 int size
= bfd_get_reloc_size (howto
);
2992 if (reloc
== BFD_RELOC_ARM_PLT32
)
2994 as_bad (_("(plt) is only valid on branch targets"));
2995 reloc
= BFD_RELOC_UNUSED
;
3000 as_bad (_("%s relocations do not fit in %d bytes"),
3001 howto
->name
, nbytes
);
3004 /* We've parsed an expression stopping at O_symbol.
3005 But there may be more expression left now that we
3006 have parsed the relocation marker. Parse it again.
3007 XXX Surely there is a cleaner way to do this. */
3008 char *p
= input_line_pointer
;
3010 char *save_buf
= alloca (input_line_pointer
- base
);
3011 memcpy (save_buf
, base
, input_line_pointer
- base
);
3012 memmove (base
+ (input_line_pointer
- before_reloc
),
3013 base
, before_reloc
- base
);
3015 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3017 memcpy (base
, save_buf
, p
- base
);
3019 offset
= nbytes
- size
;
3020 p
= frag_more ((int) nbytes
);
3021 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3022 size
, &exp
, 0, reloc
);
3027 while (*input_line_pointer
++ == ',');
3029 /* Put terminator back into stream. */
3030 input_line_pointer
--;
3031 demand_empty_rest_of_line ();
3035 /* Parse a .rel31 directive. */
3038 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3045 if (*input_line_pointer
== '1')
3046 highbit
= 0x80000000;
3047 else if (*input_line_pointer
!= '0')
3048 as_bad (_("expected 0 or 1"));
3050 input_line_pointer
++;
3051 if (*input_line_pointer
!= ',')
3052 as_bad (_("missing comma"));
3053 input_line_pointer
++;
3055 #ifdef md_flush_pending_output
3056 md_flush_pending_output ();
3059 #ifdef md_cons_align
3063 mapping_state (MAP_DATA
);
3068 md_number_to_chars (p
, highbit
, 4);
3069 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3070 BFD_RELOC_ARM_PREL31
);
3072 demand_empty_rest_of_line ();
3075 /* Directives: AEABI stack-unwind tables. */
3077 /* Parse an unwind_fnstart directive. Simply records the current location. */
3080 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3082 demand_empty_rest_of_line ();
3083 /* Mark the start of the function. */
3084 unwind
.proc_start
= expr_build_dot ();
3086 /* Reset the rest of the unwind info. */
3087 unwind
.opcode_count
= 0;
3088 unwind
.table_entry
= NULL
;
3089 unwind
.personality_routine
= NULL
;
3090 unwind
.personality_index
= -1;
3091 unwind
.frame_size
= 0;
3092 unwind
.fp_offset
= 0;
3095 unwind
.sp_restored
= 0;
3099 /* Parse a handlerdata directive. Creates the exception handling table entry
3100 for the function. */
3103 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3105 demand_empty_rest_of_line ();
3106 if (unwind
.table_entry
)
3107 as_bad (_("duplicate .handlerdata directive"));
3109 create_unwind_entry (1);
3112 /* Parse an unwind_fnend directive. Generates the index table entry. */
3115 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3121 demand_empty_rest_of_line ();
3123 /* Add eh table entry. */
3124 if (unwind
.table_entry
== NULL
)
3125 val
= create_unwind_entry (0);
3129 /* Add index table entry. This is two words. */
3130 start_unwind_section (unwind
.saved_seg
, 1);
3131 frag_align (2, 0, 0);
3132 record_alignment (now_seg
, 2);
3134 ptr
= frag_more (8);
3135 where
= frag_now_fix () - 8;
3137 /* Self relative offset of the function start. */
3138 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3139 BFD_RELOC_ARM_PREL31
);
3141 /* Indicate dependency on EHABI-defined personality routines to the
3142 linker, if it hasn't been done already. */
3143 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3144 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3146 static const char *const name
[] =
3148 "__aeabi_unwind_cpp_pr0",
3149 "__aeabi_unwind_cpp_pr1",
3150 "__aeabi_unwind_cpp_pr2"
3152 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3153 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3154 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3155 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3156 = marked_pr_dependency
;
3160 /* Inline exception table entry. */
3161 md_number_to_chars (ptr
+ 4, val
, 4);
3163 /* Self relative offset of the table entry. */
3164 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3165 BFD_RELOC_ARM_PREL31
);
3167 /* Restore the original section. */
3168 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3172 /* Parse an unwind_cantunwind directive. */
3175 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3177 demand_empty_rest_of_line ();
3178 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3179 as_bad (_("personality routine specified for cantunwind frame"));
3181 unwind
.personality_index
= -2;
3185 /* Parse a personalityindex directive. */
3188 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3192 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3193 as_bad (_("duplicate .personalityindex directive"));
3197 if (exp
.X_op
!= O_constant
3198 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3200 as_bad (_("bad personality routine number"));
3201 ignore_rest_of_line ();
3205 unwind
.personality_index
= exp
.X_add_number
;
3207 demand_empty_rest_of_line ();
3211 /* Parse a personality directive. */
3214 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3218 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3219 as_bad (_("duplicate .personality directive"));
3221 name
= input_line_pointer
;
3222 c
= get_symbol_end ();
3223 p
= input_line_pointer
;
3224 unwind
.personality_routine
= symbol_find_or_make (name
);
3226 demand_empty_rest_of_line ();
3230 /* Parse a directive saving core registers. */
3233 s_arm_unwind_save_core (void)
3239 range
= parse_reg_list (&input_line_pointer
);
3242 as_bad (_("expected register list"));
3243 ignore_rest_of_line ();
3247 demand_empty_rest_of_line ();
3249 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3250 into .unwind_save {..., sp...}. We aren't bothered about the value of
3251 ip because it is clobbered by calls. */
3252 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3253 && (range
& 0x3000) == 0x1000)
3255 unwind
.opcode_count
--;
3256 unwind
.sp_restored
= 0;
3257 range
= (range
| 0x2000) & ~0x1000;
3258 unwind
.pending_offset
= 0;
3264 /* See if we can use the short opcodes. These pop a block of up to 8
3265 registers starting with r4, plus maybe r14. */
3266 for (n
= 0; n
< 8; n
++)
3268 /* Break at the first non-saved register. */
3269 if ((range
& (1 << (n
+ 4))) == 0)
3272 /* See if there are any other bits set. */
3273 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3275 /* Use the long form. */
3276 op
= 0x8000 | ((range
>> 4) & 0xfff);
3277 add_unwind_opcode (op
, 2);
3281 /* Use the short form. */
3283 op
= 0xa8; /* Pop r14. */
3285 op
= 0xa0; /* Do not pop r14. */
3287 add_unwind_opcode (op
, 1);
3294 op
= 0xb100 | (range
& 0xf);
3295 add_unwind_opcode (op
, 2);
3298 /* Record the number of bytes pushed. */
3299 for (n
= 0; n
< 16; n
++)
3301 if (range
& (1 << n
))
3302 unwind
.frame_size
+= 4;
3307 /* Parse a directive saving FPA registers. */
3310 s_arm_unwind_save_fpa (int reg
)
3316 /* Get Number of registers to transfer. */
3317 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3320 exp
.X_op
= O_illegal
;
3322 if (exp
.X_op
!= O_constant
)
3324 as_bad (_("expected , <constant>"));
3325 ignore_rest_of_line ();
3329 num_regs
= exp
.X_add_number
;
3331 if (num_regs
< 1 || num_regs
> 4)
3333 as_bad (_("number of registers must be in the range [1:4]"));
3334 ignore_rest_of_line ();
3338 demand_empty_rest_of_line ();
3343 op
= 0xb4 | (num_regs
- 1);
3344 add_unwind_opcode (op
, 1);
3349 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3350 add_unwind_opcode (op
, 2);
3352 unwind
.frame_size
+= num_regs
* 12;
3356 /* Parse a directive saving VFP registers for ARMv6 and above. */
3359 s_arm_unwind_save_vfp_armv6 (void)
3364 int num_vfpv3_regs
= 0;
3365 int num_regs_below_16
;
3367 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3370 as_bad (_("expected register list"));
3371 ignore_rest_of_line ();
3375 demand_empty_rest_of_line ();
3377 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3378 than FSTMX/FLDMX-style ones). */
3380 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3382 num_vfpv3_regs
= count
;
3383 else if (start
+ count
> 16)
3384 num_vfpv3_regs
= start
+ count
- 16;
3386 if (num_vfpv3_regs
> 0)
3388 int start_offset
= start
> 16 ? start
- 16 : 0;
3389 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3390 add_unwind_opcode (op
, 2);
3393 /* Generate opcode for registers numbered in the range 0 .. 15. */
3394 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3395 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3396 if (num_regs_below_16
> 0)
3398 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3399 add_unwind_opcode (op
, 2);
3402 unwind
.frame_size
+= count
* 8;
3406 /* Parse a directive saving VFP registers for pre-ARMv6. */
3409 s_arm_unwind_save_vfp (void)
3415 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3418 as_bad (_("expected register list"));
3419 ignore_rest_of_line ();
3423 demand_empty_rest_of_line ();
3428 op
= 0xb8 | (count
- 1);
3429 add_unwind_opcode (op
, 1);
3434 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3435 add_unwind_opcode (op
, 2);
3437 unwind
.frame_size
+= count
* 8 + 4;
3441 /* Parse a directive saving iWMMXt data registers. */
3444 s_arm_unwind_save_mmxwr (void)
3452 if (*input_line_pointer
== '{')
3453 input_line_pointer
++;
3457 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3461 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3466 as_tsktsk (_("register list not in ascending order"));
3469 if (*input_line_pointer
== '-')
3471 input_line_pointer
++;
3472 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3475 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3478 else if (reg
>= hi_reg
)
3480 as_bad (_("bad register range"));
3483 for (; reg
< hi_reg
; reg
++)
3487 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3489 if (*input_line_pointer
== '}')
3490 input_line_pointer
++;
3492 demand_empty_rest_of_line ();
3494 /* Generate any deferred opcodes because we're going to be looking at
3496 flush_pending_unwind ();
3498 for (i
= 0; i
< 16; i
++)
3500 if (mask
& (1 << i
))
3501 unwind
.frame_size
+= 8;
3504 /* Attempt to combine with a previous opcode. We do this because gcc
3505 likes to output separate unwind directives for a single block of
3507 if (unwind
.opcode_count
> 0)
3509 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3510 if ((i
& 0xf8) == 0xc0)
3513 /* Only merge if the blocks are contiguous. */
3516 if ((mask
& 0xfe00) == (1 << 9))
3518 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3519 unwind
.opcode_count
--;
3522 else if (i
== 6 && unwind
.opcode_count
>= 2)
3524 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3528 op
= 0xffff << (reg
- 1);
3530 && ((mask
& op
) == (1u << (reg
- 1))))
3532 op
= (1 << (reg
+ i
+ 1)) - 1;
3533 op
&= ~((1 << reg
) - 1);
3535 unwind
.opcode_count
-= 2;
3542 /* We want to generate opcodes in the order the registers have been
3543 saved, ie. descending order. */
3544 for (reg
= 15; reg
>= -1; reg
--)
3546 /* Save registers in blocks. */
3548 || !(mask
& (1 << reg
)))
3550 /* We found an unsaved reg. Generate opcodes to save the
3557 op
= 0xc0 | (hi_reg
- 10);
3558 add_unwind_opcode (op
, 1);
3563 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3564 add_unwind_opcode (op
, 2);
3573 ignore_rest_of_line ();
3577 s_arm_unwind_save_mmxwcg (void)
3584 if (*input_line_pointer
== '{')
3585 input_line_pointer
++;
3589 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3593 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3599 as_tsktsk (_("register list not in ascending order"));
3602 if (*input_line_pointer
== '-')
3604 input_line_pointer
++;
3605 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3608 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3611 else if (reg
>= hi_reg
)
3613 as_bad (_("bad register range"));
3616 for (; reg
< hi_reg
; reg
++)
3620 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3622 if (*input_line_pointer
== '}')
3623 input_line_pointer
++;
3625 demand_empty_rest_of_line ();
3627 /* Generate any deferred opcodes because we're going to be looking at
3629 flush_pending_unwind ();
3631 for (reg
= 0; reg
< 16; reg
++)
3633 if (mask
& (1 << reg
))
3634 unwind
.frame_size
+= 4;
3637 add_unwind_opcode (op
, 2);
3640 ignore_rest_of_line ();
3644 /* Parse an unwind_save directive.
3645 If the argument is non-zero, this is a .vsave directive. */
3648 s_arm_unwind_save (int arch_v6
)
3651 struct reg_entry
*reg
;
3652 bfd_boolean had_brace
= FALSE
;
3654 /* Figure out what sort of save we have. */
3655 peek
= input_line_pointer
;
3663 reg
= arm_reg_parse_multi (&peek
);
3667 as_bad (_("register expected"));
3668 ignore_rest_of_line ();
3677 as_bad (_("FPA .unwind_save does not take a register list"));
3678 ignore_rest_of_line ();
3681 input_line_pointer
= peek
;
3682 s_arm_unwind_save_fpa (reg
->number
);
3685 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3688 s_arm_unwind_save_vfp_armv6 ();
3690 s_arm_unwind_save_vfp ();
3692 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3693 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3696 as_bad (_(".unwind_save does not support this kind of register"));
3697 ignore_rest_of_line ();
3702 /* Parse an unwind_movsp directive. */
3705 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3711 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3714 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3715 ignore_rest_of_line ();
3719 /* Optional constant. */
3720 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3722 if (immediate_for_directive (&offset
) == FAIL
)
3728 demand_empty_rest_of_line ();
3730 if (reg
== REG_SP
|| reg
== REG_PC
)
3732 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3736 if (unwind
.fp_reg
!= REG_SP
)
3737 as_bad (_("unexpected .unwind_movsp directive"));
3739 /* Generate opcode to restore the value. */
3741 add_unwind_opcode (op
, 1);
3743 /* Record the information for later. */
3744 unwind
.fp_reg
= reg
;
3745 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3746 unwind
.sp_restored
= 1;
3749 /* Parse an unwind_pad directive. */
3752 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3756 if (immediate_for_directive (&offset
) == FAIL
)
3761 as_bad (_("stack increment must be multiple of 4"));
3762 ignore_rest_of_line ();
3766 /* Don't generate any opcodes, just record the details for later. */
3767 unwind
.frame_size
+= offset
;
3768 unwind
.pending_offset
+= offset
;
3770 demand_empty_rest_of_line ();
3773 /* Parse an unwind_setfp directive. */
3776 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3782 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3783 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3786 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3788 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3790 as_bad (_("expected <reg>, <reg>"));
3791 ignore_rest_of_line ();
3795 /* Optional constant. */
3796 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3798 if (immediate_for_directive (&offset
) == FAIL
)
3804 demand_empty_rest_of_line ();
3806 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3808 as_bad (_("register must be either sp or set by a previous"
3809 "unwind_movsp directive"));
3813 /* Don't generate any opcodes, just record the information for later. */
3814 unwind
.fp_reg
= fp_reg
;
3817 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3819 unwind
.fp_offset
-= offset
;
3822 /* Parse an unwind_raw directive. */
3825 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3828 /* This is an arbitrary limit. */
3829 unsigned char op
[16];
3833 if (exp
.X_op
== O_constant
3834 && skip_past_comma (&input_line_pointer
) != FAIL
)
3836 unwind
.frame_size
+= exp
.X_add_number
;
3840 exp
.X_op
= O_illegal
;
3842 if (exp
.X_op
!= O_constant
)
3844 as_bad (_("expected <offset>, <opcode>"));
3845 ignore_rest_of_line ();
3851 /* Parse the opcode. */
3856 as_bad (_("unwind opcode too long"));
3857 ignore_rest_of_line ();
3859 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3861 as_bad (_("invalid unwind opcode"));
3862 ignore_rest_of_line ();
3865 op
[count
++] = exp
.X_add_number
;
3867 /* Parse the next byte. */
3868 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3874 /* Add the opcode bytes in reverse order. */
3876 add_unwind_opcode (op
[count
], 1);
3878 demand_empty_rest_of_line ();
3882 /* Parse a .eabi_attribute directive. */
3885 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3887 s_vendor_attribute (OBJ_ATTR_PROC
);
3889 #endif /* OBJ_ELF */
3891 static void s_arm_arch (int);
3892 static void s_arm_object_arch (int);
3893 static void s_arm_cpu (int);
3894 static void s_arm_fpu (int);
3899 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3906 if (exp
.X_op
== O_symbol
)
3907 exp
.X_op
= O_secrel
;
3909 emit_expr (&exp
, 4);
3911 while (*input_line_pointer
++ == ',');
3913 input_line_pointer
--;
3914 demand_empty_rest_of_line ();
3918 /* This table describes all the machine specific pseudo-ops the assembler
3919 has to support. The fields are:
3920 pseudo-op name without dot
3921 function to call to execute this pseudo-op
3922 Integer arg to pass to the function. */
3924 const pseudo_typeS md_pseudo_table
[] =
3926 /* Never called because '.req' does not start a line. */
3927 { "req", s_req
, 0 },
3928 /* Following two are likewise never called. */
3931 { "unreq", s_unreq
, 0 },
3932 { "bss", s_bss
, 0 },
3933 { "align", s_align
, 0 },
3934 { "arm", s_arm
, 0 },
3935 { "thumb", s_thumb
, 0 },
3936 { "code", s_code
, 0 },
3937 { "force_thumb", s_force_thumb
, 0 },
3938 { "thumb_func", s_thumb_func
, 0 },
3939 { "thumb_set", s_thumb_set
, 0 },
3940 { "even", s_even
, 0 },
3941 { "ltorg", s_ltorg
, 0 },
3942 { "pool", s_ltorg
, 0 },
3943 { "syntax", s_syntax
, 0 },
3944 { "cpu", s_arm_cpu
, 0 },
3945 { "arch", s_arm_arch
, 0 },
3946 { "object_arch", s_arm_object_arch
, 0 },
3947 { "fpu", s_arm_fpu
, 0 },
3949 { "word", s_arm_elf_cons
, 4 },
3950 { "long", s_arm_elf_cons
, 4 },
3951 { "rel31", s_arm_rel31
, 0 },
3952 { "fnstart", s_arm_unwind_fnstart
, 0 },
3953 { "fnend", s_arm_unwind_fnend
, 0 },
3954 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3955 { "personality", s_arm_unwind_personality
, 0 },
3956 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3957 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3958 { "save", s_arm_unwind_save
, 0 },
3959 { "vsave", s_arm_unwind_save
, 1 },
3960 { "movsp", s_arm_unwind_movsp
, 0 },
3961 { "pad", s_arm_unwind_pad
, 0 },
3962 { "setfp", s_arm_unwind_setfp
, 0 },
3963 { "unwind_raw", s_arm_unwind_raw
, 0 },
3964 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3968 /* These are used for dwarf. */
3972 /* These are used for dwarf2. */
3973 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3974 { "loc", dwarf2_directive_loc
, 0 },
3975 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3977 { "extend", float_cons
, 'x' },
3978 { "ldouble", float_cons
, 'x' },
3979 { "packed", float_cons
, 'p' },
3981 {"secrel32", pe_directive_secrel
, 0},
3986 /* Parser functions used exclusively in instruction operands. */
3988 /* Generic immediate-value read function for use in insn parsing.
3989 STR points to the beginning of the immediate (the leading #);
3990 VAL receives the value; if the value is outside [MIN, MAX]
3991 issue an error. PREFIX_OPT is true if the immediate prefix is
3995 parse_immediate (char **str
, int *val
, int min
, int max
,
3996 bfd_boolean prefix_opt
)
3999 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4000 if (exp
.X_op
!= O_constant
)
4002 inst
.error
= _("constant expression required");
4006 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4008 inst
.error
= _("immediate value out of range");
4012 *val
= exp
.X_add_number
;
4016 /* Less-generic immediate-value read function with the possibility of loading a
4017 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4018 instructions. Puts the result directly in inst.operands[i]. */
4021 parse_big_immediate (char **str
, int i
)
4026 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4028 if (exp
.X_op
== O_constant
)
4030 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4031 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4032 O_constant. We have to be careful not to break compilation for
4033 32-bit X_add_number, though. */
4034 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4036 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4037 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4038 inst
.operands
[i
].regisimm
= 1;
4041 else if (exp
.X_op
== O_big
4042 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4043 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4045 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4046 /* Bignums have their least significant bits in
4047 generic_bignum[0]. Make sure we put 32 bits in imm and
4048 32 bits in reg, in a (hopefully) portable way. */
4049 assert (parts
!= 0);
4050 inst
.operands
[i
].imm
= 0;
4051 for (j
= 0; j
< parts
; j
++, idx
++)
4052 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4053 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4054 inst
.operands
[i
].reg
= 0;
4055 for (j
= 0; j
< parts
; j
++, idx
++)
4056 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4057 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4058 inst
.operands
[i
].regisimm
= 1;
4068 /* Returns the pseudo-register number of an FPA immediate constant,
4069 or FAIL if there isn't a valid constant here. */
4072 parse_fpa_immediate (char ** str
)
4074 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4080 /* First try and match exact strings, this is to guarantee
4081 that some formats will work even for cross assembly. */
4083 for (i
= 0; fp_const
[i
]; i
++)
4085 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4089 *str
+= strlen (fp_const
[i
]);
4090 if (is_end_of_line
[(unsigned char) **str
])
4096 /* Just because we didn't get a match doesn't mean that the constant
4097 isn't valid, just that it is in a format that we don't
4098 automatically recognize. Try parsing it with the standard
4099 expression routines. */
4101 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4103 /* Look for a raw floating point number. */
4104 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4105 && is_end_of_line
[(unsigned char) *save_in
])
4107 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4109 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4111 if (words
[j
] != fp_values
[i
][j
])
4115 if (j
== MAX_LITTLENUMS
)
4123 /* Try and parse a more complex expression, this will probably fail
4124 unless the code uses a floating point prefix (eg "0f"). */
4125 save_in
= input_line_pointer
;
4126 input_line_pointer
= *str
;
4127 if (expression (&exp
) == absolute_section
4128 && exp
.X_op
== O_big
4129 && exp
.X_add_number
< 0)
4131 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4133 if (gen_to_words (words
, 5, (long) 15) == 0)
4135 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4137 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4139 if (words
[j
] != fp_values
[i
][j
])
4143 if (j
== MAX_LITTLENUMS
)
4145 *str
= input_line_pointer
;
4146 input_line_pointer
= save_in
;
4153 *str
= input_line_pointer
;
4154 input_line_pointer
= save_in
;
4155 inst
.error
= _("invalid FPA immediate expression");
4159 /* Returns 1 if a number has "quarter-precision" float format
4160 0baBbbbbbc defgh000 00000000 00000000. */
4163 is_quarter_float (unsigned imm
)
4165 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4166 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4169 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4170 0baBbbbbbc defgh000 00000000 00000000.
4171 The zero and minus-zero cases need special handling, since they can't be
4172 encoded in the "quarter-precision" float format, but can nonetheless be
4173 loaded as integer constants. */
4176 parse_qfloat_immediate (char **ccp
, int *immed
)
4180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4181 int found_fpchar
= 0;
4183 skip_past_char (&str
, '#');
4185 /* We must not accidentally parse an integer as a floating-point number. Make
4186 sure that the value we parse is not an integer by checking for special
4187 characters '.' or 'e'.
4188 FIXME: This is a horrible hack, but doing better is tricky because type
4189 information isn't in a very usable state at parse time. */
4191 skip_whitespace (fpnum
);
4193 if (strncmp (fpnum
, "0x", 2) == 0)
4197 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4198 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4208 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4210 unsigned fpword
= 0;
4213 /* Our FP word must be 32 bits (single-precision FP). */
4214 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4216 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4220 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4233 /* Shift operands. */
4236 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4239 struct asm_shift_name
4242 enum shift_kind kind
;
4245 /* Third argument to parse_shift. */
4246 enum parse_shift_mode
4248 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4249 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4250 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4251 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4252 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4255 /* Parse a <shift> specifier on an ARM data processing instruction.
4256 This has three forms:
4258 (LSL|LSR|ASL|ASR|ROR) Rs
4259 (LSL|LSR|ASL|ASR|ROR) #imm
4262 Note that ASL is assimilated to LSL in the instruction encoding, and
4263 RRX to ROR #0 (which cannot be written as such). */
4266 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4268 const struct asm_shift_name
*shift_name
;
4269 enum shift_kind shift
;
4274 for (p
= *str
; ISALPHA (*p
); p
++)
4279 inst
.error
= _("shift expression expected");
4283 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4285 if (shift_name
== NULL
)
4287 inst
.error
= _("shift expression expected");
4291 shift
= shift_name
->kind
;
4295 case NO_SHIFT_RESTRICT
:
4296 case SHIFT_IMMEDIATE
: break;
4298 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4299 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4301 inst
.error
= _("'LSL' or 'ASR' required");
4306 case SHIFT_LSL_IMMEDIATE
:
4307 if (shift
!= SHIFT_LSL
)
4309 inst
.error
= _("'LSL' required");
4314 case SHIFT_ASR_IMMEDIATE
:
4315 if (shift
!= SHIFT_ASR
)
4317 inst
.error
= _("'ASR' required");
4325 if (shift
!= SHIFT_RRX
)
4327 /* Whitespace can appear here if the next thing is a bare digit. */
4328 skip_whitespace (p
);
4330 if (mode
== NO_SHIFT_RESTRICT
4331 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4333 inst
.operands
[i
].imm
= reg
;
4334 inst
.operands
[i
].immisreg
= 1;
4336 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4339 inst
.operands
[i
].shift_kind
= shift
;
4340 inst
.operands
[i
].shifted
= 1;
4345 /* Parse a <shifter_operand> for an ARM data processing instruction:
4348 #<immediate>, <rotate>
4352 where <shift> is defined by parse_shift above, and <rotate> is a
4353 multiple of 2 between 0 and 30. Validation of immediate operands
4354 is deferred to md_apply_fix. */
4357 parse_shifter_operand (char **str
, int i
)
4362 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4364 inst
.operands
[i
].reg
= value
;
4365 inst
.operands
[i
].isreg
= 1;
4367 /* parse_shift will override this if appropriate */
4368 inst
.reloc
.exp
.X_op
= O_constant
;
4369 inst
.reloc
.exp
.X_add_number
= 0;
4371 if (skip_past_comma (str
) == FAIL
)
4374 /* Shift operation on register. */
4375 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4378 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4381 if (skip_past_comma (str
) == SUCCESS
)
4383 /* #x, y -- ie explicit rotation by Y. */
4384 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4387 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4389 inst
.error
= _("constant expression expected");
4393 value
= expr
.X_add_number
;
4394 if (value
< 0 || value
> 30 || value
% 2 != 0)
4396 inst
.error
= _("invalid rotation");
4399 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4401 inst
.error
= _("invalid constant");
4405 /* Convert to decoded value. md_apply_fix will put it back. */
4406 inst
.reloc
.exp
.X_add_number
4407 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4408 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4411 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4412 inst
.reloc
.pc_rel
= 0;
4416 /* Group relocation information. Each entry in the table contains the
4417 textual name of the relocation as may appear in assembler source
4418 and must end with a colon.
4419 Along with this textual name are the relocation codes to be used if
4420 the corresponding instruction is an ALU instruction (ADD or SUB only),
4421 an LDR, an LDRS, or an LDC. */
4423 struct group_reloc_table_entry
4434 /* Varieties of non-ALU group relocation. */
4441 static struct group_reloc_table_entry group_reloc_table
[] =
4442 { /* Program counter relative: */
4444 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4449 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4450 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4451 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4452 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4454 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4459 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4460 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4461 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4462 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4464 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4465 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4466 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4467 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4468 /* Section base relative */
4470 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4475 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4476 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4477 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4478 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4480 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4485 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4486 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4487 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4488 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4490 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4491 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4492 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4493 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4495 /* Given the address of a pointer pointing to the textual name of a group
4496 relocation as may appear in assembler source, attempt to find its details
4497 in group_reloc_table. The pointer will be updated to the character after
4498 the trailing colon. On failure, FAIL will be returned; SUCCESS
4499 otherwise. On success, *entry will be updated to point at the relevant
4500 group_reloc_table entry. */
4503 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4506 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4508 int length
= strlen (group_reloc_table
[i
].name
);
4510 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4511 && (*str
)[length
] == ':')
4513 *out
= &group_reloc_table
[i
];
4514 *str
+= (length
+ 1);
4522 /* Parse a <shifter_operand> for an ARM data processing instruction
4523 (as for parse_shifter_operand) where group relocations are allowed:
4526 #<immediate>, <rotate>
4527 #:<group_reloc>:<expression>
4531 where <group_reloc> is one of the strings defined in group_reloc_table.
4532 The hashes are optional.
4534 Everything else is as for parse_shifter_operand. */
4536 static parse_operand_result
4537 parse_shifter_operand_group_reloc (char **str
, int i
)
4539 /* Determine if we have the sequence of characters #: or just :
4540 coming next. If we do, then we check for a group relocation.
4541 If we don't, punt the whole lot to parse_shifter_operand. */
4543 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4544 || (*str
)[0] == ':')
4546 struct group_reloc_table_entry
*entry
;
4548 if ((*str
)[0] == '#')
4553 /* Try to parse a group relocation. Anything else is an error. */
4554 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4556 inst
.error
= _("unknown group relocation");
4557 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4560 /* We now have the group relocation table entry corresponding to
4561 the name in the assembler source. Next, we parse the expression. */
4562 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4563 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4565 /* Record the relocation type (always the ALU variant here). */
4566 inst
.reloc
.type
= entry
->alu_code
;
4567 assert (inst
.reloc
.type
!= 0);
4569 return PARSE_OPERAND_SUCCESS
;
4572 return parse_shifter_operand (str
, i
) == SUCCESS
4573 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4575 /* Never reached. */
4578 /* Parse all forms of an ARM address expression. Information is written
4579 to inst.operands[i] and/or inst.reloc.
4581 Preindexed addressing (.preind=1):
4583 [Rn, #offset] .reg=Rn .reloc.exp=offset
4584 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4585 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4586 .shift_kind=shift .reloc.exp=shift_imm
4588 These three may have a trailing ! which causes .writeback to be set also.
4590 Postindexed addressing (.postind=1, .writeback=1):
4592 [Rn], #offset .reg=Rn .reloc.exp=offset
4593 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4594 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4595 .shift_kind=shift .reloc.exp=shift_imm
4597 Unindexed addressing (.preind=0, .postind=0):
4599 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4603 [Rn]{!} shorthand for [Rn,#0]{!}
4604 =immediate .isreg=0 .reloc.exp=immediate
4605 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4607 It is the caller's responsibility to check for addressing modes not
4608 supported by the instruction, and to set inst.reloc.type. */
4610 static parse_operand_result
4611 parse_address_main (char **str
, int i
, int group_relocations
,
4612 group_reloc_type group_type
)
4617 if (skip_past_char (&p
, '[') == FAIL
)
4619 if (skip_past_char (&p
, '=') == FAIL
)
4621 /* bare address - translate to PC-relative offset */
4622 inst
.reloc
.pc_rel
= 1;
4623 inst
.operands
[i
].reg
= REG_PC
;
4624 inst
.operands
[i
].isreg
= 1;
4625 inst
.operands
[i
].preind
= 1;
4627 /* else a load-constant pseudo op, no special treatment needed here */
4629 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4630 return PARSE_OPERAND_FAIL
;
4633 return PARSE_OPERAND_SUCCESS
;
4636 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4638 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4639 return PARSE_OPERAND_FAIL
;
4641 inst
.operands
[i
].reg
= reg
;
4642 inst
.operands
[i
].isreg
= 1;
4644 if (skip_past_comma (&p
) == SUCCESS
)
4646 inst
.operands
[i
].preind
= 1;
4649 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4651 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4653 inst
.operands
[i
].imm
= reg
;
4654 inst
.operands
[i
].immisreg
= 1;
4656 if (skip_past_comma (&p
) == SUCCESS
)
4657 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4658 return PARSE_OPERAND_FAIL
;
4660 else if (skip_past_char (&p
, ':') == SUCCESS
)
4662 /* FIXME: '@' should be used here, but it's filtered out by generic
4663 code before we get to see it here. This may be subject to
4666 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4667 if (exp
.X_op
!= O_constant
)
4669 inst
.error
= _("alignment must be constant");
4670 return PARSE_OPERAND_FAIL
;
4672 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4673 inst
.operands
[i
].immisalign
= 1;
4674 /* Alignments are not pre-indexes. */
4675 inst
.operands
[i
].preind
= 0;
4679 if (inst
.operands
[i
].negative
)
4681 inst
.operands
[i
].negative
= 0;
4685 if (group_relocations
4686 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4688 struct group_reloc_table_entry
*entry
;
4690 /* Skip over the #: or : sequence. */
4696 /* Try to parse a group relocation. Anything else is an
4698 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4700 inst
.error
= _("unknown group relocation");
4701 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4704 /* We now have the group relocation table entry corresponding to
4705 the name in the assembler source. Next, we parse the
4707 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4708 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4710 /* Record the relocation type. */
4714 inst
.reloc
.type
= entry
->ldr_code
;
4718 inst
.reloc
.type
= entry
->ldrs_code
;
4722 inst
.reloc
.type
= entry
->ldc_code
;
4729 if (inst
.reloc
.type
== 0)
4731 inst
.error
= _("this group relocation is not allowed on this instruction");
4732 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4736 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4737 return PARSE_OPERAND_FAIL
;
4741 if (skip_past_char (&p
, ']') == FAIL
)
4743 inst
.error
= _("']' expected");
4744 return PARSE_OPERAND_FAIL
;
4747 if (skip_past_char (&p
, '!') == SUCCESS
)
4748 inst
.operands
[i
].writeback
= 1;
4750 else if (skip_past_comma (&p
) == SUCCESS
)
4752 if (skip_past_char (&p
, '{') == SUCCESS
)
4754 /* [Rn], {expr} - unindexed, with option */
4755 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4756 0, 255, TRUE
) == FAIL
)
4757 return PARSE_OPERAND_FAIL
;
4759 if (skip_past_char (&p
, '}') == FAIL
)
4761 inst
.error
= _("'}' expected at end of 'option' field");
4762 return PARSE_OPERAND_FAIL
;
4764 if (inst
.operands
[i
].preind
)
4766 inst
.error
= _("cannot combine index with option");
4767 return PARSE_OPERAND_FAIL
;
4770 return PARSE_OPERAND_SUCCESS
;
4774 inst
.operands
[i
].postind
= 1;
4775 inst
.operands
[i
].writeback
= 1;
4777 if (inst
.operands
[i
].preind
)
4779 inst
.error
= _("cannot combine pre- and post-indexing");
4780 return PARSE_OPERAND_FAIL
;
4784 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4786 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4788 /* We might be using the immediate for alignment already. If we
4789 are, OR the register number into the low-order bits. */
4790 if (inst
.operands
[i
].immisalign
)
4791 inst
.operands
[i
].imm
|= reg
;
4793 inst
.operands
[i
].imm
= reg
;
4794 inst
.operands
[i
].immisreg
= 1;
4796 if (skip_past_comma (&p
) == SUCCESS
)
4797 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4798 return PARSE_OPERAND_FAIL
;
4802 if (inst
.operands
[i
].negative
)
4804 inst
.operands
[i
].negative
= 0;
4807 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4808 return PARSE_OPERAND_FAIL
;
4813 /* If at this point neither .preind nor .postind is set, we have a
4814 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4815 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4817 inst
.operands
[i
].preind
= 1;
4818 inst
.reloc
.exp
.X_op
= O_constant
;
4819 inst
.reloc
.exp
.X_add_number
= 0;
4822 return PARSE_OPERAND_SUCCESS
;
4826 parse_address (char **str
, int i
)
4828 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4832 static parse_operand_result
4833 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4835 return parse_address_main (str
, i
, 1, type
);
4838 /* Parse an operand for a MOVW or MOVT instruction. */
4840 parse_half (char **str
)
4845 skip_past_char (&p
, '#');
4846 if (strncasecmp (p
, ":lower16:", 9) == 0)
4847 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4848 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4849 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4851 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4854 skip_whitespace (p
);
4857 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4860 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4862 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4864 inst
.error
= _("constant expression expected");
4867 if (inst
.reloc
.exp
.X_add_number
< 0
4868 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4870 inst
.error
= _("immediate value out of range");
4878 /* Miscellaneous. */
4880 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4881 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4883 parse_psr (char **str
)
4886 unsigned long psr_field
;
4887 const struct asm_psr
*psr
;
4890 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4891 feature for ease of use and backwards compatibility. */
4893 if (strncasecmp (p
, "SPSR", 4) == 0)
4894 psr_field
= SPSR_BIT
;
4895 else if (strncasecmp (p
, "CPSR", 4) == 0)
4902 while (ISALNUM (*p
) || *p
== '_');
4904 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4915 /* A suffix follows. */
4921 while (ISALNUM (*p
) || *p
== '_');
4923 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4927 psr_field
|= psr
->field
;
4932 goto error
; /* Garbage after "[CS]PSR". */
4934 psr_field
|= (PSR_c
| PSR_f
);
4940 inst
.error
= _("flag for {c}psr instruction expected");
4944 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4945 value suitable for splatting into the AIF field of the instruction. */
4948 parse_cps_flags (char **str
)
4957 case '\0': case ',':
4960 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4961 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4962 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4965 inst
.error
= _("unrecognized CPS flag");
4970 if (saw_a_flag
== 0)
4972 inst
.error
= _("missing CPS flags");
4980 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4981 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4984 parse_endian_specifier (char **str
)
4989 if (strncasecmp (s
, "BE", 2))
4991 else if (strncasecmp (s
, "LE", 2))
4995 inst
.error
= _("valid endian specifiers are be or le");
4999 if (ISALNUM (s
[2]) || s
[2] == '_')
5001 inst
.error
= _("valid endian specifiers are be or le");
5006 return little_endian
;
5009 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5010 value suitable for poking into the rotate field of an sxt or sxta
5011 instruction, or FAIL on error. */
5014 parse_ror (char **str
)
5019 if (strncasecmp (s
, "ROR", 3) == 0)
5023 inst
.error
= _("missing rotation field after comma");
5027 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5032 case 0: *str
= s
; return 0x0;
5033 case 8: *str
= s
; return 0x1;
5034 case 16: *str
= s
; return 0x2;
5035 case 24: *str
= s
; return 0x3;
5038 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5043 /* Parse a conditional code (from conds[] below). The value returned is in the
5044 range 0 .. 14, or FAIL. */
5046 parse_cond (char **str
)
5049 const struct asm_cond
*c
;
5051 /* Condition codes are always 2 characters, so matching up to
5052 3 characters is sufficient. */
5057 while (ISALPHA (*q
) && n
< 3)
5059 cond
[n
] = TOLOWER(*q
);
5064 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5067 inst
.error
= _("condition required");
5075 /* Parse an option for a barrier instruction. Returns the encoding for the
5078 parse_barrier (char **str
)
5081 const struct asm_barrier_opt
*o
;
5084 while (ISALPHA (*q
))
5087 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5095 /* Parse the operands of a table branch instruction. Similar to a memory
5098 parse_tb (char **str
)
5103 if (skip_past_char (&p
, '[') == FAIL
)
5105 inst
.error
= _("'[' expected");
5109 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5111 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5114 inst
.operands
[0].reg
= reg
;
5116 if (skip_past_comma (&p
) == FAIL
)
5118 inst
.error
= _("',' expected");
5122 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5124 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5127 inst
.operands
[0].imm
= reg
;
5129 if (skip_past_comma (&p
) == SUCCESS
)
5131 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5133 if (inst
.reloc
.exp
.X_add_number
!= 1)
5135 inst
.error
= _("invalid shift");
5138 inst
.operands
[0].shifted
= 1;
5141 if (skip_past_char (&p
, ']') == FAIL
)
5143 inst
.error
= _("']' expected");
5150 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5151 information on the types the operands can take and how they are encoded.
5152 Up to four operands may be read; this function handles setting the
5153 ".present" field for each read operand itself.
5154 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5155 else returns FAIL. */
5158 parse_neon_mov (char **str
, int *which_operand
)
5160 int i
= *which_operand
, val
;
5161 enum arm_reg_type rtype
;
5163 struct neon_type_el optype
;
5165 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5167 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5168 inst
.operands
[i
].reg
= val
;
5169 inst
.operands
[i
].isscalar
= 1;
5170 inst
.operands
[i
].vectype
= optype
;
5171 inst
.operands
[i
++].present
= 1;
5173 if (skip_past_comma (&ptr
) == FAIL
)
5176 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5179 inst
.operands
[i
].reg
= val
;
5180 inst
.operands
[i
].isreg
= 1;
5181 inst
.operands
[i
].present
= 1;
5183 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5186 /* Cases 0, 1, 2, 3, 5 (D only). */
5187 if (skip_past_comma (&ptr
) == FAIL
)
5190 inst
.operands
[i
].reg
= val
;
5191 inst
.operands
[i
].isreg
= 1;
5192 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5193 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5194 inst
.operands
[i
].isvec
= 1;
5195 inst
.operands
[i
].vectype
= optype
;
5196 inst
.operands
[i
++].present
= 1;
5198 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5200 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5201 Case 13: VMOV <Sd>, <Rm> */
5202 inst
.operands
[i
].reg
= val
;
5203 inst
.operands
[i
].isreg
= 1;
5204 inst
.operands
[i
].present
= 1;
5206 if (rtype
== REG_TYPE_NQ
)
5208 first_error (_("can't use Neon quad register here"));
5211 else if (rtype
!= REG_TYPE_VFS
)
5214 if (skip_past_comma (&ptr
) == FAIL
)
5216 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5218 inst
.operands
[i
].reg
= val
;
5219 inst
.operands
[i
].isreg
= 1;
5220 inst
.operands
[i
].present
= 1;
5223 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5226 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5227 Case 1: VMOV<c><q> <Dd>, <Dm>
5228 Case 8: VMOV.F32 <Sd>, <Sm>
5229 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5231 inst
.operands
[i
].reg
= val
;
5232 inst
.operands
[i
].isreg
= 1;
5233 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5234 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5235 inst
.operands
[i
].isvec
= 1;
5236 inst
.operands
[i
].vectype
= optype
;
5237 inst
.operands
[i
].present
= 1;
5239 if (skip_past_comma (&ptr
) == SUCCESS
)
5244 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5247 inst
.operands
[i
].reg
= val
;
5248 inst
.operands
[i
].isreg
= 1;
5249 inst
.operands
[i
++].present
= 1;
5251 if (skip_past_comma (&ptr
) == FAIL
)
5254 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5257 inst
.operands
[i
].reg
= val
;
5258 inst
.operands
[i
].isreg
= 1;
5259 inst
.operands
[i
++].present
= 1;
5262 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5263 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5264 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5265 Case 10: VMOV.F32 <Sd>, #<imm>
5266 Case 11: VMOV.F64 <Dd>, #<imm> */
5267 inst
.operands
[i
].immisfloat
= 1;
5268 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5269 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5270 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5274 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5278 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5281 inst
.operands
[i
].reg
= val
;
5282 inst
.operands
[i
].isreg
= 1;
5283 inst
.operands
[i
++].present
= 1;
5285 if (skip_past_comma (&ptr
) == FAIL
)
5288 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5290 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5291 inst
.operands
[i
].reg
= val
;
5292 inst
.operands
[i
].isscalar
= 1;
5293 inst
.operands
[i
].present
= 1;
5294 inst
.operands
[i
].vectype
= optype
;
5296 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5298 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5299 inst
.operands
[i
].reg
= val
;
5300 inst
.operands
[i
].isreg
= 1;
5301 inst
.operands
[i
++].present
= 1;
5303 if (skip_past_comma (&ptr
) == FAIL
)
5306 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5309 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5313 inst
.operands
[i
].reg
= val
;
5314 inst
.operands
[i
].isreg
= 1;
5315 inst
.operands
[i
].isvec
= 1;
5316 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5317 inst
.operands
[i
].vectype
= optype
;
5318 inst
.operands
[i
].present
= 1;
5320 if (rtype
== REG_TYPE_VFS
)
5324 if (skip_past_comma (&ptr
) == FAIL
)
5326 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5329 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5332 inst
.operands
[i
].reg
= val
;
5333 inst
.operands
[i
].isreg
= 1;
5334 inst
.operands
[i
].isvec
= 1;
5335 inst
.operands
[i
].issingle
= 1;
5336 inst
.operands
[i
].vectype
= optype
;
5337 inst
.operands
[i
].present
= 1;
5340 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5344 inst
.operands
[i
].reg
= val
;
5345 inst
.operands
[i
].isreg
= 1;
5346 inst
.operands
[i
].isvec
= 1;
5347 inst
.operands
[i
].issingle
= 1;
5348 inst
.operands
[i
].vectype
= optype
;
5349 inst
.operands
[i
++].present
= 1;
5354 first_error (_("parse error"));
5358 /* Successfully parsed the operands. Update args. */
5364 first_error (_("expected comma"));
5368 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5372 /* Matcher codes for parse_operands. */
5373 enum operand_parse_code
5375 OP_stop
, /* end of line */
5377 OP_RR
, /* ARM register */
5378 OP_RRnpc
, /* ARM register, not r15 */
5379 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5380 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5381 OP_RCP
, /* Coprocessor number */
5382 OP_RCN
, /* Coprocessor register */
5383 OP_RF
, /* FPA register */
5384 OP_RVS
, /* VFP single precision register */
5385 OP_RVD
, /* VFP double precision register (0..15) */
5386 OP_RND
, /* Neon double precision register (0..31) */
5387 OP_RNQ
, /* Neon quad precision register */
5388 OP_RVSD
, /* VFP single or double precision register */
5389 OP_RNDQ
, /* Neon double or quad precision register */
5390 OP_RNSDQ
, /* Neon single, double or quad precision register */
5391 OP_RNSC
, /* Neon scalar D[X] */
5392 OP_RVC
, /* VFP control register */
5393 OP_RMF
, /* Maverick F register */
5394 OP_RMD
, /* Maverick D register */
5395 OP_RMFX
, /* Maverick FX register */
5396 OP_RMDX
, /* Maverick DX register */
5397 OP_RMAX
, /* Maverick AX register */
5398 OP_RMDS
, /* Maverick DSPSC register */
5399 OP_RIWR
, /* iWMMXt wR register */
5400 OP_RIWC
, /* iWMMXt wC register */
5401 OP_RIWG
, /* iWMMXt wCG register */
5402 OP_RXA
, /* XScale accumulator register */
5404 OP_REGLST
, /* ARM register list */
5405 OP_VRSLST
, /* VFP single-precision register list */
5406 OP_VRDLST
, /* VFP double-precision register list */
5407 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5408 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5409 OP_NSTRLST
, /* Neon element/structure list */
5411 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5412 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5413 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5414 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5415 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5416 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5417 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5418 OP_VMOV
, /* Neon VMOV operands. */
5419 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5420 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5421 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5423 OP_I0
, /* immediate zero */
5424 OP_I7
, /* immediate value 0 .. 7 */
5425 OP_I15
, /* 0 .. 15 */
5426 OP_I16
, /* 1 .. 16 */
5427 OP_I16z
, /* 0 .. 16 */
5428 OP_I31
, /* 0 .. 31 */
5429 OP_I31w
, /* 0 .. 31, optional trailing ! */
5430 OP_I32
, /* 1 .. 32 */
5431 OP_I32z
, /* 0 .. 32 */
5432 OP_I63
, /* 0 .. 63 */
5433 OP_I63s
, /* -64 .. 63 */
5434 OP_I64
, /* 1 .. 64 */
5435 OP_I64z
, /* 0 .. 64 */
5436 OP_I255
, /* 0 .. 255 */
5438 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5439 OP_I7b
, /* 0 .. 7 */
5440 OP_I15b
, /* 0 .. 15 */
5441 OP_I31b
, /* 0 .. 31 */
5443 OP_SH
, /* shifter operand */
5444 OP_SHG
, /* shifter operand with possible group relocation */
5445 OP_ADDR
, /* Memory address expression (any mode) */
5446 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5447 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5448 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5449 OP_EXP
, /* arbitrary expression */
5450 OP_EXPi
, /* same, with optional immediate prefix */
5451 OP_EXPr
, /* same, with optional relocation suffix */
5452 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5454 OP_CPSF
, /* CPS flags */
5455 OP_ENDI
, /* Endianness specifier */
5456 OP_PSR
, /* CPSR/SPSR mask for msr */
5457 OP_COND
, /* conditional code */
5458 OP_TB
, /* Table branch. */
5460 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5461 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5463 OP_RRnpc_I0
, /* ARM register or literal 0 */
5464 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5465 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5466 OP_RF_IF
, /* FPA register or immediate */
5467 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5468 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5470 /* Optional operands. */
5471 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5472 OP_oI31b
, /* 0 .. 31 */
5473 OP_oI32b
, /* 1 .. 32 */
5474 OP_oIffffb
, /* 0 .. 65535 */
5475 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5477 OP_oRR
, /* ARM register */
5478 OP_oRRnpc
, /* ARM register, not the PC */
5479 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5480 OP_oRND
, /* Optional Neon double precision register */
5481 OP_oRNQ
, /* Optional Neon quad precision register */
5482 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5483 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5484 OP_oSHll
, /* LSL immediate */
5485 OP_oSHar
, /* ASR immediate */
5486 OP_oSHllar
, /* LSL or ASR immediate */
5487 OP_oROR
, /* ROR 0/8/16/24 */
5488 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5490 OP_FIRST_OPTIONAL
= OP_oI7b
5493 /* Generic instruction operand parser. This does no encoding and no
5494 semantic validation; it merely squirrels values away in the inst
5495 structure. Returns SUCCESS or FAIL depending on whether the
5496 specified grammar matched. */
5498 parse_operands (char *str
, const unsigned char *pattern
)
5500 unsigned const char *upat
= pattern
;
5501 char *backtrack_pos
= 0;
5502 const char *backtrack_error
= 0;
5503 int i
, val
, backtrack_index
= 0;
5504 enum arm_reg_type rtype
;
5505 parse_operand_result result
;
5507 #define po_char_or_fail(chr) do { \
5508 if (skip_past_char (&str, chr) == FAIL) \
5512 #define po_reg_or_fail(regtype) do { \
5513 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5514 &inst.operands[i].vectype); \
5517 first_error (_(reg_expected_msgs[regtype])); \
5520 inst.operands[i].reg = val; \
5521 inst.operands[i].isreg = 1; \
5522 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5523 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5524 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5525 || rtype == REG_TYPE_VFD \
5526 || rtype == REG_TYPE_NQ); \
5529 #define po_reg_or_goto(regtype, label) do { \
5530 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5531 &inst.operands[i].vectype); \
5535 inst.operands[i].reg = val; \
5536 inst.operands[i].isreg = 1; \
5537 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5538 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5539 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5540 || rtype == REG_TYPE_VFD \
5541 || rtype == REG_TYPE_NQ); \
5544 #define po_imm_or_fail(min, max, popt) do { \
5545 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5547 inst.operands[i].imm = val; \
5550 #define po_scalar_or_goto(elsz, label) do { \
5551 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5554 inst.operands[i].reg = val; \
5555 inst.operands[i].isscalar = 1; \
5558 #define po_misc_or_fail(expr) do { \
5563 #define po_misc_or_fail_no_backtrack(expr) do { \
5565 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5566 backtrack_pos = 0; \
5567 if (result != PARSE_OPERAND_SUCCESS) \
5571 skip_whitespace (str
);
5573 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5575 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5577 /* Remember where we are in case we need to backtrack. */
5578 assert (!backtrack_pos
);
5579 backtrack_pos
= str
;
5580 backtrack_error
= inst
.error
;
5581 backtrack_index
= i
;
5584 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5585 po_char_or_fail (',');
5593 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5594 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5595 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5596 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5597 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5598 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5600 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5602 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5604 /* Also accept generic coprocessor regs for unknown registers. */
5606 po_reg_or_fail (REG_TYPE_CN
);
5608 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5609 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5610 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5611 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5612 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5613 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5614 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5615 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5616 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5617 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5619 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5621 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5622 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5624 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5626 /* Neon scalar. Using an element size of 8 means that some invalid
5627 scalars are accepted here, so deal with those in later code. */
5628 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5630 /* WARNING: We can expand to two operands here. This has the potential
5631 to totally confuse the backtracking mechanism! It will be OK at
5632 least as long as we don't try to use optional args as well,
5636 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5637 inst
.operands
[i
].present
= 1;
5639 skip_past_comma (&str
);
5640 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5643 /* Optional register operand was omitted. Unfortunately, it's in
5644 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5645 here (this is a bit grotty). */
5646 inst
.operands
[i
] = inst
.operands
[i
-1];
5647 inst
.operands
[i
-1].present
= 0;
5650 /* There's a possibility of getting a 64-bit immediate here, so
5651 we need special handling. */
5652 if (parse_big_immediate (&str
, i
) == FAIL
)
5654 inst
.error
= _("immediate value is out of range");
5662 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5665 po_imm_or_fail (0, 0, TRUE
);
5670 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5675 po_scalar_or_goto (8, try_rr
);
5678 po_reg_or_fail (REG_TYPE_RN
);
5684 po_scalar_or_goto (8, try_nsdq
);
5687 po_reg_or_fail (REG_TYPE_NSDQ
);
5693 po_scalar_or_goto (8, try_ndq
);
5696 po_reg_or_fail (REG_TYPE_NDQ
);
5702 po_scalar_or_goto (8, try_vfd
);
5705 po_reg_or_fail (REG_TYPE_VFD
);
5710 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5711 not careful then bad things might happen. */
5712 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5717 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5720 /* There's a possibility of getting a 64-bit immediate here, so
5721 we need special handling. */
5722 if (parse_big_immediate (&str
, i
) == FAIL
)
5724 inst
.error
= _("immediate value is out of range");
5732 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5735 po_imm_or_fail (0, 63, TRUE
);
5740 po_char_or_fail ('[');
5741 po_reg_or_fail (REG_TYPE_RN
);
5742 po_char_or_fail (']');
5747 po_reg_or_fail (REG_TYPE_RN
);
5748 if (skip_past_char (&str
, '!') == SUCCESS
)
5749 inst
.operands
[i
].writeback
= 1;
5753 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5754 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5755 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5756 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5757 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5758 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5759 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5760 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5761 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5762 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5763 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5764 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5766 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5768 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5769 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5771 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5772 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5773 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5775 /* Immediate variants */
5777 po_char_or_fail ('{');
5778 po_imm_or_fail (0, 255, TRUE
);
5779 po_char_or_fail ('}');
5783 /* The expression parser chokes on a trailing !, so we have
5784 to find it first and zap it. */
5787 while (*s
&& *s
!= ',')
5792 inst
.operands
[i
].writeback
= 1;
5794 po_imm_or_fail (0, 31, TRUE
);
5802 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5807 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5812 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5814 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5816 val
= parse_reloc (&str
);
5819 inst
.error
= _("unrecognized relocation suffix");
5822 else if (val
!= BFD_RELOC_UNUSED
)
5824 inst
.operands
[i
].imm
= val
;
5825 inst
.operands
[i
].hasreloc
= 1;
5830 /* Operand for MOVW or MOVT. */
5832 po_misc_or_fail (parse_half (&str
));
5835 /* Register or expression */
5836 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5837 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5839 /* Register or immediate */
5840 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5841 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5843 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5845 if (!is_immediate_prefix (*str
))
5848 val
= parse_fpa_immediate (&str
);
5851 /* FPA immediates are encoded as registers 8-15.
5852 parse_fpa_immediate has already applied the offset. */
5853 inst
.operands
[i
].reg
= val
;
5854 inst
.operands
[i
].isreg
= 1;
5857 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5858 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5860 /* Two kinds of register */
5863 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5865 || (rege
->type
!= REG_TYPE_MMXWR
5866 && rege
->type
!= REG_TYPE_MMXWC
5867 && rege
->type
!= REG_TYPE_MMXWCG
))
5869 inst
.error
= _("iWMMXt data or control register expected");
5872 inst
.operands
[i
].reg
= rege
->number
;
5873 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5879 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5881 || (rege
->type
!= REG_TYPE_MMXWC
5882 && rege
->type
!= REG_TYPE_MMXWCG
))
5884 inst
.error
= _("iWMMXt control register expected");
5887 inst
.operands
[i
].reg
= rege
->number
;
5888 inst
.operands
[i
].isreg
= 1;
5893 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5894 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5895 case OP_oROR
: val
= parse_ror (&str
); break;
5896 case OP_PSR
: val
= parse_psr (&str
); break;
5897 case OP_COND
: val
= parse_cond (&str
); break;
5898 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5901 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5902 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5905 val
= parse_psr (&str
);
5909 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5912 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5914 if (strncasecmp (str
, "APSR_", 5) == 0)
5921 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5922 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5923 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5924 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5925 default: found
= 16;
5929 inst
.operands
[i
].isvec
= 1;
5936 po_misc_or_fail (parse_tb (&str
));
5939 /* Register lists */
5941 val
= parse_reg_list (&str
);
5944 inst
.operands
[1].writeback
= 1;
5950 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5954 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5958 /* Allow Q registers too. */
5959 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5966 inst
.operands
[i
].issingle
= 1;
5971 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5976 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5977 &inst
.operands
[i
].vectype
);
5980 /* Addressing modes */
5982 po_misc_or_fail (parse_address (&str
, i
));
5986 po_misc_or_fail_no_backtrack (
5987 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5991 po_misc_or_fail_no_backtrack (
5992 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5996 po_misc_or_fail_no_backtrack (
5997 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6001 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6005 po_misc_or_fail_no_backtrack (
6006 parse_shifter_operand_group_reloc (&str
, i
));
6010 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6014 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6018 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6022 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6025 /* Various value-based sanity checks and shared operations. We
6026 do not signal immediate failures for the register constraints;
6027 this allows a syntax error to take precedence. */
6036 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6037 inst
.error
= BAD_PC
;
6055 inst
.operands
[i
].imm
= val
;
6062 /* If we get here, this operand was successfully parsed. */
6063 inst
.operands
[i
].present
= 1;
6067 inst
.error
= BAD_ARGS
;
6072 /* The parse routine should already have set inst.error, but set a
6073 default here just in case. */
6075 inst
.error
= _("syntax error");
6079 /* Do not backtrack over a trailing optional argument that
6080 absorbed some text. We will only fail again, with the
6081 'garbage following instruction' error message, which is
6082 probably less helpful than the current one. */
6083 if (backtrack_index
== i
&& backtrack_pos
!= str
6084 && upat
[i
+1] == OP_stop
)
6087 inst
.error
= _("syntax error");
6091 /* Try again, skipping the optional argument at backtrack_pos. */
6092 str
= backtrack_pos
;
6093 inst
.error
= backtrack_error
;
6094 inst
.operands
[backtrack_index
].present
= 0;
6095 i
= backtrack_index
;
6099 /* Check that we have parsed all the arguments. */
6100 if (*str
!= '\0' && !inst
.error
)
6101 inst
.error
= _("garbage following instruction");
6103 return inst
.error
? FAIL
: SUCCESS
;
6106 #undef po_char_or_fail
6107 #undef po_reg_or_fail
6108 #undef po_reg_or_goto
6109 #undef po_imm_or_fail
6110 #undef po_scalar_or_fail
6112 /* Shorthand macro for instruction encoding functions issuing errors. */
6113 #define constraint(expr, err) do { \
6121 /* Functions for operand encoding. ARM, then Thumb. */
6123 #define rotate_left(v, n) (v << n | v >> (32 - n))
6125 /* If VAL can be encoded in the immediate field of an ARM instruction,
6126 return the encoded form. Otherwise, return FAIL. */
6129 encode_arm_immediate (unsigned int val
)
6133 for (i
= 0; i
< 32; i
+= 2)
6134 if ((a
= rotate_left (val
, i
)) <= 0xff)
6135 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6140 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6141 return the encoded form. Otherwise, return FAIL. */
6143 encode_thumb32_immediate (unsigned int val
)
6150 for (i
= 1; i
<= 24; i
++)
6153 if ((val
& ~(0xff << i
)) == 0)
6154 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6158 if (val
== ((a
<< 16) | a
))
6160 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6164 if (val
== ((a
<< 16) | a
))
6165 return 0x200 | (a
>> 8);
6169 /* Encode a VFP SP or DP register number into inst.instruction. */
6172 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6174 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6177 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6180 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6183 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6188 first_error (_("D register out of range for selected VFP version"));
6196 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6200 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6204 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6208 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6212 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6216 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6224 /* Encode a <shift> in an ARM-format instruction. The immediate,
6225 if any, is handled by md_apply_fix. */
6227 encode_arm_shift (int i
)
6229 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6230 inst
.instruction
|= SHIFT_ROR
<< 5;
6233 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6234 if (inst
.operands
[i
].immisreg
)
6236 inst
.instruction
|= SHIFT_BY_REG
;
6237 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6240 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6245 encode_arm_shifter_operand (int i
)
6247 if (inst
.operands
[i
].isreg
)
6249 inst
.instruction
|= inst
.operands
[i
].reg
;
6250 encode_arm_shift (i
);
6253 inst
.instruction
|= INST_IMMEDIATE
;
6256 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6258 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6260 assert (inst
.operands
[i
].isreg
);
6261 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6263 if (inst
.operands
[i
].preind
)
6267 inst
.error
= _("instruction does not accept preindexed addressing");
6270 inst
.instruction
|= PRE_INDEX
;
6271 if (inst
.operands
[i
].writeback
)
6272 inst
.instruction
|= WRITE_BACK
;
6275 else if (inst
.operands
[i
].postind
)
6277 assert (inst
.operands
[i
].writeback
);
6279 inst
.instruction
|= WRITE_BACK
;
6281 else /* unindexed - only for coprocessor */
6283 inst
.error
= _("instruction does not accept unindexed addressing");
6287 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6288 && (((inst
.instruction
& 0x000f0000) >> 16)
6289 == ((inst
.instruction
& 0x0000f000) >> 12)))
6290 as_warn ((inst
.instruction
& LOAD_BIT
)
6291 ? _("destination register same as write-back base")
6292 : _("source register same as write-back base"));
6295 /* inst.operands[i] was set up by parse_address. Encode it into an
6296 ARM-format mode 2 load or store instruction. If is_t is true,
6297 reject forms that cannot be used with a T instruction (i.e. not
6300 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6302 encode_arm_addr_mode_common (i
, is_t
);
6304 if (inst
.operands
[i
].immisreg
)
6306 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6307 inst
.instruction
|= inst
.operands
[i
].imm
;
6308 if (!inst
.operands
[i
].negative
)
6309 inst
.instruction
|= INDEX_UP
;
6310 if (inst
.operands
[i
].shifted
)
6312 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6313 inst
.instruction
|= SHIFT_ROR
<< 5;
6316 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6317 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6321 else /* immediate offset in inst.reloc */
6323 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6324 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6328 /* inst.operands[i] was set up by parse_address. Encode it into an
6329 ARM-format mode 3 load or store instruction. Reject forms that
6330 cannot be used with such instructions. If is_t is true, reject
6331 forms that cannot be used with a T instruction (i.e. not
6334 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6336 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6338 inst
.error
= _("instruction does not accept scaled register index");
6342 encode_arm_addr_mode_common (i
, is_t
);
6344 if (inst
.operands
[i
].immisreg
)
6346 inst
.instruction
|= inst
.operands
[i
].imm
;
6347 if (!inst
.operands
[i
].negative
)
6348 inst
.instruction
|= INDEX_UP
;
6350 else /* immediate offset in inst.reloc */
6352 inst
.instruction
|= HWOFFSET_IMM
;
6353 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6354 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6358 /* inst.operands[i] was set up by parse_address. Encode it into an
6359 ARM-format instruction. Reject all forms which cannot be encoded
6360 into a coprocessor load/store instruction. If wb_ok is false,
6361 reject use of writeback; if unind_ok is false, reject use of
6362 unindexed addressing. If reloc_override is not 0, use it instead
6363 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6364 (in which case it is preserved). */
6367 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6369 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6371 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6373 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6375 assert (!inst
.operands
[i
].writeback
);
6378 inst
.error
= _("instruction does not support unindexed addressing");
6381 inst
.instruction
|= inst
.operands
[i
].imm
;
6382 inst
.instruction
|= INDEX_UP
;
6386 if (inst
.operands
[i
].preind
)
6387 inst
.instruction
|= PRE_INDEX
;
6389 if (inst
.operands
[i
].writeback
)
6391 if (inst
.operands
[i
].reg
== REG_PC
)
6393 inst
.error
= _("pc may not be used with write-back");
6398 inst
.error
= _("instruction does not support writeback");
6401 inst
.instruction
|= WRITE_BACK
;
6405 inst
.reloc
.type
= reloc_override
;
6406 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6407 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6408 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6411 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6413 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6419 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6420 Determine whether it can be performed with a move instruction; if
6421 it can, convert inst.instruction to that move instruction and
6422 return 1; if it can't, convert inst.instruction to a literal-pool
6423 load and return 0. If this is not a valid thing to do in the
6424 current context, set inst.error and return 1.
6426 inst.operands[i] describes the destination register. */
6429 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6434 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6438 if ((inst
.instruction
& tbit
) == 0)
6440 inst
.error
= _("invalid pseudo operation");
6443 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6445 inst
.error
= _("constant expression expected");
6448 if (inst
.reloc
.exp
.X_op
== O_constant
)
6452 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6454 /* This can be done with a mov(1) instruction. */
6455 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6456 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6462 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6465 /* This can be done with a mov instruction. */
6466 inst
.instruction
&= LITERAL_MASK
;
6467 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6468 inst
.instruction
|= value
& 0xfff;
6472 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6475 /* This can be done with a mvn instruction. */
6476 inst
.instruction
&= LITERAL_MASK
;
6477 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6478 inst
.instruction
|= value
& 0xfff;
6484 if (add_to_lit_pool () == FAIL
)
6486 inst
.error
= _("literal pool insertion failed");
6489 inst
.operands
[1].reg
= REG_PC
;
6490 inst
.operands
[1].isreg
= 1;
6491 inst
.operands
[1].preind
= 1;
6492 inst
.reloc
.pc_rel
= 1;
6493 inst
.reloc
.type
= (thumb_p
6494 ? BFD_RELOC_ARM_THUMB_OFFSET
6496 ? BFD_RELOC_ARM_HWLITERAL
6497 : BFD_RELOC_ARM_LITERAL
));
6501 /* Functions for instruction encoding, sorted by sub-architecture.
6502 First some generics; their names are taken from the conventional
6503 bit positions for register arguments in ARM format instructions. */
6513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6520 inst
.instruction
|= inst
.operands
[1].reg
;
6526 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6527 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6533 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6534 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6540 unsigned Rn
= inst
.operands
[2].reg
;
6541 /* Enforce restrictions on SWP instruction. */
6542 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6543 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6544 _("Rn must not overlap other operands"));
6545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6546 inst
.instruction
|= inst
.operands
[1].reg
;
6547 inst
.instruction
|= Rn
<< 16;
6553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6554 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6555 inst
.instruction
|= inst
.operands
[2].reg
;
6561 inst
.instruction
|= inst
.operands
[0].reg
;
6562 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6563 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6569 inst
.instruction
|= inst
.operands
[0].imm
;
6575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6576 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6579 /* ARM instructions, in alphabetical order by function name (except
6580 that wrapper functions appear immediately after the function they
6583 /* This is a pseudo-op of the form "adr rd, label" to be converted
6584 into a relative address of the form "add rd, pc, #label-.-8". */
6589 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6591 /* Frag hacking will turn this into a sub instruction if the offset turns
6592 out to be negative. */
6593 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6594 inst
.reloc
.pc_rel
= 1;
6595 inst
.reloc
.exp
.X_add_number
-= 8;
6598 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6599 into a relative address of the form:
6600 add rd, pc, #low(label-.-8)"
6601 add rd, rd, #high(label-.-8)" */
6606 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6608 /* Frag hacking will turn this into a sub instruction if the offset turns
6609 out to be negative. */
6610 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6611 inst
.reloc
.pc_rel
= 1;
6612 inst
.size
= INSN_SIZE
* 2;
6613 inst
.reloc
.exp
.X_add_number
-= 8;
6619 if (!inst
.operands
[1].present
)
6620 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6621 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6622 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6623 encode_arm_shifter_operand (2);
6629 if (inst
.operands
[0].present
)
6631 constraint ((inst
.instruction
& 0xf0) != 0x40
6632 && inst
.operands
[0].imm
!= 0xf,
6633 _("bad barrier type"));
6634 inst
.instruction
|= inst
.operands
[0].imm
;
6637 inst
.instruction
|= 0xf;
6643 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6644 constraint (msb
> 32, _("bit-field extends past end of register"));
6645 /* The instruction encoding stores the LSB and MSB,
6646 not the LSB and width. */
6647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6648 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6649 inst
.instruction
|= (msb
- 1) << 16;
6657 /* #0 in second position is alternative syntax for bfc, which is
6658 the same instruction but with REG_PC in the Rm field. */
6659 if (!inst
.operands
[1].isreg
)
6660 inst
.operands
[1].reg
= REG_PC
;
6662 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6663 constraint (msb
> 32, _("bit-field extends past end of register"));
6664 /* The instruction encoding stores the LSB and MSB,
6665 not the LSB and width. */
6666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6667 inst
.instruction
|= inst
.operands
[1].reg
;
6668 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6669 inst
.instruction
|= (msb
- 1) << 16;
6675 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6676 _("bit-field extends past end of register"));
6677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6678 inst
.instruction
|= inst
.operands
[1].reg
;
6679 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6680 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6683 /* ARM V5 breakpoint instruction (argument parse)
6684 BKPT <16 bit unsigned immediate>
6685 Instruction is not conditional.
6686 The bit pattern given in insns[] has the COND_ALWAYS condition,
6687 and it is an error if the caller tried to override that. */
6692 /* Top 12 of 16 bits to bits 19:8. */
6693 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6695 /* Bottom 4 of 16 bits to bits 3:0. */
6696 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6700 encode_branch (int default_reloc
)
6702 if (inst
.operands
[0].hasreloc
)
6704 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6705 _("the only suffix valid here is '(plt)'"));
6706 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6710 inst
.reloc
.type
= default_reloc
;
6712 inst
.reloc
.pc_rel
= 1;
6719 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6720 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6723 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6730 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6732 if (inst
.cond
== COND_ALWAYS
)
6733 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6735 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6739 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6742 /* ARM V5 branch-link-exchange instruction (argument parse)
6743 BLX <target_addr> ie BLX(1)
6744 BLX{<condition>} <Rm> ie BLX(2)
6745 Unfortunately, there are two different opcodes for this mnemonic.
6746 So, the insns[].value is not used, and the code here zaps values
6747 into inst.instruction.
6748 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6753 if (inst
.operands
[0].isreg
)
6755 /* Arg is a register; the opcode provided by insns[] is correct.
6756 It is not illegal to do "blx pc", just useless. */
6757 if (inst
.operands
[0].reg
== REG_PC
)
6758 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6760 inst
.instruction
|= inst
.operands
[0].reg
;
6764 /* Arg is an address; this instruction cannot be executed
6765 conditionally, and the opcode must be adjusted. */
6766 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6767 inst
.instruction
= 0xfa000000;
6769 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6770 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6773 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6780 bfd_boolean want_reloc
;
6782 if (inst
.operands
[0].reg
== REG_PC
)
6783 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6785 inst
.instruction
|= inst
.operands
[0].reg
;
6786 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6787 it is for ARMv4t or earlier. */
6788 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6789 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6793 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6798 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6802 /* ARM v5TEJ. Jump to Jazelle code. */
6807 if (inst
.operands
[0].reg
== REG_PC
)
6808 as_tsktsk (_("use of r15 in bxj is not really useful"));
6810 inst
.instruction
|= inst
.operands
[0].reg
;
6813 /* Co-processor data operation:
6814 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6815 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6819 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6820 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6821 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6822 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6823 inst
.instruction
|= inst
.operands
[4].reg
;
6824 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6830 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6831 encode_arm_shifter_operand (1);
6834 /* Transfer between coprocessor and ARM registers.
6835 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6840 No special properties. */
6845 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6846 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6847 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6848 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6849 inst
.instruction
|= inst
.operands
[4].reg
;
6850 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6853 /* Transfer between coprocessor register and pair of ARM registers.
6854 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6859 Two XScale instructions are special cases of these:
6861 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6862 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6864 Result unpredictable if Rd or Rn is R15. */
6869 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6870 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6871 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6872 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6873 inst
.instruction
|= inst
.operands
[4].reg
;
6879 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6880 if (inst
.operands
[1].present
)
6882 inst
.instruction
|= CPSI_MMOD
;
6883 inst
.instruction
|= inst
.operands
[1].imm
;
6890 inst
.instruction
|= inst
.operands
[0].imm
;
6896 /* There is no IT instruction in ARM mode. We
6897 process it but do not generate code for it. */
6904 int base_reg
= inst
.operands
[0].reg
;
6905 int range
= inst
.operands
[1].imm
;
6907 inst
.instruction
|= base_reg
<< 16;
6908 inst
.instruction
|= range
;
6910 if (inst
.operands
[1].writeback
)
6911 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6913 if (inst
.operands
[0].writeback
)
6915 inst
.instruction
|= WRITE_BACK
;
6916 /* Check for unpredictable uses of writeback. */
6917 if (inst
.instruction
& LOAD_BIT
)
6919 /* Not allowed in LDM type 2. */
6920 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6921 && ((range
& (1 << REG_PC
)) == 0))
6922 as_warn (_("writeback of base register is UNPREDICTABLE"));
6923 /* Only allowed if base reg not in list for other types. */
6924 else if (range
& (1 << base_reg
))
6925 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6929 /* Not allowed for type 2. */
6930 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6931 as_warn (_("writeback of base register is UNPREDICTABLE"));
6932 /* Only allowed if base reg not in list, or first in list. */
6933 else if ((range
& (1 << base_reg
))
6934 && (range
& ((1 << base_reg
) - 1)))
6935 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6940 /* ARMv5TE load-consecutive (argument parse)
6949 constraint (inst
.operands
[0].reg
% 2 != 0,
6950 _("first destination register must be even"));
6951 constraint (inst
.operands
[1].present
6952 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6953 _("can only load two consecutive registers"));
6954 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6955 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6957 if (!inst
.operands
[1].present
)
6958 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6960 if (inst
.instruction
& LOAD_BIT
)
6962 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6963 register and the first register written; we have to diagnose
6964 overlap between the base and the second register written here. */
6966 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6967 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6968 as_warn (_("base register written back, and overlaps "
6969 "second destination register"));
6971 /* For an index-register load, the index register must not overlap the
6972 destination (even if not write-back). */
6973 else if (inst
.operands
[2].immisreg
6974 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6975 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6976 as_warn (_("index register overlaps destination register"));
6979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6980 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6986 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6987 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6988 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6989 || inst
.operands
[1].negative
6990 /* This can arise if the programmer has written
6992 or if they have mistakenly used a register name as the last
6995 It is very difficult to distinguish between these two cases
6996 because "rX" might actually be a label. ie the register
6997 name has been occluded by a symbol of the same name. So we
6998 just generate a general 'bad addressing mode' type error
6999 message and leave it up to the programmer to discover the
7000 true cause and fix their mistake. */
7001 || (inst
.operands
[1].reg
== REG_PC
),
7004 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7005 || inst
.reloc
.exp
.X_add_number
!= 0,
7006 _("offset must be zero in ARM encoding"));
7008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7009 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7010 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7016 constraint (inst
.operands
[0].reg
% 2 != 0,
7017 _("even register required"));
7018 constraint (inst
.operands
[1].present
7019 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7020 _("can only load two consecutive registers"));
7021 /* If op 1 were present and equal to PC, this function wouldn't
7022 have been called in the first place. */
7023 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7026 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7033 if (!inst
.operands
[1].isreg
)
7034 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7036 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7042 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7044 if (inst
.operands
[1].preind
)
7046 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7047 || inst
.reloc
.exp
.X_add_number
!= 0,
7048 _("this instruction requires a post-indexed address"));
7050 inst
.operands
[1].preind
= 0;
7051 inst
.operands
[1].postind
= 1;
7052 inst
.operands
[1].writeback
= 1;
7054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7055 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7058 /* Halfword and signed-byte load/store operations. */
7063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7064 if (!inst
.operands
[1].isreg
)
7065 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7067 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7073 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7075 if (inst
.operands
[1].preind
)
7077 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7078 || inst
.reloc
.exp
.X_add_number
!= 0,
7079 _("this instruction requires a post-indexed address"));
7081 inst
.operands
[1].preind
= 0;
7082 inst
.operands
[1].postind
= 1;
7083 inst
.operands
[1].writeback
= 1;
7085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7086 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7089 /* Co-processor register load/store.
7090 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7094 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7095 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7096 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7102 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7103 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7104 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7105 && !(inst
.instruction
& 0x00400000))
7106 as_tsktsk (_("Rd and Rm should be different in mla"));
7108 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7109 inst
.instruction
|= inst
.operands
[1].reg
;
7110 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7111 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7118 encode_arm_shifter_operand (1);
7121 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7128 top
= (inst
.instruction
& 0x00400000) != 0;
7129 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7130 _(":lower16: not allowed this instruction"));
7131 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7132 _(":upper16: not allowed instruction"));
7133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7134 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7136 imm
= inst
.reloc
.exp
.X_add_number
;
7137 /* The value is in two pieces: 0:11, 16:19. */
7138 inst
.instruction
|= (imm
& 0x00000fff);
7139 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7143 static void do_vfp_nsyn_opcode (const char *);
7146 do_vfp_nsyn_mrs (void)
7148 if (inst
.operands
[0].isvec
)
7150 if (inst
.operands
[1].reg
!= 1)
7151 first_error (_("operand 1 must be FPSCR"));
7152 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7153 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7154 do_vfp_nsyn_opcode ("fmstat");
7156 else if (inst
.operands
[1].isvec
)
7157 do_vfp_nsyn_opcode ("fmrx");
7165 do_vfp_nsyn_msr (void)
7167 if (inst
.operands
[0].isvec
)
7168 do_vfp_nsyn_opcode ("fmxr");
7178 if (do_vfp_nsyn_mrs () == SUCCESS
)
7181 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7182 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7184 _("'CPSR' or 'SPSR' expected"));
7185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7186 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7189 /* Two possible forms:
7190 "{C|S}PSR_<field>, Rm",
7191 "{C|S}PSR_f, #expression". */
7196 if (do_vfp_nsyn_msr () == SUCCESS
)
7199 inst
.instruction
|= inst
.operands
[0].imm
;
7200 if (inst
.operands
[1].isreg
)
7201 inst
.instruction
|= inst
.operands
[1].reg
;
7204 inst
.instruction
|= INST_IMMEDIATE
;
7205 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7206 inst
.reloc
.pc_rel
= 0;
7213 if (!inst
.operands
[2].present
)
7214 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7215 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7216 inst
.instruction
|= inst
.operands
[1].reg
;
7217 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7219 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7220 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7221 as_tsktsk (_("Rd and Rm should be different in mul"));
7224 /* Long Multiply Parser
7225 UMULL RdLo, RdHi, Rm, Rs
7226 SMULL RdLo, RdHi, Rm, Rs
7227 UMLAL RdLo, RdHi, Rm, Rs
7228 SMLAL RdLo, RdHi, Rm, Rs. */
7233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7234 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7235 inst
.instruction
|= inst
.operands
[2].reg
;
7236 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7238 /* rdhi and rdlo must be different. */
7239 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7240 as_tsktsk (_("rdhi and rdlo must be different"));
7242 /* rdhi, rdlo and rm must all be different before armv6. */
7243 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7244 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7245 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7246 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7252 if (inst
.operands
[0].present
)
7254 /* Architectural NOP hints are CPSR sets with no bits selected. */
7255 inst
.instruction
&= 0xf0000000;
7256 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7260 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7261 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7262 Condition defaults to COND_ALWAYS.
7263 Error if Rd, Rn or Rm are R15. */
7268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7270 inst
.instruction
|= inst
.operands
[2].reg
;
7271 if (inst
.operands
[3].present
)
7272 encode_arm_shift (3);
7275 /* ARM V6 PKHTB (Argument Parse). */
7280 if (!inst
.operands
[3].present
)
7282 /* If the shift specifier is omitted, turn the instruction
7283 into pkhbt rd, rm, rn. */
7284 inst
.instruction
&= 0xfff00010;
7285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7286 inst
.instruction
|= inst
.operands
[1].reg
;
7287 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7293 inst
.instruction
|= inst
.operands
[2].reg
;
7294 encode_arm_shift (3);
7298 /* ARMv5TE: Preload-Cache
7302 Syntactically, like LDR with B=1, W=0, L=1. */
7307 constraint (!inst
.operands
[0].isreg
,
7308 _("'[' expected after PLD mnemonic"));
7309 constraint (inst
.operands
[0].postind
,
7310 _("post-indexed expression used in preload instruction"));
7311 constraint (inst
.operands
[0].writeback
,
7312 _("writeback used in preload instruction"));
7313 constraint (!inst
.operands
[0].preind
,
7314 _("unindexed addressing used in preload instruction"));
7315 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7318 /* ARMv7: PLI <addr_mode> */
7322 constraint (!inst
.operands
[0].isreg
,
7323 _("'[' expected after PLI mnemonic"));
7324 constraint (inst
.operands
[0].postind
,
7325 _("post-indexed expression used in preload instruction"));
7326 constraint (inst
.operands
[0].writeback
,
7327 _("writeback used in preload instruction"));
7328 constraint (!inst
.operands
[0].preind
,
7329 _("unindexed addressing used in preload instruction"));
7330 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7331 inst
.instruction
&= ~PRE_INDEX
;
7337 inst
.operands
[1] = inst
.operands
[0];
7338 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7339 inst
.operands
[0].isreg
= 1;
7340 inst
.operands
[0].writeback
= 1;
7341 inst
.operands
[0].reg
= REG_SP
;
7345 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7346 word at the specified address and the following word
7348 Unconditionally executed.
7349 Error if Rn is R15. */
7354 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7355 if (inst
.operands
[0].writeback
)
7356 inst
.instruction
|= WRITE_BACK
;
7359 /* ARM V6 ssat (argument parse). */
7364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7365 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7366 inst
.instruction
|= inst
.operands
[2].reg
;
7368 if (inst
.operands
[3].present
)
7369 encode_arm_shift (3);
7372 /* ARM V6 usat (argument parse). */
7377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7378 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7379 inst
.instruction
|= inst
.operands
[2].reg
;
7381 if (inst
.operands
[3].present
)
7382 encode_arm_shift (3);
7385 /* ARM V6 ssat16 (argument parse). */
7390 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7391 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7392 inst
.instruction
|= inst
.operands
[2].reg
;
7398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7399 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7400 inst
.instruction
|= inst
.operands
[2].reg
;
7403 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7404 preserving the other bits.
7406 setend <endian_specifier>, where <endian_specifier> is either
7412 if (inst
.operands
[0].imm
)
7413 inst
.instruction
|= 0x200;
7419 unsigned int Rm
= (inst
.operands
[1].present
7420 ? inst
.operands
[1].reg
7421 : inst
.operands
[0].reg
);
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7424 inst
.instruction
|= Rm
;
7425 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7427 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7428 inst
.instruction
|= SHIFT_BY_REG
;
7431 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7437 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7438 inst
.reloc
.pc_rel
= 0;
7444 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7445 inst
.reloc
.pc_rel
= 0;
7448 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7449 SMLAxy{cond} Rd,Rm,Rs,Rn
7450 SMLAWy{cond} Rd,Rm,Rs,Rn
7451 Error if any register is R15. */
7456 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7457 inst
.instruction
|= inst
.operands
[1].reg
;
7458 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7459 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7462 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7463 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7464 Error if any register is R15.
7465 Warning if Rdlo == Rdhi. */
7470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7471 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7472 inst
.instruction
|= inst
.operands
[2].reg
;
7473 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7475 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7476 as_tsktsk (_("rdhi and rdlo must be different"));
7479 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7480 SMULxy{cond} Rd,Rm,Rs
7481 Error if any register is R15. */
7486 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7487 inst
.instruction
|= inst
.operands
[1].reg
;
7488 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7491 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7492 the same for both ARM and Thumb-2. */
7499 if (inst
.operands
[0].present
)
7501 reg
= inst
.operands
[0].reg
;
7502 constraint (reg
!= 13, _("SRS base register must be r13"));
7507 inst
.instruction
|= reg
<< 16;
7508 inst
.instruction
|= inst
.operands
[1].imm
;
7509 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7510 inst
.instruction
|= WRITE_BACK
;
7513 /* ARM V6 strex (argument parse). */
7518 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7519 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7520 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7521 || inst
.operands
[2].negative
7522 /* See comment in do_ldrex(). */
7523 || (inst
.operands
[2].reg
== REG_PC
),
7526 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7527 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7529 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7530 || inst
.reloc
.exp
.X_add_number
!= 0,
7531 _("offset must be zero in ARM encoding"));
7533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7534 inst
.instruction
|= inst
.operands
[1].reg
;
7535 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7536 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7542 constraint (inst
.operands
[1].reg
% 2 != 0,
7543 _("even register required"));
7544 constraint (inst
.operands
[2].present
7545 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7546 _("can only store two consecutive registers"));
7547 /* If op 2 were present and equal to PC, this function wouldn't
7548 have been called in the first place. */
7549 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7551 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7552 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7553 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7557 inst
.instruction
|= inst
.operands
[1].reg
;
7558 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7561 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7562 extends it to 32-bits, and adds the result to a value in another
7563 register. You can specify a rotation by 0, 8, 16, or 24 bits
7564 before extracting the 16-bit value.
7565 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7566 Condition defaults to COND_ALWAYS.
7567 Error if any register uses R15. */
7572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7574 inst
.instruction
|= inst
.operands
[2].reg
;
7575 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7580 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7581 Condition defaults to COND_ALWAYS.
7582 Error if any register uses R15. */
7587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7588 inst
.instruction
|= inst
.operands
[1].reg
;
7589 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7592 /* VFP instructions. In a logical order: SP variant first, monad
7593 before dyad, arithmetic then move then load/store. */
7596 do_vfp_sp_monadic (void)
7598 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7599 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7603 do_vfp_sp_dyadic (void)
7605 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7606 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7607 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7611 do_vfp_sp_compare_z (void)
7613 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7617 do_vfp_dp_sp_cvt (void)
7619 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7620 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7624 do_vfp_sp_dp_cvt (void)
7626 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7627 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7631 do_vfp_reg_from_sp (void)
7633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7634 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7638 do_vfp_reg2_from_sp2 (void)
7640 constraint (inst
.operands
[2].imm
!= 2,
7641 _("only two consecutive VFP SP registers allowed here"));
7642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7643 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7644 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7648 do_vfp_sp_from_reg (void)
7650 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7651 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7655 do_vfp_sp2_from_reg2 (void)
7657 constraint (inst
.operands
[0].imm
!= 2,
7658 _("only two consecutive VFP SP registers allowed here"));
7659 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7660 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7661 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7665 do_vfp_sp_ldst (void)
7667 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7668 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7672 do_vfp_dp_ldst (void)
7674 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7675 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7680 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7682 if (inst
.operands
[0].writeback
)
7683 inst
.instruction
|= WRITE_BACK
;
7685 constraint (ldstm_type
!= VFP_LDSTMIA
,
7686 _("this addressing mode requires base-register writeback"));
7687 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7689 inst
.instruction
|= inst
.operands
[1].imm
;
7693 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7697 if (inst
.operands
[0].writeback
)
7698 inst
.instruction
|= WRITE_BACK
;
7700 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7701 _("this addressing mode requires base-register writeback"));
7703 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7704 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7706 count
= inst
.operands
[1].imm
<< 1;
7707 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7710 inst
.instruction
|= count
;
7714 do_vfp_sp_ldstmia (void)
7716 vfp_sp_ldstm (VFP_LDSTMIA
);
7720 do_vfp_sp_ldstmdb (void)
7722 vfp_sp_ldstm (VFP_LDSTMDB
);
7726 do_vfp_dp_ldstmia (void)
7728 vfp_dp_ldstm (VFP_LDSTMIA
);
7732 do_vfp_dp_ldstmdb (void)
7734 vfp_dp_ldstm (VFP_LDSTMDB
);
7738 do_vfp_xp_ldstmia (void)
7740 vfp_dp_ldstm (VFP_LDSTMIAX
);
7744 do_vfp_xp_ldstmdb (void)
7746 vfp_dp_ldstm (VFP_LDSTMDBX
);
7750 do_vfp_dp_rd_rm (void)
7752 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7753 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7757 do_vfp_dp_rn_rd (void)
7759 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7760 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7764 do_vfp_dp_rd_rn (void)
7766 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7767 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7771 do_vfp_dp_rd_rn_rm (void)
7773 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7774 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7775 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7785 do_vfp_dp_rm_rd_rn (void)
7787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7788 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7789 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7792 /* VFPv3 instructions. */
7794 do_vfp_sp_const (void)
7796 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7797 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7798 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7802 do_vfp_dp_const (void)
7804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7805 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7806 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7810 vfp_conv (int srcsize
)
7812 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7813 inst
.instruction
|= (immbits
& 1) << 5;
7814 inst
.instruction
|= (immbits
>> 1);
7818 do_vfp_sp_conv_16 (void)
7820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7825 do_vfp_dp_conv_16 (void)
7827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7832 do_vfp_sp_conv_32 (void)
7834 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7839 do_vfp_dp_conv_32 (void)
7841 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7845 /* FPA instructions. Also in a logical order. */
7850 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7851 inst
.instruction
|= inst
.operands
[1].reg
;
7855 do_fpa_ldmstm (void)
7857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7858 switch (inst
.operands
[1].imm
)
7860 case 1: inst
.instruction
|= CP_T_X
; break;
7861 case 2: inst
.instruction
|= CP_T_Y
; break;
7862 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7867 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7869 /* The instruction specified "ea" or "fd", so we can only accept
7870 [Rn]{!}. The instruction does not really support stacking or
7871 unstacking, so we have to emulate these by setting appropriate
7872 bits and offsets. */
7873 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7874 || inst
.reloc
.exp
.X_add_number
!= 0,
7875 _("this instruction does not support indexing"));
7877 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7878 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7880 if (!(inst
.instruction
& INDEX_UP
))
7881 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7883 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7885 inst
.operands
[2].preind
= 0;
7886 inst
.operands
[2].postind
= 1;
7890 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7893 /* iWMMXt instructions: strictly in alphabetical order. */
7896 do_iwmmxt_tandorc (void)
7898 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7902 do_iwmmxt_textrc (void)
7904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7905 inst
.instruction
|= inst
.operands
[1].imm
;
7909 do_iwmmxt_textrm (void)
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7913 inst
.instruction
|= inst
.operands
[2].imm
;
7917 do_iwmmxt_tinsr (void)
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7920 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7921 inst
.instruction
|= inst
.operands
[2].imm
;
7925 do_iwmmxt_tmia (void)
7927 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7928 inst
.instruction
|= inst
.operands
[1].reg
;
7929 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7933 do_iwmmxt_waligni (void)
7935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7937 inst
.instruction
|= inst
.operands
[2].reg
;
7938 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7942 do_iwmmxt_wmerge (void)
7944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7945 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7946 inst
.instruction
|= inst
.operands
[2].reg
;
7947 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7951 do_iwmmxt_wmov (void)
7953 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7956 inst
.instruction
|= inst
.operands
[1].reg
;
7960 do_iwmmxt_wldstbh (void)
7963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7965 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7967 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7968 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7972 do_iwmmxt_wldstw (void)
7974 /* RIWR_RIWC clears .isreg for a control register. */
7975 if (!inst
.operands
[0].isreg
)
7977 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7978 inst
.instruction
|= 0xf0000000;
7981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7982 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7986 do_iwmmxt_wldstd (void)
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7990 && inst
.operands
[1].immisreg
)
7992 inst
.instruction
&= ~0x1a000ff;
7993 inst
.instruction
|= (0xf << 28);
7994 if (inst
.operands
[1].preind
)
7995 inst
.instruction
|= PRE_INDEX
;
7996 if (!inst
.operands
[1].negative
)
7997 inst
.instruction
|= INDEX_UP
;
7998 if (inst
.operands
[1].writeback
)
7999 inst
.instruction
|= WRITE_BACK
;
8000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8001 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8002 inst
.instruction
|= inst
.operands
[1].imm
;
8005 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8009 do_iwmmxt_wshufh (void)
8011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8013 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8014 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8018 do_iwmmxt_wzero (void)
8020 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8021 inst
.instruction
|= inst
.operands
[0].reg
;
8022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8027 do_iwmmxt_wrwrwr_or_imm5 (void)
8029 if (inst
.operands
[2].isreg
)
8032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8033 _("immediate operand requires iWMMXt2"));
8035 if (inst
.operands
[2].imm
== 0)
8037 switch ((inst
.instruction
>> 20) & 0xf)
8043 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8044 inst
.operands
[2].imm
= 16;
8045 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8051 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8052 inst
.operands
[2].imm
= 32;
8053 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8060 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8062 wrn
= (inst
.instruction
>> 16) & 0xf;
8063 inst
.instruction
&= 0xff0fff0f;
8064 inst
.instruction
|= wrn
;
8065 /* Bail out here; the instruction is now assembled. */
8070 /* Map 32 -> 0, etc. */
8071 inst
.operands
[2].imm
&= 0x1f;
8072 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8076 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8077 operations first, then control, shift, and load/store. */
8079 /* Insns like "foo X,Y,Z". */
8082 do_mav_triple (void)
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8085 inst
.instruction
|= inst
.operands
[1].reg
;
8086 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8089 /* Insns like "foo W,X,Y,Z".
8090 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8095 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8097 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8098 inst
.instruction
|= inst
.operands
[3].reg
;
8101 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8105 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8108 /* Maverick shift immediate instructions.
8109 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8110 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8115 int imm
= inst
.operands
[2].imm
;
8117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8120 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8121 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8122 Bit 4 should be 0. */
8123 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8125 inst
.instruction
|= imm
;
8128 /* XScale instructions. Also sorted arithmetic before move. */
8130 /* Xscale multiply-accumulate (argument parse)
8133 MIAxycc acc0,Rm,Rs. */
8138 inst
.instruction
|= inst
.operands
[1].reg
;
8139 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8142 /* Xscale move-accumulator-register (argument parse)
8144 MARcc acc0,RdLo,RdHi. */
8149 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8150 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8153 /* Xscale move-register-accumulator (argument parse)
8155 MRAcc RdLo,RdHi,acc0. */
8160 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8165 /* Encoding functions relevant only to Thumb. */
8167 /* inst.operands[i] is a shifted-register operand; encode
8168 it into inst.instruction in the format used by Thumb32. */
8171 encode_thumb32_shifted_operand (int i
)
8173 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8174 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8176 constraint (inst
.operands
[i
].immisreg
,
8177 _("shift by register not allowed in thumb mode"));
8178 inst
.instruction
|= inst
.operands
[i
].reg
;
8179 if (shift
== SHIFT_RRX
)
8180 inst
.instruction
|= SHIFT_ROR
<< 4;
8183 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8184 _("expression too complex"));
8186 constraint (value
> 32
8187 || (value
== 32 && (shift
== SHIFT_LSL
8188 || shift
== SHIFT_ROR
)),
8189 _("shift expression is too large"));
8193 else if (value
== 32)
8196 inst
.instruction
|= shift
<< 4;
8197 inst
.instruction
|= (value
& 0x1c) << 10;
8198 inst
.instruction
|= (value
& 0x03) << 6;
8203 /* inst.operands[i] was set up by parse_address. Encode it into a
8204 Thumb32 format load or store instruction. Reject forms that cannot
8205 be used with such instructions. If is_t is true, reject forms that
8206 cannot be used with a T instruction; if is_d is true, reject forms
8207 that cannot be used with a D instruction. */
8210 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8212 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8214 constraint (!inst
.operands
[i
].isreg
,
8215 _("Instruction does not support =N addresses"));
8217 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8218 if (inst
.operands
[i
].immisreg
)
8220 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8221 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8222 constraint (inst
.operands
[i
].negative
,
8223 _("Thumb does not support negative register indexing"));
8224 constraint (inst
.operands
[i
].postind
,
8225 _("Thumb does not support register post-indexing"));
8226 constraint (inst
.operands
[i
].writeback
,
8227 _("Thumb does not support register indexing with writeback"));
8228 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8229 _("Thumb supports only LSL in shifted register indexing"));
8231 inst
.instruction
|= inst
.operands
[i
].imm
;
8232 if (inst
.operands
[i
].shifted
)
8234 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8235 _("expression too complex"));
8236 constraint (inst
.reloc
.exp
.X_add_number
< 0
8237 || inst
.reloc
.exp
.X_add_number
> 3,
8238 _("shift out of range"));
8239 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8241 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8243 else if (inst
.operands
[i
].preind
)
8245 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8246 _("cannot use writeback with PC-relative addressing"));
8247 constraint (is_t
&& inst
.operands
[i
].writeback
,
8248 _("cannot use writeback with this instruction"));
8252 inst
.instruction
|= 0x01000000;
8253 if (inst
.operands
[i
].writeback
)
8254 inst
.instruction
|= 0x00200000;
8258 inst
.instruction
|= 0x00000c00;
8259 if (inst
.operands
[i
].writeback
)
8260 inst
.instruction
|= 0x00000100;
8262 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8264 else if (inst
.operands
[i
].postind
)
8266 assert (inst
.operands
[i
].writeback
);
8267 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8268 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8271 inst
.instruction
|= 0x00200000;
8273 inst
.instruction
|= 0x00000900;
8274 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8276 else /* unindexed - only for coprocessor */
8277 inst
.error
= _("instruction does not accept unindexed addressing");
8280 /* Table of Thumb instructions which exist in both 16- and 32-bit
8281 encodings (the latter only in post-V6T2 cores). The index is the
8282 value used in the insns table below. When there is more than one
8283 possible 16-bit encoding for the instruction, this table always
8285 Also contains several pseudo-instructions used during relaxation. */
8286 #define T16_32_TAB \
8287 X(adc, 4140, eb400000), \
8288 X(adcs, 4140, eb500000), \
8289 X(add, 1c00, eb000000), \
8290 X(adds, 1c00, eb100000), \
8291 X(addi, 0000, f1000000), \
8292 X(addis, 0000, f1100000), \
8293 X(add_pc,000f, f20f0000), \
8294 X(add_sp,000d, f10d0000), \
8295 X(adr, 000f, f20f0000), \
8296 X(and, 4000, ea000000), \
8297 X(ands, 4000, ea100000), \
8298 X(asr, 1000, fa40f000), \
8299 X(asrs, 1000, fa50f000), \
8300 X(b, e000, f000b000), \
8301 X(bcond, d000, f0008000), \
8302 X(bic, 4380, ea200000), \
8303 X(bics, 4380, ea300000), \
8304 X(cmn, 42c0, eb100f00), \
8305 X(cmp, 2800, ebb00f00), \
8306 X(cpsie, b660, f3af8400), \
8307 X(cpsid, b670, f3af8600), \
8308 X(cpy, 4600, ea4f0000), \
8309 X(dec_sp,80dd, f1ad0d00), \
8310 X(eor, 4040, ea800000), \
8311 X(eors, 4040, ea900000), \
8312 X(inc_sp,00dd, f10d0d00), \
8313 X(ldmia, c800, e8900000), \
8314 X(ldr, 6800, f8500000), \
8315 X(ldrb, 7800, f8100000), \
8316 X(ldrh, 8800, f8300000), \
8317 X(ldrsb, 5600, f9100000), \
8318 X(ldrsh, 5e00, f9300000), \
8319 X(ldr_pc,4800, f85f0000), \
8320 X(ldr_pc2,4800, f85f0000), \
8321 X(ldr_sp,9800, f85d0000), \
8322 X(lsl, 0000, fa00f000), \
8323 X(lsls, 0000, fa10f000), \
8324 X(lsr, 0800, fa20f000), \
8325 X(lsrs, 0800, fa30f000), \
8326 X(mov, 2000, ea4f0000), \
8327 X(movs, 2000, ea5f0000), \
8328 X(mul, 4340, fb00f000), \
8329 X(muls, 4340, ffffffff), /* no 32b muls */ \
8330 X(mvn, 43c0, ea6f0000), \
8331 X(mvns, 43c0, ea7f0000), \
8332 X(neg, 4240, f1c00000), /* rsb #0 */ \
8333 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8334 X(orr, 4300, ea400000), \
8335 X(orrs, 4300, ea500000), \
8336 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8337 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8338 X(rev, ba00, fa90f080), \
8339 X(rev16, ba40, fa90f090), \
8340 X(revsh, bac0, fa90f0b0), \
8341 X(ror, 41c0, fa60f000), \
8342 X(rors, 41c0, fa70f000), \
8343 X(sbc, 4180, eb600000), \
8344 X(sbcs, 4180, eb700000), \
8345 X(stmia, c000, e8800000), \
8346 X(str, 6000, f8400000), \
8347 X(strb, 7000, f8000000), \
8348 X(strh, 8000, f8200000), \
8349 X(str_sp,9000, f84d0000), \
8350 X(sub, 1e00, eba00000), \
8351 X(subs, 1e00, ebb00000), \
8352 X(subi, 8000, f1a00000), \
8353 X(subis, 8000, f1b00000), \
8354 X(sxtb, b240, fa4ff080), \
8355 X(sxth, b200, fa0ff080), \
8356 X(tst, 4200, ea100f00), \
8357 X(uxtb, b2c0, fa5ff080), \
8358 X(uxth, b280, fa1ff080), \
8359 X(nop, bf00, f3af8000), \
8360 X(yield, bf10, f3af8001), \
8361 X(wfe, bf20, f3af8002), \
8362 X(wfi, bf30, f3af8003), \
8363 X(sev, bf40, f3af9004), /* typo, 8004? */
8365 /* To catch errors in encoding functions, the codes are all offset by
8366 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8367 as 16-bit instructions. */
8368 #define X(a,b,c) T_MNEM_##a
8369 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8372 #define X(a,b,c) 0x##b
8373 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8374 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8377 #define X(a,b,c) 0x##c
8378 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8379 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8380 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8384 /* Thumb instruction encoders, in alphabetical order. */
8388 do_t_add_sub_w (void)
8392 Rd
= inst
.operands
[0].reg
;
8393 Rn
= inst
.operands
[1].reg
;
8395 constraint (Rd
== 15, _("PC not allowed as destination"));
8396 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8397 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8400 /* Parse an add or subtract instruction. We get here with inst.instruction
8401 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8408 Rd
= inst
.operands
[0].reg
;
8409 Rs
= (inst
.operands
[1].present
8410 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8411 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8419 flags
= (inst
.instruction
== T_MNEM_adds
8420 || inst
.instruction
== T_MNEM_subs
);
8422 narrow
= (current_it_mask
== 0);
8424 narrow
= (current_it_mask
!= 0);
8425 if (!inst
.operands
[2].isreg
)
8429 add
= (inst
.instruction
== T_MNEM_add
8430 || inst
.instruction
== T_MNEM_adds
);
8432 if (inst
.size_req
!= 4)
8434 /* Attempt to use a narrow opcode, with relaxation if
8436 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8437 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8438 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8439 opcode
= T_MNEM_add_sp
;
8440 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8441 opcode
= T_MNEM_add_pc
;
8442 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8445 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8447 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8451 inst
.instruction
= THUMB_OP16(opcode
);
8452 inst
.instruction
|= (Rd
<< 4) | Rs
;
8453 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8454 if (inst
.size_req
!= 2)
8455 inst
.relax
= opcode
;
8458 constraint (inst
.size_req
== 2, BAD_HIREG
);
8460 if (inst
.size_req
== 4
8461 || (inst
.size_req
!= 2 && !opcode
))
8465 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8466 _("only SUBS PC, LR, #const allowed"));
8467 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8468 _("expression too complex"));
8469 constraint (inst
.reloc
.exp
.X_add_number
< 0
8470 || inst
.reloc
.exp
.X_add_number
> 0xff,
8471 _("immediate value out of range"));
8472 inst
.instruction
= T2_SUBS_PC_LR
8473 | inst
.reloc
.exp
.X_add_number
;
8474 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8477 else if (Rs
== REG_PC
)
8479 /* Always use addw/subw. */
8480 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8481 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8485 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8486 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8489 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8491 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8493 inst
.instruction
|= Rd
<< 8;
8494 inst
.instruction
|= Rs
<< 16;
8499 Rn
= inst
.operands
[2].reg
;
8500 /* See if we can do this with a 16-bit instruction. */
8501 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8503 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8508 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8509 || inst
.instruction
== T_MNEM_add
)
8512 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8516 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8518 /* Thumb-1 cores (except v6-M) require at least one high
8519 register in a narrow non flag setting add. */
8520 if (Rd
> 7 || Rn
> 7
8521 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8522 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8529 inst
.instruction
= T_OPCODE_ADD_HI
;
8530 inst
.instruction
|= (Rd
& 8) << 4;
8531 inst
.instruction
|= (Rd
& 7);
8532 inst
.instruction
|= Rn
<< 3;
8537 /* If we get here, it can't be done in 16 bits. */
8538 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8539 _("shift must be constant"));
8540 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8541 inst
.instruction
|= Rd
<< 8;
8542 inst
.instruction
|= Rs
<< 16;
8543 encode_thumb32_shifted_operand (2);
8548 constraint (inst
.instruction
== T_MNEM_adds
8549 || inst
.instruction
== T_MNEM_subs
,
8552 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8554 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8555 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8558 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8560 inst
.instruction
|= (Rd
<< 4) | Rs
;
8561 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8565 Rn
= inst
.operands
[2].reg
;
8566 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8568 /* We now have Rd, Rs, and Rn set to registers. */
8569 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8571 /* Can't do this for SUB. */
8572 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8573 inst
.instruction
= T_OPCODE_ADD_HI
;
8574 inst
.instruction
|= (Rd
& 8) << 4;
8575 inst
.instruction
|= (Rd
& 7);
8577 inst
.instruction
|= Rn
<< 3;
8579 inst
.instruction
|= Rs
<< 3;
8581 constraint (1, _("dest must overlap one source register"));
8585 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8586 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8587 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8595 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8597 /* Defer to section relaxation. */
8598 inst
.relax
= inst
.instruction
;
8599 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8600 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8602 else if (unified_syntax
&& inst
.size_req
!= 2)
8604 /* Generate a 32-bit opcode. */
8605 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8606 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8607 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8608 inst
.reloc
.pc_rel
= 1;
8612 /* Generate a 16-bit opcode. */
8613 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8614 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8615 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8616 inst
.reloc
.pc_rel
= 1;
8618 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8622 /* Arithmetic instructions for which there is just one 16-bit
8623 instruction encoding, and it allows only two low registers.
8624 For maximal compatibility with ARM syntax, we allow three register
8625 operands even when Thumb-32 instructions are not available, as long
8626 as the first two are identical. For instance, both "sbc r0,r1" and
8627 "sbc r0,r0,r1" are allowed. */
8633 Rd
= inst
.operands
[0].reg
;
8634 Rs
= (inst
.operands
[1].present
8635 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8636 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8637 Rn
= inst
.operands
[2].reg
;
8641 if (!inst
.operands
[2].isreg
)
8643 /* For an immediate, we always generate a 32-bit opcode;
8644 section relaxation will shrink it later if possible. */
8645 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8646 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8647 inst
.instruction
|= Rd
<< 8;
8648 inst
.instruction
|= Rs
<< 16;
8649 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8655 /* See if we can do this with a 16-bit instruction. */
8656 if (THUMB_SETS_FLAGS (inst
.instruction
))
8657 narrow
= current_it_mask
== 0;
8659 narrow
= current_it_mask
!= 0;
8661 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8663 if (inst
.operands
[2].shifted
)
8665 if (inst
.size_req
== 4)
8671 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8672 inst
.instruction
|= Rd
;
8673 inst
.instruction
|= Rn
<< 3;
8677 /* If we get here, it can't be done in 16 bits. */
8678 constraint (inst
.operands
[2].shifted
8679 && inst
.operands
[2].immisreg
,
8680 _("shift must be constant"));
8681 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8682 inst
.instruction
|= Rd
<< 8;
8683 inst
.instruction
|= Rs
<< 16;
8684 encode_thumb32_shifted_operand (2);
8689 /* On its face this is a lie - the instruction does set the
8690 flags. However, the only supported mnemonic in this mode
8692 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8694 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8695 _("unshifted register required"));
8696 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8697 constraint (Rd
!= Rs
,
8698 _("dest and source1 must be the same register"));
8700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8701 inst
.instruction
|= Rd
;
8702 inst
.instruction
|= Rn
<< 3;
8706 /* Similarly, but for instructions where the arithmetic operation is
8707 commutative, so we can allow either of them to be different from
8708 the destination operand in a 16-bit instruction. For instance, all
8709 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8716 Rd
= inst
.operands
[0].reg
;
8717 Rs
= (inst
.operands
[1].present
8718 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8719 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8720 Rn
= inst
.operands
[2].reg
;
8724 if (!inst
.operands
[2].isreg
)
8726 /* For an immediate, we always generate a 32-bit opcode;
8727 section relaxation will shrink it later if possible. */
8728 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8729 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8730 inst
.instruction
|= Rd
<< 8;
8731 inst
.instruction
|= Rs
<< 16;
8732 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8738 /* See if we can do this with a 16-bit instruction. */
8739 if (THUMB_SETS_FLAGS (inst
.instruction
))
8740 narrow
= current_it_mask
== 0;
8742 narrow
= current_it_mask
!= 0;
8744 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8746 if (inst
.operands
[2].shifted
)
8748 if (inst
.size_req
== 4)
8755 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8756 inst
.instruction
|= Rd
;
8757 inst
.instruction
|= Rn
<< 3;
8762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8763 inst
.instruction
|= Rd
;
8764 inst
.instruction
|= Rs
<< 3;
8769 /* If we get here, it can't be done in 16 bits. */
8770 constraint (inst
.operands
[2].shifted
8771 && inst
.operands
[2].immisreg
,
8772 _("shift must be constant"));
8773 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8774 inst
.instruction
|= Rd
<< 8;
8775 inst
.instruction
|= Rs
<< 16;
8776 encode_thumb32_shifted_operand (2);
8781 /* On its face this is a lie - the instruction does set the
8782 flags. However, the only supported mnemonic in this mode
8784 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8786 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8787 _("unshifted register required"));
8788 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8790 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8791 inst
.instruction
|= Rd
;
8794 inst
.instruction
|= Rn
<< 3;
8796 inst
.instruction
|= Rs
<< 3;
8798 constraint (1, _("dest must overlap one source register"));
8805 if (inst
.operands
[0].present
)
8807 constraint ((inst
.instruction
& 0xf0) != 0x40
8808 && inst
.operands
[0].imm
!= 0xf,
8809 _("bad barrier type"));
8810 inst
.instruction
|= inst
.operands
[0].imm
;
8813 inst
.instruction
|= 0xf;
8819 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8820 constraint (msb
> 32, _("bit-field extends past end of register"));
8821 /* The instruction encoding stores the LSB and MSB,
8822 not the LSB and width. */
8823 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8824 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8825 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8826 inst
.instruction
|= msb
- 1;
8834 /* #0 in second position is alternative syntax for bfc, which is
8835 the same instruction but with REG_PC in the Rm field. */
8836 if (!inst
.operands
[1].isreg
)
8837 inst
.operands
[1].reg
= REG_PC
;
8839 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8840 constraint (msb
> 32, _("bit-field extends past end of register"));
8841 /* The instruction encoding stores the LSB and MSB,
8842 not the LSB and width. */
8843 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8844 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8845 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8846 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8847 inst
.instruction
|= msb
- 1;
8853 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8854 _("bit-field extends past end of register"));
8855 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8856 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8857 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8858 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8859 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8862 /* ARM V5 Thumb BLX (argument parse)
8863 BLX <target_addr> which is BLX(1)
8864 BLX <Rm> which is BLX(2)
8865 Unfortunately, there are two different opcodes for this mnemonic.
8866 So, the insns[].value is not used, and the code here zaps values
8867 into inst.instruction.
8869 ??? How to take advantage of the additional two bits of displacement
8870 available in Thumb32 mode? Need new relocation? */
8875 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8876 if (inst
.operands
[0].isreg
)
8877 /* We have a register, so this is BLX(2). */
8878 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8881 /* No register. This must be BLX(1). */
8882 inst
.instruction
= 0xf000e800;
8884 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8885 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8888 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8889 inst
.reloc
.pc_rel
= 1;
8899 if (current_it_mask
)
8901 /* Conditional branches inside IT blocks are encoded as unconditional
8904 /* A branch must be the last instruction in an IT block. */
8905 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8910 if (cond
!= COND_ALWAYS
)
8911 opcode
= T_MNEM_bcond
;
8913 opcode
= inst
.instruction
;
8915 if (unified_syntax
&& inst
.size_req
== 4)
8917 inst
.instruction
= THUMB_OP32(opcode
);
8918 if (cond
== COND_ALWAYS
)
8919 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8922 assert (cond
!= 0xF);
8923 inst
.instruction
|= cond
<< 22;
8924 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8929 inst
.instruction
= THUMB_OP16(opcode
);
8930 if (cond
== COND_ALWAYS
)
8931 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8934 inst
.instruction
|= cond
<< 8;
8935 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8937 /* Allow section relaxation. */
8938 if (unified_syntax
&& inst
.size_req
!= 2)
8939 inst
.relax
= opcode
;
8942 inst
.reloc
.pc_rel
= 1;
8948 constraint (inst
.cond
!= COND_ALWAYS
,
8949 _("instruction is always unconditional"));
8950 if (inst
.operands
[0].present
)
8952 constraint (inst
.operands
[0].imm
> 255,
8953 _("immediate value out of range"));
8954 inst
.instruction
|= inst
.operands
[0].imm
;
8959 do_t_branch23 (void)
8961 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8962 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8963 inst
.reloc
.pc_rel
= 1;
8965 /* If the destination of the branch is a defined symbol which does not have
8966 the THUMB_FUNC attribute, then we must be calling a function which has
8967 the (interfacearm) attribute. We look for the Thumb entry point to that
8968 function and change the branch to refer to that function instead. */
8969 if ( inst
.reloc
.exp
.X_op
== O_symbol
8970 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8971 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8972 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8973 inst
.reloc
.exp
.X_add_symbol
=
8974 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8980 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8981 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8982 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8983 should cause the alignment to be checked once it is known. This is
8984 because BX PC only works if the instruction is word aligned. */
8990 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8991 if (inst
.operands
[0].reg
== REG_PC
)
8992 as_tsktsk (_("use of r15 in bxj is not really useful"));
8994 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9000 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9001 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9002 inst
.instruction
|= inst
.operands
[1].reg
;
9008 constraint (current_it_mask
, BAD_NOT_IT
);
9009 inst
.instruction
|= inst
.operands
[0].imm
;
9015 constraint (current_it_mask
, BAD_NOT_IT
);
9017 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9018 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9020 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9021 inst
.instruction
= 0xf3af8000;
9022 inst
.instruction
|= imod
<< 9;
9023 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9024 if (inst
.operands
[1].present
)
9025 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9030 && (inst
.operands
[0].imm
& 4),
9031 _("selected processor does not support 'A' form "
9032 "of this instruction"));
9033 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9034 _("Thumb does not support the 2-argument "
9035 "form of this instruction"));
9036 inst
.instruction
|= inst
.operands
[0].imm
;
9040 /* THUMB CPY instruction (argument parse). */
9045 if (inst
.size_req
== 4)
9047 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9048 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9049 inst
.instruction
|= inst
.operands
[1].reg
;
9053 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9054 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9055 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9062 constraint (current_it_mask
, BAD_NOT_IT
);
9063 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9064 inst
.instruction
|= inst
.operands
[0].reg
;
9065 inst
.reloc
.pc_rel
= 1;
9066 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9072 inst
.instruction
|= inst
.operands
[0].imm
;
9078 if (!inst
.operands
[1].present
)
9079 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9080 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9082 inst
.instruction
|= inst
.operands
[2].reg
;
9088 if (unified_syntax
&& inst
.size_req
== 4)
9089 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9091 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9097 unsigned int cond
= inst
.operands
[0].imm
;
9099 constraint (current_it_mask
, BAD_NOT_IT
);
9100 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9103 /* If the condition is a negative condition, invert the mask. */
9104 if ((cond
& 0x1) == 0x0)
9106 unsigned int mask
= inst
.instruction
& 0x000f;
9108 if ((mask
& 0x7) == 0)
9109 /* no conversion needed */;
9110 else if ((mask
& 0x3) == 0)
9112 else if ((mask
& 0x1) == 0)
9117 inst
.instruction
&= 0xfff0;
9118 inst
.instruction
|= mask
;
9121 inst
.instruction
|= cond
<< 4;
9124 /* Helper function used for both push/pop and ldm/stm. */
9126 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9130 load
= (inst
.instruction
& (1 << 20)) != 0;
9132 if (mask
& (1 << 13))
9133 inst
.error
= _("SP not allowed in register list");
9136 if (mask
& (1 << 14)
9137 && mask
& (1 << 15))
9138 inst
.error
= _("LR and PC should not both be in register list");
9140 if ((mask
& (1 << base
)) != 0
9142 as_warn (_("base register should not be in register list "
9143 "when written back"));
9147 if (mask
& (1 << 15))
9148 inst
.error
= _("PC not allowed in register list");
9150 if (mask
& (1 << base
))
9151 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9154 if ((mask
& (mask
- 1)) == 0)
9156 /* Single register transfers implemented as str/ldr. */
9159 if (inst
.instruction
& (1 << 23))
9160 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9162 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9166 if (inst
.instruction
& (1 << 23))
9167 inst
.instruction
= 0x00800000; /* ia -> [base] */
9169 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9172 inst
.instruction
|= 0xf8400000;
9174 inst
.instruction
|= 0x00100000;
9176 mask
= ffs (mask
) - 1;
9180 inst
.instruction
|= WRITE_BACK
;
9182 inst
.instruction
|= mask
;
9183 inst
.instruction
|= base
<< 16;
9189 /* This really doesn't seem worth it. */
9190 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9191 _("expression too complex"));
9192 constraint (inst
.operands
[1].writeback
,
9193 _("Thumb load/store multiple does not support {reglist}^"));
9201 /* See if we can use a 16-bit instruction. */
9202 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9203 && inst
.size_req
!= 4
9204 && !(inst
.operands
[1].imm
& ~0xff))
9206 mask
= 1 << inst
.operands
[0].reg
;
9208 if (inst
.operands
[0].reg
<= 7
9209 && (inst
.instruction
== T_MNEM_stmia
9210 ? inst
.operands
[0].writeback
9211 : (inst
.operands
[0].writeback
9212 == !(inst
.operands
[1].imm
& mask
))))
9214 if (inst
.instruction
== T_MNEM_stmia
9215 && (inst
.operands
[1].imm
& mask
)
9216 && (inst
.operands
[1].imm
& (mask
- 1)))
9217 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9218 inst
.operands
[0].reg
);
9220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9221 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9222 inst
.instruction
|= inst
.operands
[1].imm
;
9225 else if (inst
.operands
[0] .reg
== REG_SP
9226 && inst
.operands
[0].writeback
)
9228 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9229 ? T_MNEM_push
: T_MNEM_pop
);
9230 inst
.instruction
|= inst
.operands
[1].imm
;
9237 if (inst
.instruction
< 0xffff)
9238 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9240 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9241 inst
.operands
[0].writeback
);
9246 constraint (inst
.operands
[0].reg
> 7
9247 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9248 constraint (inst
.instruction
!= T_MNEM_ldmia
9249 && inst
.instruction
!= T_MNEM_stmia
,
9250 _("Thumb-2 instruction only valid in unified syntax"));
9251 if (inst
.instruction
== T_MNEM_stmia
)
9253 if (!inst
.operands
[0].writeback
)
9254 as_warn (_("this instruction will write back the base register"));
9255 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9256 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9257 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9258 inst
.operands
[0].reg
);
9262 if (!inst
.operands
[0].writeback
9263 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9264 as_warn (_("this instruction will write back the base register"));
9265 else if (inst
.operands
[0].writeback
9266 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9267 as_warn (_("this instruction will not write back the base register"));
9270 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9271 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9272 inst
.instruction
|= inst
.operands
[1].imm
;
9279 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9280 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9281 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9282 || inst
.operands
[1].negative
,
9285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9286 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9287 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9293 if (!inst
.operands
[1].present
)
9295 constraint (inst
.operands
[0].reg
== REG_LR
,
9296 _("r14 not allowed as first register "
9297 "when second register is omitted"));
9298 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9300 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9304 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9305 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9311 unsigned long opcode
;
9314 opcode
= inst
.instruction
;
9317 if (!inst
.operands
[1].isreg
)
9319 if (opcode
<= 0xffff)
9320 inst
.instruction
= THUMB_OP32 (opcode
);
9321 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9324 if (inst
.operands
[1].isreg
9325 && !inst
.operands
[1].writeback
9326 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9327 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9329 && inst
.size_req
!= 4)
9331 /* Insn may have a 16-bit form. */
9332 Rn
= inst
.operands
[1].reg
;
9333 if (inst
.operands
[1].immisreg
)
9335 inst
.instruction
= THUMB_OP16 (opcode
);
9337 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9340 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9341 && opcode
!= T_MNEM_ldrsb
)
9342 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9343 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9350 if (inst
.reloc
.pc_rel
)
9351 opcode
= T_MNEM_ldr_pc2
;
9353 opcode
= T_MNEM_ldr_pc
;
9357 if (opcode
== T_MNEM_ldr
)
9358 opcode
= T_MNEM_ldr_sp
;
9360 opcode
= T_MNEM_str_sp
;
9362 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9366 inst
.instruction
= inst
.operands
[0].reg
;
9367 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9369 inst
.instruction
|= THUMB_OP16 (opcode
);
9370 if (inst
.size_req
== 2)
9371 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9373 inst
.relax
= opcode
;
9377 /* Definitely a 32-bit variant. */
9378 inst
.instruction
= THUMB_OP32 (opcode
);
9379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9380 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9384 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9386 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9388 /* Only [Rn,Rm] is acceptable. */
9389 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9390 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9391 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9392 || inst
.operands
[1].negative
,
9393 _("Thumb does not support this addressing mode"));
9394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9398 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9399 if (!inst
.operands
[1].isreg
)
9400 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9403 constraint (!inst
.operands
[1].preind
9404 || inst
.operands
[1].shifted
9405 || inst
.operands
[1].writeback
,
9406 _("Thumb does not support this addressing mode"));
9407 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9409 constraint (inst
.instruction
& 0x0600,
9410 _("byte or halfword not valid for base register"));
9411 constraint (inst
.operands
[1].reg
== REG_PC
9412 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9413 _("r15 based store not allowed"));
9414 constraint (inst
.operands
[1].immisreg
,
9415 _("invalid base register for register offset"));
9417 if (inst
.operands
[1].reg
== REG_PC
)
9418 inst
.instruction
= T_OPCODE_LDR_PC
;
9419 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9420 inst
.instruction
= T_OPCODE_LDR_SP
;
9422 inst
.instruction
= T_OPCODE_STR_SP
;
9424 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9425 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9429 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9430 if (!inst
.operands
[1].immisreg
)
9432 /* Immediate offset. */
9433 inst
.instruction
|= inst
.operands
[0].reg
;
9434 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9435 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9439 /* Register offset. */
9440 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9441 constraint (inst
.operands
[1].negative
,
9442 _("Thumb does not support this addressing mode"));
9445 switch (inst
.instruction
)
9447 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9448 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9449 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9450 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9451 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9452 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9453 case 0x5600 /* ldrsb */:
9454 case 0x5e00 /* ldrsh */: break;
9458 inst
.instruction
|= inst
.operands
[0].reg
;
9459 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9460 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9466 if (!inst
.operands
[1].present
)
9468 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9469 constraint (inst
.operands
[0].reg
== REG_LR
,
9470 _("r14 not allowed here"));
9472 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9473 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9474 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9481 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9487 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9488 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9489 inst
.instruction
|= inst
.operands
[2].reg
;
9490 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9497 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9498 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9499 inst
.instruction
|= inst
.operands
[3].reg
;
9507 int r0off
= (inst
.instruction
== T_MNEM_mov
9508 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9509 unsigned long opcode
;
9511 bfd_boolean low_regs
;
9513 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9514 opcode
= inst
.instruction
;
9515 if (current_it_mask
)
9516 narrow
= opcode
!= T_MNEM_movs
;
9518 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9519 if (inst
.size_req
== 4
9520 || inst
.operands
[1].shifted
)
9523 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9524 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9525 && !inst
.operands
[1].shifted
9526 && inst
.operands
[0].reg
== REG_PC
9527 && inst
.operands
[1].reg
== REG_LR
)
9529 inst
.instruction
= T2_SUBS_PC_LR
;
9533 if (!inst
.operands
[1].isreg
)
9535 /* Immediate operand. */
9536 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9538 if (low_regs
&& narrow
)
9540 inst
.instruction
= THUMB_OP16 (opcode
);
9541 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9542 if (inst
.size_req
== 2)
9543 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9545 inst
.relax
= opcode
;
9549 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9550 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9551 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9552 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9555 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9556 && (inst
.instruction
== T_MNEM_mov
9557 || inst
.instruction
== T_MNEM_movs
))
9559 /* Register shifts are encoded as separate shift instructions. */
9560 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9562 if (current_it_mask
)
9567 if (inst
.size_req
== 4)
9570 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9573 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9576 switch (inst
.operands
[1].shift_kind
)
9579 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9582 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9585 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9588 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9594 inst
.instruction
= opcode
;
9597 inst
.instruction
|= inst
.operands
[0].reg
;
9598 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9603 inst
.instruction
|= CONDS_BIT
;
9605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9607 inst
.instruction
|= inst
.operands
[1].imm
;
9612 /* Some mov with immediate shift have narrow variants.
9613 Register shifts are handled above. */
9614 if (low_regs
&& inst
.operands
[1].shifted
9615 && (inst
.instruction
== T_MNEM_mov
9616 || inst
.instruction
== T_MNEM_movs
))
9618 if (current_it_mask
)
9619 narrow
= (inst
.instruction
== T_MNEM_mov
);
9621 narrow
= (inst
.instruction
== T_MNEM_movs
);
9626 switch (inst
.operands
[1].shift_kind
)
9628 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9629 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9630 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9631 default: narrow
= FALSE
; break;
9637 inst
.instruction
|= inst
.operands
[0].reg
;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9639 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9643 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9644 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9645 encode_thumb32_shifted_operand (1);
9649 switch (inst
.instruction
)
9652 inst
.instruction
= T_OPCODE_MOV_HR
;
9653 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9654 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9659 /* We know we have low registers at this point.
9660 Generate ADD Rd, Rs, #0. */
9661 inst
.instruction
= T_OPCODE_ADD_I3
;
9662 inst
.instruction
|= inst
.operands
[0].reg
;
9663 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9669 inst
.instruction
= T_OPCODE_CMP_LR
;
9670 inst
.instruction
|= inst
.operands
[0].reg
;
9671 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9675 inst
.instruction
= T_OPCODE_CMP_HR
;
9676 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9677 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9678 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9685 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9686 if (inst
.operands
[1].isreg
)
9688 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9690 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9691 since a MOV instruction produces unpredictable results. */
9692 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9693 inst
.instruction
= T_OPCODE_ADD_I3
;
9695 inst
.instruction
= T_OPCODE_CMP_LR
;
9697 inst
.instruction
|= inst
.operands
[0].reg
;
9698 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9702 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9703 inst
.instruction
= T_OPCODE_MOV_HR
;
9705 inst
.instruction
= T_OPCODE_CMP_HR
;
9711 constraint (inst
.operands
[0].reg
> 7,
9712 _("only lo regs allowed with immediate"));
9713 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9714 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9724 top
= (inst
.instruction
& 0x00800000) != 0;
9725 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9727 constraint (top
, _(":lower16: not allowed this instruction"));
9728 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9730 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9732 constraint (!top
, _(":upper16: not allowed this instruction"));
9733 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9737 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9739 imm
= inst
.reloc
.exp
.X_add_number
;
9740 inst
.instruction
|= (imm
& 0xf000) << 4;
9741 inst
.instruction
|= (imm
& 0x0800) << 15;
9742 inst
.instruction
|= (imm
& 0x0700) << 4;
9743 inst
.instruction
|= (imm
& 0x00ff);
9752 int r0off
= (inst
.instruction
== T_MNEM_mvn
9753 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9756 if (inst
.size_req
== 4
9757 || inst
.instruction
> 0xffff
9758 || inst
.operands
[1].shifted
9759 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9761 else if (inst
.instruction
== T_MNEM_cmn
)
9763 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9764 narrow
= (current_it_mask
== 0);
9766 narrow
= (current_it_mask
!= 0);
9768 if (!inst
.operands
[1].isreg
)
9770 /* For an immediate, we always generate a 32-bit opcode;
9771 section relaxation will shrink it later if possible. */
9772 if (inst
.instruction
< 0xffff)
9773 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9774 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9775 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9776 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9780 /* See if we can do this with a 16-bit instruction. */
9783 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9784 inst
.instruction
|= inst
.operands
[0].reg
;
9785 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9789 constraint (inst
.operands
[1].shifted
9790 && inst
.operands
[1].immisreg
,
9791 _("shift must be constant"));
9792 if (inst
.instruction
< 0xffff)
9793 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9794 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9795 encode_thumb32_shifted_operand (1);
9801 constraint (inst
.instruction
> 0xffff
9802 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9803 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9804 _("unshifted register required"));
9805 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9808 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9809 inst
.instruction
|= inst
.operands
[0].reg
;
9810 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9819 if (do_vfp_nsyn_mrs () == SUCCESS
)
9822 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9826 _("selected processor does not support "
9827 "requested special purpose register"));
9831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9832 _("selected processor does not support "
9833 "requested special purpose register"));
9834 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9835 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9836 _("'CPSR' or 'SPSR' expected"));
9839 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9840 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9841 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9849 if (do_vfp_nsyn_msr () == SUCCESS
)
9852 constraint (!inst
.operands
[1].isreg
,
9853 _("Thumb encoding does not support an immediate here"));
9854 flags
= inst
.operands
[0].imm
;
9857 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9858 _("selected processor does not support "
9859 "requested special purpose register"));
9863 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9864 _("selected processor does not support "
9865 "requested special purpose register"));
9868 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9869 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9870 inst
.instruction
|= (flags
& 0xff);
9871 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9877 if (!inst
.operands
[2].present
)
9878 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9880 /* There is no 32-bit MULS and no 16-bit MUL. */
9881 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9883 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9884 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9885 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9886 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9890 constraint (!unified_syntax
9891 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9892 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9895 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9896 inst
.instruction
|= inst
.operands
[0].reg
;
9898 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9899 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9900 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9901 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9903 constraint (1, _("dest must overlap one source register"));
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9911 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9912 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9913 inst
.instruction
|= inst
.operands
[3].reg
;
9915 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9916 as_tsktsk (_("rdhi and rdlo must be different"));
9924 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9926 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9927 inst
.instruction
|= inst
.operands
[0].imm
;
9931 /* PR9722: Check for Thumb2 availability before
9932 generating a thumb2 nop instruction. */
9933 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
9935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9936 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9939 inst
.instruction
= 0x46c0;
9944 constraint (inst
.operands
[0].present
,
9945 _("Thumb does not support NOP with hints"));
9946 inst
.instruction
= 0x46c0;
9957 if (THUMB_SETS_FLAGS (inst
.instruction
))
9958 narrow
= (current_it_mask
== 0);
9960 narrow
= (current_it_mask
!= 0);
9961 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9963 if (inst
.size_req
== 4)
9968 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9975 inst
.instruction
|= inst
.operands
[0].reg
;
9976 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9981 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9983 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9985 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9986 inst
.instruction
|= inst
.operands
[0].reg
;
9987 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9994 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9996 inst
.instruction
|= inst
.operands
[2].reg
;
9997 if (inst
.operands
[3].present
)
9999 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10000 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10001 _("expression too complex"));
10002 inst
.instruction
|= (val
& 0x1c) << 10;
10003 inst
.instruction
|= (val
& 0x03) << 6;
10010 if (!inst
.operands
[3].present
)
10011 inst
.instruction
&= ~0x00000020;
10018 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10022 do_t_push_pop (void)
10026 constraint (inst
.operands
[0].writeback
,
10027 _("push/pop do not support {reglist}^"));
10028 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10029 _("expression too complex"));
10031 mask
= inst
.operands
[0].imm
;
10032 if ((mask
& ~0xff) == 0)
10033 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10034 else if ((inst
.instruction
== T_MNEM_push
10035 && (mask
& ~0xff) == 1 << REG_LR
)
10036 || (inst
.instruction
== T_MNEM_pop
10037 && (mask
& ~0xff) == 1 << REG_PC
))
10039 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10040 inst
.instruction
|= THUMB_PP_PC_LR
;
10041 inst
.instruction
|= mask
& 0xff;
10043 else if (unified_syntax
)
10045 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10046 encode_thumb2_ldmstm (13, mask
, TRUE
);
10050 inst
.error
= _("invalid register list to push/pop instruction");
10058 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10059 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10060 inst
.instruction
|= inst
.operands
[1].reg
;
10066 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10067 && inst
.size_req
!= 4)
10069 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10070 inst
.instruction
|= inst
.operands
[0].reg
;
10071 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10073 else if (unified_syntax
)
10075 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10077 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10078 inst
.instruction
|= inst
.operands
[1].reg
;
10081 inst
.error
= BAD_HIREG
;
10089 Rd
= inst
.operands
[0].reg
;
10090 Rs
= (inst
.operands
[1].present
10091 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10092 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10094 inst
.instruction
|= Rd
<< 8;
10095 inst
.instruction
|= Rs
<< 16;
10096 if (!inst
.operands
[2].isreg
)
10098 bfd_boolean narrow
;
10100 if ((inst
.instruction
& 0x00100000) != 0)
10101 narrow
= (current_it_mask
== 0);
10103 narrow
= (current_it_mask
!= 0);
10105 if (Rd
> 7 || Rs
> 7)
10108 if (inst
.size_req
== 4 || !unified_syntax
)
10111 if (inst
.reloc
.exp
.X_op
!= O_constant
10112 || inst
.reloc
.exp
.X_add_number
!= 0)
10115 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10116 relaxation, but it doesn't seem worth the hassle. */
10119 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10120 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10121 inst
.instruction
|= Rs
<< 3;
10122 inst
.instruction
|= Rd
;
10126 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10127 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10131 encode_thumb32_shifted_operand (2);
10137 constraint (current_it_mask
, BAD_NOT_IT
);
10138 if (inst
.operands
[0].imm
)
10139 inst
.instruction
|= 0x8;
10145 if (!inst
.operands
[1].present
)
10146 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10148 if (unified_syntax
)
10150 bfd_boolean narrow
;
10153 switch (inst
.instruction
)
10156 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10158 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10160 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10162 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10166 if (THUMB_SETS_FLAGS (inst
.instruction
))
10167 narrow
= (current_it_mask
== 0);
10169 narrow
= (current_it_mask
!= 0);
10170 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10172 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10174 if (inst
.operands
[2].isreg
10175 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10176 || inst
.operands
[2].reg
> 7))
10178 if (inst
.size_req
== 4)
10183 if (inst
.operands
[2].isreg
)
10185 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10186 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10188 inst
.instruction
|= inst
.operands
[2].reg
;
10192 inst
.operands
[1].shifted
= 1;
10193 inst
.operands
[1].shift_kind
= shift_kind
;
10194 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10195 ? T_MNEM_movs
: T_MNEM_mov
);
10196 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10197 encode_thumb32_shifted_operand (1);
10198 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10199 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10204 if (inst
.operands
[2].isreg
)
10206 switch (shift_kind
)
10208 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10209 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10210 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10211 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10215 inst
.instruction
|= inst
.operands
[0].reg
;
10216 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10220 switch (shift_kind
)
10222 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10223 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10224 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10227 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10228 inst
.instruction
|= inst
.operands
[0].reg
;
10229 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10235 constraint (inst
.operands
[0].reg
> 7
10236 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10237 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10239 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10241 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10242 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10243 _("source1 and dest must be same register"));
10245 switch (inst
.instruction
)
10247 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10248 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10249 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10250 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10254 inst
.instruction
|= inst
.operands
[0].reg
;
10255 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10259 switch (inst
.instruction
)
10261 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10262 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10263 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10264 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10267 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10268 inst
.instruction
|= inst
.operands
[0].reg
;
10269 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10277 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10278 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10279 inst
.instruction
|= inst
.operands
[2].reg
;
10285 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10286 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10287 _("expression too complex"));
10288 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10289 inst
.instruction
|= (value
& 0xf000) >> 12;
10290 inst
.instruction
|= (value
& 0x0ff0);
10291 inst
.instruction
|= (value
& 0x000f) << 16;
10297 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10298 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10299 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10301 if (inst
.operands
[3].present
)
10303 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10304 _("expression too complex"));
10306 if (inst
.reloc
.exp
.X_add_number
!= 0)
10308 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10309 inst
.instruction
|= 0x00200000; /* sh bit */
10310 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10311 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10313 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10320 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10321 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10322 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10328 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10329 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10330 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10331 || inst
.operands
[2].negative
,
10334 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10335 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10336 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10337 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10343 if (!inst
.operands
[2].present
)
10344 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10346 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10347 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10348 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10349 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10352 inst
.instruction
|= inst
.operands
[0].reg
;
10353 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10354 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10355 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10361 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10362 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10363 inst
.instruction
|= inst
.operands
[2].reg
;
10364 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10370 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10371 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10372 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10374 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10375 inst
.instruction
|= inst
.operands
[0].reg
;
10376 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10378 else if (unified_syntax
)
10380 if (inst
.instruction
<= 0xffff)
10381 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10382 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10383 inst
.instruction
|= inst
.operands
[1].reg
;
10384 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10388 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10389 _("Thumb encoding does not support rotation"));
10390 constraint (1, BAD_HIREG
);
10397 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10405 half
= (inst
.instruction
& 0x10) != 0;
10406 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10407 constraint (inst
.operands
[0].immisreg
,
10408 _("instruction requires register index"));
10409 constraint (inst
.operands
[0].imm
== 15,
10410 _("PC is not a valid index register"));
10411 constraint (!half
&& inst
.operands
[0].shifted
,
10412 _("instruction does not allow shifted index"));
10413 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10419 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10420 inst
.instruction
|= inst
.operands
[1].imm
;
10421 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10423 if (inst
.operands
[3].present
)
10425 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10426 _("expression too complex"));
10427 if (inst
.reloc
.exp
.X_add_number
!= 0)
10429 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10430 inst
.instruction
|= 0x00200000; /* sh bit */
10432 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10433 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10435 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10442 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10443 inst
.instruction
|= inst
.operands
[1].imm
;
10444 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10447 /* Neon instruction encoder helpers. */
10449 /* Encodings for the different types for various Neon opcodes. */
10451 /* An "invalid" code for the following tables. */
10454 struct neon_tab_entry
10457 unsigned float_or_poly
;
10458 unsigned scalar_or_imm
;
10461 /* Map overloaded Neon opcodes to their respective encodings. */
10462 #define NEON_ENC_TAB \
10463 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10464 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10465 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10466 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10467 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10468 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10469 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10470 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10471 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10472 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10473 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10474 /* Register variants of the following two instructions are encoded as
10475 vcge / vcgt with the operands reversed. */ \
10476 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10477 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10478 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10479 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10480 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10481 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10482 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10483 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10484 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10485 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10486 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10487 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10488 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10489 X(vshl, 0x0000400, N_INV, 0x0800510), \
10490 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10491 X(vand, 0x0000110, N_INV, 0x0800030), \
10492 X(vbic, 0x0100110, N_INV, 0x0800030), \
10493 X(veor, 0x1000110, N_INV, N_INV), \
10494 X(vorn, 0x0300110, N_INV, 0x0800010), \
10495 X(vorr, 0x0200110, N_INV, 0x0800010), \
10496 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10497 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10498 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10499 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10500 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10501 X(vst1, 0x0000000, 0x0800000, N_INV), \
10502 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10503 X(vst2, 0x0000100, 0x0800100, N_INV), \
10504 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10505 X(vst3, 0x0000200, 0x0800200, N_INV), \
10506 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10507 X(vst4, 0x0000300, 0x0800300, N_INV), \
10508 X(vmovn, 0x1b20200, N_INV, N_INV), \
10509 X(vtrn, 0x1b20080, N_INV, N_INV), \
10510 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10511 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10512 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10513 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10514 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10515 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10516 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10517 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10518 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10522 #define X(OPC,I,F,S) N_MNEM_##OPC
10527 static const struct neon_tab_entry neon_enc_tab
[] =
10529 #define X(OPC,I,F,S) { (I), (F), (S) }
10534 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10535 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10536 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10537 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10538 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10539 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10540 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10541 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10542 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10543 #define NEON_ENC_SINGLE(X) \
10544 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10545 #define NEON_ENC_DOUBLE(X) \
10546 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10548 /* Define shapes for instruction operands. The following mnemonic characters
10549 are used in this table:
10551 F - VFP S<n> register
10552 D - Neon D<n> register
10553 Q - Neon Q<n> register
10557 L - D<n> register list
10559 This table is used to generate various data:
10560 - enumerations of the form NS_DDR to be used as arguments to
10562 - a table classifying shapes into single, double, quad, mixed.
10563 - a table used to drive neon_select_shape. */
10565 #define NEON_SHAPE_DEF \
10566 X(3, (D, D, D), DOUBLE), \
10567 X(3, (Q, Q, Q), QUAD), \
10568 X(3, (D, D, I), DOUBLE), \
10569 X(3, (Q, Q, I), QUAD), \
10570 X(3, (D, D, S), DOUBLE), \
10571 X(3, (Q, Q, S), QUAD), \
10572 X(2, (D, D), DOUBLE), \
10573 X(2, (Q, Q), QUAD), \
10574 X(2, (D, S), DOUBLE), \
10575 X(2, (Q, S), QUAD), \
10576 X(2, (D, R), DOUBLE), \
10577 X(2, (Q, R), QUAD), \
10578 X(2, (D, I), DOUBLE), \
10579 X(2, (Q, I), QUAD), \
10580 X(3, (D, L, D), DOUBLE), \
10581 X(2, (D, Q), MIXED), \
10582 X(2, (Q, D), MIXED), \
10583 X(3, (D, Q, I), MIXED), \
10584 X(3, (Q, D, I), MIXED), \
10585 X(3, (Q, D, D), MIXED), \
10586 X(3, (D, Q, Q), MIXED), \
10587 X(3, (Q, Q, D), MIXED), \
10588 X(3, (Q, D, S), MIXED), \
10589 X(3, (D, Q, S), MIXED), \
10590 X(4, (D, D, D, I), DOUBLE), \
10591 X(4, (Q, Q, Q, I), QUAD), \
10592 X(2, (F, F), SINGLE), \
10593 X(3, (F, F, F), SINGLE), \
10594 X(2, (F, I), SINGLE), \
10595 X(2, (F, D), MIXED), \
10596 X(2, (D, F), MIXED), \
10597 X(3, (F, F, I), MIXED), \
10598 X(4, (R, R, F, F), SINGLE), \
10599 X(4, (F, F, R, R), SINGLE), \
10600 X(3, (D, R, R), DOUBLE), \
10601 X(3, (R, R, D), DOUBLE), \
10602 X(2, (S, R), SINGLE), \
10603 X(2, (R, S), SINGLE), \
10604 X(2, (F, R), SINGLE), \
10605 X(2, (R, F), SINGLE)
10607 #define S2(A,B) NS_##A##B
10608 #define S3(A,B,C) NS_##A##B##C
10609 #define S4(A,B,C,D) NS_##A##B##C##D
10611 #define X(N, L, C) S##N L
10624 enum neon_shape_class
10632 #define X(N, L, C) SC_##C
10634 static enum neon_shape_class neon_shape_class
[] =
10652 /* Register widths of above. */
10653 static unsigned neon_shape_el_size
[] =
10664 struct neon_shape_info
10667 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10670 #define S2(A,B) { SE_##A, SE_##B }
10671 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10672 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10674 #define X(N, L, C) { N, S##N L }
10676 static struct neon_shape_info neon_shape_tab
[] =
10686 /* Bit masks used in type checking given instructions.
10687 'N_EQK' means the type must be the same as (or based on in some way) the key
10688 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10689 set, various other bits can be set as well in order to modify the meaning of
10690 the type constraint. */
10692 enum neon_type_mask
10715 N_KEY
= 0x1000000, /* key element (main type specifier). */
10716 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
10717 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
10718 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
10719 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
10720 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
10721 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
10722 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
10723 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
10724 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
10726 N_MAX_NONSPECIAL
= N_F64
10729 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10731 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10732 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10733 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10734 #define N_SUF_32 (N_SU_32 | N_F32)
10735 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10736 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10738 /* Pass this as the first type argument to neon_check_type to ignore types
10740 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10742 /* Select a "shape" for the current instruction (describing register types or
10743 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10744 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10745 function of operand parsing, so this function doesn't need to be called.
10746 Shapes should be listed in order of decreasing length. */
10748 static enum neon_shape
10749 neon_select_shape (enum neon_shape shape
, ...)
10752 enum neon_shape first_shape
= shape
;
10754 /* Fix missing optional operands. FIXME: we don't know at this point how
10755 many arguments we should have, so this makes the assumption that we have
10756 > 1. This is true of all current Neon opcodes, I think, but may not be
10757 true in the future. */
10758 if (!inst
.operands
[1].present
)
10759 inst
.operands
[1] = inst
.operands
[0];
10761 va_start (ap
, shape
);
10763 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10768 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10770 if (!inst
.operands
[j
].present
)
10776 switch (neon_shape_tab
[shape
].el
[j
])
10779 if (!(inst
.operands
[j
].isreg
10780 && inst
.operands
[j
].isvec
10781 && inst
.operands
[j
].issingle
10782 && !inst
.operands
[j
].isquad
))
10787 if (!(inst
.operands
[j
].isreg
10788 && inst
.operands
[j
].isvec
10789 && !inst
.operands
[j
].isquad
10790 && !inst
.operands
[j
].issingle
))
10795 if (!(inst
.operands
[j
].isreg
10796 && !inst
.operands
[j
].isvec
))
10801 if (!(inst
.operands
[j
].isreg
10802 && inst
.operands
[j
].isvec
10803 && inst
.operands
[j
].isquad
10804 && !inst
.operands
[j
].issingle
))
10809 if (!(!inst
.operands
[j
].isreg
10810 && !inst
.operands
[j
].isscalar
))
10815 if (!(!inst
.operands
[j
].isreg
10816 && inst
.operands
[j
].isscalar
))
10830 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10831 first_error (_("invalid instruction shape"));
10836 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10837 means the Q bit should be set). */
10840 neon_quad (enum neon_shape shape
)
10842 return neon_shape_class
[shape
] == SC_QUAD
;
10846 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10849 /* Allow modification to be made to types which are constrained to be
10850 based on the key element, based on bits set alongside N_EQK. */
10851 if ((typebits
& N_EQK
) != 0)
10853 if ((typebits
& N_HLF
) != 0)
10855 else if ((typebits
& N_DBL
) != 0)
10857 if ((typebits
& N_SGN
) != 0)
10858 *g_type
= NT_signed
;
10859 else if ((typebits
& N_UNS
) != 0)
10860 *g_type
= NT_unsigned
;
10861 else if ((typebits
& N_INT
) != 0)
10862 *g_type
= NT_integer
;
10863 else if ((typebits
& N_FLT
) != 0)
10864 *g_type
= NT_float
;
10865 else if ((typebits
& N_SIZ
) != 0)
10866 *g_type
= NT_untyped
;
10870 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10871 operand type, i.e. the single type specified in a Neon instruction when it
10872 is the only one given. */
10874 static struct neon_type_el
10875 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10877 struct neon_type_el dest
= *key
;
10879 assert ((thisarg
& N_EQK
) != 0);
10881 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10886 /* Convert Neon type and size into compact bitmask representation. */
10888 static enum neon_type_mask
10889 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10896 case 8: return N_8
;
10897 case 16: return N_16
;
10898 case 32: return N_32
;
10899 case 64: return N_64
;
10907 case 8: return N_I8
;
10908 case 16: return N_I16
;
10909 case 32: return N_I32
;
10910 case 64: return N_I64
;
10918 case 16: return N_F16
;
10919 case 32: return N_F32
;
10920 case 64: return N_F64
;
10928 case 8: return N_P8
;
10929 case 16: return N_P16
;
10937 case 8: return N_S8
;
10938 case 16: return N_S16
;
10939 case 32: return N_S32
;
10940 case 64: return N_S64
;
10948 case 8: return N_U8
;
10949 case 16: return N_U16
;
10950 case 32: return N_U32
;
10951 case 64: return N_U64
;
10962 /* Convert compact Neon bitmask type representation to a type and size. Only
10963 handles the case where a single bit is set in the mask. */
10966 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10967 enum neon_type_mask mask
)
10969 if ((mask
& N_EQK
) != 0)
10972 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10974 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10976 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10978 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10983 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10985 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10986 *type
= NT_unsigned
;
10987 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10988 *type
= NT_integer
;
10989 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10990 *type
= NT_untyped
;
10991 else if ((mask
& (N_P8
| N_P16
)) != 0)
10993 else if ((mask
& (N_F32
| N_F64
)) != 0)
11001 /* Modify a bitmask of allowed types. This is only needed for type
11005 modify_types_allowed (unsigned allowed
, unsigned mods
)
11008 enum neon_el_type type
;
11014 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11016 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11018 neon_modify_type_size (mods
, &type
, &size
);
11019 destmask
|= type_chk_of_el_type (type
, size
);
11026 /* Check type and return type classification.
11027 The manual states (paraphrase): If one datatype is given, it indicates the
11029 - the second operand, if there is one
11030 - the operand, if there is no second operand
11031 - the result, if there are no operands.
11032 This isn't quite good enough though, so we use a concept of a "key" datatype
11033 which is set on a per-instruction basis, which is the one which matters when
11034 only one data type is written.
11035 Note: this function has side-effects (e.g. filling in missing operands). All
11036 Neon instructions should call it before performing bit encoding. */
11038 static struct neon_type_el
11039 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11042 unsigned i
, pass
, key_el
= 0;
11043 unsigned types
[NEON_MAX_TYPE_ELS
];
11044 enum neon_el_type k_type
= NT_invtype
;
11045 unsigned k_size
= -1u;
11046 struct neon_type_el badtype
= {NT_invtype
, -1};
11047 unsigned key_allowed
= 0;
11049 /* Optional registers in Neon instructions are always (not) in operand 1.
11050 Fill in the missing operand here, if it was omitted. */
11051 if (els
> 1 && !inst
.operands
[1].present
)
11052 inst
.operands
[1] = inst
.operands
[0];
11054 /* Suck up all the varargs. */
11056 for (i
= 0; i
< els
; i
++)
11058 unsigned thisarg
= va_arg (ap
, unsigned);
11059 if (thisarg
== N_IGNORE_TYPE
)
11064 types
[i
] = thisarg
;
11065 if ((thisarg
& N_KEY
) != 0)
11070 if (inst
.vectype
.elems
> 0)
11071 for (i
= 0; i
< els
; i
++)
11072 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11074 first_error (_("types specified in both the mnemonic and operands"));
11078 /* Duplicate inst.vectype elements here as necessary.
11079 FIXME: No idea if this is exactly the same as the ARM assembler,
11080 particularly when an insn takes one register and one non-register
11082 if (inst
.vectype
.elems
== 1 && els
> 1)
11085 inst
.vectype
.elems
= els
;
11086 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11087 for (j
= 0; j
< els
; j
++)
11089 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11092 else if (inst
.vectype
.elems
== 0 && els
> 0)
11095 /* No types were given after the mnemonic, so look for types specified
11096 after each operand. We allow some flexibility here; as long as the
11097 "key" operand has a type, we can infer the others. */
11098 for (j
= 0; j
< els
; j
++)
11099 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11100 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11102 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11104 for (j
= 0; j
< els
; j
++)
11105 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11106 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11111 first_error (_("operand types can't be inferred"));
11115 else if (inst
.vectype
.elems
!= els
)
11117 first_error (_("type specifier has the wrong number of parts"));
11121 for (pass
= 0; pass
< 2; pass
++)
11123 for (i
= 0; i
< els
; i
++)
11125 unsigned thisarg
= types
[i
];
11126 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11127 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11128 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11129 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11131 /* Decay more-specific signed & unsigned types to sign-insensitive
11132 integer types if sign-specific variants are unavailable. */
11133 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11134 && (types_allowed
& N_SU_ALL
) == 0)
11135 g_type
= NT_integer
;
11137 /* If only untyped args are allowed, decay any more specific types to
11138 them. Some instructions only care about signs for some element
11139 sizes, so handle that properly. */
11140 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11141 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11142 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11143 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11144 g_type
= NT_untyped
;
11148 if ((thisarg
& N_KEY
) != 0)
11152 key_allowed
= thisarg
& ~N_KEY
;
11157 if ((thisarg
& N_VFP
) != 0)
11159 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11160 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11162 /* In VFP mode, operands must match register widths. If we
11163 have a key operand, use its width, else use the width of
11164 the current operand. */
11170 if (regwidth
!= match
)
11172 first_error (_("operand size must match register width"));
11177 if ((thisarg
& N_EQK
) == 0)
11179 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11181 if ((given_type
& types_allowed
) == 0)
11183 first_error (_("bad type in Neon instruction"));
11189 enum neon_el_type mod_k_type
= k_type
;
11190 unsigned mod_k_size
= k_size
;
11191 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11192 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11194 first_error (_("inconsistent types in Neon instruction"));
11202 return inst
.vectype
.el
[key_el
];
11205 /* Neon-style VFP instruction forwarding. */
11207 /* Thumb VFP instructions have 0xE in the condition field. */
11210 do_vfp_cond_or_thumb (void)
11213 inst
.instruction
|= 0xe0000000;
11215 inst
.instruction
|= inst
.cond
<< 28;
11218 /* Look up and encode a simple mnemonic, for use as a helper function for the
11219 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11220 etc. It is assumed that operand parsing has already been done, and that the
11221 operands are in the form expected by the given opcode (this isn't necessarily
11222 the same as the form in which they were parsed, hence some massaging must
11223 take place before this function is called).
11224 Checks current arch version against that in the looked-up opcode. */
11227 do_vfp_nsyn_opcode (const char *opname
)
11229 const struct asm_opcode
*opcode
;
11231 opcode
= hash_find (arm_ops_hsh
, opname
);
11236 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11237 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11242 inst
.instruction
= opcode
->tvalue
;
11243 opcode
->tencode ();
11247 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11248 opcode
->aencode ();
11253 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11255 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11260 do_vfp_nsyn_opcode ("fadds");
11262 do_vfp_nsyn_opcode ("fsubs");
11267 do_vfp_nsyn_opcode ("faddd");
11269 do_vfp_nsyn_opcode ("fsubd");
11273 /* Check operand types to see if this is a VFP instruction, and if so call
11277 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11279 enum neon_shape rs
;
11280 struct neon_type_el et
;
11285 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11286 et
= neon_check_type (2, rs
,
11287 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11291 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11292 et
= neon_check_type (3, rs
,
11293 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11300 if (et
.type
!= NT_invtype
)
11312 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11314 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11319 do_vfp_nsyn_opcode ("fmacs");
11321 do_vfp_nsyn_opcode ("fmscs");
11326 do_vfp_nsyn_opcode ("fmacd");
11328 do_vfp_nsyn_opcode ("fmscd");
11333 do_vfp_nsyn_mul (enum neon_shape rs
)
11336 do_vfp_nsyn_opcode ("fmuls");
11338 do_vfp_nsyn_opcode ("fmuld");
11342 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11344 int is_neg
= (inst
.instruction
& 0x80) != 0;
11345 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11350 do_vfp_nsyn_opcode ("fnegs");
11352 do_vfp_nsyn_opcode ("fabss");
11357 do_vfp_nsyn_opcode ("fnegd");
11359 do_vfp_nsyn_opcode ("fabsd");
11363 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11364 insns belong to Neon, and are handled elsewhere. */
11367 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11369 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11373 do_vfp_nsyn_opcode ("fldmdbs");
11375 do_vfp_nsyn_opcode ("fldmias");
11380 do_vfp_nsyn_opcode ("fstmdbs");
11382 do_vfp_nsyn_opcode ("fstmias");
11387 do_vfp_nsyn_sqrt (void)
11389 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11390 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11393 do_vfp_nsyn_opcode ("fsqrts");
11395 do_vfp_nsyn_opcode ("fsqrtd");
11399 do_vfp_nsyn_div (void)
11401 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11402 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11403 N_F32
| N_F64
| N_KEY
| N_VFP
);
11406 do_vfp_nsyn_opcode ("fdivs");
11408 do_vfp_nsyn_opcode ("fdivd");
11412 do_vfp_nsyn_nmul (void)
11414 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11415 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11416 N_F32
| N_F64
| N_KEY
| N_VFP
);
11420 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11421 do_vfp_sp_dyadic ();
11425 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11426 do_vfp_dp_rd_rn_rm ();
11428 do_vfp_cond_or_thumb ();
11432 do_vfp_nsyn_cmp (void)
11434 if (inst
.operands
[1].isreg
)
11436 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11437 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11441 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11442 do_vfp_sp_monadic ();
11446 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11447 do_vfp_dp_rd_rm ();
11452 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11453 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11455 switch (inst
.instruction
& 0x0fffffff)
11458 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11461 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11469 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11470 do_vfp_sp_compare_z ();
11474 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11478 do_vfp_cond_or_thumb ();
11482 nsyn_insert_sp (void)
11484 inst
.operands
[1] = inst
.operands
[0];
11485 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11486 inst
.operands
[0].reg
= 13;
11487 inst
.operands
[0].isreg
= 1;
11488 inst
.operands
[0].writeback
= 1;
11489 inst
.operands
[0].present
= 1;
11493 do_vfp_nsyn_push (void)
11496 if (inst
.operands
[1].issingle
)
11497 do_vfp_nsyn_opcode ("fstmdbs");
11499 do_vfp_nsyn_opcode ("fstmdbd");
11503 do_vfp_nsyn_pop (void)
11506 if (inst
.operands
[1].issingle
)
11507 do_vfp_nsyn_opcode ("fldmias");
11509 do_vfp_nsyn_opcode ("fldmiad");
11512 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11513 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11516 neon_dp_fixup (unsigned i
)
11520 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11534 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11538 neon_logbits (unsigned x
)
11540 return ffs (x
) - 4;
11543 #define LOW4(R) ((R) & 0xf)
11544 #define HI1(R) (((R) >> 4) & 1)
11546 /* Encode insns with bit pattern:
11548 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11549 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11551 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11552 different meaning for some instruction. */
11555 neon_three_same (int isquad
, int ubit
, int size
)
11557 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11558 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11559 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11560 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11561 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11562 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11563 inst
.instruction
|= (isquad
!= 0) << 6;
11564 inst
.instruction
|= (ubit
!= 0) << 24;
11566 inst
.instruction
|= neon_logbits (size
) << 20;
11568 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11571 /* Encode instructions of the form:
11573 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11574 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11576 Don't write size if SIZE == -1. */
11579 neon_two_same (int qbit
, int ubit
, int size
)
11581 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11582 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11583 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11584 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11585 inst
.instruction
|= (qbit
!= 0) << 6;
11586 inst
.instruction
|= (ubit
!= 0) << 24;
11589 inst
.instruction
|= neon_logbits (size
) << 18;
11591 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11594 /* Neon instruction encoders, in approximate order of appearance. */
11597 do_neon_dyadic_i_su (void)
11599 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11600 struct neon_type_el et
= neon_check_type (3, rs
,
11601 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11602 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11606 do_neon_dyadic_i64_su (void)
11608 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11609 struct neon_type_el et
= neon_check_type (3, rs
,
11610 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11611 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11615 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11618 unsigned size
= et
.size
>> 3;
11619 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11621 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11622 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11623 inst
.instruction
|= (isquad
!= 0) << 6;
11624 inst
.instruction
|= immbits
<< 16;
11625 inst
.instruction
|= (size
>> 3) << 7;
11626 inst
.instruction
|= (size
& 0x7) << 19;
11628 inst
.instruction
|= (uval
!= 0) << 24;
11630 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11634 do_neon_shl_imm (void)
11636 if (!inst
.operands
[2].isreg
)
11638 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11639 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11640 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11641 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11645 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11646 struct neon_type_el et
= neon_check_type (3, rs
,
11647 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11650 /* VSHL/VQSHL 3-register variants have syntax such as:
11652 whereas other 3-register operations encoded by neon_three_same have
11655 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11657 tmp
= inst
.operands
[2].reg
;
11658 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11659 inst
.operands
[1].reg
= tmp
;
11660 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11661 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11666 do_neon_qshl_imm (void)
11668 if (!inst
.operands
[2].isreg
)
11670 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11671 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11673 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11674 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11675 inst
.operands
[2].imm
);
11679 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11680 struct neon_type_el et
= neon_check_type (3, rs
,
11681 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11684 /* See note in do_neon_shl_imm. */
11685 tmp
= inst
.operands
[2].reg
;
11686 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11687 inst
.operands
[1].reg
= tmp
;
11688 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11689 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11694 do_neon_rshl (void)
11696 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11697 struct neon_type_el et
= neon_check_type (3, rs
,
11698 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11701 tmp
= inst
.operands
[2].reg
;
11702 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11703 inst
.operands
[1].reg
= tmp
;
11704 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11708 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11710 /* Handle .I8 pseudo-instructions. */
11713 /* Unfortunately, this will make everything apart from zero out-of-range.
11714 FIXME is this the intended semantics? There doesn't seem much point in
11715 accepting .I8 if so. */
11716 immediate
|= immediate
<< 8;
11722 if (immediate
== (immediate
& 0x000000ff))
11724 *immbits
= immediate
;
11727 else if (immediate
== (immediate
& 0x0000ff00))
11729 *immbits
= immediate
>> 8;
11732 else if (immediate
== (immediate
& 0x00ff0000))
11734 *immbits
= immediate
>> 16;
11737 else if (immediate
== (immediate
& 0xff000000))
11739 *immbits
= immediate
>> 24;
11742 if ((immediate
& 0xffff) != (immediate
>> 16))
11743 goto bad_immediate
;
11744 immediate
&= 0xffff;
11747 if (immediate
== (immediate
& 0x000000ff))
11749 *immbits
= immediate
;
11752 else if (immediate
== (immediate
& 0x0000ff00))
11754 *immbits
= immediate
>> 8;
11759 first_error (_("immediate value out of range"));
11763 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11767 neon_bits_same_in_bytes (unsigned imm
)
11769 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11770 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11771 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11772 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11775 /* For immediate of above form, return 0bABCD. */
11778 neon_squash_bits (unsigned imm
)
11780 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11781 | ((imm
& 0x01000000) >> 21);
11784 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11787 neon_qfloat_bits (unsigned imm
)
11789 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11792 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11793 the instruction. *OP is passed as the initial value of the op field, and
11794 may be set to a different value depending on the constant (i.e.
11795 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11796 MVN). If the immediate looks like a repeated pattern then also
11797 try smaller element sizes. */
11800 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11801 unsigned *immbits
, int *op
, int size
,
11802 enum neon_el_type type
)
11804 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11806 if (type
== NT_float
&& !float_p
)
11809 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11811 if (size
!= 32 || *op
== 1)
11813 *immbits
= neon_qfloat_bits (immlo
);
11819 if (neon_bits_same_in_bytes (immhi
)
11820 && neon_bits_same_in_bytes (immlo
))
11824 *immbits
= (neon_squash_bits (immhi
) << 4)
11825 | neon_squash_bits (immlo
);
11830 if (immhi
!= immlo
)
11836 if (immlo
== (immlo
& 0x000000ff))
11841 else if (immlo
== (immlo
& 0x0000ff00))
11843 *immbits
= immlo
>> 8;
11846 else if (immlo
== (immlo
& 0x00ff0000))
11848 *immbits
= immlo
>> 16;
11851 else if (immlo
== (immlo
& 0xff000000))
11853 *immbits
= immlo
>> 24;
11856 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11858 *immbits
= (immlo
>> 8) & 0xff;
11861 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11863 *immbits
= (immlo
>> 16) & 0xff;
11867 if ((immlo
& 0xffff) != (immlo
>> 16))
11874 if (immlo
== (immlo
& 0x000000ff))
11879 else if (immlo
== (immlo
& 0x0000ff00))
11881 *immbits
= immlo
>> 8;
11885 if ((immlo
& 0xff) != (immlo
>> 8))
11890 if (immlo
== (immlo
& 0x000000ff))
11892 /* Don't allow MVN with 8-bit immediate. */
11902 /* Write immediate bits [7:0] to the following locations:
11904 |28/24|23 19|18 16|15 4|3 0|
11905 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11907 This function is used by VMOV/VMVN/VORR/VBIC. */
11910 neon_write_immbits (unsigned immbits
)
11912 inst
.instruction
|= immbits
& 0xf;
11913 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11914 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11917 /* Invert low-order SIZE bits of XHI:XLO. */
11920 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11922 unsigned immlo
= xlo
? *xlo
: 0;
11923 unsigned immhi
= xhi
? *xhi
: 0;
11928 immlo
= (~immlo
) & 0xff;
11932 immlo
= (~immlo
) & 0xffff;
11936 immhi
= (~immhi
) & 0xffffffff;
11937 /* fall through. */
11940 immlo
= (~immlo
) & 0xffffffff;
11955 do_neon_logic (void)
11957 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11959 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11960 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11961 /* U bit and size field were set as part of the bitmask. */
11962 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11963 neon_three_same (neon_quad (rs
), 0, -1);
11967 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11968 struct neon_type_el et
= neon_check_type (2, rs
,
11969 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11970 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11974 if (et
.type
== NT_invtype
)
11977 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11979 immbits
= inst
.operands
[1].imm
;
11982 /* .i64 is a pseudo-op, so the immediate must be a repeating
11984 if (immbits
!= (inst
.operands
[1].regisimm
?
11985 inst
.operands
[1].reg
: 0))
11987 /* Set immbits to an invalid constant. */
11988 immbits
= 0xdeadbeef;
11995 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11999 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12003 /* Pseudo-instruction for VBIC. */
12004 neon_invert_size (&immbits
, 0, et
.size
);
12005 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12009 /* Pseudo-instruction for VORR. */
12010 neon_invert_size (&immbits
, 0, et
.size
);
12011 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12021 inst
.instruction
|= neon_quad (rs
) << 6;
12022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12024 inst
.instruction
|= cmode
<< 8;
12025 neon_write_immbits (immbits
);
12027 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12032 do_neon_bitfield (void)
12034 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12035 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12036 neon_three_same (neon_quad (rs
), 0, -1);
12040 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12043 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12044 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12046 if (et
.type
== NT_float
)
12048 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12049 neon_three_same (neon_quad (rs
), 0, -1);
12053 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12054 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12059 do_neon_dyadic_if_su (void)
12061 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12065 do_neon_dyadic_if_su_d (void)
12067 /* This version only allow D registers, but that constraint is enforced during
12068 operand parsing so we don't need to do anything extra here. */
12069 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12073 do_neon_dyadic_if_i_d (void)
12075 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12076 affected if we specify unsigned args. */
12077 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12080 enum vfp_or_neon_is_neon_bits
12083 NEON_CHECK_ARCH
= 2
12086 /* Call this function if an instruction which may have belonged to the VFP or
12087 Neon instruction sets, but turned out to be a Neon instruction (due to the
12088 operand types involved, etc.). We have to check and/or fix-up a couple of
12091 - Make sure the user hasn't attempted to make a Neon instruction
12093 - Alter the value in the condition code field if necessary.
12094 - Make sure that the arch supports Neon instructions.
12096 Which of these operations take place depends on bits from enum
12097 vfp_or_neon_is_neon_bits.
12099 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12100 current instruction's condition is COND_ALWAYS, the condition field is
12101 changed to inst.uncond_value. This is necessary because instructions shared
12102 between VFP and Neon may be conditional for the VFP variants only, and the
12103 unconditional Neon version must have, e.g., 0xF in the condition field. */
12106 vfp_or_neon_is_neon (unsigned check
)
12108 /* Conditions are always legal in Thumb mode (IT blocks). */
12109 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12111 if (inst
.cond
!= COND_ALWAYS
)
12113 first_error (_(BAD_COND
));
12116 if (inst
.uncond_value
!= -1)
12117 inst
.instruction
|= inst
.uncond_value
<< 28;
12120 if ((check
& NEON_CHECK_ARCH
)
12121 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12123 first_error (_(BAD_FPU
));
12131 do_neon_addsub_if_i (void)
12133 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12136 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12139 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12140 affected if we specify unsigned args. */
12141 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12144 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12146 V<op> A,B (A is operand 0, B is operand 2)
12151 so handle that case specially. */
12154 neon_exchange_operands (void)
12156 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12157 if (inst
.operands
[1].present
)
12159 /* Swap operands[1] and operands[2]. */
12160 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12161 inst
.operands
[1] = inst
.operands
[2];
12162 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12166 inst
.operands
[1] = inst
.operands
[2];
12167 inst
.operands
[2] = inst
.operands
[0];
12172 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12174 if (inst
.operands
[2].isreg
)
12177 neon_exchange_operands ();
12178 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12182 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12183 struct neon_type_el et
= neon_check_type (2, rs
,
12184 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12186 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12188 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12189 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12190 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12191 inst
.instruction
|= neon_quad (rs
) << 6;
12192 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12193 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12195 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12202 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12206 do_neon_cmp_inv (void)
12208 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12214 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12217 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12218 scalars, which are encoded in 5 bits, M : Rm.
12219 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12220 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12224 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12226 unsigned regno
= NEON_SCALAR_REG (scalar
);
12227 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12232 if (regno
> 7 || elno
> 3)
12234 return regno
| (elno
<< 3);
12237 if (regno
> 15 || elno
> 1)
12239 return regno
| (elno
<< 4);
12243 first_error (_("scalar out of range for multiply instruction"));
12249 /* Encode multiply / multiply-accumulate scalar instructions. */
12252 neon_mul_mac (struct neon_type_el et
, int ubit
)
12256 /* Give a more helpful error message if we have an invalid type. */
12257 if (et
.type
== NT_invtype
)
12260 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12261 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12262 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12263 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12264 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12265 inst
.instruction
|= LOW4 (scalar
);
12266 inst
.instruction
|= HI1 (scalar
) << 5;
12267 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12268 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12269 inst
.instruction
|= (ubit
!= 0) << 24;
12271 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12275 do_neon_mac_maybe_scalar (void)
12277 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12280 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12283 if (inst
.operands
[2].isscalar
)
12285 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12286 struct neon_type_el et
= neon_check_type (3, rs
,
12287 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12288 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12289 neon_mul_mac (et
, neon_quad (rs
));
12293 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12294 affected if we specify unsigned args. */
12295 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12302 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12303 struct neon_type_el et
= neon_check_type (3, rs
,
12304 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12305 neon_three_same (neon_quad (rs
), 0, et
.size
);
12308 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12309 same types as the MAC equivalents. The polynomial type for this instruction
12310 is encoded the same as the integer type. */
12315 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12318 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12321 if (inst
.operands
[2].isscalar
)
12322 do_neon_mac_maybe_scalar ();
12324 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12328 do_neon_qdmulh (void)
12330 if (inst
.operands
[2].isscalar
)
12332 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12333 struct neon_type_el et
= neon_check_type (3, rs
,
12334 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12335 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12336 neon_mul_mac (et
, neon_quad (rs
));
12340 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12341 struct neon_type_el et
= neon_check_type (3, rs
,
12342 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12343 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12344 /* The U bit (rounding) comes from bit mask. */
12345 neon_three_same (neon_quad (rs
), 0, et
.size
);
12350 do_neon_fcmp_absolute (void)
12352 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12353 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12354 /* Size field comes from bit mask. */
12355 neon_three_same (neon_quad (rs
), 1, -1);
12359 do_neon_fcmp_absolute_inv (void)
12361 neon_exchange_operands ();
12362 do_neon_fcmp_absolute ();
12366 do_neon_step (void)
12368 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12369 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12370 neon_three_same (neon_quad (rs
), 0, -1);
12374 do_neon_abs_neg (void)
12376 enum neon_shape rs
;
12377 struct neon_type_el et
;
12379 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12382 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12385 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12386 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12388 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12389 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12390 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12391 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12392 inst
.instruction
|= neon_quad (rs
) << 6;
12393 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12394 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12396 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12402 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12403 struct neon_type_el et
= neon_check_type (2, rs
,
12404 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12405 int imm
= inst
.operands
[2].imm
;
12406 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12407 _("immediate out of range for insert"));
12408 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12414 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12415 struct neon_type_el et
= neon_check_type (2, rs
,
12416 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12417 int imm
= inst
.operands
[2].imm
;
12418 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12419 _("immediate out of range for insert"));
12420 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12424 do_neon_qshlu_imm (void)
12426 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12427 struct neon_type_el et
= neon_check_type (2, rs
,
12428 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12429 int imm
= inst
.operands
[2].imm
;
12430 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12431 _("immediate out of range for shift"));
12432 /* Only encodes the 'U present' variant of the instruction.
12433 In this case, signed types have OP (bit 8) set to 0.
12434 Unsigned types have OP set to 1. */
12435 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12436 /* The rest of the bits are the same as other immediate shifts. */
12437 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12441 do_neon_qmovn (void)
12443 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12444 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12445 /* Saturating move where operands can be signed or unsigned, and the
12446 destination has the same signedness. */
12447 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12448 if (et
.type
== NT_unsigned
)
12449 inst
.instruction
|= 0xc0;
12451 inst
.instruction
|= 0x80;
12452 neon_two_same (0, 1, et
.size
/ 2);
12456 do_neon_qmovun (void)
12458 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12459 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12460 /* Saturating move with unsigned results. Operands must be signed. */
12461 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12462 neon_two_same (0, 1, et
.size
/ 2);
12466 do_neon_rshift_sat_narrow (void)
12468 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12469 or unsigned. If operands are unsigned, results must also be unsigned. */
12470 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12471 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12472 int imm
= inst
.operands
[2].imm
;
12473 /* This gets the bounds check, size encoding and immediate bits calculation
12477 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12478 VQMOVN.I<size> <Dd>, <Qm>. */
12481 inst
.operands
[2].present
= 0;
12482 inst
.instruction
= N_MNEM_vqmovn
;
12487 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12488 _("immediate out of range"));
12489 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12493 do_neon_rshift_sat_narrow_u (void)
12495 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12496 or unsigned. If operands are unsigned, results must also be unsigned. */
12497 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12498 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12499 int imm
= inst
.operands
[2].imm
;
12500 /* This gets the bounds check, size encoding and immediate bits calculation
12504 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12505 VQMOVUN.I<size> <Dd>, <Qm>. */
12508 inst
.operands
[2].present
= 0;
12509 inst
.instruction
= N_MNEM_vqmovun
;
12514 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12515 _("immediate out of range"));
12516 /* FIXME: The manual is kind of unclear about what value U should have in
12517 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12519 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12523 do_neon_movn (void)
12525 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12526 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12527 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12528 neon_two_same (0, 1, et
.size
/ 2);
12532 do_neon_rshift_narrow (void)
12534 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12535 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12536 int imm
= inst
.operands
[2].imm
;
12537 /* This gets the bounds check, size encoding and immediate bits calculation
12541 /* If immediate is zero then we are a pseudo-instruction for
12542 VMOVN.I<size> <Dd>, <Qm> */
12545 inst
.operands
[2].present
= 0;
12546 inst
.instruction
= N_MNEM_vmovn
;
12551 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12552 _("immediate out of range for narrowing operation"));
12553 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12557 do_neon_shll (void)
12559 /* FIXME: Type checking when lengthening. */
12560 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12561 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12562 unsigned imm
= inst
.operands
[2].imm
;
12564 if (imm
== et
.size
)
12566 /* Maximum shift variant. */
12567 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12568 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12569 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12570 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12571 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12572 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12574 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12578 /* A more-specific type check for non-max versions. */
12579 et
= neon_check_type (2, NS_QDI
,
12580 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12581 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12582 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12586 /* Check the various types for the VCVT instruction, and return which version
12587 the current instruction is. */
12590 neon_cvt_flavour (enum neon_shape rs
)
12592 #define CVT_VAR(C,X,Y) \
12593 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12594 if (et.type != NT_invtype) \
12596 inst.error = NULL; \
12599 struct neon_type_el et
;
12600 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12601 || rs
== NS_FF
) ? N_VFP
: 0;
12602 /* The instruction versions which take an immediate take one register
12603 argument, which is extended to the width of the full register. Thus the
12604 "source" and "destination" registers must have the same width. Hack that
12605 here by making the size equal to the key (wider, in this case) operand. */
12606 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12608 CVT_VAR (0, N_S32
, N_F32
);
12609 CVT_VAR (1, N_U32
, N_F32
);
12610 CVT_VAR (2, N_F32
, N_S32
);
12611 CVT_VAR (3, N_F32
, N_U32
);
12612 /* Half-precision conversions. */
12613 CVT_VAR (4, N_F32
, N_F16
);
12614 CVT_VAR (5, N_F16
, N_F32
);
12618 /* VFP instructions. */
12619 CVT_VAR (6, N_F32
, N_F64
);
12620 CVT_VAR (7, N_F64
, N_F32
);
12621 CVT_VAR (8, N_S32
, N_F64
| key
);
12622 CVT_VAR (9, N_U32
, N_F64
| key
);
12623 CVT_VAR (10, N_F64
| key
, N_S32
);
12624 CVT_VAR (11, N_F64
| key
, N_U32
);
12625 /* VFP instructions with bitshift. */
12626 CVT_VAR (12, N_F32
| key
, N_S16
);
12627 CVT_VAR (13, N_F32
| key
, N_U16
);
12628 CVT_VAR (14, N_F64
| key
, N_S16
);
12629 CVT_VAR (15, N_F64
| key
, N_U16
);
12630 CVT_VAR (16, N_S16
, N_F32
| key
);
12631 CVT_VAR (17, N_U16
, N_F32
| key
);
12632 CVT_VAR (18, N_S16
, N_F64
| key
);
12633 CVT_VAR (19, N_U16
, N_F64
| key
);
12639 /* Neon-syntax VFP conversions. */
12642 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12644 const char *opname
= 0;
12646 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12648 /* Conversions with immediate bitshift. */
12649 const char *enc
[] =
12673 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12675 opname
= enc
[flavour
];
12676 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12677 _("operands 0 and 1 must be the same register"));
12678 inst
.operands
[1] = inst
.operands
[2];
12679 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12684 /* Conversions without bitshift. */
12685 const char *enc
[] =
12701 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12702 opname
= enc
[flavour
];
12706 do_vfp_nsyn_opcode (opname
);
12710 do_vfp_nsyn_cvtz (void)
12712 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12713 int flavour
= neon_cvt_flavour (rs
);
12714 const char *enc
[] =
12728 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12729 do_vfp_nsyn_opcode (enc
[flavour
]);
12735 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12736 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
12737 int flavour
= neon_cvt_flavour (rs
);
12739 /* VFP rather than Neon conversions. */
12742 do_vfp_nsyn_cvt (rs
, flavour
);
12752 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12754 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12757 /* Fixed-point conversion with #0 immediate is encoded as an
12758 integer conversion. */
12759 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12761 immbits
= 32 - inst
.operands
[2].imm
;
12762 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12764 inst
.instruction
|= enctab
[flavour
];
12765 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12766 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12767 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12768 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12769 inst
.instruction
|= neon_quad (rs
) << 6;
12770 inst
.instruction
|= 1 << 21;
12771 inst
.instruction
|= immbits
<< 16;
12773 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12781 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12783 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12785 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12789 inst
.instruction
|= enctab
[flavour
];
12791 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12792 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12793 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12794 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12795 inst
.instruction
|= neon_quad (rs
) << 6;
12796 inst
.instruction
|= 2 << 18;
12798 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12802 /* Half-precision conversions for Advanced SIMD -- neon. */
12807 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
12809 as_bad (_("operand size must match register width"));
12814 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
12816 as_bad (_("operand size must match register width"));
12821 inst
.instruction
= 0x3b60600;
12823 inst
.instruction
= 0x3b60700;
12825 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12826 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12827 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12828 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12829 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12833 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12834 do_vfp_nsyn_cvt (rs
, flavour
);
12839 do_neon_cvtb (void)
12841 inst
.instruction
= 0xeb20a40;
12843 /* The sizes are attached to the mnemonic. */
12844 if (inst
.vectype
.el
[0].type
!= NT_invtype
12845 && inst
.vectype
.el
[0].size
== 16)
12846 inst
.instruction
|= 0x00010000;
12848 /* Programmer's syntax: the sizes are attached to the operands. */
12849 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
12850 && inst
.operands
[0].vectype
.size
== 16)
12851 inst
.instruction
|= 0x00010000;
12853 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
12854 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
12855 do_vfp_cond_or_thumb ();
12860 do_neon_cvtt (void)
12863 inst
.instruction
|= 0x80;
12867 neon_move_immediate (void)
12869 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12870 struct neon_type_el et
= neon_check_type (2, rs
,
12871 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12872 unsigned immlo
, immhi
= 0, immbits
;
12873 int op
, cmode
, float_p
;
12875 constraint (et
.type
== NT_invtype
,
12876 _("operand size must be specified for immediate VMOV"));
12878 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12879 op
= (inst
.instruction
& (1 << 5)) != 0;
12881 immlo
= inst
.operands
[1].imm
;
12882 if (inst
.operands
[1].regisimm
)
12883 immhi
= inst
.operands
[1].reg
;
12885 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12886 _("immediate has bits set outside the operand size"));
12888 float_p
= inst
.operands
[1].immisfloat
;
12890 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12891 et
.size
, et
.type
)) == FAIL
)
12893 /* Invert relevant bits only. */
12894 neon_invert_size (&immlo
, &immhi
, et
.size
);
12895 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12896 with one or the other; those cases are caught by
12897 neon_cmode_for_move_imm. */
12899 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12900 &op
, et
.size
, et
.type
)) == FAIL
)
12902 first_error (_("immediate out of range"));
12907 inst
.instruction
&= ~(1 << 5);
12908 inst
.instruction
|= op
<< 5;
12910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12912 inst
.instruction
|= neon_quad (rs
) << 6;
12913 inst
.instruction
|= cmode
<< 8;
12915 neon_write_immbits (immbits
);
12921 if (inst
.operands
[1].isreg
)
12923 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12925 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12926 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12927 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12930 inst
.instruction
|= neon_quad (rs
) << 6;
12934 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12935 neon_move_immediate ();
12938 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12941 /* Encode instructions of form:
12943 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12944 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12947 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12951 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12952 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12953 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12954 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12955 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12956 inst
.instruction
|= neon_logbits (size
) << 20;
12958 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12962 do_neon_dyadic_long (void)
12964 /* FIXME: Type checking for lengthening op. */
12965 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12966 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12967 neon_mixed_length (et
, et
.size
);
12971 do_neon_abal (void)
12973 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12974 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12975 neon_mixed_length (et
, et
.size
);
12979 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12981 if (inst
.operands
[2].isscalar
)
12983 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12984 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12985 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12986 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12990 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12991 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12992 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12993 neon_mixed_length (et
, et
.size
);
12998 do_neon_mac_maybe_scalar_long (void)
13000 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13004 do_neon_dyadic_wide (void)
13006 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13007 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13008 neon_mixed_length (et
, et
.size
);
13012 do_neon_dyadic_narrow (void)
13014 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13015 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13016 /* Operand sign is unimportant, and the U bit is part of the opcode,
13017 so force the operand type to integer. */
13018 et
.type
= NT_integer
;
13019 neon_mixed_length (et
, et
.size
/ 2);
13023 do_neon_mul_sat_scalar_long (void)
13025 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13029 do_neon_vmull (void)
13031 if (inst
.operands
[2].isscalar
)
13032 do_neon_mac_maybe_scalar_long ();
13035 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13036 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13037 if (et
.type
== NT_poly
)
13038 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13040 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13041 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13042 zero. Should be OK as-is. */
13043 neon_mixed_length (et
, et
.size
);
13050 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13051 struct neon_type_el et
= neon_check_type (3, rs
,
13052 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13053 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13055 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13056 _("shift out of range"));
13057 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13061 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13062 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13063 inst
.instruction
|= neon_quad (rs
) << 6;
13064 inst
.instruction
|= imm
<< 8;
13066 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13072 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13073 struct neon_type_el et
= neon_check_type (2, rs
,
13074 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13075 unsigned op
= (inst
.instruction
>> 7) & 3;
13076 /* N (width of reversed regions) is encoded as part of the bitmask. We
13077 extract it here to check the elements to be reversed are smaller.
13078 Otherwise we'd get a reserved instruction. */
13079 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13080 assert (elsize
!= 0);
13081 constraint (et
.size
>= elsize
,
13082 _("elements must be smaller than reversal region"));
13083 neon_two_same (neon_quad (rs
), 1, et
.size
);
13089 if (inst
.operands
[1].isscalar
)
13091 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13092 struct neon_type_el et
= neon_check_type (2, rs
,
13093 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13094 unsigned sizebits
= et
.size
>> 3;
13095 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13096 int logsize
= neon_logbits (et
.size
);
13097 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13099 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13102 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13103 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13104 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13105 inst
.instruction
|= LOW4 (dm
);
13106 inst
.instruction
|= HI1 (dm
) << 5;
13107 inst
.instruction
|= neon_quad (rs
) << 6;
13108 inst
.instruction
|= x
<< 17;
13109 inst
.instruction
|= sizebits
<< 16;
13111 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13115 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13116 struct neon_type_el et
= neon_check_type (2, rs
,
13117 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13118 /* Duplicate ARM register to lanes of vector. */
13119 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13122 case 8: inst
.instruction
|= 0x400000; break;
13123 case 16: inst
.instruction
|= 0x000020; break;
13124 case 32: inst
.instruction
|= 0x000000; break;
13127 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13128 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13129 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13130 inst
.instruction
|= neon_quad (rs
) << 21;
13131 /* The encoding for this instruction is identical for the ARM and Thumb
13132 variants, except for the condition field. */
13133 do_vfp_cond_or_thumb ();
13137 /* VMOV has particularly many variations. It can be one of:
13138 0. VMOV<c><q> <Qd>, <Qm>
13139 1. VMOV<c><q> <Dd>, <Dm>
13140 (Register operations, which are VORR with Rm = Rn.)
13141 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13142 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13144 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13145 (ARM register to scalar.)
13146 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13147 (Two ARM registers to vector.)
13148 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13149 (Scalar to ARM register.)
13150 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13151 (Vector to two ARM registers.)
13152 8. VMOV.F32 <Sd>, <Sm>
13153 9. VMOV.F64 <Dd>, <Dm>
13154 (VFP register moves.)
13155 10. VMOV.F32 <Sd>, #imm
13156 11. VMOV.F64 <Dd>, #imm
13157 (VFP float immediate load.)
13158 12. VMOV <Rd>, <Sm>
13159 (VFP single to ARM reg.)
13160 13. VMOV <Sd>, <Rm>
13161 (ARM reg to VFP single.)
13162 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13163 (Two ARM regs to two VFP singles.)
13164 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13165 (Two VFP singles to two ARM regs.)
13167 These cases can be disambiguated using neon_select_shape, except cases 1/9
13168 and 3/11 which depend on the operand type too.
13170 All the encoded bits are hardcoded by this function.
13172 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13173 Cases 5, 7 may be used with VFPv2 and above.
13175 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13176 can specify a type where it doesn't make sense to, and is ignored). */
13181 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13182 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13184 struct neon_type_el et
;
13185 const char *ldconst
= 0;
13189 case NS_DD
: /* case 1/9. */
13190 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13191 /* It is not an error here if no type is given. */
13193 if (et
.type
== NT_float
&& et
.size
== 64)
13195 do_vfp_nsyn_opcode ("fcpyd");
13198 /* fall through. */
13200 case NS_QQ
: /* case 0/1. */
13202 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13204 /* The architecture manual I have doesn't explicitly state which
13205 value the U bit should have for register->register moves, but
13206 the equivalent VORR instruction has U = 0, so do that. */
13207 inst
.instruction
= 0x0200110;
13208 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13209 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13210 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13211 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13214 inst
.instruction
|= neon_quad (rs
) << 6;
13216 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13220 case NS_DI
: /* case 3/11. */
13221 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13223 if (et
.type
== NT_float
&& et
.size
== 64)
13225 /* case 11 (fconstd). */
13226 ldconst
= "fconstd";
13227 goto encode_fconstd
;
13229 /* fall through. */
13231 case NS_QI
: /* case 2/3. */
13232 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13234 inst
.instruction
= 0x0800010;
13235 neon_move_immediate ();
13236 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13239 case NS_SR
: /* case 4. */
13241 unsigned bcdebits
= 0;
13242 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13243 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13244 int logsize
= neon_logbits (et
.size
);
13245 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13246 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13248 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13250 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13251 && et
.size
!= 32, _(BAD_FPU
));
13252 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13253 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13257 case 8: bcdebits
= 0x8; break;
13258 case 16: bcdebits
= 0x1; break;
13259 case 32: bcdebits
= 0x0; break;
13263 bcdebits
|= x
<< logsize
;
13265 inst
.instruction
= 0xe000b10;
13266 do_vfp_cond_or_thumb ();
13267 inst
.instruction
|= LOW4 (dn
) << 16;
13268 inst
.instruction
|= HI1 (dn
) << 7;
13269 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13270 inst
.instruction
|= (bcdebits
& 3) << 5;
13271 inst
.instruction
|= (bcdebits
>> 2) << 21;
13275 case NS_DRR
: /* case 5 (fmdrr). */
13276 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13279 inst
.instruction
= 0xc400b10;
13280 do_vfp_cond_or_thumb ();
13281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13283 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13284 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13287 case NS_RS
: /* case 6. */
13289 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13290 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13291 unsigned logsize
= neon_logbits (et
.size
);
13292 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13293 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13294 unsigned abcdebits
= 0;
13296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13298 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13299 && et
.size
!= 32, _(BAD_FPU
));
13300 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13301 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13305 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13306 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13307 case 32: abcdebits
= 0x00; break;
13311 abcdebits
|= x
<< logsize
;
13312 inst
.instruction
= 0xe100b10;
13313 do_vfp_cond_or_thumb ();
13314 inst
.instruction
|= LOW4 (dn
) << 16;
13315 inst
.instruction
|= HI1 (dn
) << 7;
13316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13317 inst
.instruction
|= (abcdebits
& 3) << 5;
13318 inst
.instruction
|= (abcdebits
>> 2) << 21;
13322 case NS_RRD
: /* case 7 (fmrrd). */
13323 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13326 inst
.instruction
= 0xc500b10;
13327 do_vfp_cond_or_thumb ();
13328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13329 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13330 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13331 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13334 case NS_FF
: /* case 8 (fcpys). */
13335 do_vfp_nsyn_opcode ("fcpys");
13338 case NS_FI
: /* case 10 (fconsts). */
13339 ldconst
= "fconsts";
13341 if (is_quarter_float (inst
.operands
[1].imm
))
13343 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13344 do_vfp_nsyn_opcode (ldconst
);
13347 first_error (_("immediate out of range"));
13350 case NS_RF
: /* case 12 (fmrs). */
13351 do_vfp_nsyn_opcode ("fmrs");
13354 case NS_FR
: /* case 13 (fmsr). */
13355 do_vfp_nsyn_opcode ("fmsr");
13358 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13359 (one of which is a list), but we have parsed four. Do some fiddling to
13360 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13362 case NS_RRFF
: /* case 14 (fmrrs). */
13363 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13364 _("VFP registers must be adjacent"));
13365 inst
.operands
[2].imm
= 2;
13366 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13367 do_vfp_nsyn_opcode ("fmrrs");
13370 case NS_FFRR
: /* case 15 (fmsrr). */
13371 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13372 _("VFP registers must be adjacent"));
13373 inst
.operands
[1] = inst
.operands
[2];
13374 inst
.operands
[2] = inst
.operands
[3];
13375 inst
.operands
[0].imm
= 2;
13376 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13377 do_vfp_nsyn_opcode ("fmsrr");
13386 do_neon_rshift_round_imm (void)
13388 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13389 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13390 int imm
= inst
.operands
[2].imm
;
13392 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13395 inst
.operands
[2].present
= 0;
13400 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13401 _("immediate out of range for shift"));
13402 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13407 do_neon_movl (void)
13409 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13410 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13411 unsigned sizebits
= et
.size
>> 3;
13412 inst
.instruction
|= sizebits
<< 19;
13413 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13419 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13420 struct neon_type_el et
= neon_check_type (2, rs
,
13421 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13422 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13423 neon_two_same (neon_quad (rs
), 1, et
.size
);
13427 do_neon_zip_uzp (void)
13429 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13430 struct neon_type_el et
= neon_check_type (2, rs
,
13431 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13432 if (rs
== NS_DD
&& et
.size
== 32)
13434 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13435 inst
.instruction
= N_MNEM_vtrn
;
13439 neon_two_same (neon_quad (rs
), 1, et
.size
);
13443 do_neon_sat_abs_neg (void)
13445 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13446 struct neon_type_el et
= neon_check_type (2, rs
,
13447 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13448 neon_two_same (neon_quad (rs
), 1, et
.size
);
13452 do_neon_pair_long (void)
13454 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13455 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13456 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13457 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13458 neon_two_same (neon_quad (rs
), 1, et
.size
);
13462 do_neon_recip_est (void)
13464 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13465 struct neon_type_el et
= neon_check_type (2, rs
,
13466 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13467 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13468 neon_two_same (neon_quad (rs
), 1, et
.size
);
13474 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13475 struct neon_type_el et
= neon_check_type (2, rs
,
13476 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13477 neon_two_same (neon_quad (rs
), 1, et
.size
);
13483 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13484 struct neon_type_el et
= neon_check_type (2, rs
,
13485 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13486 neon_two_same (neon_quad (rs
), 1, et
.size
);
13492 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13493 struct neon_type_el et
= neon_check_type (2, rs
,
13494 N_EQK
| N_INT
, N_8
| N_KEY
);
13495 neon_two_same (neon_quad (rs
), 1, et
.size
);
13501 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13502 neon_two_same (neon_quad (rs
), 1, -1);
13506 do_neon_tbl_tbx (void)
13508 unsigned listlenbits
;
13509 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13511 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13513 first_error (_("bad list length for table lookup"));
13517 listlenbits
= inst
.operands
[1].imm
- 1;
13518 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13519 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13520 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13521 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13522 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13523 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13524 inst
.instruction
|= listlenbits
<< 8;
13526 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13530 do_neon_ldm_stm (void)
13532 /* P, U and L bits are part of bitmask. */
13533 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13534 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13536 if (inst
.operands
[1].issingle
)
13538 do_vfp_nsyn_ldm_stm (is_dbmode
);
13542 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13543 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13545 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13546 _("register list must contain at least 1 and at most 16 "
13549 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13550 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13551 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13552 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13554 inst
.instruction
|= offsetbits
;
13556 do_vfp_cond_or_thumb ();
13560 do_neon_ldr_str (void)
13562 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13564 if (inst
.operands
[0].issingle
)
13567 do_vfp_nsyn_opcode ("flds");
13569 do_vfp_nsyn_opcode ("fsts");
13574 do_vfp_nsyn_opcode ("fldd");
13576 do_vfp_nsyn_opcode ("fstd");
13580 /* "interleave" version also handles non-interleaving register VLD1/VST1
13584 do_neon_ld_st_interleave (void)
13586 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13587 N_8
| N_16
| N_32
| N_64
);
13588 unsigned alignbits
= 0;
13590 /* The bits in this table go:
13591 0: register stride of one (0) or two (1)
13592 1,2: register list length, minus one (1, 2, 3, 4).
13593 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13594 We use -1 for invalid entries. */
13595 const int typetable
[] =
13597 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13598 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13599 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13600 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13604 if (et
.type
== NT_invtype
)
13607 if (inst
.operands
[1].immisalign
)
13608 switch (inst
.operands
[1].imm
>> 8)
13610 case 64: alignbits
= 1; break;
13612 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13613 goto bad_alignment
;
13617 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13618 goto bad_alignment
;
13623 first_error (_("bad alignment"));
13627 inst
.instruction
|= alignbits
<< 4;
13628 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13630 /* Bits [4:6] of the immediate in a list specifier encode register stride
13631 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13632 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13633 up the right value for "type" in a table based on this value and the given
13634 list style, then stick it back. */
13635 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13636 | (((inst
.instruction
>> 8) & 3) << 3);
13638 typebits
= typetable
[idx
];
13640 constraint (typebits
== -1, _("bad list type for instruction"));
13642 inst
.instruction
&= ~0xf00;
13643 inst
.instruction
|= typebits
<< 8;
13646 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13647 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13648 otherwise. The variable arguments are a list of pairs of legal (size, align)
13649 values, terminated with -1. */
13652 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13655 int result
= FAIL
, thissize
, thisalign
;
13657 if (!inst
.operands
[1].immisalign
)
13663 va_start (ap
, do_align
);
13667 thissize
= va_arg (ap
, int);
13668 if (thissize
== -1)
13670 thisalign
= va_arg (ap
, int);
13672 if (size
== thissize
&& align
== thisalign
)
13675 while (result
!= SUCCESS
);
13679 if (result
== SUCCESS
)
13682 first_error (_("unsupported alignment for instruction"));
13688 do_neon_ld_st_lane (void)
13690 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13691 int align_good
, do_align
= 0;
13692 int logsize
= neon_logbits (et
.size
);
13693 int align
= inst
.operands
[1].imm
>> 8;
13694 int n
= (inst
.instruction
>> 8) & 3;
13695 int max_el
= 64 / et
.size
;
13697 if (et
.type
== NT_invtype
)
13700 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13701 _("bad list length"));
13702 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13703 _("scalar index out of range"));
13704 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13706 _("stride of 2 unavailable when element size is 8"));
13710 case 0: /* VLD1 / VST1. */
13711 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13713 if (align_good
== FAIL
)
13717 unsigned alignbits
= 0;
13720 case 16: alignbits
= 0x1; break;
13721 case 32: alignbits
= 0x3; break;
13724 inst
.instruction
|= alignbits
<< 4;
13728 case 1: /* VLD2 / VST2. */
13729 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13731 if (align_good
== FAIL
)
13734 inst
.instruction
|= 1 << 4;
13737 case 2: /* VLD3 / VST3. */
13738 constraint (inst
.operands
[1].immisalign
,
13739 _("can't use alignment with this instruction"));
13742 case 3: /* VLD4 / VST4. */
13743 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13744 16, 64, 32, 64, 32, 128, -1);
13745 if (align_good
== FAIL
)
13749 unsigned alignbits
= 0;
13752 case 8: alignbits
= 0x1; break;
13753 case 16: alignbits
= 0x1; break;
13754 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13757 inst
.instruction
|= alignbits
<< 4;
13764 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13765 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13766 inst
.instruction
|= 1 << (4 + logsize
);
13768 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13769 inst
.instruction
|= logsize
<< 10;
13772 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13775 do_neon_ld_dup (void)
13777 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13778 int align_good
, do_align
= 0;
13780 if (et
.type
== NT_invtype
)
13783 switch ((inst
.instruction
>> 8) & 3)
13785 case 0: /* VLD1. */
13786 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13787 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13788 &do_align
, 16, 16, 32, 32, -1);
13789 if (align_good
== FAIL
)
13791 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13794 case 2: inst
.instruction
|= 1 << 5; break;
13795 default: first_error (_("bad list length")); return;
13797 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13800 case 1: /* VLD2. */
13801 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13802 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13803 if (align_good
== FAIL
)
13805 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13806 _("bad list length"));
13807 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13808 inst
.instruction
|= 1 << 5;
13809 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13812 case 2: /* VLD3. */
13813 constraint (inst
.operands
[1].immisalign
,
13814 _("can't use alignment with this instruction"));
13815 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13816 _("bad list length"));
13817 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13818 inst
.instruction
|= 1 << 5;
13819 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13822 case 3: /* VLD4. */
13824 int align
= inst
.operands
[1].imm
>> 8;
13825 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13826 16, 64, 32, 64, 32, 128, -1);
13827 if (align_good
== FAIL
)
13829 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13830 _("bad list length"));
13831 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13832 inst
.instruction
|= 1 << 5;
13833 if (et
.size
== 32 && align
== 128)
13834 inst
.instruction
|= 0x3 << 6;
13836 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13843 inst
.instruction
|= do_align
<< 4;
13846 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13847 apart from bits [11:4]. */
13850 do_neon_ldx_stx (void)
13852 switch (NEON_LANE (inst
.operands
[0].imm
))
13854 case NEON_INTERLEAVE_LANES
:
13855 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13856 do_neon_ld_st_interleave ();
13859 case NEON_ALL_LANES
:
13860 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13865 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13866 do_neon_ld_st_lane ();
13869 /* L bit comes from bit mask. */
13870 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13871 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13874 if (inst
.operands
[1].postind
)
13876 int postreg
= inst
.operands
[1].imm
& 0xf;
13877 constraint (!inst
.operands
[1].immisreg
,
13878 _("post-index must be a register"));
13879 constraint (postreg
== 0xd || postreg
== 0xf,
13880 _("bad register for post-index"));
13881 inst
.instruction
|= postreg
;
13883 else if (inst
.operands
[1].writeback
)
13885 inst
.instruction
|= 0xd;
13888 inst
.instruction
|= 0xf;
13891 inst
.instruction
|= 0xf9000000;
13893 inst
.instruction
|= 0xf4000000;
13896 /* Overall per-instruction processing. */
13898 /* We need to be able to fix up arbitrary expressions in some statements.
13899 This is so that we can handle symbols that are an arbitrary distance from
13900 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13901 which returns part of an address in a form which will be valid for
13902 a data instruction. We do this by pushing the expression into a symbol
13903 in the expr_section, and creating a fix for that. */
13906 fix_new_arm (fragS
* frag
,
13921 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13925 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13930 /* Mark whether the fix is to a THUMB instruction, or an ARM
13932 new_fix
->tc_fix_data
= thumb_mode
;
13935 /* Create a frg for an instruction requiring relaxation. */
13937 output_relax_insn (void)
13943 /* The size of the instruction is unknown, so tie the debug info to the
13944 start of the instruction. */
13945 dwarf2_emit_insn (0);
13947 switch (inst
.reloc
.exp
.X_op
)
13950 sym
= inst
.reloc
.exp
.X_add_symbol
;
13951 offset
= inst
.reloc
.exp
.X_add_number
;
13955 offset
= inst
.reloc
.exp
.X_add_number
;
13958 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13962 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13963 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13964 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13967 /* Write a 32-bit thumb instruction to buf. */
13969 put_thumb32_insn (char * buf
, unsigned long insn
)
13971 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13972 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13976 output_inst (const char * str
)
13982 as_bad ("%s -- `%s'", inst
.error
, str
);
13987 output_relax_insn ();
13990 if (inst
.size
== 0)
13993 to
= frag_more (inst
.size
);
13995 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13997 assert (inst
.size
== (2 * THUMB_SIZE
));
13998 put_thumb32_insn (to
, inst
.instruction
);
14000 else if (inst
.size
> INSN_SIZE
)
14002 assert (inst
.size
== (2 * INSN_SIZE
));
14003 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14004 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14007 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14009 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14010 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14011 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14014 dwarf2_emit_insn (inst
.size
);
14017 /* Tag values used in struct asm_opcode's tag field. */
14020 OT_unconditional
, /* Instruction cannot be conditionalized.
14021 The ARM condition field is still 0xE. */
14022 OT_unconditionalF
, /* Instruction cannot be conditionalized
14023 and carries 0xF in its ARM condition field. */
14024 OT_csuffix
, /* Instruction takes a conditional suffix. */
14025 OT_csuffixF
, /* Some forms of the instruction take a conditional
14026 suffix, others place 0xF where the condition field
14028 OT_cinfix3
, /* Instruction takes a conditional infix,
14029 beginning at character index 3. (In
14030 unified mode, it becomes a suffix.) */
14031 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14032 tsts, cmps, cmns, and teqs. */
14033 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14034 character index 3, even in unified mode. Used for
14035 legacy instructions where suffix and infix forms
14036 may be ambiguous. */
14037 OT_csuf_or_in3
, /* Instruction takes either a conditional
14038 suffix or an infix at character index 3. */
14039 OT_odd_infix_unc
, /* This is the unconditional variant of an
14040 instruction that takes a conditional infix
14041 at an unusual position. In unified mode,
14042 this variant will accept a suffix. */
14043 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14044 are the conditional variants of instructions that
14045 take conditional infixes in unusual positions.
14046 The infix appears at character index
14047 (tag - OT_odd_infix_0). These are not accepted
14048 in unified mode. */
14051 /* Subroutine of md_assemble, responsible for looking up the primary
14052 opcode from the mnemonic the user wrote. STR points to the
14053 beginning of the mnemonic.
14055 This is not simply a hash table lookup, because of conditional
14056 variants. Most instructions have conditional variants, which are
14057 expressed with a _conditional affix_ to the mnemonic. If we were
14058 to encode each conditional variant as a literal string in the opcode
14059 table, it would have approximately 20,000 entries.
14061 Most mnemonics take this affix as a suffix, and in unified syntax,
14062 'most' is upgraded to 'all'. However, in the divided syntax, some
14063 instructions take the affix as an infix, notably the s-variants of
14064 the arithmetic instructions. Of those instructions, all but six
14065 have the infix appear after the third character of the mnemonic.
14067 Accordingly, the algorithm for looking up primary opcodes given
14070 1. Look up the identifier in the opcode table.
14071 If we find a match, go to step U.
14073 2. Look up the last two characters of the identifier in the
14074 conditions table. If we find a match, look up the first N-2
14075 characters of the identifier in the opcode table. If we
14076 find a match, go to step CE.
14078 3. Look up the fourth and fifth characters of the identifier in
14079 the conditions table. If we find a match, extract those
14080 characters from the identifier, and look up the remaining
14081 characters in the opcode table. If we find a match, go
14086 U. Examine the tag field of the opcode structure, in case this is
14087 one of the six instructions with its conditional infix in an
14088 unusual place. If it is, the tag tells us where to find the
14089 infix; look it up in the conditions table and set inst.cond
14090 accordingly. Otherwise, this is an unconditional instruction.
14091 Again set inst.cond accordingly. Return the opcode structure.
14093 CE. Examine the tag field to make sure this is an instruction that
14094 should receive a conditional suffix. If it is not, fail.
14095 Otherwise, set inst.cond from the suffix we already looked up,
14096 and return the opcode structure.
14098 CM. Examine the tag field to make sure this is an instruction that
14099 should receive a conditional infix after the third character.
14100 If it is not, fail. Otherwise, undo the edits to the current
14101 line of input and proceed as for case CE. */
14103 static const struct asm_opcode
*
14104 opcode_lookup (char **str
)
14108 const struct asm_opcode
*opcode
;
14109 const struct asm_cond
*cond
;
14111 bfd_boolean neon_supported
;
14113 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14115 /* Scan up to the end of the mnemonic, which must end in white space,
14116 '.' (in unified mode, or for Neon instructions), or end of string. */
14117 for (base
= end
= *str
; *end
!= '\0'; end
++)
14118 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14124 /* Handle a possible width suffix and/or Neon type suffix. */
14129 /* The .w and .n suffixes are only valid if the unified syntax is in
14131 if (unified_syntax
&& end
[1] == 'w')
14133 else if (unified_syntax
&& end
[1] == 'n')
14138 inst
.vectype
.elems
= 0;
14140 *str
= end
+ offset
;
14142 if (end
[offset
] == '.')
14144 /* See if we have a Neon type suffix (possible in either unified or
14145 non-unified ARM syntax mode). */
14146 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14149 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14155 /* Look for unaffixed or special-case affixed mnemonic. */
14156 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14160 if (opcode
->tag
< OT_odd_infix_0
)
14162 inst
.cond
= COND_ALWAYS
;
14166 if (warn_on_deprecated
&& unified_syntax
)
14167 as_warn (_("conditional infixes are deprecated in unified syntax"));
14168 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14169 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14172 inst
.cond
= cond
->value
;
14176 /* Cannot have a conditional suffix on a mnemonic of less than two
14178 if (end
- base
< 3)
14181 /* Look for suffixed mnemonic. */
14183 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14184 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14185 if (opcode
&& cond
)
14188 switch (opcode
->tag
)
14190 case OT_cinfix3_legacy
:
14191 /* Ignore conditional suffixes matched on infix only mnemonics. */
14195 case OT_cinfix3_deprecated
:
14196 case OT_odd_infix_unc
:
14197 if (!unified_syntax
)
14199 /* else fall through */
14203 case OT_csuf_or_in3
:
14204 inst
.cond
= cond
->value
;
14207 case OT_unconditional
:
14208 case OT_unconditionalF
:
14211 inst
.cond
= cond
->value
;
14215 /* delayed diagnostic */
14216 inst
.error
= BAD_COND
;
14217 inst
.cond
= COND_ALWAYS
;
14226 /* Cannot have a usual-position infix on a mnemonic of less than
14227 six characters (five would be a suffix). */
14228 if (end
- base
< 6)
14231 /* Look for infixed mnemonic in the usual position. */
14233 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14237 memcpy (save
, affix
, 2);
14238 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14239 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14240 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14241 memcpy (affix
, save
, 2);
14244 && (opcode
->tag
== OT_cinfix3
14245 || opcode
->tag
== OT_cinfix3_deprecated
14246 || opcode
->tag
== OT_csuf_or_in3
14247 || opcode
->tag
== OT_cinfix3_legacy
))
14250 if (warn_on_deprecated
&& unified_syntax
14251 && (opcode
->tag
== OT_cinfix3
14252 || opcode
->tag
== OT_cinfix3_deprecated
))
14253 as_warn (_("conditional infixes are deprecated in unified syntax"));
14255 inst
.cond
= cond
->value
;
14263 md_assemble (char *str
)
14266 const struct asm_opcode
* opcode
;
14268 /* Align the previous label if needed. */
14269 if (last_label_seen
!= NULL
)
14271 symbol_set_frag (last_label_seen
, frag_now
);
14272 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14273 S_SET_SEGMENT (last_label_seen
, now_seg
);
14276 memset (&inst
, '\0', sizeof (inst
));
14277 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14279 opcode
= opcode_lookup (&p
);
14282 /* It wasn't an instruction, but it might be a register alias of
14283 the form alias .req reg, or a Neon .dn/.qn directive. */
14284 if (!create_register_alias (str
, p
)
14285 && !create_neon_reg_alias (str
, p
))
14286 as_bad (_("bad instruction `%s'"), str
);
14291 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
14292 as_warn (_("s suffix on comparison instruction is deprecated"));
14294 /* The value which unconditional instructions should have in place of the
14295 condition field. */
14296 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14300 arm_feature_set variant
;
14302 variant
= cpu_variant
;
14303 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14304 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14305 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14306 /* Check that this instruction is supported for this CPU. */
14307 if (!opcode
->tvariant
14308 || (thumb_mode
== 1
14309 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14311 as_bad (_("selected processor does not support `%s'"), str
);
14314 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14315 && opcode
->tencode
!= do_t_branch
)
14317 as_bad (_("Thumb does not support conditional execution"));
14321 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14323 /* Implicit require narrow instructions on Thumb-1. This avoids
14324 relaxation accidentally introducing Thumb-2 instructions. */
14325 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14326 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14330 /* Check conditional suffixes. */
14331 if (current_it_mask
)
14334 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14335 current_it_mask
<<= 1;
14336 current_it_mask
&= 0x1f;
14337 /* The BKPT instruction is unconditional even in an IT block. */
14339 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14341 as_bad (_("incorrect condition in IT block"));
14345 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14347 as_bad (_("thumb conditional instruction not in IT block"));
14351 mapping_state (MAP_THUMB
);
14352 inst
.instruction
= opcode
->tvalue
;
14354 if (!parse_operands (p
, opcode
->operands
))
14355 opcode
->tencode ();
14357 /* Clear current_it_mask at the end of an IT block. */
14358 if (current_it_mask
== 0x10)
14359 current_it_mask
= 0;
14361 if (!(inst
.error
|| inst
.relax
))
14363 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14364 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14365 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14367 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14372 /* Something has gone badly wrong if we try to relax a fixed size
14374 assert (inst
.size_req
== 0 || !inst
.relax
);
14376 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14377 *opcode
->tvariant
);
14378 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14379 set those bits when Thumb-2 32-bit instructions are seen. ie.
14380 anything other than bl/blx and v6-M instructions.
14381 This is overly pessimistic for relaxable instructions. */
14382 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14384 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14385 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14388 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14392 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14393 is_bx
= (opcode
->aencode
== do_bx
);
14395 /* Check that this instruction is supported for this CPU. */
14396 if (!(is_bx
&& fix_v4bx
)
14397 && !(opcode
->avariant
&&
14398 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14400 as_bad (_("selected processor does not support `%s'"), str
);
14405 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14409 mapping_state (MAP_ARM
);
14410 inst
.instruction
= opcode
->avalue
;
14411 if (opcode
->tag
== OT_unconditionalF
)
14412 inst
.instruction
|= 0xF << 28;
14414 inst
.instruction
|= inst
.cond
<< 28;
14415 inst
.size
= INSN_SIZE
;
14416 if (!parse_operands (p
, opcode
->operands
))
14417 opcode
->aencode ();
14418 /* Arm mode bx is marked as both v4T and v5 because it's still required
14419 on a hypothetical non-thumb v5 core. */
14421 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14423 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14424 *opcode
->avariant
);
14428 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14435 /* Various frobbings of labels and their addresses. */
14438 arm_start_line_hook (void)
14440 last_label_seen
= NULL
;
14444 arm_frob_label (symbolS
* sym
)
14446 last_label_seen
= sym
;
14448 ARM_SET_THUMB (sym
, thumb_mode
);
14450 #if defined OBJ_COFF || defined OBJ_ELF
14451 ARM_SET_INTERWORK (sym
, support_interwork
);
14454 /* Note - do not allow local symbols (.Lxxx) to be labelled
14455 as Thumb functions. This is because these labels, whilst
14456 they exist inside Thumb code, are not the entry points for
14457 possible ARM->Thumb calls. Also, these labels can be used
14458 as part of a computed goto or switch statement. eg gcc
14459 can generate code that looks like this:
14461 ldr r2, [pc, .Laaa]
14471 The first instruction loads the address of the jump table.
14472 The second instruction converts a table index into a byte offset.
14473 The third instruction gets the jump address out of the table.
14474 The fourth instruction performs the jump.
14476 If the address stored at .Laaa is that of a symbol which has the
14477 Thumb_Func bit set, then the linker will arrange for this address
14478 to have the bottom bit set, which in turn would mean that the
14479 address computation performed by the third instruction would end
14480 up with the bottom bit set. Since the ARM is capable of unaligned
14481 word loads, the instruction would then load the incorrect address
14482 out of the jump table, and chaos would ensue. */
14483 if (label_is_thumb_function_name
14484 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14485 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14487 /* When the address of a Thumb function is taken the bottom
14488 bit of that address should be set. This will allow
14489 interworking between Arm and Thumb functions to work
14492 THUMB_SET_FUNC (sym
, 1);
14494 label_is_thumb_function_name
= FALSE
;
14497 dwarf2_emit_label (sym
);
14501 arm_data_in_code (void)
14503 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14505 *input_line_pointer
= '/';
14506 input_line_pointer
+= 5;
14507 *input_line_pointer
= 0;
14515 arm_canonicalize_symbol_name (char * name
)
14519 if (thumb_mode
&& (len
= strlen (name
)) > 5
14520 && streq (name
+ len
- 5, "/data"))
14521 *(name
+ len
- 5) = 0;
14526 /* Table of all register names defined by default. The user can
14527 define additional names with .req. Note that all register names
14528 should appear in both upper and lowercase variants. Some registers
14529 also have mixed-case names. */
14531 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14532 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14533 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14534 #define REGSET(p,t) \
14535 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14536 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14537 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14538 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14539 #define REGSETH(p,t) \
14540 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14541 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14542 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14543 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14544 #define REGSET2(p,t) \
14545 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14546 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14547 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14548 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14550 static const struct reg_entry reg_names
[] =
14552 /* ARM integer registers. */
14553 REGSET(r
, RN
), REGSET(R
, RN
),
14555 /* ATPCS synonyms. */
14556 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14557 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14558 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14560 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14561 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14562 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14564 /* Well-known aliases. */
14565 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14566 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14568 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14569 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14571 /* Coprocessor numbers. */
14572 REGSET(p
, CP
), REGSET(P
, CP
),
14574 /* Coprocessor register numbers. The "cr" variants are for backward
14576 REGSET(c
, CN
), REGSET(C
, CN
),
14577 REGSET(cr
, CN
), REGSET(CR
, CN
),
14579 /* FPA registers. */
14580 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14581 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14583 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14584 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14586 /* VFP SP registers. */
14587 REGSET(s
,VFS
), REGSET(S
,VFS
),
14588 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14590 /* VFP DP Registers. */
14591 REGSET(d
,VFD
), REGSET(D
,VFD
),
14592 /* Extra Neon DP registers. */
14593 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14595 /* Neon QP registers. */
14596 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14598 /* VFP control registers. */
14599 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14600 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14601 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14602 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14603 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14604 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14606 /* Maverick DSP coprocessor registers. */
14607 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14608 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14610 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14611 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14612 REGDEF(dspsc
,0,DSPSC
),
14614 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14615 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14616 REGDEF(DSPSC
,0,DSPSC
),
14618 /* iWMMXt data registers - p0, c0-15. */
14619 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14621 /* iWMMXt control registers - p1, c0-3. */
14622 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14623 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14624 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14625 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14627 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14628 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14629 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14630 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14631 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14633 /* XScale accumulator registers. */
14634 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14640 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14641 within psr_required_here. */
14642 static const struct asm_psr psrs
[] =
14644 /* Backward compatibility notation. Note that "all" is no longer
14645 truly all possible PSR bits. */
14646 {"all", PSR_c
| PSR_f
},
14650 /* Individual flags. */
14655 /* Combinations of flags. */
14656 {"fs", PSR_f
| PSR_s
},
14657 {"fx", PSR_f
| PSR_x
},
14658 {"fc", PSR_f
| PSR_c
},
14659 {"sf", PSR_s
| PSR_f
},
14660 {"sx", PSR_s
| PSR_x
},
14661 {"sc", PSR_s
| PSR_c
},
14662 {"xf", PSR_x
| PSR_f
},
14663 {"xs", PSR_x
| PSR_s
},
14664 {"xc", PSR_x
| PSR_c
},
14665 {"cf", PSR_c
| PSR_f
},
14666 {"cs", PSR_c
| PSR_s
},
14667 {"cx", PSR_c
| PSR_x
},
14668 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14669 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14670 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14671 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14672 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14673 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14674 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14675 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14676 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14677 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14678 {"scf", PSR_s
| PSR_c
| PSR_f
},
14679 {"scx", PSR_s
| PSR_c
| PSR_x
},
14680 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14681 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14682 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14683 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14684 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14685 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14686 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14687 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14688 {"csf", PSR_c
| PSR_s
| PSR_f
},
14689 {"csx", PSR_c
| PSR_s
| PSR_x
},
14690 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14691 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14692 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14693 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14694 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14695 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14696 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14697 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14698 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14699 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14700 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14701 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14702 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14703 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14704 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14705 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14706 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14707 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14708 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14709 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14710 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14711 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14712 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14713 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14714 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14715 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14718 /* Table of V7M psr names. */
14719 static const struct asm_psr v7m_psrs
[] =
14721 {"apsr", 0 }, {"APSR", 0 },
14722 {"iapsr", 1 }, {"IAPSR", 1 },
14723 {"eapsr", 2 }, {"EAPSR", 2 },
14724 {"psr", 3 }, {"PSR", 3 },
14725 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14726 {"ipsr", 5 }, {"IPSR", 5 },
14727 {"epsr", 6 }, {"EPSR", 6 },
14728 {"iepsr", 7 }, {"IEPSR", 7 },
14729 {"msp", 8 }, {"MSP", 8 },
14730 {"psp", 9 }, {"PSP", 9 },
14731 {"primask", 16}, {"PRIMASK", 16},
14732 {"basepri", 17}, {"BASEPRI", 17},
14733 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14734 {"faultmask", 19}, {"FAULTMASK", 19},
14735 {"control", 20}, {"CONTROL", 20}
14738 /* Table of all shift-in-operand names. */
14739 static const struct asm_shift_name shift_names
[] =
14741 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14742 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14743 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14744 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14745 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14746 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14749 /* Table of all explicit relocation names. */
14751 static struct reloc_entry reloc_names
[] =
14753 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14754 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14755 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14756 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14757 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14758 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14759 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14760 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14761 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14762 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14763 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14767 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14768 static const struct asm_cond conds
[] =
14772 {"cs", 0x2}, {"hs", 0x2},
14773 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14787 static struct asm_barrier_opt barrier_opt_names
[] =
14795 /* Table of ARM-format instructions. */
14797 /* Macros for gluing together operand strings. N.B. In all cases
14798 other than OPS0, the trailing OP_stop comes from default
14799 zero-initialization of the unspecified elements of the array. */
14800 #define OPS0() { OP_stop, }
14801 #define OPS1(a) { OP_##a, }
14802 #define OPS2(a,b) { OP_##a,OP_##b, }
14803 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14804 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14805 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14806 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14808 /* These macros abstract out the exact format of the mnemonic table and
14809 save some repeated characters. */
14811 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14812 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14813 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14814 THUMB_VARIANT, do_##ae, do_##te }
14816 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14817 a T_MNEM_xyz enumerator. */
14818 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14819 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14820 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14821 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14823 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14824 infix after the third character. */
14825 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14826 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14827 THUMB_VARIANT, do_##ae, do_##te }
14828 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14829 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14830 THUMB_VARIANT, do_##ae, do_##te }
14831 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14832 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14833 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14834 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14835 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14836 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14837 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14838 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14840 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14841 appear in the condition table. */
14842 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14843 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14844 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14846 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14847 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14848 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14849 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14850 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14851 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14852 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14853 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14854 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14855 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14856 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14857 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14858 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14859 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14860 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14861 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14862 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14863 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14864 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14865 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14867 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14868 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14869 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14870 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14872 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14873 field is still 0xE. Many of the Thumb variants can be executed
14874 conditionally, so this is checked separately. */
14875 #define TUE(mnem, op, top, nops, ops, ae, te) \
14876 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14877 THUMB_VARIANT, do_##ae, do_##te }
14879 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14880 condition code field. */
14881 #define TUF(mnem, op, top, nops, ops, ae, te) \
14882 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14883 THUMB_VARIANT, do_##ae, do_##te }
14885 /* ARM-only variants of all the above. */
14886 #define CE(mnem, op, nops, ops, ae) \
14887 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14889 #define C3(mnem, op, nops, ops, ae) \
14890 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14892 /* Legacy mnemonics that always have conditional infix after the third
14894 #define CL(mnem, op, nops, ops, ae) \
14895 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14896 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14898 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14899 #define cCE(mnem, op, nops, ops, ae) \
14900 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14902 /* Legacy coprocessor instructions where conditional infix and conditional
14903 suffix are ambiguous. For consistency this includes all FPA instructions,
14904 not just the potentially ambiguous ones. */
14905 #define cCL(mnem, op, nops, ops, ae) \
14906 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14907 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14909 /* Coprocessor, takes either a suffix or a position-3 infix
14910 (for an FPA corner case). */
14911 #define C3E(mnem, op, nops, ops, ae) \
14912 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14913 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14915 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14916 { #m1 #m2 #m3, OPS##nops ops, \
14917 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14918 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14920 #define CM(m1, m2, op, nops, ops, ae) \
14921 xCM_(m1, , m2, op, nops, ops, ae), \
14922 xCM_(m1, eq, m2, op, nops, ops, ae), \
14923 xCM_(m1, ne, m2, op, nops, ops, ae), \
14924 xCM_(m1, cs, m2, op, nops, ops, ae), \
14925 xCM_(m1, hs, m2, op, nops, ops, ae), \
14926 xCM_(m1, cc, m2, op, nops, ops, ae), \
14927 xCM_(m1, ul, m2, op, nops, ops, ae), \
14928 xCM_(m1, lo, m2, op, nops, ops, ae), \
14929 xCM_(m1, mi, m2, op, nops, ops, ae), \
14930 xCM_(m1, pl, m2, op, nops, ops, ae), \
14931 xCM_(m1, vs, m2, op, nops, ops, ae), \
14932 xCM_(m1, vc, m2, op, nops, ops, ae), \
14933 xCM_(m1, hi, m2, op, nops, ops, ae), \
14934 xCM_(m1, ls, m2, op, nops, ops, ae), \
14935 xCM_(m1, ge, m2, op, nops, ops, ae), \
14936 xCM_(m1, lt, m2, op, nops, ops, ae), \
14937 xCM_(m1, gt, m2, op, nops, ops, ae), \
14938 xCM_(m1, le, m2, op, nops, ops, ae), \
14939 xCM_(m1, al, m2, op, nops, ops, ae)
14941 #define UE(mnem, op, nops, ops, ae) \
14942 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14944 #define UF(mnem, op, nops, ops, ae) \
14945 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14947 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14948 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14949 use the same encoding function for each. */
14950 #define NUF(mnem, op, nops, ops, enc) \
14951 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14952 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14954 /* Neon data processing, version which indirects through neon_enc_tab for
14955 the various overloaded versions of opcodes. */
14956 #define nUF(mnem, op, nops, ops, enc) \
14957 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14958 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14960 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14962 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14963 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14964 THUMB_VARIANT, do_##enc, do_##enc }
14966 #define NCE(mnem, op, nops, ops, enc) \
14967 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14969 #define NCEF(mnem, op, nops, ops, enc) \
14970 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14972 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14973 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14974 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14975 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14977 #define nCE(mnem, op, nops, ops, enc) \
14978 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14980 #define nCEF(mnem, op, nops, ops, enc) \
14981 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14985 /* Thumb-only, unconditional. */
14986 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14988 static const struct asm_opcode insns
[] =
14990 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14991 #define THUMB_VARIANT &arm_ext_v4t
14992 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14993 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14994 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14995 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14996 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14997 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14998 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14999 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15000 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15001 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15002 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15003 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15004 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15005 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15006 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15007 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15009 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15010 for setting PSR flag bits. They are obsolete in V6 and do not
15011 have Thumb equivalents. */
15012 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15013 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15014 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15015 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15016 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15017 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15018 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15019 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15020 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15022 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15023 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15024 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15025 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15027 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15028 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15029 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15030 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15032 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15033 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15034 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15035 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15036 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15037 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15039 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15040 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15041 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15042 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15045 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15046 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15047 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15049 /* Thumb-compatibility pseudo ops. */
15050 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15051 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15052 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15053 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15054 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15055 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15056 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15057 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15058 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15059 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15060 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15061 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15063 /* These may simplify to neg. */
15064 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15065 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15067 #undef THUMB_VARIANT
15068 #define THUMB_VARIANT &arm_ext_v6
15069 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15071 /* V1 instructions with no Thumb analogue prior to V6T2. */
15072 #undef THUMB_VARIANT
15073 #define THUMB_VARIANT &arm_ext_v6t2
15074 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15075 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15076 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15078 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15079 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15080 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15081 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15083 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15084 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15086 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15087 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15089 /* V1 instructions with no Thumb analogue at all. */
15090 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15091 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15093 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15094 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15095 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15096 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15097 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15098 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15099 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15100 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15103 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15104 #undef THUMB_VARIANT
15105 #define THUMB_VARIANT &arm_ext_v4t
15106 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15107 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15109 #undef THUMB_VARIANT
15110 #define THUMB_VARIANT &arm_ext_v6t2
15111 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15112 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15114 /* Generic coprocessor instructions. */
15115 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15116 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15117 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15118 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15119 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15120 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15121 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15124 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15125 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15126 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15129 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15130 #undef THUMB_VARIANT
15131 #define THUMB_VARIANT &arm_ext_msr
15132 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15133 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15136 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15137 #undef THUMB_VARIANT
15138 #define THUMB_VARIANT &arm_ext_v6t2
15139 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15140 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15141 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15142 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15143 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15144 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15145 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15146 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15149 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15150 #undef THUMB_VARIANT
15151 #define THUMB_VARIANT &arm_ext_v4t
15152 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15153 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15154 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15155 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15156 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15157 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15160 #define ARM_VARIANT &arm_ext_v4t_5
15161 /* ARM Architecture 4T. */
15162 /* Note: bx (and blx) are required on V5, even if the processor does
15163 not support Thumb. */
15164 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15167 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15168 #undef THUMB_VARIANT
15169 #define THUMB_VARIANT &arm_ext_v5t
15170 /* Note: blx has 2 variants; the .value coded here is for
15171 BLX(2). Only this variant has conditional execution. */
15172 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15173 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15175 #undef THUMB_VARIANT
15176 #define THUMB_VARIANT &arm_ext_v6t2
15177 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15178 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15179 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15180 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15181 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15182 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15183 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15184 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15187 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15188 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15189 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15190 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15191 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15193 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15194 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15196 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15197 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15198 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15199 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15201 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15202 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15203 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15204 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15206 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15207 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15209 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15210 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15211 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15212 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15215 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15216 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15217 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15218 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15220 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15221 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15224 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15225 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15228 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15229 #undef THUMB_VARIANT
15230 #define THUMB_VARIANT &arm_ext_v6
15231 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15232 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15233 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15234 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15235 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15236 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15237 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15238 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15239 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15240 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15242 #undef THUMB_VARIANT
15243 #define THUMB_VARIANT &arm_ext_v6t2
15244 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15245 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15246 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15247 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15249 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15250 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15252 /* ARM V6 not included in V7M (eg. integer SIMD). */
15253 #undef THUMB_VARIANT
15254 #define THUMB_VARIANT &arm_ext_v6_notm
15255 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15256 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15257 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15258 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15259 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15260 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15261 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15262 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15263 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15264 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15265 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15266 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15267 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15268 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15269 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15270 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15271 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15272 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15273 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15274 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15275 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15276 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15277 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15278 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15279 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15280 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15281 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15282 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15283 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15284 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15285 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15286 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15287 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15288 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15289 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15290 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15291 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15292 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15293 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15294 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15295 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15296 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15297 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15298 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15299 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15300 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15301 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15302 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15303 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15304 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15305 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15306 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15307 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15308 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15309 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15310 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15311 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15312 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15313 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15314 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15315 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15316 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15317 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15318 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15319 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15320 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15321 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15322 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15323 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15324 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15325 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15326 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15327 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15328 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15329 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15330 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15331 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15332 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15333 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15334 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15335 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15336 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15337 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15340 #define ARM_VARIANT &arm_ext_v6k
15341 #undef THUMB_VARIANT
15342 #define THUMB_VARIANT &arm_ext_v6k
15343 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15344 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15345 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15346 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15348 #undef THUMB_VARIANT
15349 #define THUMB_VARIANT &arm_ext_v6_notm
15350 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15351 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15353 #undef THUMB_VARIANT
15354 #define THUMB_VARIANT &arm_ext_v6t2
15355 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15356 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15357 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15358 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15359 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15362 #define ARM_VARIANT &arm_ext_v6z
15363 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15366 #define ARM_VARIANT &arm_ext_v6t2
15367 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15368 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15369 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15370 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15372 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15373 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15374 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15375 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15377 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15378 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15379 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15380 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15382 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15383 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15384 /* ARM does not really have an IT instruction, so always allow it. */
15386 #define ARM_VARIANT &arm_ext_v1
15387 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15388 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15389 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15390 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15391 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15392 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15393 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15394 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15395 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15396 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15397 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15398 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15399 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15400 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15401 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15403 /* Thumb2 only instructions. */
15405 #define ARM_VARIANT NULL
15407 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15408 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15409 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15410 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15412 /* Thumb-2 hardware division instructions (R and M profiles only). */
15413 #undef THUMB_VARIANT
15414 #define THUMB_VARIANT &arm_ext_div
15415 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15416 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15418 /* ARM V6M/V7 instructions. */
15420 #define ARM_VARIANT &arm_ext_barrier
15421 #undef THUMB_VARIANT
15422 #define THUMB_VARIANT &arm_ext_barrier
15423 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15424 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15425 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15427 /* ARM V7 instructions. */
15429 #define ARM_VARIANT &arm_ext_v7
15430 #undef THUMB_VARIANT
15431 #define THUMB_VARIANT &arm_ext_v7
15432 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15433 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15436 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15437 cCE(wfs
, e200110
, 1, (RR
), rd
),
15438 cCE(rfs
, e300110
, 1, (RR
), rd
),
15439 cCE(wfc
, e400110
, 1, (RR
), rd
),
15440 cCE(rfc
, e500110
, 1, (RR
), rd
),
15442 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15443 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15444 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15445 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15447 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15448 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15449 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15450 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15452 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15527 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15535 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15537 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15539 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15540 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15548 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15550 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15552 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15553 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15554 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15556 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15557 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15558 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15559 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15560 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15561 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15562 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15563 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15564 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15565 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15566 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15567 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15569 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15570 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15571 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15572 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15573 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15574 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15575 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15576 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15577 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15578 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15579 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15580 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15582 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15583 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15584 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15585 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15586 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15587 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15588 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15589 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15590 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15591 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15592 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15593 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15595 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15596 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15597 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15598 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15599 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15600 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15601 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15602 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15603 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15604 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15605 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15606 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15608 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15609 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15610 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15611 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15612 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15613 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15614 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15615 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15616 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15617 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15618 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15619 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15621 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15622 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15623 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15624 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15625 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15626 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15627 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15628 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15629 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15630 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15631 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15632 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15634 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15635 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15636 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15637 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15638 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15639 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15640 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15641 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15642 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15643 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15644 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15645 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15647 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15648 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15649 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15650 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15651 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15652 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15653 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15654 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15655 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15656 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15657 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15658 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15660 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15696 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15704 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15706 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15708 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15709 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15717 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15719 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15720 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15721 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15722 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15723 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15725 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15726 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15727 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15728 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15729 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15730 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15731 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15732 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15733 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15734 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15735 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15736 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15738 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15739 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15740 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15741 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15742 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15743 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15744 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15745 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15746 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15747 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15748 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15749 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15751 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15752 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15753 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15754 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15755 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15756 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15757 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15758 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15759 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15760 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15761 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15762 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15764 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15765 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15766 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15767 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15768 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15769 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15770 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15771 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15772 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15773 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15774 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15775 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15777 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15778 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15779 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15780 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15781 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15782 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15783 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15784 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15785 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15786 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15787 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15788 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15790 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15791 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15792 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15793 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15794 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15795 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15796 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15797 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15798 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15799 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15800 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15801 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15803 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15804 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15805 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15806 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15807 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15808 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15809 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15810 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15811 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15812 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15813 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15814 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15816 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15817 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15818 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15819 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15820 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15821 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15822 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15823 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15824 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15825 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15826 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15827 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15829 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15830 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15831 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15832 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15834 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15835 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15836 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15837 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15838 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15839 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15840 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15841 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15842 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15843 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15844 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15845 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15847 /* The implementation of the FIX instruction is broken on some
15848 assemblers, in that it accepts a precision specifier as well as a
15849 rounding specifier, despite the fact that this is meaningless.
15850 To be more compatible, we accept it as well, though of course it
15851 does not set any bits. */
15852 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15853 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15854 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15855 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15856 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15857 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15858 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15859 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15860 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15861 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15862 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15863 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15864 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15866 /* Instructions that were new with the real FPA, call them V2. */
15868 #define ARM_VARIANT &fpu_fpa_ext_v2
15869 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15870 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15871 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15872 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15873 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15874 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15877 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15878 /* Moves and type conversions. */
15879 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15880 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15881 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15882 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15883 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15884 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15885 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15886 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15887 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15888 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15889 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15890 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15892 /* Memory operations. */
15893 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15894 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15895 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15896 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15897 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15898 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15899 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15900 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15901 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15902 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15903 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15904 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15905 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15906 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15907 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15908 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15909 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15910 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15912 /* Monadic operations. */
15913 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15914 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15915 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15917 /* Dyadic operations. */
15918 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15919 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15920 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15921 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15922 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15923 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15924 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15925 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15926 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15929 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15930 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15931 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15932 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15935 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15936 /* Moves and type conversions. */
15937 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15938 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15939 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15940 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15941 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15942 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15943 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15944 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15945 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15946 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15947 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15948 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15949 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15951 /* Memory operations. */
15952 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15953 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15954 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15955 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15956 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15957 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15958 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15959 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15960 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15961 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15963 /* Monadic operations. */
15964 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15965 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15966 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15968 /* Dyadic operations. */
15969 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15970 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15971 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15972 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15973 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15974 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15975 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15976 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15977 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15980 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15981 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15982 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15983 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15986 #define ARM_VARIANT &fpu_vfp_ext_v2
15987 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15988 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15989 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15990 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15992 /* Instructions which may belong to either the Neon or VFP instruction sets.
15993 Individual encoder functions perform additional architecture checks. */
15995 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15996 #undef THUMB_VARIANT
15997 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15998 /* These mnemonics are unique to VFP. */
15999 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
16000 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
16001 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16002 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16003 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16004 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16005 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16006 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16007 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16008 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16010 /* Mnemonics shared by Neon and VFP. */
16011 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16012 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16013 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16015 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16016 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16018 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16019 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16021 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16022 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16023 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16024 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16025 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16026 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16027 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16028 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16030 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16031 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16032 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16035 /* NOTE: All VMOV encoding is special-cased! */
16036 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16037 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16039 #undef THUMB_VARIANT
16040 #define THUMB_VARIANT &fpu_neon_ext_v1
16042 #define ARM_VARIANT &fpu_neon_ext_v1
16043 /* Data processing with three registers of the same length. */
16044 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16045 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16046 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16047 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16048 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16049 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16050 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16051 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16052 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16053 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16054 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16055 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16056 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16057 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16058 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16059 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16060 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16061 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16062 /* If not immediate, fall back to neon_dyadic_i64_su.
16063 shl_imm should accept I8 I16 I32 I64,
16064 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16065 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16066 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16067 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16068 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16069 /* Logic ops, types optional & ignored. */
16070 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16071 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16072 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16073 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16074 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16075 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16076 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16077 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16078 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16079 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16080 /* Bitfield ops, untyped. */
16081 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16082 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16083 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16084 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16085 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16086 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16087 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16088 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16089 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16090 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16091 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16092 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16093 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16094 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16095 back to neon_dyadic_if_su. */
16096 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16097 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16098 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16099 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16100 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16101 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16102 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16103 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16104 /* Comparison. Type I8 I16 I32 F32. */
16105 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16106 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16107 /* As above, D registers only. */
16108 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16109 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16110 /* Int and float variants, signedness unimportant. */
16111 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16112 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16113 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16114 /* Add/sub take types I8 I16 I32 I64 F32. */
16115 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16116 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16117 /* vtst takes sizes 8, 16, 32. */
16118 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16119 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16120 /* VMUL takes I8 I16 I32 F32 P8. */
16121 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16122 /* VQD{R}MULH takes S16 S32. */
16123 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16124 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16125 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16126 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16127 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16128 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16129 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16130 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16131 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16132 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16133 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16134 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16135 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16136 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16137 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16138 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16140 /* Two address, int/float. Types S8 S16 S32 F32. */
16141 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16142 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16144 /* Data processing with two registers and a shift amount. */
16145 /* Right shifts, and variants with rounding.
16146 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16147 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16148 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16149 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16150 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16151 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16152 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16153 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16154 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16155 /* Shift and insert. Sizes accepted 8 16 32 64. */
16156 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16157 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16158 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16159 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16160 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16161 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16162 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16163 /* Right shift immediate, saturating & narrowing, with rounding variants.
16164 Types accepted S16 S32 S64 U16 U32 U64. */
16165 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16166 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16167 /* As above, unsigned. Types accepted S16 S32 S64. */
16168 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16169 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16170 /* Right shift narrowing. Types accepted I16 I32 I64. */
16171 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16172 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16173 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16174 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16175 /* CVT with optional immediate for fixed-point variant. */
16176 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16178 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16179 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16181 /* Data processing, three registers of different lengths. */
16182 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16183 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16184 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16185 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16186 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16187 /* If not scalar, fall back to neon_dyadic_long.
16188 Vector types as above, scalar types S16 S32 U16 U32. */
16189 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16190 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16191 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16192 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16193 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16194 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16195 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16196 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16197 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16198 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16199 /* Saturating doubling multiplies. Types S16 S32. */
16200 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16201 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16202 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16203 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16204 S16 S32 U16 U32. */
16205 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16207 /* Extract. Size 8. */
16208 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16209 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16211 /* Two registers, miscellaneous. */
16212 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16213 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16214 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16215 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16216 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16217 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16218 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16219 /* Vector replicate. Sizes 8 16 32. */
16220 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16221 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16222 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16223 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16224 /* VMOVN. Types I16 I32 I64. */
16225 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16226 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16227 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16228 /* VQMOVUN. Types S16 S32 S64. */
16229 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16230 /* VZIP / VUZP. Sizes 8 16 32. */
16231 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16232 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16233 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16234 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16235 /* VQABS / VQNEG. Types S8 S16 S32. */
16236 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16237 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16238 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16239 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16240 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16241 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16242 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16243 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16244 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16245 /* Reciprocal estimates. Types U32 F32. */
16246 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16247 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16248 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16249 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16250 /* VCLS. Types S8 S16 S32. */
16251 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16252 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16253 /* VCLZ. Types I8 I16 I32. */
16254 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16255 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16256 /* VCNT. Size 8. */
16257 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16258 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16259 /* Two address, untyped. */
16260 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16261 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16262 /* VTRN. Sizes 8 16 32. */
16263 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16264 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16266 /* Table lookup. Size 8. */
16267 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16268 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16270 #undef THUMB_VARIANT
16271 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16273 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16274 /* Neon element/structure load/store. */
16275 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16276 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16277 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16278 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16279 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16280 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16281 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16282 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16284 #undef THUMB_VARIANT
16285 #define THUMB_VARIANT &fpu_vfp_ext_v3
16287 #define ARM_VARIANT &fpu_vfp_ext_v3
16288 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16289 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16290 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16291 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16292 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16293 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16294 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16295 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16296 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16297 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16298 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16299 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16300 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16301 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16302 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16303 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16304 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16305 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16307 #undef THUMB_VARIANT
16309 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16310 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16311 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16312 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16313 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16314 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16315 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16316 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16317 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16320 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16321 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16322 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16323 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16324 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16325 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16326 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16327 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16328 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16329 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16330 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16331 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16332 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16333 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16334 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16335 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16336 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16337 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16338 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16339 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16340 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16341 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16342 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16343 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16344 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16345 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16346 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16347 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16348 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16349 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16350 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16351 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16352 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16353 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16354 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16355 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16356 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16357 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16358 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16364 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16366 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16368 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16369 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16371 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16372 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16373 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16374 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16375 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16376 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16377 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16378 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16379 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16380 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16388 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16389 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16390 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16391 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16410 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16420 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16421 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16422 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16423 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16424 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16425 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16426 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16427 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16429 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16430 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16431 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16432 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16433 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16434 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16435 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16436 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16437 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16438 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16439 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16440 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16441 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16442 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16443 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16444 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16445 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16446 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16447 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16448 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16449 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16450 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16451 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16452 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16453 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16454 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16455 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16456 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16457 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16458 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16459 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16460 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16461 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16462 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16463 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16464 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16465 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16466 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16467 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16468 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16469 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16470 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16471 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16472 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16473 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16474 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16475 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16476 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16477 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16478 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16479 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16480 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16481 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16482 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16485 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16486 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16487 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16488 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16489 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16490 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16491 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16492 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16493 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16494 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16495 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16496 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16497 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16498 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16499 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16500 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16501 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16502 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16503 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16504 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16505 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16506 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16507 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16508 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16509 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16510 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16511 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16512 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16513 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16514 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16515 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16516 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16517 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16518 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16519 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16520 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16521 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16522 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16523 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16524 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16525 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16526 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16527 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16528 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16529 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16530 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16531 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16532 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16533 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16534 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16535 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16536 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16537 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16538 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16539 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16540 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16541 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16542 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16545 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16546 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16547 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16548 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16549 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16550 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16551 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16552 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16553 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16554 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16555 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16556 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16557 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16558 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16559 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16560 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16561 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16562 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16563 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16564 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16565 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16566 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16567 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16568 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16569 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16570 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16571 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16572 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16573 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16574 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16575 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16576 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16577 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16578 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16579 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16580 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16581 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16582 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16583 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16584 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16585 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16586 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16587 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16588 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16589 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16590 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16591 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16592 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16593 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16594 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16595 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16596 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16597 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16598 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16599 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16600 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16601 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16602 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16603 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16604 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16605 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16606 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16607 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16608 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16609 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16610 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16611 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16612 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16613 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16614 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16615 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16616 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16617 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16618 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16619 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16620 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16621 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16624 #undef THUMB_VARIANT
16651 /* MD interface: bits in the object file. */
16653 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16654 for use in the a.out file, and stores them in the array pointed to by buf.
16655 This knows about the endian-ness of the target machine and does
16656 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16657 2 (short) and 4 (long) Floating numbers are put out as a series of
16658 LITTLENUMS (shorts, here at least). */
16661 md_number_to_chars (char * buf
, valueT val
, int n
)
16663 if (target_big_endian
)
16664 number_to_chars_bigendian (buf
, val
, n
);
16666 number_to_chars_littleendian (buf
, val
, n
);
16670 md_chars_to_number (char * buf
, int n
)
16673 unsigned char * where
= (unsigned char *) buf
;
16675 if (target_big_endian
)
16680 result
|= (*where
++ & 255);
16688 result
|= (where
[n
] & 255);
16695 /* MD interface: Sections. */
16697 /* Estimate the size of a frag before relaxing. Assume everything fits in
16701 md_estimate_size_before_relax (fragS
* fragp
,
16702 segT segtype ATTRIBUTE_UNUSED
)
16708 /* Convert a machine dependent frag. */
16711 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16713 unsigned long insn
;
16714 unsigned long old_op
;
16722 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16724 old_op
= bfd_get_16(abfd
, buf
);
16725 if (fragp
->fr_symbol
)
16727 exp
.X_op
= O_symbol
;
16728 exp
.X_add_symbol
= fragp
->fr_symbol
;
16732 exp
.X_op
= O_constant
;
16734 exp
.X_add_number
= fragp
->fr_offset
;
16735 opcode
= fragp
->fr_subtype
;
16738 case T_MNEM_ldr_pc
:
16739 case T_MNEM_ldr_pc2
:
16740 case T_MNEM_ldr_sp
:
16741 case T_MNEM_str_sp
:
16748 if (fragp
->fr_var
== 4)
16750 insn
= THUMB_OP32 (opcode
);
16751 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16753 insn
|= (old_op
& 0x700) << 4;
16757 insn
|= (old_op
& 7) << 12;
16758 insn
|= (old_op
& 0x38) << 13;
16760 insn
|= 0x00000c00;
16761 put_thumb32_insn (buf
, insn
);
16762 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16766 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16768 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16771 if (fragp
->fr_var
== 4)
16773 insn
= THUMB_OP32 (opcode
);
16774 insn
|= (old_op
& 0xf0) << 4;
16775 put_thumb32_insn (buf
, insn
);
16776 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16780 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16781 exp
.X_add_number
-= 4;
16789 if (fragp
->fr_var
== 4)
16791 int r0off
= (opcode
== T_MNEM_mov
16792 || opcode
== T_MNEM_movs
) ? 0 : 8;
16793 insn
= THUMB_OP32 (opcode
);
16794 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16795 insn
|= (old_op
& 0x700) << r0off
;
16796 put_thumb32_insn (buf
, insn
);
16797 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16801 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16806 if (fragp
->fr_var
== 4)
16808 insn
= THUMB_OP32(opcode
);
16809 put_thumb32_insn (buf
, insn
);
16810 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16813 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16817 if (fragp
->fr_var
== 4)
16819 insn
= THUMB_OP32(opcode
);
16820 insn
|= (old_op
& 0xf00) << 14;
16821 put_thumb32_insn (buf
, insn
);
16822 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16825 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16828 case T_MNEM_add_sp
:
16829 case T_MNEM_add_pc
:
16830 case T_MNEM_inc_sp
:
16831 case T_MNEM_dec_sp
:
16832 if (fragp
->fr_var
== 4)
16834 /* ??? Choose between add and addw. */
16835 insn
= THUMB_OP32 (opcode
);
16836 insn
|= (old_op
& 0xf0) << 4;
16837 put_thumb32_insn (buf
, insn
);
16838 if (opcode
== T_MNEM_add_pc
)
16839 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16841 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16844 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16852 if (fragp
->fr_var
== 4)
16854 insn
= THUMB_OP32 (opcode
);
16855 insn
|= (old_op
& 0xf0) << 4;
16856 insn
|= (old_op
& 0xf) << 16;
16857 put_thumb32_insn (buf
, insn
);
16858 if (insn
& (1 << 20))
16859 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16861 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16864 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16870 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16872 fixp
->fx_file
= fragp
->fr_file
;
16873 fixp
->fx_line
= fragp
->fr_line
;
16874 fragp
->fr_fix
+= fragp
->fr_var
;
16877 /* Return the size of a relaxable immediate operand instruction.
16878 SHIFT and SIZE specify the form of the allowable immediate. */
16880 relax_immediate (fragS
*fragp
, int size
, int shift
)
16886 /* ??? Should be able to do better than this. */
16887 if (fragp
->fr_symbol
)
16890 low
= (1 << shift
) - 1;
16891 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16892 offset
= fragp
->fr_offset
;
16893 /* Force misaligned offsets to 32-bit variant. */
16896 if (offset
& ~mask
)
16901 /* Get the address of a symbol during relaxation. */
16903 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16909 sym
= fragp
->fr_symbol
;
16910 sym_frag
= symbol_get_frag (sym
);
16911 know (S_GET_SEGMENT (sym
) != absolute_section
16912 || sym_frag
== &zero_address_frag
);
16913 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16915 /* If frag has yet to be reached on this pass, assume it will
16916 move by STRETCH just as we did. If this is not so, it will
16917 be because some frag between grows, and that will force
16921 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16925 /* Adjust stretch for any alignment frag. Note that if have
16926 been expanding the earlier code, the symbol may be
16927 defined in what appears to be an earlier frag. FIXME:
16928 This doesn't handle the fr_subtype field, which specifies
16929 a maximum number of bytes to skip when doing an
16931 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16933 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16936 stretch
= - ((- stretch
)
16937 & ~ ((1 << (int) f
->fr_offset
) - 1));
16939 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16951 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16954 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16959 /* Assume worst case for symbols not known to be in the same section. */
16960 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16961 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16964 val
= relaxed_symbol_addr (fragp
, stretch
);
16965 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16966 addr
= (addr
+ 4) & ~3;
16967 /* Force misaligned targets to 32-bit variant. */
16971 if (val
< 0 || val
> 1020)
16976 /* Return the size of a relaxable add/sub immediate instruction. */
16978 relax_addsub (fragS
*fragp
, asection
*sec
)
16983 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16984 op
= bfd_get_16(sec
->owner
, buf
);
16985 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16986 return relax_immediate (fragp
, 8, 0);
16988 return relax_immediate (fragp
, 3, 0);
16992 /* Return the size of a relaxable branch instruction. BITS is the
16993 size of the offset field in the narrow instruction. */
16996 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17002 /* Assume worst case for symbols not known to be in the same section. */
17003 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17004 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17007 val
= relaxed_symbol_addr (fragp
, stretch
);
17008 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17011 /* Offset is a signed value *2 */
17013 if (val
>= limit
|| val
< -limit
)
17019 /* Relax a machine dependent frag. This returns the amount by which
17020 the current size of the frag should change. */
17023 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17028 oldsize
= fragp
->fr_var
;
17029 switch (fragp
->fr_subtype
)
17031 case T_MNEM_ldr_pc2
:
17032 newsize
= relax_adr (fragp
, sec
, stretch
);
17034 case T_MNEM_ldr_pc
:
17035 case T_MNEM_ldr_sp
:
17036 case T_MNEM_str_sp
:
17037 newsize
= relax_immediate (fragp
, 8, 2);
17041 newsize
= relax_immediate (fragp
, 5, 2);
17045 newsize
= relax_immediate (fragp
, 5, 1);
17049 newsize
= relax_immediate (fragp
, 5, 0);
17052 newsize
= relax_adr (fragp
, sec
, stretch
);
17058 newsize
= relax_immediate (fragp
, 8, 0);
17061 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17064 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17066 case T_MNEM_add_sp
:
17067 case T_MNEM_add_pc
:
17068 newsize
= relax_immediate (fragp
, 8, 2);
17070 case T_MNEM_inc_sp
:
17071 case T_MNEM_dec_sp
:
17072 newsize
= relax_immediate (fragp
, 7, 2);
17078 newsize
= relax_addsub (fragp
, sec
);
17084 fragp
->fr_var
= newsize
;
17085 /* Freeze wide instructions that are at or before the same location as
17086 in the previous pass. This avoids infinite loops.
17087 Don't freeze them unconditionally because targets may be artificially
17088 misaligned by the expansion of preceding frags. */
17089 if (stretch
<= 0 && newsize
> 2)
17091 md_convert_frag (sec
->owner
, sec
, fragp
);
17095 return newsize
- oldsize
;
17098 /* Round up a section size to the appropriate boundary. */
17101 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17104 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17105 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17107 /* For a.out, force the section size to be aligned. If we don't do
17108 this, BFD will align it for us, but it will not write out the
17109 final bytes of the section. This may be a bug in BFD, but it is
17110 easier to fix it here since that is how the other a.out targets
17114 align
= bfd_get_section_alignment (stdoutput
, segment
);
17115 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17122 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17123 of an rs_align_code fragment. */
17126 arm_handle_align (fragS
* fragP
)
17128 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17129 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17130 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17131 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17133 int bytes
, fix
, noop_size
;
17137 if (fragP
->fr_type
!= rs_align_code
)
17140 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17141 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17144 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17145 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17147 if (fragP
->tc_frag_data
)
17149 if (target_big_endian
)
17150 noop
= thumb_bigend_noop
;
17153 noop_size
= sizeof (thumb_noop
);
17157 if (target_big_endian
)
17158 noop
= arm_bigend_noop
;
17161 noop_size
= sizeof (arm_noop
);
17164 if (bytes
& (noop_size
- 1))
17166 fix
= bytes
& (noop_size
- 1);
17167 memset (p
, 0, fix
);
17172 while (bytes
>= noop_size
)
17174 memcpy (p
, noop
, noop_size
);
17176 bytes
-= noop_size
;
17180 fragP
->fr_fix
+= fix
;
17181 fragP
->fr_var
= noop_size
;
17184 /* Called from md_do_align. Used to create an alignment
17185 frag in a code section. */
17188 arm_frag_align_code (int n
, int max
)
17192 /* We assume that there will never be a requirement
17193 to support alignments greater than 32 bytes. */
17194 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17195 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17197 p
= frag_var (rs_align_code
,
17198 MAX_MEM_FOR_RS_ALIGN_CODE
,
17200 (relax_substateT
) max
,
17207 /* Perform target specific initialisation of a frag. */
17210 arm_init_frag (fragS
* fragP
)
17212 /* Record whether this frag is in an ARM or a THUMB area. */
17213 fragP
->tc_frag_data
= thumb_mode
;
17217 /* When we change sections we need to issue a new mapping symbol. */
17220 arm_elf_change_section (void)
17223 segment_info_type
*seginfo
;
17225 /* Link an unlinked unwind index table section to the .text section. */
17226 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17227 && elf_linked_to_section (now_seg
) == NULL
)
17228 elf_linked_to_section (now_seg
) = text_section
;
17230 if (!SEG_NORMAL (now_seg
))
17233 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17235 /* We can ignore sections that only contain debug info. */
17236 if ((flags
& SEC_ALLOC
) == 0)
17239 seginfo
= seg_info (now_seg
);
17240 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17241 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17245 arm_elf_section_type (const char * str
, size_t len
)
17247 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17248 return SHT_ARM_EXIDX
;
17253 /* Code to deal with unwinding tables. */
17255 static void add_unwind_adjustsp (offsetT
);
17257 /* Generate any deferred unwind frame offset. */
17260 flush_pending_unwind (void)
17264 offset
= unwind
.pending_offset
;
17265 unwind
.pending_offset
= 0;
17267 add_unwind_adjustsp (offset
);
17270 /* Add an opcode to this list for this function. Two-byte opcodes should
17271 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17275 add_unwind_opcode (valueT op
, int length
)
17277 /* Add any deferred stack adjustment. */
17278 if (unwind
.pending_offset
)
17279 flush_pending_unwind ();
17281 unwind
.sp_restored
= 0;
17283 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17285 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17286 if (unwind
.opcodes
)
17287 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17288 unwind
.opcode_alloc
);
17290 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17295 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17297 unwind
.opcode_count
++;
17301 /* Add unwind opcodes to adjust the stack pointer. */
17304 add_unwind_adjustsp (offsetT offset
)
17308 if (offset
> 0x200)
17310 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17315 /* Long form: 0xb2, uleb128. */
17316 /* This might not fit in a word so add the individual bytes,
17317 remembering the list is built in reverse order. */
17318 o
= (valueT
) ((offset
- 0x204) >> 2);
17320 add_unwind_opcode (0, 1);
17322 /* Calculate the uleb128 encoding of the offset. */
17326 bytes
[n
] = o
& 0x7f;
17332 /* Add the insn. */
17334 add_unwind_opcode (bytes
[n
- 1], 1);
17335 add_unwind_opcode (0xb2, 1);
17337 else if (offset
> 0x100)
17339 /* Two short opcodes. */
17340 add_unwind_opcode (0x3f, 1);
17341 op
= (offset
- 0x104) >> 2;
17342 add_unwind_opcode (op
, 1);
17344 else if (offset
> 0)
17346 /* Short opcode. */
17347 op
= (offset
- 4) >> 2;
17348 add_unwind_opcode (op
, 1);
17350 else if (offset
< 0)
17353 while (offset
> 0x100)
17355 add_unwind_opcode (0x7f, 1);
17358 op
= ((offset
- 4) >> 2) | 0x40;
17359 add_unwind_opcode (op
, 1);
17363 /* Finish the list of unwind opcodes for this function. */
17365 finish_unwind_opcodes (void)
17369 if (unwind
.fp_used
)
17371 /* Adjust sp as necessary. */
17372 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17373 flush_pending_unwind ();
17375 /* After restoring sp from the frame pointer. */
17376 op
= 0x90 | unwind
.fp_reg
;
17377 add_unwind_opcode (op
, 1);
17380 flush_pending_unwind ();
17384 /* Start an exception table entry. If idx is nonzero this is an index table
17388 start_unwind_section (const segT text_seg
, int idx
)
17390 const char * text_name
;
17391 const char * prefix
;
17392 const char * prefix_once
;
17393 const char * group_name
;
17397 size_t sec_name_len
;
17404 prefix
= ELF_STRING_ARM_unwind
;
17405 prefix_once
= ELF_STRING_ARM_unwind_once
;
17406 type
= SHT_ARM_EXIDX
;
17410 prefix
= ELF_STRING_ARM_unwind_info
;
17411 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17412 type
= SHT_PROGBITS
;
17415 text_name
= segment_name (text_seg
);
17416 if (streq (text_name
, ".text"))
17419 if (strncmp (text_name
, ".gnu.linkonce.t.",
17420 strlen (".gnu.linkonce.t.")) == 0)
17422 prefix
= prefix_once
;
17423 text_name
+= strlen (".gnu.linkonce.t.");
17426 prefix_len
= strlen (prefix
);
17427 text_len
= strlen (text_name
);
17428 sec_name_len
= prefix_len
+ text_len
;
17429 sec_name
= xmalloc (sec_name_len
+ 1);
17430 memcpy (sec_name
, prefix
, prefix_len
);
17431 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17432 sec_name
[prefix_len
+ text_len
] = '\0';
17438 /* Handle COMDAT group. */
17439 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17441 group_name
= elf_group_name (text_seg
);
17442 if (group_name
== NULL
)
17444 as_bad (_("Group section `%s' has no group signature"),
17445 segment_name (text_seg
));
17446 ignore_rest_of_line ();
17449 flags
|= SHF_GROUP
;
17453 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17455 /* Set the section link for index tables. */
17457 elf_linked_to_section (now_seg
) = text_seg
;
17461 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17462 personality routine data. Returns zero, or the index table value for
17463 and inline entry. */
17466 create_unwind_entry (int have_data
)
17471 /* The current word of data. */
17473 /* The number of bytes left in this word. */
17476 finish_unwind_opcodes ();
17478 /* Remember the current text section. */
17479 unwind
.saved_seg
= now_seg
;
17480 unwind
.saved_subseg
= now_subseg
;
17482 start_unwind_section (now_seg
, 0);
17484 if (unwind
.personality_routine
== NULL
)
17486 if (unwind
.personality_index
== -2)
17489 as_bad (_("handlerdata in cantunwind frame"));
17490 return 1; /* EXIDX_CANTUNWIND. */
17493 /* Use a default personality routine if none is specified. */
17494 if (unwind
.personality_index
== -1)
17496 if (unwind
.opcode_count
> 3)
17497 unwind
.personality_index
= 1;
17499 unwind
.personality_index
= 0;
17502 /* Space for the personality routine entry. */
17503 if (unwind
.personality_index
== 0)
17505 if (unwind
.opcode_count
> 3)
17506 as_bad (_("too many unwind opcodes for personality routine 0"));
17510 /* All the data is inline in the index table. */
17513 while (unwind
.opcode_count
> 0)
17515 unwind
.opcode_count
--;
17516 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17520 /* Pad with "finish" opcodes. */
17522 data
= (data
<< 8) | 0xb0;
17529 /* We get two opcodes "free" in the first word. */
17530 size
= unwind
.opcode_count
- 2;
17533 /* An extra byte is required for the opcode count. */
17534 size
= unwind
.opcode_count
+ 1;
17536 size
= (size
+ 3) >> 2;
17538 as_bad (_("too many unwind opcodes"));
17540 frag_align (2, 0, 0);
17541 record_alignment (now_seg
, 2);
17542 unwind
.table_entry
= expr_build_dot ();
17544 /* Allocate the table entry. */
17545 ptr
= frag_more ((size
<< 2) + 4);
17546 where
= frag_now_fix () - ((size
<< 2) + 4);
17548 switch (unwind
.personality_index
)
17551 /* ??? Should this be a PLT generating relocation? */
17552 /* Custom personality routine. */
17553 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17554 BFD_RELOC_ARM_PREL31
);
17559 /* Set the first byte to the number of additional words. */
17564 /* ABI defined personality routines. */
17566 /* Three opcodes bytes are packed into the first word. */
17573 /* The size and first two opcode bytes go in the first word. */
17574 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17579 /* Should never happen. */
17583 /* Pack the opcodes into words (MSB first), reversing the list at the same
17585 while (unwind
.opcode_count
> 0)
17589 md_number_to_chars (ptr
, data
, 4);
17594 unwind
.opcode_count
--;
17596 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17599 /* Finish off the last word. */
17602 /* Pad with "finish" opcodes. */
17604 data
= (data
<< 8) | 0xb0;
17606 md_number_to_chars (ptr
, data
, 4);
17611 /* Add an empty descriptor if there is no user-specified data. */
17612 ptr
= frag_more (4);
17613 md_number_to_chars (ptr
, 0, 4);
17620 /* Initialize the DWARF-2 unwind information for this procedure. */
17623 tc_arm_frame_initial_instructions (void)
17625 cfi_add_CFA_def_cfa (REG_SP
, 0);
17627 #endif /* OBJ_ELF */
17629 /* Convert REGNAME to a DWARF-2 register number. */
17632 tc_arm_regname_to_dw2regnum (char *regname
)
17634 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17644 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17648 expr
.X_op
= O_secrel
;
17649 expr
.X_add_symbol
= symbol
;
17650 expr
.X_add_number
= 0;
17651 emit_expr (&expr
, size
);
17655 /* MD interface: Symbol and relocation handling. */
17657 /* Return the address within the segment that a PC-relative fixup is
17658 relative to. For ARM, PC-relative fixups applied to instructions
17659 are generally relative to the location of the fixup plus 8 bytes.
17660 Thumb branches are offset by 4, and Thumb loads relative to PC
17661 require special handling. */
17664 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17666 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17668 /* If this is pc-relative and we are going to emit a relocation
17669 then we just want to put out any pipeline compensation that the linker
17670 will need. Otherwise we want to use the calculated base.
17671 For WinCE we skip the bias for externals as well, since this
17672 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17674 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17675 || (arm_force_relocation (fixP
)
17677 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17682 switch (fixP
->fx_r_type
)
17684 /* PC relative addressing on the Thumb is slightly odd as the
17685 bottom two bits of the PC are forced to zero for the
17686 calculation. This happens *after* application of the
17687 pipeline offset. However, Thumb adrl already adjusts for
17688 this, so we need not do it again. */
17689 case BFD_RELOC_ARM_THUMB_ADD
:
17692 case BFD_RELOC_ARM_THUMB_OFFSET
:
17693 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17694 case BFD_RELOC_ARM_T32_ADD_PC12
:
17695 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17696 return (base
+ 4) & ~3;
17698 /* Thumb branches are simply offset by +4. */
17699 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17700 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17701 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17702 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17703 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17704 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17705 case BFD_RELOC_THUMB_PCREL_BLX
:
17708 /* ARM mode branches are offset by +8. However, the Windows CE
17709 loader expects the relocation not to take this into account. */
17710 case BFD_RELOC_ARM_PCREL_BRANCH
:
17711 case BFD_RELOC_ARM_PCREL_CALL
:
17712 case BFD_RELOC_ARM_PCREL_JUMP
:
17713 case BFD_RELOC_ARM_PCREL_BLX
:
17714 case BFD_RELOC_ARM_PLT32
:
17716 /* When handling fixups immediately, because we have already
17717 discovered the value of a symbol, or the address of the frag involved
17718 we must account for the offset by +8, as the OS loader will never see the reloc.
17719 see fixup_segment() in write.c
17720 The S_IS_EXTERNAL test handles the case of global symbols.
17721 Those need the calculated base, not just the pipe compensation the linker will need. */
17723 && fixP
->fx_addsy
!= NULL
17724 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17725 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17732 /* ARM mode loads relative to PC are also offset by +8. Unlike
17733 branches, the Windows CE loader *does* expect the relocation
17734 to take this into account. */
17735 case BFD_RELOC_ARM_OFFSET_IMM
:
17736 case BFD_RELOC_ARM_OFFSET_IMM8
:
17737 case BFD_RELOC_ARM_HWLITERAL
:
17738 case BFD_RELOC_ARM_LITERAL
:
17739 case BFD_RELOC_ARM_CP_OFF_IMM
:
17743 /* Other PC-relative relocations are un-offset. */
17749 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17750 Otherwise we have no need to default values of symbols. */
17753 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17756 if (name
[0] == '_' && name
[1] == 'G'
17757 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17761 if (symbol_find (name
))
17762 as_bad (_("GOT already in the symbol table"));
17764 GOT_symbol
= symbol_new (name
, undefined_section
,
17765 (valueT
) 0, & zero_address_frag
);
17775 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17776 computed as two separate immediate values, added together. We
17777 already know that this value cannot be computed by just one ARM
17780 static unsigned int
17781 validate_immediate_twopart (unsigned int val
,
17782 unsigned int * highpart
)
17787 for (i
= 0; i
< 32; i
+= 2)
17788 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17794 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17796 else if (a
& 0xff0000)
17798 if (a
& 0xff000000)
17800 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17804 assert (a
& 0xff000000);
17805 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17808 return (a
& 0xff) | (i
<< 7);
17815 validate_offset_imm (unsigned int val
, int hwse
)
17817 if ((hwse
&& val
> 255) || val
> 4095)
17822 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17823 negative immediate constant by altering the instruction. A bit of
17828 by inverting the second operand, and
17831 by negating the second operand. */
17834 negate_data_op (unsigned long * instruction
,
17835 unsigned long value
)
17838 unsigned long negated
, inverted
;
17840 negated
= encode_arm_immediate (-value
);
17841 inverted
= encode_arm_immediate (~value
);
17843 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17846 /* First negates. */
17847 case OPCODE_SUB
: /* ADD <-> SUB */
17848 new_inst
= OPCODE_ADD
;
17853 new_inst
= OPCODE_SUB
;
17857 case OPCODE_CMP
: /* CMP <-> CMN */
17858 new_inst
= OPCODE_CMN
;
17863 new_inst
= OPCODE_CMP
;
17867 /* Now Inverted ops. */
17868 case OPCODE_MOV
: /* MOV <-> MVN */
17869 new_inst
= OPCODE_MVN
;
17874 new_inst
= OPCODE_MOV
;
17878 case OPCODE_AND
: /* AND <-> BIC */
17879 new_inst
= OPCODE_BIC
;
17884 new_inst
= OPCODE_AND
;
17888 case OPCODE_ADC
: /* ADC <-> SBC */
17889 new_inst
= OPCODE_SBC
;
17894 new_inst
= OPCODE_ADC
;
17898 /* We cannot do anything. */
17903 if (value
== (unsigned) FAIL
)
17906 *instruction
&= OPCODE_MASK
;
17907 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17911 /* Like negate_data_op, but for Thumb-2. */
17913 static unsigned int
17914 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17918 unsigned int negated
, inverted
;
17920 negated
= encode_thumb32_immediate (-value
);
17921 inverted
= encode_thumb32_immediate (~value
);
17923 rd
= (*instruction
>> 8) & 0xf;
17924 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17927 /* ADD <-> SUB. Includes CMP <-> CMN. */
17928 case T2_OPCODE_SUB
:
17929 new_inst
= T2_OPCODE_ADD
;
17933 case T2_OPCODE_ADD
:
17934 new_inst
= T2_OPCODE_SUB
;
17938 /* ORR <-> ORN. Includes MOV <-> MVN. */
17939 case T2_OPCODE_ORR
:
17940 new_inst
= T2_OPCODE_ORN
;
17944 case T2_OPCODE_ORN
:
17945 new_inst
= T2_OPCODE_ORR
;
17949 /* AND <-> BIC. TST has no inverted equivalent. */
17950 case T2_OPCODE_AND
:
17951 new_inst
= T2_OPCODE_BIC
;
17958 case T2_OPCODE_BIC
:
17959 new_inst
= T2_OPCODE_AND
;
17964 case T2_OPCODE_ADC
:
17965 new_inst
= T2_OPCODE_SBC
;
17969 case T2_OPCODE_SBC
:
17970 new_inst
= T2_OPCODE_ADC
;
17974 /* We cannot do anything. */
17979 if (value
== (unsigned int)FAIL
)
17982 *instruction
&= T2_OPCODE_MASK
;
17983 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17987 /* Read a 32-bit thumb instruction from buf. */
17988 static unsigned long
17989 get_thumb32_insn (char * buf
)
17991 unsigned long insn
;
17992 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17993 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17999 /* We usually want to set the low bit on the address of thumb function
18000 symbols. In particular .word foo - . should have the low bit set.
18001 Generic code tries to fold the difference of two symbols to
18002 a constant. Prevent this and force a relocation when the first symbols
18003 is a thumb function. */
18005 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18007 if (op
== O_subtract
18008 && l
->X_op
== O_symbol
18009 && r
->X_op
== O_symbol
18010 && THUMB_IS_FUNC (l
->X_add_symbol
))
18012 l
->X_op
= O_subtract
;
18013 l
->X_op_symbol
= r
->X_add_symbol
;
18014 l
->X_add_number
-= r
->X_add_number
;
18017 /* Process as normal. */
18022 md_apply_fix (fixS
* fixP
,
18026 offsetT value
= * valP
;
18028 unsigned int newimm
;
18029 unsigned long temp
;
18031 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18033 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18035 /* Note whether this will delete the relocation. */
18037 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18040 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18041 consistency with the behaviour on 32-bit hosts. Remember value
18043 value
&= 0xffffffff;
18044 value
^= 0x80000000;
18045 value
-= 0x80000000;
18048 fixP
->fx_addnumber
= value
;
18050 /* Same treatment for fixP->fx_offset. */
18051 fixP
->fx_offset
&= 0xffffffff;
18052 fixP
->fx_offset
^= 0x80000000;
18053 fixP
->fx_offset
-= 0x80000000;
18055 switch (fixP
->fx_r_type
)
18057 case BFD_RELOC_NONE
:
18058 /* This will need to go in the object file. */
18062 case BFD_RELOC_ARM_IMMEDIATE
:
18063 /* We claim that this fixup has been processed here,
18064 even if in fact we generate an error because we do
18065 not have a reloc for it, so tc_gen_reloc will reject it. */
18069 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18072 _("undefined symbol %s used as an immediate value"),
18073 S_GET_NAME (fixP
->fx_addsy
));
18077 newimm
= encode_arm_immediate (value
);
18078 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18080 /* If the instruction will fail, see if we can fix things up by
18081 changing the opcode. */
18082 if (newimm
== (unsigned int) FAIL
18083 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18086 _("invalid constant (%lx) after fixup"),
18087 (unsigned long) value
);
18091 newimm
|= (temp
& 0xfffff000);
18092 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18095 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18097 unsigned int highpart
= 0;
18098 unsigned int newinsn
= 0xe1a00000; /* nop. */
18100 newimm
= encode_arm_immediate (value
);
18101 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18103 /* If the instruction will fail, see if we can fix things up by
18104 changing the opcode. */
18105 if (newimm
== (unsigned int) FAIL
18106 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18108 /* No ? OK - try using two ADD instructions to generate
18110 newimm
= validate_immediate_twopart (value
, & highpart
);
18112 /* Yes - then make sure that the second instruction is
18114 if (newimm
!= (unsigned int) FAIL
)
18116 /* Still No ? Try using a negated value. */
18117 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18118 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18119 /* Otherwise - give up. */
18122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18123 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18128 /* Replace the first operand in the 2nd instruction (which
18129 is the PC) with the destination register. We have
18130 already added in the PC in the first instruction and we
18131 do not want to do it again. */
18132 newinsn
&= ~ 0xf0000;
18133 newinsn
|= ((newinsn
& 0x0f000) << 4);
18136 newimm
|= (temp
& 0xfffff000);
18137 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18139 highpart
|= (newinsn
& 0xfffff000);
18140 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18144 case BFD_RELOC_ARM_OFFSET_IMM
:
18145 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18148 case BFD_RELOC_ARM_LITERAL
:
18154 if (validate_offset_imm (value
, 0) == FAIL
)
18156 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18158 _("invalid literal constant: pool needs to be closer"));
18160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18161 _("bad immediate value for offset (%ld)"),
18166 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18167 newval
&= 0xff7ff000;
18168 newval
|= value
| (sign
? INDEX_UP
: 0);
18169 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18172 case BFD_RELOC_ARM_OFFSET_IMM8
:
18173 case BFD_RELOC_ARM_HWLITERAL
:
18179 if (validate_offset_imm (value
, 1) == FAIL
)
18181 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18183 _("invalid literal constant: pool needs to be closer"));
18185 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18190 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18191 newval
&= 0xff7ff0f0;
18192 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18193 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18196 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18197 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18199 _("bad immediate value for offset (%ld)"), (long) value
);
18202 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18204 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18207 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18208 /* This is a complicated relocation used for all varieties of Thumb32
18209 load/store instruction with immediate offset:
18211 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18212 *4, optional writeback(W)
18213 (doubleword load/store)
18215 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18216 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18217 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18218 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18219 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18221 Uppercase letters indicate bits that are already encoded at
18222 this point. Lowercase letters are our problem. For the
18223 second block of instructions, the secondary opcode nybble
18224 (bits 8..11) is present, and bit 23 is zero, even if this is
18225 a PC-relative operation. */
18226 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18228 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18230 if ((newval
& 0xf0000000) == 0xe0000000)
18232 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18234 newval
|= (1 << 23);
18237 if (value
% 4 != 0)
18239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18240 _("offset not a multiple of 4"));
18246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18247 _("offset out of range"));
18252 else if ((newval
& 0x000f0000) == 0x000f0000)
18254 /* PC-relative, 12-bit offset. */
18256 newval
|= (1 << 23);
18261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18262 _("offset out of range"));
18267 else if ((newval
& 0x00000100) == 0x00000100)
18269 /* Writeback: 8-bit, +/- offset. */
18271 newval
|= (1 << 9);
18276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18277 _("offset out of range"));
18282 else if ((newval
& 0x00000f00) == 0x00000e00)
18284 /* T-instruction: positive 8-bit offset. */
18285 if (value
< 0 || value
> 0xff)
18287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18288 _("offset out of range"));
18296 /* Positive 12-bit or negative 8-bit offset. */
18300 newval
|= (1 << 23);
18310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18311 _("offset out of range"));
18318 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18319 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18322 case BFD_RELOC_ARM_SHIFT_IMM
:
18323 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18324 if (((unsigned long) value
) > 32
18326 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18329 _("shift expression is too large"));
18334 /* Shifts of zero must be done as lsl. */
18336 else if (value
== 32)
18338 newval
&= 0xfffff07f;
18339 newval
|= (value
& 0x1f) << 7;
18340 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18343 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18344 case BFD_RELOC_ARM_T32_ADD_IMM
:
18345 case BFD_RELOC_ARM_T32_IMM12
:
18346 case BFD_RELOC_ARM_T32_ADD_PC12
:
18347 /* We claim that this fixup has been processed here,
18348 even if in fact we generate an error because we do
18349 not have a reloc for it, so tc_gen_reloc will reject it. */
18353 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18356 _("undefined symbol %s used as an immediate value"),
18357 S_GET_NAME (fixP
->fx_addsy
));
18361 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18363 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18366 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18367 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18369 newimm
= encode_thumb32_immediate (value
);
18370 if (newimm
== (unsigned int) FAIL
)
18371 newimm
= thumb32_negate_data_op (&newval
, value
);
18373 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18374 && newimm
== (unsigned int) FAIL
)
18376 /* Turn add/sum into addw/subw. */
18377 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18378 newval
= (newval
& 0xfeffffff) | 0x02000000;
18380 /* 12 bit immediate for addw/subw. */
18384 newval
^= 0x00a00000;
18387 newimm
= (unsigned int) FAIL
;
18392 if (newimm
== (unsigned int)FAIL
)
18394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18395 _("invalid constant (%lx) after fixup"),
18396 (unsigned long) value
);
18400 newval
|= (newimm
& 0x800) << 15;
18401 newval
|= (newimm
& 0x700) << 4;
18402 newval
|= (newimm
& 0x0ff);
18404 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18405 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18408 case BFD_RELOC_ARM_SMC
:
18409 if (((unsigned long) value
) > 0xffff)
18410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18411 _("invalid smc expression"));
18412 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18413 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18414 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18417 case BFD_RELOC_ARM_SWI
:
18418 if (fixP
->tc_fix_data
!= 0)
18420 if (((unsigned long) value
) > 0xff)
18421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18422 _("invalid swi expression"));
18423 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18425 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18429 if (((unsigned long) value
) > 0x00ffffff)
18430 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18431 _("invalid swi expression"));
18432 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18434 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18438 case BFD_RELOC_ARM_MULTI
:
18439 if (((unsigned long) value
) > 0xffff)
18440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18441 _("invalid expression in load/store multiple"));
18442 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18443 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18447 case BFD_RELOC_ARM_PCREL_CALL
:
18448 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18449 if ((newval
& 0xf0000000) == 0xf0000000)
18453 goto arm_branch_common
;
18455 case BFD_RELOC_ARM_PCREL_JUMP
:
18456 case BFD_RELOC_ARM_PLT32
:
18458 case BFD_RELOC_ARM_PCREL_BRANCH
:
18460 goto arm_branch_common
;
18462 case BFD_RELOC_ARM_PCREL_BLX
:
18465 /* We are going to store value (shifted right by two) in the
18466 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18467 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18468 also be be clear. */
18470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18471 _("misaligned branch destination"));
18472 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18473 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18475 _("branch out of range"));
18477 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18479 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18480 newval
|= (value
>> 2) & 0x00ffffff;
18481 /* Set the H bit on BLX instructions. */
18485 newval
|= 0x01000000;
18487 newval
&= ~0x01000000;
18489 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18493 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18494 /* CBZ can only branch forward. */
18496 /* Attempts to use CBZ to branch to the next instruction
18497 (which, strictly speaking, are prohibited) will be turned into
18500 FIXME: It may be better to remove the instruction completely and
18501 perform relaxation. */
18504 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18505 newval
= 0xbf00; /* NOP encoding T1 */
18506 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18512 _("branch out of range"));
18514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18516 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18517 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18518 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18523 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18524 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18526 _("branch out of range"));
18528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18530 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18531 newval
|= (value
& 0x1ff) >> 1;
18532 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18536 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18537 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18539 _("branch out of range"));
18541 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18543 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18544 newval
|= (value
& 0xfff) >> 1;
18545 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18549 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18550 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18552 _("conditional branch out of range"));
18554 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18557 addressT S
, J1
, J2
, lo
, hi
;
18559 S
= (value
& 0x00100000) >> 20;
18560 J2
= (value
& 0x00080000) >> 19;
18561 J1
= (value
& 0x00040000) >> 18;
18562 hi
= (value
& 0x0003f000) >> 12;
18563 lo
= (value
& 0x00000ffe) >> 1;
18565 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18566 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18567 newval
|= (S
<< 10) | hi
;
18568 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18569 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18570 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18574 case BFD_RELOC_THUMB_PCREL_BLX
:
18575 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18576 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18578 _("branch out of range"));
18580 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18581 /* For a BLX instruction, make sure that the relocation is rounded up
18582 to a word boundary. This follows the semantics of the instruction
18583 which specifies that bit 1 of the target address will come from bit
18584 1 of the base address. */
18585 value
= (value
+ 1) & ~ 1;
18587 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18591 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18592 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18593 newval
|= (value
& 0x7fffff) >> 12;
18594 newval2
|= (value
& 0xfff) >> 1;
18595 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18596 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18600 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18601 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18603 _("branch out of range"));
18605 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18608 addressT S
, I1
, I2
, lo
, hi
;
18610 S
= (value
& 0x01000000) >> 24;
18611 I1
= (value
& 0x00800000) >> 23;
18612 I2
= (value
& 0x00400000) >> 22;
18613 hi
= (value
& 0x003ff000) >> 12;
18614 lo
= (value
& 0x00000ffe) >> 1;
18619 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18620 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18621 newval
|= (S
<< 10) | hi
;
18622 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18623 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18624 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18629 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18630 md_number_to_chars (buf
, value
, 1);
18634 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18635 md_number_to_chars (buf
, value
, 2);
18639 case BFD_RELOC_ARM_TLS_GD32
:
18640 case BFD_RELOC_ARM_TLS_LE32
:
18641 case BFD_RELOC_ARM_TLS_IE32
:
18642 case BFD_RELOC_ARM_TLS_LDM32
:
18643 case BFD_RELOC_ARM_TLS_LDO32
:
18644 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18647 case BFD_RELOC_ARM_GOT32
:
18648 case BFD_RELOC_ARM_GOTOFF
:
18649 case BFD_RELOC_ARM_TARGET2
:
18650 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18651 md_number_to_chars (buf
, 0, 4);
18655 case BFD_RELOC_RVA
:
18657 case BFD_RELOC_ARM_TARGET1
:
18658 case BFD_RELOC_ARM_ROSEGREL32
:
18659 case BFD_RELOC_ARM_SBREL32
:
18660 case BFD_RELOC_32_PCREL
:
18662 case BFD_RELOC_32_SECREL
:
18664 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18666 /* For WinCE we only do this for pcrel fixups. */
18667 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18669 md_number_to_chars (buf
, value
, 4);
18673 case BFD_RELOC_ARM_PREL31
:
18674 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18676 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18677 if ((value
^ (value
>> 1)) & 0x40000000)
18679 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18680 _("rel31 relocation overflow"));
18682 newval
|= value
& 0x7fffffff;
18683 md_number_to_chars (buf
, newval
, 4);
18688 case BFD_RELOC_ARM_CP_OFF_IMM
:
18689 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18690 if (value
< -1023 || value
> 1023 || (value
& 3))
18691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18692 _("co-processor offset out of range"));
18697 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18698 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18699 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18701 newval
= get_thumb32_insn (buf
);
18702 newval
&= 0xff7fff00;
18703 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18704 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18705 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18706 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18708 put_thumb32_insn (buf
, newval
);
18711 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18712 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18713 if (value
< -255 || value
> 255)
18714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18715 _("co-processor offset out of range"));
18717 goto cp_off_common
;
18719 case BFD_RELOC_ARM_THUMB_OFFSET
:
18720 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18721 /* Exactly what ranges, and where the offset is inserted depends
18722 on the type of instruction, we can establish this from the
18724 switch (newval
>> 12)
18726 case 4: /* PC load. */
18727 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18728 forced to zero for these loads; md_pcrel_from has already
18729 compensated for this. */
18731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18732 _("invalid offset, target not word aligned (0x%08lX)"),
18733 (((unsigned long) fixP
->fx_frag
->fr_address
18734 + (unsigned long) fixP
->fx_where
) & ~3)
18735 + (unsigned long) value
);
18737 if (value
& ~0x3fc)
18738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18739 _("invalid offset, value too big (0x%08lX)"),
18742 newval
|= value
>> 2;
18745 case 9: /* SP load/store. */
18746 if (value
& ~0x3fc)
18747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18748 _("invalid offset, value too big (0x%08lX)"),
18750 newval
|= value
>> 2;
18753 case 6: /* Word load/store. */
18755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18756 _("invalid offset, value too big (0x%08lX)"),
18758 newval
|= value
<< 4; /* 6 - 2. */
18761 case 7: /* Byte load/store. */
18763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18764 _("invalid offset, value too big (0x%08lX)"),
18766 newval
|= value
<< 6;
18769 case 8: /* Halfword load/store. */
18771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18772 _("invalid offset, value too big (0x%08lX)"),
18774 newval
|= value
<< 5; /* 6 - 1. */
18778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18779 "Unable to process relocation for thumb opcode: %lx",
18780 (unsigned long) newval
);
18783 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18786 case BFD_RELOC_ARM_THUMB_ADD
:
18787 /* This is a complicated relocation, since we use it for all of
18788 the following immediate relocations:
18792 9bit ADD/SUB SP word-aligned
18793 10bit ADD PC/SP word-aligned
18795 The type of instruction being processed is encoded in the
18802 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18804 int rd
= (newval
>> 4) & 0xf;
18805 int rs
= newval
& 0xf;
18806 int subtract
= !!(newval
& 0x8000);
18808 /* Check for HI regs, only very restricted cases allowed:
18809 Adjusting SP, and using PC or SP to get an address. */
18810 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18811 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18813 _("invalid Hi register with immediate"));
18815 /* If value is negative, choose the opposite instruction. */
18819 subtract
= !subtract
;
18821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18822 _("immediate value out of range"));
18827 if (value
& ~0x1fc)
18828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18829 _("invalid immediate for stack address calculation"));
18830 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18831 newval
|= value
>> 2;
18833 else if (rs
== REG_PC
|| rs
== REG_SP
)
18835 if (subtract
|| value
& ~0x3fc)
18836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18837 _("invalid immediate for address calculation (value = 0x%08lX)"),
18838 (unsigned long) value
);
18839 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18841 newval
|= value
>> 2;
18846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18847 _("immediate value out of range"));
18848 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18849 newval
|= (rd
<< 8) | value
;
18854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18855 _("immediate value out of range"));
18856 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18857 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18860 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18863 case BFD_RELOC_ARM_THUMB_IMM
:
18864 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18865 if (value
< 0 || value
> 255)
18866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18867 _("invalid immediate: %ld is out of range"),
18870 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18873 case BFD_RELOC_ARM_THUMB_SHIFT
:
18874 /* 5bit shift value (0..32). LSL cannot take 32. */
18875 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18876 temp
= newval
& 0xf800;
18877 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18879 _("invalid shift value: %ld"), (long) value
);
18880 /* Shifts of zero must be encoded as LSL. */
18882 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18883 /* Shifts of 32 are encoded as zero. */
18884 else if (value
== 32)
18886 newval
|= value
<< 6;
18887 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18890 case BFD_RELOC_VTABLE_INHERIT
:
18891 case BFD_RELOC_VTABLE_ENTRY
:
18895 case BFD_RELOC_ARM_MOVW
:
18896 case BFD_RELOC_ARM_MOVT
:
18897 case BFD_RELOC_ARM_THUMB_MOVW
:
18898 case BFD_RELOC_ARM_THUMB_MOVT
:
18899 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18901 /* REL format relocations are limited to a 16-bit addend. */
18902 if (!fixP
->fx_done
)
18904 if (value
< -0x8000 || value
> 0x7fff)
18905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18906 _("offset out of range"));
18908 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18909 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18914 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18915 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18917 newval
= get_thumb32_insn (buf
);
18918 newval
&= 0xfbf08f00;
18919 newval
|= (value
& 0xf000) << 4;
18920 newval
|= (value
& 0x0800) << 15;
18921 newval
|= (value
& 0x0700) << 4;
18922 newval
|= (value
& 0x00ff);
18923 put_thumb32_insn (buf
, newval
);
18927 newval
= md_chars_to_number (buf
, 4);
18928 newval
&= 0xfff0f000;
18929 newval
|= value
& 0x0fff;
18930 newval
|= (value
& 0xf000) << 4;
18931 md_number_to_chars (buf
, newval
, 4);
18936 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18937 case BFD_RELOC_ARM_ALU_PC_G0
:
18938 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18939 case BFD_RELOC_ARM_ALU_PC_G1
:
18940 case BFD_RELOC_ARM_ALU_PC_G2
:
18941 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18942 case BFD_RELOC_ARM_ALU_SB_G0
:
18943 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18944 case BFD_RELOC_ARM_ALU_SB_G1
:
18945 case BFD_RELOC_ARM_ALU_SB_G2
:
18946 assert (!fixP
->fx_done
);
18947 if (!seg
->use_rela_p
)
18950 bfd_vma encoded_addend
;
18951 bfd_vma addend_abs
= abs (value
);
18953 /* Check that the absolute value of the addend can be
18954 expressed as an 8-bit constant plus a rotation. */
18955 encoded_addend
= encode_arm_immediate (addend_abs
);
18956 if (encoded_addend
== (unsigned int) FAIL
)
18957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18958 _("the offset 0x%08lX is not representable"),
18959 (unsigned long) addend_abs
);
18961 /* Extract the instruction. */
18962 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18964 /* If the addend is positive, use an ADD instruction.
18965 Otherwise use a SUB. Take care not to destroy the S bit. */
18966 insn
&= 0xff1fffff;
18972 /* Place the encoded addend into the first 12 bits of the
18974 insn
&= 0xfffff000;
18975 insn
|= encoded_addend
;
18977 /* Update the instruction. */
18978 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18982 case BFD_RELOC_ARM_LDR_PC_G0
:
18983 case BFD_RELOC_ARM_LDR_PC_G1
:
18984 case BFD_RELOC_ARM_LDR_PC_G2
:
18985 case BFD_RELOC_ARM_LDR_SB_G0
:
18986 case BFD_RELOC_ARM_LDR_SB_G1
:
18987 case BFD_RELOC_ARM_LDR_SB_G2
:
18988 assert (!fixP
->fx_done
);
18989 if (!seg
->use_rela_p
)
18992 bfd_vma addend_abs
= abs (value
);
18994 /* Check that the absolute value of the addend can be
18995 encoded in 12 bits. */
18996 if (addend_abs
>= 0x1000)
18997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18998 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18999 (unsigned long) addend_abs
);
19001 /* Extract the instruction. */
19002 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19004 /* If the addend is negative, clear bit 23 of the instruction.
19005 Otherwise set it. */
19007 insn
&= ~(1 << 23);
19011 /* Place the absolute value of the addend into the first 12 bits
19012 of the instruction. */
19013 insn
&= 0xfffff000;
19014 insn
|= addend_abs
;
19016 /* Update the instruction. */
19017 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19021 case BFD_RELOC_ARM_LDRS_PC_G0
:
19022 case BFD_RELOC_ARM_LDRS_PC_G1
:
19023 case BFD_RELOC_ARM_LDRS_PC_G2
:
19024 case BFD_RELOC_ARM_LDRS_SB_G0
:
19025 case BFD_RELOC_ARM_LDRS_SB_G1
:
19026 case BFD_RELOC_ARM_LDRS_SB_G2
:
19027 assert (!fixP
->fx_done
);
19028 if (!seg
->use_rela_p
)
19031 bfd_vma addend_abs
= abs (value
);
19033 /* Check that the absolute value of the addend can be
19034 encoded in 8 bits. */
19035 if (addend_abs
>= 0x100)
19036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19037 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19038 (unsigned long) addend_abs
);
19040 /* Extract the instruction. */
19041 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19043 /* If the addend is negative, clear bit 23 of the instruction.
19044 Otherwise set it. */
19046 insn
&= ~(1 << 23);
19050 /* Place the first four bits of the absolute value of the addend
19051 into the first 4 bits of the instruction, and the remaining
19052 four into bits 8 .. 11. */
19053 insn
&= 0xfffff0f0;
19054 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19056 /* Update the instruction. */
19057 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19061 case BFD_RELOC_ARM_LDC_PC_G0
:
19062 case BFD_RELOC_ARM_LDC_PC_G1
:
19063 case BFD_RELOC_ARM_LDC_PC_G2
:
19064 case BFD_RELOC_ARM_LDC_SB_G0
:
19065 case BFD_RELOC_ARM_LDC_SB_G1
:
19066 case BFD_RELOC_ARM_LDC_SB_G2
:
19067 assert (!fixP
->fx_done
);
19068 if (!seg
->use_rela_p
)
19071 bfd_vma addend_abs
= abs (value
);
19073 /* Check that the absolute value of the addend is a multiple of
19074 four and, when divided by four, fits in 8 bits. */
19075 if (addend_abs
& 0x3)
19076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19077 _("bad offset 0x%08lX (must be word-aligned)"),
19078 (unsigned long) addend_abs
);
19080 if ((addend_abs
>> 2) > 0xff)
19081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19082 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19083 (unsigned long) addend_abs
);
19085 /* Extract the instruction. */
19086 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19088 /* If the addend is negative, clear bit 23 of the instruction.
19089 Otherwise set it. */
19091 insn
&= ~(1 << 23);
19095 /* Place the addend (divided by four) into the first eight
19096 bits of the instruction. */
19097 insn
&= 0xfffffff0;
19098 insn
|= addend_abs
>> 2;
19100 /* Update the instruction. */
19101 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19105 case BFD_RELOC_ARM_V4BX
:
19106 /* This will need to go in the object file. */
19110 case BFD_RELOC_UNUSED
:
19112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19113 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19117 /* Translate internal representation of relocation info to BFD target
19121 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19124 bfd_reloc_code_real_type code
;
19126 reloc
= xmalloc (sizeof (arelent
));
19128 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19129 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19130 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19132 if (fixp
->fx_pcrel
)
19134 if (section
->use_rela_p
)
19135 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19137 fixp
->fx_offset
= reloc
->address
;
19139 reloc
->addend
= fixp
->fx_offset
;
19141 switch (fixp
->fx_r_type
)
19144 if (fixp
->fx_pcrel
)
19146 code
= BFD_RELOC_8_PCREL
;
19151 if (fixp
->fx_pcrel
)
19153 code
= BFD_RELOC_16_PCREL
;
19158 if (fixp
->fx_pcrel
)
19160 code
= BFD_RELOC_32_PCREL
;
19164 case BFD_RELOC_ARM_MOVW
:
19165 if (fixp
->fx_pcrel
)
19167 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19171 case BFD_RELOC_ARM_MOVT
:
19172 if (fixp
->fx_pcrel
)
19174 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19178 case BFD_RELOC_ARM_THUMB_MOVW
:
19179 if (fixp
->fx_pcrel
)
19181 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19185 case BFD_RELOC_ARM_THUMB_MOVT
:
19186 if (fixp
->fx_pcrel
)
19188 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19192 case BFD_RELOC_NONE
:
19193 case BFD_RELOC_ARM_PCREL_BRANCH
:
19194 case BFD_RELOC_ARM_PCREL_BLX
:
19195 case BFD_RELOC_RVA
:
19196 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19197 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19198 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19199 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19200 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19201 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19202 case BFD_RELOC_THUMB_PCREL_BLX
:
19203 case BFD_RELOC_VTABLE_ENTRY
:
19204 case BFD_RELOC_VTABLE_INHERIT
:
19206 case BFD_RELOC_32_SECREL
:
19208 code
= fixp
->fx_r_type
;
19211 case BFD_RELOC_ARM_LITERAL
:
19212 case BFD_RELOC_ARM_HWLITERAL
:
19213 /* If this is called then the a literal has
19214 been referenced across a section boundary. */
19215 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19216 _("literal referenced across section boundary"));
19220 case BFD_RELOC_ARM_GOT32
:
19221 case BFD_RELOC_ARM_GOTOFF
:
19222 case BFD_RELOC_ARM_PLT32
:
19223 case BFD_RELOC_ARM_TARGET1
:
19224 case BFD_RELOC_ARM_ROSEGREL32
:
19225 case BFD_RELOC_ARM_SBREL32
:
19226 case BFD_RELOC_ARM_PREL31
:
19227 case BFD_RELOC_ARM_TARGET2
:
19228 case BFD_RELOC_ARM_TLS_LE32
:
19229 case BFD_RELOC_ARM_TLS_LDO32
:
19230 case BFD_RELOC_ARM_PCREL_CALL
:
19231 case BFD_RELOC_ARM_PCREL_JUMP
:
19232 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19233 case BFD_RELOC_ARM_ALU_PC_G0
:
19234 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19235 case BFD_RELOC_ARM_ALU_PC_G1
:
19236 case BFD_RELOC_ARM_ALU_PC_G2
:
19237 case BFD_RELOC_ARM_LDR_PC_G0
:
19238 case BFD_RELOC_ARM_LDR_PC_G1
:
19239 case BFD_RELOC_ARM_LDR_PC_G2
:
19240 case BFD_RELOC_ARM_LDRS_PC_G0
:
19241 case BFD_RELOC_ARM_LDRS_PC_G1
:
19242 case BFD_RELOC_ARM_LDRS_PC_G2
:
19243 case BFD_RELOC_ARM_LDC_PC_G0
:
19244 case BFD_RELOC_ARM_LDC_PC_G1
:
19245 case BFD_RELOC_ARM_LDC_PC_G2
:
19246 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19247 case BFD_RELOC_ARM_ALU_SB_G0
:
19248 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19249 case BFD_RELOC_ARM_ALU_SB_G1
:
19250 case BFD_RELOC_ARM_ALU_SB_G2
:
19251 case BFD_RELOC_ARM_LDR_SB_G0
:
19252 case BFD_RELOC_ARM_LDR_SB_G1
:
19253 case BFD_RELOC_ARM_LDR_SB_G2
:
19254 case BFD_RELOC_ARM_LDRS_SB_G0
:
19255 case BFD_RELOC_ARM_LDRS_SB_G1
:
19256 case BFD_RELOC_ARM_LDRS_SB_G2
:
19257 case BFD_RELOC_ARM_LDC_SB_G0
:
19258 case BFD_RELOC_ARM_LDC_SB_G1
:
19259 case BFD_RELOC_ARM_LDC_SB_G2
:
19260 case BFD_RELOC_ARM_V4BX
:
19261 code
= fixp
->fx_r_type
;
19264 case BFD_RELOC_ARM_TLS_GD32
:
19265 case BFD_RELOC_ARM_TLS_IE32
:
19266 case BFD_RELOC_ARM_TLS_LDM32
:
19267 /* BFD will include the symbol's address in the addend.
19268 But we don't want that, so subtract it out again here. */
19269 if (!S_IS_COMMON (fixp
->fx_addsy
))
19270 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19271 code
= fixp
->fx_r_type
;
19275 case BFD_RELOC_ARM_IMMEDIATE
:
19276 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19277 _("internal relocation (type: IMMEDIATE) not fixed up"));
19280 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19281 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19282 _("ADRL used for a symbol not defined in the same file"));
19285 case BFD_RELOC_ARM_OFFSET_IMM
:
19286 if (section
->use_rela_p
)
19288 code
= fixp
->fx_r_type
;
19292 if (fixp
->fx_addsy
!= NULL
19293 && !S_IS_DEFINED (fixp
->fx_addsy
)
19294 && S_IS_LOCAL (fixp
->fx_addsy
))
19296 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19297 _("undefined local label `%s'"),
19298 S_GET_NAME (fixp
->fx_addsy
));
19302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19303 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19310 switch (fixp
->fx_r_type
)
19312 case BFD_RELOC_NONE
: type
= "NONE"; break;
19313 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19314 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19315 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19316 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19317 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19318 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19319 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19320 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19321 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19322 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19323 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19324 default: type
= _("<unknown>"); break;
19326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19327 _("cannot represent %s relocation in this object file format"),
19334 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19336 && fixp
->fx_addsy
== GOT_symbol
)
19338 code
= BFD_RELOC_ARM_GOTPC
;
19339 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19343 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19345 if (reloc
->howto
== NULL
)
19347 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19348 _("cannot represent %s relocation in this object file format"),
19349 bfd_get_reloc_code_name (code
));
19353 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19354 vtable entry to be used in the relocation's section offset. */
19355 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19356 reloc
->address
= fixp
->fx_offset
;
19361 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19364 cons_fix_new_arm (fragS
* frag
,
19369 bfd_reloc_code_real_type type
;
19373 FIXME: @@ Should look at CPU word size. */
19377 type
= BFD_RELOC_8
;
19380 type
= BFD_RELOC_16
;
19384 type
= BFD_RELOC_32
;
19387 type
= BFD_RELOC_64
;
19392 if (exp
->X_op
== O_secrel
)
19394 exp
->X_op
= O_symbol
;
19395 type
= BFD_RELOC_32_SECREL
;
19399 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19402 #if defined OBJ_COFF || defined OBJ_ELF
19404 arm_validate_fix (fixS
* fixP
)
19406 /* If the destination of the branch is a defined symbol which does not have
19407 the THUMB_FUNC attribute, then we must be calling a function which has
19408 the (interfacearm) attribute. We look for the Thumb entry point to that
19409 function and change the branch to refer to that function instead. */
19410 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19411 && fixP
->fx_addsy
!= NULL
19412 && S_IS_DEFINED (fixP
->fx_addsy
)
19413 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19415 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19421 arm_force_relocation (struct fix
* fixp
)
19423 #if defined (OBJ_COFF) && defined (TE_PE)
19424 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19428 /* Resolve these relocations even if the symbol is extern or weak. */
19429 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19430 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19431 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19432 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19433 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19434 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19435 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19438 /* Always leave these relocations for the linker. */
19439 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19440 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19441 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19444 /* Always generate relocations against function symbols. */
19445 if (fixp
->fx_r_type
== BFD_RELOC_32
19447 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19450 return generic_force_reloc (fixp
);
19453 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19454 /* Relocations against function names must be left unadjusted,
19455 so that the linker can use this information to generate interworking
19456 stubs. The MIPS version of this function
19457 also prevents relocations that are mips-16 specific, but I do not
19458 know why it does this.
19461 There is one other problem that ought to be addressed here, but
19462 which currently is not: Taking the address of a label (rather
19463 than a function) and then later jumping to that address. Such
19464 addresses also ought to have their bottom bit set (assuming that
19465 they reside in Thumb code), but at the moment they will not. */
19468 arm_fix_adjustable (fixS
* fixP
)
19470 if (fixP
->fx_addsy
== NULL
)
19473 /* Preserve relocations against symbols with function type. */
19474 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19477 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19478 && fixP
->fx_subsy
== NULL
)
19481 /* We need the symbol name for the VTABLE entries. */
19482 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19483 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19486 /* Don't allow symbols to be discarded on GOT related relocs. */
19487 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19488 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19489 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19490 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19491 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19492 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19493 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19494 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19495 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19498 /* Similarly for group relocations. */
19499 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19500 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19501 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19504 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
19505 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
19506 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19507 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
19508 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
19509 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19510 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
19511 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
19512 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
19517 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19522 elf32_arm_target_format (void)
19525 return (target_big_endian
19526 ? "elf32-bigarm-symbian"
19527 : "elf32-littlearm-symbian");
19528 #elif defined (TE_VXWORKS)
19529 return (target_big_endian
19530 ? "elf32-bigarm-vxworks"
19531 : "elf32-littlearm-vxworks");
19533 if (target_big_endian
)
19534 return "elf32-bigarm";
19536 return "elf32-littlearm";
19541 armelf_frob_symbol (symbolS
* symp
,
19544 elf_frob_symbol (symp
, puntp
);
19548 /* MD interface: Finalization. */
19550 /* A good place to do this, although this was probably not intended
19551 for this kind of use. We need to dump the literal pool before
19552 references are made to a null symbol pointer. */
19557 literal_pool
* pool
;
19559 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19561 /* Put it at the end of the relevant section. */
19562 subseg_set (pool
->section
, pool
->sub_section
);
19564 arm_elf_change_section ();
19570 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19574 arm_adjust_symtab (void)
19579 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19581 if (ARM_IS_THUMB (sym
))
19583 if (THUMB_IS_FUNC (sym
))
19585 /* Mark the symbol as a Thumb function. */
19586 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19587 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19588 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19590 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19591 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19593 as_bad (_("%s: unexpected function type: %d"),
19594 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19596 else switch (S_GET_STORAGE_CLASS (sym
))
19599 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19602 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19605 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19613 if (ARM_IS_INTERWORK (sym
))
19614 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19621 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19623 if (ARM_IS_THUMB (sym
))
19625 elf_symbol_type
* elf_sym
;
19627 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19628 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19630 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19631 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19633 /* If it's a .thumb_func, declare it as so,
19634 otherwise tag label as .code 16. */
19635 if (THUMB_IS_FUNC (sym
))
19636 elf_sym
->internal_elf_sym
.st_info
=
19637 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19638 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19639 elf_sym
->internal_elf_sym
.st_info
=
19640 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19647 /* MD interface: Initialization. */
19650 set_constant_flonums (void)
19654 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19655 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19659 /* Auto-select Thumb mode if it's the only available instruction set for the
19660 given architecture. */
19663 autoselect_thumb_from_cpu_variant (void)
19665 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19666 opcode_select (16);
19675 if ( (arm_ops_hsh
= hash_new ()) == NULL
19676 || (arm_cond_hsh
= hash_new ()) == NULL
19677 || (arm_shift_hsh
= hash_new ()) == NULL
19678 || (arm_psr_hsh
= hash_new ()) == NULL
19679 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19680 || (arm_reg_hsh
= hash_new ()) == NULL
19681 || (arm_reloc_hsh
= hash_new ()) == NULL
19682 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19683 as_fatal (_("virtual memory exhausted"));
19685 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19686 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
19687 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19688 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
19689 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19690 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
19691 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19692 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
19693 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19694 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
19695 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19696 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
19698 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19700 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19701 (void *) (barrier_opt_names
+ i
));
19703 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19704 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
19707 set_constant_flonums ();
19709 /* Set the cpu variant based on the command-line options. We prefer
19710 -mcpu= over -march= if both are set (as for GCC); and we prefer
19711 -mfpu= over any other way of setting the floating point unit.
19712 Use of legacy options with new options are faulted. */
19715 if (mcpu_cpu_opt
|| march_cpu_opt
)
19716 as_bad (_("use of old and new-style options to set CPU type"));
19718 mcpu_cpu_opt
= legacy_cpu
;
19720 else if (!mcpu_cpu_opt
)
19721 mcpu_cpu_opt
= march_cpu_opt
;
19726 as_bad (_("use of old and new-style options to set FPU type"));
19728 mfpu_opt
= legacy_fpu
;
19730 else if (!mfpu_opt
)
19732 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19733 /* Some environments specify a default FPU. If they don't, infer it
19734 from the processor. */
19736 mfpu_opt
= mcpu_fpu_opt
;
19738 mfpu_opt
= march_fpu_opt
;
19740 mfpu_opt
= &fpu_default
;
19746 if (mcpu_cpu_opt
!= NULL
)
19747 mfpu_opt
= &fpu_default
;
19748 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19749 mfpu_opt
= &fpu_arch_vfp_v2
;
19751 mfpu_opt
= &fpu_arch_fpa
;
19757 mcpu_cpu_opt
= &cpu_default
;
19758 selected_cpu
= cpu_default
;
19762 selected_cpu
= *mcpu_cpu_opt
;
19764 mcpu_cpu_opt
= &arm_arch_any
;
19767 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19769 autoselect_thumb_from_cpu_variant ();
19771 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19773 #if defined OBJ_COFF || defined OBJ_ELF
19775 unsigned int flags
= 0;
19777 #if defined OBJ_ELF
19778 flags
= meabi_flags
;
19780 switch (meabi_flags
)
19782 case EF_ARM_EABI_UNKNOWN
:
19784 /* Set the flags in the private structure. */
19785 if (uses_apcs_26
) flags
|= F_APCS26
;
19786 if (support_interwork
) flags
|= F_INTERWORK
;
19787 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19788 if (pic_code
) flags
|= F_PIC
;
19789 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19790 flags
|= F_SOFT_FLOAT
;
19792 switch (mfloat_abi_opt
)
19794 case ARM_FLOAT_ABI_SOFT
:
19795 case ARM_FLOAT_ABI_SOFTFP
:
19796 flags
|= F_SOFT_FLOAT
;
19799 case ARM_FLOAT_ABI_HARD
:
19800 if (flags
& F_SOFT_FLOAT
)
19801 as_bad (_("hard-float conflicts with specified fpu"));
19805 /* Using pure-endian doubles (even if soft-float). */
19806 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19807 flags
|= F_VFP_FLOAT
;
19809 #if defined OBJ_ELF
19810 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19811 flags
|= EF_ARM_MAVERICK_FLOAT
;
19814 case EF_ARM_EABI_VER4
:
19815 case EF_ARM_EABI_VER5
:
19816 /* No additional flags to set. */
19823 bfd_set_private_flags (stdoutput
, flags
);
19825 /* We have run out flags in the COFF header to encode the
19826 status of ATPCS support, so instead we create a dummy,
19827 empty, debug section called .arm.atpcs. */
19832 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19836 bfd_set_section_flags
19837 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19838 bfd_set_section_size (stdoutput
, sec
, 0);
19839 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19845 /* Record the CPU type as well. */
19846 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19847 mach
= bfd_mach_arm_iWMMXt2
;
19848 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19849 mach
= bfd_mach_arm_iWMMXt
;
19850 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19851 mach
= bfd_mach_arm_XScale
;
19852 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19853 mach
= bfd_mach_arm_ep9312
;
19854 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19855 mach
= bfd_mach_arm_5TE
;
19856 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19858 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19859 mach
= bfd_mach_arm_5T
;
19861 mach
= bfd_mach_arm_5
;
19863 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19865 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19866 mach
= bfd_mach_arm_4T
;
19868 mach
= bfd_mach_arm_4
;
19870 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19871 mach
= bfd_mach_arm_3M
;
19872 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19873 mach
= bfd_mach_arm_3
;
19874 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19875 mach
= bfd_mach_arm_2a
;
19876 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19877 mach
= bfd_mach_arm_2
;
19879 mach
= bfd_mach_arm_unknown
;
19881 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19884 /* Command line processing. */
19887 Invocation line includes a switch not recognized by the base assembler.
19888 See if it's a processor-specific option.
19890 This routine is somewhat complicated by the need for backwards
19891 compatibility (since older releases of gcc can't be changed).
19892 The new options try to make the interface as compatible as
19895 New options (supported) are:
19897 -mcpu=<cpu name> Assemble for selected processor
19898 -march=<architecture name> Assemble for selected architecture
19899 -mfpu=<fpu architecture> Assemble for selected FPU.
19900 -EB/-mbig-endian Big-endian
19901 -EL/-mlittle-endian Little-endian
19902 -k Generate PIC code
19903 -mthumb Start in Thumb mode
19904 -mthumb-interwork Code supports ARM/Thumb interworking
19906 -m[no-]warn-deprecated Warn about deprecated features
19908 For now we will also provide support for:
19910 -mapcs-32 32-bit Program counter
19911 -mapcs-26 26-bit Program counter
19912 -macps-float Floats passed in FP registers
19913 -mapcs-reentrant Reentrant code
19915 (sometime these will probably be replaced with -mapcs=<list of options>
19916 and -matpcs=<list of options>)
19918 The remaining options are only supported for back-wards compatibility.
19919 Cpu variants, the arm part is optional:
19920 -m[arm]1 Currently not supported.
19921 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19922 -m[arm]3 Arm 3 processor
19923 -m[arm]6[xx], Arm 6 processors
19924 -m[arm]7[xx][t][[d]m] Arm 7 processors
19925 -m[arm]8[10] Arm 8 processors
19926 -m[arm]9[20][tdmi] Arm 9 processors
19927 -mstrongarm[110[0]] StrongARM processors
19928 -mxscale XScale processors
19929 -m[arm]v[2345[t[e]]] Arm architectures
19930 -mall All (except the ARM1)
19932 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19933 -mfpe-old (No float load/store multiples)
19934 -mvfpxd VFP Single precision
19936 -mno-fpu Disable all floating point instructions
19938 The following CPU names are recognized:
19939 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19940 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19941 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19942 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19943 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19944 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19945 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19949 const char * md_shortopts
= "m:k";
19951 #ifdef ARM_BI_ENDIAN
19952 #define OPTION_EB (OPTION_MD_BASE + 0)
19953 #define OPTION_EL (OPTION_MD_BASE + 1)
19955 #if TARGET_BYTES_BIG_ENDIAN
19956 #define OPTION_EB (OPTION_MD_BASE + 0)
19958 #define OPTION_EL (OPTION_MD_BASE + 1)
19961 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
19963 struct option md_longopts
[] =
19966 {"EB", no_argument
, NULL
, OPTION_EB
},
19969 {"EL", no_argument
, NULL
, OPTION_EL
},
19971 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
19972 {NULL
, no_argument
, NULL
, 0}
19975 size_t md_longopts_size
= sizeof (md_longopts
);
19977 struct arm_option_table
19979 char *option
; /* Option name to match. */
19980 char *help
; /* Help information. */
19981 int *var
; /* Variable to change. */
19982 int value
; /* What to change it to. */
19983 char *deprecated
; /* If non-null, print this message. */
19986 struct arm_option_table arm_opts
[] =
19988 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19989 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19990 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19991 &support_interwork
, 1, NULL
},
19992 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19993 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19994 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19996 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19997 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19998 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19999 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
20002 /* These are recognized by the assembler, but have no affect on code. */
20003 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20004 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20006 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
20007 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
20008 &warn_on_deprecated
, 0, NULL
},
20009 {NULL
, NULL
, NULL
, 0, NULL
}
20012 struct arm_legacy_option_table
20014 char *option
; /* Option name to match. */
20015 const arm_feature_set
**var
; /* Variable to change. */
20016 const arm_feature_set value
; /* What to change it to. */
20017 char *deprecated
; /* If non-null, print this message. */
20020 const struct arm_legacy_option_table arm_legacy_opts
[] =
20022 /* DON'T add any new processors to this list -- we want the whole list
20023 to go away... Add them to the processors table instead. */
20024 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20025 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20026 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20027 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20028 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20029 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20030 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20031 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20032 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20033 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20034 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20035 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20036 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20037 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20038 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20039 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20040 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20041 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20042 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20043 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20044 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20045 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20046 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20047 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20048 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20049 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20050 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20051 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20052 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20053 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20054 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20055 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20056 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20057 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20058 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20059 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20060 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20061 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20062 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20063 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20064 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20065 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20066 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20067 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20068 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20069 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20070 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20071 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20072 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20073 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20074 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20075 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20076 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20077 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20078 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20079 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20080 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20081 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20082 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20083 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20084 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20085 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20086 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20087 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20088 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20089 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20090 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20091 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20092 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20093 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20094 N_("use -mcpu=strongarm110")},
20095 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20096 N_("use -mcpu=strongarm1100")},
20097 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20098 N_("use -mcpu=strongarm1110")},
20099 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20100 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20101 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20103 /* Architecture variants -- don't add any more to this list either. */
20104 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20105 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20106 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20107 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20108 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20109 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20110 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20111 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20112 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20113 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20114 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20115 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20116 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20117 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20118 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20119 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20120 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20121 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20123 /* Floating point variants -- don't add any more to this list either. */
20124 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20125 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20126 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20127 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20128 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20130 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20133 struct arm_cpu_option_table
20136 const arm_feature_set value
;
20137 /* For some CPUs we assume an FPU unless the user explicitly sets
20139 const arm_feature_set default_fpu
;
20140 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20142 const char *canonical_name
;
20145 /* This list should, at a minimum, contain all the cpu names
20146 recognized by GCC. */
20147 static const struct arm_cpu_option_table arm_cpus
[] =
20149 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20150 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20151 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20152 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20153 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20154 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20155 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20156 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20157 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20158 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20159 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20160 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20161 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20162 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20163 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20164 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20165 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20166 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20167 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20168 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20169 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20170 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20171 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20172 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20173 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20174 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20175 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20176 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20177 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20178 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20179 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20180 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20181 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20182 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20183 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20184 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20185 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20186 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20187 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20188 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20189 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20190 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20191 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20192 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20193 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20194 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20195 /* For V5 or later processors we default to using VFP; but the user
20196 should really set the FPU type explicitly. */
20197 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20198 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20199 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20200 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20201 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20202 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20203 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20204 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20205 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20206 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20207 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20208 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20209 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20210 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20211 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20212 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20213 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20214 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20215 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20216 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20217 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20218 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20219 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20220 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20221 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20222 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20223 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20224 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20225 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20226 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20227 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20228 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20229 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20230 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20231 | FPU_NEON_EXT_V1
),
20233 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20234 | FPU_NEON_EXT_V1
),
20236 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20237 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20238 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20239 /* ??? XSCALE is really an architecture. */
20240 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20241 /* ??? iwmmxt is not a processor. */
20242 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20243 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20244 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20246 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20247 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20250 struct arm_arch_option_table
20253 const arm_feature_set value
;
20254 const arm_feature_set default_fpu
;
20257 /* This list should, at a minimum, contain all the architecture names
20258 recognized by GCC. */
20259 static const struct arm_arch_option_table arm_archs
[] =
20261 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20262 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20263 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20264 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20265 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20266 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20267 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20268 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20269 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20270 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20271 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20272 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20273 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20274 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20275 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20276 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20277 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20278 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20279 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20280 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20281 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20282 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20283 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20284 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20285 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20286 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20287 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20288 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20289 /* The official spelling of the ARMv7 profile variants is the dashed form.
20290 Accept the non-dashed form for compatibility with old toolchains. */
20291 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20292 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20293 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20294 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20295 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20296 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20297 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20298 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20299 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20300 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20303 /* ISA extensions in the co-processor space. */
20304 struct arm_option_cpu_value_table
20307 const arm_feature_set value
;
20310 static const struct arm_option_cpu_value_table arm_extensions
[] =
20312 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20313 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20314 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20315 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20316 {NULL
, ARM_ARCH_NONE
}
20319 /* This list should, at a minimum, contain all the fpu names
20320 recognized by GCC. */
20321 static const struct arm_option_cpu_value_table arm_fpus
[] =
20323 {"softfpa", FPU_NONE
},
20324 {"fpe", FPU_ARCH_FPE
},
20325 {"fpe2", FPU_ARCH_FPE
},
20326 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20327 {"fpa", FPU_ARCH_FPA
},
20328 {"fpa10", FPU_ARCH_FPA
},
20329 {"fpa11", FPU_ARCH_FPA
},
20330 {"arm7500fe", FPU_ARCH_FPA
},
20331 {"softvfp", FPU_ARCH_VFP
},
20332 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20333 {"vfp", FPU_ARCH_VFP_V2
},
20334 {"vfp9", FPU_ARCH_VFP_V2
},
20335 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
20336 {"vfp10", FPU_ARCH_VFP_V2
},
20337 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20338 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20339 {"vfpv2", FPU_ARCH_VFP_V2
},
20340 {"vfpv3", FPU_ARCH_VFP_V3
},
20341 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
20342 {"arm1020t", FPU_ARCH_VFP_V1
},
20343 {"arm1020e", FPU_ARCH_VFP_V2
},
20344 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20345 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20346 {"maverick", FPU_ARCH_MAVERICK
},
20347 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20348 {"neon-fp16", FPU_ARCH_NEON_FP16
},
20349 {NULL
, ARM_ARCH_NONE
}
20352 struct arm_option_value_table
20358 static const struct arm_option_value_table arm_float_abis
[] =
20360 {"hard", ARM_FLOAT_ABI_HARD
},
20361 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20362 {"soft", ARM_FLOAT_ABI_SOFT
},
20367 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20368 static const struct arm_option_value_table arm_eabis
[] =
20370 {"gnu", EF_ARM_EABI_UNKNOWN
},
20371 {"4", EF_ARM_EABI_VER4
},
20372 {"5", EF_ARM_EABI_VER5
},
20377 struct arm_long_option_table
20379 char * option
; /* Substring to match. */
20380 char * help
; /* Help information. */
20381 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20382 char * deprecated
; /* If non-null, print this message. */
20386 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20388 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20390 /* Copy the feature set, so that we can modify it. */
20391 *ext_set
= **opt_p
;
20394 while (str
!= NULL
&& *str
!= 0)
20396 const struct arm_option_cpu_value_table
* opt
;
20402 as_bad (_("invalid architectural extension"));
20407 ext
= strchr (str
, '+');
20410 optlen
= ext
- str
;
20412 optlen
= strlen (str
);
20416 as_bad (_("missing architectural extension"));
20420 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20421 if (strncmp (opt
->name
, str
, optlen
) == 0)
20423 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20427 if (opt
->name
== NULL
)
20429 as_bad (_("unknown architectural extension `%s'"), str
);
20440 arm_parse_cpu (char * str
)
20442 const struct arm_cpu_option_table
* opt
;
20443 char * ext
= strchr (str
, '+');
20447 optlen
= ext
- str
;
20449 optlen
= strlen (str
);
20453 as_bad (_("missing cpu name `%s'"), str
);
20457 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20458 if (strncmp (opt
->name
, str
, optlen
) == 0)
20460 mcpu_cpu_opt
= &opt
->value
;
20461 mcpu_fpu_opt
= &opt
->default_fpu
;
20462 if (opt
->canonical_name
)
20463 strcpy (selected_cpu_name
, opt
->canonical_name
);
20467 for (i
= 0; i
< optlen
; i
++)
20468 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20469 selected_cpu_name
[i
] = 0;
20473 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20478 as_bad (_("unknown cpu `%s'"), str
);
20483 arm_parse_arch (char * str
)
20485 const struct arm_arch_option_table
*opt
;
20486 char *ext
= strchr (str
, '+');
20490 optlen
= ext
- str
;
20492 optlen
= strlen (str
);
20496 as_bad (_("missing architecture name `%s'"), str
);
20500 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20501 if (streq (opt
->name
, str
))
20503 march_cpu_opt
= &opt
->value
;
20504 march_fpu_opt
= &opt
->default_fpu
;
20505 strcpy (selected_cpu_name
, opt
->name
);
20508 return arm_parse_extension (ext
, &march_cpu_opt
);
20513 as_bad (_("unknown architecture `%s'\n"), str
);
20518 arm_parse_fpu (char * str
)
20520 const struct arm_option_cpu_value_table
* opt
;
20522 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20523 if (streq (opt
->name
, str
))
20525 mfpu_opt
= &opt
->value
;
20529 as_bad (_("unknown floating point format `%s'\n"), str
);
20534 arm_parse_float_abi (char * str
)
20536 const struct arm_option_value_table
* opt
;
20538 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20539 if (streq (opt
->name
, str
))
20541 mfloat_abi_opt
= opt
->value
;
20545 as_bad (_("unknown floating point abi `%s'\n"), str
);
20551 arm_parse_eabi (char * str
)
20553 const struct arm_option_value_table
*opt
;
20555 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20556 if (streq (opt
->name
, str
))
20558 meabi_flags
= opt
->value
;
20561 as_bad (_("unknown EABI `%s'\n"), str
);
20566 struct arm_long_option_table arm_long_opts
[] =
20568 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20569 arm_parse_cpu
, NULL
},
20570 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20571 arm_parse_arch
, NULL
},
20572 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20573 arm_parse_fpu
, NULL
},
20574 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20575 arm_parse_float_abi
, NULL
},
20577 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
20578 arm_parse_eabi
, NULL
},
20580 {NULL
, NULL
, 0, NULL
}
20584 md_parse_option (int c
, char * arg
)
20586 struct arm_option_table
*opt
;
20587 const struct arm_legacy_option_table
*fopt
;
20588 struct arm_long_option_table
*lopt
;
20594 target_big_endian
= 1;
20600 target_big_endian
= 0;
20604 case OPTION_FIX_V4BX
:
20609 /* Listing option. Just ignore these, we don't support additional
20614 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20616 if (c
== opt
->option
[0]
20617 && ((arg
== NULL
&& opt
->option
[1] == 0)
20618 || streq (arg
, opt
->option
+ 1)))
20620 /* If the option is deprecated, tell the user. */
20621 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
20622 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20623 arg
? arg
: "", _(opt
->deprecated
));
20625 if (opt
->var
!= NULL
)
20626 *opt
->var
= opt
->value
;
20632 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20634 if (c
== fopt
->option
[0]
20635 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20636 || streq (arg
, fopt
->option
+ 1)))
20638 /* If the option is deprecated, tell the user. */
20639 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
20640 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20641 arg
? arg
: "", _(fopt
->deprecated
));
20643 if (fopt
->var
!= NULL
)
20644 *fopt
->var
= &fopt
->value
;
20650 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20652 /* These options are expected to have an argument. */
20653 if (c
== lopt
->option
[0]
20655 && strncmp (arg
, lopt
->option
+ 1,
20656 strlen (lopt
->option
+ 1)) == 0)
20658 /* If the option is deprecated, tell the user. */
20659 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
20660 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20661 _(lopt
->deprecated
));
20663 /* Call the sup-option parser. */
20664 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20675 md_show_usage (FILE * fp
)
20677 struct arm_option_table
*opt
;
20678 struct arm_long_option_table
*lopt
;
20680 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20682 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20683 if (opt
->help
!= NULL
)
20684 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20686 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20687 if (lopt
->help
!= NULL
)
20688 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20692 -EB assemble code for a big-endian cpu\n"));
20697 -EL assemble code for a little-endian cpu\n"));
20701 --fix-v4bx Allow BX in ARMv4 code\n"));
20709 arm_feature_set flags
;
20710 } cpu_arch_ver_table
;
20712 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20713 least features first. */
20714 static const cpu_arch_ver_table cpu_arch_ver
[] =
20719 {4, ARM_ARCH_V5TE
},
20720 {5, ARM_ARCH_V5TEJ
},
20724 {11, ARM_ARCH_V6M
},
20725 {8, ARM_ARCH_V6T2
},
20726 {10, ARM_ARCH_V7A
},
20727 {10, ARM_ARCH_V7R
},
20728 {10, ARM_ARCH_V7M
},
20732 /* Set the public EABI object attributes. */
20734 aeabi_set_public_attributes (void)
20737 arm_feature_set flags
;
20738 arm_feature_set tmp
;
20739 const cpu_arch_ver_table
*p
;
20741 /* Choose the architecture based on the capabilities of the requested cpu
20742 (if any) and/or the instructions actually used. */
20743 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20744 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20745 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20746 /*Allow the user to override the reported architecture. */
20749 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20750 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20755 for (p
= cpu_arch_ver
; p
->val
; p
++)
20757 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20760 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20764 /* Tag_CPU_name. */
20765 if (selected_cpu_name
[0])
20769 p
= selected_cpu_name
;
20770 if (strncmp (p
, "armv", 4) == 0)
20775 for (i
= 0; p
[i
]; i
++)
20776 p
[i
] = TOUPPER (p
[i
]);
20778 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20780 /* Tag_CPU_arch. */
20781 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20782 /* Tag_CPU_arch_profile. */
20783 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20784 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20785 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20786 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20787 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
20788 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20789 /* Tag_ARM_ISA_use. */
20790 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20791 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20792 /* Tag_THUMB_ISA_use. */
20793 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20794 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20795 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20796 /* Tag_VFP_arch. */
20797 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_d32
)
20798 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_d32
))
20799 bfd_elf_add_proc_attr_int (stdoutput
, 10, 4);
20800 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20801 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20802 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20803 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20804 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20805 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20806 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20807 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20808 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20809 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20810 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20811 /* Tag_WMMX_arch. */
20812 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20813 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20814 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20815 /* Tag_NEON_arch. */
20816 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
20817 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20818 /* Tag_NEON_FP16_arch. */
20819 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
20820 bfd_elf_add_proc_attr_int (stdoutput
, 36, 1);
20823 /* Add the default contents for the .ARM.attributes section. */
20827 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20830 aeabi_set_public_attributes ();
20832 #endif /* OBJ_ELF */
20835 /* Parse a .cpu directive. */
20838 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20840 const struct arm_cpu_option_table
*opt
;
20844 name
= input_line_pointer
;
20845 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20846 input_line_pointer
++;
20847 saved_char
= *input_line_pointer
;
20848 *input_line_pointer
= 0;
20850 /* Skip the first "all" entry. */
20851 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20852 if (streq (opt
->name
, name
))
20854 mcpu_cpu_opt
= &opt
->value
;
20855 selected_cpu
= opt
->value
;
20856 if (opt
->canonical_name
)
20857 strcpy (selected_cpu_name
, opt
->canonical_name
);
20861 for (i
= 0; opt
->name
[i
]; i
++)
20862 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20863 selected_cpu_name
[i
] = 0;
20865 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20866 *input_line_pointer
= saved_char
;
20867 demand_empty_rest_of_line ();
20870 as_bad (_("unknown cpu `%s'"), name
);
20871 *input_line_pointer
= saved_char
;
20872 ignore_rest_of_line ();
20876 /* Parse a .arch directive. */
20879 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20881 const struct arm_arch_option_table
*opt
;
20885 name
= input_line_pointer
;
20886 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20887 input_line_pointer
++;
20888 saved_char
= *input_line_pointer
;
20889 *input_line_pointer
= 0;
20891 /* Skip the first "all" entry. */
20892 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20893 if (streq (opt
->name
, name
))
20895 mcpu_cpu_opt
= &opt
->value
;
20896 selected_cpu
= opt
->value
;
20897 strcpy (selected_cpu_name
, opt
->name
);
20898 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20899 *input_line_pointer
= saved_char
;
20900 demand_empty_rest_of_line ();
20904 as_bad (_("unknown architecture `%s'\n"), name
);
20905 *input_line_pointer
= saved_char
;
20906 ignore_rest_of_line ();
20910 /* Parse a .object_arch directive. */
20913 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20915 const struct arm_arch_option_table
*opt
;
20919 name
= input_line_pointer
;
20920 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20921 input_line_pointer
++;
20922 saved_char
= *input_line_pointer
;
20923 *input_line_pointer
= 0;
20925 /* Skip the first "all" entry. */
20926 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20927 if (streq (opt
->name
, name
))
20929 object_arch
= &opt
->value
;
20930 *input_line_pointer
= saved_char
;
20931 demand_empty_rest_of_line ();
20935 as_bad (_("unknown architecture `%s'\n"), name
);
20936 *input_line_pointer
= saved_char
;
20937 ignore_rest_of_line ();
20940 /* Parse a .fpu directive. */
20943 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20945 const struct arm_option_cpu_value_table
*opt
;
20949 name
= input_line_pointer
;
20950 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20951 input_line_pointer
++;
20952 saved_char
= *input_line_pointer
;
20953 *input_line_pointer
= 0;
20955 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20956 if (streq (opt
->name
, name
))
20958 mfpu_opt
= &opt
->value
;
20959 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20960 *input_line_pointer
= saved_char
;
20961 demand_empty_rest_of_line ();
20965 as_bad (_("unknown floating point format `%s'\n"), name
);
20966 *input_line_pointer
= saved_char
;
20967 ignore_rest_of_line ();
20970 /* Copy symbol information. */
20973 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20975 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
20979 /* Given a symbolic attribute NAME, return the proper integer value.
20980 Returns -1 if the attribute is not known. */
20983 arm_convert_symbolic_attribute (const char *name
)
20985 static const struct
20990 attribute_table
[] =
20992 /* When you modify this table you should
20993 also modify the list in doc/c-arm.texi. */
20994 #define T(tag) {#tag, tag}
20995 T (Tag_CPU_raw_name
),
20998 T (Tag_CPU_arch_profile
),
20999 T (Tag_ARM_ISA_use
),
21000 T (Tag_THUMB_ISA_use
),
21003 T (Tag_Advanced_SIMD_arch
),
21004 T (Tag_PCS_config
),
21005 T (Tag_ABI_PCS_R9_use
),
21006 T (Tag_ABI_PCS_RW_data
),
21007 T (Tag_ABI_PCS_RO_data
),
21008 T (Tag_ABI_PCS_GOT_use
),
21009 T (Tag_ABI_PCS_wchar_t
),
21010 T (Tag_ABI_FP_rounding
),
21011 T (Tag_ABI_FP_denormal
),
21012 T (Tag_ABI_FP_exceptions
),
21013 T (Tag_ABI_FP_user_exceptions
),
21014 T (Tag_ABI_FP_number_model
),
21015 T (Tag_ABI_align8_needed
),
21016 T (Tag_ABI_align8_preserved
),
21017 T (Tag_ABI_enum_size
),
21018 T (Tag_ABI_HardFP_use
),
21019 T (Tag_ABI_VFP_args
),
21020 T (Tag_ABI_WMMX_args
),
21021 T (Tag_ABI_optimization_goals
),
21022 T (Tag_ABI_FP_optimization_goals
),
21023 T (Tag_compatibility
),
21024 T (Tag_CPU_unaligned_access
),
21025 T (Tag_VFP_HP_extension
),
21026 T (Tag_ABI_FP_16bit_format
),
21027 T (Tag_nodefaults
),
21028 T (Tag_also_compatible_with
),
21029 T (Tag_conformance
),
21031 T (Tag_Virtualization_use
),
21032 T (Tag_MPextension_use
)
21040 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
21041 if (strcmp (name
, attribute_table
[i
].name
) == 0)
21042 return attribute_table
[i
].tag
;
21046 #endif /* OBJ_ELF */