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Cope with PE relocs.
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include <string.h>
25 #define NO_RELOC 0
26 #include "as.h"
27
28 /* need TARGET_CPU */
29 #include "config.h"
30 #include "subsegs.h"
31 #include "obstack.h"
32 #include "symbols.h"
33 #include "listing.h"
34
35 #ifdef OBJ_ELF
36 #include "elf/arm.h"
37 #endif
38
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
43 #define ARM_250 ARM_3
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
49
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55
56 /* Architectures are the sum of the base and extensions. */
57 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
58 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
59 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
60 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
61
62 /* Some useful combinations: */
63 #define ARM_ANY 0x00ffffff
64 #define ARM_2UP (ARM_ANY - ARM_1)
65 #define ARM_ALL ARM_2UP /* Not arm1 only */
66 #define ARM_3UP 0x00fffffc
67 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
68
69 #define FPU_CORE 0x80000000
70 #define FPU_FPA10 0x40000000
71 #define FPU_FPA11 0x40000000
72 #define FPU_NONE 0
73
74 /* Some useful combinations */
75 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
76 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
77
78
79 #ifndef CPU_DEFAULT
80 #if defined __thumb__
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
82 #else
83 #define CPU_DEFAULT ARM_ALL
84 #endif
85 #endif
86
87 #ifndef FPU_DEFAULT
88 #define FPU_DEFAULT FPU_ALL
89 #endif
90
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
93
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
96
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
103 #endif
104
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
108
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
117
118 #ifdef TE_LINUX
119 CONST char line_separator_chars[] = ";";
120 #else
121 CONST char line_separator_chars[] = "";
122 #endif
123
124 /* Chars that can be used to separate mant
125 from exp in floating point numbers. */
126 CONST char EXP_CHARS[] = "eE";
127
128 /* Chars that mean this number is a floating point constant */
129 /* As in 0f12.456 */
130 /* or 0d1.2345e12 */
131
132 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
133
134 /* Prefix characters that indicate the start of an immediate
135 value. */
136 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
137
138 #ifdef OBJ_ELF
139 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
140 #endif
141
142 CONST int md_reloc_size = 8; /* Size of relocation record */
143
144 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
145 2: assemble for Thumb even though target cpu
146 does not support thumb instructions. */
147 typedef struct arm_fix
148 {
149 int thumb_mode;
150 } arm_fix_data;
151
152 struct arm_it
153 {
154 CONST char * error;
155 unsigned long instruction;
156 int suffix;
157 int size;
158 struct
159 {
160 bfd_reloc_code_real_type type;
161 expressionS exp;
162 int pc_rel;
163 } reloc;
164 };
165
166 struct arm_it inst;
167
168 struct asm_shift
169 {
170 CONST char * template;
171 unsigned long value;
172 };
173
174 static CONST struct asm_shift shift[] =
175 {
176 {"asl", 0},
177 {"lsl", 0},
178 {"lsr", 0x00000020},
179 {"asr", 0x00000040},
180 {"ror", 0x00000060},
181 {"rrx", 0x00000060},
182 {"ASL", 0},
183 {"LSL", 0},
184 {"LSR", 0x00000020},
185 {"ASR", 0x00000040},
186 {"ROR", 0x00000060},
187 {"RRX", 0x00000060}
188 };
189
190 #define NO_SHIFT_RESTRICT 1
191 #define SHIFT_RESTRICT 0
192
193 #define NUM_FLOAT_VALS 8
194
195 CONST char * fp_const[] =
196 {
197 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
198 };
199
200 /* Number of littlenums required to hold an extended precision number. */
201 #define MAX_LITTLENUMS 6
202
203 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
204
205 #define FAIL (-1)
206 #define SUCCESS (0)
207
208 #define SUFF_S 1
209 #define SUFF_D 2
210 #define SUFF_E 3
211 #define SUFF_P 4
212
213 #define CP_T_X 0x00008000
214 #define CP_T_Y 0x00400000
215 #define CP_T_Pre 0x01000000
216 #define CP_T_UD 0x00800000
217 #define CP_T_WB 0x00200000
218
219 #define CONDS_BIT (0x00100000)
220 #define LOAD_BIT (0x00100000)
221 #define TRANS_BIT (0x00200000)
222
223 struct asm_cond
224 {
225 CONST char * template;
226 unsigned long value;
227 };
228
229 /* This is to save a hash look-up in the common case. */
230 #define COND_ALWAYS 0xe0000000
231
232 static CONST struct asm_cond conds[] =
233 {
234 {"eq", 0x00000000},
235 {"ne", 0x10000000},
236 {"cs", 0x20000000}, {"hs", 0x20000000},
237 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
238 {"mi", 0x40000000},
239 {"pl", 0x50000000},
240 {"vs", 0x60000000},
241 {"vc", 0x70000000},
242 {"hi", 0x80000000},
243 {"ls", 0x90000000},
244 {"ge", 0xa0000000},
245 {"lt", 0xb0000000},
246 {"gt", 0xc0000000},
247 {"le", 0xd0000000},
248 {"al", 0xe0000000},
249 {"nv", 0xf0000000}
250 };
251
252 /* Warning: If the top bit of the set_bits is set, then the standard
253 instruction bitmask is ignored, and the new bitmask is taken from
254 the set_bits: */
255 struct asm_flg
256 {
257 CONST char * template; /* Basic flag string */
258 unsigned long set_bits; /* Bits to set */
259 };
260
261 static CONST struct asm_flg s_flag[] =
262 {
263 {"s", CONDS_BIT},
264 {NULL, 0}
265 };
266
267 static CONST struct asm_flg ldr_flags[] =
268 {
269 {"b", 0x00400000},
270 {"t", TRANS_BIT},
271 {"bt", 0x00400000 | TRANS_BIT},
272 {"h", 0x801000b0},
273 {"sh", 0x801000f0},
274 {"sb", 0x801000d0},
275 {NULL, 0}
276 };
277
278 static CONST struct asm_flg str_flags[] =
279 {
280 {"b", 0x00400000},
281 {"t", TRANS_BIT},
282 {"bt", 0x00400000 | TRANS_BIT},
283 {"h", 0x800000b0},
284 {NULL, 0}
285 };
286
287 static CONST struct asm_flg byte_flag[] =
288 {
289 {"b", 0x00400000},
290 {NULL, 0}
291 };
292
293 static CONST struct asm_flg cmp_flags[] =
294 {
295 {"s", CONDS_BIT},
296 {"p", 0x0010f000},
297 {NULL, 0}
298 };
299
300 static CONST struct asm_flg ldm_flags[] =
301 {
302 {"ed", 0x01800000},
303 {"fd", 0x00800000},
304 {"ea", 0x01000000},
305 {"fa", 0x08000000},
306 {"ib", 0x01800000},
307 {"ia", 0x00800000},
308 {"db", 0x01000000},
309 {"da", 0x08000000},
310 {NULL, 0}
311 };
312
313 static CONST struct asm_flg stm_flags[] =
314 {
315 {"ed", 0x08000000},
316 {"fd", 0x01000000},
317 {"ea", 0x00800000},
318 {"fa", 0x01800000},
319 {"ib", 0x01800000},
320 {"ia", 0x00800000},
321 {"db", 0x01000000},
322 {"da", 0x08000000},
323 {NULL, 0}
324 };
325
326 static CONST struct asm_flg lfm_flags[] =
327 {
328 {"fd", 0x00800000},
329 {"ea", 0x01000000},
330 {NULL, 0}
331 };
332
333 static CONST struct asm_flg sfm_flags[] =
334 {
335 {"fd", 0x01000000},
336 {"ea", 0x00800000},
337 {NULL, 0}
338 };
339
340 static CONST struct asm_flg round_flags[] =
341 {
342 {"p", 0x00000020},
343 {"m", 0x00000040},
344 {"z", 0x00000060},
345 {NULL, 0}
346 };
347
348 /* The implementation of the FIX instruction is broken on some assemblers,
349 in that it accepts a precision specifier as well as a rounding specifier,
350 despite the fact that this is meaningless. To be more compatible, we
351 accept it as well, though of course it does not set any bits. */
352 static CONST struct asm_flg fix_flags[] =
353 {
354 {"p", 0x00000020},
355 {"m", 0x00000040},
356 {"z", 0x00000060},
357 {"sp", 0x00000020},
358 {"sm", 0x00000040},
359 {"sz", 0x00000060},
360 {"dp", 0x00000020},
361 {"dm", 0x00000040},
362 {"dz", 0x00000060},
363 {"ep", 0x00000020},
364 {"em", 0x00000040},
365 {"ez", 0x00000060},
366 {NULL, 0}
367 };
368
369 static CONST struct asm_flg except_flag[] =
370 {
371 {"e", 0x00400000},
372 {NULL, 0}
373 };
374
375 static CONST struct asm_flg cplong_flag[] =
376 {
377 {"l", 0x00400000},
378 {NULL, 0}
379 };
380
381 struct asm_psr
382 {
383 CONST char * template;
384 unsigned long number;
385 };
386
387 #define PSR_FIELD_MASK 0x000f0000
388
389 #define PSR_FLAGS 0x00080000
390 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
391 #define PSR_ALL 0x00090000
392
393 #define CPSR_ALL 0
394 #define SPSR_ALL 1
395 #define CPSR_FLG 2
396 #define SPSR_FLG 3
397 #define CPSR_CTL 4
398 #define SPSR_CTL 5
399
400 static CONST struct asm_psr psrs[] =
401 {
402 /* Valid <psr>'s */
403 {"cpsr", CPSR_ALL},
404 {"cpsr_all", CPSR_ALL},
405 {"spsr", SPSR_ALL},
406 {"spsr_all", SPSR_ALL},
407
408 /* Valid <psrf>'s */
409 {"cpsr_flg", CPSR_FLG},
410 {"spsr_flg", SPSR_FLG},
411
412 /* Valid <psrc>'s */
413 {"cpsr_c", CPSR_CTL},
414 {"cpsr_ctl", CPSR_CTL},
415 {"spsr_c", SPSR_CTL},
416 {"spsr_ctl", SPSR_CTL}
417 };
418
419 /* Functions called by parser. */
420 /* ARM instructions */
421 static void do_arit PARAMS ((char *, unsigned long));
422 static void do_cmp PARAMS ((char *, unsigned long));
423 static void do_mov PARAMS ((char *, unsigned long));
424 static void do_ldst PARAMS ((char *, unsigned long));
425 static void do_ldmstm PARAMS ((char *, unsigned long));
426 static void do_branch PARAMS ((char *, unsigned long));
427 static void do_swi PARAMS ((char *, unsigned long));
428 /* Pseudo Op codes */
429 static void do_adr PARAMS ((char *, unsigned long));
430 static void do_adrl PARAMS ((char *, unsigned long));
431 static void do_nop PARAMS ((char *, unsigned long));
432 /* ARM 2 */
433 static void do_mul PARAMS ((char *, unsigned long));
434 static void do_mla PARAMS ((char *, unsigned long));
435 /* ARM 3 */
436 static void do_swap PARAMS ((char *, unsigned long));
437 /* ARM 6 */
438 static void do_msr PARAMS ((char *, unsigned long));
439 static void do_mrs PARAMS ((char *, unsigned long));
440 /* ARM 7M */
441 static void do_mull PARAMS ((char *, unsigned long));
442 /* ARM THUMB */
443 static void do_bx PARAMS ((char *, unsigned long));
444
445
446 /* Coprocessor Instructions */
447 static void do_cdp PARAMS ((char *, unsigned long));
448 static void do_lstc PARAMS ((char *, unsigned long));
449 static void do_co_reg PARAMS ((char *, unsigned long));
450 static void do_fp_ctrl PARAMS ((char *, unsigned long));
451 static void do_fp_ldst PARAMS ((char *, unsigned long));
452 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
453 static void do_fp_dyadic PARAMS ((char *, unsigned long));
454 static void do_fp_monadic PARAMS ((char *, unsigned long));
455 static void do_fp_cmp PARAMS ((char *, unsigned long));
456 static void do_fp_from_reg PARAMS ((char *, unsigned long));
457 static void do_fp_to_reg PARAMS ((char *, unsigned long));
458
459 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
460 static int arm_reg_parse PARAMS ((char **));
461 static int arm_psr_parse PARAMS ((char **));
462 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
463 static int add_to_lit_pool PARAMS ((void));
464 static unsigned validate_immediate PARAMS ((unsigned));
465 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
466 static int validate_offset_imm PARAMS ((unsigned int, int));
467 static void opcode_select PARAMS ((int));
468 static void end_of_line PARAMS ((char *));
469 static int reg_required_here PARAMS ((char **, int));
470 static int psr_required_here PARAMS ((char **, int, int));
471 static int co_proc_number PARAMS ((char **));
472 static int cp_opc_expr PARAMS ((char **, int, int));
473 static int cp_reg_required_here PARAMS ((char **, int));
474 static int fp_reg_required_here PARAMS ((char **, int));
475 static int cp_address_offset PARAMS ((char **));
476 static int cp_address_required_here PARAMS ((char **));
477 static int my_get_float_expression PARAMS ((char **));
478 static int skip_past_comma PARAMS ((char **));
479 static int walk_no_bignums PARAMS ((symbolS *));
480 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
481 static int data_op2 PARAMS ((char **));
482 static int fp_op2 PARAMS ((char **));
483 static long reg_list PARAMS ((char **));
484 static void thumb_load_store PARAMS ((char *, int, int));
485 static int decode_shift PARAMS ((char **, int));
486 static int ldst_extend PARAMS ((char **, int));
487 static void thumb_add_sub PARAMS ((char *, int));
488 static void insert_reg PARAMS ((int));
489 static void thumb_shift PARAMS ((char *, int));
490 static void thumb_mov_compare PARAMS ((char *, int));
491 static void set_constant_flonums PARAMS ((void));
492 static valueT md_chars_to_number PARAMS ((char *, int));
493 static void insert_reg_alias PARAMS ((char *, int));
494 static void output_inst PARAMS ((void));
495 #ifdef OBJ_ELF
496 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
497 #endif
498
499 /* ARM instructions take 4bytes in the object file, Thumb instructions
500 take 2: */
501 #define INSN_SIZE 4
502
503 /* LONGEST_INST is the longest basic instruction name without conditions or
504 flags. ARM7M has 4 of length 5. */
505
506 #define LONGEST_INST 5
507
508
509 struct asm_opcode
510 {
511 CONST char * template; /* Basic string to match */
512 unsigned long value; /* Basic instruction code */
513
514 /* Compulsory suffix that must follow conds. If "", then the
515 instruction is not conditional and must have no suffix. */
516 CONST char * comp_suffix;
517
518 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
519 unsigned long variants; /* Which CPU variants this exists for */
520 /* Function to call to parse args */
521 void (* parms) PARAMS ((char *, unsigned long));
522 };
523
524 static CONST struct asm_opcode insns[] =
525 {
526 /* ARM Instructions */
527 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
528 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
529 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
530 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
531 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
532 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
533 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
534 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
535 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
536 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
537 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
538 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
539 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
540 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
541 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
542 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
543 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
544 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
545 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
546 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
547 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
548 #ifdef TE_WINCE
549 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
550 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
551 #else
552 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
553 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
554 #endif
555
556 /* Pseudo ops */
557 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
558 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
559 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
560
561 /* ARM 2 multiplies */
562 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
563 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
564
565 /* ARM 3 - swp instructions */
566 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
567
568 /* ARM 6 Coprocessor instructions */
569 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
570 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
571 /* ScottB: our code uses 0x0128f000 for msr.
572 NickC: but this is wrong because the bits 16 and 19 are handled
573 by the PSR_xxx defines above. */
574
575 /* ARM 7M long multiplies - need signed/unsigned flags! */
576 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
577 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
578 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
579 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
580
581 /* ARM THUMB interworking */
582 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
583
584 /* Floating point instructions */
585 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
586 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
587 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
588 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
589 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
590 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
591 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
592 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
593 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
594 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
595 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
596 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
597 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
598 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
599 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
600 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
607 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
608 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
609 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
610 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
611 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
612 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
613 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
614 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
615 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
616 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
620 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
621 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
622 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
623 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
624 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
625 be an optional suffix, but part of the instruction. To be compatible,
626 we accept either. */
627 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
628 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
629 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
630 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
631
632 /* Generic copressor instructions. */
633 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
634 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
635 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
636 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
637 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
638 };
639
640 /* Defines for various bits that we will want to toggle. */
641 #define INST_IMMEDIATE 0x02000000
642 #define OFFSET_REG 0x02000000
643 #define HWOFFSET_IMM 0x00400000
644 #define SHIFT_BY_REG 0x00000010
645 #define PRE_INDEX 0x01000000
646 #define INDEX_UP 0x00800000
647 #define WRITE_BACK 0x00200000
648 #define LDM_TYPE_2_OR_3 0x00400000
649
650 #define LITERAL_MASK 0xf000f000
651 #define COND_MASK 0xf0000000
652 #define OPCODE_MASK 0xfe1fffff
653 #define DATA_OP_SHIFT 21
654
655 /* Codes to distinguish the arithmetic instructions. */
656 #define OPCODE_AND 0
657 #define OPCODE_EOR 1
658 #define OPCODE_SUB 2
659 #define OPCODE_RSB 3
660 #define OPCODE_ADD 4
661 #define OPCODE_ADC 5
662 #define OPCODE_SBC 6
663 #define OPCODE_RSC 7
664 #define OPCODE_TST 8
665 #define OPCODE_TEQ 9
666 #define OPCODE_CMP 10
667 #define OPCODE_CMN 11
668 #define OPCODE_ORR 12
669 #define OPCODE_MOV 13
670 #define OPCODE_BIC 14
671 #define OPCODE_MVN 15
672
673 static void do_t_nop PARAMS ((char *));
674 static void do_t_arit PARAMS ((char *));
675 static void do_t_add PARAMS ((char *));
676 static void do_t_asr PARAMS ((char *));
677 static void do_t_branch9 PARAMS ((char *));
678 static void do_t_branch12 PARAMS ((char *));
679 static void do_t_branch23 PARAMS ((char *));
680 static void do_t_bx PARAMS ((char *));
681 static void do_t_compare PARAMS ((char *));
682 static void do_t_ldmstm PARAMS ((char *));
683 static void do_t_ldr PARAMS ((char *));
684 static void do_t_ldrb PARAMS ((char *));
685 static void do_t_ldrh PARAMS ((char *));
686 static void do_t_lds PARAMS ((char *));
687 static void do_t_lsl PARAMS ((char *));
688 static void do_t_lsr PARAMS ((char *));
689 static void do_t_mov PARAMS ((char *));
690 static void do_t_push_pop PARAMS ((char *));
691 static void do_t_str PARAMS ((char *));
692 static void do_t_strb PARAMS ((char *));
693 static void do_t_strh PARAMS ((char *));
694 static void do_t_sub PARAMS ((char *));
695 static void do_t_swi PARAMS ((char *));
696 static void do_t_adr PARAMS ((char *));
697
698 #define T_OPCODE_MUL 0x4340
699 #define T_OPCODE_TST 0x4200
700 #define T_OPCODE_CMN 0x42c0
701 #define T_OPCODE_NEG 0x4240
702 #define T_OPCODE_MVN 0x43c0
703
704 #define T_OPCODE_ADD_R3 0x1800
705 #define T_OPCODE_SUB_R3 0x1a00
706 #define T_OPCODE_ADD_HI 0x4400
707 #define T_OPCODE_ADD_ST 0xb000
708 #define T_OPCODE_SUB_ST 0xb080
709 #define T_OPCODE_ADD_SP 0xa800
710 #define T_OPCODE_ADD_PC 0xa000
711 #define T_OPCODE_ADD_I8 0x3000
712 #define T_OPCODE_SUB_I8 0x3800
713 #define T_OPCODE_ADD_I3 0x1c00
714 #define T_OPCODE_SUB_I3 0x1e00
715
716 #define T_OPCODE_ASR_R 0x4100
717 #define T_OPCODE_LSL_R 0x4080
718 #define T_OPCODE_LSR_R 0x40c0
719 #define T_OPCODE_ASR_I 0x1000
720 #define T_OPCODE_LSL_I 0x0000
721 #define T_OPCODE_LSR_I 0x0800
722
723 #define T_OPCODE_MOV_I8 0x2000
724 #define T_OPCODE_CMP_I8 0x2800
725 #define T_OPCODE_CMP_LR 0x4280
726 #define T_OPCODE_MOV_HR 0x4600
727 #define T_OPCODE_CMP_HR 0x4500
728
729 #define T_OPCODE_LDR_PC 0x4800
730 #define T_OPCODE_LDR_SP 0x9800
731 #define T_OPCODE_STR_SP 0x9000
732 #define T_OPCODE_LDR_IW 0x6800
733 #define T_OPCODE_STR_IW 0x6000
734 #define T_OPCODE_LDR_IH 0x8800
735 #define T_OPCODE_STR_IH 0x8000
736 #define T_OPCODE_LDR_IB 0x7800
737 #define T_OPCODE_STR_IB 0x7000
738 #define T_OPCODE_LDR_RW 0x5800
739 #define T_OPCODE_STR_RW 0x5000
740 #define T_OPCODE_LDR_RH 0x5a00
741 #define T_OPCODE_STR_RH 0x5200
742 #define T_OPCODE_LDR_RB 0x5c00
743 #define T_OPCODE_STR_RB 0x5400
744
745 #define T_OPCODE_PUSH 0xb400
746 #define T_OPCODE_POP 0xbc00
747
748 #define T_OPCODE_BRANCH 0xe7fe
749
750 static int thumb_reg PARAMS ((char ** str, int hi_lo));
751
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_REG_LO 0x1
754 #define THUMB_REG_HI 0x2
755 #define THUMB_REG_ANY 0x3
756
757 #define THUMB_H1 0x0080
758 #define THUMB_H2 0x0040
759
760 #define THUMB_ASR 0
761 #define THUMB_LSL 1
762 #define THUMB_LSR 2
763
764 #define THUMB_MOVE 0
765 #define THUMB_COMPARE 1
766
767 #define THUMB_LOAD 0
768 #define THUMB_STORE 1
769
770 #define THUMB_PP_PC_LR 0x0100
771
772 /* These three are used for immediate shifts, do not alter. */
773 #define THUMB_WORD 2
774 #define THUMB_HALFWORD 1
775 #define THUMB_BYTE 0
776
777 struct thumb_opcode
778 {
779 CONST char * template; /* Basic string to match */
780 unsigned long value; /* Basic instruction code */
781 int size;
782 unsigned long variants; /* Which CPU variants this exists for */
783 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
784 };
785
786 static CONST struct thumb_opcode tinsns[] =
787 {
788 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
789 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
790 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
791 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
792 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
793 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
794 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
795 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
796 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
797 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
798 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
799 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
800 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
801 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
802 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
803 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
804 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
805 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
806 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
807 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
808 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
809 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
810 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
811 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
812 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
813 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
814 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
815 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
816 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
817 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
818 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
819 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
820 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
821 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
822 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
823 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
824 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
825 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
826 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
827 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
828 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
829 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
830 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
831 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
832 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
833 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
834 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
835 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
836 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
837 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
838 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
839 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
840 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
841 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
842 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
843 /* Pseudo ops: */
844 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
845 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
846 };
847
848 struct reg_entry
849 {
850 CONST char * name;
851 int number;
852 };
853
854 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
855 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
856 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
857
858 #define REG_PC 15
859 #define REG_LR 14
860 #define REG_SP 13
861
862 /* These are the standard names. Users can add aliases with .req */
863 static CONST struct reg_entry reg_table[] =
864 {
865 /* Processor Register Numbers. */
866 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
867 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
868 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
869 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
870 /* APCS conventions. */
871 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
872 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
873 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
874 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
875 /* ATPCS additions to APCS conventions. */
876 {"wr", 7}, {"v8", 11},
877 /* FP Registers. */
878 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
879 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
880 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
881 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
882 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
883 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
884 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
885 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
886 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
887 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
888 /* ATPCS additions to float register names. */
889 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
890 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
891 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
892 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
893 /* FIXME: At some point we need to add VFP register names. */
894 /* Array terminator. */
895 {NULL, 0}
896 };
897
898 #define BAD_ARGS _("Bad arguments to instruction")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_FLAGS _("Instruction should not have flags")
901 #define BAD_COND _("Instruction is not conditional")
902
903 static struct hash_control * arm_ops_hsh = NULL;
904 static struct hash_control * arm_tops_hsh = NULL;
905 static struct hash_control * arm_cond_hsh = NULL;
906 static struct hash_control * arm_shift_hsh = NULL;
907 static struct hash_control * arm_reg_hsh = NULL;
908 static struct hash_control * arm_psr_hsh = NULL;
909
910 /* This table describes all the machine specific pseudo-ops the assembler
911 has to support. The fields are:
912 pseudo-op name without dot
913 function to call to execute this pseudo-op
914 Integer arg to pass to the function. */
915
916 static void s_req PARAMS ((int));
917 static void s_align PARAMS ((int));
918 static void s_bss PARAMS ((int));
919 static void s_even PARAMS ((int));
920 static void s_ltorg PARAMS ((int));
921 static void s_arm PARAMS ((int));
922 static void s_thumb PARAMS ((int));
923 static void s_code PARAMS ((int));
924 static void s_force_thumb PARAMS ((int));
925 static void s_thumb_func PARAMS ((int));
926 static void s_thumb_set PARAMS ((int));
927 static void arm_s_text PARAMS ((int));
928 static void arm_s_data PARAMS ((int));
929 #ifdef OBJ_ELF
930 static void arm_s_section PARAMS ((int));
931 static void s_arm_elf_cons PARAMS ((int));
932 #endif
933
934 static int my_get_expression PARAMS ((expressionS *, char **));
935
936 CONST pseudo_typeS md_pseudo_table[] =
937 {
938 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
939 { "bss", s_bss, 0 },
940 { "align", s_align, 0 },
941 { "arm", s_arm, 0 },
942 { "thumb", s_thumb, 0 },
943 { "code", s_code, 0 },
944 { "force_thumb", s_force_thumb, 0 },
945 { "thumb_func", s_thumb_func, 0 },
946 { "thumb_set", s_thumb_set, 0 },
947 { "even", s_even, 0 },
948 { "ltorg", s_ltorg, 0 },
949 { "pool", s_ltorg, 0 },
950 /* Allow for the effect of section changes. */
951 { "text", arm_s_text, 0 },
952 { "data", arm_s_data, 0 },
953 #ifdef OBJ_ELF
954 { "section", arm_s_section, 0 },
955 { "section.s", arm_s_section, 0 },
956 { "sect", arm_s_section, 0 },
957 { "sect.s", arm_s_section, 0 },
958 { "word", s_arm_elf_cons, 4 },
959 { "long", s_arm_elf_cons, 4 },
960 #else
961 { "word", cons, 4},
962 #endif
963 { "extend", float_cons, 'x' },
964 { "ldouble", float_cons, 'x' },
965 { "packed", float_cons, 'p' },
966 { 0, 0, 0 }
967 };
968
969 /* Stuff needed to resolve the label ambiguity
970 As:
971 ...
972 label: <insn>
973 may differ from:
974 ...
975 label:
976 <insn>
977 */
978
979 symbolS * last_label_seen;
980 static int label_is_thumb_function_name = false;
981
982 /* Literal stuff */
983
984 #define MAX_LITERAL_POOL_SIZE 1024
985
986 typedef struct literalS
987 {
988 struct expressionS exp;
989 struct arm_it * inst;
990 } literalT;
991
992 literalT literals[MAX_LITERAL_POOL_SIZE];
993 int next_literal_pool_place = 0; /* Next free entry in the pool */
994 int lit_pool_num = 1; /* Next literal pool number */
995 symbolS * current_poolP = NULL;
996
997 static int
998 add_to_lit_pool ()
999 {
1000 int lit_count = 0;
1001
1002 if (current_poolP == NULL)
1003 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1004 (valueT) 0, &zero_address_frag);
1005
1006 /* Check if this literal value is already in the pool: */
1007 while (lit_count < next_literal_pool_place)
1008 {
1009 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1010 && inst.reloc.exp.X_op == O_constant
1011 && literals[lit_count].exp.X_add_number
1012 == inst.reloc.exp.X_add_number
1013 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1014 break;
1015 lit_count++;
1016 }
1017
1018 if (lit_count == next_literal_pool_place) /* new entry */
1019 {
1020 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1021 {
1022 inst.error = _("Literal Pool Overflow");
1023 return FAIL;
1024 }
1025
1026 literals[next_literal_pool_place].exp = inst.reloc.exp;
1027 lit_count = next_literal_pool_place++;
1028 }
1029
1030 inst.reloc.exp.X_op = O_symbol;
1031 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1032 inst.reloc.exp.X_add_symbol = current_poolP;
1033
1034 return SUCCESS;
1035 }
1036
1037 /* Can't use symbol_new here, so have to create a symbol and then at
1038 a later date assign it a value. Thats what these functions do. */
1039 static void
1040 symbol_locate (symbolP, name, segment, valu, frag)
1041 symbolS * symbolP;
1042 CONST char * name; /* It is copied, the caller can modify */
1043 segT segment; /* Segment identifier (SEG_<something>) */
1044 valueT valu; /* Symbol value */
1045 fragS * frag; /* Associated fragment */
1046 {
1047 unsigned int name_length;
1048 char * preserved_copy_of_name;
1049
1050 name_length = strlen (name) + 1; /* +1 for \0 */
1051 obstack_grow (&notes, name, name_length);
1052 preserved_copy_of_name = obstack_finish (&notes);
1053 #ifdef STRIP_UNDERSCORE
1054 if (preserved_copy_of_name[0] == '_')
1055 preserved_copy_of_name++;
1056 #endif
1057
1058 #ifdef tc_canonicalize_symbol_name
1059 preserved_copy_of_name =
1060 tc_canonicalize_symbol_name (preserved_copy_of_name);
1061 #endif
1062
1063 S_SET_NAME (symbolP, preserved_copy_of_name);
1064
1065 S_SET_SEGMENT (symbolP, segment);
1066 S_SET_VALUE (symbolP, valu);
1067 symbol_clear_list_pointers(symbolP);
1068
1069 symbol_set_frag (symbolP, frag);
1070
1071 /* Link to end of symbol chain. */
1072 {
1073 extern int symbol_table_frozen;
1074 if (symbol_table_frozen)
1075 abort ();
1076 }
1077
1078 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1079
1080 obj_symbol_new_hook (symbolP);
1081
1082 #ifdef tc_symbol_new_hook
1083 tc_symbol_new_hook (symbolP);
1084 #endif
1085
1086 #ifdef DEBUG_SYMS
1087 verify_symbol_chain (symbol_rootP, symbol_lastP);
1088 #endif /* DEBUG_SYMS */
1089 }
1090
1091 /* Check that an immediate is valid, and if so,
1092 convert it to the right format. */
1093 static unsigned int
1094 validate_immediate (val)
1095 unsigned int val;
1096 {
1097 unsigned int a;
1098 unsigned int i;
1099
1100 #define rotate_left(v, n) (v << n | v >> (32 - n))
1101
1102 for (i = 0; i < 32; i += 2)
1103 if ((a = rotate_left (val, i)) <= 0xff)
1104 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1105
1106 return FAIL;
1107 }
1108
1109 /* Check to see if an immediate can be computed as two seperate immediate
1110 values, added together. We already know that this value cannot be
1111 computed by just one ARM instruction. */
1112 static unsigned int
1113 validate_immediate_twopart (val, highpart)
1114 unsigned int val;
1115 unsigned int * highpart;
1116 {
1117 unsigned int a;
1118 unsigned int i;
1119
1120 for (i = 0; i < 32; i += 2)
1121 if (((a = rotate_left (val, i)) & 0xff) != 0)
1122 {
1123 if (a & 0xff00)
1124 {
1125 if (a & ~ 0xffff)
1126 continue;
1127 * highpart = (a >> 8) | ((i + 24) << 7);
1128 }
1129 else if (a & 0xff0000)
1130 {
1131 if (a & 0xff000000)
1132 continue;
1133
1134 * highpart = (a >> 16) | ((i + 16) << 7);
1135 }
1136 else
1137 {
1138 assert (a & 0xff000000);
1139
1140 * highpart = (a >> 24) | ((i + 8) << 7);
1141 }
1142
1143 return (a & 0xff) | (i << 7);
1144 }
1145
1146 return FAIL;
1147 }
1148
1149 static int
1150 validate_offset_imm (val, hwse)
1151 unsigned int val;
1152 int hwse;
1153 {
1154 if ((hwse && val > 255) || val > 4095)
1155 return FAIL;
1156 return val;
1157 }
1158
1159
1160 static void
1161 s_req (a)
1162 int a ATTRIBUTE_UNUSED;
1163 {
1164 as_bad (_("Invalid syntax for .req directive."));
1165 }
1166
1167 static void
1168 s_bss (ignore)
1169 int ignore ATTRIBUTE_UNUSED;
1170 {
1171 /* We don't support putting frags in the BSS segment, we fake it by
1172 marking in_bss, then looking at s_skip for clues?.. */
1173 subseg_set (bss_section, 0);
1174 demand_empty_rest_of_line ();
1175 }
1176
1177 static void
1178 s_even (ignore)
1179 int ignore ATTRIBUTE_UNUSED;
1180 {
1181 if (!need_pass_2) /* Never make frag if expect extra pass. */
1182 frag_align (1, 0, 0);
1183
1184 record_alignment (now_seg, 1);
1185
1186 demand_empty_rest_of_line ();
1187 }
1188
1189 static void
1190 s_ltorg (ignored)
1191 int ignored ATTRIBUTE_UNUSED;
1192 {
1193 int lit_count = 0;
1194 char sym_name[20];
1195
1196 if (current_poolP == NULL)
1197 return;
1198
1199 /* Align pool as you have word accesses */
1200 /* Only make a frag if we have to ... */
1201 if (!need_pass_2)
1202 frag_align (2, 0, 0);
1203
1204 record_alignment (now_seg, 2);
1205
1206 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1207
1208 symbol_locate (current_poolP, sym_name, now_seg,
1209 (valueT) frag_now_fix (), frag_now);
1210 symbol_table_insert (current_poolP);
1211
1212 ARM_SET_THUMB (current_poolP, thumb_mode);
1213
1214 #if defined OBJ_COFF || defined OBJ_ELF
1215 ARM_SET_INTERWORK (current_poolP, support_interwork);
1216 #endif
1217
1218 while (lit_count < next_literal_pool_place)
1219 /* First output the expression in the instruction to the pool. */
1220 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1221
1222 next_literal_pool_place = 0;
1223 current_poolP = NULL;
1224 }
1225
1226 static void
1227 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1228 int unused ATTRIBUTE_UNUSED;
1229 {
1230 register int temp;
1231 register long temp_fill;
1232 long max_alignment = 15;
1233
1234 temp = get_absolute_expression ();
1235 if (temp > max_alignment)
1236 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1237 else if (temp < 0)
1238 {
1239 as_bad (_("Alignment negative. 0 assumed."));
1240 temp = 0;
1241 }
1242
1243 if (*input_line_pointer == ',')
1244 {
1245 input_line_pointer++;
1246 temp_fill = get_absolute_expression ();
1247 }
1248 else
1249 temp_fill = 0;
1250
1251 if (!temp)
1252 temp = 2;
1253
1254 /* Only make a frag if we HAVE to. . . */
1255 if (temp && !need_pass_2)
1256 frag_align (temp, (int) temp_fill, 0);
1257 demand_empty_rest_of_line ();
1258
1259 record_alignment (now_seg, temp);
1260 }
1261
1262 static void
1263 s_force_thumb (ignore)
1264 int ignore ATTRIBUTE_UNUSED;
1265 {
1266 /* If we are not already in thumb mode go into it, EVEN if
1267 the target processor does not support thumb instructions.
1268 This is used by gcc/config/arm/lib1funcs.asm for example
1269 to compile interworking support functions even if the
1270 target processor should not support interworking. */
1271
1272 if (! thumb_mode)
1273 {
1274 thumb_mode = 2;
1275
1276 record_alignment (now_seg, 1);
1277 }
1278
1279 demand_empty_rest_of_line ();
1280 }
1281
1282 static void
1283 s_thumb_func (ignore)
1284 int ignore ATTRIBUTE_UNUSED;
1285 {
1286 /* The following label is the name/address of the start of a Thumb function.
1287 We need to know this for the interworking support. */
1288
1289 label_is_thumb_function_name = true;
1290
1291 demand_empty_rest_of_line ();
1292 }
1293
1294 /* Perform a .set directive, but also mark the alias as
1295 being a thumb function. */
1296
1297 static void
1298 s_thumb_set (equiv)
1299 int equiv;
1300 {
1301 /* XXX the following is a duplicate of the code for s_set() in read.c
1302 We cannot just call that code as we need to get at the symbol that
1303 is created. */
1304 register char * name;
1305 register char delim;
1306 register char * end_name;
1307 register symbolS * symbolP;
1308
1309 /*
1310 * Especial apologies for the random logic:
1311 * this just grew, and could be parsed much more simply!
1312 * Dean in haste.
1313 */
1314 name = input_line_pointer;
1315 delim = get_symbol_end ();
1316 end_name = input_line_pointer;
1317 *end_name = delim;
1318
1319 SKIP_WHITESPACE ();
1320
1321 if (*input_line_pointer != ',')
1322 {
1323 *end_name = 0;
1324 as_bad (_("Expected comma after name \"%s\""), name);
1325 *end_name = delim;
1326 ignore_rest_of_line ();
1327 return;
1328 }
1329
1330 input_line_pointer++;
1331 *end_name = 0;
1332
1333 if (name[0] == '.' && name[1] == '\0')
1334 {
1335 /* XXX - this should not happen to .thumb_set */
1336 abort ();
1337 }
1338
1339 if ((symbolP = symbol_find (name)) == NULL
1340 && (symbolP = md_undefined_symbol (name)) == NULL)
1341 {
1342 #ifndef NO_LISTING
1343 /* When doing symbol listings, play games with dummy fragments living
1344 outside the normal fragment chain to record the file and line info
1345 for this symbol. */
1346 if (listing & LISTING_SYMBOLS)
1347 {
1348 extern struct list_info_struct * listing_tail;
1349 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1350 memset (dummy_frag, 0, sizeof(fragS));
1351 dummy_frag->fr_type = rs_fill;
1352 dummy_frag->line = listing_tail;
1353 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1354 dummy_frag->fr_symbol = symbolP;
1355 }
1356 else
1357 #endif
1358 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1359
1360 #ifdef OBJ_COFF
1361 /* "set" symbols are local unless otherwise specified. */
1362 SF_SET_LOCAL (symbolP);
1363 #endif /* OBJ_COFF */
1364 } /* make a new symbol */
1365
1366 symbol_table_insert (symbolP);
1367
1368 * end_name = delim;
1369
1370 if (equiv
1371 && S_IS_DEFINED (symbolP)
1372 && S_GET_SEGMENT (symbolP) != reg_section)
1373 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1374
1375 pseudo_set (symbolP);
1376
1377 demand_empty_rest_of_line ();
1378
1379 /* XXX Now we come to the Thumb specific bit of code. */
1380
1381 THUMB_SET_FUNC (symbolP, 1);
1382 ARM_SET_THUMB (symbolP, 1);
1383 #if defined OBJ_ELF || defined OBJ_COFF
1384 ARM_SET_INTERWORK (symbolP, support_interwork);
1385 #endif
1386 }
1387
1388 /* If we change section we must dump the literal pool first. */
1389 static void
1390 arm_s_text (ignore)
1391 int ignore;
1392 {
1393 if (now_seg != text_section)
1394 s_ltorg (0);
1395
1396 #ifdef OBJ_ELF
1397 obj_elf_text (ignore);
1398 #else
1399 s_text (ignore);
1400 #endif
1401 }
1402
1403 static void
1404 arm_s_data (ignore)
1405 int ignore;
1406 {
1407 if (flag_readonly_data_in_text)
1408 {
1409 if (now_seg != text_section)
1410 s_ltorg (0);
1411 }
1412 else if (now_seg != data_section)
1413 s_ltorg (0);
1414
1415 #ifdef OBJ_ELF
1416 obj_elf_data (ignore);
1417 #else
1418 s_data (ignore);
1419 #endif
1420 }
1421
1422 #ifdef OBJ_ELF
1423 static void
1424 arm_s_section (ignore)
1425 int ignore;
1426 {
1427 s_ltorg (0);
1428
1429 obj_elf_section (ignore);
1430 }
1431 #endif
1432
1433 static void
1434 opcode_select (width)
1435 int width;
1436 {
1437 switch (width)
1438 {
1439 case 16:
1440 if (! thumb_mode)
1441 {
1442 if (! (cpu_variant & ARM_THUMB))
1443 as_bad (_("selected processor does not support THUMB opcodes"));
1444 thumb_mode = 1;
1445 /* No need to force the alignment, since we will have been
1446 coming from ARM mode, which is word-aligned. */
1447 record_alignment (now_seg, 1);
1448 }
1449 break;
1450
1451 case 32:
1452 if (thumb_mode)
1453 {
1454 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1455 as_bad (_("selected processor does not support ARM opcodes"));
1456 thumb_mode = 0;
1457 if (!need_pass_2)
1458 frag_align (2, 0, 0);
1459 record_alignment (now_seg, 1);
1460 }
1461 break;
1462
1463 default:
1464 as_bad (_("invalid instruction size selected (%d)"), width);
1465 }
1466 }
1467
1468 static void
1469 s_arm (ignore)
1470 int ignore ATTRIBUTE_UNUSED;
1471 {
1472 opcode_select (32);
1473 demand_empty_rest_of_line ();
1474 }
1475
1476 static void
1477 s_thumb (ignore)
1478 int ignore ATTRIBUTE_UNUSED;
1479 {
1480 opcode_select (16);
1481 demand_empty_rest_of_line ();
1482 }
1483
1484 static void
1485 s_code (unused)
1486 int unused ATTRIBUTE_UNUSED;
1487 {
1488 register int temp;
1489
1490 temp = get_absolute_expression ();
1491 switch (temp)
1492 {
1493 case 16:
1494 case 32:
1495 opcode_select (temp);
1496 break;
1497
1498 default:
1499 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1500 }
1501 }
1502
1503 static void
1504 end_of_line (str)
1505 char * str;
1506 {
1507 skip_whitespace (str);
1508
1509 if (* str != '\0')
1510 inst.error = _("Garbage following instruction");
1511 }
1512
1513 static int
1514 skip_past_comma (str)
1515 char ** str;
1516 {
1517 char *p = *str, c;
1518 int comma = 0;
1519
1520 while ((c = *p) == ' ' || c == ',')
1521 {
1522 p++;
1523 if (c == ',' && comma++)
1524 return FAIL;
1525 }
1526
1527 if (c == '\0')
1528 return FAIL;
1529
1530 *str = p;
1531 return comma ? SUCCESS : FAIL;
1532 }
1533
1534 /* A standard register must be given at this point.
1535 Shift is the place to put it in inst.instruction.
1536 Restores input start point on err.
1537 Returns the reg#, or FAIL. */
1538 static int
1539 reg_required_here (str, shift)
1540 char ** str;
1541 int shift;
1542 {
1543 static char buff [128]; /* XXX */
1544 int reg;
1545 char * start = *str;
1546
1547 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1548 {
1549 if (shift >= 0)
1550 inst.instruction |= reg << shift;
1551 return reg;
1552 }
1553
1554 /* Restore the start point, we may have got a reg of the wrong class. */
1555 *str = start;
1556
1557 /* In the few cases where we might be able to accept something else
1558 this error can be overridden. */
1559 sprintf (buff, _("Register expected, not '%.100s'"), start);
1560 inst.error = buff;
1561
1562 return FAIL;
1563 }
1564
1565 static int
1566 psr_required_here (str, cpsr, spsr)
1567 char ** str;
1568 int cpsr;
1569 int spsr;
1570 {
1571 int psr;
1572 char * start = *str;
1573 psr = arm_psr_parse (str);
1574
1575 if (psr == cpsr || psr == spsr)
1576 {
1577 if (psr == spsr)
1578 inst.instruction |= 1 << 22;
1579
1580 return SUCCESS;
1581 }
1582
1583 /* In the few cases where we might be able to accept something else
1584 this error can be overridden. */
1585 inst.error = _("<psr(f)> expected");
1586
1587 /* Restore the start point. */
1588 *str = start;
1589 return FAIL;
1590 }
1591
1592 static int
1593 co_proc_number (str)
1594 char ** str;
1595 {
1596 int processor, pchar;
1597
1598 skip_whitespace (* str);
1599
1600 /* The data sheet seems to imply that just a number on its own is valid
1601 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1602 accept either. */
1603 if (**str == 'p' || **str == 'P')
1604 (*str)++;
1605
1606 pchar = *(*str)++;
1607 if (pchar >= '0' && pchar <= '9')
1608 {
1609 processor = pchar - '0';
1610 if (**str >= '0' && **str <= '9')
1611 {
1612 processor = processor * 10 + *(*str)++ - '0';
1613 if (processor > 15)
1614 {
1615 inst.error = _("Illegal co-processor number");
1616 return FAIL;
1617 }
1618 }
1619 }
1620 else
1621 {
1622 inst.error = _("Bad or missing co-processor number");
1623 return FAIL;
1624 }
1625
1626 inst.instruction |= processor << 8;
1627 return SUCCESS;
1628 }
1629
1630 static int
1631 cp_opc_expr (str, where, length)
1632 char ** str;
1633 int where;
1634 int length;
1635 {
1636 expressionS expr;
1637
1638 skip_whitespace (* str);
1639
1640 memset (&expr, '\0', sizeof (expr));
1641
1642 if (my_get_expression (&expr, str))
1643 return FAIL;
1644 if (expr.X_op != O_constant)
1645 {
1646 inst.error = _("bad or missing expression");
1647 return FAIL;
1648 }
1649
1650 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1651 {
1652 inst.error = _("immediate co-processor expression too large");
1653 return FAIL;
1654 }
1655
1656 inst.instruction |= expr.X_add_number << where;
1657 return SUCCESS;
1658 }
1659
1660 static int
1661 cp_reg_required_here (str, where)
1662 char ** str;
1663 int where;
1664 {
1665 int reg;
1666 char * start = *str;
1667
1668 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1669 {
1670 reg &= 15;
1671 inst.instruction |= reg << where;
1672 return reg;
1673 }
1674
1675 /* In the few cases where we might be able to accept something else
1676 this error can be overridden. */
1677 inst.error = _("Co-processor register expected");
1678
1679 /* Restore the start point. */
1680 *str = start;
1681 return FAIL;
1682 }
1683
1684 static int
1685 fp_reg_required_here (str, where)
1686 char ** str;
1687 int where;
1688 {
1689 int reg;
1690 char * start = *str;
1691
1692 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1693 {
1694 reg &= 7;
1695 inst.instruction |= reg << where;
1696 return reg;
1697 }
1698
1699 /* In the few cases where we might be able to accept something else
1700 this error can be overridden. */
1701 inst.error = _("Floating point register expected");
1702
1703 /* Restore the start point. */
1704 *str = start;
1705 return FAIL;
1706 }
1707
1708 static int
1709 cp_address_offset (str)
1710 char ** str;
1711 {
1712 int offset;
1713
1714 skip_whitespace (* str);
1715
1716 if (! is_immediate_prefix (**str))
1717 {
1718 inst.error = _("immediate expression expected");
1719 return FAIL;
1720 }
1721
1722 (*str)++;
1723
1724 if (my_get_expression (& inst.reloc.exp, str))
1725 return FAIL;
1726
1727 if (inst.reloc.exp.X_op == O_constant)
1728 {
1729 offset = inst.reloc.exp.X_add_number;
1730
1731 if (offset & 3)
1732 {
1733 inst.error = _("co-processor address must be word aligned");
1734 return FAIL;
1735 }
1736
1737 if (offset > 1023 || offset < -1023)
1738 {
1739 inst.error = _("offset too large");
1740 return FAIL;
1741 }
1742
1743 if (offset >= 0)
1744 inst.instruction |= INDEX_UP;
1745 else
1746 offset = -offset;
1747
1748 inst.instruction |= offset >> 2;
1749 }
1750 else
1751 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1752
1753 return SUCCESS;
1754 }
1755
1756 static int
1757 cp_address_required_here (str)
1758 char ** str;
1759 {
1760 char * p = * str;
1761 int pre_inc = 0;
1762 int write_back = 0;
1763
1764 if (*p == '[')
1765 {
1766 int reg;
1767
1768 p++;
1769 skip_whitespace (p);
1770
1771 if ((reg = reg_required_here (& p, 16)) == FAIL)
1772 return FAIL;
1773
1774 skip_whitespace (p);
1775
1776 if (*p == ']')
1777 {
1778 p++;
1779
1780 if (skip_past_comma (& p) == SUCCESS)
1781 {
1782 /* [Rn], #expr */
1783 write_back = WRITE_BACK;
1784
1785 if (reg == REG_PC)
1786 {
1787 inst.error = _("pc may not be used in post-increment");
1788 return FAIL;
1789 }
1790
1791 if (cp_address_offset (& p) == FAIL)
1792 return FAIL;
1793 }
1794 else
1795 pre_inc = PRE_INDEX | INDEX_UP;
1796 }
1797 else
1798 {
1799 /* '['Rn, #expr']'[!] */
1800
1801 if (skip_past_comma (& p) == FAIL)
1802 {
1803 inst.error = _("pre-indexed expression expected");
1804 return FAIL;
1805 }
1806
1807 pre_inc = PRE_INDEX;
1808
1809 if (cp_address_offset (& p) == FAIL)
1810 return FAIL;
1811
1812 skip_whitespace (p);
1813
1814 if (*p++ != ']')
1815 {
1816 inst.error = _("missing ]");
1817 return FAIL;
1818 }
1819
1820 skip_whitespace (p);
1821
1822 if (*p == '!')
1823 {
1824 if (reg == REG_PC)
1825 {
1826 inst.error = _("pc may not be used with write-back");
1827 return FAIL;
1828 }
1829
1830 p++;
1831 write_back = WRITE_BACK;
1832 }
1833 }
1834 }
1835 else
1836 {
1837 if (my_get_expression (&inst.reloc.exp, &p))
1838 return FAIL;
1839
1840 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1841 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1842 inst.reloc.pc_rel = 1;
1843 inst.instruction |= (REG_PC << 16);
1844 pre_inc = PRE_INDEX;
1845 }
1846
1847 inst.instruction |= write_back | pre_inc;
1848 *str = p;
1849 return SUCCESS;
1850 }
1851
1852 static void
1853 do_nop (str, flags)
1854 char * str;
1855 unsigned long flags;
1856 {
1857 /* Do nothing really. */
1858 inst.instruction |= flags; /* This is pointless. */
1859 end_of_line (str);
1860 return;
1861 }
1862
1863 static void
1864 do_mrs (str, flags)
1865 char *str;
1866 unsigned long flags;
1867 {
1868 /* Only one syntax. */
1869 skip_whitespace (str);
1870
1871 if (reg_required_here (&str, 12) == FAIL)
1872 {
1873 inst.error = BAD_ARGS;
1874 return;
1875 }
1876
1877 if (skip_past_comma (&str) == FAIL
1878 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1879 {
1880 inst.error = _("<psr> expected");
1881 return;
1882 }
1883
1884 inst.instruction |= flags;
1885 end_of_line (str);
1886 return;
1887 }
1888
1889 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1890 static void
1891 do_msr (str, flags)
1892 char * str;
1893 unsigned long flags;
1894 {
1895 int reg;
1896
1897 skip_whitespace (str);
1898
1899 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1900 {
1901 inst.instruction |= PSR_ALL;
1902
1903 /* Sytax should be "<psr>, Rm" */
1904 if (skip_past_comma (&str) == FAIL
1905 || (reg = reg_required_here (&str, 0)) == FAIL)
1906 {
1907 inst.error = BAD_ARGS;
1908 return;
1909 }
1910 }
1911 else
1912 {
1913 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1914 inst.instruction |= PSR_FLAGS;
1915 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1916 inst.instruction |= PSR_CONTROL;
1917 else
1918 {
1919 inst.error = BAD_ARGS;
1920 return;
1921 }
1922
1923 if (skip_past_comma (&str) == FAIL)
1924 {
1925 inst.error = BAD_ARGS;
1926 return;
1927 }
1928
1929 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1930
1931 if ((reg = reg_required_here (& str, 0)) != FAIL)
1932 ;
1933 /* Immediate expression. */
1934 else if (is_immediate_prefix (* str))
1935 {
1936 str ++;
1937 inst.error = NULL;
1938
1939 if (my_get_expression (& inst.reloc.exp, & str))
1940 {
1941 inst.error = _("Register or shift expression expected");
1942 return;
1943 }
1944
1945 if (inst.reloc.exp.X_add_symbol)
1946 {
1947 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1948 inst.reloc.pc_rel = 0;
1949 }
1950 else
1951 {
1952 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1953 if (value == (unsigned) FAIL)
1954 {
1955 inst.error = _("Invalid constant");
1956 return;
1957 }
1958
1959 inst.instruction |= value;
1960 }
1961
1962 flags |= INST_IMMEDIATE;
1963 }
1964 else
1965 {
1966 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1967 return;
1968 }
1969 }
1970
1971 inst.error = NULL;
1972 inst.instruction |= flags;
1973 end_of_line (str);
1974 return;
1975 }
1976
1977 /* Long Multiply Parser
1978 UMULL RdLo, RdHi, Rm, Rs
1979 SMULL RdLo, RdHi, Rm, Rs
1980 UMLAL RdLo, RdHi, Rm, Rs
1981 SMLAL RdLo, RdHi, Rm, Rs
1982 */
1983 static void
1984 do_mull (str, flags)
1985 char * str;
1986 unsigned long flags;
1987 {
1988 int rdlo, rdhi, rm, rs;
1989
1990 /* Only one format "rdlo, rdhi, rm, rs" */
1991 skip_whitespace (str);
1992
1993 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1994 {
1995 inst.error = BAD_ARGS;
1996 return;
1997 }
1998
1999 if (skip_past_comma (&str) == FAIL
2000 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2001 {
2002 inst.error = BAD_ARGS;
2003 return;
2004 }
2005
2006 if (skip_past_comma (&str) == FAIL
2007 || (rm = reg_required_here (&str, 0)) == FAIL)
2008 {
2009 inst.error = BAD_ARGS;
2010 return;
2011 }
2012
2013 /* rdhi, rdlo and rm must all be different */
2014 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2015 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2016
2017 if (skip_past_comma (&str) == FAIL
2018 || (rs = reg_required_here (&str, 8)) == FAIL)
2019 {
2020 inst.error = BAD_ARGS;
2021 return;
2022 }
2023
2024 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2025 {
2026 inst.error = BAD_PC;
2027 return;
2028 }
2029
2030 inst.instruction |= flags;
2031 end_of_line (str);
2032 return;
2033 }
2034
2035 static void
2036 do_mul (str, flags)
2037 char * str;
2038 unsigned long flags;
2039 {
2040 int rd, rm;
2041
2042 /* Only one format "rd, rm, rs" */
2043 skip_whitespace (str);
2044
2045 if ((rd = reg_required_here (&str, 16)) == FAIL)
2046 {
2047 inst.error = BAD_ARGS;
2048 return;
2049 }
2050
2051 if (rd == REG_PC)
2052 {
2053 inst.error = BAD_PC;
2054 return;
2055 }
2056
2057 if (skip_past_comma (&str) == FAIL
2058 || (rm = reg_required_here (&str, 0)) == FAIL)
2059 {
2060 inst.error = BAD_ARGS;
2061 return;
2062 }
2063
2064 if (rm == REG_PC)
2065 {
2066 inst.error = BAD_PC;
2067 return;
2068 }
2069
2070 if (rm == rd)
2071 as_tsktsk (_("rd and rm should be different in mul"));
2072
2073 if (skip_past_comma (&str) == FAIL
2074 || (rm = reg_required_here (&str, 8)) == FAIL)
2075 {
2076 inst.error = BAD_ARGS;
2077 return;
2078 }
2079
2080 if (rm == REG_PC)
2081 {
2082 inst.error = BAD_PC;
2083 return;
2084 }
2085
2086 inst.instruction |= flags;
2087 end_of_line (str);
2088 return;
2089 }
2090
2091 static void
2092 do_mla (str, flags)
2093 char * str;
2094 unsigned long flags;
2095 {
2096 int rd, rm;
2097
2098 /* Only one format "rd, rm, rs, rn" */
2099 skip_whitespace (str);
2100
2101 if ((rd = reg_required_here (&str, 16)) == FAIL)
2102 {
2103 inst.error = BAD_ARGS;
2104 return;
2105 }
2106
2107 if (rd == REG_PC)
2108 {
2109 inst.error = BAD_PC;
2110 return;
2111 }
2112
2113 if (skip_past_comma (&str) == FAIL
2114 || (rm = reg_required_here (&str, 0)) == FAIL)
2115 {
2116 inst.error = BAD_ARGS;
2117 return;
2118 }
2119
2120 if (rm == REG_PC)
2121 {
2122 inst.error = BAD_PC;
2123 return;
2124 }
2125
2126 if (rm == rd)
2127 as_tsktsk (_("rd and rm should be different in mla"));
2128
2129 if (skip_past_comma (&str) == FAIL
2130 || (rd = reg_required_here (&str, 8)) == FAIL
2131 || skip_past_comma (&str) == FAIL
2132 || (rm = reg_required_here (&str, 12)) == FAIL)
2133 {
2134 inst.error = BAD_ARGS;
2135 return;
2136 }
2137
2138 if (rd == REG_PC || rm == REG_PC)
2139 {
2140 inst.error = BAD_PC;
2141 return;
2142 }
2143
2144 inst.instruction |= flags;
2145 end_of_line (str);
2146 return;
2147 }
2148
2149 /* Returns the index into fp_values of a floating point number, or -1 if
2150 not in the table. */
2151 static int
2152 my_get_float_expression (str)
2153 char ** str;
2154 {
2155 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2156 char * save_in;
2157 expressionS exp;
2158 int i;
2159 int j;
2160
2161 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2162 /* Look for a raw floating point number */
2163 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2164 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
2165 {
2166 for (i = 0; i < NUM_FLOAT_VALS; i++)
2167 {
2168 for (j = 0; j < MAX_LITTLENUMS; j++)
2169 {
2170 if (words[j] != fp_values[i][j])
2171 break;
2172 }
2173
2174 if (j == MAX_LITTLENUMS)
2175 {
2176 *str = save_in;
2177 return i;
2178 }
2179 }
2180 }
2181
2182 /* Try and parse a more complex expression, this will probably fail
2183 unless the code uses a floating point prefix (eg "0f") */
2184 save_in = input_line_pointer;
2185 input_line_pointer = *str;
2186 if (expression (&exp) == absolute_section
2187 && exp.X_op == O_big
2188 && exp.X_add_number < 0)
2189 {
2190 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2191 Ditto for 15. */
2192 if (gen_to_words (words, 5, (long)15) == 0)
2193 {
2194 for (i = 0; i < NUM_FLOAT_VALS; i++)
2195 {
2196 for (j = 0; j < MAX_LITTLENUMS; j++)
2197 {
2198 if (words[j] != fp_values[i][j])
2199 break;
2200 }
2201
2202 if (j == MAX_LITTLENUMS)
2203 {
2204 *str = input_line_pointer;
2205 input_line_pointer = save_in;
2206 return i;
2207 }
2208 }
2209 }
2210 }
2211
2212 *str = input_line_pointer;
2213 input_line_pointer = save_in;
2214 return -1;
2215 }
2216
2217 /* Return true if anything in the expression is a bignum */
2218 static int
2219 walk_no_bignums (sp)
2220 symbolS * sp;
2221 {
2222 if (symbol_get_value_expression (sp)->X_op == O_big)
2223 return 1;
2224
2225 if (symbol_get_value_expression (sp)->X_add_symbol)
2226 {
2227 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2228 || (symbol_get_value_expression (sp)->X_op_symbol
2229 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2230 }
2231
2232 return 0;
2233 }
2234
2235 static int
2236 my_get_expression (ep, str)
2237 expressionS * ep;
2238 char ** str;
2239 {
2240 char * save_in;
2241 segT seg;
2242
2243 save_in = input_line_pointer;
2244 input_line_pointer = *str;
2245 seg = expression (ep);
2246
2247 #ifdef OBJ_AOUT
2248 if (seg != absolute_section
2249 && seg != text_section
2250 && seg != data_section
2251 && seg != bss_section
2252 && seg != undefined_section)
2253 {
2254 inst.error = _("bad_segment");
2255 *str = input_line_pointer;
2256 input_line_pointer = save_in;
2257 return 1;
2258 }
2259 #endif
2260
2261 /* Get rid of any bignums now, so that we don't generate an error for which
2262 we can't establish a line number later on. Big numbers are never valid
2263 in instructions, which is where this routine is always called. */
2264 if (ep->X_op == O_big
2265 || (ep->X_add_symbol
2266 && (walk_no_bignums (ep->X_add_symbol)
2267 || (ep->X_op_symbol
2268 && walk_no_bignums (ep->X_op_symbol)))))
2269 {
2270 inst.error = _("Invalid constant");
2271 *str = input_line_pointer;
2272 input_line_pointer = save_in;
2273 return 1;
2274 }
2275
2276 *str = input_line_pointer;
2277 input_line_pointer = save_in;
2278 return 0;
2279 }
2280
2281 /* unrestrict should be one if <shift> <register> is permitted for this
2282 instruction */
2283
2284 static int
2285 decode_shift (str, unrestrict)
2286 char ** str;
2287 int unrestrict;
2288 {
2289 struct asm_shift * shft;
2290 char * p;
2291 char c;
2292
2293 skip_whitespace (* str);
2294
2295 for (p = *str; isalpha (*p); p++)
2296 ;
2297
2298 if (p == *str)
2299 {
2300 inst.error = _("Shift expression expected");
2301 return FAIL;
2302 }
2303
2304 c = *p;
2305 *p = '\0';
2306 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2307 *p = c;
2308 if (shft)
2309 {
2310 if (!strncmp (*str, "rrx", 3)
2311 || !strncmp (*str, "RRX", 3))
2312 {
2313 *str = p;
2314 inst.instruction |= shft->value;
2315 return SUCCESS;
2316 }
2317
2318 skip_whitespace (p);
2319
2320 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2321 {
2322 inst.instruction |= shft->value | SHIFT_BY_REG;
2323 *str = p;
2324 return SUCCESS;
2325 }
2326 else if (is_immediate_prefix (* p))
2327 {
2328 inst.error = NULL;
2329 p++;
2330 if (my_get_expression (&inst.reloc.exp, &p))
2331 return FAIL;
2332
2333 /* Validate some simple #expressions */
2334 if (inst.reloc.exp.X_op == O_constant)
2335 {
2336 unsigned num = inst.reloc.exp.X_add_number;
2337
2338 /* Reject operations greater than 32, or lsl #32 */
2339 if (num > 32 || (num == 32 && shft->value == 0))
2340 {
2341 inst.error = _("Invalid immediate shift");
2342 return FAIL;
2343 }
2344
2345 /* Shifts of zero should be converted to lsl (which is zero)*/
2346 if (num == 0)
2347 {
2348 *str = p;
2349 return SUCCESS;
2350 }
2351
2352 /* Shifts of 32 are encoded as 0, for those shifts that
2353 support it. */
2354 if (num == 32)
2355 num = 0;
2356
2357 inst.instruction |= (num << 7) | shft->value;
2358 *str = p;
2359 return SUCCESS;
2360 }
2361
2362 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2363 inst.reloc.pc_rel = 0;
2364 inst.instruction |= shft->value;
2365 *str = p;
2366 return SUCCESS;
2367 }
2368 else
2369 {
2370 inst.error = unrestrict ? _("shift requires register or #expression")
2371 : _("shift requires #expression");
2372 *str = p;
2373 return FAIL;
2374 }
2375 }
2376
2377 inst.error = _("Shift expression expected");
2378 return FAIL;
2379 }
2380
2381 /* Do those data_ops which can take a negative immediate constant */
2382 /* by altering the instuction. A bit of a hack really */
2383 /* MOV <-> MVN
2384 AND <-> BIC
2385 ADC <-> SBC
2386 by inverting the second operand, and
2387 ADD <-> SUB
2388 CMP <-> CMN
2389 by negating the second operand.
2390 */
2391 static int
2392 negate_data_op (instruction, value)
2393 unsigned long * instruction;
2394 unsigned long value;
2395 {
2396 int op, new_inst;
2397 unsigned long negated, inverted;
2398
2399 negated = validate_immediate (-value);
2400 inverted = validate_immediate (~value);
2401
2402 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2403 switch (op)
2404 {
2405 /* First negates */
2406 case OPCODE_SUB: /* ADD <-> SUB */
2407 new_inst = OPCODE_ADD;
2408 value = negated;
2409 break;
2410
2411 case OPCODE_ADD:
2412 new_inst = OPCODE_SUB;
2413 value = negated;
2414 break;
2415
2416 case OPCODE_CMP: /* CMP <-> CMN */
2417 new_inst = OPCODE_CMN;
2418 value = negated;
2419 break;
2420
2421 case OPCODE_CMN:
2422 new_inst = OPCODE_CMP;
2423 value = negated;
2424 break;
2425
2426 /* Now Inverted ops */
2427 case OPCODE_MOV: /* MOV <-> MVN */
2428 new_inst = OPCODE_MVN;
2429 value = inverted;
2430 break;
2431
2432 case OPCODE_MVN:
2433 new_inst = OPCODE_MOV;
2434 value = inverted;
2435 break;
2436
2437 case OPCODE_AND: /* AND <-> BIC */
2438 new_inst = OPCODE_BIC;
2439 value = inverted;
2440 break;
2441
2442 case OPCODE_BIC:
2443 new_inst = OPCODE_AND;
2444 value = inverted;
2445 break;
2446
2447 case OPCODE_ADC: /* ADC <-> SBC */
2448 new_inst = OPCODE_SBC;
2449 value = inverted;
2450 break;
2451
2452 case OPCODE_SBC:
2453 new_inst = OPCODE_ADC;
2454 value = inverted;
2455 break;
2456
2457 /* We cannot do anything */
2458 default:
2459 return FAIL;
2460 }
2461
2462 if (value == (unsigned) FAIL)
2463 return FAIL;
2464
2465 *instruction &= OPCODE_MASK;
2466 *instruction |= new_inst << DATA_OP_SHIFT;
2467 return value;
2468 }
2469
2470 static int
2471 data_op2 (str)
2472 char ** str;
2473 {
2474 int value;
2475 expressionS expr;
2476
2477 skip_whitespace (* str);
2478
2479 if (reg_required_here (str, 0) != FAIL)
2480 {
2481 if (skip_past_comma (str) == SUCCESS)
2482 /* Shift operation on register. */
2483 return decode_shift (str, NO_SHIFT_RESTRICT);
2484
2485 return SUCCESS;
2486 }
2487 else
2488 {
2489 /* Immediate expression */
2490 if (is_immediate_prefix (**str))
2491 {
2492 (*str)++;
2493 inst.error = NULL;
2494
2495 if (my_get_expression (&inst.reloc.exp, str))
2496 return FAIL;
2497
2498 if (inst.reloc.exp.X_add_symbol)
2499 {
2500 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2501 inst.reloc.pc_rel = 0;
2502 }
2503 else
2504 {
2505 if (skip_past_comma (str) == SUCCESS)
2506 {
2507 /* #x, y -- ie explicit rotation by Y */
2508 if (my_get_expression (&expr, str))
2509 return FAIL;
2510
2511 if (expr.X_op != O_constant)
2512 {
2513 inst.error = _("Constant expression expected");
2514 return FAIL;
2515 }
2516
2517 /* Rotate must be a multiple of 2 */
2518 if (((unsigned) expr.X_add_number) > 30
2519 || (expr.X_add_number & 1) != 0
2520 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2521 {
2522 inst.error = _("Invalid constant");
2523 return FAIL;
2524 }
2525 inst.instruction |= INST_IMMEDIATE;
2526 inst.instruction |= inst.reloc.exp.X_add_number;
2527 inst.instruction |= expr.X_add_number << 7;
2528 return SUCCESS;
2529 }
2530
2531 /* Implicit rotation, select a suitable one */
2532 value = validate_immediate (inst.reloc.exp.X_add_number);
2533
2534 if (value == FAIL)
2535 {
2536 /* Can't be done, perhaps the code reads something like
2537 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2538 if ((value = negate_data_op (&inst.instruction,
2539 inst.reloc.exp.X_add_number))
2540 == FAIL)
2541 {
2542 inst.error = _("Invalid constant");
2543 return FAIL;
2544 }
2545 }
2546
2547 inst.instruction |= value;
2548 }
2549
2550 inst.instruction |= INST_IMMEDIATE;
2551 return SUCCESS;
2552 }
2553
2554 (*str)++;
2555 inst.error = _("Register or shift expression expected");
2556 return FAIL;
2557 }
2558 }
2559
2560 static int
2561 fp_op2 (str)
2562 char ** str;
2563 {
2564 skip_whitespace (* str);
2565
2566 if (fp_reg_required_here (str, 0) != FAIL)
2567 return SUCCESS;
2568 else
2569 {
2570 /* Immediate expression */
2571 if (*((*str)++) == '#')
2572 {
2573 int i;
2574
2575 inst.error = NULL;
2576
2577 skip_whitespace (* str);
2578
2579 /* First try and match exact strings, this is to guarantee that
2580 some formats will work even for cross assembly */
2581
2582 for (i = 0; fp_const[i]; i++)
2583 {
2584 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2585 {
2586 char *start = *str;
2587
2588 *str += strlen (fp_const[i]);
2589 if (is_end_of_line[(int)**str] || **str == '\0')
2590 {
2591 inst.instruction |= i + 8;
2592 return SUCCESS;
2593 }
2594 *str = start;
2595 }
2596 }
2597
2598 /* Just because we didn't get a match doesn't mean that the
2599 constant isn't valid, just that it is in a format that we
2600 don't automatically recognize. Try parsing it with
2601 the standard expression routines. */
2602 if ((i = my_get_float_expression (str)) >= 0)
2603 {
2604 inst.instruction |= i + 8;
2605 return SUCCESS;
2606 }
2607
2608 inst.error = _("Invalid floating point immediate expression");
2609 return FAIL;
2610 }
2611 inst.error = _("Floating point register or immediate expression expected");
2612 return FAIL;
2613 }
2614 }
2615
2616 static void
2617 do_arit (str, flags)
2618 char * str;
2619 unsigned long flags;
2620 {
2621 skip_whitespace (str);
2622
2623 if (reg_required_here (&str, 12) == FAIL
2624 || skip_past_comma (&str) == FAIL
2625 || reg_required_here (&str, 16) == FAIL
2626 || skip_past_comma (&str) == FAIL
2627 || data_op2 (&str) == FAIL)
2628 {
2629 if (!inst.error)
2630 inst.error = BAD_ARGS;
2631 return;
2632 }
2633
2634 inst.instruction |= flags;
2635 end_of_line (str);
2636 return;
2637 }
2638
2639 static void
2640 do_adr (str, flags)
2641 char * str;
2642 unsigned long flags;
2643 {
2644 /* This is a pseudo-op of the form "adr rd, label" to be converted
2645 into a relative address of the form "add rd, pc, #label-.-8". */
2646 skip_whitespace (str);
2647
2648 if (reg_required_here (&str, 12) == FAIL
2649 || skip_past_comma (&str) == FAIL
2650 || my_get_expression (&inst.reloc.exp, &str))
2651 {
2652 if (!inst.error)
2653 inst.error = BAD_ARGS;
2654 return;
2655 }
2656
2657 /* Frag hacking will turn this into a sub instruction if the offset turns
2658 out to be negative. */
2659 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2660 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2661 inst.reloc.pc_rel = 1;
2662 inst.instruction |= flags;
2663
2664 end_of_line (str);
2665 }
2666
2667 static void
2668 do_adrl (str, flags)
2669 char * str;
2670 unsigned long flags;
2671 {
2672 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2673 into a relative address of the form:
2674 add rd, pc, #low(label-.-8)"
2675 add rd, rd, #high(label-.-8)" */
2676
2677 skip_whitespace (str);
2678
2679 if (reg_required_here (& str, 12) == FAIL
2680 || skip_past_comma (& str) == FAIL
2681 || my_get_expression (& inst.reloc.exp, & str))
2682 {
2683 if (!inst.error)
2684 inst.error = BAD_ARGS;
2685 return;
2686 }
2687
2688 end_of_line (str);
2689
2690 /* Frag hacking will turn this into a sub instruction if the offset turns
2691 out to be negative. */
2692 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2693 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2694 inst.reloc.pc_rel = 1;
2695 inst.instruction |= flags;
2696 inst.size = INSN_SIZE * 2;
2697
2698 return;
2699 }
2700
2701 static void
2702 do_cmp (str, flags)
2703 char * str;
2704 unsigned long flags;
2705 {
2706 skip_whitespace (str);
2707
2708 if (reg_required_here (&str, 16) == FAIL)
2709 {
2710 if (!inst.error)
2711 inst.error = BAD_ARGS;
2712 return;
2713 }
2714
2715 if (skip_past_comma (&str) == FAIL
2716 || data_op2 (&str) == FAIL)
2717 {
2718 if (!inst.error)
2719 inst.error = BAD_ARGS;
2720 return;
2721 }
2722
2723 inst.instruction |= flags;
2724 if ((flags & 0x0000f000) == 0)
2725 inst.instruction |= CONDS_BIT;
2726
2727 end_of_line (str);
2728 return;
2729 }
2730
2731 static void
2732 do_mov (str, flags)
2733 char * str;
2734 unsigned long flags;
2735 {
2736 skip_whitespace (str);
2737
2738 if (reg_required_here (&str, 12) == FAIL)
2739 {
2740 if (!inst.error)
2741 inst.error = BAD_ARGS;
2742 return;
2743 }
2744
2745 if (skip_past_comma (&str) == FAIL
2746 || data_op2 (&str) == FAIL)
2747 {
2748 if (!inst.error)
2749 inst.error = BAD_ARGS;
2750 return;
2751 }
2752
2753 inst.instruction |= flags;
2754 end_of_line (str);
2755 return;
2756 }
2757
2758 static int
2759 ldst_extend (str, hwse)
2760 char ** str;
2761 int hwse;
2762 {
2763 int add = INDEX_UP;
2764
2765 switch (**str)
2766 {
2767 case '#':
2768 case '$':
2769 (*str)++;
2770 if (my_get_expression (& inst.reloc.exp, str))
2771 return FAIL;
2772
2773 if (inst.reloc.exp.X_op == O_constant)
2774 {
2775 int value = inst.reloc.exp.X_add_number;
2776
2777 if ((hwse && (value < -255 || value > 255))
2778 || (value < -4095 || value > 4095))
2779 {
2780 inst.error = _("address offset too large");
2781 return FAIL;
2782 }
2783
2784 if (value < 0)
2785 {
2786 value = -value;
2787 add = 0;
2788 }
2789
2790 /* Halfword and signextension instructions have the
2791 immediate value split across bits 11..8 and bits 3..0 */
2792 if (hwse)
2793 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2794 else
2795 inst.instruction |= add | value;
2796 }
2797 else
2798 {
2799 if (hwse)
2800 {
2801 inst.instruction |= HWOFFSET_IMM;
2802 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2803 }
2804 else
2805 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2806 inst.reloc.pc_rel = 0;
2807 }
2808 return SUCCESS;
2809
2810 case '-':
2811 add = 0; /* and fall through */
2812 case '+':
2813 (*str)++; /* and fall through */
2814 default:
2815 if (reg_required_here (str, 0) == FAIL)
2816 return FAIL;
2817
2818 if (hwse)
2819 inst.instruction |= add;
2820 else
2821 {
2822 inst.instruction |= add | OFFSET_REG;
2823 if (skip_past_comma (str) == SUCCESS)
2824 return decode_shift (str, SHIFT_RESTRICT);
2825 }
2826
2827 return SUCCESS;
2828 }
2829 }
2830
2831 static void
2832 do_ldst (str, flags)
2833 char * str;
2834 unsigned long flags;
2835 {
2836 int halfword = 0;
2837 int pre_inc = 0;
2838 int conflict_reg;
2839 int value;
2840
2841 /* This is not ideal, but it is the simplest way of dealing with the
2842 ARM7T halfword instructions (since they use a different
2843 encoding, but the same mnemonic): */
2844 halfword = (flags & 0x80000000) != 0;
2845 if (halfword)
2846 {
2847 /* This is actually a load/store of a halfword, or a
2848 signed-extension load */
2849 if ((cpu_variant & ARM_HALFWORD) == 0)
2850 {
2851 inst.error
2852 = _("Processor does not support halfwords or signed bytes");
2853 return;
2854 }
2855
2856 inst.instruction = (inst.instruction & COND_MASK)
2857 | (flags & ~COND_MASK);
2858
2859 flags = 0;
2860 }
2861
2862 skip_whitespace (str);
2863
2864 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2865 {
2866 if (!inst.error)
2867 inst.error = BAD_ARGS;
2868 return;
2869 }
2870
2871 if (skip_past_comma (& str) == FAIL)
2872 {
2873 inst.error = _("Address expected");
2874 return;
2875 }
2876
2877 if (*str == '[')
2878 {
2879 int reg;
2880
2881 str++;
2882
2883 skip_whitespace (str);
2884
2885 if ((reg = reg_required_here (&str, 16)) == FAIL)
2886 return;
2887
2888 /* Conflicts can occur on stores as well as loads. */
2889 conflict_reg = (conflict_reg == reg);
2890
2891 skip_whitespace (str);
2892
2893 if (*str == ']')
2894 {
2895 str ++;
2896
2897 if (skip_past_comma (&str) == SUCCESS)
2898 {
2899 /* [Rn],... (post inc) */
2900 if (ldst_extend (&str, halfword) == FAIL)
2901 return;
2902 if (conflict_reg)
2903 as_warn (_("%s register same as write-back base"),
2904 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2905 }
2906 else
2907 {
2908 /* [Rn] */
2909 if (halfword)
2910 inst.instruction |= HWOFFSET_IMM;
2911
2912 skip_whitespace (str);
2913
2914 if (*str == '!')
2915 {
2916 if (conflict_reg)
2917 as_warn (_("%s register same as write-back base"),
2918 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2919 str++;
2920 inst.instruction |= WRITE_BACK;
2921 }
2922
2923 flags |= INDEX_UP;
2924 if (! (flags & TRANS_BIT))
2925 pre_inc = 1;
2926 }
2927 }
2928 else
2929 {
2930 /* [Rn,...] */
2931 if (skip_past_comma (&str) == FAIL)
2932 {
2933 inst.error = _("pre-indexed expression expected");
2934 return;
2935 }
2936
2937 pre_inc = 1;
2938 if (ldst_extend (&str, halfword) == FAIL)
2939 return;
2940
2941 skip_whitespace (str);
2942
2943 if (*str++ != ']')
2944 {
2945 inst.error = _("missing ]");
2946 return;
2947 }
2948
2949 skip_whitespace (str);
2950
2951 if (*str == '!')
2952 {
2953 if (conflict_reg)
2954 as_warn (_("%s register same as write-back base"),
2955 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2956 str++;
2957 inst.instruction |= WRITE_BACK;
2958 }
2959 }
2960 }
2961 else if (*str == '=')
2962 {
2963 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2964 str++;
2965
2966 skip_whitespace (str);
2967
2968 if (my_get_expression (&inst.reloc.exp, &str))
2969 return;
2970
2971 if (inst.reloc.exp.X_op != O_constant
2972 && inst.reloc.exp.X_op != O_symbol)
2973 {
2974 inst.error = _("Constant expression expected");
2975 return;
2976 }
2977
2978 if (inst.reloc.exp.X_op == O_constant
2979 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2980 {
2981 /* This can be done with a mov instruction */
2982 inst.instruction &= LITERAL_MASK;
2983 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2984 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2985 end_of_line(str);
2986 return;
2987 }
2988 else
2989 {
2990 /* Insert into literal pool */
2991 if (add_to_lit_pool () == FAIL)
2992 {
2993 if (!inst.error)
2994 inst.error = _("literal pool insertion failed");
2995 return;
2996 }
2997
2998 /* Change the instruction exp to point to the pool */
2999 if (halfword)
3000 {
3001 inst.instruction |= HWOFFSET_IMM;
3002 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3003 }
3004 else
3005 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3006 inst.reloc.pc_rel = 1;
3007 inst.instruction |= (REG_PC << 16);
3008 pre_inc = 1;
3009 }
3010 }
3011 else
3012 {
3013 if (my_get_expression (&inst.reloc.exp, &str))
3014 return;
3015
3016 if (halfword)
3017 {
3018 inst.instruction |= HWOFFSET_IMM;
3019 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3020 }
3021 else
3022 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3023 #ifndef TE_WINCE
3024 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3025 #endif
3026 inst.reloc.pc_rel = 1;
3027 inst.instruction |= (REG_PC << 16);
3028 pre_inc = 1;
3029 }
3030
3031 if (pre_inc && (flags & TRANS_BIT))
3032 inst.error = _("Pre-increment instruction with translate");
3033
3034 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3035 end_of_line (str);
3036 return;
3037 }
3038
3039 static long
3040 reg_list (strp)
3041 char ** strp;
3042 {
3043 char * str = *strp;
3044 long range = 0;
3045 int another_range;
3046
3047 /* We come back here if we get ranges concatenated by '+' or '|' */
3048 do
3049 {
3050 another_range = 0;
3051
3052 if (*str == '{')
3053 {
3054 int in_range = 0;
3055 int cur_reg = -1;
3056
3057 str++;
3058 do
3059 {
3060 int reg;
3061
3062 skip_whitespace (str);
3063
3064 if ((reg = reg_required_here (& str, -1)) == FAIL)
3065 return FAIL;
3066
3067 if (in_range)
3068 {
3069 int i;
3070
3071 if (reg <= cur_reg)
3072 {
3073 inst.error = _("Bad range in register list");
3074 return FAIL;
3075 }
3076
3077 for (i = cur_reg + 1; i < reg; i++)
3078 {
3079 if (range & (1 << i))
3080 as_tsktsk
3081 (_("Warning: Duplicated register (r%d) in register list"),
3082 i);
3083 else
3084 range |= 1 << i;
3085 }
3086 in_range = 0;
3087 }
3088
3089 if (range & (1 << reg))
3090 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3091 reg);
3092 else if (reg <= cur_reg)
3093 as_tsktsk (_("Warning: Register range not in ascending order"));
3094
3095 range |= 1 << reg;
3096 cur_reg = reg;
3097 } while (skip_past_comma (&str) != FAIL
3098 || (in_range = 1, *str++ == '-'));
3099 str--;
3100 skip_whitespace (str);
3101
3102 if (*str++ != '}')
3103 {
3104 inst.error = _("Missing `}'");
3105 return FAIL;
3106 }
3107 }
3108 else
3109 {
3110 expressionS expr;
3111
3112 if (my_get_expression (&expr, &str))
3113 return FAIL;
3114
3115 if (expr.X_op == O_constant)
3116 {
3117 if (expr.X_add_number
3118 != (expr.X_add_number & 0x0000ffff))
3119 {
3120 inst.error = _("invalid register mask");
3121 return FAIL;
3122 }
3123
3124 if ((range & expr.X_add_number) != 0)
3125 {
3126 int regno = range & expr.X_add_number;
3127
3128 regno &= -regno;
3129 regno = (1 << regno) - 1;
3130 as_tsktsk
3131 (_("Warning: Duplicated register (r%d) in register list"),
3132 regno);
3133 }
3134
3135 range |= expr.X_add_number;
3136 }
3137 else
3138 {
3139 if (inst.reloc.type != 0)
3140 {
3141 inst.error = _("expression too complex");
3142 return FAIL;
3143 }
3144
3145 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3146 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3147 inst.reloc.pc_rel = 0;
3148 }
3149 }
3150
3151 skip_whitespace (str);
3152
3153 if (*str == '|' || *str == '+')
3154 {
3155 str++;
3156 another_range = 1;
3157 }
3158 } while (another_range);
3159
3160 *strp = str;
3161 return range;
3162 }
3163
3164 static void
3165 do_ldmstm (str, flags)
3166 char * str;
3167 unsigned long flags;
3168 {
3169 int base_reg;
3170 long range;
3171
3172 skip_whitespace (str);
3173
3174 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3175 return;
3176
3177 if (base_reg == REG_PC)
3178 {
3179 inst.error = _("r15 not allowed as base register");
3180 return;
3181 }
3182
3183 skip_whitespace (str);
3184
3185 if (*str == '!')
3186 {
3187 flags |= WRITE_BACK;
3188 str++;
3189 }
3190
3191 if (skip_past_comma (&str) == FAIL
3192 || (range = reg_list (&str)) == FAIL)
3193 {
3194 if (! inst.error)
3195 inst.error = BAD_ARGS;
3196 return;
3197 }
3198
3199 if (*str == '^')
3200 {
3201 str++;
3202 flags |= LDM_TYPE_2_OR_3;
3203 }
3204
3205 inst.instruction |= flags | range;
3206 end_of_line (str);
3207 return;
3208 }
3209
3210 static void
3211 do_swi (str, flags)
3212 char * str;
3213 unsigned long flags;
3214 {
3215 skip_whitespace (str);
3216
3217 /* Allow optional leading '#'. */
3218 if (is_immediate_prefix (*str))
3219 str++;
3220
3221 if (my_get_expression (& inst.reloc.exp, & str))
3222 return;
3223
3224 inst.reloc.type = BFD_RELOC_ARM_SWI;
3225 inst.reloc.pc_rel = 0;
3226 inst.instruction |= flags;
3227
3228 end_of_line (str);
3229
3230 return;
3231 }
3232
3233 static void
3234 do_swap (str, flags)
3235 char * str;
3236 unsigned long flags;
3237 {
3238 int reg;
3239
3240 skip_whitespace (str);
3241
3242 if ((reg = reg_required_here (&str, 12)) == FAIL)
3243 return;
3244
3245 if (reg == REG_PC)
3246 {
3247 inst.error = _("r15 not allowed in swap");
3248 return;
3249 }
3250
3251 if (skip_past_comma (&str) == FAIL
3252 || (reg = reg_required_here (&str, 0)) == FAIL)
3253 {
3254 if (!inst.error)
3255 inst.error = BAD_ARGS;
3256 return;
3257 }
3258
3259 if (reg == REG_PC)
3260 {
3261 inst.error = _("r15 not allowed in swap");
3262 return;
3263 }
3264
3265 if (skip_past_comma (&str) == FAIL
3266 || *str++ != '[')
3267 {
3268 inst.error = BAD_ARGS;
3269 return;
3270 }
3271
3272 skip_whitespace (str);
3273
3274 if ((reg = reg_required_here (&str, 16)) == FAIL)
3275 return;
3276
3277 if (reg == REG_PC)
3278 {
3279 inst.error = BAD_PC;
3280 return;
3281 }
3282
3283 skip_whitespace (str);
3284
3285 if (*str++ != ']')
3286 {
3287 inst.error = _("missing ]");
3288 return;
3289 }
3290
3291 inst.instruction |= flags;
3292 end_of_line (str);
3293 return;
3294 }
3295
3296 static void
3297 do_branch (str, flags)
3298 char * str;
3299 unsigned long flags ATTRIBUTE_UNUSED;
3300 {
3301 if (my_get_expression (&inst.reloc.exp, &str))
3302 return;
3303
3304 #ifdef OBJ_ELF
3305 {
3306 char * save_in;
3307
3308 /* ScottB: February 5, 1998 */
3309 /* Check to see of PLT32 reloc required for the instruction. */
3310
3311 /* arm_parse_reloc() works on input_line_pointer.
3312 We actually want to parse the operands to the branch instruction
3313 passed in 'str'. Save the input pointer and restore it later. */
3314 save_in = input_line_pointer;
3315 input_line_pointer = str;
3316 if (inst.reloc.exp.X_op == O_symbol
3317 && *str == '('
3318 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3319 {
3320 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3321 inst.reloc.pc_rel = 0;
3322 /* Modify str to point to after parsed operands, otherwise
3323 end_of_line() will complain about the (PLT) left in str. */
3324 str = input_line_pointer;
3325 }
3326 else
3327 {
3328 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3329 inst.reloc.pc_rel = 1;
3330 }
3331 input_line_pointer = save_in;
3332 }
3333 #else
3334 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3335 inst.reloc.pc_rel = 1;
3336 #endif /* OBJ_ELF */
3337
3338 end_of_line (str);
3339 return;
3340 }
3341
3342 static void
3343 do_bx (str, flags)
3344 char * str;
3345 unsigned long flags ATTRIBUTE_UNUSED;
3346 {
3347 int reg;
3348
3349 skip_whitespace (str);
3350
3351 if ((reg = reg_required_here (&str, 0)) == FAIL)
3352 {
3353 inst.error = BAD_ARGS;
3354 return;
3355 }
3356
3357 if (reg == REG_PC)
3358 inst.error = BAD_PC;
3359
3360 end_of_line (str);
3361 }
3362
3363 static void
3364 do_cdp (str, flags)
3365 char * str;
3366 unsigned long flags ATTRIBUTE_UNUSED;
3367 {
3368 /* Co-processor data operation.
3369 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3370 skip_whitespace (str);
3371
3372 if (co_proc_number (&str) == FAIL)
3373 {
3374 if (!inst.error)
3375 inst.error = BAD_ARGS;
3376 return;
3377 }
3378
3379 if (skip_past_comma (&str) == FAIL
3380 || cp_opc_expr (&str, 20,4) == FAIL)
3381 {
3382 if (!inst.error)
3383 inst.error = BAD_ARGS;
3384 return;
3385 }
3386
3387 if (skip_past_comma (&str) == FAIL
3388 || cp_reg_required_here (&str, 12) == FAIL)
3389 {
3390 if (!inst.error)
3391 inst.error = BAD_ARGS;
3392 return;
3393 }
3394
3395 if (skip_past_comma (&str) == FAIL
3396 || cp_reg_required_here (&str, 16) == FAIL)
3397 {
3398 if (!inst.error)
3399 inst.error = BAD_ARGS;
3400 return;
3401 }
3402
3403 if (skip_past_comma (&str) == FAIL
3404 || cp_reg_required_here (&str, 0) == FAIL)
3405 {
3406 if (!inst.error)
3407 inst.error = BAD_ARGS;
3408 return;
3409 }
3410
3411 if (skip_past_comma (&str) == SUCCESS)
3412 {
3413 if (cp_opc_expr (&str, 5, 3) == FAIL)
3414 {
3415 if (!inst.error)
3416 inst.error = BAD_ARGS;
3417 return;
3418 }
3419 }
3420
3421 end_of_line (str);
3422 return;
3423 }
3424
3425 static void
3426 do_lstc (str, flags)
3427 char * str;
3428 unsigned long flags;
3429 {
3430 /* Co-processor register load/store.
3431 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3432
3433 skip_whitespace (str);
3434
3435 if (co_proc_number (&str) == FAIL)
3436 {
3437 if (!inst.error)
3438 inst.error = BAD_ARGS;
3439 return;
3440 }
3441
3442 if (skip_past_comma (&str) == FAIL
3443 || cp_reg_required_here (&str, 12) == FAIL)
3444 {
3445 if (!inst.error)
3446 inst.error = BAD_ARGS;
3447 return;
3448 }
3449
3450 if (skip_past_comma (&str) == FAIL
3451 || cp_address_required_here (&str) == FAIL)
3452 {
3453 if (! inst.error)
3454 inst.error = BAD_ARGS;
3455 return;
3456 }
3457
3458 inst.instruction |= flags;
3459 end_of_line (str);
3460 return;
3461 }
3462
3463 static void
3464 do_co_reg (str, flags)
3465 char * str;
3466 unsigned long flags;
3467 {
3468 /* Co-processor register transfer.
3469 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3470
3471 skip_whitespace (str);
3472
3473 if (co_proc_number (&str) == FAIL)
3474 {
3475 if (!inst.error)
3476 inst.error = BAD_ARGS;
3477 return;
3478 }
3479
3480 if (skip_past_comma (&str) == FAIL
3481 || cp_opc_expr (&str, 21, 3) == FAIL)
3482 {
3483 if (!inst.error)
3484 inst.error = BAD_ARGS;
3485 return;
3486 }
3487
3488 if (skip_past_comma (&str) == FAIL
3489 || reg_required_here (&str, 12) == FAIL)
3490 {
3491 if (!inst.error)
3492 inst.error = BAD_ARGS;
3493 return;
3494 }
3495
3496 if (skip_past_comma (&str) == FAIL
3497 || cp_reg_required_here (&str, 16) == FAIL)
3498 {
3499 if (!inst.error)
3500 inst.error = BAD_ARGS;
3501 return;
3502 }
3503
3504 if (skip_past_comma (&str) == FAIL
3505 || cp_reg_required_here (&str, 0) == FAIL)
3506 {
3507 if (!inst.error)
3508 inst.error = BAD_ARGS;
3509 return;
3510 }
3511
3512 if (skip_past_comma (&str) == SUCCESS)
3513 {
3514 if (cp_opc_expr (&str, 5, 3) == FAIL)
3515 {
3516 if (!inst.error)
3517 inst.error = BAD_ARGS;
3518 return;
3519 }
3520 }
3521 if (flags)
3522 {
3523 inst.error = BAD_COND;
3524 }
3525
3526 end_of_line (str);
3527 return;
3528 }
3529
3530 static void
3531 do_fp_ctrl (str, flags)
3532 char * str;
3533 unsigned long flags ATTRIBUTE_UNUSED;
3534 {
3535 /* FP control registers.
3536 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3537
3538 skip_whitespace (str);
3539
3540 if (reg_required_here (&str, 12) == FAIL)
3541 {
3542 if (!inst.error)
3543 inst.error = BAD_ARGS;
3544 return;
3545 }
3546
3547 end_of_line (str);
3548 return;
3549 }
3550
3551 static void
3552 do_fp_ldst (str, flags)
3553 char * str;
3554 unsigned long flags ATTRIBUTE_UNUSED;
3555 {
3556 skip_whitespace (str);
3557
3558 switch (inst.suffix)
3559 {
3560 case SUFF_S:
3561 break;
3562 case SUFF_D:
3563 inst.instruction |= CP_T_X;
3564 break;
3565 case SUFF_E:
3566 inst.instruction |= CP_T_Y;
3567 break;
3568 case SUFF_P:
3569 inst.instruction |= CP_T_X | CP_T_Y;
3570 break;
3571 default:
3572 abort ();
3573 }
3574
3575 if (fp_reg_required_here (&str, 12) == FAIL)
3576 {
3577 if (!inst.error)
3578 inst.error = BAD_ARGS;
3579 return;
3580 }
3581
3582 if (skip_past_comma (&str) == FAIL
3583 || cp_address_required_here (&str) == FAIL)
3584 {
3585 if (!inst.error)
3586 inst.error = BAD_ARGS;
3587 return;
3588 }
3589
3590 end_of_line (str);
3591 }
3592
3593 static void
3594 do_fp_ldmstm (str, flags)
3595 char * str;
3596 unsigned long flags;
3597 {
3598 int num_regs;
3599
3600 skip_whitespace (str);
3601
3602 if (fp_reg_required_here (&str, 12) == FAIL)
3603 {
3604 if (! inst.error)
3605 inst.error = BAD_ARGS;
3606 return;
3607 }
3608
3609 /* Get Number of registers to transfer */
3610 if (skip_past_comma (&str) == FAIL
3611 || my_get_expression (&inst.reloc.exp, &str))
3612 {
3613 if (! inst.error)
3614 inst.error = _("constant expression expected");
3615 return;
3616 }
3617
3618 if (inst.reloc.exp.X_op != O_constant)
3619 {
3620 inst.error = _("Constant value required for number of registers");
3621 return;
3622 }
3623
3624 num_regs = inst.reloc.exp.X_add_number;
3625
3626 if (num_regs < 1 || num_regs > 4)
3627 {
3628 inst.error = _("number of registers must be in the range [1:4]");
3629 return;
3630 }
3631
3632 switch (num_regs)
3633 {
3634 case 1:
3635 inst.instruction |= CP_T_X;
3636 break;
3637 case 2:
3638 inst.instruction |= CP_T_Y;
3639 break;
3640 case 3:
3641 inst.instruction |= CP_T_Y | CP_T_X;
3642 break;
3643 case 4:
3644 break;
3645 default:
3646 abort ();
3647 }
3648
3649 if (flags)
3650 {
3651 int reg;
3652 int write_back;
3653 int offset;
3654
3655 /* The instruction specified "ea" or "fd", so we can only accept
3656 [Rn]{!}. The instruction does not really support stacking or
3657 unstacking, so we have to emulate these by setting appropriate
3658 bits and offsets. */
3659 if (skip_past_comma (&str) == FAIL
3660 || *str != '[')
3661 {
3662 if (! inst.error)
3663 inst.error = BAD_ARGS;
3664 return;
3665 }
3666
3667 str++;
3668 skip_whitespace (str);
3669
3670 if ((reg = reg_required_here (&str, 16)) == FAIL)
3671 return;
3672
3673 skip_whitespace (str);
3674
3675 if (*str != ']')
3676 {
3677 inst.error = BAD_ARGS;
3678 return;
3679 }
3680
3681 str++;
3682 if (*str == '!')
3683 {
3684 write_back = 1;
3685 str++;
3686 if (reg == REG_PC)
3687 {
3688 inst.error = _("R15 not allowed as base register with write-back");
3689 return;
3690 }
3691 }
3692 else
3693 write_back = 0;
3694
3695 if (flags & CP_T_Pre)
3696 {
3697 /* Pre-decrement */
3698 offset = 3 * num_regs;
3699 if (write_back)
3700 flags |= CP_T_WB;
3701 }
3702 else
3703 {
3704 /* Post-increment */
3705 if (write_back)
3706 {
3707 flags |= CP_T_WB;
3708 offset = 3 * num_regs;
3709 }
3710 else
3711 {
3712 /* No write-back, so convert this into a standard pre-increment
3713 instruction -- aesthetically more pleasing. */
3714 flags = CP_T_Pre | CP_T_UD;
3715 offset = 0;
3716 }
3717 }
3718
3719 inst.instruction |= flags | offset;
3720 }
3721 else if (skip_past_comma (&str) == FAIL
3722 || cp_address_required_here (&str) == FAIL)
3723 {
3724 if (! inst.error)
3725 inst.error = BAD_ARGS;
3726 return;
3727 }
3728
3729 end_of_line (str);
3730 }
3731
3732 static void
3733 do_fp_dyadic (str, flags)
3734 char * str;
3735 unsigned long flags;
3736 {
3737 skip_whitespace (str);
3738
3739 switch (inst.suffix)
3740 {
3741 case SUFF_S:
3742 break;
3743 case SUFF_D:
3744 inst.instruction |= 0x00000080;
3745 break;
3746 case SUFF_E:
3747 inst.instruction |= 0x00080000;
3748 break;
3749 default:
3750 abort ();
3751 }
3752
3753 if (fp_reg_required_here (&str, 12) == FAIL)
3754 {
3755 if (! inst.error)
3756 inst.error = BAD_ARGS;
3757 return;
3758 }
3759
3760 if (skip_past_comma (&str) == FAIL
3761 || fp_reg_required_here (&str, 16) == FAIL)
3762 {
3763 if (! inst.error)
3764 inst.error = BAD_ARGS;
3765 return;
3766 }
3767
3768 if (skip_past_comma (&str) == FAIL
3769 || fp_op2 (&str) == FAIL)
3770 {
3771 if (! inst.error)
3772 inst.error = BAD_ARGS;
3773 return;
3774 }
3775
3776 inst.instruction |= flags;
3777 end_of_line (str);
3778 return;
3779 }
3780
3781 static void
3782 do_fp_monadic (str, flags)
3783 char * str;
3784 unsigned long flags;
3785 {
3786 skip_whitespace (str);
3787
3788 switch (inst.suffix)
3789 {
3790 case SUFF_S:
3791 break;
3792 case SUFF_D:
3793 inst.instruction |= 0x00000080;
3794 break;
3795 case SUFF_E:
3796 inst.instruction |= 0x00080000;
3797 break;
3798 default:
3799 abort ();
3800 }
3801
3802 if (fp_reg_required_here (&str, 12) == FAIL)
3803 {
3804 if (! inst.error)
3805 inst.error = BAD_ARGS;
3806 return;
3807 }
3808
3809 if (skip_past_comma (&str) == FAIL
3810 || fp_op2 (&str) == FAIL)
3811 {
3812 if (! inst.error)
3813 inst.error = BAD_ARGS;
3814 return;
3815 }
3816
3817 inst.instruction |= flags;
3818 end_of_line (str);
3819 return;
3820 }
3821
3822 static void
3823 do_fp_cmp (str, flags)
3824 char * str;
3825 unsigned long flags;
3826 {
3827 skip_whitespace (str);
3828
3829 if (fp_reg_required_here (&str, 16) == FAIL)
3830 {
3831 if (! inst.error)
3832 inst.error = BAD_ARGS;
3833 return;
3834 }
3835
3836 if (skip_past_comma (&str) == FAIL
3837 || fp_op2 (&str) == FAIL)
3838 {
3839 if (! inst.error)
3840 inst.error = BAD_ARGS;
3841 return;
3842 }
3843
3844 inst.instruction |= flags;
3845 end_of_line (str);
3846 return;
3847 }
3848
3849 static void
3850 do_fp_from_reg (str, flags)
3851 char * str;
3852 unsigned long flags;
3853 {
3854 skip_whitespace (str);
3855
3856 switch (inst.suffix)
3857 {
3858 case SUFF_S:
3859 break;
3860 case SUFF_D:
3861 inst.instruction |= 0x00000080;
3862 break;
3863 case SUFF_E:
3864 inst.instruction |= 0x00080000;
3865 break;
3866 default:
3867 abort ();
3868 }
3869
3870 if (fp_reg_required_here (&str, 16) == FAIL)
3871 {
3872 if (! inst.error)
3873 inst.error = BAD_ARGS;
3874 return;
3875 }
3876
3877 if (skip_past_comma (&str) == FAIL
3878 || reg_required_here (&str, 12) == FAIL)
3879 {
3880 if (! inst.error)
3881 inst.error = BAD_ARGS;
3882 return;
3883 }
3884
3885 inst.instruction |= flags;
3886 end_of_line (str);
3887 return;
3888 }
3889
3890 static void
3891 do_fp_to_reg (str, flags)
3892 char * str;
3893 unsigned long flags;
3894 {
3895 skip_whitespace (str);
3896
3897 if (reg_required_here (&str, 12) == FAIL)
3898 return;
3899
3900 if (skip_past_comma (&str) == FAIL
3901 || fp_reg_required_here (&str, 0) == FAIL)
3902 {
3903 if (! inst.error)
3904 inst.error = BAD_ARGS;
3905 return;
3906 }
3907
3908 inst.instruction |= flags;
3909 end_of_line (str);
3910 return;
3911 }
3912
3913 /* Thumb specific routines */
3914
3915 /* Parse and validate that a register is of the right form, this saves
3916 repeated checking of this information in many similar cases.
3917 Unlike the 32-bit case we do not insert the register into the opcode
3918 here, since the position is often unknown until the full instruction
3919 has been parsed. */
3920 static int
3921 thumb_reg (strp, hi_lo)
3922 char ** strp;
3923 int hi_lo;
3924 {
3925 int reg;
3926
3927 if ((reg = reg_required_here (strp, -1)) == FAIL)
3928 return FAIL;
3929
3930 switch (hi_lo)
3931 {
3932 case THUMB_REG_LO:
3933 if (reg > 7)
3934 {
3935 inst.error = _("lo register required");
3936 return FAIL;
3937 }
3938 break;
3939
3940 case THUMB_REG_HI:
3941 if (reg < 8)
3942 {
3943 inst.error = _("hi register required");
3944 return FAIL;
3945 }
3946 break;
3947
3948 default:
3949 break;
3950 }
3951
3952 return reg;
3953 }
3954
3955 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3956 was SUB. */
3957 static void
3958 thumb_add_sub (str, subtract)
3959 char * str;
3960 int subtract;
3961 {
3962 int Rd, Rs, Rn = FAIL;
3963
3964 skip_whitespace (str);
3965
3966 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3967 || skip_past_comma (&str) == FAIL)
3968 {
3969 if (! inst.error)
3970 inst.error = BAD_ARGS;
3971 return;
3972 }
3973
3974 if (is_immediate_prefix (*str))
3975 {
3976 Rs = Rd;
3977 str++;
3978 if (my_get_expression (&inst.reloc.exp, &str))
3979 return;
3980 }
3981 else
3982 {
3983 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3984 return;
3985
3986 if (skip_past_comma (&str) == FAIL)
3987 {
3988 /* Two operand format, shuffle the registers and pretend there
3989 are 3 */
3990 Rn = Rs;
3991 Rs = Rd;
3992 }
3993 else if (is_immediate_prefix (*str))
3994 {
3995 str++;
3996 if (my_get_expression (&inst.reloc.exp, &str))
3997 return;
3998 }
3999 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4000 return;
4001 }
4002
4003 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4004 for the latter case, EXPR contains the immediate that was found. */
4005 if (Rn != FAIL)
4006 {
4007 /* All register format. */
4008 if (Rd > 7 || Rs > 7 || Rn > 7)
4009 {
4010 if (Rs != Rd)
4011 {
4012 inst.error = _("dest and source1 must be the same register");
4013 return;
4014 }
4015
4016 /* Can't do this for SUB */
4017 if (subtract)
4018 {
4019 inst.error = _("subtract valid only on lo regs");
4020 return;
4021 }
4022
4023 inst.instruction = (T_OPCODE_ADD_HI
4024 | (Rd > 7 ? THUMB_H1 : 0)
4025 | (Rn > 7 ? THUMB_H2 : 0));
4026 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4027 }
4028 else
4029 {
4030 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4031 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4032 }
4033 }
4034 else
4035 {
4036 /* Immediate expression, now things start to get nasty. */
4037
4038 /* First deal with HI regs, only very restricted cases allowed:
4039 Adjusting SP, and using PC or SP to get an address. */
4040 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4041 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4042 {
4043 inst.error = _("invalid Hi register with immediate");
4044 return;
4045 }
4046
4047 if (inst.reloc.exp.X_op != O_constant)
4048 {
4049 /* Value isn't known yet, all we can do is store all the fragments
4050 we know about in the instruction and let the reloc hacking
4051 work it all out. */
4052 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4053 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4054 }
4055 else
4056 {
4057 int offset = inst.reloc.exp.X_add_number;
4058
4059 if (subtract)
4060 offset = -offset;
4061
4062 if (offset < 0)
4063 {
4064 offset = -offset;
4065 subtract = 1;
4066
4067 /* Quick check, in case offset is MIN_INT */
4068 if (offset < 0)
4069 {
4070 inst.error = _("immediate value out of range");
4071 return;
4072 }
4073 }
4074 else
4075 subtract = 0;
4076
4077 if (Rd == REG_SP)
4078 {
4079 if (offset & ~0x1fc)
4080 {
4081 inst.error = _("invalid immediate value for stack adjust");
4082 return;
4083 }
4084 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4085 inst.instruction |= offset >> 2;
4086 }
4087 else if (Rs == REG_PC || Rs == REG_SP)
4088 {
4089 if (subtract
4090 || (offset & ~0x3fc))
4091 {
4092 inst.error = _("invalid immediate for address calculation");
4093 return;
4094 }
4095 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4096 : T_OPCODE_ADD_SP);
4097 inst.instruction |= (Rd << 8) | (offset >> 2);
4098 }
4099 else if (Rs == Rd)
4100 {
4101 if (offset & ~0xff)
4102 {
4103 inst.error = _("immediate value out of range");
4104 return;
4105 }
4106 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4107 inst.instruction |= (Rd << 8) | offset;
4108 }
4109 else
4110 {
4111 if (offset & ~0x7)
4112 {
4113 inst.error = _("immediate value out of range");
4114 return;
4115 }
4116 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4117 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4118 }
4119 }
4120 }
4121
4122 end_of_line (str);
4123 }
4124
4125 static void
4126 thumb_shift (str, shift)
4127 char * str;
4128 int shift;
4129 {
4130 int Rd, Rs, Rn = FAIL;
4131
4132 skip_whitespace (str);
4133
4134 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4135 || skip_past_comma (&str) == FAIL)
4136 {
4137 if (! inst.error)
4138 inst.error = BAD_ARGS;
4139 return;
4140 }
4141
4142 if (is_immediate_prefix (*str))
4143 {
4144 /* Two operand immediate format, set Rs to Rd. */
4145 Rs = Rd;
4146 str ++;
4147 if (my_get_expression (&inst.reloc.exp, &str))
4148 return;
4149 }
4150 else
4151 {
4152 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4153 return;
4154
4155 if (skip_past_comma (&str) == FAIL)
4156 {
4157 /* Two operand format, shuffle the registers and pretend there
4158 are 3 */
4159 Rn = Rs;
4160 Rs = Rd;
4161 }
4162 else if (is_immediate_prefix (*str))
4163 {
4164 str++;
4165 if (my_get_expression (&inst.reloc.exp, &str))
4166 return;
4167 }
4168 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4169 return;
4170 }
4171
4172 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4173 for the latter case, EXPR contains the immediate that was found. */
4174
4175 if (Rn != FAIL)
4176 {
4177 if (Rs != Rd)
4178 {
4179 inst.error = _("source1 and dest must be same register");
4180 return;
4181 }
4182
4183 switch (shift)
4184 {
4185 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4186 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4187 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4188 }
4189
4190 inst.instruction |= Rd | (Rn << 3);
4191 }
4192 else
4193 {
4194 switch (shift)
4195 {
4196 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4197 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4198 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4199 }
4200
4201 if (inst.reloc.exp.X_op != O_constant)
4202 {
4203 /* Value isn't known yet, create a dummy reloc and let reloc
4204 hacking fix it up */
4205
4206 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4207 }
4208 else
4209 {
4210 unsigned shift_value = inst.reloc.exp.X_add_number;
4211
4212 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4213 {
4214 inst.error = _("Invalid immediate for shift");
4215 return;
4216 }
4217
4218 /* Shifts of zero are handled by converting to LSL */
4219 if (shift_value == 0)
4220 inst.instruction = T_OPCODE_LSL_I;
4221
4222 /* Shifts of 32 are encoded as a shift of zero */
4223 if (shift_value == 32)
4224 shift_value = 0;
4225
4226 inst.instruction |= shift_value << 6;
4227 }
4228
4229 inst.instruction |= Rd | (Rs << 3);
4230 }
4231
4232 end_of_line (str);
4233 }
4234
4235 static void
4236 thumb_mov_compare (str, move)
4237 char * str;
4238 int move;
4239 {
4240 int Rd, Rs = FAIL;
4241
4242 skip_whitespace (str);
4243
4244 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4245 || skip_past_comma (&str) == FAIL)
4246 {
4247 if (! inst.error)
4248 inst.error = BAD_ARGS;
4249 return;
4250 }
4251
4252 if (is_immediate_prefix (*str))
4253 {
4254 str++;
4255 if (my_get_expression (&inst.reloc.exp, &str))
4256 return;
4257 }
4258 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4259 return;
4260
4261 if (Rs != FAIL)
4262 {
4263 if (Rs < 8 && Rd < 8)
4264 {
4265 if (move == THUMB_MOVE)
4266 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4267 since a MOV instruction produces unpredictable results */
4268 inst.instruction = T_OPCODE_ADD_I3;
4269 else
4270 inst.instruction = T_OPCODE_CMP_LR;
4271 inst.instruction |= Rd | (Rs << 3);
4272 }
4273 else
4274 {
4275 if (move == THUMB_MOVE)
4276 inst.instruction = T_OPCODE_MOV_HR;
4277 else
4278 inst.instruction = T_OPCODE_CMP_HR;
4279
4280 if (Rd > 7)
4281 inst.instruction |= THUMB_H1;
4282
4283 if (Rs > 7)
4284 inst.instruction |= THUMB_H2;
4285
4286 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4287 }
4288 }
4289 else
4290 {
4291 if (Rd > 7)
4292 {
4293 inst.error = _("only lo regs allowed with immediate");
4294 return;
4295 }
4296
4297 if (move == THUMB_MOVE)
4298 inst.instruction = T_OPCODE_MOV_I8;
4299 else
4300 inst.instruction = T_OPCODE_CMP_I8;
4301
4302 inst.instruction |= Rd << 8;
4303
4304 if (inst.reloc.exp.X_op != O_constant)
4305 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4306 else
4307 {
4308 unsigned value = inst.reloc.exp.X_add_number;
4309
4310 if (value > 255)
4311 {
4312 inst.error = _("invalid immediate");
4313 return;
4314 }
4315
4316 inst.instruction |= value;
4317 }
4318 }
4319
4320 end_of_line (str);
4321 }
4322
4323 static void
4324 thumb_load_store (str, load_store, size)
4325 char * str;
4326 int load_store;
4327 int size;
4328 {
4329 int Rd, Rb, Ro = FAIL;
4330
4331 skip_whitespace (str);
4332
4333 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4334 || skip_past_comma (&str) == FAIL)
4335 {
4336 if (! inst.error)
4337 inst.error = BAD_ARGS;
4338 return;
4339 }
4340
4341 if (*str == '[')
4342 {
4343 str++;
4344 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4345 return;
4346
4347 if (skip_past_comma (&str) != FAIL)
4348 {
4349 if (is_immediate_prefix (*str))
4350 {
4351 str++;
4352 if (my_get_expression (&inst.reloc.exp, &str))
4353 return;
4354 }
4355 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4356 return;
4357 }
4358 else
4359 {
4360 inst.reloc.exp.X_op = O_constant;
4361 inst.reloc.exp.X_add_number = 0;
4362 }
4363
4364 if (*str != ']')
4365 {
4366 inst.error = _("expected ']'");
4367 return;
4368 }
4369 str++;
4370 }
4371 else if (*str == '=')
4372 {
4373 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4374 str++;
4375
4376 skip_whitespace (str);
4377
4378 if (my_get_expression (& inst.reloc.exp, & str))
4379 return;
4380
4381 end_of_line (str);
4382
4383 if ( inst.reloc.exp.X_op != O_constant
4384 && inst.reloc.exp.X_op != O_symbol)
4385 {
4386 inst.error = "Constant expression expected";
4387 return;
4388 }
4389
4390 if (inst.reloc.exp.X_op == O_constant
4391 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4392 {
4393 /* This can be done with a mov instruction */
4394
4395 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4396 inst.instruction |= inst.reloc.exp.X_add_number;
4397 return;
4398 }
4399
4400 /* Insert into literal pool */
4401 if (add_to_lit_pool () == FAIL)
4402 {
4403 if (!inst.error)
4404 inst.error = "literal pool insertion failed";
4405 return;
4406 }
4407
4408 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4409 inst.reloc.pc_rel = 1;
4410 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4411 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4412
4413 return;
4414 }
4415 else
4416 {
4417 if (my_get_expression (&inst.reloc.exp, &str))
4418 return;
4419
4420 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4421 inst.reloc.pc_rel = 1;
4422 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4423 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4424 end_of_line (str);
4425 return;
4426 }
4427
4428 if (Rb == REG_PC || Rb == REG_SP)
4429 {
4430 if (size != THUMB_WORD)
4431 {
4432 inst.error = _("byte or halfword not valid for base register");
4433 return;
4434 }
4435 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4436 {
4437 inst.error = _("R15 based store not allowed");
4438 return;
4439 }
4440 else if (Ro != FAIL)
4441 {
4442 inst.error = _("Invalid base register for register offset");
4443 return;
4444 }
4445
4446 if (Rb == REG_PC)
4447 inst.instruction = T_OPCODE_LDR_PC;
4448 else if (load_store == THUMB_LOAD)
4449 inst.instruction = T_OPCODE_LDR_SP;
4450 else
4451 inst.instruction = T_OPCODE_STR_SP;
4452
4453 inst.instruction |= Rd << 8;
4454 if (inst.reloc.exp.X_op == O_constant)
4455 {
4456 unsigned offset = inst.reloc.exp.X_add_number;
4457
4458 if (offset & ~0x3fc)
4459 {
4460 inst.error = _("invalid offset");
4461 return;
4462 }
4463
4464 inst.instruction |= offset >> 2;
4465 }
4466 else
4467 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4468 }
4469 else if (Rb > 7)
4470 {
4471 inst.error = _("invalid base register in load/store");
4472 return;
4473 }
4474 else if (Ro == FAIL)
4475 {
4476 /* Immediate offset */
4477 if (size == THUMB_WORD)
4478 inst.instruction = (load_store == THUMB_LOAD
4479 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4480 else if (size == THUMB_HALFWORD)
4481 inst.instruction = (load_store == THUMB_LOAD
4482 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4483 else
4484 inst.instruction = (load_store == THUMB_LOAD
4485 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4486
4487 inst.instruction |= Rd | (Rb << 3);
4488
4489 if (inst.reloc.exp.X_op == O_constant)
4490 {
4491 unsigned offset = inst.reloc.exp.X_add_number;
4492
4493 if (offset & ~(0x1f << size))
4494 {
4495 inst.error = _("Invalid offset");
4496 return;
4497 }
4498 inst.instruction |= (offset >> size) << 6;
4499 }
4500 else
4501 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4502 }
4503 else
4504 {
4505 /* Register offset */
4506 if (size == THUMB_WORD)
4507 inst.instruction = (load_store == THUMB_LOAD
4508 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4509 else if (size == THUMB_HALFWORD)
4510 inst.instruction = (load_store == THUMB_LOAD
4511 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4512 else
4513 inst.instruction = (load_store == THUMB_LOAD
4514 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4515
4516 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4517 }
4518
4519 end_of_line (str);
4520 }
4521
4522 static void
4523 do_t_nop (str)
4524 char * str;
4525 {
4526 /* Do nothing */
4527 end_of_line (str);
4528 return;
4529 }
4530
4531 /* Handle the Format 4 instructions that do not have equivalents in other
4532 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4533 BIC and MVN. */
4534 static void
4535 do_t_arit (str)
4536 char * str;
4537 {
4538 int Rd, Rs, Rn;
4539
4540 skip_whitespace (str);
4541
4542 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4543 || skip_past_comma (&str) == FAIL
4544 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4545 {
4546 inst.error = BAD_ARGS;
4547 return;
4548 }
4549
4550 if (skip_past_comma (&str) != FAIL)
4551 {
4552 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4553 (It isn't allowed for CMP either, but that isn't handled by this
4554 function.) */
4555 if (inst.instruction == T_OPCODE_TST
4556 || inst.instruction == T_OPCODE_CMN
4557 || inst.instruction == T_OPCODE_NEG
4558 || inst.instruction == T_OPCODE_MVN)
4559 {
4560 inst.error = BAD_ARGS;
4561 return;
4562 }
4563
4564 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4565 return;
4566
4567 if (Rs != Rd)
4568 {
4569 inst.error = _("dest and source1 one must be the same register");
4570 return;
4571 }
4572 Rs = Rn;
4573 }
4574
4575 if (inst.instruction == T_OPCODE_MUL
4576 && Rs == Rd)
4577 as_tsktsk (_("Rs and Rd must be different in MUL"));
4578
4579 inst.instruction |= Rd | (Rs << 3);
4580 end_of_line (str);
4581 }
4582
4583 static void
4584 do_t_add (str)
4585 char * str;
4586 {
4587 thumb_add_sub (str, 0);
4588 }
4589
4590 static void
4591 do_t_asr (str)
4592 char * str;
4593 {
4594 thumb_shift (str, THUMB_ASR);
4595 }
4596
4597 static void
4598 do_t_branch9 (str)
4599 char * str;
4600 {
4601 if (my_get_expression (&inst.reloc.exp, &str))
4602 return;
4603 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4604 inst.reloc.pc_rel = 1;
4605 end_of_line (str);
4606 }
4607
4608 static void
4609 do_t_branch12 (str)
4610 char * str;
4611 {
4612 if (my_get_expression (&inst.reloc.exp, &str))
4613 return;
4614 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4615 inst.reloc.pc_rel = 1;
4616 end_of_line (str);
4617 }
4618
4619 /* Find the real, Thumb encoded start of a Thumb function. */
4620
4621 static symbolS *
4622 find_real_start (symbolP)
4623 symbolS * symbolP;
4624 {
4625 char * real_start;
4626 const char * name = S_GET_NAME (symbolP);
4627 symbolS * new_target;
4628
4629 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4630 #define STUB_NAME ".real_start_of"
4631
4632 if (name == NULL)
4633 abort();
4634
4635 /* Names that start with '.' are local labels, not function entry points.
4636 The compiler may generate BL instructions to these labels because it
4637 needs to perform a branch to a far away location. */
4638 if (name[0] == '.')
4639 return symbolP;
4640
4641 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4642 sprintf (real_start, "%s%s", STUB_NAME, name);
4643
4644 new_target = symbol_find (real_start);
4645
4646 if (new_target == NULL)
4647 {
4648 as_warn ("Failed to find real start of function: %s\n", name);
4649 new_target = symbolP;
4650 }
4651
4652 free (real_start);
4653
4654 return new_target;
4655 }
4656
4657
4658 static void
4659 do_t_branch23 (str)
4660 char * str;
4661 {
4662 if (my_get_expression (& inst.reloc.exp, & str))
4663 return;
4664
4665 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4666 inst.reloc.pc_rel = 1;
4667 end_of_line (str);
4668
4669 /* If the destination of the branch is a defined symbol which does not have
4670 the THUMB_FUNC attribute, then we must be calling a function which has
4671 the (interfacearm) attribute. We look for the Thumb entry point to that
4672 function and change the branch to refer to that function instead. */
4673 if ( inst.reloc.exp.X_op == O_symbol
4674 && inst.reloc.exp.X_add_symbol != NULL
4675 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4676 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4677 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4678 }
4679
4680 static void
4681 do_t_bx (str)
4682 char * str;
4683 {
4684 int reg;
4685
4686 skip_whitespace (str);
4687
4688 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4689 return;
4690
4691 /* This sets THUMB_H2 from the top bit of reg. */
4692 inst.instruction |= reg << 3;
4693
4694 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4695 should cause the alignment to be checked once it is known. This is
4696 because BX PC only works if the instruction is word aligned. */
4697
4698 end_of_line (str);
4699 }
4700
4701 static void
4702 do_t_compare (str)
4703 char * str;
4704 {
4705 thumb_mov_compare (str, THUMB_COMPARE);
4706 }
4707
4708 static void
4709 do_t_ldmstm (str)
4710 char * str;
4711 {
4712 int Rb;
4713 long range;
4714
4715 skip_whitespace (str);
4716
4717 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4718 return;
4719
4720 if (*str != '!')
4721 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4722 else
4723 str++;
4724
4725 if (skip_past_comma (&str) == FAIL
4726 || (range = reg_list (&str)) == FAIL)
4727 {
4728 if (! inst.error)
4729 inst.error = BAD_ARGS;
4730 return;
4731 }
4732
4733 if (inst.reloc.type != BFD_RELOC_NONE)
4734 {
4735 /* This really doesn't seem worth it. */
4736 inst.reloc.type = BFD_RELOC_NONE;
4737 inst.error = _("Expression too complex");
4738 return;
4739 }
4740
4741 if (range & ~0xff)
4742 {
4743 inst.error = _("only lo-regs valid in load/store multiple");
4744 return;
4745 }
4746
4747 inst.instruction |= (Rb << 8) | range;
4748 end_of_line (str);
4749 }
4750
4751 static void
4752 do_t_ldr (str)
4753 char * str;
4754 {
4755 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4756 }
4757
4758 static void
4759 do_t_ldrb (str)
4760 char * str;
4761 {
4762 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4763 }
4764
4765 static void
4766 do_t_ldrh (str)
4767 char * str;
4768 {
4769 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4770 }
4771
4772 static void
4773 do_t_lds (str)
4774 char * str;
4775 {
4776 int Rd, Rb, Ro;
4777
4778 skip_whitespace (str);
4779
4780 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4781 || skip_past_comma (&str) == FAIL
4782 || *str++ != '['
4783 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4784 || skip_past_comma (&str) == FAIL
4785 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4786 || *str++ != ']')
4787 {
4788 if (! inst.error)
4789 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4790 return;
4791 }
4792
4793 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4794 end_of_line (str);
4795 }
4796
4797 static void
4798 do_t_lsl (str)
4799 char * str;
4800 {
4801 thumb_shift (str, THUMB_LSL);
4802 }
4803
4804 static void
4805 do_t_lsr (str)
4806 char * str;
4807 {
4808 thumb_shift (str, THUMB_LSR);
4809 }
4810
4811 static void
4812 do_t_mov (str)
4813 char * str;
4814 {
4815 thumb_mov_compare (str, THUMB_MOVE);
4816 }
4817
4818 static void
4819 do_t_push_pop (str)
4820 char * str;
4821 {
4822 long range;
4823
4824 skip_whitespace (str);
4825
4826 if ((range = reg_list (&str)) == FAIL)
4827 {
4828 if (! inst.error)
4829 inst.error = BAD_ARGS;
4830 return;
4831 }
4832
4833 if (inst.reloc.type != BFD_RELOC_NONE)
4834 {
4835 /* This really doesn't seem worth it. */
4836 inst.reloc.type = BFD_RELOC_NONE;
4837 inst.error = _("Expression too complex");
4838 return;
4839 }
4840
4841 if (range & ~0xff)
4842 {
4843 if ((inst.instruction == T_OPCODE_PUSH
4844 && (range & ~0xff) == 1 << REG_LR)
4845 || (inst.instruction == T_OPCODE_POP
4846 && (range & ~0xff) == 1 << REG_PC))
4847 {
4848 inst.instruction |= THUMB_PP_PC_LR;
4849 range &= 0xff;
4850 }
4851 else
4852 {
4853 inst.error = _("invalid register list to push/pop instruction");
4854 return;
4855 }
4856 }
4857
4858 inst.instruction |= range;
4859 end_of_line (str);
4860 }
4861
4862 static void
4863 do_t_str (str)
4864 char * str;
4865 {
4866 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4867 }
4868
4869 static void
4870 do_t_strb (str)
4871 char * str;
4872 {
4873 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4874 }
4875
4876 static void
4877 do_t_strh (str)
4878 char * str;
4879 {
4880 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4881 }
4882
4883 static void
4884 do_t_sub (str)
4885 char * str;
4886 {
4887 thumb_add_sub (str, 1);
4888 }
4889
4890 static void
4891 do_t_swi (str)
4892 char * str;
4893 {
4894 skip_whitespace (str);
4895
4896 if (my_get_expression (&inst.reloc.exp, &str))
4897 return;
4898
4899 inst.reloc.type = BFD_RELOC_ARM_SWI;
4900 end_of_line (str);
4901 return;
4902 }
4903
4904 static void
4905 do_t_adr (str)
4906 char * str;
4907 {
4908 int reg;
4909
4910 /* This is a pseudo-op of the form "adr rd, label" to be converted
4911 into a relative address of the form "add rd, pc, #label-.-4". */
4912 skip_whitespace (str);
4913
4914 /* Store Rd in temporary location inside instruction. */
4915 if ((reg = reg_required_here (&str, 4)) == FAIL
4916 || (reg > 7) /* For Thumb reg must be r0..r7. */
4917 || skip_past_comma (&str) == FAIL
4918 || my_get_expression (&inst.reloc.exp, &str))
4919 {
4920 if (!inst.error)
4921 inst.error = BAD_ARGS;
4922 return;
4923 }
4924
4925 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4926 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
4927 inst.reloc.pc_rel = 1;
4928 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
4929
4930 end_of_line (str);
4931 }
4932
4933 static void
4934 insert_reg (entry)
4935 int entry;
4936 {
4937 int len = strlen (reg_table[entry].name) + 2;
4938 char * buf = (char *) xmalloc (len);
4939 char * buf2 = (char *) xmalloc (len);
4940 int i = 0;
4941
4942 #ifdef REGISTER_PREFIX
4943 buf[i++] = REGISTER_PREFIX;
4944 #endif
4945
4946 strcpy (buf + i, reg_table[entry].name);
4947
4948 for (i = 0; buf[i]; i++)
4949 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4950
4951 buf2[i] = '\0';
4952
4953 hash_insert (arm_reg_hsh, buf, (PTR) &reg_table[entry]);
4954 hash_insert (arm_reg_hsh, buf2, (PTR) &reg_table[entry]);
4955 }
4956
4957 static void
4958 insert_reg_alias (str, regnum)
4959 char *str;
4960 int regnum;
4961 {
4962 struct reg_entry *new =
4963 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4964 char *name = xmalloc (strlen (str) + 1);
4965 strcpy (name, str);
4966
4967 new->name = name;
4968 new->number = regnum;
4969
4970 hash_insert (arm_reg_hsh, name, (PTR) new);
4971 }
4972
4973 static void
4974 set_constant_flonums ()
4975 {
4976 int i;
4977
4978 for (i = 0; i < NUM_FLOAT_VALS; i++)
4979 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4980 abort ();
4981 }
4982
4983 void
4984 md_begin ()
4985 {
4986 unsigned mach;
4987 unsigned int i;
4988
4989 if ( (arm_ops_hsh = hash_new ()) == NULL
4990 || (arm_tops_hsh = hash_new ()) == NULL
4991 || (arm_cond_hsh = hash_new ()) == NULL
4992 || (arm_shift_hsh = hash_new ()) == NULL
4993 || (arm_reg_hsh = hash_new ()) == NULL
4994 || (arm_psr_hsh = hash_new ()) == NULL)
4995 as_fatal (_("Virtual memory exhausted"));
4996
4997 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4998 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4999 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5000 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5001 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5002 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5003 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5004 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5005 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5006 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5007
5008 for (i = 0; reg_table[i].name; i++)
5009 insert_reg (i);
5010
5011 set_constant_flonums ();
5012
5013 #if defined OBJ_COFF || defined OBJ_ELF
5014 {
5015 unsigned int flags = 0;
5016
5017 /* Set the flags in the private structure. */
5018 if (uses_apcs_26) flags |= F_APCS26;
5019 if (support_interwork) flags |= F_INTERWORK;
5020 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5021 if (pic_code) flags |= F_PIC;
5022 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5023
5024 bfd_set_private_flags (stdoutput, flags);
5025 }
5026 #endif
5027
5028 /* Record the CPU type as well. */
5029 switch (cpu_variant & ARM_CPU_MASK)
5030 {
5031 case ARM_2:
5032 mach = bfd_mach_arm_2;
5033 break;
5034
5035 case ARM_3: /* Also ARM_250. */
5036 mach = bfd_mach_arm_2a;
5037 break;
5038
5039 default:
5040 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5041 mach = bfd_mach_arm_4;
5042 break;
5043
5044 case ARM_7: /* Also ARM_6. */
5045 mach = bfd_mach_arm_3;
5046 break;
5047 }
5048
5049 /* Catch special cases. */
5050 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5051 {
5052 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5053 mach = bfd_mach_arm_5T;
5054 else if (cpu_variant & ARM_EXT_V5)
5055 mach = bfd_mach_arm_5;
5056 else if (cpu_variant & ARM_THUMB)
5057 mach = bfd_mach_arm_4T;
5058 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5059 mach = bfd_mach_arm_4;
5060 else if (cpu_variant & ARM_LONGMUL)
5061 mach = bfd_mach_arm_3M;
5062 }
5063
5064 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5065 }
5066
5067 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5068 for use in the a.out file, and stores them in the array pointed to by buf.
5069 This knows about the endian-ness of the target machine and does
5070 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5071 2 (short) and 4 (long) Floating numbers are put out as a series of
5072 LITTLENUMS (shorts, here at least). */
5073 void
5074 md_number_to_chars (buf, val, n)
5075 char * buf;
5076 valueT val;
5077 int n;
5078 {
5079 if (target_big_endian)
5080 number_to_chars_bigendian (buf, val, n);
5081 else
5082 number_to_chars_littleendian (buf, val, n);
5083 }
5084
5085 static valueT
5086 md_chars_to_number (buf, n)
5087 char * buf;
5088 int n;
5089 {
5090 valueT result = 0;
5091 unsigned char * where = (unsigned char *) buf;
5092
5093 if (target_big_endian)
5094 {
5095 while (n--)
5096 {
5097 result <<= 8;
5098 result |= (*where++ & 255);
5099 }
5100 }
5101 else
5102 {
5103 while (n--)
5104 {
5105 result <<= 8;
5106 result |= (where[n] & 255);
5107 }
5108 }
5109
5110 return result;
5111 }
5112
5113 /* Turn a string in input_line_pointer into a floating point constant
5114 of type TYPE, and store the appropriate bytes in *litP. The number
5115 of LITTLENUMS emitted is stored in *sizeP . An error message is
5116 returned, or NULL on OK.
5117
5118 Note that fp constants aren't represent in the normal way on the ARM.
5119 In big endian mode, things are as expected. However, in little endian
5120 mode fp constants are big-endian word-wise, and little-endian byte-wise
5121 within the words. For example, (double) 1.1 in big endian mode is
5122 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5123 the byte sequence 99 99 f1 3f 9a 99 99 99.
5124
5125 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5126
5127 char *
5128 md_atof (type, litP, sizeP)
5129 char type;
5130 char * litP;
5131 int * sizeP;
5132 {
5133 int prec;
5134 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5135 char *t;
5136 int i;
5137
5138 switch (type)
5139 {
5140 case 'f':
5141 case 'F':
5142 case 's':
5143 case 'S':
5144 prec = 2;
5145 break;
5146
5147 case 'd':
5148 case 'D':
5149 case 'r':
5150 case 'R':
5151 prec = 4;
5152 break;
5153
5154 case 'x':
5155 case 'X':
5156 prec = 6;
5157 break;
5158
5159 case 'p':
5160 case 'P':
5161 prec = 6;
5162 break;
5163
5164 default:
5165 *sizeP = 0;
5166 return _("Bad call to MD_ATOF()");
5167 }
5168
5169 t = atof_ieee (input_line_pointer, type, words);
5170 if (t)
5171 input_line_pointer = t;
5172 *sizeP = prec * 2;
5173
5174 if (target_big_endian)
5175 {
5176 for (i = 0; i < prec; i++)
5177 {
5178 md_number_to_chars (litP, (valueT) words[i], 2);
5179 litP += 2;
5180 }
5181 }
5182 else
5183 {
5184 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5185 8 byte float the order is 1 0 3 2. */
5186 for (i = 0; i < prec; i += 2)
5187 {
5188 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5189 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5190 litP += 4;
5191 }
5192 }
5193
5194 return 0;
5195 }
5196
5197 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5198 long
5199 md_pcrel_from (fixP)
5200 fixS * fixP;
5201 {
5202 if ( fixP->fx_addsy
5203 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5204 && fixP->fx_subsy == NULL)
5205 return 0;
5206
5207 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5208 {
5209 /* PC relative addressing on the Thumb is slightly odd
5210 as the bottom two bits of the PC are forced to zero
5211 for the calculation. */
5212 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5213 }
5214
5215 #ifdef TE_WINCE
5216 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5217 so we un-adjust here to compensate for the accomodation. */
5218 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5219 #else
5220 return fixP->fx_where + fixP->fx_frag->fr_address;
5221 #endif
5222 }
5223
5224 /* Round up a section size to the appropriate boundary. */
5225 valueT
5226 md_section_align (segment, size)
5227 segT segment ATTRIBUTE_UNUSED;
5228 valueT size;
5229 {
5230 #ifdef OBJ_ELF
5231 return size;
5232 #else
5233 /* Round all sects to multiple of 4 */
5234 return (size + 3) & ~3;
5235 #endif
5236 }
5237
5238 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5239 we have no need to default values of symbols. */
5240
5241 /* ARGSUSED */
5242 symbolS *
5243 md_undefined_symbol (name)
5244 char * name;
5245 {
5246 #ifdef OBJ_ELF
5247 if (name[0] == '_' && name[1] == 'G'
5248 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5249 {
5250 if (!GOT_symbol)
5251 {
5252 if (symbol_find (name))
5253 as_bad ("GOT already in the symbol table");
5254
5255 GOT_symbol = symbol_new (name, undefined_section,
5256 (valueT)0, & zero_address_frag);
5257 }
5258
5259 return GOT_symbol;
5260 }
5261 #endif
5262
5263 return 0;
5264 }
5265
5266 /* arm_reg_parse () := if it looks like a register, return its token and
5267 advance the pointer. */
5268
5269 static int
5270 arm_reg_parse (ccp)
5271 register char ** ccp;
5272 {
5273 char * start = * ccp;
5274 char c;
5275 char * p;
5276 struct reg_entry * reg;
5277
5278 #ifdef REGISTER_PREFIX
5279 if (*start != REGISTER_PREFIX)
5280 return FAIL;
5281 p = start + 1;
5282 #else
5283 p = start;
5284 #ifdef OPTIONAL_REGISTER_PREFIX
5285 if (*p == OPTIONAL_REGISTER_PREFIX)
5286 p++, start++;
5287 #endif
5288 #endif
5289 if (!isalpha (*p) || !is_name_beginner (*p))
5290 return FAIL;
5291
5292 c = *p++;
5293 while (isalpha (c) || isdigit (c) || c == '_')
5294 c = *p++;
5295
5296 *--p = 0;
5297 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5298 *p = c;
5299
5300 if (reg)
5301 {
5302 *ccp = p;
5303 return reg->number;
5304 }
5305
5306 return FAIL;
5307 }
5308
5309 static int
5310 arm_psr_parse (ccp)
5311 register char ** ccp;
5312 {
5313 char * start = * ccp;
5314 char c;
5315 char * p;
5316 CONST struct asm_psr * psr;
5317
5318 p = start;
5319 c = *p++;
5320 while (isalpha (c) || c == '_')
5321 c = *p++;
5322
5323 *--p = 0;
5324 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5325 *p = c;
5326
5327 if (psr)
5328 {
5329 *ccp = p;
5330 return psr->number;
5331 }
5332
5333 return FAIL;
5334 }
5335
5336 int
5337 md_apply_fix3 (fixP, val, seg)
5338 fixS * fixP;
5339 valueT * val;
5340 segT seg;
5341 {
5342 offsetT value = * val;
5343 offsetT newval;
5344 unsigned int newimm;
5345 unsigned long temp;
5346 int sign;
5347 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5348 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5349
5350 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5351
5352 /* Note whether this will delete the relocation. */
5353 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5354 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5355 && !fixP->fx_pcrel)
5356 #else
5357 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5358 #endif
5359 fixP->fx_done = 1;
5360
5361 /* If this symbol is in a different section then we need to leave it for
5362 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5363 so we have to undo it's effects here. */
5364 if (fixP->fx_pcrel)
5365 {
5366 if (fixP->fx_addsy != NULL
5367 && S_IS_DEFINED (fixP->fx_addsy)
5368 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5369 {
5370 if (target_oabi
5371 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5372 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5373 ))
5374 value = 0;
5375 else
5376 value += md_pcrel_from (fixP);
5377 }
5378 }
5379
5380 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5381
5382 switch (fixP->fx_r_type)
5383 {
5384 case BFD_RELOC_ARM_IMMEDIATE:
5385 newimm = validate_immediate (value);
5386 temp = md_chars_to_number (buf, INSN_SIZE);
5387
5388 /* If the instruction will fail, see if we can fix things up by
5389 changing the opcode. */
5390 if (newimm == (unsigned int) FAIL
5391 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5392 {
5393 as_bad_where (fixP->fx_file, fixP->fx_line,
5394 _("invalid constant (%lx) after fixup"),
5395 (unsigned long) value);
5396 break;
5397 }
5398
5399 newimm |= (temp & 0xfffff000);
5400 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5401 break;
5402
5403 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5404 {
5405 unsigned int highpart = 0;
5406 unsigned int newinsn = 0xe1a00000; /* nop */
5407 newimm = validate_immediate (value);
5408 temp = md_chars_to_number (buf, INSN_SIZE);
5409
5410 /* If the instruction will fail, see if we can fix things up by
5411 changing the opcode. */
5412 if (newimm == (unsigned int) FAIL
5413 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5414 {
5415 /* No ? OK - try using two ADD instructions to generate the value. */
5416 newimm = validate_immediate_twopart (value, & highpart);
5417
5418 /* Yes - then make sure that the second instruction is also an add. */
5419 if (newimm != (unsigned int) FAIL)
5420 newinsn = temp;
5421 /* Still No ? Try using a negated value. */
5422 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5423 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5424 /* Otherwise - give up. */
5425 else
5426 {
5427 as_bad_where (fixP->fx_file, fixP->fx_line,
5428 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5429 break;
5430 }
5431
5432 /* Replace the first operand in the 2nd instruction (which is the PC)
5433 with the destination register. We have already added in the PC in the
5434 first instruction and we do not want to do it again. */
5435 newinsn &= ~ 0xf0000;
5436 newinsn |= ((newinsn & 0x0f000) << 4);
5437 }
5438
5439 newimm |= (temp & 0xfffff000);
5440 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5441
5442 highpart |= (newinsn & 0xfffff000);
5443 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5444 }
5445 break;
5446
5447 case BFD_RELOC_ARM_OFFSET_IMM:
5448 sign = value >= 0;
5449
5450 if (value < 0)
5451 value = - value;
5452
5453 if (validate_offset_imm (value, 0) == FAIL)
5454 {
5455 as_bad_where (fixP->fx_file, fixP->fx_line,
5456 _("bad immediate value for offset (%ld)"), (long) value);
5457 break;
5458 }
5459
5460 newval = md_chars_to_number (buf, INSN_SIZE);
5461 newval &= 0xff7ff000;
5462 newval |= value | (sign ? INDEX_UP : 0);
5463 md_number_to_chars (buf, newval, INSN_SIZE);
5464 break;
5465
5466 case BFD_RELOC_ARM_OFFSET_IMM8:
5467 case BFD_RELOC_ARM_HWLITERAL:
5468 sign = value >= 0;
5469
5470 if (value < 0)
5471 value = - value;
5472
5473 if (validate_offset_imm (value, 1) == FAIL)
5474 {
5475 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5476 as_bad_where (fixP->fx_file, fixP->fx_line,
5477 _("invalid literal constant: pool needs to be closer"));
5478 else
5479 as_bad (_("bad immediate value for half-word offset (%ld)"),
5480 (long) value);
5481 break;
5482 }
5483
5484 newval = md_chars_to_number (buf, INSN_SIZE);
5485 newval &= 0xff7ff0f0;
5486 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5487 md_number_to_chars (buf, newval, INSN_SIZE);
5488 break;
5489
5490 case BFD_RELOC_ARM_LITERAL:
5491 sign = value >= 0;
5492
5493 if (value < 0)
5494 value = - value;
5495
5496 if (validate_offset_imm (value, 0) == FAIL)
5497 {
5498 as_bad_where (fixP->fx_file, fixP->fx_line,
5499 _("invalid literal constant: pool needs to be closer"));
5500 break;
5501 }
5502
5503 newval = md_chars_to_number (buf, INSN_SIZE);
5504 newval &= 0xff7ff000;
5505 newval |= value | (sign ? INDEX_UP : 0);
5506 md_number_to_chars (buf, newval, INSN_SIZE);
5507 break;
5508
5509 case BFD_RELOC_ARM_SHIFT_IMM:
5510 newval = md_chars_to_number (buf, INSN_SIZE);
5511 if (((unsigned long) value) > 32
5512 || (value == 32
5513 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5514 {
5515 as_bad_where (fixP->fx_file, fixP->fx_line,
5516 _("shift expression is too large"));
5517 break;
5518 }
5519
5520 if (value == 0)
5521 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5522 else if (value == 32)
5523 value = 0;
5524 newval &= 0xfffff07f;
5525 newval |= (value & 0x1f) << 7;
5526 md_number_to_chars (buf, newval , INSN_SIZE);
5527 break;
5528
5529 case BFD_RELOC_ARM_SWI:
5530 if (arm_data->thumb_mode)
5531 {
5532 if (((unsigned long) value) > 0xff)
5533 as_bad_where (fixP->fx_file, fixP->fx_line,
5534 _("Invalid swi expression"));
5535 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5536 newval |= value;
5537 md_number_to_chars (buf, newval, THUMB_SIZE);
5538 }
5539 else
5540 {
5541 if (((unsigned long) value) > 0x00ffffff)
5542 as_bad_where (fixP->fx_file, fixP->fx_line,
5543 _("Invalid swi expression"));
5544 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5545 newval |= value;
5546 md_number_to_chars (buf, newval , INSN_SIZE);
5547 }
5548 break;
5549
5550 case BFD_RELOC_ARM_MULTI:
5551 if (((unsigned long) value) > 0xffff)
5552 as_bad_where (fixP->fx_file, fixP->fx_line,
5553 _("Invalid expression in load/store multiple"));
5554 newval = value | md_chars_to_number (buf, INSN_SIZE);
5555 md_number_to_chars (buf, newval, INSN_SIZE);
5556 break;
5557
5558 case BFD_RELOC_ARM_PCREL_BRANCH:
5559 newval = md_chars_to_number (buf, INSN_SIZE);
5560
5561 /* Sign-extend a 24-bit number. */
5562 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5563
5564 #ifdef OBJ_ELF
5565 if (! target_oabi)
5566 value = fixP->fx_offset;
5567 #endif
5568
5569 /* We are going to store value (shifted right by two) in the
5570 instruction, in a 24 bit, signed field. Thus we need to check
5571 that none of the top 8 bits of the shifted value (top 7 bits of
5572 the unshifted, unsigned value) are set, or that they are all set. */
5573 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5574 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5575 {
5576 #ifdef OBJ_ELF
5577 /* Normally we would be stuck at this point, since we cannot store
5578 the absolute address that is the destination of the branch in the
5579 24 bits of the branch instruction. If however, we happen to know
5580 that the destination of the branch is in the same section as the
5581 branch instruciton itself, then we can compute the relocation for
5582 ourselves and not have to bother the linker with it.
5583
5584 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5585 because I have not worked out how to do this for OBJ_COFF or
5586 target_oabi. */
5587 if (! target_oabi
5588 && fixP->fx_addsy != NULL
5589 && S_IS_DEFINED (fixP->fx_addsy)
5590 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5591 {
5592 /* Get pc relative value to go into the branch. */
5593 value = * val;
5594
5595 /* Permit a backward branch provided that enough bits are set.
5596 Allow a forwards branch, provided that enough bits are clear. */
5597 if ((value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5598 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5599 fixP->fx_done = 1;
5600 }
5601
5602 if (! fixP->fx_done)
5603 #endif
5604 as_bad_where (fixP->fx_file, fixP->fx_line,
5605 _("gas can't handle same-section branch dest >= 0x04000000"));
5606 }
5607
5608 value >>= 2;
5609 value += SEXT24 (newval);
5610
5611 if ((value & ~ ((offsetT) 0xffffff)) != 0
5612 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5613 as_bad_where (fixP->fx_file, fixP->fx_line,
5614 _("out of range branch"));
5615
5616 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5617 md_number_to_chars (buf, newval, INSN_SIZE);
5618 break;
5619
5620 case BFD_RELOC_ARM_PCREL_BLX:
5621 {
5622 offsetT hbit;
5623 newval = md_chars_to_number (buf, INSN_SIZE);
5624
5625 #ifdef OBJ_ELF
5626 if (! target_oabi)
5627 value = fixP->fx_offset;
5628 #endif
5629 hbit = (value >> 1) & 1;
5630 value = (value >> 2) & 0x00ffffff;
5631 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5632 newval = value | (newval & 0xfe000000) | (hbit << 24);
5633 md_number_to_chars (buf, newval, INSN_SIZE);
5634 }
5635 break;
5636
5637 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5638 newval = md_chars_to_number (buf, THUMB_SIZE);
5639 {
5640 addressT diff = (newval & 0xff) << 1;
5641 if (diff & 0x100)
5642 diff |= ~0xff;
5643
5644 value += diff;
5645 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5646 as_bad_where (fixP->fx_file, fixP->fx_line,
5647 _("Branch out of range"));
5648 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5649 }
5650 md_number_to_chars (buf, newval, THUMB_SIZE);
5651 break;
5652
5653 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5654 newval = md_chars_to_number (buf, THUMB_SIZE);
5655 {
5656 addressT diff = (newval & 0x7ff) << 1;
5657 if (diff & 0x800)
5658 diff |= ~0x7ff;
5659
5660 value += diff;
5661 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5662 as_bad_where (fixP->fx_file, fixP->fx_line,
5663 _("Branch out of range"));
5664 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5665 }
5666 md_number_to_chars (buf, newval, THUMB_SIZE);
5667 break;
5668
5669 case BFD_RELOC_THUMB_PCREL_BLX:
5670 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5671 {
5672 offsetT newval2;
5673 addressT diff;
5674
5675 newval = md_chars_to_number (buf, THUMB_SIZE);
5676 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5677 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5678 if (diff & 0x400000)
5679 diff |= ~0x3fffff;
5680 #ifdef OBJ_ELF
5681 value = fixP->fx_offset;
5682 #endif
5683 value += diff;
5684 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5685 as_bad_where (fixP->fx_file, fixP->fx_line,
5686 _("Branch with link out of range"));
5687
5688 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5689 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5690 md_number_to_chars (buf, newval, THUMB_SIZE);
5691 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5692 }
5693 break;
5694
5695 case BFD_RELOC_8:
5696 if (fixP->fx_done || fixP->fx_pcrel)
5697 md_number_to_chars (buf, value, 1);
5698 #ifdef OBJ_ELF
5699 else if (!target_oabi)
5700 {
5701 value = fixP->fx_offset;
5702 md_number_to_chars (buf, value, 1);
5703 }
5704 #endif
5705 break;
5706
5707 case BFD_RELOC_16:
5708 if (fixP->fx_done || fixP->fx_pcrel)
5709 md_number_to_chars (buf, value, 2);
5710 #ifdef OBJ_ELF
5711 else if (!target_oabi)
5712 {
5713 value = fixP->fx_offset;
5714 md_number_to_chars (buf, value, 2);
5715 }
5716 #endif
5717 break;
5718
5719 #ifdef OBJ_ELF
5720 case BFD_RELOC_ARM_GOT32:
5721 case BFD_RELOC_ARM_GOTOFF:
5722 md_number_to_chars (buf, 0, 4);
5723 break;
5724 #endif
5725
5726 case BFD_RELOC_RVA:
5727 case BFD_RELOC_32:
5728 if (fixP->fx_done || fixP->fx_pcrel)
5729 md_number_to_chars (buf, value, 4);
5730 #ifdef OBJ_ELF
5731 else if (!target_oabi)
5732 {
5733 value = fixP->fx_offset;
5734 md_number_to_chars (buf, value, 4);
5735 }
5736 #endif
5737 break;
5738
5739 #ifdef OBJ_ELF
5740 case BFD_RELOC_ARM_PLT32:
5741 /* It appears the instruction is fully prepared at this point. */
5742 break;
5743 #endif
5744
5745 case BFD_RELOC_ARM_GOTPC:
5746 md_number_to_chars (buf, value, 4);
5747 break;
5748
5749 case BFD_RELOC_ARM_CP_OFF_IMM:
5750 sign = value >= 0;
5751 if (value < -1023 || value > 1023 || (value & 3))
5752 as_bad_where (fixP->fx_file, fixP->fx_line,
5753 _("Illegal value for co-processor offset"));
5754 if (value < 0)
5755 value = -value;
5756 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5757 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5758 md_number_to_chars (buf, newval , INSN_SIZE);
5759 break;
5760
5761 case BFD_RELOC_ARM_THUMB_OFFSET:
5762 newval = md_chars_to_number (buf, THUMB_SIZE);
5763 /* Exactly what ranges, and where the offset is inserted depends on
5764 the type of instruction, we can establish this from the top 4 bits */
5765 switch (newval >> 12)
5766 {
5767 case 4: /* PC load */
5768 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5769 forced to zero for these loads, so we will need to round
5770 up the offset if the instruction address is not word
5771 aligned (since the final address produced must be, and
5772 we can only describe word-aligned immediate offsets). */
5773
5774 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5775 as_bad_where (fixP->fx_file, fixP->fx_line,
5776 _("Invalid offset, target not word aligned (0x%08X)"),
5777 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5778
5779 if ((value + 2) & ~0x3fe)
5780 as_bad_where (fixP->fx_file, fixP->fx_line,
5781 _("Invalid offset, value too big (0x%08X)"), value);
5782
5783 /* Round up, since pc will be rounded down. */
5784 newval |= (value + 2) >> 2;
5785 break;
5786
5787 case 9: /* SP load/store */
5788 if (value & ~0x3fc)
5789 as_bad_where (fixP->fx_file, fixP->fx_line,
5790 _("Invalid offset, value too big (0x%08X)"), value);
5791 newval |= value >> 2;
5792 break;
5793
5794 case 6: /* Word load/store */
5795 if (value & ~0x7c)
5796 as_bad_where (fixP->fx_file, fixP->fx_line,
5797 _("Invalid offset, value too big (0x%08X)"), value);
5798 newval |= value << 4; /* 6 - 2 */
5799 break;
5800
5801 case 7: /* Byte load/store */
5802 if (value & ~0x1f)
5803 as_bad_where (fixP->fx_file, fixP->fx_line,
5804 _("Invalid offset, value too big (0x%08X)"), value);
5805 newval |= value << 6;
5806 break;
5807
5808 case 8: /* Halfword load/store */
5809 if (value & ~0x3e)
5810 as_bad_where (fixP->fx_file, fixP->fx_line,
5811 _("Invalid offset, value too big (0x%08X)"), value);
5812 newval |= value << 5; /* 6 - 1 */
5813 break;
5814
5815 default:
5816 as_bad_where (fixP->fx_file, fixP->fx_line,
5817 "Unable to process relocation for thumb opcode: %lx",
5818 (unsigned long) newval);
5819 break;
5820 }
5821 md_number_to_chars (buf, newval, THUMB_SIZE);
5822 break;
5823
5824 case BFD_RELOC_ARM_THUMB_ADD:
5825 /* This is a complicated relocation, since we use it for all of
5826 the following immediate relocations:
5827 3bit ADD/SUB
5828 8bit ADD/SUB
5829 9bit ADD/SUB SP word-aligned
5830 10bit ADD PC/SP word-aligned
5831
5832 The type of instruction being processed is encoded in the
5833 instruction field:
5834 0x8000 SUB
5835 0x00F0 Rd
5836 0x000F Rs
5837 */
5838 newval = md_chars_to_number (buf, THUMB_SIZE);
5839 {
5840 int rd = (newval >> 4) & 0xf;
5841 int rs = newval & 0xf;
5842 int subtract = newval & 0x8000;
5843
5844 if (rd == REG_SP)
5845 {
5846 if (value & ~0x1fc)
5847 as_bad_where (fixP->fx_file, fixP->fx_line,
5848 _("Invalid immediate for stack address calculation"));
5849 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5850 newval |= value >> 2;
5851 }
5852 else if (rs == REG_PC || rs == REG_SP)
5853 {
5854 if (subtract ||
5855 value & ~0x3fc)
5856 as_bad_where (fixP->fx_file, fixP->fx_line,
5857 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5858 (unsigned long) value);
5859 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5860 newval |= rd << 8;
5861 newval |= value >> 2;
5862 }
5863 else if (rs == rd)
5864 {
5865 if (value & ~0xff)
5866 as_bad_where (fixP->fx_file, fixP->fx_line,
5867 _("Invalid 8bit immediate"));
5868 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5869 newval |= (rd << 8) | value;
5870 }
5871 else
5872 {
5873 if (value & ~0x7)
5874 as_bad_where (fixP->fx_file, fixP->fx_line,
5875 _("Invalid 3bit immediate"));
5876 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5877 newval |= rd | (rs << 3) | (value << 6);
5878 }
5879 }
5880 md_number_to_chars (buf, newval , THUMB_SIZE);
5881 break;
5882
5883 case BFD_RELOC_ARM_THUMB_IMM:
5884 newval = md_chars_to_number (buf, THUMB_SIZE);
5885 switch (newval >> 11)
5886 {
5887 case 0x04: /* 8bit immediate MOV */
5888 case 0x05: /* 8bit immediate CMP */
5889 if (value < 0 || value > 255)
5890 as_bad_where (fixP->fx_file, fixP->fx_line,
5891 _("Invalid immediate: %ld is too large"),
5892 (long) value);
5893 newval |= value;
5894 break;
5895
5896 default:
5897 abort ();
5898 }
5899 md_number_to_chars (buf, newval , THUMB_SIZE);
5900 break;
5901
5902 case BFD_RELOC_ARM_THUMB_SHIFT:
5903 /* 5bit shift value (0..31) */
5904 if (value < 0 || value > 31)
5905 as_bad_where (fixP->fx_file, fixP->fx_line,
5906 _("Illegal Thumb shift value: %ld"), (long) value);
5907 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5908 newval |= value << 6;
5909 md_number_to_chars (buf, newval , THUMB_SIZE);
5910 break;
5911
5912 case BFD_RELOC_VTABLE_INHERIT:
5913 case BFD_RELOC_VTABLE_ENTRY:
5914 fixP->fx_done = 0;
5915 return 1;
5916
5917 case BFD_RELOC_NONE:
5918 default:
5919 as_bad_where (fixP->fx_file, fixP->fx_line,
5920 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5921 }
5922
5923 return 1;
5924 }
5925
5926 /* Translate internal representation of relocation info to BFD target
5927 format. */
5928 arelent *
5929 tc_gen_reloc (section, fixp)
5930 asection * section ATTRIBUTE_UNUSED;
5931 fixS * fixp;
5932 {
5933 arelent * reloc;
5934 bfd_reloc_code_real_type code;
5935
5936 reloc = (arelent *) xmalloc (sizeof (arelent));
5937
5938 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5939 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5940 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5941
5942 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5943 #ifndef OBJ_ELF
5944 if (fixp->fx_pcrel == 0)
5945 reloc->addend = fixp->fx_offset;
5946 else
5947 reloc->addend = fixp->fx_offset = reloc->address;
5948 #else /* OBJ_ELF */
5949 reloc->addend = fixp->fx_offset;
5950 #endif
5951
5952 switch (fixp->fx_r_type)
5953 {
5954 case BFD_RELOC_8:
5955 if (fixp->fx_pcrel)
5956 {
5957 code = BFD_RELOC_8_PCREL;
5958 break;
5959 }
5960
5961 case BFD_RELOC_16:
5962 if (fixp->fx_pcrel)
5963 {
5964 code = BFD_RELOC_16_PCREL;
5965 break;
5966 }
5967
5968 case BFD_RELOC_32:
5969 if (fixp->fx_pcrel)
5970 {
5971 code = BFD_RELOC_32_PCREL;
5972 break;
5973 }
5974
5975 case BFD_RELOC_ARM_PCREL_BRANCH:
5976 case BFD_RELOC_ARM_PCREL_BLX:
5977 case BFD_RELOC_RVA:
5978 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5979 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5980 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5981 case BFD_RELOC_THUMB_PCREL_BLX:
5982 case BFD_RELOC_VTABLE_ENTRY:
5983 case BFD_RELOC_VTABLE_INHERIT:
5984 code = fixp->fx_r_type;
5985 break;
5986
5987 case BFD_RELOC_ARM_LITERAL:
5988 case BFD_RELOC_ARM_HWLITERAL:
5989 /* If this is called then the a literal has been referenced across
5990 a section boundary - possibly due to an implicit dump */
5991 as_bad_where (fixp->fx_file, fixp->fx_line,
5992 _("Literal referenced across section boundary (Implicit dump?)"));
5993 return NULL;
5994
5995 #ifdef OBJ_ELF
5996 case BFD_RELOC_ARM_GOT32:
5997 case BFD_RELOC_ARM_GOTOFF:
5998 case BFD_RELOC_ARM_PLT32:
5999 code = fixp->fx_r_type;
6000 break;
6001 #endif
6002
6003 case BFD_RELOC_ARM_IMMEDIATE:
6004 as_bad_where (fixp->fx_file, fixp->fx_line,
6005 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6006 fixp->fx_r_type);
6007 return NULL;
6008
6009 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6010 as_bad_where (fixp->fx_file, fixp->fx_line,
6011 _("ADRL used for a symbol not defined in the same file"),
6012 fixp->fx_r_type);
6013 return NULL;
6014
6015 case BFD_RELOC_ARM_OFFSET_IMM:
6016 as_bad_where (fixp->fx_file, fixp->fx_line,
6017 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6018 fixp->fx_r_type);
6019 return NULL;
6020
6021 default:
6022 {
6023 char * type;
6024 switch (fixp->fx_r_type)
6025 {
6026 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6027 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6028 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6029 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6030 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6031 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6032 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6033 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6034 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6035 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6036 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6037 default: type = _("<unknown>"); break;
6038 }
6039 as_bad_where (fixp->fx_file, fixp->fx_line,
6040 _("Can not represent %s relocation in this object file format (%d)"),
6041 type, fixp->fx_pcrel);
6042 return NULL;
6043 }
6044 }
6045
6046 #ifdef OBJ_ELF
6047 if (code == BFD_RELOC_32_PCREL
6048 && GOT_symbol
6049 && fixp->fx_addsy == GOT_symbol)
6050 {
6051 code = BFD_RELOC_ARM_GOTPC;
6052 reloc->addend = fixp->fx_offset = reloc->address;
6053 }
6054 #endif
6055
6056 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6057
6058 if (reloc->howto == NULL)
6059 {
6060 as_bad_where (fixp->fx_file, fixp->fx_line,
6061 _("Can not represent %s relocation in this object file format"),
6062 bfd_get_reloc_code_name (code));
6063 return NULL;
6064 }
6065
6066 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6067 vtable entry to be used in the relocation's section offset. */
6068 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6069 reloc->address = fixp->fx_offset;
6070
6071 return reloc;
6072 }
6073
6074 int
6075 md_estimate_size_before_relax (fragP, segtype)
6076 fragS * fragP ATTRIBUTE_UNUSED;
6077 segT segtype ATTRIBUTE_UNUSED;
6078 {
6079 as_fatal (_("md_estimate_size_before_relax\n"));
6080 return 1;
6081 }
6082
6083 static void
6084 output_inst PARAMS ((void))
6085 {
6086 char * to = NULL;
6087
6088 if (inst.error)
6089 {
6090 as_bad (inst.error);
6091 return;
6092 }
6093
6094 to = frag_more (inst.size);
6095
6096 if (thumb_mode && (inst.size > THUMB_SIZE))
6097 {
6098 assert (inst.size == (2 * THUMB_SIZE));
6099 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6100 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6101 }
6102 else if (inst.size > INSN_SIZE)
6103 {
6104 assert (inst.size == (2 * INSN_SIZE));
6105 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6106 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6107 }
6108 else
6109 md_number_to_chars (to, inst.instruction, inst.size);
6110
6111 if (inst.reloc.type != BFD_RELOC_NONE)
6112 fix_new_arm (frag_now, to - frag_now->fr_literal,
6113 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6114 inst.reloc.type);
6115
6116 return;
6117 }
6118
6119 void
6120 md_assemble (str)
6121 char * str;
6122 {
6123 char c;
6124 char * p;
6125 char * q;
6126 char * start;
6127
6128 /* Align the instruction.
6129 This may not be the right thing to do but ... */
6130 /* arm_align (2, 0); */
6131 listing_prev_line (); /* Defined in listing.h */
6132
6133 /* Align the previous label if needed. */
6134 if (last_label_seen != NULL)
6135 {
6136 symbol_set_frag (last_label_seen, frag_now);
6137 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6138 S_SET_SEGMENT (last_label_seen, now_seg);
6139 }
6140
6141 memset (&inst, '\0', sizeof (inst));
6142 inst.reloc.type = BFD_RELOC_NONE;
6143
6144 skip_whitespace (str);
6145
6146 /* Scan up to the end of the op-code, which must end in white space or
6147 end of string. */
6148 for (start = p = str; *p != '\0'; p++)
6149 if (*p == ' ')
6150 break;
6151
6152 if (p == str)
6153 {
6154 as_bad (_("No operator -- statement `%s'\n"), str);
6155 return;
6156 }
6157
6158 if (thumb_mode)
6159 {
6160 CONST struct thumb_opcode * opcode;
6161
6162 c = *p;
6163 *p = '\0';
6164 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6165 *p = c;
6166
6167 if (opcode)
6168 {
6169 /* Check that this instruction is supported for this CPU. */
6170 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6171 {
6172 as_bad (_("selected processor does not support this opcode"));
6173 return;
6174 }
6175
6176 inst.instruction = opcode->value;
6177 inst.size = opcode->size;
6178 (*opcode->parms)(p);
6179 output_inst ();
6180 return;
6181 }
6182 }
6183 else
6184 {
6185 CONST struct asm_opcode * opcode;
6186 unsigned long cond_code;
6187
6188 inst.size = INSN_SIZE;
6189 /* p now points to the end of the opcode, probably white space, but we
6190 have to break the opcode up in case it contains condionals and flags;
6191 keep trying with progressively smaller basic instructions until one
6192 matches, or we run out of opcode. */
6193 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6194
6195 for (; q != str; q--)
6196 {
6197 c = *q;
6198 *q = '\0';
6199
6200 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6201 *q = c;
6202
6203 if (opcode && opcode->template)
6204 {
6205 unsigned long flag_bits = 0;
6206 char * r;
6207
6208 /* Check that this instruction is supported for this CPU. */
6209 if ((opcode->variants & cpu_variant) == 0)
6210 goto try_shorter;
6211
6212 inst.instruction = opcode->value;
6213 if (q == p) /* Just a simple opcode. */
6214 {
6215 if (opcode->comp_suffix)
6216 {
6217 if (*opcode->comp_suffix != '\0')
6218 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6219 str, opcode->comp_suffix);
6220 else
6221 /* Not a conditional instruction. */
6222 (*opcode->parms)(q, 0);
6223 }
6224 else
6225 {
6226 /* A conditional instruction with default condition. */
6227 inst.instruction |= COND_ALWAYS;
6228 (*opcode->parms)(q, 0);
6229 }
6230 output_inst ();
6231 return;
6232 }
6233
6234 /* Not just a simple opcode. Check if extra is a conditional. */
6235 r = q;
6236 if (p - r >= 2)
6237 {
6238 CONST struct asm_cond *cond;
6239 char d = *(r + 2);
6240
6241 *(r + 2) = '\0';
6242 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6243 *(r + 2) = d;
6244 if (cond)
6245 {
6246 if (cond->value == 0xf0000000)
6247 as_tsktsk (
6248 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6249
6250 cond_code = cond->value;
6251 r += 2;
6252 }
6253 else
6254 cond_code = COND_ALWAYS;
6255 }
6256 else
6257 cond_code = COND_ALWAYS;
6258
6259 /* Apply the conditional, or complain it's not allowed. */
6260 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6261 {
6262 /* Instruction isn't conditional */
6263 if (cond_code != COND_ALWAYS)
6264 {
6265 as_bad (_("Opcode `%s' is unconditional\n"), str);
6266 return;
6267 }
6268 }
6269 else
6270 /* Instruction is conditional: set the condition into it. */
6271 inst.instruction |= cond_code;
6272
6273
6274 /* If there is a compulsory suffix, it should come here, before
6275 any optional flags. */
6276 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6277 {
6278 CONST char *s = opcode->comp_suffix;
6279
6280 while (*s)
6281 {
6282 inst.suffix++;
6283 if (*r == *s)
6284 break;
6285 s++;
6286 }
6287
6288 if (*s == '\0')
6289 {
6290 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6291 opcode->comp_suffix);
6292 return;
6293 }
6294
6295 r++;
6296 }
6297
6298 /* The remainder, if any should now be flags for the instruction;
6299 Scan these checking each one found with the opcode. */
6300 if (r != p)
6301 {
6302 char d;
6303 CONST struct asm_flg *flag = opcode->flags;
6304
6305 if (flag)
6306 {
6307 int flagno;
6308
6309 d = *p;
6310 *p = '\0';
6311
6312 for (flagno = 0; flag[flagno].template; flagno++)
6313 {
6314 if (streq (r, flag[flagno].template))
6315 {
6316 flag_bits |= flag[flagno].set_bits;
6317 break;
6318 }
6319 }
6320
6321 *p = d;
6322 if (! flag[flagno].template)
6323 goto try_shorter;
6324 }
6325 else
6326 goto try_shorter;
6327 }
6328
6329 (*opcode->parms) (p, flag_bits);
6330 output_inst ();
6331 return;
6332 }
6333
6334 try_shorter:
6335 ;
6336 }
6337 }
6338
6339 /* It wasn't an instruction, but it might be a register alias of the form
6340 alias .req reg */
6341 q = p;
6342 skip_whitespace (q);
6343
6344 c = *p;
6345 *p = '\0';
6346
6347 if (*q && !strncmp (q, ".req ", 4))
6348 {
6349 int reg;
6350 char * copy_of_str = str;
6351 char * r;
6352
6353 q += 4;
6354 skip_whitespace (q);
6355
6356 for (r = q; *r != '\0'; r++)
6357 if (*r == ' ')
6358 break;
6359
6360 if (r != q)
6361 {
6362 int regnum;
6363 char d = *r;
6364
6365 *r = '\0';
6366 regnum = arm_reg_parse (& q);
6367 *r = d;
6368
6369 reg = arm_reg_parse (& str);
6370
6371 if (reg == FAIL)
6372 {
6373 if (regnum != FAIL)
6374 insert_reg_alias (str, regnum);
6375 else
6376 as_warn (_("register '%s' does not exist\n"), q);
6377 }
6378 else if (regnum != FAIL)
6379 {
6380 if (reg != regnum)
6381 as_warn (_("ignoring redefinition of register alias '%s'"),
6382 copy_of_str );
6383
6384 /* Do not warn about redefinitions to the same alias. */
6385 }
6386 else
6387 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6388 copy_of_str, q);
6389 }
6390 else
6391 as_warn (_("ignoring incomplete .req pseuso op"));
6392
6393 *p = c;
6394 return;
6395 }
6396
6397 *p = c;
6398 as_bad (_("bad instruction `%s'"), start);
6399 }
6400
6401 /*
6402 * md_parse_option
6403 * Invocation line includes a switch not recognized by the base assembler.
6404 * See if it's a processor-specific option. These are:
6405 * Cpu variants, the arm part is optional:
6406 * -m[arm]1 Currently not supported.
6407 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6408 * -m[arm]3 Arm 3 processor
6409 * -m[arm]6[xx], Arm 6 processors
6410 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6411 * -m[arm]8[10] Arm 8 processors
6412 * -m[arm]9[20][tdmi] Arm 9 processors
6413 * -mstrongarm[110[0]] StrongARM processors
6414 * -m[arm]v[2345] Arm architectures
6415 * -mall All (except the ARM1)
6416 * FP variants:
6417 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6418 * -mfpe-old (No float load/store multiples)
6419 * -mno-fpu Disable all floating point instructions
6420 * Run-time endian selection:
6421 * -EB big endian cpu
6422 * -EL little endian cpu
6423 * ARM Procedure Calling Standard:
6424 * -mapcs-32 32 bit APCS
6425 * -mapcs-26 26 bit APCS
6426 * -mapcs-float Pass floats in float regs
6427 * -mapcs-reentrant Position independent code
6428 * -mthumb-interwork Code supports Arm/Thumb interworking
6429 * -moabi Old ELF ABI
6430 */
6431
6432 CONST char * md_shortopts = "m:k";
6433 struct option md_longopts[] =
6434 {
6435 #ifdef ARM_BI_ENDIAN
6436 #define OPTION_EB (OPTION_MD_BASE + 0)
6437 {"EB", no_argument, NULL, OPTION_EB},
6438 #define OPTION_EL (OPTION_MD_BASE + 1)
6439 {"EL", no_argument, NULL, OPTION_EL},
6440 #ifdef OBJ_ELF
6441 #define OPTION_OABI (OPTION_MD_BASE +2)
6442 {"oabi", no_argument, NULL, OPTION_OABI},
6443 #endif
6444 #endif
6445 {NULL, no_argument, NULL, 0}
6446 };
6447 size_t md_longopts_size = sizeof (md_longopts);
6448
6449 int
6450 md_parse_option (c, arg)
6451 int c;
6452 char * arg;
6453 {
6454 char * str = arg;
6455
6456 switch (c)
6457 {
6458 #ifdef ARM_BI_ENDIAN
6459 case OPTION_EB:
6460 target_big_endian = 1;
6461 break;
6462 case OPTION_EL:
6463 target_big_endian = 0;
6464 break;
6465 #endif
6466
6467 case 'm':
6468 switch (*str)
6469 {
6470 case 'f':
6471 if (streq (str, "fpa10"))
6472 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6473 else if (streq (str, "fpa11"))
6474 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6475 else if (streq (str, "fpe-old"))
6476 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6477 else
6478 goto bad;
6479 break;
6480
6481 case 'n':
6482 if (streq (str, "no-fpu"))
6483 cpu_variant &= ~FPU_ALL;
6484 break;
6485
6486 #ifdef OBJ_ELF
6487 case 'o':
6488 if (streq (str, "oabi"))
6489 target_oabi = true;
6490 break;
6491 #endif
6492
6493 case 't':
6494 /* Limit assembler to generating only Thumb instructions: */
6495 if (streq (str, "thumb"))
6496 {
6497 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6498 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6499 thumb_mode = 1;
6500 }
6501 else if (streq (str, "thumb-interwork"))
6502 {
6503 if ((cpu_variant & ARM_THUMB) == 0)
6504 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6505 #if defined OBJ_COFF || defined OBJ_ELF
6506 support_interwork = true;
6507 #endif
6508 }
6509 else
6510 goto bad;
6511 break;
6512
6513 default:
6514 if (streq (str, "all"))
6515 {
6516 cpu_variant = ARM_ALL | FPU_ALL;
6517 return 1;
6518 }
6519 #if defined OBJ_COFF || defined OBJ_ELF
6520 if (! strncmp (str, "apcs-", 5))
6521 {
6522 /* GCC passes on all command line options starting "-mapcs-..."
6523 to us, so we must parse them here. */
6524
6525 str += 5;
6526
6527 if (streq (str, "32"))
6528 {
6529 uses_apcs_26 = false;
6530 return 1;
6531 }
6532 else if (streq (str, "26"))
6533 {
6534 uses_apcs_26 = true;
6535 return 1;
6536 }
6537 else if (streq (str, "frame"))
6538 {
6539 /* Stack frames are being generated - does not affect
6540 linkage of code. */
6541 return 1;
6542 }
6543 else if (streq (str, "stack-check"))
6544 {
6545 /* Stack checking is being performed - does not affect
6546 linkage, but does require that the functions
6547 __rt_stkovf_split_small and __rt_stkovf_split_big be
6548 present in the final link. */
6549
6550 return 1;
6551 }
6552 else if (streq (str, "float"))
6553 {
6554 /* Floating point arguments are being passed in the floating
6555 point registers. This does affect linking, since this
6556 version of the APCS is incompatible with the version that
6557 passes floating points in the integer registers. */
6558
6559 uses_apcs_float = true;
6560 return 1;
6561 }
6562 else if (streq (str, "reentrant"))
6563 {
6564 /* Reentrant code has been generated. This does affect
6565 linking, since there is no point in linking reentrant/
6566 position independent code with absolute position code. */
6567 pic_code = true;
6568 return 1;
6569 }
6570
6571 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6572 return 0;
6573 }
6574 #endif
6575 /* Strip off optional "arm" */
6576 if (! strncmp (str, "arm", 3))
6577 str += 3;
6578
6579 switch (*str)
6580 {
6581 case '1':
6582 if (streq (str, "1"))
6583 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6584 else
6585 goto bad;
6586 break;
6587
6588 case '2':
6589 if (streq (str, "2"))
6590 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6591 else if (streq (str, "250"))
6592 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6593 else
6594 goto bad;
6595 break;
6596
6597 case '3':
6598 if (streq (str, "3"))
6599 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6600 else
6601 goto bad;
6602 break;
6603
6604 case '6':
6605 switch (strtol (str, NULL, 10))
6606 {
6607 case 6:
6608 case 60:
6609 case 600:
6610 case 610:
6611 case 620:
6612 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6613 break;
6614 default:
6615 goto bad;
6616 }
6617 break;
6618
6619 case '7':
6620 switch (strtol (str, & str, 10)) /* Eat the processor name */
6621 {
6622 case 7:
6623 case 70:
6624 case 700:
6625 case 710:
6626 case 720:
6627 case 7100:
6628 case 7500:
6629 break;
6630 default:
6631 goto bad;
6632 }
6633 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6634 for (; *str; str++)
6635 {
6636 switch (* str)
6637 {
6638 case 't':
6639 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6640 break;
6641
6642 case 'm':
6643 cpu_variant |= ARM_LONGMUL;
6644 break;
6645
6646 case 'f': /* fe => fp enabled cpu. */
6647 if (str[1] == 'e')
6648 ++ str;
6649 else
6650 goto bad;
6651
6652 case 'c': /* Left over from 710c processor name. */
6653 case 'd': /* Debug */
6654 case 'i': /* Embedded ICE */
6655 /* Included for completeness in ARM processor naming. */
6656 break;
6657
6658 default:
6659 goto bad;
6660 }
6661 }
6662 break;
6663
6664 case '8':
6665 if (streq (str, "8") || streq (str, "810"))
6666 cpu_variant = (cpu_variant & ~ARM_ANY)
6667 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6668 else
6669 goto bad;
6670 break;
6671
6672 case '9':
6673 if (streq (str, "9"))
6674 cpu_variant = (cpu_variant & ~ARM_ANY)
6675 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6676 else if (streq (str, "920"))
6677 cpu_variant = (cpu_variant & ~ARM_ANY)
6678 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6679 else if (streq (str, "920t"))
6680 cpu_variant = (cpu_variant & ~ARM_ANY)
6681 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6682 else if (streq (str, "9tdmi"))
6683 cpu_variant = (cpu_variant & ~ARM_ANY)
6684 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6685 else
6686 goto bad;
6687 break;
6688
6689
6690 case 's':
6691 if (streq (str, "strongarm")
6692 || streq (str, "strongarm110")
6693 || streq (str, "strongarm1100"))
6694 cpu_variant = (cpu_variant & ~ARM_ANY)
6695 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6696 else
6697 goto bad;
6698 break;
6699
6700 case 'v':
6701 /* Select variant based on architecture rather than processor. */
6702 switch (*++str)
6703 {
6704 case '2':
6705 switch (*++str)
6706 {
6707 case 'a':
6708 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6709 break;
6710 case 0:
6711 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6712 break;
6713 default:
6714 as_bad (_("Invalid architecture variant -m%s"), arg);
6715 break;
6716 }
6717 break;
6718
6719 case '3':
6720 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6721
6722 switch (*++str)
6723 {
6724 case 'm': cpu_variant |= ARM_LONGMUL; break;
6725 case 0: break;
6726 default:
6727 as_bad (_("Invalid architecture variant -m%s"), arg);
6728 break;
6729 }
6730 break;
6731
6732 case '4':
6733 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6734
6735 switch (*++str)
6736 {
6737 case 't': cpu_variant |= ARM_THUMB; break;
6738 case 0: break;
6739 default:
6740 as_bad (_("Invalid architecture variant -m%s"), arg);
6741 break;
6742 }
6743 break;
6744
6745 case '5':
6746 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6747 switch (*++str)
6748 {
6749 case 't': cpu_variant |= ARM_THUMB; break;
6750 case 0: break;
6751 default:
6752 as_bad (_("Invalid architecture variant -m%s"), arg);
6753 break;
6754 }
6755 break;
6756
6757 default:
6758 as_bad (_("Invalid architecture variant -m%s"), arg);
6759 break;
6760 }
6761 break;
6762
6763 default:
6764 bad:
6765 as_bad (_("Invalid processor variant -m%s"), arg);
6766 return 0;
6767 }
6768 }
6769 break;
6770
6771 #if defined OBJ_ELF || defined OBJ_COFF
6772 case 'k':
6773 pic_code = 1;
6774 break;
6775 #endif
6776
6777 default:
6778 return 0;
6779 }
6780
6781 return 1;
6782 }
6783
6784 void
6785 md_show_usage (fp)
6786 FILE * fp;
6787 {
6788 fprintf (fp, _("\
6789 ARM Specific Assembler Options:\n\
6790 -m[arm][<processor name>] select processor variant\n\
6791 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6792 -mthumb only allow Thumb instructions\n\
6793 -mthumb-interwork mark the assembled code as supporting interworking\n\
6794 -mall allow any instruction\n\
6795 -mfpa10, -mfpa11 select floating point architecture\n\
6796 -mfpe-old don't allow floating-point multiple instructions\n\
6797 -mno-fpu don't allow any floating-point instructions.\n\
6798 -k generate PIC code.\n"));
6799 #if defined OBJ_COFF || defined OBJ_ELF
6800 fprintf (fp, _("\
6801 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
6802 -mapcs-float floating point args are passed in FP regs\n\
6803 -mapcs-reentrant the code is position independent/reentrant\n"));
6804 #endif
6805 #ifdef OBJ_ELF
6806 fprintf (fp, _("\
6807 -moabi support the old ELF ABI\n"));
6808 #endif
6809 #ifdef ARM_BI_ENDIAN
6810 fprintf (fp, _("\
6811 -EB assemble code for a big endian cpu\n\
6812 -EL assemble code for a little endian cpu\n"));
6813 #endif
6814 }
6815
6816 /* We need to be able to fix up arbitrary expressions in some statements.
6817 This is so that we can handle symbols that are an arbitrary distance from
6818 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6819 which returns part of an address in a form which will be valid for
6820 a data instruction. We do this by pushing the expression into a symbol
6821 in the expr_section, and creating a fix for that. */
6822
6823 static void
6824 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6825 fragS * frag;
6826 int where;
6827 short int size;
6828 expressionS * exp;
6829 int pc_rel;
6830 int reloc;
6831 {
6832 fixS * new_fix;
6833 arm_fix_data * arm_data;
6834
6835 switch (exp->X_op)
6836 {
6837 case O_constant:
6838 case O_symbol:
6839 case O_add:
6840 case O_subtract:
6841 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6842 break;
6843
6844 default:
6845 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6846 pc_rel, reloc);
6847 break;
6848 }
6849
6850 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6851 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6852 new_fix->tc_fix_data = (PTR) arm_data;
6853 arm_data->thumb_mode = thumb_mode;
6854
6855 return;
6856 }
6857
6858
6859 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6860 void
6861 cons_fix_new_arm (frag, where, size, exp)
6862 fragS * frag;
6863 int where;
6864 int size;
6865 expressionS * exp;
6866 {
6867 bfd_reloc_code_real_type type;
6868 int pcrel = 0;
6869
6870 /* Pick a reloc ...
6871 *
6872 * @@ Should look at CPU word size.
6873 */
6874 switch (size)
6875 {
6876 case 2:
6877 type = BFD_RELOC_16;
6878 break;
6879 case 4:
6880 default:
6881 type = BFD_RELOC_32;
6882 break;
6883 case 8:
6884 type = BFD_RELOC_64;
6885 break;
6886 }
6887
6888 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6889 }
6890
6891 /* A good place to do this, although this was probably not intended
6892 for this kind of use. We need to dump the literal pool before
6893 references are made to a null symbol pointer. */
6894 void
6895 arm_cleanup ()
6896 {
6897 if (current_poolP == NULL)
6898 return;
6899
6900 subseg_set (text_section, 0); /* Put it at the end of text section. */
6901 s_ltorg (0);
6902 listing_prev_line ();
6903 }
6904
6905 void
6906 arm_start_line_hook ()
6907 {
6908 last_label_seen = NULL;
6909 }
6910
6911 void
6912 arm_frob_label (sym)
6913 symbolS * sym;
6914 {
6915 last_label_seen = sym;
6916
6917 ARM_SET_THUMB (sym, thumb_mode);
6918
6919 #if defined OBJ_COFF || defined OBJ_ELF
6920 ARM_SET_INTERWORK (sym, support_interwork);
6921 #endif
6922
6923 if (label_is_thumb_function_name)
6924 {
6925 /* When the address of a Thumb function is taken the bottom
6926 bit of that address should be set. This will allow
6927 interworking between Arm and Thumb functions to work
6928 correctly. */
6929
6930 THUMB_SET_FUNC (sym, 1);
6931
6932 label_is_thumb_function_name = false;
6933 }
6934 }
6935
6936 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6937 ARM ones. */
6938
6939 void
6940 arm_adjust_symtab ()
6941 {
6942 #ifdef OBJ_COFF
6943 symbolS * sym;
6944
6945 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6946 {
6947 if (ARM_IS_THUMB (sym))
6948 {
6949 if (THUMB_IS_FUNC (sym))
6950 {
6951 /* Mark the symbol as a Thumb function. */
6952 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6953 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6954 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6955
6956 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6957 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6958 else
6959 as_bad (_("%s: unexpected function type: %d"),
6960 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6961 }
6962 else switch (S_GET_STORAGE_CLASS (sym))
6963 {
6964 case C_EXT:
6965 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6966 break;
6967 case C_STAT:
6968 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6969 break;
6970 case C_LABEL:
6971 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6972 break;
6973 default: /* do nothing */
6974 break;
6975 }
6976 }
6977
6978 if (ARM_IS_INTERWORK (sym))
6979 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
6980 }
6981 #endif
6982 #ifdef OBJ_ELF
6983 symbolS * sym;
6984 char bind;
6985
6986 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6987 {
6988 if (ARM_IS_THUMB (sym))
6989 {
6990 elf_symbol_type * elf_sym;
6991
6992 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
6993 bind = ELF_ST_BIND (elf_sym);
6994
6995 /* If it's a .thumb_func, declare it as so,
6996 otherwise tag label as .code 16. */
6997 if (THUMB_IS_FUNC (sym))
6998 elf_sym->internal_elf_sym.st_info =
6999 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7000 else
7001 elf_sym->internal_elf_sym.st_info =
7002 ELF_ST_INFO (bind, STT_ARM_16BIT);
7003 }
7004 }
7005 #endif
7006 }
7007
7008 int
7009 arm_data_in_code ()
7010 {
7011 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7012 {
7013 *input_line_pointer = '/';
7014 input_line_pointer += 5;
7015 *input_line_pointer = 0;
7016 return 1;
7017 }
7018
7019 return 0;
7020 }
7021
7022 char *
7023 arm_canonicalize_symbol_name (name)
7024 char * name;
7025 {
7026 int len;
7027
7028 if (thumb_mode && (len = strlen (name)) > 5
7029 && streq (name + len - 5, "/data"))
7030 *(name + len - 5) = 0;
7031
7032 return name;
7033 }
7034
7035 boolean
7036 arm_validate_fix (fixP)
7037 fixS * fixP;
7038 {
7039 /* If the destination of the branch is a defined symbol which does not have
7040 the THUMB_FUNC attribute, then we must be calling a function which has
7041 the (interfacearm) attribute. We look for the Thumb entry point to that
7042 function and change the branch to refer to that function instead. */
7043 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7044 && fixP->fx_addsy != NULL
7045 && S_IS_DEFINED (fixP->fx_addsy)
7046 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7047 {
7048 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7049 return true;
7050 }
7051
7052 return false;
7053 }
7054
7055 #ifdef OBJ_ELF
7056 /* Relocations against Thumb function names must be left unadjusted,
7057 so that the linker can use this information to correctly set the
7058 bottom bit of their addresses. The MIPS version of this function
7059 also prevents relocations that are mips-16 specific, but I do not
7060 know why it does this.
7061
7062 FIXME:
7063 There is one other problem that ought to be addressed here, but
7064 which currently is not: Taking the address of a label (rather
7065 than a function) and then later jumping to that address. Such
7066 addresses also ought to have their bottom bit set (assuming that
7067 they reside in Thumb code), but at the moment they will not. */
7068
7069 boolean
7070 arm_fix_adjustable (fixP)
7071 fixS * fixP;
7072 {
7073 if (fixP->fx_addsy == NULL)
7074 return 1;
7075
7076 /* Prevent all adjustments to global symbols. */
7077 if (S_IS_EXTERN (fixP->fx_addsy))
7078 return 0;
7079
7080 if (S_IS_WEAK (fixP->fx_addsy))
7081 return 0;
7082
7083 if (THUMB_IS_FUNC (fixP->fx_addsy)
7084 && fixP->fx_subsy == NULL)
7085 return 0;
7086
7087 /* We need the symbol name for the VTABLE entries */
7088 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7089 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7090 return 0;
7091
7092 return 1;
7093 }
7094
7095 const char *
7096 elf32_arm_target_format ()
7097 {
7098 if (target_big_endian)
7099 if (target_oabi)
7100 return "elf32-bigarm-oabi";
7101 else
7102 return "elf32-bigarm";
7103 else
7104 if (target_oabi)
7105 return "elf32-littlearm-oabi";
7106 else
7107 return "elf32-littlearm";
7108 }
7109
7110 void
7111 armelf_frob_symbol (symp, puntp)
7112 symbolS * symp;
7113 int * puntp;
7114 {
7115 elf_frob_symbol (symp, puntp);
7116 }
7117
7118 int
7119 arm_force_relocation (fixp)
7120 struct fix * fixp;
7121 {
7122 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7123 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7124 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7125 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7126 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7127 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7128 return 1;
7129
7130 return 0;
7131 }
7132
7133 static bfd_reloc_code_real_type
7134 arm_parse_reloc ()
7135 {
7136 char id[16];
7137 char * ip;
7138 unsigned int i;
7139 static struct
7140 {
7141 char * str;
7142 int len;
7143 bfd_reloc_code_real_type reloc;
7144 }
7145 reloc_map[] =
7146 {
7147 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7148 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7149 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7150 /* ScottB: Jan 30, 1998 */
7151 /* Added support for parsing "var(PLT)" branch instructions */
7152 /* generated by GCC for PLT relocs */
7153 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7154 { NULL, 0, BFD_RELOC_UNUSED }
7155 #undef MAP
7156 };
7157
7158 for (i = 0, ip = input_line_pointer;
7159 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7160 i++, ip++)
7161 id[i] = tolower (*ip);
7162
7163 for (i = 0; reloc_map[i].str; i++)
7164 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7165 break;
7166
7167 input_line_pointer += reloc_map[i].len;
7168
7169 return reloc_map[i].reloc;
7170 }
7171
7172 static void
7173 s_arm_elf_cons (nbytes)
7174 int nbytes;
7175 {
7176 expressionS exp;
7177
7178 #ifdef md_flush_pending_output
7179 md_flush_pending_output ();
7180 #endif
7181
7182 if (is_it_end_of_statement ())
7183 {
7184 demand_empty_rest_of_line ();
7185 return;
7186 }
7187
7188 #ifdef md_cons_align
7189 md_cons_align (nbytes);
7190 #endif
7191
7192 do
7193 {
7194 bfd_reloc_code_real_type reloc;
7195
7196 expression (& exp);
7197
7198 if (exp.X_op == O_symbol
7199 && * input_line_pointer == '('
7200 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7201 {
7202 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7203 int size = bfd_get_reloc_size (howto);
7204
7205 if (size > nbytes)
7206 as_bad ("%s relocations do not fit in %d bytes",
7207 howto->name, nbytes);
7208 else
7209 {
7210 register char * p = frag_more ((int) nbytes);
7211 int offset = nbytes - size;
7212
7213 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7214 & exp, 0, reloc);
7215 }
7216 }
7217 else
7218 emit_expr (& exp, (unsigned int) nbytes);
7219 }
7220 while (*input_line_pointer++ == ',');
7221
7222 input_line_pointer--; /* Put terminator back into stream. */
7223 demand_empty_rest_of_line ();
7224 }
7225
7226 #endif /* OBJ_ELF */
GDB Binutils - Deliverables
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