1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
234 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
236 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
237 static const arm_feature_set arm_ext_m
=
238 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
239 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
240 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
241 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
242 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
243 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
244 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
245 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
246 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
247 static const arm_feature_set arm_ext_v8m_main
=
248 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
249 static const arm_feature_set arm_ext_v8_1m_main
=
250 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
251 /* Instructions in ARMv8-M only found in M profile architectures. */
252 static const arm_feature_set arm_ext_v8m_m_only
=
253 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
254 static const arm_feature_set arm_ext_v6t2_v8m
=
255 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
256 /* Instructions shared between ARMv8-A and ARMv8-M. */
257 static const arm_feature_set arm_ext_atomics
=
258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
260 /* DSP instructions Tag_DSP_extension refers to. */
261 static const arm_feature_set arm_ext_dsp
=
262 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
264 static const arm_feature_set arm_ext_ras
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
266 /* FP16 instructions. */
267 static const arm_feature_set arm_ext_fp16
=
268 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
269 static const arm_feature_set arm_ext_fp16_fml
=
270 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
271 static const arm_feature_set arm_ext_v8_2
=
272 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
273 static const arm_feature_set arm_ext_v8_3
=
274 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
275 static const arm_feature_set arm_ext_sb
=
276 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
277 static const arm_feature_set arm_ext_predres
=
278 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
279 static const arm_feature_set arm_ext_bf16
=
280 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
281 static const arm_feature_set arm_ext_i8mm
=
282 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
283 static const arm_feature_set arm_ext_crc
=
284 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
285 static const arm_feature_set arm_ext_cde
=
286 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
287 static const arm_feature_set arm_ext_cde0
=
288 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
289 static const arm_feature_set arm_ext_cde1
=
290 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
291 static const arm_feature_set arm_ext_cde2
=
292 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
293 static const arm_feature_set arm_ext_cde3
=
294 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
295 static const arm_feature_set arm_ext_cde4
=
296 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
297 static const arm_feature_set arm_ext_cde5
=
298 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
299 static const arm_feature_set arm_ext_cde6
=
300 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
301 static const arm_feature_set arm_ext_cde7
=
302 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
304 static const arm_feature_set arm_arch_any
= ARM_ANY
;
305 static const arm_feature_set fpu_any
= FPU_ANY
;
306 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
307 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
308 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
310 static const arm_feature_set arm_cext_iwmmxt2
=
311 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
312 static const arm_feature_set arm_cext_iwmmxt
=
313 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
314 static const arm_feature_set arm_cext_xscale
=
315 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
316 static const arm_feature_set arm_cext_maverick
=
317 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
318 static const arm_feature_set fpu_fpa_ext_v1
=
319 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
320 static const arm_feature_set fpu_fpa_ext_v2
=
321 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
322 static const arm_feature_set fpu_vfp_ext_v1xd
=
323 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
324 static const arm_feature_set fpu_vfp_ext_v1
=
325 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
326 static const arm_feature_set fpu_vfp_ext_v2
=
327 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
328 static const arm_feature_set fpu_vfp_ext_v3xd
=
329 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
330 static const arm_feature_set fpu_vfp_ext_v3
=
331 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
332 static const arm_feature_set fpu_vfp_ext_d32
=
333 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
334 static const arm_feature_set fpu_neon_ext_v1
=
335 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
336 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
337 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
338 static const arm_feature_set mve_ext
=
339 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
340 static const arm_feature_set mve_fp_ext
=
341 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
342 /* Note: This has more than one bit set, which means using it with
343 mark_feature_used (which returns if *any* of the bits are set in the current
344 cpu variant) can give surprising results. */
345 static const arm_feature_set armv8m_fp
=
346 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
348 static const arm_feature_set fpu_vfp_fp16
=
349 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
350 static const arm_feature_set fpu_neon_ext_fma
=
351 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
353 static const arm_feature_set fpu_vfp_ext_fma
=
354 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
355 static const arm_feature_set fpu_vfp_ext_armv8
=
356 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
357 static const arm_feature_set fpu_vfp_ext_armv8xd
=
358 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
359 static const arm_feature_set fpu_neon_ext_armv8
=
360 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
361 static const arm_feature_set fpu_crypto_ext_armv8
=
362 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
363 static const arm_feature_set fpu_neon_ext_v8_1
=
364 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
365 static const arm_feature_set fpu_neon_ext_dotprod
=
366 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
368 static int mfloat_abi_opt
= -1;
369 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
371 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
372 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
374 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
375 /* Feature bits selected by the last -mcpu/-march or by the combination of the
376 last .cpu/.arch directive .arch_extension directives since that
378 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
379 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
380 static arm_feature_set selected_fpu
= FPU_NONE
;
381 /* Feature bits selected by the last .object_arch directive. */
382 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
383 /* Must be long enough to hold any of the names in arm_cpus. */
384 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
385 static char selected_cpu_name
[20];
387 extern FLONUM_TYPE generic_floating_point_number
;
389 /* Return if no cpu was selected on command-line. */
391 no_cpu_selected (void)
393 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
398 static int meabi_flags
= EABI_DEFAULT
;
400 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
403 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
408 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
413 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
414 symbolS
* GOT_symbol
;
417 /* 0: assemble for ARM,
418 1: assemble for Thumb,
419 2: assemble for Thumb even though target CPU does not support thumb
421 static int thumb_mode
= 0;
422 /* A value distinct from the possible values for thumb_mode that we
423 can use to record whether thumb_mode has been copied into the
424 tc_frag_data field of a frag. */
425 #define MODE_RECORDED (1 << 4)
427 /* Specifies the intrinsic IT insn behavior mode. */
428 enum implicit_it_mode
430 IMPLICIT_IT_MODE_NEVER
= 0x00,
431 IMPLICIT_IT_MODE_ARM
= 0x01,
432 IMPLICIT_IT_MODE_THUMB
= 0x02,
433 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
435 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
437 /* If unified_syntax is true, we are processing the new unified
438 ARM/Thumb syntax. Important differences from the old ARM mode:
440 - Immediate operands do not require a # prefix.
441 - Conditional affixes always appear at the end of the
442 instruction. (For backward compatibility, those instructions
443 that formerly had them in the middle, continue to accept them
445 - The IT instruction may appear, and if it does is validated
446 against subsequent conditional affixes. It does not generate
449 Important differences from the old Thumb mode:
451 - Immediate operands do not require a # prefix.
452 - Most of the V6T2 instructions are only available in unified mode.
453 - The .N and .W suffixes are recognized and honored (it is an error
454 if they cannot be honored).
455 - All instructions set the flags if and only if they have an 's' affix.
456 - Conditional affixes may be used. They are validated against
457 preceding IT instructions. Unlike ARM mode, you cannot use a
458 conditional affix except in the scope of an IT instruction. */
460 static bfd_boolean unified_syntax
= FALSE
;
462 /* An immediate operand can start with #, and ld*, st*, pld operands
463 can contain [ and ]. We need to tell APP not to elide whitespace
464 before a [, which can appear as the first operand for pld.
465 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
466 const char arm_symbol_chars
[] = "#[]{}";
482 enum neon_el_type type
;
486 #define NEON_MAX_TYPE_ELS 5
490 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
494 enum pred_instruction_type
500 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
501 if inside, should be the last one. */
502 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
503 i.e. BKPT and NOP. */
504 IT_INSN
, /* The IT insn has been parsed. */
505 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
506 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
507 a predication code. */
508 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
511 /* The maximum number of operands we need. */
512 #define ARM_IT_MAX_OPERANDS 6
513 #define ARM_IT_MAX_RELOCS 3
518 unsigned long instruction
;
522 /* "uncond_value" is set to the value in place of the conditional field in
523 unconditional versions of the instruction, or -1 if nothing is
526 struct neon_type vectype
;
527 /* This does not indicate an actual NEON instruction, only that
528 the mnemonic accepts neon-style type suffixes. */
530 /* Set to the opcode if the instruction needs relaxation.
531 Zero if the instruction is not relaxed. */
535 bfd_reloc_code_real_type type
;
538 } relocs
[ARM_IT_MAX_RELOCS
];
540 enum pred_instruction_type pred_insn_type
;
546 struct neon_type_el vectype
;
547 unsigned present
: 1; /* Operand present. */
548 unsigned isreg
: 1; /* Operand was a register. */
549 unsigned immisreg
: 2; /* .imm field is a second register.
550 0: imm, 1: gpr, 2: MVE Q-register. */
551 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
555 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
556 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
557 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
558 instructions. This allows us to disambiguate ARM <-> vector insns. */
559 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
560 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
561 unsigned isquad
: 1; /* Operand is SIMD quad register. */
562 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
563 unsigned iszr
: 1; /* Operand is ZR register. */
564 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
565 unsigned writeback
: 1; /* Operand has trailing ! */
566 unsigned preind
: 1; /* Preindexed address. */
567 unsigned postind
: 1; /* Postindexed address. */
568 unsigned negative
: 1; /* Index register was negated. */
569 unsigned shifted
: 1; /* Shift applied to operation. */
570 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
571 } operands
[ARM_IT_MAX_OPERANDS
];
574 static struct arm_it inst
;
576 #define NUM_FLOAT_VALS 8
578 const char * fp_const
[] =
580 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
583 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
593 #define CP_T_X 0x00008000
594 #define CP_T_Y 0x00400000
596 #define CONDS_BIT 0x00100000
597 #define LOAD_BIT 0x00100000
599 #define DOUBLE_LOAD_FLAG 0x00000001
603 const char * template_name
;
607 #define COND_ALWAYS 0xE
611 const char * template_name
;
615 struct asm_barrier_opt
617 const char * template_name
;
619 const arm_feature_set arch
;
622 /* The bit that distinguishes CPSR and SPSR. */
623 #define SPSR_BIT (1 << 22)
625 /* The individual PSR flag bits. */
626 #define PSR_c (1 << 16)
627 #define PSR_x (1 << 17)
628 #define PSR_s (1 << 18)
629 #define PSR_f (1 << 19)
634 bfd_reloc_code_real_type reloc
;
639 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
640 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
645 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
648 /* Bits for DEFINED field in neon_typed_alias. */
649 #define NTA_HASTYPE 1
650 #define NTA_HASINDEX 2
652 struct neon_typed_alias
654 unsigned char defined
;
656 struct neon_type_el eltype
;
659 /* ARM register categories. This includes coprocessor numbers and various
660 architecture extensions' registers. Each entry should have an error message
661 in reg_expected_msgs below. */
691 /* Structure for a hash table entry for a register.
692 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
693 information which states whether a vector type or index is specified (for a
694 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
700 unsigned char builtin
;
701 struct neon_typed_alias
* neon
;
704 /* Diagnostics used when we don't get a register of the expected type. */
705 const char * const reg_expected_msgs
[] =
707 [REG_TYPE_RN
] = N_("ARM register expected"),
708 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
709 [REG_TYPE_CN
] = N_("co-processor register expected"),
710 [REG_TYPE_FN
] = N_("FPA register expected"),
711 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
712 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
713 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
714 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
715 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
716 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
717 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
719 [REG_TYPE_VFC
] = N_("VFP system register expected"),
720 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
721 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
722 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
723 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
724 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
725 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
726 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
727 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
728 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
729 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
730 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
734 /* Some well known registers that we refer to directly elsewhere. */
740 /* ARM instructions take 4bytes in the object file, Thumb instructions
746 /* Basic string to match. */
747 const char * template_name
;
749 /* Parameters to instruction. */
750 unsigned int operands
[8];
752 /* Conditional tag - see opcode_lookup. */
753 unsigned int tag
: 4;
755 /* Basic instruction code. */
758 /* Thumb-format instruction code. */
761 /* Which architecture variant provides this instruction. */
762 const arm_feature_set
* avariant
;
763 const arm_feature_set
* tvariant
;
765 /* Function to call to encode instruction in ARM format. */
766 void (* aencode
) (void);
768 /* Function to call to encode instruction in Thumb format. */
769 void (* tencode
) (void);
771 /* Indicates whether this instruction may be vector predicated. */
772 unsigned int mayBeVecPred
: 1;
775 /* Defines for various bits that we will want to toggle. */
776 #define INST_IMMEDIATE 0x02000000
777 #define OFFSET_REG 0x02000000
778 #define HWOFFSET_IMM 0x00400000
779 #define SHIFT_BY_REG 0x00000010
780 #define PRE_INDEX 0x01000000
781 #define INDEX_UP 0x00800000
782 #define WRITE_BACK 0x00200000
783 #define LDM_TYPE_2_OR_3 0x00400000
784 #define CPSI_MMOD 0x00020000
786 #define LITERAL_MASK 0xf000f000
787 #define OPCODE_MASK 0xfe1fffff
788 #define V4_STR_BIT 0x00000020
789 #define VLDR_VMOV_SAME 0x0040f000
791 #define T2_SUBS_PC_LR 0xf3de8f00
793 #define DATA_OP_SHIFT 21
794 #define SBIT_SHIFT 20
796 #define T2_OPCODE_MASK 0xfe1fffff
797 #define T2_DATA_OP_SHIFT 21
798 #define T2_SBIT_SHIFT 20
800 #define A_COND_MASK 0xf0000000
801 #define A_PUSH_POP_OP_MASK 0x0fff0000
803 /* Opcodes for pushing/poping registers to/from the stack. */
804 #define A1_OPCODE_PUSH 0x092d0000
805 #define A2_OPCODE_PUSH 0x052d0004
806 #define A2_OPCODE_POP 0x049d0004
808 /* Codes to distinguish the arithmetic instructions. */
819 #define OPCODE_CMP 10
820 #define OPCODE_CMN 11
821 #define OPCODE_ORR 12
822 #define OPCODE_MOV 13
823 #define OPCODE_BIC 14
824 #define OPCODE_MVN 15
826 #define T2_OPCODE_AND 0
827 #define T2_OPCODE_BIC 1
828 #define T2_OPCODE_ORR 2
829 #define T2_OPCODE_ORN 3
830 #define T2_OPCODE_EOR 4
831 #define T2_OPCODE_ADD 8
832 #define T2_OPCODE_ADC 10
833 #define T2_OPCODE_SBC 11
834 #define T2_OPCODE_SUB 13
835 #define T2_OPCODE_RSB 14
837 #define T_OPCODE_MUL 0x4340
838 #define T_OPCODE_TST 0x4200
839 #define T_OPCODE_CMN 0x42c0
840 #define T_OPCODE_NEG 0x4240
841 #define T_OPCODE_MVN 0x43c0
843 #define T_OPCODE_ADD_R3 0x1800
844 #define T_OPCODE_SUB_R3 0x1a00
845 #define T_OPCODE_ADD_HI 0x4400
846 #define T_OPCODE_ADD_ST 0xb000
847 #define T_OPCODE_SUB_ST 0xb080
848 #define T_OPCODE_ADD_SP 0xa800
849 #define T_OPCODE_ADD_PC 0xa000
850 #define T_OPCODE_ADD_I8 0x3000
851 #define T_OPCODE_SUB_I8 0x3800
852 #define T_OPCODE_ADD_I3 0x1c00
853 #define T_OPCODE_SUB_I3 0x1e00
855 #define T_OPCODE_ASR_R 0x4100
856 #define T_OPCODE_LSL_R 0x4080
857 #define T_OPCODE_LSR_R 0x40c0
858 #define T_OPCODE_ROR_R 0x41c0
859 #define T_OPCODE_ASR_I 0x1000
860 #define T_OPCODE_LSL_I 0x0000
861 #define T_OPCODE_LSR_I 0x0800
863 #define T_OPCODE_MOV_I8 0x2000
864 #define T_OPCODE_CMP_I8 0x2800
865 #define T_OPCODE_CMP_LR 0x4280
866 #define T_OPCODE_MOV_HR 0x4600
867 #define T_OPCODE_CMP_HR 0x4500
869 #define T_OPCODE_LDR_PC 0x4800
870 #define T_OPCODE_LDR_SP 0x9800
871 #define T_OPCODE_STR_SP 0x9000
872 #define T_OPCODE_LDR_IW 0x6800
873 #define T_OPCODE_STR_IW 0x6000
874 #define T_OPCODE_LDR_IH 0x8800
875 #define T_OPCODE_STR_IH 0x8000
876 #define T_OPCODE_LDR_IB 0x7800
877 #define T_OPCODE_STR_IB 0x7000
878 #define T_OPCODE_LDR_RW 0x5800
879 #define T_OPCODE_STR_RW 0x5000
880 #define T_OPCODE_LDR_RH 0x5a00
881 #define T_OPCODE_STR_RH 0x5200
882 #define T_OPCODE_LDR_RB 0x5c00
883 #define T_OPCODE_STR_RB 0x5400
885 #define T_OPCODE_PUSH 0xb400
886 #define T_OPCODE_POP 0xbc00
888 #define T_OPCODE_BRANCH 0xe000
890 #define THUMB_SIZE 2 /* Size of thumb instruction. */
891 #define THUMB_PP_PC_LR 0x0100
892 #define THUMB_LOAD_BIT 0x0800
893 #define THUMB2_LOAD_BIT 0x00100000
895 #define BAD_SYNTAX _("syntax error")
896 #define BAD_ARGS _("bad arguments to instruction")
897 #define BAD_SP _("r13 not allowed here")
898 #define BAD_PC _("r15 not allowed here")
899 #define BAD_ODD _("Odd register not allowed here")
900 #define BAD_EVEN _("Even register not allowed here")
901 #define BAD_COND _("instruction cannot be conditional")
902 #define BAD_OVERLAP _("registers may not be the same")
903 #define BAD_HIREG _("lo register required")
904 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
905 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
906 #define BAD_BRANCH _("branch must be last instruction in IT block")
907 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
908 #define BAD_NO_VPT _("instruction not allowed in VPT block")
909 #define BAD_NOT_IT _("instruction not allowed in IT block")
910 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
911 #define BAD_FPU _("selected FPU does not support instruction")
912 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
913 #define BAD_OUT_VPT \
914 _("vector predicated instruction should be in VPT/VPST block")
915 #define BAD_IT_COND _("incorrect condition in IT block")
916 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
917 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
918 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
919 #define BAD_PC_ADDRESSING \
920 _("cannot use register index with PC-relative addressing")
921 #define BAD_PC_WRITEBACK \
922 _("cannot use writeback with PC-relative addressing")
923 #define BAD_RANGE _("branch out of range")
924 #define BAD_FP16 _("selected processor does not support fp16 instruction")
925 #define BAD_BF16 _("selected processor does not support bf16 instruction")
926 #define BAD_CDE _("selected processor does not support cde instruction")
927 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
928 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
929 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
930 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
932 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
934 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
936 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
938 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
939 #define BAD_MVE_AUTO \
940 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
941 " use a valid -march or -mcpu option.")
942 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
943 "and source operands makes instruction UNPREDICTABLE")
944 #define BAD_EL_TYPE _("bad element type for instruction")
945 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
947 static struct hash_control
* arm_ops_hsh
;
948 static struct hash_control
* arm_cond_hsh
;
949 static struct hash_control
* arm_vcond_hsh
;
950 static struct hash_control
* arm_shift_hsh
;
951 static struct hash_control
* arm_psr_hsh
;
952 static struct hash_control
* arm_v7m_psr_hsh
;
953 static struct hash_control
* arm_reg_hsh
;
954 static struct hash_control
* arm_reloc_hsh
;
955 static struct hash_control
* arm_barrier_opt_hsh
;
957 /* Stuff needed to resolve the label ambiguity
966 symbolS
* last_label_seen
;
967 static int label_is_thumb_function_name
= FALSE
;
969 /* Literal pool structure. Held on a per-section
970 and per-sub-section basis. */
972 #define MAX_LITERAL_POOL_SIZE 1024
973 typedef struct literal_pool
975 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
976 unsigned int next_free_entry
;
982 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
984 struct literal_pool
* next
;
985 unsigned int alignment
;
988 /* Pointer to a linked list of literal pools. */
989 literal_pool
* list_of_pools
= NULL
;
991 typedef enum asmfunc_states
994 WAITING_ASMFUNC_NAME
,
998 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1001 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1003 static struct current_pred now_pred
;
1007 now_pred_compatible (int cond
)
1009 return (cond
& ~1) == (now_pred
.cc
& ~1);
1013 conditional_insn (void)
1015 return inst
.cond
!= COND_ALWAYS
;
1018 static int in_pred_block (void);
1020 static int handle_pred_state (void);
1022 static void force_automatic_it_block_close (void);
1024 static void it_fsm_post_encode (void);
1026 #define set_pred_insn_type(type) \
1029 inst.pred_insn_type = type; \
1030 if (handle_pred_state () == FAIL) \
1035 #define set_pred_insn_type_nonvoid(type, failret) \
1038 inst.pred_insn_type = type; \
1039 if (handle_pred_state () == FAIL) \
1044 #define set_pred_insn_type_last() \
1047 if (inst.cond == COND_ALWAYS) \
1048 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1050 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1054 /* Toggle value[pos]. */
1055 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1059 /* This array holds the chars that always start a comment. If the
1060 pre-processor is disabled, these aren't very useful. */
1061 char arm_comment_chars
[] = "@";
1063 /* This array holds the chars that only start a comment at the beginning of
1064 a line. If the line seems to have the form '# 123 filename'
1065 .line and .file directives will appear in the pre-processed output. */
1066 /* Note that input_file.c hand checks for '#' at the beginning of the
1067 first line of the input file. This is because the compiler outputs
1068 #NO_APP at the beginning of its output. */
1069 /* Also note that comments like this one will always work. */
1070 const char line_comment_chars
[] = "#";
1072 char arm_line_separator_chars
[] = ";";
1074 /* Chars that can be used to separate mant
1075 from exp in floating point numbers. */
1076 const char EXP_CHARS
[] = "eE";
1078 /* Chars that mean this number is a floating point constant. */
1079 /* As in 0f12.456 */
1080 /* or 0d1.2345e12 */
1082 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1084 /* Prefix characters that indicate the start of an immediate
1086 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1088 /* Separator character handling. */
1090 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1092 enum fp_16bit_format
1094 ARM_FP16_FORMAT_IEEE
= 0x1,
1095 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1096 ARM_FP16_FORMAT_DEFAULT
= 0x3
1099 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1103 skip_past_char (char ** str
, char c
)
1105 /* PR gas/14987: Allow for whitespace before the expected character. */
1106 skip_whitespace (*str
);
1117 #define skip_past_comma(str) skip_past_char (str, ',')
1119 /* Arithmetic expressions (possibly involving symbols). */
1121 /* Return TRUE if anything in the expression is a bignum. */
1124 walk_no_bignums (symbolS
* sp
)
1126 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1129 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1131 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 || (symbol_get_value_expression (sp
)->X_op_symbol
1133 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1139 static bfd_boolean in_my_get_expression
= FALSE
;
1141 /* Third argument to my_get_expression. */
1142 #define GE_NO_PREFIX 0
1143 #define GE_IMM_PREFIX 1
1144 #define GE_OPT_PREFIX 2
1145 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1146 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1147 #define GE_OPT_PREFIX_BIG 3
1150 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1154 /* In unified syntax, all prefixes are optional. */
1156 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1159 switch (prefix_mode
)
1161 case GE_NO_PREFIX
: break;
1163 if (!is_immediate_prefix (**str
))
1165 inst
.error
= _("immediate expression requires a # prefix");
1171 case GE_OPT_PREFIX_BIG
:
1172 if (is_immediate_prefix (**str
))
1179 memset (ep
, 0, sizeof (expressionS
));
1181 save_in
= input_line_pointer
;
1182 input_line_pointer
= *str
;
1183 in_my_get_expression
= TRUE
;
1185 in_my_get_expression
= FALSE
;
1187 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1189 /* We found a bad or missing expression in md_operand(). */
1190 *str
= input_line_pointer
;
1191 input_line_pointer
= save_in
;
1192 if (inst
.error
== NULL
)
1193 inst
.error
= (ep
->X_op
== O_absent
1194 ? _("missing expression") :_("bad expression"));
1198 /* Get rid of any bignums now, so that we don't generate an error for which
1199 we can't establish a line number later on. Big numbers are never valid
1200 in instructions, which is where this routine is always called. */
1201 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1202 && (ep
->X_op
== O_big
1203 || (ep
->X_add_symbol
1204 && (walk_no_bignums (ep
->X_add_symbol
)
1206 && walk_no_bignums (ep
->X_op_symbol
))))))
1208 inst
.error
= _("invalid constant");
1209 *str
= input_line_pointer
;
1210 input_line_pointer
= save_in
;
1214 *str
= input_line_pointer
;
1215 input_line_pointer
= save_in
;
1219 /* Turn a string in input_line_pointer into a floating point constant
1220 of type TYPE, and store the appropriate bytes in *LITP. The number
1221 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1222 returned, or NULL on OK.
1224 Note that fp constants aren't represent in the normal way on the ARM.
1225 In big endian mode, things are as expected. However, in little endian
1226 mode fp constants are big-endian word-wise, and little-endian byte-wise
1227 within the words. For example, (double) 1.1 in big endian mode is
1228 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1229 the byte sequence 99 99 f1 3f 9a 99 99 99.
1231 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1234 md_atof (int type
, char * litP
, int * sizeP
)
1237 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1248 /* If this is a bfloat16, then parse it slightly differently, as it
1249 does not follow the IEEE specification for floating point numbers
1253 FLONUM_TYPE generic_float
;
1255 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1258 input_line_pointer
= t
;
1260 return _("invalid floating point number");
1262 switch (generic_float
.sign
)
1275 /* bfloat16 has two types of NaN - quiet and signalling.
1276 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1277 signalling NaN's have bit[0] == 0 && fraction != 0.
1278 Chosen this specific encoding as it is the same form
1279 as used by other IEEE 754 encodings in GAS. */
1290 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1320 return _("Unrecognized or unsupported floating point constant");
1323 t
= atof_ieee (input_line_pointer
, type
, words
);
1325 input_line_pointer
= t
;
1326 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1328 if (target_big_endian
|| prec
== 1)
1329 for (i
= 0; i
< prec
; i
++)
1331 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1332 litP
+= sizeof (LITTLENUM_TYPE
);
1334 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1335 for (i
= prec
- 1; i
>= 0; i
--)
1337 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1338 litP
+= sizeof (LITTLENUM_TYPE
);
1341 /* For a 4 byte float the order of elements in `words' is 1 0.
1342 For an 8 byte float the order is 1 0 3 2. */
1343 for (i
= 0; i
< prec
; i
+= 2)
1345 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1346 sizeof (LITTLENUM_TYPE
));
1347 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1348 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1349 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1355 /* We handle all bad expressions here, so that we can report the faulty
1356 instruction in the error message. */
1359 md_operand (expressionS
* exp
)
1361 if (in_my_get_expression
)
1362 exp
->X_op
= O_illegal
;
1365 /* Immediate values. */
1368 /* Generic immediate-value read function for use in directives.
1369 Accepts anything that 'expression' can fold to a constant.
1370 *val receives the number. */
1373 immediate_for_directive (int *val
)
1376 exp
.X_op
= O_illegal
;
1378 if (is_immediate_prefix (*input_line_pointer
))
1380 input_line_pointer
++;
1384 if (exp
.X_op
!= O_constant
)
1386 as_bad (_("expected #constant"));
1387 ignore_rest_of_line ();
1390 *val
= exp
.X_add_number
;
1395 /* Register parsing. */
1397 /* Generic register parser. CCP points to what should be the
1398 beginning of a register name. If it is indeed a valid register
1399 name, advance CCP over it and return the reg_entry structure;
1400 otherwise return NULL. Does not issue diagnostics. */
1402 static struct reg_entry
*
1403 arm_reg_parse_multi (char **ccp
)
1407 struct reg_entry
*reg
;
1409 skip_whitespace (start
);
1411 #ifdef REGISTER_PREFIX
1412 if (*start
!= REGISTER_PREFIX
)
1416 #ifdef OPTIONAL_REGISTER_PREFIX
1417 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1422 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1427 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1429 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1439 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1440 enum arm_reg_type type
)
1442 /* Alternative syntaxes are accepted for a few register classes. */
1449 /* Generic coprocessor register names are allowed for these. */
1450 if (reg
&& reg
->type
== REG_TYPE_CN
)
1455 /* For backward compatibility, a bare number is valid here. */
1457 unsigned long processor
= strtoul (start
, ccp
, 10);
1458 if (*ccp
!= start
&& processor
<= 15)
1463 case REG_TYPE_MMXWC
:
1464 /* WC includes WCG. ??? I'm not sure this is true for all
1465 instructions that take WC registers. */
1466 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1477 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1478 return value is the register number or FAIL. */
1481 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1484 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1487 /* Do not allow a scalar (reg+index) to parse as a register. */
1488 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1491 if (reg
&& reg
->type
== type
)
1494 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1501 /* Parse a Neon type specifier. *STR should point at the leading '.'
1502 character. Does no verification at this stage that the type fits the opcode
1509 Can all be legally parsed by this function.
1511 Fills in neon_type struct pointer with parsed information, and updates STR
1512 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1513 type, FAIL if not. */
1516 parse_neon_type (struct neon_type
*type
, char **str
)
1523 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1525 enum neon_el_type thistype
= NT_untyped
;
1526 unsigned thissize
= -1u;
1533 /* Just a size without an explicit type. */
1537 switch (TOLOWER (*ptr
))
1539 case 'i': thistype
= NT_integer
; break;
1540 case 'f': thistype
= NT_float
; break;
1541 case 'p': thistype
= NT_poly
; break;
1542 case 's': thistype
= NT_signed
; break;
1543 case 'u': thistype
= NT_unsigned
; break;
1545 thistype
= NT_float
;
1550 thistype
= NT_bfloat
;
1551 switch (TOLOWER (*(++ptr
)))
1555 thissize
= strtoul (ptr
, &ptr
, 10);
1558 as_bad (_("bad size %d in type specifier"), thissize
);
1562 case '0': case '1': case '2': case '3': case '4':
1563 case '5': case '6': case '7': case '8': case '9':
1565 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1572 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1578 /* .f is an abbreviation for .f32. */
1579 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1584 thissize
= strtoul (ptr
, &ptr
, 10);
1586 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1589 as_bad (_("bad size %d in type specifier"), thissize
);
1597 type
->el
[type
->elems
].type
= thistype
;
1598 type
->el
[type
->elems
].size
= thissize
;
1603 /* Empty/missing type is not a successful parse. */
1604 if (type
->elems
== 0)
1612 /* Errors may be set multiple times during parsing or bit encoding
1613 (particularly in the Neon bits), but usually the earliest error which is set
1614 will be the most meaningful. Avoid overwriting it with later (cascading)
1615 errors by calling this function. */
1618 first_error (const char *err
)
1624 /* Parse a single type, e.g. ".s32", leading period included. */
1626 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1629 struct neon_type optype
;
1633 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1635 if (optype
.elems
== 1)
1636 *vectype
= optype
.el
[0];
1639 first_error (_("only one type should be specified for operand"));
1645 first_error (_("vector type expected"));
1657 /* Special meanings for indices (which have a range of 0-7), which will fit into
1660 #define NEON_ALL_LANES 15
1661 #define NEON_INTERLEAVE_LANES 14
1663 /* Record a use of the given feature. */
1665 record_feature_use (const arm_feature_set
*feature
)
1668 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1670 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1673 /* If the given feature available in the selected CPU, mark it as used.
1674 Returns TRUE iff feature is available. */
1676 mark_feature_used (const arm_feature_set
*feature
)
1679 /* Do not support the use of MVE only instructions when in auto-detection or
1681 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1682 && ARM_CPU_IS_ANY (cpu_variant
))
1684 first_error (BAD_MVE_AUTO
);
1687 /* Ensure the option is valid on the current architecture. */
1688 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1691 /* Add the appropriate architecture feature for the barrier option used.
1693 record_feature_use (feature
);
1698 /* Parse either a register or a scalar, with an optional type. Return the
1699 register number, and optionally fill in the actual type of the register
1700 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1701 type/index information in *TYPEINFO. */
1704 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1705 enum arm_reg_type
*rtype
,
1706 struct neon_typed_alias
*typeinfo
)
1709 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1710 struct neon_typed_alias atype
;
1711 struct neon_type_el parsetype
;
1715 atype
.eltype
.type
= NT_invtype
;
1716 atype
.eltype
.size
= -1;
1718 /* Try alternate syntax for some types of register. Note these are mutually
1719 exclusive with the Neon syntax extensions. */
1722 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1730 /* Undo polymorphism when a set of register types may be accepted. */
1731 if ((type
== REG_TYPE_NDQ
1732 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1733 || (type
== REG_TYPE_VFSD
1734 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1735 || (type
== REG_TYPE_NSDQ
1736 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1737 || reg
->type
== REG_TYPE_NQ
))
1738 || (type
== REG_TYPE_NSD
1739 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1740 || (type
== REG_TYPE_MMXWC
1741 && (reg
->type
== REG_TYPE_MMXWCG
)))
1742 type
= (enum arm_reg_type
) reg
->type
;
1744 if (type
== REG_TYPE_MQ
)
1746 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1749 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1752 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1754 first_error (_("expected MVE register [q0..q7]"));
1759 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1760 && (type
== REG_TYPE_NQ
))
1764 if (type
!= reg
->type
)
1770 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1772 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1774 first_error (_("can't redefine type for operand"));
1777 atype
.defined
|= NTA_HASTYPE
;
1778 atype
.eltype
= parsetype
;
1781 if (skip_past_char (&str
, '[') == SUCCESS
)
1783 if (type
!= REG_TYPE_VFD
1784 && !(type
== REG_TYPE_VFS
1785 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1786 && !(type
== REG_TYPE_NQ
1787 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1789 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1790 first_error (_("only D and Q registers may be indexed"));
1792 first_error (_("only D registers may be indexed"));
1796 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1798 first_error (_("can't change index for operand"));
1802 atype
.defined
|= NTA_HASINDEX
;
1804 if (skip_past_char (&str
, ']') == SUCCESS
)
1805 atype
.index
= NEON_ALL_LANES
;
1810 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1812 if (exp
.X_op
!= O_constant
)
1814 first_error (_("constant expression required"));
1818 if (skip_past_char (&str
, ']') == FAIL
)
1821 atype
.index
= exp
.X_add_number
;
1836 /* Like arm_reg_parse, but also allow the following extra features:
1837 - If RTYPE is non-zero, return the (possibly restricted) type of the
1838 register (e.g. Neon double or quad reg when either has been requested).
1839 - If this is a Neon vector type with additional type information, fill
1840 in the struct pointed to by VECTYPE (if non-NULL).
1841 This function will fault on encountering a scalar. */
1844 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1845 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1847 struct neon_typed_alias atype
;
1849 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1854 /* Do not allow regname(... to parse as a register. */
1858 /* Do not allow a scalar (reg+index) to parse as a register. */
1859 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1861 first_error (_("register operand expected, but got scalar"));
1866 *vectype
= atype
.eltype
;
1873 #define NEON_SCALAR_REG(X) ((X) >> 4)
1874 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1876 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1877 have enough information to be able to do a good job bounds-checking. So, we
1878 just do easy checks here, and do further checks later. */
1881 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1882 arm_reg_type reg_type
)
1886 struct neon_typed_alias atype
;
1889 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1907 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1910 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1912 first_error (_("scalar must have an index"));
1915 else if (atype
.index
>= reg_size
/ elsize
)
1917 first_error (_("scalar index out of range"));
1922 *type
= atype
.eltype
;
1926 return reg
* 16 + atype
.index
;
1929 /* Types of registers in a list. */
1942 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1945 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1951 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1953 /* We come back here if we get ranges concatenated by '+' or '|'. */
1956 skip_whitespace (str
);
1969 const char apsr_str
[] = "apsr";
1970 int apsr_str_len
= strlen (apsr_str
);
1972 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1973 if (etype
== REGLIST_CLRM
)
1975 if (reg
== REG_SP
|| reg
== REG_PC
)
1977 else if (reg
== FAIL
1978 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1979 && !ISALPHA (*(str
+ apsr_str_len
)))
1982 str
+= apsr_str_len
;
1987 first_error (_("r0-r12, lr or APSR expected"));
1991 else /* etype == REGLIST_RN. */
1995 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2006 first_error (_("bad range in register list"));
2010 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2012 if (range
& (1 << i
))
2014 (_("Warning: duplicated register (r%d) in register list"),
2022 if (range
& (1 << reg
))
2023 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2025 else if (reg
<= cur_reg
)
2026 as_tsktsk (_("Warning: register range not in ascending order"));
2031 while (skip_past_comma (&str
) != FAIL
2032 || (in_range
= 1, *str
++ == '-'));
2035 if (skip_past_char (&str
, '}') == FAIL
)
2037 first_error (_("missing `}'"));
2041 else if (etype
== REGLIST_RN
)
2045 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2048 if (exp
.X_op
== O_constant
)
2050 if (exp
.X_add_number
2051 != (exp
.X_add_number
& 0x0000ffff))
2053 inst
.error
= _("invalid register mask");
2057 if ((range
& exp
.X_add_number
) != 0)
2059 int regno
= range
& exp
.X_add_number
;
2062 regno
= (1 << regno
) - 1;
2064 (_("Warning: duplicated register (r%d) in register list"),
2068 range
|= exp
.X_add_number
;
2072 if (inst
.relocs
[0].type
!= 0)
2074 inst
.error
= _("expression too complex");
2078 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2080 inst
.relocs
[0].pc_rel
= 0;
2084 if (*str
== '|' || *str
== '+')
2090 while (another_range
);
2096 /* Parse a VFP register list. If the string is invalid return FAIL.
2097 Otherwise return the number of registers, and set PBASE to the first
2098 register. Parses registers of type ETYPE.
2099 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2100 - Q registers can be used to specify pairs of D registers
2101 - { } can be omitted from around a singleton register list
2102 FIXME: This is not implemented, as it would require backtracking in
2105 This could be done (the meaning isn't really ambiguous), but doesn't
2106 fit in well with the current parsing framework.
2107 - 32 D registers may be used (also true for VFPv3).
2108 FIXME: Types are ignored in these register lists, which is probably a
2112 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2113 bfd_boolean
*partial_match
)
2118 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2122 unsigned long mask
= 0;
2124 bfd_boolean vpr_seen
= FALSE
;
2125 bfd_boolean expect_vpr
=
2126 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2128 if (skip_past_char (&str
, '{') == FAIL
)
2130 inst
.error
= _("expecting {");
2137 case REGLIST_VFP_S_VPR
:
2138 regtype
= REG_TYPE_VFS
;
2143 case REGLIST_VFP_D_VPR
:
2144 regtype
= REG_TYPE_VFD
;
2147 case REGLIST_NEON_D
:
2148 regtype
= REG_TYPE_NDQ
;
2155 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2157 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2158 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2162 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2165 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2172 base_reg
= max_regs
;
2173 *partial_match
= FALSE
;
2177 int setmask
= 1, addregs
= 1;
2178 const char vpr_str
[] = "vpr";
2179 int vpr_str_len
= strlen (vpr_str
);
2181 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2185 if (new_base
== FAIL
2186 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2187 && !ISALPHA (*(str
+ vpr_str_len
))
2193 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2197 first_error (_("VPR expected last"));
2200 else if (new_base
== FAIL
)
2202 if (regtype
== REG_TYPE_VFS
)
2203 first_error (_("VFP single precision register or VPR "
2205 else /* regtype == REG_TYPE_VFD. */
2206 first_error (_("VFP/Neon double precision register or VPR "
2211 else if (new_base
== FAIL
)
2213 first_error (_(reg_expected_msgs
[regtype
]));
2217 *partial_match
= TRUE
;
2221 if (new_base
>= max_regs
)
2223 first_error (_("register out of range in list"));
2227 /* Note: a value of 2 * n is returned for the register Q<n>. */
2228 if (regtype
== REG_TYPE_NQ
)
2234 if (new_base
< base_reg
)
2235 base_reg
= new_base
;
2237 if (mask
& (setmask
<< new_base
))
2239 first_error (_("invalid register list"));
2243 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2245 as_tsktsk (_("register list not in ascending order"));
2249 mask
|= setmask
<< new_base
;
2252 if (*str
== '-') /* We have the start of a range expression */
2258 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2261 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2265 if (high_range
>= max_regs
)
2267 first_error (_("register out of range in list"));
2271 if (regtype
== REG_TYPE_NQ
)
2272 high_range
= high_range
+ 1;
2274 if (high_range
<= new_base
)
2276 inst
.error
= _("register range not in ascending order");
2280 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2282 if (mask
& (setmask
<< new_base
))
2284 inst
.error
= _("invalid register list");
2288 mask
|= setmask
<< new_base
;
2293 while (skip_past_comma (&str
) != FAIL
);
2297 /* Sanity check -- should have raised a parse error above. */
2298 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2303 if (expect_vpr
&& !vpr_seen
)
2305 first_error (_("VPR expected last"));
2309 /* Final test -- the registers must be consecutive. */
2311 for (i
= 0; i
< count
; i
++)
2313 if ((mask
& (1u << i
)) == 0)
2315 inst
.error
= _("non-contiguous register range");
2325 /* True if two alias types are the same. */
2328 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2336 if (a
->defined
!= b
->defined
)
2339 if ((a
->defined
& NTA_HASTYPE
) != 0
2340 && (a
->eltype
.type
!= b
->eltype
.type
2341 || a
->eltype
.size
!= b
->eltype
.size
))
2344 if ((a
->defined
& NTA_HASINDEX
) != 0
2345 && (a
->index
!= b
->index
))
2351 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2352 The base register is put in *PBASE.
2353 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2355 The register stride (minus one) is put in bit 4 of the return value.
2356 Bits [6:5] encode the list length (minus one).
2357 The type of the list elements is put in *ELTYPE, if non-NULL. */
2359 #define NEON_LANE(X) ((X) & 0xf)
2360 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2361 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2364 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2366 struct neon_type_el
*eltype
)
2373 int leading_brace
= 0;
2374 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2375 const char *const incr_error
= mve
? _("register stride must be 1") :
2376 _("register stride must be 1 or 2");
2377 const char *const type_error
= _("mismatched element/structure types in list");
2378 struct neon_typed_alias firsttype
;
2379 firsttype
.defined
= 0;
2380 firsttype
.eltype
.type
= NT_invtype
;
2381 firsttype
.eltype
.size
= -1;
2382 firsttype
.index
= -1;
2384 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2389 struct neon_typed_alias atype
;
2391 rtype
= REG_TYPE_MQ
;
2392 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2396 first_error (_(reg_expected_msgs
[rtype
]));
2403 if (rtype
== REG_TYPE_NQ
)
2409 else if (reg_incr
== -1)
2411 reg_incr
= getreg
- base_reg
;
2412 if (reg_incr
< 1 || reg_incr
> 2)
2414 first_error (_(incr_error
));
2418 else if (getreg
!= base_reg
+ reg_incr
* count
)
2420 first_error (_(incr_error
));
2424 if (! neon_alias_types_same (&atype
, &firsttype
))
2426 first_error (_(type_error
));
2430 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2434 struct neon_typed_alias htype
;
2435 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2437 lane
= NEON_INTERLEAVE_LANES
;
2438 else if (lane
!= NEON_INTERLEAVE_LANES
)
2440 first_error (_(type_error
));
2445 else if (reg_incr
!= 1)
2447 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2451 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2454 first_error (_(reg_expected_msgs
[rtype
]));
2457 if (! neon_alias_types_same (&htype
, &firsttype
))
2459 first_error (_(type_error
));
2462 count
+= hireg
+ dregs
- getreg
;
2466 /* If we're using Q registers, we can't use [] or [n] syntax. */
2467 if (rtype
== REG_TYPE_NQ
)
2473 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2477 else if (lane
!= atype
.index
)
2479 first_error (_(type_error
));
2483 else if (lane
== -1)
2484 lane
= NEON_INTERLEAVE_LANES
;
2485 else if (lane
!= NEON_INTERLEAVE_LANES
)
2487 first_error (_(type_error
));
2492 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2494 /* No lane set by [x]. We must be interleaving structures. */
2496 lane
= NEON_INTERLEAVE_LANES
;
2499 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2500 || (count
> 1 && reg_incr
== -1))
2502 first_error (_("error parsing element/structure list"));
2506 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2508 first_error (_("expected }"));
2516 *eltype
= firsttype
.eltype
;
2521 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2524 /* Parse an explicit relocation suffix on an expression. This is
2525 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2526 arm_reloc_hsh contains no entries, so this function can only
2527 succeed if there is no () after the word. Returns -1 on error,
2528 BFD_RELOC_UNUSED if there wasn't any suffix. */
2531 parse_reloc (char **str
)
2533 struct reloc_entry
*r
;
2537 return BFD_RELOC_UNUSED
;
2542 while (*q
&& *q
!= ')' && *q
!= ',')
2547 if ((r
= (struct reloc_entry
*)
2548 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2555 /* Directives: register aliases. */
2557 static struct reg_entry
*
2558 insert_reg_alias (char *str
, unsigned number
, int type
)
2560 struct reg_entry
*new_reg
;
2563 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2565 if (new_reg
->builtin
)
2566 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2568 /* Only warn about a redefinition if it's not defined as the
2570 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2571 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2576 name
= xstrdup (str
);
2577 new_reg
= XNEW (struct reg_entry
);
2579 new_reg
->name
= name
;
2580 new_reg
->number
= number
;
2581 new_reg
->type
= type
;
2582 new_reg
->builtin
= FALSE
;
2583 new_reg
->neon
= NULL
;
2585 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 hash_delete (arm_reg_hsh
, name
, FALSE
);
2900 free ((char *) reg
->name
);
2905 /* Also locate the all upper case and all lower case versions.
2906 Do not complain if we cannot find one or the other as it
2907 was probably deleted above. */
2909 nbuf
= strdup (name
);
2910 for (p
= nbuf
; *p
; p
++)
2912 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2915 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2916 free ((char *) reg
->name
);
2922 for (p
= nbuf
; *p
; p
++)
2924 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2927 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2928 free ((char *) reg
->name
);
2938 *input_line_pointer
= saved_char
;
2939 demand_empty_rest_of_line ();
2942 /* Directives: Instruction set selection. */
2945 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2946 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2947 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2948 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2950 /* Create a new mapping symbol for the transition to STATE. */
2953 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2956 const char * symname
;
2963 type
= BSF_NO_FLAGS
;
2967 type
= BSF_NO_FLAGS
;
2971 type
= BSF_NO_FLAGS
;
2977 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2978 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2983 THUMB_SET_FUNC (symbolP
, 0);
2984 ARM_SET_THUMB (symbolP
, 0);
2985 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2989 THUMB_SET_FUNC (symbolP
, 1);
2990 ARM_SET_THUMB (symbolP
, 1);
2991 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2999 /* Save the mapping symbols for future reference. Also check that
3000 we do not place two mapping symbols at the same offset within a
3001 frag. We'll handle overlap between frags in
3002 check_mapping_symbols.
3004 If .fill or other data filling directive generates zero sized data,
3005 the mapping symbol for the following code will have the same value
3006 as the one generated for the data filling directive. In this case,
3007 we replace the old symbol with the new one at the same address. */
3010 if (frag
->tc_frag_data
.first_map
!= NULL
)
3012 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3013 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3015 frag
->tc_frag_data
.first_map
= symbolP
;
3017 if (frag
->tc_frag_data
.last_map
!= NULL
)
3019 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3020 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3021 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3023 frag
->tc_frag_data
.last_map
= symbolP
;
3026 /* We must sometimes convert a region marked as code to data during
3027 code alignment, if an odd number of bytes have to be padded. The
3028 code mapping symbol is pushed to an aligned address. */
3031 insert_data_mapping_symbol (enum mstate state
,
3032 valueT value
, fragS
*frag
, offsetT bytes
)
3034 /* If there was already a mapping symbol, remove it. */
3035 if (frag
->tc_frag_data
.last_map
!= NULL
3036 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3038 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3042 know (frag
->tc_frag_data
.first_map
== symp
);
3043 frag
->tc_frag_data
.first_map
= NULL
;
3045 frag
->tc_frag_data
.last_map
= NULL
;
3046 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3049 make_mapping_symbol (MAP_DATA
, value
, frag
);
3050 make_mapping_symbol (state
, value
+ bytes
, frag
);
3053 static void mapping_state_2 (enum mstate state
, int max_chars
);
3055 /* Set the mapping state to STATE. Only call this when about to
3056 emit some STATE bytes to the file. */
3058 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3060 mapping_state (enum mstate state
)
3062 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3064 if (mapstate
== state
)
3065 /* The mapping symbol has already been emitted.
3066 There is nothing else to do. */
3069 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3071 All ARM instructions require 4-byte alignment.
3072 (Almost) all Thumb instructions require 2-byte alignment.
3074 When emitting instructions into any section, mark the section
3077 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3078 but themselves require 2-byte alignment; this applies to some
3079 PC- relative forms. However, these cases will involve implicit
3080 literal pool generation or an explicit .align >=2, both of
3081 which will cause the section to me marked with sufficient
3082 alignment. Thus, we don't handle those cases here. */
3083 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3085 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3086 /* This case will be evaluated later. */
3089 mapping_state_2 (state
, 0);
3092 /* Same as mapping_state, but MAX_CHARS bytes have already been
3093 allocated. Put the mapping symbol that far back. */
3096 mapping_state_2 (enum mstate state
, int max_chars
)
3098 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3100 if (!SEG_NORMAL (now_seg
))
3103 if (mapstate
== state
)
3104 /* The mapping symbol has already been emitted.
3105 There is nothing else to do. */
3108 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3109 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3111 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3112 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3115 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3118 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3119 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3123 #define mapping_state(x) ((void)0)
3124 #define mapping_state_2(x, y) ((void)0)
3127 /* Find the real, Thumb encoded start of a Thumb function. */
3131 find_real_start (symbolS
* symbolP
)
3134 const char * name
= S_GET_NAME (symbolP
);
3135 symbolS
* new_target
;
3137 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3138 #define STUB_NAME ".real_start_of"
3143 /* The compiler may generate BL instructions to local labels because
3144 it needs to perform a branch to a far away location. These labels
3145 do not have a corresponding ".real_start_of" label. We check
3146 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3147 the ".real_start_of" convention for nonlocal branches. */
3148 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3151 real_start
= concat (STUB_NAME
, name
, NULL
);
3152 new_target
= symbol_find (real_start
);
3155 if (new_target
== NULL
)
3157 as_warn (_("Failed to find real start of function: %s\n"), name
);
3158 new_target
= symbolP
;
3166 opcode_select (int width
)
3173 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3174 as_bad (_("selected processor does not support THUMB opcodes"));
3177 /* No need to force the alignment, since we will have been
3178 coming from ARM mode, which is word-aligned. */
3179 record_alignment (now_seg
, 1);
3186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3187 as_bad (_("selected processor does not support ARM opcodes"));
3192 frag_align (2, 0, 0);
3194 record_alignment (now_seg
, 1);
3199 as_bad (_("invalid instruction size selected (%d)"), width
);
3204 s_arm (int ignore ATTRIBUTE_UNUSED
)
3207 demand_empty_rest_of_line ();
3211 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3214 demand_empty_rest_of_line ();
3218 s_code (int unused ATTRIBUTE_UNUSED
)
3222 temp
= get_absolute_expression ();
3227 opcode_select (temp
);
3231 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3236 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3238 /* If we are not already in thumb mode go into it, EVEN if
3239 the target processor does not support thumb instructions.
3240 This is used by gcc/config/arm/lib1funcs.asm for example
3241 to compile interworking support functions even if the
3242 target processor should not support interworking. */
3246 record_alignment (now_seg
, 1);
3249 demand_empty_rest_of_line ();
3253 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3257 /* The following label is the name/address of the start of a Thumb function.
3258 We need to know this for the interworking support. */
3259 label_is_thumb_function_name
= TRUE
;
3262 /* Perform a .set directive, but also mark the alias as
3263 being a thumb function. */
3266 s_thumb_set (int equiv
)
3268 /* XXX the following is a duplicate of the code for s_set() in read.c
3269 We cannot just call that code as we need to get at the symbol that
3276 /* Especial apologies for the random logic:
3277 This just grew, and could be parsed much more simply!
3279 delim
= get_symbol_name (& name
);
3280 end_name
= input_line_pointer
;
3281 (void) restore_line_pointer (delim
);
3283 if (*input_line_pointer
!= ',')
3286 as_bad (_("expected comma after name \"%s\""), name
);
3288 ignore_rest_of_line ();
3292 input_line_pointer
++;
3295 if (name
[0] == '.' && name
[1] == '\0')
3297 /* XXX - this should not happen to .thumb_set. */
3301 if ((symbolP
= symbol_find (name
)) == NULL
3302 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3305 /* When doing symbol listings, play games with dummy fragments living
3306 outside the normal fragment chain to record the file and line info
3308 if (listing
& LISTING_SYMBOLS
)
3310 extern struct list_info_struct
* listing_tail
;
3311 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3313 memset (dummy_frag
, 0, sizeof (fragS
));
3314 dummy_frag
->fr_type
= rs_fill
;
3315 dummy_frag
->line
= listing_tail
;
3316 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3317 dummy_frag
->fr_symbol
= symbolP
;
3321 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3324 /* "set" symbols are local unless otherwise specified. */
3325 SF_SET_LOCAL (symbolP
);
3326 #endif /* OBJ_COFF */
3327 } /* Make a new symbol. */
3329 symbol_table_insert (symbolP
);
3334 && S_IS_DEFINED (symbolP
)
3335 && S_GET_SEGMENT (symbolP
) != reg_section
)
3336 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3338 pseudo_set (symbolP
);
3340 demand_empty_rest_of_line ();
3342 /* XXX Now we come to the Thumb specific bit of code. */
3344 THUMB_SET_FUNC (symbolP
, 1);
3345 ARM_SET_THUMB (symbolP
, 1);
3346 #if defined OBJ_ELF || defined OBJ_COFF
3347 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3351 /* Directives: Mode selection. */
3353 /* .syntax [unified|divided] - choose the new unified syntax
3354 (same for Arm and Thumb encoding, modulo slight differences in what
3355 can be represented) or the old divergent syntax for each mode. */
3357 s_syntax (int unused ATTRIBUTE_UNUSED
)
3361 delim
= get_symbol_name (& name
);
3363 if (!strcasecmp (name
, "unified"))
3364 unified_syntax
= TRUE
;
3365 else if (!strcasecmp (name
, "divided"))
3366 unified_syntax
= FALSE
;
3369 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3372 (void) restore_line_pointer (delim
);
3373 demand_empty_rest_of_line ();
3376 /* Directives: sectioning and alignment. */
3379 s_bss (int ignore ATTRIBUTE_UNUSED
)
3381 /* We don't support putting frags in the BSS segment, we fake it by
3382 marking in_bss, then looking at s_skip for clues. */
3383 subseg_set (bss_section
, 0);
3384 demand_empty_rest_of_line ();
3386 #ifdef md_elf_section_change_hook
3387 md_elf_section_change_hook ();
3392 s_even (int ignore ATTRIBUTE_UNUSED
)
3394 /* Never make frag if expect extra pass. */
3396 frag_align (1, 0, 0);
3398 record_alignment (now_seg
, 1);
3400 demand_empty_rest_of_line ();
3403 /* Directives: CodeComposer Studio. */
3405 /* .ref (for CodeComposer Studio syntax only). */
3407 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3409 if (codecomposer_syntax
)
3410 ignore_rest_of_line ();
3412 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3415 /* If name is not NULL, then it is used for marking the beginning of a
3416 function, whereas if it is NULL then it means the function end. */
3418 asmfunc_debug (const char * name
)
3420 static const char * last_name
= NULL
;
3424 gas_assert (last_name
== NULL
);
3427 if (debug_type
== DEBUG_STABS
)
3428 stabs_generate_asm_func (name
, name
);
3432 gas_assert (last_name
!= NULL
);
3434 if (debug_type
== DEBUG_STABS
)
3435 stabs_generate_asm_endfunc (last_name
, last_name
);
3442 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3444 if (codecomposer_syntax
)
3446 switch (asmfunc_state
)
3448 case OUTSIDE_ASMFUNC
:
3449 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3452 case WAITING_ASMFUNC_NAME
:
3453 as_bad (_(".asmfunc repeated."));
3456 case WAITING_ENDASMFUNC
:
3457 as_bad (_(".asmfunc without function."));
3460 demand_empty_rest_of_line ();
3463 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3467 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3469 if (codecomposer_syntax
)
3471 switch (asmfunc_state
)
3473 case OUTSIDE_ASMFUNC
:
3474 as_bad (_(".endasmfunc without a .asmfunc."));
3477 case WAITING_ASMFUNC_NAME
:
3478 as_bad (_(".endasmfunc without function."));
3481 case WAITING_ENDASMFUNC
:
3482 asmfunc_state
= OUTSIDE_ASMFUNC
;
3483 asmfunc_debug (NULL
);
3486 demand_empty_rest_of_line ();
3489 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3493 s_ccs_def (int name
)
3495 if (codecomposer_syntax
)
3498 as_bad (_(".def pseudo-op only available with -mccs flag."));
3501 /* Directives: Literal pools. */
3503 static literal_pool
*
3504 find_literal_pool (void)
3506 literal_pool
* pool
;
3508 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3510 if (pool
->section
== now_seg
3511 && pool
->sub_section
== now_subseg
)
3518 static literal_pool
*
3519 find_or_make_literal_pool (void)
3521 /* Next literal pool ID number. */
3522 static unsigned int latest_pool_num
= 1;
3523 literal_pool
* pool
;
3525 pool
= find_literal_pool ();
3529 /* Create a new pool. */
3530 pool
= XNEW (literal_pool
);
3534 pool
->next_free_entry
= 0;
3535 pool
->section
= now_seg
;
3536 pool
->sub_section
= now_subseg
;
3537 pool
->next
= list_of_pools
;
3538 pool
->symbol
= NULL
;
3539 pool
->alignment
= 2;
3541 /* Add it to the list. */
3542 list_of_pools
= pool
;
3545 /* New pools, and emptied pools, will have a NULL symbol. */
3546 if (pool
->symbol
== NULL
)
3548 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3549 (valueT
) 0, &zero_address_frag
);
3550 pool
->id
= latest_pool_num
++;
3557 /* Add the literal in the global 'inst'
3558 structure to the relevant literal pool. */
3561 add_to_lit_pool (unsigned int nbytes
)
3563 #define PADDING_SLOT 0x1
3564 #define LIT_ENTRY_SIZE_MASK 0xFF
3565 literal_pool
* pool
;
3566 unsigned int entry
, pool_size
= 0;
3567 bfd_boolean padding_slot_p
= FALSE
;
3573 imm1
= inst
.operands
[1].imm
;
3574 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3575 : inst
.relocs
[0].exp
.X_unsigned
? 0
3576 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3577 if (target_big_endian
)
3580 imm2
= inst
.operands
[1].imm
;
3584 pool
= find_or_make_literal_pool ();
3586 /* Check if this literal value is already in the pool. */
3587 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3591 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3592 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3593 && (pool
->literals
[entry
].X_add_number
3594 == inst
.relocs
[0].exp
.X_add_number
)
3595 && (pool
->literals
[entry
].X_md
== nbytes
)
3596 && (pool
->literals
[entry
].X_unsigned
3597 == inst
.relocs
[0].exp
.X_unsigned
))
3600 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3601 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3602 && (pool
->literals
[entry
].X_add_number
3603 == inst
.relocs
[0].exp
.X_add_number
)
3604 && (pool
->literals
[entry
].X_add_symbol
3605 == inst
.relocs
[0].exp
.X_add_symbol
)
3606 && (pool
->literals
[entry
].X_op_symbol
3607 == inst
.relocs
[0].exp
.X_op_symbol
)
3608 && (pool
->literals
[entry
].X_md
== nbytes
))
3611 else if ((nbytes
== 8)
3612 && !(pool_size
& 0x7)
3613 && ((entry
+ 1) != pool
->next_free_entry
)
3614 && (pool
->literals
[entry
].X_op
== O_constant
)
3615 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3616 && (pool
->literals
[entry
].X_unsigned
3617 == inst
.relocs
[0].exp
.X_unsigned
)
3618 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3619 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3620 && (pool
->literals
[entry
+ 1].X_unsigned
3621 == inst
.relocs
[0].exp
.X_unsigned
))
3624 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3625 if (padding_slot_p
&& (nbytes
== 4))
3631 /* Do we need to create a new entry? */
3632 if (entry
== pool
->next_free_entry
)
3634 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3636 inst
.error
= _("literal pool overflow");
3642 /* For 8-byte entries, we align to an 8-byte boundary,
3643 and split it into two 4-byte entries, because on 32-bit
3644 host, 8-byte constants are treated as big num, thus
3645 saved in "generic_bignum" which will be overwritten
3646 by later assignments.
3648 We also need to make sure there is enough space for
3651 We also check to make sure the literal operand is a
3653 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3654 || inst
.relocs
[0].exp
.X_op
== O_big
))
3656 inst
.error
= _("invalid type for literal pool");
3659 else if (pool_size
& 0x7)
3661 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3663 inst
.error
= _("literal pool overflow");
3667 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3668 pool
->literals
[entry
].X_op
= O_constant
;
3669 pool
->literals
[entry
].X_add_number
= 0;
3670 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3671 pool
->next_free_entry
+= 1;
3674 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3676 inst
.error
= _("literal pool overflow");
3680 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3681 pool
->literals
[entry
].X_op
= O_constant
;
3682 pool
->literals
[entry
].X_add_number
= imm1
;
3683 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3684 pool
->literals
[entry
++].X_md
= 4;
3685 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3686 pool
->literals
[entry
].X_op
= O_constant
;
3687 pool
->literals
[entry
].X_add_number
= imm2
;
3688 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3689 pool
->literals
[entry
].X_md
= 4;
3690 pool
->alignment
= 3;
3691 pool
->next_free_entry
+= 1;
3695 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3696 pool
->literals
[entry
].X_md
= 4;
3700 /* PR ld/12974: Record the location of the first source line to reference
3701 this entry in the literal pool. If it turns out during linking that the
3702 symbol does not exist we will be able to give an accurate line number for
3703 the (first use of the) missing reference. */
3704 if (debug_type
== DEBUG_DWARF2
)
3705 dwarf2_where (pool
->locs
+ entry
);
3707 pool
->next_free_entry
+= 1;
3709 else if (padding_slot_p
)
3711 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3712 pool
->literals
[entry
].X_md
= nbytes
;
3715 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3716 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3717 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3723 tc_start_label_without_colon (void)
3725 bfd_boolean ret
= TRUE
;
3727 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3729 const char *label
= input_line_pointer
;
3731 while (!is_end_of_line
[(int) label
[-1]])
3736 as_bad (_("Invalid label '%s'"), label
);
3740 asmfunc_debug (label
);
3742 asmfunc_state
= WAITING_ENDASMFUNC
;
3748 /* Can't use symbol_new here, so have to create a symbol and then at
3749 a later date assign it a value. That's what these functions do. */
3752 symbol_locate (symbolS
* symbolP
,
3753 const char * name
, /* It is copied, the caller can modify. */
3754 segT segment
, /* Segment identifier (SEG_<something>). */
3755 valueT valu
, /* Symbol value. */
3756 fragS
* frag
) /* Associated fragment. */
3759 char * preserved_copy_of_name
;
3761 name_length
= strlen (name
) + 1; /* +1 for \0. */
3762 obstack_grow (¬es
, name
, name_length
);
3763 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3765 #ifdef tc_canonicalize_symbol_name
3766 preserved_copy_of_name
=
3767 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3770 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3772 S_SET_SEGMENT (symbolP
, segment
);
3773 S_SET_VALUE (symbolP
, valu
);
3774 symbol_clear_list_pointers (symbolP
);
3776 symbol_set_frag (symbolP
, frag
);
3778 /* Link to end of symbol chain. */
3780 extern int symbol_table_frozen
;
3782 if (symbol_table_frozen
)
3786 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3788 obj_symbol_new_hook (symbolP
);
3790 #ifdef tc_symbol_new_hook
3791 tc_symbol_new_hook (symbolP
);
3795 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3796 #endif /* DEBUG_SYMS */
3800 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3803 literal_pool
* pool
;
3806 pool
= find_literal_pool ();
3808 || pool
->symbol
== NULL
3809 || pool
->next_free_entry
== 0)
3812 /* Align pool as you have word accesses.
3813 Only make a frag if we have to. */
3815 frag_align (pool
->alignment
, 0, 0);
3817 record_alignment (now_seg
, 2);
3820 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3821 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3823 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3825 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3826 (valueT
) frag_now_fix (), frag_now
);
3827 symbol_table_insert (pool
->symbol
);
3829 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3831 #if defined OBJ_COFF || defined OBJ_ELF
3832 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3835 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3838 if (debug_type
== DEBUG_DWARF2
)
3839 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3841 /* First output the expression in the instruction to the pool. */
3842 emit_expr (&(pool
->literals
[entry
]),
3843 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3846 /* Mark the pool as empty. */
3847 pool
->next_free_entry
= 0;
3848 pool
->symbol
= NULL
;
3852 /* Forward declarations for functions below, in the MD interface
3854 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3855 static valueT
create_unwind_entry (int);
3856 static void start_unwind_section (const segT
, int);
3857 static void add_unwind_opcode (valueT
, int);
3858 static void flush_pending_unwind (void);
3860 /* Directives: Data. */
3863 s_arm_elf_cons (int nbytes
)
3867 #ifdef md_flush_pending_output
3868 md_flush_pending_output ();
3871 if (is_it_end_of_statement ())
3873 demand_empty_rest_of_line ();
3877 #ifdef md_cons_align
3878 md_cons_align (nbytes
);
3881 mapping_state (MAP_DATA
);
3885 char *base
= input_line_pointer
;
3889 if (exp
.X_op
!= O_symbol
)
3890 emit_expr (&exp
, (unsigned int) nbytes
);
3893 char *before_reloc
= input_line_pointer
;
3894 reloc
= parse_reloc (&input_line_pointer
);
3897 as_bad (_("unrecognized relocation suffix"));
3898 ignore_rest_of_line ();
3901 else if (reloc
== BFD_RELOC_UNUSED
)
3902 emit_expr (&exp
, (unsigned int) nbytes
);
3905 reloc_howto_type
*howto
= (reloc_howto_type
*)
3906 bfd_reloc_type_lookup (stdoutput
,
3907 (bfd_reloc_code_real_type
) reloc
);
3908 int size
= bfd_get_reloc_size (howto
);
3910 if (reloc
== BFD_RELOC_ARM_PLT32
)
3912 as_bad (_("(plt) is only valid on branch targets"));
3913 reloc
= BFD_RELOC_UNUSED
;
3918 as_bad (ngettext ("%s relocations do not fit in %d byte",
3919 "%s relocations do not fit in %d bytes",
3921 howto
->name
, nbytes
);
3924 /* We've parsed an expression stopping at O_symbol.
3925 But there may be more expression left now that we
3926 have parsed the relocation marker. Parse it again.
3927 XXX Surely there is a cleaner way to do this. */
3928 char *p
= input_line_pointer
;
3930 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3932 memcpy (save_buf
, base
, input_line_pointer
- base
);
3933 memmove (base
+ (input_line_pointer
- before_reloc
),
3934 base
, before_reloc
- base
);
3936 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3938 memcpy (base
, save_buf
, p
- base
);
3940 offset
= nbytes
- size
;
3941 p
= frag_more (nbytes
);
3942 memset (p
, 0, nbytes
);
3943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3944 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3950 while (*input_line_pointer
++ == ',');
3952 /* Put terminator back into stream. */
3953 input_line_pointer
--;
3954 demand_empty_rest_of_line ();
3957 /* Emit an expression containing a 32-bit thumb instruction.
3958 Implementation based on put_thumb32_insn. */
3961 emit_thumb32_expr (expressionS
* exp
)
3963 expressionS exp_high
= *exp
;
3965 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3966 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3967 exp
->X_add_number
&= 0xffff;
3968 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3971 /* Guess the instruction size based on the opcode. */
3974 thumb_insn_size (int opcode
)
3976 if ((unsigned int) opcode
< 0xe800u
)
3978 else if ((unsigned int) opcode
>= 0xe8000000u
)
3985 emit_insn (expressionS
*exp
, int nbytes
)
3989 if (exp
->X_op
== O_constant
)
3994 size
= thumb_insn_size (exp
->X_add_number
);
3998 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
4000 as_bad (_(".inst.n operand too big. "\
4001 "Use .inst.w instead"));
4006 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4007 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4009 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4011 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4012 emit_thumb32_expr (exp
);
4014 emit_expr (exp
, (unsigned int) size
);
4016 it_fsm_post_encode ();
4020 as_bad (_("cannot determine Thumb instruction size. " \
4021 "Use .inst.n/.inst.w instead"));
4024 as_bad (_("constant expression required"));
4029 /* Like s_arm_elf_cons but do not use md_cons_align and
4030 set the mapping state to MAP_ARM/MAP_THUMB. */
4033 s_arm_elf_inst (int nbytes
)
4035 if (is_it_end_of_statement ())
4037 demand_empty_rest_of_line ();
4041 /* Calling mapping_state () here will not change ARM/THUMB,
4042 but will ensure not to be in DATA state. */
4045 mapping_state (MAP_THUMB
);
4050 as_bad (_("width suffixes are invalid in ARM mode"));
4051 ignore_rest_of_line ();
4057 mapping_state (MAP_ARM
);
4066 if (! emit_insn (& exp
, nbytes
))
4068 ignore_rest_of_line ();
4072 while (*input_line_pointer
++ == ',');
4074 /* Put terminator back into stream. */
4075 input_line_pointer
--;
4076 demand_empty_rest_of_line ();
4079 /* Parse a .rel31 directive. */
4082 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4089 if (*input_line_pointer
== '1')
4090 highbit
= 0x80000000;
4091 else if (*input_line_pointer
!= '0')
4092 as_bad (_("expected 0 or 1"));
4094 input_line_pointer
++;
4095 if (*input_line_pointer
!= ',')
4096 as_bad (_("missing comma"));
4097 input_line_pointer
++;
4099 #ifdef md_flush_pending_output
4100 md_flush_pending_output ();
4103 #ifdef md_cons_align
4107 mapping_state (MAP_DATA
);
4112 md_number_to_chars (p
, highbit
, 4);
4113 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4114 BFD_RELOC_ARM_PREL31
);
4116 demand_empty_rest_of_line ();
4119 /* Directives: AEABI stack-unwind tables. */
4121 /* Parse an unwind_fnstart directive. Simply records the current location. */
4124 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4126 demand_empty_rest_of_line ();
4127 if (unwind
.proc_start
)
4129 as_bad (_("duplicate .fnstart directive"));
4133 /* Mark the start of the function. */
4134 unwind
.proc_start
= expr_build_dot ();
4136 /* Reset the rest of the unwind info. */
4137 unwind
.opcode_count
= 0;
4138 unwind
.table_entry
= NULL
;
4139 unwind
.personality_routine
= NULL
;
4140 unwind
.personality_index
= -1;
4141 unwind
.frame_size
= 0;
4142 unwind
.fp_offset
= 0;
4143 unwind
.fp_reg
= REG_SP
;
4145 unwind
.sp_restored
= 0;
4149 /* Parse a handlerdata directive. Creates the exception handling table entry
4150 for the function. */
4153 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4155 demand_empty_rest_of_line ();
4156 if (!unwind
.proc_start
)
4157 as_bad (MISSING_FNSTART
);
4159 if (unwind
.table_entry
)
4160 as_bad (_("duplicate .handlerdata directive"));
4162 create_unwind_entry (1);
4165 /* Parse an unwind_fnend directive. Generates the index table entry. */
4168 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4173 unsigned int marked_pr_dependency
;
4175 demand_empty_rest_of_line ();
4177 if (!unwind
.proc_start
)
4179 as_bad (_(".fnend directive without .fnstart"));
4183 /* Add eh table entry. */
4184 if (unwind
.table_entry
== NULL
)
4185 val
= create_unwind_entry (0);
4189 /* Add index table entry. This is two words. */
4190 start_unwind_section (unwind
.saved_seg
, 1);
4191 frag_align (2, 0, 0);
4192 record_alignment (now_seg
, 2);
4194 ptr
= frag_more (8);
4196 where
= frag_now_fix () - 8;
4198 /* Self relative offset of the function start. */
4199 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4200 BFD_RELOC_ARM_PREL31
);
4202 /* Indicate dependency on EHABI-defined personality routines to the
4203 linker, if it hasn't been done already. */
4204 marked_pr_dependency
4205 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4206 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4207 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4209 static const char *const name
[] =
4211 "__aeabi_unwind_cpp_pr0",
4212 "__aeabi_unwind_cpp_pr1",
4213 "__aeabi_unwind_cpp_pr2"
4215 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4216 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4217 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4218 |= 1 << unwind
.personality_index
;
4222 /* Inline exception table entry. */
4223 md_number_to_chars (ptr
+ 4, val
, 4);
4225 /* Self relative offset of the table entry. */
4226 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4227 BFD_RELOC_ARM_PREL31
);
4229 /* Restore the original section. */
4230 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4232 unwind
.proc_start
= NULL
;
4236 /* Parse an unwind_cantunwind directive. */
4239 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4241 demand_empty_rest_of_line ();
4242 if (!unwind
.proc_start
)
4243 as_bad (MISSING_FNSTART
);
4245 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4246 as_bad (_("personality routine specified for cantunwind frame"));
4248 unwind
.personality_index
= -2;
4252 /* Parse a personalityindex directive. */
4255 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4259 if (!unwind
.proc_start
)
4260 as_bad (MISSING_FNSTART
);
4262 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4263 as_bad (_("duplicate .personalityindex directive"));
4267 if (exp
.X_op
!= O_constant
4268 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4270 as_bad (_("bad personality routine number"));
4271 ignore_rest_of_line ();
4275 unwind
.personality_index
= exp
.X_add_number
;
4277 demand_empty_rest_of_line ();
4281 /* Parse a personality directive. */
4284 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4288 if (!unwind
.proc_start
)
4289 as_bad (MISSING_FNSTART
);
4291 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4292 as_bad (_("duplicate .personality directive"));
4294 c
= get_symbol_name (& name
);
4295 p
= input_line_pointer
;
4297 ++ input_line_pointer
;
4298 unwind
.personality_routine
= symbol_find_or_make (name
);
4300 demand_empty_rest_of_line ();
4304 /* Parse a directive saving core registers. */
4307 s_arm_unwind_save_core (void)
4313 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4316 as_bad (_("expected register list"));
4317 ignore_rest_of_line ();
4321 demand_empty_rest_of_line ();
4323 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4324 into .unwind_save {..., sp...}. We aren't bothered about the value of
4325 ip because it is clobbered by calls. */
4326 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4327 && (range
& 0x3000) == 0x1000)
4329 unwind
.opcode_count
--;
4330 unwind
.sp_restored
= 0;
4331 range
= (range
| 0x2000) & ~0x1000;
4332 unwind
.pending_offset
= 0;
4338 /* See if we can use the short opcodes. These pop a block of up to 8
4339 registers starting with r4, plus maybe r14. */
4340 for (n
= 0; n
< 8; n
++)
4342 /* Break at the first non-saved register. */
4343 if ((range
& (1 << (n
+ 4))) == 0)
4346 /* See if there are any other bits set. */
4347 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4349 /* Use the long form. */
4350 op
= 0x8000 | ((range
>> 4) & 0xfff);
4351 add_unwind_opcode (op
, 2);
4355 /* Use the short form. */
4357 op
= 0xa8; /* Pop r14. */
4359 op
= 0xa0; /* Do not pop r14. */
4361 add_unwind_opcode (op
, 1);
4368 op
= 0xb100 | (range
& 0xf);
4369 add_unwind_opcode (op
, 2);
4372 /* Record the number of bytes pushed. */
4373 for (n
= 0; n
< 16; n
++)
4375 if (range
& (1 << n
))
4376 unwind
.frame_size
+= 4;
4381 /* Parse a directive saving FPA registers. */
4384 s_arm_unwind_save_fpa (int reg
)
4390 /* Get Number of registers to transfer. */
4391 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4394 exp
.X_op
= O_illegal
;
4396 if (exp
.X_op
!= O_constant
)
4398 as_bad (_("expected , <constant>"));
4399 ignore_rest_of_line ();
4403 num_regs
= exp
.X_add_number
;
4405 if (num_regs
< 1 || num_regs
> 4)
4407 as_bad (_("number of registers must be in the range [1:4]"));
4408 ignore_rest_of_line ();
4412 demand_empty_rest_of_line ();
4417 op
= 0xb4 | (num_regs
- 1);
4418 add_unwind_opcode (op
, 1);
4423 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4424 add_unwind_opcode (op
, 2);
4426 unwind
.frame_size
+= num_regs
* 12;
4430 /* Parse a directive saving VFP registers for ARMv6 and above. */
4433 s_arm_unwind_save_vfp_armv6 (void)
4438 int num_vfpv3_regs
= 0;
4439 int num_regs_below_16
;
4440 bfd_boolean partial_match
;
4442 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4446 as_bad (_("expected register list"));
4447 ignore_rest_of_line ();
4451 demand_empty_rest_of_line ();
4453 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4454 than FSTMX/FLDMX-style ones). */
4456 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4458 num_vfpv3_regs
= count
;
4459 else if (start
+ count
> 16)
4460 num_vfpv3_regs
= start
+ count
- 16;
4462 if (num_vfpv3_regs
> 0)
4464 int start_offset
= start
> 16 ? start
- 16 : 0;
4465 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4466 add_unwind_opcode (op
, 2);
4469 /* Generate opcode for registers numbered in the range 0 .. 15. */
4470 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4471 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4472 if (num_regs_below_16
> 0)
4474 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4475 add_unwind_opcode (op
, 2);
4478 unwind
.frame_size
+= count
* 8;
4482 /* Parse a directive saving VFP registers for pre-ARMv6. */
4485 s_arm_unwind_save_vfp (void)
4490 bfd_boolean partial_match
;
4492 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4496 as_bad (_("expected register list"));
4497 ignore_rest_of_line ();
4501 demand_empty_rest_of_line ();
4506 op
= 0xb8 | (count
- 1);
4507 add_unwind_opcode (op
, 1);
4512 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4513 add_unwind_opcode (op
, 2);
4515 unwind
.frame_size
+= count
* 8 + 4;
4519 /* Parse a directive saving iWMMXt data registers. */
4522 s_arm_unwind_save_mmxwr (void)
4530 if (*input_line_pointer
== '{')
4531 input_line_pointer
++;
4535 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4539 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4544 as_tsktsk (_("register list not in ascending order"));
4547 if (*input_line_pointer
== '-')
4549 input_line_pointer
++;
4550 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4553 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4556 else if (reg
>= hi_reg
)
4558 as_bad (_("bad register range"));
4561 for (; reg
< hi_reg
; reg
++)
4565 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4567 skip_past_char (&input_line_pointer
, '}');
4569 demand_empty_rest_of_line ();
4571 /* Generate any deferred opcodes because we're going to be looking at
4573 flush_pending_unwind ();
4575 for (i
= 0; i
< 16; i
++)
4577 if (mask
& (1 << i
))
4578 unwind
.frame_size
+= 8;
4581 /* Attempt to combine with a previous opcode. We do this because gcc
4582 likes to output separate unwind directives for a single block of
4584 if (unwind
.opcode_count
> 0)
4586 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4587 if ((i
& 0xf8) == 0xc0)
4590 /* Only merge if the blocks are contiguous. */
4593 if ((mask
& 0xfe00) == (1 << 9))
4595 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4596 unwind
.opcode_count
--;
4599 else if (i
== 6 && unwind
.opcode_count
>= 2)
4601 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4605 op
= 0xffff << (reg
- 1);
4607 && ((mask
& op
) == (1u << (reg
- 1))))
4609 op
= (1 << (reg
+ i
+ 1)) - 1;
4610 op
&= ~((1 << reg
) - 1);
4612 unwind
.opcode_count
-= 2;
4619 /* We want to generate opcodes in the order the registers have been
4620 saved, ie. descending order. */
4621 for (reg
= 15; reg
>= -1; reg
--)
4623 /* Save registers in blocks. */
4625 || !(mask
& (1 << reg
)))
4627 /* We found an unsaved reg. Generate opcodes to save the
4634 op
= 0xc0 | (hi_reg
- 10);
4635 add_unwind_opcode (op
, 1);
4640 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4641 add_unwind_opcode (op
, 2);
4650 ignore_rest_of_line ();
4654 s_arm_unwind_save_mmxwcg (void)
4661 if (*input_line_pointer
== '{')
4662 input_line_pointer
++;
4664 skip_whitespace (input_line_pointer
);
4668 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4672 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4678 as_tsktsk (_("register list not in ascending order"));
4681 if (*input_line_pointer
== '-')
4683 input_line_pointer
++;
4684 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4687 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4690 else if (reg
>= hi_reg
)
4692 as_bad (_("bad register range"));
4695 for (; reg
< hi_reg
; reg
++)
4699 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4701 skip_past_char (&input_line_pointer
, '}');
4703 demand_empty_rest_of_line ();
4705 /* Generate any deferred opcodes because we're going to be looking at
4707 flush_pending_unwind ();
4709 for (reg
= 0; reg
< 16; reg
++)
4711 if (mask
& (1 << reg
))
4712 unwind
.frame_size
+= 4;
4715 add_unwind_opcode (op
, 2);
4718 ignore_rest_of_line ();
4722 /* Parse an unwind_save directive.
4723 If the argument is non-zero, this is a .vsave directive. */
4726 s_arm_unwind_save (int arch_v6
)
4729 struct reg_entry
*reg
;
4730 bfd_boolean had_brace
= FALSE
;
4732 if (!unwind
.proc_start
)
4733 as_bad (MISSING_FNSTART
);
4735 /* Figure out what sort of save we have. */
4736 peek
= input_line_pointer
;
4744 reg
= arm_reg_parse_multi (&peek
);
4748 as_bad (_("register expected"));
4749 ignore_rest_of_line ();
4758 as_bad (_("FPA .unwind_save does not take a register list"));
4759 ignore_rest_of_line ();
4762 input_line_pointer
= peek
;
4763 s_arm_unwind_save_fpa (reg
->number
);
4767 s_arm_unwind_save_core ();
4772 s_arm_unwind_save_vfp_armv6 ();
4774 s_arm_unwind_save_vfp ();
4777 case REG_TYPE_MMXWR
:
4778 s_arm_unwind_save_mmxwr ();
4781 case REG_TYPE_MMXWCG
:
4782 s_arm_unwind_save_mmxwcg ();
4786 as_bad (_(".unwind_save does not support this kind of register"));
4787 ignore_rest_of_line ();
4792 /* Parse an unwind_movsp directive. */
4795 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4801 if (!unwind
.proc_start
)
4802 as_bad (MISSING_FNSTART
);
4804 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4807 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4808 ignore_rest_of_line ();
4812 /* Optional constant. */
4813 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4815 if (immediate_for_directive (&offset
) == FAIL
)
4821 demand_empty_rest_of_line ();
4823 if (reg
== REG_SP
|| reg
== REG_PC
)
4825 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4829 if (unwind
.fp_reg
!= REG_SP
)
4830 as_bad (_("unexpected .unwind_movsp directive"));
4832 /* Generate opcode to restore the value. */
4834 add_unwind_opcode (op
, 1);
4836 /* Record the information for later. */
4837 unwind
.fp_reg
= reg
;
4838 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4839 unwind
.sp_restored
= 1;
4842 /* Parse an unwind_pad directive. */
4845 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4849 if (!unwind
.proc_start
)
4850 as_bad (MISSING_FNSTART
);
4852 if (immediate_for_directive (&offset
) == FAIL
)
4857 as_bad (_("stack increment must be multiple of 4"));
4858 ignore_rest_of_line ();
4862 /* Don't generate any opcodes, just record the details for later. */
4863 unwind
.frame_size
+= offset
;
4864 unwind
.pending_offset
+= offset
;
4866 demand_empty_rest_of_line ();
4869 /* Parse an unwind_setfp directive. */
4872 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4878 if (!unwind
.proc_start
)
4879 as_bad (MISSING_FNSTART
);
4881 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4882 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4885 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4887 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4889 as_bad (_("expected <reg>, <reg>"));
4890 ignore_rest_of_line ();
4894 /* Optional constant. */
4895 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4897 if (immediate_for_directive (&offset
) == FAIL
)
4903 demand_empty_rest_of_line ();
4905 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4907 as_bad (_("register must be either sp or set by a previous"
4908 "unwind_movsp directive"));
4912 /* Don't generate any opcodes, just record the information for later. */
4913 unwind
.fp_reg
= fp_reg
;
4915 if (sp_reg
== REG_SP
)
4916 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4918 unwind
.fp_offset
-= offset
;
4921 /* Parse an unwind_raw directive. */
4924 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4927 /* This is an arbitrary limit. */
4928 unsigned char op
[16];
4931 if (!unwind
.proc_start
)
4932 as_bad (MISSING_FNSTART
);
4935 if (exp
.X_op
== O_constant
4936 && skip_past_comma (&input_line_pointer
) != FAIL
)
4938 unwind
.frame_size
+= exp
.X_add_number
;
4942 exp
.X_op
= O_illegal
;
4944 if (exp
.X_op
!= O_constant
)
4946 as_bad (_("expected <offset>, <opcode>"));
4947 ignore_rest_of_line ();
4953 /* Parse the opcode. */
4958 as_bad (_("unwind opcode too long"));
4959 ignore_rest_of_line ();
4961 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4963 as_bad (_("invalid unwind opcode"));
4964 ignore_rest_of_line ();
4967 op
[count
++] = exp
.X_add_number
;
4969 /* Parse the next byte. */
4970 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4976 /* Add the opcode bytes in reverse order. */
4978 add_unwind_opcode (op
[count
], 1);
4980 demand_empty_rest_of_line ();
4984 /* Parse a .eabi_attribute directive. */
4987 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4989 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4991 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4992 attributes_set_explicitly
[tag
] = 1;
4995 /* Emit a tls fix for the symbol. */
4998 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
5002 #ifdef md_flush_pending_output
5003 md_flush_pending_output ();
5006 #ifdef md_cons_align
5010 /* Since we're just labelling the code, there's no need to define a
5013 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5014 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5015 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5016 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5018 #endif /* OBJ_ELF */
5020 static void s_arm_arch (int);
5021 static void s_arm_object_arch (int);
5022 static void s_arm_cpu (int);
5023 static void s_arm_fpu (int);
5024 static void s_arm_arch_extension (int);
5029 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5036 if (exp
.X_op
== O_symbol
)
5037 exp
.X_op
= O_secrel
;
5039 emit_expr (&exp
, 4);
5041 while (*input_line_pointer
++ == ',');
5043 input_line_pointer
--;
5044 demand_empty_rest_of_line ();
5049 arm_is_largest_exponent_ok (int precision
)
5051 /* precision == 1 ensures that this will only return
5052 true for 16 bit floats. */
5053 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5057 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5061 enum fp_16bit_format new_format
;
5063 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5065 name
= input_line_pointer
;
5066 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5067 input_line_pointer
++;
5069 saved_char
= *input_line_pointer
;
5070 *input_line_pointer
= 0;
5072 if (strcasecmp (name
, "ieee") == 0)
5073 new_format
= ARM_FP16_FORMAT_IEEE
;
5074 else if (strcasecmp (name
, "alternative") == 0)
5075 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5078 as_bad (_("unrecognised float16 format \"%s\""), name
);
5082 /* Only set fp16_format if it is still the default (aka not already
5084 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5085 fp16_format
= new_format
;
5088 if (new_format
!= fp16_format
)
5089 as_warn (_("float16 format cannot be set more than once, ignoring."));
5093 *input_line_pointer
= saved_char
;
5094 ignore_rest_of_line ();
5097 /* This table describes all the machine specific pseudo-ops the assembler
5098 has to support. The fields are:
5099 pseudo-op name without dot
5100 function to call to execute this pseudo-op
5101 Integer arg to pass to the function. */
5103 const pseudo_typeS md_pseudo_table
[] =
5105 /* Never called because '.req' does not start a line. */
5106 { "req", s_req
, 0 },
5107 /* Following two are likewise never called. */
5110 { "unreq", s_unreq
, 0 },
5111 { "bss", s_bss
, 0 },
5112 { "align", s_align_ptwo
, 2 },
5113 { "arm", s_arm
, 0 },
5114 { "thumb", s_thumb
, 0 },
5115 { "code", s_code
, 0 },
5116 { "force_thumb", s_force_thumb
, 0 },
5117 { "thumb_func", s_thumb_func
, 0 },
5118 { "thumb_set", s_thumb_set
, 0 },
5119 { "even", s_even
, 0 },
5120 { "ltorg", s_ltorg
, 0 },
5121 { "pool", s_ltorg
, 0 },
5122 { "syntax", s_syntax
, 0 },
5123 { "cpu", s_arm_cpu
, 0 },
5124 { "arch", s_arm_arch
, 0 },
5125 { "object_arch", s_arm_object_arch
, 0 },
5126 { "fpu", s_arm_fpu
, 0 },
5127 { "arch_extension", s_arm_arch_extension
, 0 },
5129 { "word", s_arm_elf_cons
, 4 },
5130 { "long", s_arm_elf_cons
, 4 },
5131 { "inst.n", s_arm_elf_inst
, 2 },
5132 { "inst.w", s_arm_elf_inst
, 4 },
5133 { "inst", s_arm_elf_inst
, 0 },
5134 { "rel31", s_arm_rel31
, 0 },
5135 { "fnstart", s_arm_unwind_fnstart
, 0 },
5136 { "fnend", s_arm_unwind_fnend
, 0 },
5137 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5138 { "personality", s_arm_unwind_personality
, 0 },
5139 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5140 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5141 { "save", s_arm_unwind_save
, 0 },
5142 { "vsave", s_arm_unwind_save
, 1 },
5143 { "movsp", s_arm_unwind_movsp
, 0 },
5144 { "pad", s_arm_unwind_pad
, 0 },
5145 { "setfp", s_arm_unwind_setfp
, 0 },
5146 { "unwind_raw", s_arm_unwind_raw
, 0 },
5147 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5148 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5152 /* These are used for dwarf. */
5156 /* These are used for dwarf2. */
5157 { "file", dwarf2_directive_file
, 0 },
5158 { "loc", dwarf2_directive_loc
, 0 },
5159 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5161 { "extend", float_cons
, 'x' },
5162 { "ldouble", float_cons
, 'x' },
5163 { "packed", float_cons
, 'p' },
5164 { "bfloat16", float_cons
, 'b' },
5166 {"secrel32", pe_directive_secrel
, 0},
5169 /* These are for compatibility with CodeComposer Studio. */
5170 {"ref", s_ccs_ref
, 0},
5171 {"def", s_ccs_def
, 0},
5172 {"asmfunc", s_ccs_asmfunc
, 0},
5173 {"endasmfunc", s_ccs_endasmfunc
, 0},
5175 {"float16", float_cons
, 'h' },
5176 {"float16_format", set_fp16_format
, 0 },
5181 /* Parser functions used exclusively in instruction operands. */
5183 /* Generic immediate-value read function for use in insn parsing.
5184 STR points to the beginning of the immediate (the leading #);
5185 VAL receives the value; if the value is outside [MIN, MAX]
5186 issue an error. PREFIX_OPT is true if the immediate prefix is
5190 parse_immediate (char **str
, int *val
, int min
, int max
,
5191 bfd_boolean prefix_opt
)
5195 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5196 if (exp
.X_op
!= O_constant
)
5198 inst
.error
= _("constant expression required");
5202 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5204 inst
.error
= _("immediate value out of range");
5208 *val
= exp
.X_add_number
;
5212 /* Less-generic immediate-value read function with the possibility of loading a
5213 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5214 instructions. Puts the result directly in inst.operands[i]. */
5217 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5218 bfd_boolean allow_symbol_p
)
5221 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5224 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5226 if (exp_p
->X_op
== O_constant
)
5228 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5229 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5230 O_constant. We have to be careful not to break compilation for
5231 32-bit X_add_number, though. */
5232 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5234 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5235 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5237 inst
.operands
[i
].regisimm
= 1;
5240 else if (exp_p
->X_op
== O_big
5241 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5243 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5245 /* Bignums have their least significant bits in
5246 generic_bignum[0]. Make sure we put 32 bits in imm and
5247 32 bits in reg, in a (hopefully) portable way. */
5248 gas_assert (parts
!= 0);
5250 /* Make sure that the number is not too big.
5251 PR 11972: Bignums can now be sign-extended to the
5252 size of a .octa so check that the out of range bits
5253 are all zero or all one. */
5254 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5256 LITTLENUM_TYPE m
= -1;
5258 if (generic_bignum
[parts
* 2] != 0
5259 && generic_bignum
[parts
* 2] != m
)
5262 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5263 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5267 inst
.operands
[i
].imm
= 0;
5268 for (j
= 0; j
< parts
; j
++, idx
++)
5269 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5270 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5271 inst
.operands
[i
].reg
= 0;
5272 for (j
= 0; j
< parts
; j
++, idx
++)
5273 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5274 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5275 inst
.operands
[i
].regisimm
= 1;
5277 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5285 /* Returns the pseudo-register number of an FPA immediate constant,
5286 or FAIL if there isn't a valid constant here. */
5289 parse_fpa_immediate (char ** str
)
5291 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5297 /* First try and match exact strings, this is to guarantee
5298 that some formats will work even for cross assembly. */
5300 for (i
= 0; fp_const
[i
]; i
++)
5302 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5306 *str
+= strlen (fp_const
[i
]);
5307 if (is_end_of_line
[(unsigned char) **str
])
5313 /* Just because we didn't get a match doesn't mean that the constant
5314 isn't valid, just that it is in a format that we don't
5315 automatically recognize. Try parsing it with the standard
5316 expression routines. */
5318 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5320 /* Look for a raw floating point number. */
5321 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5322 && is_end_of_line
[(unsigned char) *save_in
])
5324 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5326 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5328 if (words
[j
] != fp_values
[i
][j
])
5332 if (j
== MAX_LITTLENUMS
)
5340 /* Try and parse a more complex expression, this will probably fail
5341 unless the code uses a floating point prefix (eg "0f"). */
5342 save_in
= input_line_pointer
;
5343 input_line_pointer
= *str
;
5344 if (expression (&exp
) == absolute_section
5345 && exp
.X_op
== O_big
5346 && exp
.X_add_number
< 0)
5348 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5350 #define X_PRECISION 5
5351 #define E_PRECISION 15L
5352 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5354 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5356 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5358 if (words
[j
] != fp_values
[i
][j
])
5362 if (j
== MAX_LITTLENUMS
)
5364 *str
= input_line_pointer
;
5365 input_line_pointer
= save_in
;
5372 *str
= input_line_pointer
;
5373 input_line_pointer
= save_in
;
5374 inst
.error
= _("invalid FPA immediate expression");
5378 /* Returns 1 if a number has "quarter-precision" float format
5379 0baBbbbbbc defgh000 00000000 00000000. */
5382 is_quarter_float (unsigned imm
)
5384 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5385 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5389 /* Detect the presence of a floating point or integer zero constant,
5393 parse_ifimm_zero (char **in
)
5397 if (!is_immediate_prefix (**in
))
5399 /* In unified syntax, all prefixes are optional. */
5400 if (!unified_syntax
)
5406 /* Accept #0x0 as a synonym for #0. */
5407 if (strncmp (*in
, "0x", 2) == 0)
5410 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5415 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5416 &generic_floating_point_number
);
5419 && generic_floating_point_number
.sign
== '+'
5420 && (generic_floating_point_number
.low
5421 > generic_floating_point_number
.leader
))
5427 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5428 0baBbbbbbc defgh000 00000000 00000000.
5429 The zero and minus-zero cases need special handling, since they can't be
5430 encoded in the "quarter-precision" float format, but can nonetheless be
5431 loaded as integer constants. */
5434 parse_qfloat_immediate (char **ccp
, int *immed
)
5438 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5439 int found_fpchar
= 0;
5441 skip_past_char (&str
, '#');
5443 /* We must not accidentally parse an integer as a floating-point number. Make
5444 sure that the value we parse is not an integer by checking for special
5445 characters '.' or 'e'.
5446 FIXME: This is a horrible hack, but doing better is tricky because type
5447 information isn't in a very usable state at parse time. */
5449 skip_whitespace (fpnum
);
5451 if (strncmp (fpnum
, "0x", 2) == 0)
5455 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5456 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5466 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5468 unsigned fpword
= 0;
5471 /* Our FP word must be 32 bits (single-precision FP). */
5472 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5474 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5478 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5491 /* Shift operands. */
5494 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5497 struct asm_shift_name
5500 enum shift_kind kind
;
5503 /* Third argument to parse_shift. */
5504 enum parse_shift_mode
5506 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5507 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5508 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5509 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5510 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5511 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5514 /* Parse a <shift> specifier on an ARM data processing instruction.
5515 This has three forms:
5517 (LSL|LSR|ASL|ASR|ROR) Rs
5518 (LSL|LSR|ASL|ASR|ROR) #imm
5521 Note that ASL is assimilated to LSL in the instruction encoding, and
5522 RRX to ROR #0 (which cannot be written as such). */
5525 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5527 const struct asm_shift_name
*shift_name
;
5528 enum shift_kind shift
;
5533 for (p
= *str
; ISALPHA (*p
); p
++)
5538 inst
.error
= _("shift expression expected");
5542 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5545 if (shift_name
== NULL
)
5547 inst
.error
= _("shift expression expected");
5551 shift
= shift_name
->kind
;
5555 case NO_SHIFT_RESTRICT
:
5556 case SHIFT_IMMEDIATE
:
5557 if (shift
== SHIFT_UXTW
)
5559 inst
.error
= _("'UXTW' not allowed here");
5564 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5565 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5567 inst
.error
= _("'LSL' or 'ASR' required");
5572 case SHIFT_LSL_IMMEDIATE
:
5573 if (shift
!= SHIFT_LSL
)
5575 inst
.error
= _("'LSL' required");
5580 case SHIFT_ASR_IMMEDIATE
:
5581 if (shift
!= SHIFT_ASR
)
5583 inst
.error
= _("'ASR' required");
5587 case SHIFT_UXTW_IMMEDIATE
:
5588 if (shift
!= SHIFT_UXTW
)
5590 inst
.error
= _("'UXTW' required");
5598 if (shift
!= SHIFT_RRX
)
5600 /* Whitespace can appear here if the next thing is a bare digit. */
5601 skip_whitespace (p
);
5603 if (mode
== NO_SHIFT_RESTRICT
5604 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5606 inst
.operands
[i
].imm
= reg
;
5607 inst
.operands
[i
].immisreg
= 1;
5609 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5612 inst
.operands
[i
].shift_kind
= shift
;
5613 inst
.operands
[i
].shifted
= 1;
5618 /* Parse a <shifter_operand> for an ARM data processing instruction:
5621 #<immediate>, <rotate>
5625 where <shift> is defined by parse_shift above, and <rotate> is a
5626 multiple of 2 between 0 and 30. Validation of immediate operands
5627 is deferred to md_apply_fix. */
5630 parse_shifter_operand (char **str
, int i
)
5635 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5637 inst
.operands
[i
].reg
= value
;
5638 inst
.operands
[i
].isreg
= 1;
5640 /* parse_shift will override this if appropriate */
5641 inst
.relocs
[0].exp
.X_op
= O_constant
;
5642 inst
.relocs
[0].exp
.X_add_number
= 0;
5644 if (skip_past_comma (str
) == FAIL
)
5647 /* Shift operation on register. */
5648 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5651 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5654 if (skip_past_comma (str
) == SUCCESS
)
5656 /* #x, y -- ie explicit rotation by Y. */
5657 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5660 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5662 inst
.error
= _("constant expression expected");
5666 value
= exp
.X_add_number
;
5667 if (value
< 0 || value
> 30 || value
% 2 != 0)
5669 inst
.error
= _("invalid rotation");
5672 if (inst
.relocs
[0].exp
.X_add_number
< 0
5673 || inst
.relocs
[0].exp
.X_add_number
> 255)
5675 inst
.error
= _("invalid constant");
5679 /* Encode as specified. */
5680 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5684 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5685 inst
.relocs
[0].pc_rel
= 0;
5689 /* Group relocation information. Each entry in the table contains the
5690 textual name of the relocation as may appear in assembler source
5691 and must end with a colon.
5692 Along with this textual name are the relocation codes to be used if
5693 the corresponding instruction is an ALU instruction (ADD or SUB only),
5694 an LDR, an LDRS, or an LDC. */
5696 struct group_reloc_table_entry
5707 /* Varieties of non-ALU group relocation. */
5715 static struct group_reloc_table_entry group_reloc_table
[] =
5716 { /* Program counter relative: */
5718 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5723 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5724 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5725 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5726 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5728 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5733 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5734 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5735 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5736 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5738 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5739 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5740 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5741 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5742 /* Section base relative */
5744 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5749 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5750 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5751 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5752 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5754 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5759 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5760 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5761 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5762 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5764 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5765 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5766 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5767 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5768 /* Absolute thumb alu relocations. */
5770 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5775 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5780 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5785 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5790 /* Given the address of a pointer pointing to the textual name of a group
5791 relocation as may appear in assembler source, attempt to find its details
5792 in group_reloc_table. The pointer will be updated to the character after
5793 the trailing colon. On failure, FAIL will be returned; SUCCESS
5794 otherwise. On success, *entry will be updated to point at the relevant
5795 group_reloc_table entry. */
5798 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5801 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5803 int length
= strlen (group_reloc_table
[i
].name
);
5805 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5806 && (*str
)[length
] == ':')
5808 *out
= &group_reloc_table
[i
];
5809 *str
+= (length
+ 1);
5817 /* Parse a <shifter_operand> for an ARM data processing instruction
5818 (as for parse_shifter_operand) where group relocations are allowed:
5821 #<immediate>, <rotate>
5822 #:<group_reloc>:<expression>
5826 where <group_reloc> is one of the strings defined in group_reloc_table.
5827 The hashes are optional.
5829 Everything else is as for parse_shifter_operand. */
5831 static parse_operand_result
5832 parse_shifter_operand_group_reloc (char **str
, int i
)
5834 /* Determine if we have the sequence of characters #: or just :
5835 coming next. If we do, then we check for a group relocation.
5836 If we don't, punt the whole lot to parse_shifter_operand. */
5838 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5839 || (*str
)[0] == ':')
5841 struct group_reloc_table_entry
*entry
;
5843 if ((*str
)[0] == '#')
5848 /* Try to parse a group relocation. Anything else is an error. */
5849 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5851 inst
.error
= _("unknown group relocation");
5852 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5855 /* We now have the group relocation table entry corresponding to
5856 the name in the assembler source. Next, we parse the expression. */
5857 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5858 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5860 /* Record the relocation type (always the ALU variant here). */
5861 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5862 gas_assert (inst
.relocs
[0].type
!= 0);
5864 return PARSE_OPERAND_SUCCESS
;
5867 return parse_shifter_operand (str
, i
) == SUCCESS
5868 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5870 /* Never reached. */
5873 /* Parse a Neon alignment expression. Information is written to
5874 inst.operands[i]. We assume the initial ':' has been skipped.
5876 align .imm = align << 8, .immisalign=1, .preind=0 */
5877 static parse_operand_result
5878 parse_neon_alignment (char **str
, int i
)
5883 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5885 if (exp
.X_op
!= O_constant
)
5887 inst
.error
= _("alignment must be constant");
5888 return PARSE_OPERAND_FAIL
;
5891 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5892 inst
.operands
[i
].immisalign
= 1;
5893 /* Alignments are not pre-indexes. */
5894 inst
.operands
[i
].preind
= 0;
5897 return PARSE_OPERAND_SUCCESS
;
5900 /* Parse all forms of an ARM address expression. Information is written
5901 to inst.operands[i] and/or inst.relocs[0].
5903 Preindexed addressing (.preind=1):
5905 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5906 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5907 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5908 .shift_kind=shift .relocs[0].exp=shift_imm
5910 These three may have a trailing ! which causes .writeback to be set also.
5912 Postindexed addressing (.postind=1, .writeback=1):
5914 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5915 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5916 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5917 .shift_kind=shift .relocs[0].exp=shift_imm
5919 Unindexed addressing (.preind=0, .postind=0):
5921 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5925 [Rn]{!} shorthand for [Rn,#0]{!}
5926 =immediate .isreg=0 .relocs[0].exp=immediate
5927 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5929 It is the caller's responsibility to check for addressing modes not
5930 supported by the instruction, and to set inst.relocs[0].type. */
5932 static parse_operand_result
5933 parse_address_main (char **str
, int i
, int group_relocations
,
5934 group_reloc_type group_type
)
5939 if (skip_past_char (&p
, '[') == FAIL
)
5941 if (skip_past_char (&p
, '=') == FAIL
)
5943 /* Bare address - translate to PC-relative offset. */
5944 inst
.relocs
[0].pc_rel
= 1;
5945 inst
.operands
[i
].reg
= REG_PC
;
5946 inst
.operands
[i
].isreg
= 1;
5947 inst
.operands
[i
].preind
= 1;
5949 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5950 return PARSE_OPERAND_FAIL
;
5952 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5953 /*allow_symbol_p=*/TRUE
))
5954 return PARSE_OPERAND_FAIL
;
5957 return PARSE_OPERAND_SUCCESS
;
5960 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5961 skip_whitespace (p
);
5963 if (group_type
== GROUP_MVE
)
5965 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5966 struct neon_type_el et
;
5967 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5969 inst
.operands
[i
].isquad
= 1;
5971 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5973 inst
.error
= BAD_ADDR_MODE
;
5974 return PARSE_OPERAND_FAIL
;
5977 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5979 if (group_type
== GROUP_MVE
)
5980 inst
.error
= BAD_ADDR_MODE
;
5982 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5983 return PARSE_OPERAND_FAIL
;
5985 inst
.operands
[i
].reg
= reg
;
5986 inst
.operands
[i
].isreg
= 1;
5988 if (skip_past_comma (&p
) == SUCCESS
)
5990 inst
.operands
[i
].preind
= 1;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 if (skip_past_comma (&p
) == SUCCESS
)
6005 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6007 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6008 inst
.relocs
[0].exp
.X_add_number
= 0;
6011 return PARSE_OPERAND_FAIL
;
6014 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6016 inst
.operands
[i
].imm
= reg
;
6017 inst
.operands
[i
].immisreg
= 1;
6019 if (skip_past_comma (&p
) == SUCCESS
)
6020 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6021 return PARSE_OPERAND_FAIL
;
6023 else if (skip_past_char (&p
, ':') == SUCCESS
)
6025 /* FIXME: '@' should be used here, but it's filtered out by generic
6026 code before we get to see it here. This may be subject to
6028 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6030 if (result
!= PARSE_OPERAND_SUCCESS
)
6035 if (inst
.operands
[i
].negative
)
6037 inst
.operands
[i
].negative
= 0;
6041 if (group_relocations
6042 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6044 struct group_reloc_table_entry
*entry
;
6046 /* Skip over the #: or : sequence. */
6052 /* Try to parse a group relocation. Anything else is an
6054 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6056 inst
.error
= _("unknown group relocation");
6057 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6060 /* We now have the group relocation table entry corresponding to
6061 the name in the assembler source. Next, we parse the
6063 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6064 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6066 /* Record the relocation type. */
6071 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6076 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6081 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6088 if (inst
.relocs
[0].type
== 0)
6090 inst
.error
= _("this group relocation is not allowed on this instruction");
6091 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6098 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6099 return PARSE_OPERAND_FAIL
;
6100 /* If the offset is 0, find out if it's a +0 or -0. */
6101 if (inst
.relocs
[0].exp
.X_op
== O_constant
6102 && inst
.relocs
[0].exp
.X_add_number
== 0)
6104 skip_whitespace (q
);
6108 skip_whitespace (q
);
6111 inst
.operands
[i
].negative
= 1;
6116 else if (skip_past_char (&p
, ':') == SUCCESS
)
6118 /* FIXME: '@' should be used here, but it's filtered out by generic code
6119 before we get to see it here. This may be subject to change. */
6120 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6122 if (result
!= PARSE_OPERAND_SUCCESS
)
6126 if (skip_past_char (&p
, ']') == FAIL
)
6128 inst
.error
= _("']' expected");
6129 return PARSE_OPERAND_FAIL
;
6132 if (skip_past_char (&p
, '!') == SUCCESS
)
6133 inst
.operands
[i
].writeback
= 1;
6135 else if (skip_past_comma (&p
) == SUCCESS
)
6137 if (skip_past_char (&p
, '{') == SUCCESS
)
6139 /* [Rn], {expr} - unindexed, with option */
6140 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6141 0, 255, TRUE
) == FAIL
)
6142 return PARSE_OPERAND_FAIL
;
6144 if (skip_past_char (&p
, '}') == FAIL
)
6146 inst
.error
= _("'}' expected at end of 'option' field");
6147 return PARSE_OPERAND_FAIL
;
6149 if (inst
.operands
[i
].preind
)
6151 inst
.error
= _("cannot combine index with option");
6152 return PARSE_OPERAND_FAIL
;
6155 return PARSE_OPERAND_SUCCESS
;
6159 inst
.operands
[i
].postind
= 1;
6160 inst
.operands
[i
].writeback
= 1;
6162 if (inst
.operands
[i
].preind
)
6164 inst
.error
= _("cannot combine pre- and post-indexing");
6165 return PARSE_OPERAND_FAIL
;
6169 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6171 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6172 struct neon_type_el et
;
6173 if (group_type
== GROUP_MVE
6174 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6176 inst
.operands
[i
].immisreg
= 2;
6177 inst
.operands
[i
].imm
= reg
;
6179 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6181 /* We might be using the immediate for alignment already. If we
6182 are, OR the register number into the low-order bits. */
6183 if (inst
.operands
[i
].immisalign
)
6184 inst
.operands
[i
].imm
|= reg
;
6186 inst
.operands
[i
].imm
= reg
;
6187 inst
.operands
[i
].immisreg
= 1;
6189 if (skip_past_comma (&p
) == SUCCESS
)
6190 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6191 return PARSE_OPERAND_FAIL
;
6197 if (inst
.operands
[i
].negative
)
6199 inst
.operands
[i
].negative
= 0;
6202 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6203 return PARSE_OPERAND_FAIL
;
6204 /* If the offset is 0, find out if it's a +0 or -0. */
6205 if (inst
.relocs
[0].exp
.X_op
== O_constant
6206 && inst
.relocs
[0].exp
.X_add_number
== 0)
6208 skip_whitespace (q
);
6212 skip_whitespace (q
);
6215 inst
.operands
[i
].negative
= 1;
6221 /* If at this point neither .preind nor .postind is set, we have a
6222 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6223 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6225 inst
.operands
[i
].preind
= 1;
6226 inst
.relocs
[0].exp
.X_op
= O_constant
;
6227 inst
.relocs
[0].exp
.X_add_number
= 0;
6230 return PARSE_OPERAND_SUCCESS
;
6234 parse_address (char **str
, int i
)
6236 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6240 static parse_operand_result
6241 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6243 return parse_address_main (str
, i
, 1, type
);
6246 /* Parse an operand for a MOVW or MOVT instruction. */
6248 parse_half (char **str
)
6253 skip_past_char (&p
, '#');
6254 if (strncasecmp (p
, ":lower16:", 9) == 0)
6255 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6256 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6257 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6259 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6262 skip_whitespace (p
);
6265 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6268 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6270 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6272 inst
.error
= _("constant expression expected");
6275 if (inst
.relocs
[0].exp
.X_add_number
< 0
6276 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6278 inst
.error
= _("immediate value out of range");
6286 /* Miscellaneous. */
6288 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6289 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6291 parse_psr (char **str
, bfd_boolean lhs
)
6294 unsigned long psr_field
;
6295 const struct asm_psr
*psr
;
6297 bfd_boolean is_apsr
= FALSE
;
6298 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6300 /* PR gas/12698: If the user has specified -march=all then m_profile will
6301 be TRUE, but we want to ignore it in this case as we are building for any
6302 CPU type, including non-m variants. */
6303 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6306 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6307 feature for ease of use and backwards compatibility. */
6309 if (strncasecmp (p
, "SPSR", 4) == 0)
6312 goto unsupported_psr
;
6314 psr_field
= SPSR_BIT
;
6316 else if (strncasecmp (p
, "CPSR", 4) == 0)
6319 goto unsupported_psr
;
6323 else if (strncasecmp (p
, "APSR", 4) == 0)
6325 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6326 and ARMv7-R architecture CPUs. */
6335 while (ISALNUM (*p
) || *p
== '_');
6337 if (strncasecmp (start
, "iapsr", 5) == 0
6338 || strncasecmp (start
, "eapsr", 5) == 0
6339 || strncasecmp (start
, "xpsr", 4) == 0
6340 || strncasecmp (start
, "psr", 3) == 0)
6341 p
= start
+ strcspn (start
, "rR") + 1;
6343 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6349 /* If APSR is being written, a bitfield may be specified. Note that
6350 APSR itself is handled above. */
6351 if (psr
->field
<= 3)
6353 psr_field
= psr
->field
;
6359 /* M-profile MSR instructions have the mask field set to "10", except
6360 *PSR variants which modify APSR, which may use a different mask (and
6361 have been handled already). Do that by setting the PSR_f field
6363 return psr
->field
| (lhs
? PSR_f
: 0);
6366 goto unsupported_psr
;
6372 /* A suffix follows. */
6378 while (ISALNUM (*p
) || *p
== '_');
6382 /* APSR uses a notation for bits, rather than fields. */
6383 unsigned int nzcvq_bits
= 0;
6384 unsigned int g_bit
= 0;
6387 for (bit
= start
; bit
!= p
; bit
++)
6389 switch (TOLOWER (*bit
))
6392 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6396 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6400 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6404 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6408 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6412 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6416 inst
.error
= _("unexpected bit specified after APSR");
6421 if (nzcvq_bits
== 0x1f)
6426 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6428 inst
.error
= _("selected processor does not "
6429 "support DSP extension");
6436 if ((nzcvq_bits
& 0x20) != 0
6437 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6438 || (g_bit
& 0x2) != 0)
6440 inst
.error
= _("bad bitmask specified after APSR");
6446 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6451 psr_field
|= psr
->field
;
6457 goto error
; /* Garbage after "[CS]PSR". */
6459 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6460 is deprecated, but allow it anyway. */
6464 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6467 else if (!m_profile
)
6468 /* These bits are never right for M-profile devices: don't set them
6469 (only code paths which read/write APSR reach here). */
6470 psr_field
|= (PSR_c
| PSR_f
);
6476 inst
.error
= _("selected processor does not support requested special "
6477 "purpose register");
6481 inst
.error
= _("flag for {c}psr instruction expected");
6486 parse_sys_vldr_vstr (char **str
)
6495 {"FPSCR", 0x1, 0x0},
6496 {"FPSCR_nzcvqc", 0x2, 0x0},
6499 {"FPCXTNS", 0x6, 0x1},
6500 {"FPCXTS", 0x7, 0x1}
6502 char *op_end
= strchr (*str
, ',');
6503 size_t op_strlen
= op_end
- *str
;
6505 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6507 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6509 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6518 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6519 value suitable for splatting into the AIF field of the instruction. */
6522 parse_cps_flags (char **str
)
6531 case '\0': case ',':
6534 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6535 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6536 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6539 inst
.error
= _("unrecognized CPS flag");
6544 if (saw_a_flag
== 0)
6546 inst
.error
= _("missing CPS flags");
6554 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6555 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6558 parse_endian_specifier (char **str
)
6563 if (strncasecmp (s
, "BE", 2))
6565 else if (strncasecmp (s
, "LE", 2))
6569 inst
.error
= _("valid endian specifiers are be or le");
6573 if (ISALNUM (s
[2]) || s
[2] == '_')
6575 inst
.error
= _("valid endian specifiers are be or le");
6580 return little_endian
;
6583 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6584 value suitable for poking into the rotate field of an sxt or sxta
6585 instruction, or FAIL on error. */
6588 parse_ror (char **str
)
6593 if (strncasecmp (s
, "ROR", 3) == 0)
6597 inst
.error
= _("missing rotation field after comma");
6601 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6606 case 0: *str
= s
; return 0x0;
6607 case 8: *str
= s
; return 0x1;
6608 case 16: *str
= s
; return 0x2;
6609 case 24: *str
= s
; return 0x3;
6612 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6617 /* Parse a conditional code (from conds[] below). The value returned is in the
6618 range 0 .. 14, or FAIL. */
6620 parse_cond (char **str
)
6623 const struct asm_cond
*c
;
6625 /* Condition codes are always 2 characters, so matching up to
6626 3 characters is sufficient. */
6631 while (ISALPHA (*q
) && n
< 3)
6633 cond
[n
] = TOLOWER (*q
);
6638 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6641 inst
.error
= _("condition required");
6649 /* Parse an option for a barrier instruction. Returns the encoding for the
6652 parse_barrier (char **str
)
6655 const struct asm_barrier_opt
*o
;
6658 while (ISALPHA (*q
))
6661 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6666 if (!mark_feature_used (&o
->arch
))
6673 /* Parse the operands of a table branch instruction. Similar to a memory
6676 parse_tb (char **str
)
6681 if (skip_past_char (&p
, '[') == FAIL
)
6683 inst
.error
= _("'[' expected");
6687 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6689 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6692 inst
.operands
[0].reg
= reg
;
6694 if (skip_past_comma (&p
) == FAIL
)
6696 inst
.error
= _("',' expected");
6700 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6702 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6705 inst
.operands
[0].imm
= reg
;
6707 if (skip_past_comma (&p
) == SUCCESS
)
6709 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6711 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6713 inst
.error
= _("invalid shift");
6716 inst
.operands
[0].shifted
= 1;
6719 if (skip_past_char (&p
, ']') == FAIL
)
6721 inst
.error
= _("']' expected");
6728 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6729 information on the types the operands can take and how they are encoded.
6730 Up to four operands may be read; this function handles setting the
6731 ".present" field for each read operand itself.
6732 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6733 else returns FAIL. */
6736 parse_neon_mov (char **str
, int *which_operand
)
6738 int i
= *which_operand
, val
;
6739 enum arm_reg_type rtype
;
6741 struct neon_type_el optype
;
6743 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6745 /* Cases 17 or 19. */
6746 inst
.operands
[i
].reg
= val
;
6747 inst
.operands
[i
].isvec
= 1;
6748 inst
.operands
[i
].isscalar
= 2;
6749 inst
.operands
[i
].vectype
= optype
;
6750 inst
.operands
[i
++].present
= 1;
6752 if (skip_past_comma (&ptr
) == FAIL
)
6755 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6757 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isreg
= 1;
6760 inst
.operands
[i
].present
= 1;
6762 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6764 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isvec
= 1;
6767 inst
.operands
[i
].isscalar
= 2;
6768 inst
.operands
[i
].vectype
= optype
;
6769 inst
.operands
[i
++].present
= 1;
6771 if (skip_past_comma (&ptr
) == FAIL
)
6774 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
++].present
= 1;
6781 if (skip_past_comma (&ptr
) == FAIL
)
6784 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6787 inst
.operands
[i
].reg
= val
;
6788 inst
.operands
[i
].isreg
= 1;
6789 inst
.operands
[i
].present
= 1;
6793 first_error (_("expected ARM or MVE vector register"));
6797 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6799 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6800 inst
.operands
[i
].reg
= val
;
6801 inst
.operands
[i
].isscalar
= 1;
6802 inst
.operands
[i
].vectype
= optype
;
6803 inst
.operands
[i
++].present
= 1;
6805 if (skip_past_comma (&ptr
) == FAIL
)
6808 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6811 inst
.operands
[i
].reg
= val
;
6812 inst
.operands
[i
].isreg
= 1;
6813 inst
.operands
[i
].present
= 1;
6815 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6817 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6820 /* Cases 0, 1, 2, 3, 5 (D only). */
6821 if (skip_past_comma (&ptr
) == FAIL
)
6824 inst
.operands
[i
].reg
= val
;
6825 inst
.operands
[i
].isreg
= 1;
6826 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6827 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6828 inst
.operands
[i
].isvec
= 1;
6829 inst
.operands
[i
].vectype
= optype
;
6830 inst
.operands
[i
++].present
= 1;
6832 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6834 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6835 Case 13: VMOV <Sd>, <Rm> */
6836 inst
.operands
[i
].reg
= val
;
6837 inst
.operands
[i
].isreg
= 1;
6838 inst
.operands
[i
].present
= 1;
6840 if (rtype
== REG_TYPE_NQ
)
6842 first_error (_("can't use Neon quad register here"));
6845 else if (rtype
!= REG_TYPE_VFS
)
6848 if (skip_past_comma (&ptr
) == FAIL
)
6850 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6852 inst
.operands
[i
].reg
= val
;
6853 inst
.operands
[i
].isreg
= 1;
6854 inst
.operands
[i
].present
= 1;
6857 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6859 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6862 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6863 Case 1: VMOV<c><q> <Dd>, <Dm>
6864 Case 8: VMOV.F32 <Sd>, <Sm>
6865 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6867 inst
.operands
[i
].reg
= val
;
6868 inst
.operands
[i
].isreg
= 1;
6869 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6870 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6871 inst
.operands
[i
].isvec
= 1;
6872 inst
.operands
[i
].vectype
= optype
;
6873 inst
.operands
[i
].present
= 1;
6875 if (skip_past_comma (&ptr
) == SUCCESS
)
6880 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6883 inst
.operands
[i
].reg
= val
;
6884 inst
.operands
[i
].isreg
= 1;
6885 inst
.operands
[i
++].present
= 1;
6887 if (skip_past_comma (&ptr
) == FAIL
)
6890 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6893 inst
.operands
[i
].reg
= val
;
6894 inst
.operands
[i
].isreg
= 1;
6895 inst
.operands
[i
].present
= 1;
6898 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6899 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6900 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6901 Case 10: VMOV.F32 <Sd>, #<imm>
6902 Case 11: VMOV.F64 <Dd>, #<imm> */
6903 inst
.operands
[i
].immisfloat
= 1;
6904 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6906 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6907 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6911 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6915 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6917 /* Cases 6, 7, 16, 18. */
6918 inst
.operands
[i
].reg
= val
;
6919 inst
.operands
[i
].isreg
= 1;
6920 inst
.operands
[i
++].present
= 1;
6922 if (skip_past_comma (&ptr
) == FAIL
)
6925 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6927 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6928 inst
.operands
[i
].reg
= val
;
6929 inst
.operands
[i
].isscalar
= 2;
6930 inst
.operands
[i
].present
= 1;
6931 inst
.operands
[i
].vectype
= optype
;
6933 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6935 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6936 inst
.operands
[i
].reg
= val
;
6937 inst
.operands
[i
].isscalar
= 1;
6938 inst
.operands
[i
].present
= 1;
6939 inst
.operands
[i
].vectype
= optype
;
6941 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6943 inst
.operands
[i
].reg
= val
;
6944 inst
.operands
[i
].isreg
= 1;
6945 inst
.operands
[i
++].present
= 1;
6947 if (skip_past_comma (&ptr
) == FAIL
)
6950 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6953 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6955 inst
.operands
[i
].reg
= val
;
6956 inst
.operands
[i
].isreg
= 1;
6957 inst
.operands
[i
].isvec
= 1;
6958 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6959 inst
.operands
[i
].vectype
= optype
;
6960 inst
.operands
[i
].present
= 1;
6962 if (rtype
== REG_TYPE_VFS
)
6966 if (skip_past_comma (&ptr
) == FAIL
)
6968 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6971 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6974 inst
.operands
[i
].reg
= val
;
6975 inst
.operands
[i
].isreg
= 1;
6976 inst
.operands
[i
].isvec
= 1;
6977 inst
.operands
[i
].issingle
= 1;
6978 inst
.operands
[i
].vectype
= optype
;
6979 inst
.operands
[i
].present
= 1;
6984 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6987 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6988 inst
.operands
[i
].reg
= val
;
6989 inst
.operands
[i
].isvec
= 1;
6990 inst
.operands
[i
].isscalar
= 2;
6991 inst
.operands
[i
].vectype
= optype
;
6992 inst
.operands
[i
++].present
= 1;
6994 if (skip_past_comma (&ptr
) == FAIL
)
6997 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
7000 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7003 inst
.operands
[i
].reg
= val
;
7004 inst
.operands
[i
].isvec
= 1;
7005 inst
.operands
[i
].isscalar
= 2;
7006 inst
.operands
[i
].vectype
= optype
;
7007 inst
.operands
[i
].present
= 1;
7011 first_error (_("VFP single, double or MVE vector register"
7017 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7021 inst
.operands
[i
].reg
= val
;
7022 inst
.operands
[i
].isreg
= 1;
7023 inst
.operands
[i
].isvec
= 1;
7024 inst
.operands
[i
].issingle
= 1;
7025 inst
.operands
[i
].vectype
= optype
;
7026 inst
.operands
[i
].present
= 1;
7031 first_error (_("parse error"));
7035 /* Successfully parsed the operands. Update args. */
7041 first_error (_("expected comma"));
7045 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7049 /* Use this macro when the operand constraints are different
7050 for ARM and THUMB (e.g. ldrd). */
7051 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7052 ((arm_operand) | ((thumb_operand) << 16))
7054 /* Matcher codes for parse_operands. */
7055 enum operand_parse_code
7057 OP_stop
, /* end of line */
7059 OP_RR
, /* ARM register */
7060 OP_RRnpc
, /* ARM register, not r15 */
7061 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7062 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7063 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7064 optional trailing ! */
7065 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7066 OP_RCP
, /* Coprocessor number */
7067 OP_RCN
, /* Coprocessor register */
7068 OP_RF
, /* FPA register */
7069 OP_RVS
, /* VFP single precision register */
7070 OP_RVD
, /* VFP double precision register (0..15) */
7071 OP_RND
, /* Neon double precision register (0..31) */
7072 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7073 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7075 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7077 OP_RNQ
, /* Neon quad precision register */
7078 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7079 OP_RVSD
, /* VFP single or double precision register */
7080 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7081 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7082 OP_RNSD
, /* Neon single or double precision register */
7083 OP_RNDQ
, /* Neon double or quad precision register */
7084 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7085 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7086 OP_RNSDQ
, /* Neon single, double or quad precision register */
7087 OP_RNSC
, /* Neon scalar D[X] */
7088 OP_RVC
, /* VFP control register */
7089 OP_RMF
, /* Maverick F register */
7090 OP_RMD
, /* Maverick D register */
7091 OP_RMFX
, /* Maverick FX register */
7092 OP_RMDX
, /* Maverick DX register */
7093 OP_RMAX
, /* Maverick AX register */
7094 OP_RMDS
, /* Maverick DSPSC register */
7095 OP_RIWR
, /* iWMMXt wR register */
7096 OP_RIWC
, /* iWMMXt wC register */
7097 OP_RIWG
, /* iWMMXt wCG register */
7098 OP_RXA
, /* XScale accumulator register */
7100 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7101 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7103 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7105 OP_RMQ
, /* MVE vector register. */
7106 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7107 OP_RMQRR
, /* MVE vector or ARM register. */
7109 /* New operands for Armv8.1-M Mainline. */
7110 OP_LR
, /* ARM LR register */
7111 OP_RRe
, /* ARM register, only even numbered. */
7112 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7113 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7114 OP_RR_ZR
, /* ARM register or ZR but no PC */
7116 OP_REGLST
, /* ARM register list */
7117 OP_CLRMLST
, /* CLRM register list */
7118 OP_VRSLST
, /* VFP single-precision register list */
7119 OP_VRDLST
, /* VFP double-precision register list */
7120 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7121 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7122 OP_NSTRLST
, /* Neon element/structure list */
7123 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7124 OP_MSTRLST2
, /* MVE vector list with two elements. */
7125 OP_MSTRLST4
, /* MVE vector list with four elements. */
7127 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7128 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7129 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7130 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7132 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7133 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7134 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7135 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7137 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7138 scalar, or ARM register. */
7139 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7140 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7141 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7143 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7144 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7145 OP_VMOV
, /* Neon VMOV operands. */
7146 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7147 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7149 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7150 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7152 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7153 OP_VLDR
, /* VLDR operand. */
7155 OP_I0
, /* immediate zero */
7156 OP_I7
, /* immediate value 0 .. 7 */
7157 OP_I15
, /* 0 .. 15 */
7158 OP_I16
, /* 1 .. 16 */
7159 OP_I16z
, /* 0 .. 16 */
7160 OP_I31
, /* 0 .. 31 */
7161 OP_I31w
, /* 0 .. 31, optional trailing ! */
7162 OP_I32
, /* 1 .. 32 */
7163 OP_I32z
, /* 0 .. 32 */
7164 OP_I48_I64
, /* 48 or 64 */
7165 OP_I63
, /* 0 .. 63 */
7166 OP_I63s
, /* -64 .. 63 */
7167 OP_I64
, /* 1 .. 64 */
7168 OP_I64z
, /* 0 .. 64 */
7169 OP_I127
, /* 0 .. 127 */
7170 OP_I255
, /* 0 .. 255 */
7171 OP_I511
, /* 0 .. 511 */
7172 OP_I4095
, /* 0 .. 4095 */
7173 OP_I8191
, /* 0 .. 8191 */
7174 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7175 OP_I7b
, /* 0 .. 7 */
7176 OP_I15b
, /* 0 .. 15 */
7177 OP_I31b
, /* 0 .. 31 */
7179 OP_SH
, /* shifter operand */
7180 OP_SHG
, /* shifter operand with possible group relocation */
7181 OP_ADDR
, /* Memory address expression (any mode) */
7182 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7183 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7184 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7185 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7186 OP_EXP
, /* arbitrary expression */
7187 OP_EXPi
, /* same, with optional immediate prefix */
7188 OP_EXPr
, /* same, with optional relocation suffix */
7189 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7190 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7191 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7192 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7194 OP_CPSF
, /* CPS flags */
7195 OP_ENDI
, /* Endianness specifier */
7196 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7197 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7198 OP_COND
, /* conditional code */
7199 OP_TB
, /* Table branch. */
7201 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7203 OP_RRnpc_I0
, /* ARM register or literal 0 */
7204 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7205 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7206 OP_RF_IF
, /* FPA register or immediate */
7207 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7208 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7210 /* Optional operands. */
7211 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7212 OP_oI31b
, /* 0 .. 31 */
7213 OP_oI32b
, /* 1 .. 32 */
7214 OP_oI32z
, /* 0 .. 32 */
7215 OP_oIffffb
, /* 0 .. 65535 */
7216 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7218 OP_oRR
, /* ARM register */
7219 OP_oLR
, /* ARM LR register */
7220 OP_oRRnpc
, /* ARM register, not the PC */
7221 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7222 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7223 OP_oRND
, /* Optional Neon double precision register */
7224 OP_oRNQ
, /* Optional Neon quad precision register */
7225 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7226 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7227 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7228 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7230 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7232 OP_oSHll
, /* LSL immediate */
7233 OP_oSHar
, /* ASR immediate */
7234 OP_oSHllar
, /* LSL or ASR immediate */
7235 OP_oROR
, /* ROR 0/8/16/24 */
7236 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7238 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7240 /* Some pre-defined mixed (ARM/THUMB) operands. */
7241 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7242 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7243 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7245 OP_FIRST_OPTIONAL
= OP_oI7b
7248 /* Generic instruction operand parser. This does no encoding and no
7249 semantic validation; it merely squirrels values away in the inst
7250 structure. Returns SUCCESS or FAIL depending on whether the
7251 specified grammar matched. */
7253 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7255 unsigned const int *upat
= pattern
;
7256 char *backtrack_pos
= 0;
7257 const char *backtrack_error
= 0;
7258 int i
, val
= 0, backtrack_index
= 0;
7259 enum arm_reg_type rtype
;
7260 parse_operand_result result
;
7261 unsigned int op_parse_code
;
7262 bfd_boolean partial_match
;
7264 #define po_char_or_fail(chr) \
7267 if (skip_past_char (&str, chr) == FAIL) \
7272 #define po_reg_or_fail(regtype) \
7275 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7276 & inst.operands[i].vectype); \
7279 first_error (_(reg_expected_msgs[regtype])); \
7282 inst.operands[i].reg = val; \
7283 inst.operands[i].isreg = 1; \
7284 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7285 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7286 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7287 || rtype == REG_TYPE_VFD \
7288 || rtype == REG_TYPE_NQ); \
7289 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7293 #define po_reg_or_goto(regtype, label) \
7296 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7297 & inst.operands[i].vectype); \
7301 inst.operands[i].reg = val; \
7302 inst.operands[i].isreg = 1; \
7303 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7304 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7305 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7306 || rtype == REG_TYPE_VFD \
7307 || rtype == REG_TYPE_NQ); \
7308 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7312 #define po_imm_or_fail(min, max, popt) \
7315 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7317 inst.operands[i].imm = val; \
7321 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7325 my_get_expression (&exp, &str, popt); \
7326 if (exp.X_op != O_constant) \
7328 inst.error = _("constant expression required"); \
7331 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7333 inst.error = _("immediate value 48 or 64 expected"); \
7336 inst.operands[i].imm = exp.X_add_number; \
7340 #define po_scalar_or_goto(elsz, label, reg_type) \
7343 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7347 inst.operands[i].reg = val; \
7348 inst.operands[i].isscalar = 1; \
7352 #define po_misc_or_fail(expr) \
7360 #define po_misc_or_fail_no_backtrack(expr) \
7364 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7365 backtrack_pos = 0; \
7366 if (result != PARSE_OPERAND_SUCCESS) \
7371 #define po_barrier_or_imm(str) \
7374 val = parse_barrier (&str); \
7375 if (val == FAIL && ! ISALPHA (*str)) \
7378 /* ISB can only take SY as an option. */ \
7379 || ((inst.instruction & 0xf0) == 0x60 \
7382 inst.error = _("invalid barrier type"); \
7383 backtrack_pos = 0; \
7389 skip_whitespace (str
);
7391 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7393 op_parse_code
= upat
[i
];
7394 if (op_parse_code
>= 1<<16)
7395 op_parse_code
= thumb
? (op_parse_code
>> 16)
7396 : (op_parse_code
& ((1<<16)-1));
7398 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7400 /* Remember where we are in case we need to backtrack. */
7401 backtrack_pos
= str
;
7402 backtrack_error
= inst
.error
;
7403 backtrack_index
= i
;
7406 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7407 po_char_or_fail (',');
7409 switch (op_parse_code
)
7421 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7422 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7423 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7424 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7425 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7426 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7429 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7433 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7437 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7440 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7442 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7444 /* Also accept generic coprocessor regs for unknown registers. */
7446 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7448 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7449 existing register with a value of 0, this seems like the
7450 best way to parse P0. */
7452 if (strncasecmp (str
, "P0", 2) == 0)
7455 inst
.operands
[i
].isreg
= 1;
7456 inst
.operands
[i
].reg
= 13;
7461 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7462 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7463 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7464 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7465 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7466 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7467 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7468 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7469 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7470 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7473 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7476 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7477 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7479 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7484 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7488 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7490 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7493 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7495 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7499 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7502 po_reg_or_fail (REG_TYPE_MQ
);
7505 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7507 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7512 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7515 po_reg_or_fail (REG_TYPE_NSDQ
);
7519 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7523 po_reg_or_fail (REG_TYPE_MQ
);
7525 /* Neon scalar. Using an element size of 8 means that some invalid
7526 scalars are accepted here, so deal with those in later code. */
7527 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7531 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7534 po_imm_or_fail (0, 0, TRUE
);
7539 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7543 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7548 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7551 if (parse_ifimm_zero (&str
))
7552 inst
.operands
[i
].imm
= 0;
7556 = _("only floating point zero is allowed as immediate value");
7564 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7567 po_reg_or_fail (REG_TYPE_RN
);
7571 case OP_RNSDQ_RNSC_MQ_RR
:
7572 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7575 case OP_RNSDQ_RNSC_MQ
:
7576 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7581 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7585 po_reg_or_fail (REG_TYPE_NSDQ
);
7592 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7595 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7598 po_reg_or_fail (REG_TYPE_NSD
);
7602 case OP_RNDQMQ_RNSC_RR
:
7603 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7606 case OP_RNDQ_RNSC_RR
:
7607 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7609 case OP_RNDQMQ_RNSC
:
7610 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7615 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7618 po_reg_or_fail (REG_TYPE_NDQ
);
7624 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7627 po_reg_or_fail (REG_TYPE_VFD
);
7632 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7633 not careful then bad things might happen. */
7634 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7637 case OP_RNDQMQ_Ibig
:
7638 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7643 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7646 /* There's a possibility of getting a 64-bit immediate here, so
7647 we need special handling. */
7648 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7651 inst
.error
= _("immediate value is out of range");
7657 case OP_RNDQMQ_I63b_RR
:
7658 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7661 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7666 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7669 po_imm_or_fail (0, 63, TRUE
);
7674 po_char_or_fail ('[');
7675 po_reg_or_fail (REG_TYPE_RN
);
7676 po_char_or_fail (']');
7682 po_reg_or_fail (REG_TYPE_RN
);
7683 if (skip_past_char (&str
, '!') == SUCCESS
)
7684 inst
.operands
[i
].writeback
= 1;
7688 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7689 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7690 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7691 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7692 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7693 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7694 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7695 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7696 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7697 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7698 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7699 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7700 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7701 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7702 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7703 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7704 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7705 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7707 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7708 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7710 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7711 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7712 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7713 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7715 /* Immediate variants */
7717 po_char_or_fail ('{');
7718 po_imm_or_fail (0, 255, TRUE
);
7719 po_char_or_fail ('}');
7723 /* The expression parser chokes on a trailing !, so we have
7724 to find it first and zap it. */
7727 while (*s
&& *s
!= ',')
7732 inst
.operands
[i
].writeback
= 1;
7734 po_imm_or_fail (0, 31, TRUE
);
7742 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7747 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7752 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7754 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7756 val
= parse_reloc (&str
);
7759 inst
.error
= _("unrecognized relocation suffix");
7762 else if (val
!= BFD_RELOC_UNUSED
)
7764 inst
.operands
[i
].imm
= val
;
7765 inst
.operands
[i
].hasreloc
= 1;
7771 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7773 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7775 inst
.operands
[i
].hasreloc
= 1;
7777 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7779 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7780 inst
.operands
[i
].hasreloc
= 0;
7784 /* Operand for MOVW or MOVT. */
7786 po_misc_or_fail (parse_half (&str
));
7789 /* Register or expression. */
7790 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7791 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7793 /* Register or immediate. */
7794 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7795 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7797 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7798 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7800 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7802 if (!is_immediate_prefix (*str
))
7805 val
= parse_fpa_immediate (&str
);
7808 /* FPA immediates are encoded as registers 8-15.
7809 parse_fpa_immediate has already applied the offset. */
7810 inst
.operands
[i
].reg
= val
;
7811 inst
.operands
[i
].isreg
= 1;
7814 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7815 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7817 /* Two kinds of register. */
7820 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7822 || (rege
->type
!= REG_TYPE_MMXWR
7823 && rege
->type
!= REG_TYPE_MMXWC
7824 && rege
->type
!= REG_TYPE_MMXWCG
))
7826 inst
.error
= _("iWMMXt data or control register expected");
7829 inst
.operands
[i
].reg
= rege
->number
;
7830 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7836 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7838 || (rege
->type
!= REG_TYPE_MMXWC
7839 && rege
->type
!= REG_TYPE_MMXWCG
))
7841 inst
.error
= _("iWMMXt control register expected");
7844 inst
.operands
[i
].reg
= rege
->number
;
7845 inst
.operands
[i
].isreg
= 1;
7850 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7851 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7852 case OP_oROR
: val
= parse_ror (&str
); break;
7854 case OP_COND
: val
= parse_cond (&str
); break;
7855 case OP_oBARRIER_I15
:
7856 po_barrier_or_imm (str
); break;
7858 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7864 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7865 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7867 inst
.error
= _("Banked registers are not available with this "
7873 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7877 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7880 val
= parse_sys_vldr_vstr (&str
);
7884 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7887 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7889 if (strncasecmp (str
, "APSR_", 5) == 0)
7896 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7897 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7898 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7899 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7900 default: found
= 16;
7904 inst
.operands
[i
].isvec
= 1;
7905 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7906 inst
.operands
[i
].reg
= REG_PC
;
7913 po_misc_or_fail (parse_tb (&str
));
7916 /* Register lists. */
7918 val
= parse_reg_list (&str
, REGLIST_RN
);
7921 inst
.operands
[i
].writeback
= 1;
7927 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7931 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7936 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7941 /* Allow Q registers too. */
7942 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7943 REGLIST_NEON_D
, &partial_match
);
7947 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7948 REGLIST_VFP_S
, &partial_match
);
7949 inst
.operands
[i
].issingle
= 1;
7954 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7955 REGLIST_VFP_D_VPR
, &partial_match
);
7956 if (val
== FAIL
&& !partial_match
)
7959 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7960 REGLIST_VFP_S_VPR
, &partial_match
);
7961 inst
.operands
[i
].issingle
= 1;
7966 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7967 REGLIST_NEON_D
, &partial_match
);
7972 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7973 1, &inst
.operands
[i
].vectype
);
7974 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7978 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7979 0, &inst
.operands
[i
].vectype
);
7982 /* Addressing modes */
7984 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7988 po_misc_or_fail (parse_address (&str
, i
));
7992 po_misc_or_fail_no_backtrack (
7993 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7997 po_misc_or_fail_no_backtrack (
7998 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
8002 po_misc_or_fail_no_backtrack (
8003 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8007 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8011 po_misc_or_fail_no_backtrack (
8012 parse_shifter_operand_group_reloc (&str
, i
));
8016 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8020 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8024 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8029 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8034 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8037 po_reg_or_fail (REG_TYPE_ZR
);
8041 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8044 /* Various value-based sanity checks and shared operations. We
8045 do not signal immediate failures for the register constraints;
8046 this allows a syntax error to take precedence. */
8047 switch (op_parse_code
)
8055 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8056 inst
.error
= BAD_PC
;
8061 case OP_RRnpcsp_I32
:
8062 if (inst
.operands
[i
].isreg
)
8064 if (inst
.operands
[i
].reg
== REG_PC
)
8065 inst
.error
= BAD_PC
;
8066 else if (inst
.operands
[i
].reg
== REG_SP
8067 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8068 relaxed since ARMv8-A. */
8069 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8072 inst
.error
= BAD_SP
;
8078 if (inst
.operands
[i
].isreg
8079 && inst
.operands
[i
].reg
== REG_PC
8080 && (inst
.operands
[i
].writeback
|| thumb
))
8081 inst
.error
= BAD_PC
;
8086 if (inst
.operands
[i
].isreg
)
8096 case OP_oBARRIER_I15
:
8109 inst
.operands
[i
].imm
= val
;
8114 if (inst
.operands
[i
].reg
!= REG_LR
)
8115 inst
.error
= _("operand must be LR register");
8121 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8122 inst
.error
= BAD_PC
;
8126 if (inst
.operands
[i
].isreg
8127 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8128 inst
.error
= BAD_ODD
;
8132 if (inst
.operands
[i
].isreg
)
8134 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8135 inst
.error
= BAD_EVEN
;
8136 else if (inst
.operands
[i
].reg
== REG_SP
)
8137 as_tsktsk (MVE_BAD_SP
);
8138 else if (inst
.operands
[i
].reg
== REG_PC
)
8139 inst
.error
= BAD_PC
;
8147 /* If we get here, this operand was successfully parsed. */
8148 inst
.operands
[i
].present
= 1;
8152 inst
.error
= BAD_ARGS
;
8157 /* The parse routine should already have set inst.error, but set a
8158 default here just in case. */
8160 inst
.error
= BAD_SYNTAX
;
8164 /* Do not backtrack over a trailing optional argument that
8165 absorbed some text. We will only fail again, with the
8166 'garbage following instruction' error message, which is
8167 probably less helpful than the current one. */
8168 if (backtrack_index
== i
&& backtrack_pos
!= str
8169 && upat
[i
+1] == OP_stop
)
8172 inst
.error
= BAD_SYNTAX
;
8176 /* Try again, skipping the optional argument at backtrack_pos. */
8177 str
= backtrack_pos
;
8178 inst
.error
= backtrack_error
;
8179 inst
.operands
[backtrack_index
].present
= 0;
8180 i
= backtrack_index
;
8184 /* Check that we have parsed all the arguments. */
8185 if (*str
!= '\0' && !inst
.error
)
8186 inst
.error
= _("garbage following instruction");
8188 return inst
.error
? FAIL
: SUCCESS
;
8191 #undef po_char_or_fail
8192 #undef po_reg_or_fail
8193 #undef po_reg_or_goto
8194 #undef po_imm_or_fail
8195 #undef po_scalar_or_fail
8196 #undef po_barrier_or_imm
8198 /* Shorthand macro for instruction encoding functions issuing errors. */
8199 #define constraint(expr, err) \
8210 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8211 instructions are unpredictable if these registers are used. This
8212 is the BadReg predicate in ARM's Thumb-2 documentation.
8214 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8215 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8216 #define reject_bad_reg(reg) \
8218 if (reg == REG_PC) \
8220 inst.error = BAD_PC; \
8223 else if (reg == REG_SP \
8224 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8226 inst.error = BAD_SP; \
8231 /* If REG is R13 (the stack pointer), warn that its use is
8233 #define warn_deprecated_sp(reg) \
8235 if (warn_on_deprecated && reg == REG_SP) \
8236 as_tsktsk (_("use of r13 is deprecated")); \
8239 /* Functions for operand encoding. ARM, then Thumb. */
8241 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8243 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8245 The only binary encoding difference is the Coprocessor number. Coprocessor
8246 9 is used for half-precision calculations or conversions. The format of the
8247 instruction is the same as the equivalent Coprocessor 10 instruction that
8248 exists for Single-Precision operation. */
8251 do_scalar_fp16_v82_encode (void)
8253 if (inst
.cond
< COND_ALWAYS
)
8254 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8255 " the behaviour is UNPREDICTABLE"));
8256 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8259 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8260 mark_feature_used (&arm_ext_fp16
);
8263 /* If VAL can be encoded in the immediate field of an ARM instruction,
8264 return the encoded form. Otherwise, return FAIL. */
8267 encode_arm_immediate (unsigned int val
)
8274 for (i
= 2; i
< 32; i
+= 2)
8275 if ((a
= rotate_left (val
, i
)) <= 0xff)
8276 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8281 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8282 return the encoded form. Otherwise, return FAIL. */
8284 encode_thumb32_immediate (unsigned int val
)
8291 for (i
= 1; i
<= 24; i
++)
8294 if ((val
& ~(0xff << i
)) == 0)
8295 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8299 if (val
== ((a
<< 16) | a
))
8301 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8305 if (val
== ((a
<< 16) | a
))
8306 return 0x200 | (a
>> 8);
8310 /* Encode a VFP SP or DP register number into inst.instruction. */
8313 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8315 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8318 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8321 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8324 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8329 first_error (_("D register out of range for selected VFP version"));
8337 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8341 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8345 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8349 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8353 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8357 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8365 /* Encode a <shift> in an ARM-format instruction. The immediate,
8366 if any, is handled by md_apply_fix. */
8368 encode_arm_shift (int i
)
8370 /* register-shifted register. */
8371 if (inst
.operands
[i
].immisreg
)
8374 for (op_index
= 0; op_index
<= i
; ++op_index
)
8376 /* Check the operand only when it's presented. In pre-UAL syntax,
8377 if the destination register is the same as the first operand, two
8378 register form of the instruction can be used. */
8379 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8380 && inst
.operands
[op_index
].reg
== REG_PC
)
8381 as_warn (UNPRED_REG ("r15"));
8384 if (inst
.operands
[i
].imm
== REG_PC
)
8385 as_warn (UNPRED_REG ("r15"));
8388 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8389 inst
.instruction
|= SHIFT_ROR
<< 5;
8392 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8393 if (inst
.operands
[i
].immisreg
)
8395 inst
.instruction
|= SHIFT_BY_REG
;
8396 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8399 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8404 encode_arm_shifter_operand (int i
)
8406 if (inst
.operands
[i
].isreg
)
8408 inst
.instruction
|= inst
.operands
[i
].reg
;
8409 encode_arm_shift (i
);
8413 inst
.instruction
|= INST_IMMEDIATE
;
8414 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8415 inst
.instruction
|= inst
.operands
[i
].imm
;
8419 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8421 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8424 Generate an error if the operand is not a register. */
8425 constraint (!inst
.operands
[i
].isreg
,
8426 _("Instruction does not support =N addresses"));
8428 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8430 if (inst
.operands
[i
].preind
)
8434 inst
.error
= _("instruction does not accept preindexed addressing");
8437 inst
.instruction
|= PRE_INDEX
;
8438 if (inst
.operands
[i
].writeback
)
8439 inst
.instruction
|= WRITE_BACK
;
8442 else if (inst
.operands
[i
].postind
)
8444 gas_assert (inst
.operands
[i
].writeback
);
8446 inst
.instruction
|= WRITE_BACK
;
8448 else /* unindexed - only for coprocessor */
8450 inst
.error
= _("instruction does not accept unindexed addressing");
8454 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8455 && (((inst
.instruction
& 0x000f0000) >> 16)
8456 == ((inst
.instruction
& 0x0000f000) >> 12)))
8457 as_warn ((inst
.instruction
& LOAD_BIT
)
8458 ? _("destination register same as write-back base")
8459 : _("source register same as write-back base"));
8462 /* inst.operands[i] was set up by parse_address. Encode it into an
8463 ARM-format mode 2 load or store instruction. If is_t is true,
8464 reject forms that cannot be used with a T instruction (i.e. not
8467 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8469 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8471 encode_arm_addr_mode_common (i
, is_t
);
8473 if (inst
.operands
[i
].immisreg
)
8475 constraint ((inst
.operands
[i
].imm
== REG_PC
8476 || (is_pc
&& inst
.operands
[i
].writeback
)),
8478 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8479 inst
.instruction
|= inst
.operands
[i
].imm
;
8480 if (!inst
.operands
[i
].negative
)
8481 inst
.instruction
|= INDEX_UP
;
8482 if (inst
.operands
[i
].shifted
)
8484 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8485 inst
.instruction
|= SHIFT_ROR
<< 5;
8488 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8489 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8493 else /* immediate offset in inst.relocs[0] */
8495 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8497 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8499 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8500 cannot use PC in addressing.
8501 PC cannot be used in writeback addressing, either. */
8502 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8505 /* Use of PC in str is deprecated for ARMv7. */
8506 if (warn_on_deprecated
8508 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8509 as_tsktsk (_("use of PC in this instruction is deprecated"));
8512 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8514 /* Prefer + for zero encoded value. */
8515 if (!inst
.operands
[i
].negative
)
8516 inst
.instruction
|= INDEX_UP
;
8517 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8522 /* inst.operands[i] was set up by parse_address. Encode it into an
8523 ARM-format mode 3 load or store instruction. Reject forms that
8524 cannot be used with such instructions. If is_t is true, reject
8525 forms that cannot be used with a T instruction (i.e. not
8528 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8530 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8532 inst
.error
= _("instruction does not accept scaled register index");
8536 encode_arm_addr_mode_common (i
, is_t
);
8538 if (inst
.operands
[i
].immisreg
)
8540 constraint ((inst
.operands
[i
].imm
== REG_PC
8541 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8543 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8545 inst
.instruction
|= inst
.operands
[i
].imm
;
8546 if (!inst
.operands
[i
].negative
)
8547 inst
.instruction
|= INDEX_UP
;
8549 else /* immediate offset in inst.relocs[0] */
8551 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8552 && inst
.operands
[i
].writeback
),
8554 inst
.instruction
|= HWOFFSET_IMM
;
8555 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8557 /* Prefer + for zero encoded value. */
8558 if (!inst
.operands
[i
].negative
)
8559 inst
.instruction
|= INDEX_UP
;
8561 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8566 /* Write immediate bits [7:0] to the following locations:
8568 |28/24|23 19|18 16|15 4|3 0|
8569 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8571 This function is used by VMOV/VMVN/VORR/VBIC. */
8574 neon_write_immbits (unsigned immbits
)
8576 inst
.instruction
|= immbits
& 0xf;
8577 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8578 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8581 /* Invert low-order SIZE bits of XHI:XLO. */
8584 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8586 unsigned immlo
= xlo
? *xlo
: 0;
8587 unsigned immhi
= xhi
? *xhi
: 0;
8592 immlo
= (~immlo
) & 0xff;
8596 immlo
= (~immlo
) & 0xffff;
8600 immhi
= (~immhi
) & 0xffffffff;
8604 immlo
= (~immlo
) & 0xffffffff;
8618 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8622 neon_bits_same_in_bytes (unsigned imm
)
8624 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8625 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8626 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8627 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8630 /* For immediate of above form, return 0bABCD. */
8633 neon_squash_bits (unsigned imm
)
8635 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8636 | ((imm
& 0x01000000) >> 21);
8639 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8642 neon_qfloat_bits (unsigned imm
)
8644 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8647 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8648 the instruction. *OP is passed as the initial value of the op field, and
8649 may be set to a different value depending on the constant (i.e.
8650 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8651 MVN). If the immediate looks like a repeated pattern then also
8652 try smaller element sizes. */
8655 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8656 unsigned *immbits
, int *op
, int size
,
8657 enum neon_el_type type
)
8659 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8661 if (type
== NT_float
&& !float_p
)
8664 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8666 if (size
!= 32 || *op
== 1)
8668 *immbits
= neon_qfloat_bits (immlo
);
8674 if (neon_bits_same_in_bytes (immhi
)
8675 && neon_bits_same_in_bytes (immlo
))
8679 *immbits
= (neon_squash_bits (immhi
) << 4)
8680 | neon_squash_bits (immlo
);
8691 if (immlo
== (immlo
& 0x000000ff))
8696 else if (immlo
== (immlo
& 0x0000ff00))
8698 *immbits
= immlo
>> 8;
8701 else if (immlo
== (immlo
& 0x00ff0000))
8703 *immbits
= immlo
>> 16;
8706 else if (immlo
== (immlo
& 0xff000000))
8708 *immbits
= immlo
>> 24;
8711 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8713 *immbits
= (immlo
>> 8) & 0xff;
8716 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8718 *immbits
= (immlo
>> 16) & 0xff;
8722 if ((immlo
& 0xffff) != (immlo
>> 16))
8729 if (immlo
== (immlo
& 0x000000ff))
8734 else if (immlo
== (immlo
& 0x0000ff00))
8736 *immbits
= immlo
>> 8;
8740 if ((immlo
& 0xff) != (immlo
>> 8))
8745 if (immlo
== (immlo
& 0x000000ff))
8747 /* Don't allow MVN with 8-bit immediate. */
8757 #if defined BFD_HOST_64_BIT
8758 /* Returns TRUE if double precision value V may be cast
8759 to single precision without loss of accuracy. */
8762 is_double_a_single (bfd_int64_t v
)
8764 int exp
= (int)((v
>> 52) & 0x7FF);
8765 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8767 return (exp
== 0 || exp
== 0x7FF
8768 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8769 && (mantissa
& 0x1FFFFFFFl
) == 0;
8772 /* Returns a double precision value casted to single precision
8773 (ignoring the least significant bits in exponent and mantissa). */
8776 double_to_single (bfd_int64_t v
)
8778 int sign
= (int) ((v
>> 63) & 1l);
8779 int exp
= (int) ((v
>> 52) & 0x7FF);
8780 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8786 exp
= exp
- 1023 + 127;
8795 /* No denormalized numbers. */
8801 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8803 #endif /* BFD_HOST_64_BIT */
8812 static void do_vfp_nsyn_opcode (const char *);
8814 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8815 Determine whether it can be performed with a move instruction; if
8816 it can, convert inst.instruction to that move instruction and
8817 return TRUE; if it can't, convert inst.instruction to a literal-pool
8818 load and return FALSE. If this is not a valid thing to do in the
8819 current context, set inst.error and return TRUE.
8821 inst.operands[i] describes the destination register. */
8824 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8827 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8828 bfd_boolean arm_p
= (t
== CONST_ARM
);
8831 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8835 if ((inst
.instruction
& tbit
) == 0)
8837 inst
.error
= _("invalid pseudo operation");
8841 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8842 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8843 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8845 inst
.error
= _("constant expression expected");
8849 if (inst
.relocs
[0].exp
.X_op
== O_constant
8850 || inst
.relocs
[0].exp
.X_op
== O_big
)
8852 #if defined BFD_HOST_64_BIT
8857 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8859 LITTLENUM_TYPE w
[X_PRECISION
];
8862 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8864 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8866 /* FIXME: Should we check words w[2..5] ? */
8871 #if defined BFD_HOST_64_BIT
8873 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8874 << LITTLENUM_NUMBER_OF_BITS
)
8875 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8876 << LITTLENUM_NUMBER_OF_BITS
)
8877 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8878 << LITTLENUM_NUMBER_OF_BITS
)
8879 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8881 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8882 | (l
[0] & LITTLENUM_MASK
);
8886 v
= inst
.relocs
[0].exp
.X_add_number
;
8888 if (!inst
.operands
[i
].issingle
)
8892 /* LDR should not use lead in a flag-setting instruction being
8893 chosen so we do not check whether movs can be used. */
8895 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8896 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8897 && inst
.operands
[i
].reg
!= 13
8898 && inst
.operands
[i
].reg
!= 15)
8900 /* Check if on thumb2 it can be done with a mov.w, mvn or
8901 movw instruction. */
8902 unsigned int newimm
;
8903 bfd_boolean isNegated
;
8905 newimm
= encode_thumb32_immediate (v
);
8906 if (newimm
!= (unsigned int) FAIL
)
8910 newimm
= encode_thumb32_immediate (~v
);
8911 if (newimm
!= (unsigned int) FAIL
)
8915 /* The number can be loaded with a mov.w or mvn
8917 if (newimm
!= (unsigned int) FAIL
8918 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8920 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8921 | (inst
.operands
[i
].reg
<< 8));
8922 /* Change to MOVN. */
8923 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8924 inst
.instruction
|= (newimm
& 0x800) << 15;
8925 inst
.instruction
|= (newimm
& 0x700) << 4;
8926 inst
.instruction
|= (newimm
& 0x0ff);
8929 /* The number can be loaded with a movw instruction. */
8930 else if ((v
& ~0xFFFF) == 0
8931 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8933 int imm
= v
& 0xFFFF;
8935 inst
.instruction
= 0xf2400000; /* MOVW. */
8936 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8937 inst
.instruction
|= (imm
& 0xf000) << 4;
8938 inst
.instruction
|= (imm
& 0x0800) << 15;
8939 inst
.instruction
|= (imm
& 0x0700) << 4;
8940 inst
.instruction
|= (imm
& 0x00ff);
8941 /* In case this replacement is being done on Armv8-M
8942 Baseline we need to make sure to disable the
8943 instruction size check, as otherwise GAS will reject
8944 the use of this T32 instruction. */
8952 int value
= encode_arm_immediate (v
);
8956 /* This can be done with a mov instruction. */
8957 inst
.instruction
&= LITERAL_MASK
;
8958 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8959 inst
.instruction
|= value
& 0xfff;
8963 value
= encode_arm_immediate (~ v
);
8966 /* This can be done with a mvn instruction. */
8967 inst
.instruction
&= LITERAL_MASK
;
8968 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8969 inst
.instruction
|= value
& 0xfff;
8973 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8976 unsigned immbits
= 0;
8977 unsigned immlo
= inst
.operands
[1].imm
;
8978 unsigned immhi
= inst
.operands
[1].regisimm
8979 ? inst
.operands
[1].reg
8980 : inst
.relocs
[0].exp
.X_unsigned
8982 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8983 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8984 &op
, 64, NT_invtype
);
8988 neon_invert_size (&immlo
, &immhi
, 64);
8990 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8991 &op
, 64, NT_invtype
);
8996 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
9002 /* Fill other bits in vmov encoding for both thumb and arm. */
9004 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9006 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9007 neon_write_immbits (immbits
);
9015 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9016 if (inst
.operands
[i
].issingle
9017 && is_quarter_float (inst
.operands
[1].imm
)
9018 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9020 inst
.operands
[1].imm
=
9021 neon_qfloat_bits (v
);
9022 do_vfp_nsyn_opcode ("fconsts");
9026 /* If our host does not support a 64-bit type then we cannot perform
9027 the following optimization. This mean that there will be a
9028 discrepancy between the output produced by an assembler built for
9029 a 32-bit-only host and the output produced from a 64-bit host, but
9030 this cannot be helped. */
9031 #if defined BFD_HOST_64_BIT
9032 else if (!inst
.operands
[1].issingle
9033 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9035 if (is_double_a_single (v
)
9036 && is_quarter_float (double_to_single (v
)))
9038 inst
.operands
[1].imm
=
9039 neon_qfloat_bits (double_to_single (v
));
9040 do_vfp_nsyn_opcode ("fconstd");
9048 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9049 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9052 inst
.operands
[1].reg
= REG_PC
;
9053 inst
.operands
[1].isreg
= 1;
9054 inst
.operands
[1].preind
= 1;
9055 inst
.relocs
[0].pc_rel
= 1;
9056 inst
.relocs
[0].type
= (thumb_p
9057 ? BFD_RELOC_ARM_THUMB_OFFSET
9059 ? BFD_RELOC_ARM_HWLITERAL
9060 : BFD_RELOC_ARM_LITERAL
));
9064 /* inst.operands[i] was set up by parse_address. Encode it into an
9065 ARM-format instruction. Reject all forms which cannot be encoded
9066 into a coprocessor load/store instruction. If wb_ok is false,
9067 reject use of writeback; if unind_ok is false, reject use of
9068 unindexed addressing. If reloc_override is not 0, use it instead
9069 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9070 (in which case it is preserved). */
9073 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9075 if (!inst
.operands
[i
].isreg
)
9078 if (! inst
.operands
[0].isvec
)
9080 inst
.error
= _("invalid co-processor operand");
9083 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9087 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9089 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9091 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9093 gas_assert (!inst
.operands
[i
].writeback
);
9096 inst
.error
= _("instruction does not support unindexed addressing");
9099 inst
.instruction
|= inst
.operands
[i
].imm
;
9100 inst
.instruction
|= INDEX_UP
;
9104 if (inst
.operands
[i
].preind
)
9105 inst
.instruction
|= PRE_INDEX
;
9107 if (inst
.operands
[i
].writeback
)
9109 if (inst
.operands
[i
].reg
== REG_PC
)
9111 inst
.error
= _("pc may not be used with write-back");
9116 inst
.error
= _("instruction does not support writeback");
9119 inst
.instruction
|= WRITE_BACK
;
9123 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9124 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9125 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9126 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9129 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9131 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9134 /* Prefer + for zero encoded value. */
9135 if (!inst
.operands
[i
].negative
)
9136 inst
.instruction
|= INDEX_UP
;
9141 /* Functions for instruction encoding, sorted by sub-architecture.
9142 First some generics; their names are taken from the conventional
9143 bit positions for register arguments in ARM format instructions. */
9153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9159 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9166 inst
.instruction
|= inst
.operands
[1].reg
;
9172 inst
.instruction
|= inst
.operands
[0].reg
;
9173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9187 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9193 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9194 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9198 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9200 if (ARM_CPU_IS_ANY (cpu_variant
))
9202 as_tsktsk ("%s", msg
);
9205 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9217 unsigned Rn
= inst
.operands
[2].reg
;
9218 /* Enforce restrictions on SWP instruction. */
9219 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9221 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9222 _("Rn must not overlap other operands"));
9224 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9226 if (!check_obsolete (&arm_ext_v8
,
9227 _("swp{b} use is obsoleted for ARMv8 and later"))
9228 && warn_on_deprecated
9229 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9230 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9234 inst
.instruction
|= inst
.operands
[1].reg
;
9235 inst
.instruction
|= Rn
<< 16;
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9242 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9243 inst
.instruction
|= inst
.operands
[2].reg
;
9249 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9250 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9251 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9252 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9254 inst
.instruction
|= inst
.operands
[0].reg
;
9255 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9256 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9262 inst
.instruction
|= inst
.operands
[0].imm
;
9268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9269 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9272 /* ARM instructions, in alphabetical order by function name (except
9273 that wrapper functions appear immediately after the function they
9276 /* This is a pseudo-op of the form "adr rd, label" to be converted
9277 into a relative address of the form "add rd, pc, #label-.-8". */
9282 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9284 /* Frag hacking will turn this into a sub instruction if the offset turns
9285 out to be negative. */
9286 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9287 inst
.relocs
[0].pc_rel
= 1;
9288 inst
.relocs
[0].exp
.X_add_number
-= 8;
9290 if (support_interwork
9291 && inst
.relocs
[0].exp
.X_op
== O_symbol
9292 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9293 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9294 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9295 inst
.relocs
[0].exp
.X_add_number
|= 1;
9298 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9299 into a relative address of the form:
9300 add rd, pc, #low(label-.-8)"
9301 add rd, rd, #high(label-.-8)" */
9306 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9308 /* Frag hacking will turn this into a sub instruction if the offset turns
9309 out to be negative. */
9310 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9311 inst
.relocs
[0].pc_rel
= 1;
9312 inst
.size
= INSN_SIZE
* 2;
9313 inst
.relocs
[0].exp
.X_add_number
-= 8;
9315 if (support_interwork
9316 && inst
.relocs
[0].exp
.X_op
== O_symbol
9317 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9318 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9319 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9320 inst
.relocs
[0].exp
.X_add_number
|= 1;
9326 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9327 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9329 if (!inst
.operands
[1].present
)
9330 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9332 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9333 encode_arm_shifter_operand (2);
9339 if (inst
.operands
[0].present
)
9340 inst
.instruction
|= inst
.operands
[0].imm
;
9342 inst
.instruction
|= 0xf;
9348 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9349 constraint (msb
> 32, _("bit-field extends past end of register"));
9350 /* The instruction encoding stores the LSB and MSB,
9351 not the LSB and width. */
9352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9353 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9354 inst
.instruction
|= (msb
- 1) << 16;
9362 /* #0 in second position is alternative syntax for bfc, which is
9363 the same instruction but with REG_PC in the Rm field. */
9364 if (!inst
.operands
[1].isreg
)
9365 inst
.operands
[1].reg
= REG_PC
;
9367 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9368 constraint (msb
> 32, _("bit-field extends past end of register"));
9369 /* The instruction encoding stores the LSB and MSB,
9370 not the LSB and width. */
9371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9372 inst
.instruction
|= inst
.operands
[1].reg
;
9373 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9374 inst
.instruction
|= (msb
- 1) << 16;
9380 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9381 _("bit-field extends past end of register"));
9382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9383 inst
.instruction
|= inst
.operands
[1].reg
;
9384 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9385 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9388 /* ARM V5 breakpoint instruction (argument parse)
9389 BKPT <16 bit unsigned immediate>
9390 Instruction is not conditional.
9391 The bit pattern given in insns[] has the COND_ALWAYS condition,
9392 and it is an error if the caller tried to override that. */
9397 /* Top 12 of 16 bits to bits 19:8. */
9398 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9400 /* Bottom 4 of 16 bits to bits 3:0. */
9401 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9405 encode_branch (int default_reloc
)
9407 if (inst
.operands
[0].hasreloc
)
9409 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9410 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9411 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9412 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9413 ? BFD_RELOC_ARM_PLT32
9414 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9417 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9418 inst
.relocs
[0].pc_rel
= 1;
9425 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9426 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9429 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9436 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9438 if (inst
.cond
== COND_ALWAYS
)
9439 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9441 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9445 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9448 /* ARM V5 branch-link-exchange instruction (argument parse)
9449 BLX <target_addr> ie BLX(1)
9450 BLX{<condition>} <Rm> ie BLX(2)
9451 Unfortunately, there are two different opcodes for this mnemonic.
9452 So, the insns[].value is not used, and the code here zaps values
9453 into inst.instruction.
9454 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9459 if (inst
.operands
[0].isreg
)
9461 /* Arg is a register; the opcode provided by insns[] is correct.
9462 It is not illegal to do "blx pc", just useless. */
9463 if (inst
.operands
[0].reg
== REG_PC
)
9464 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9466 inst
.instruction
|= inst
.operands
[0].reg
;
9470 /* Arg is an address; this instruction cannot be executed
9471 conditionally, and the opcode must be adjusted.
9472 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9473 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9474 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9475 inst
.instruction
= 0xfa000000;
9476 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9483 bfd_boolean want_reloc
;
9485 if (inst
.operands
[0].reg
== REG_PC
)
9486 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9488 inst
.instruction
|= inst
.operands
[0].reg
;
9489 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9490 it is for ARMv4t or earlier. */
9491 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9492 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9493 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9497 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9502 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9506 /* ARM v5TEJ. Jump to Jazelle code. */
9511 if (inst
.operands
[0].reg
== REG_PC
)
9512 as_tsktsk (_("use of r15 in bxj is not really useful"));
9514 inst
.instruction
|= inst
.operands
[0].reg
;
9517 /* Co-processor data operation:
9518 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9519 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9523 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9524 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9525 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9526 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9527 inst
.instruction
|= inst
.operands
[4].reg
;
9528 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9534 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9535 encode_arm_shifter_operand (1);
9538 /* Transfer between coprocessor and ARM registers.
9539 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9544 No special properties. */
9546 struct deprecated_coproc_regs_s
9553 arm_feature_set deprecated
;
9554 arm_feature_set obsoleted
;
9555 const char *dep_msg
;
9556 const char *obs_msg
;
9559 #define DEPR_ACCESS_V8 \
9560 N_("This coprocessor register access is deprecated in ARMv8")
9562 /* Table of all deprecated coprocessor registers. */
9563 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9565 {15, 0, 7, 10, 5, /* CP15DMB. */
9566 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9567 DEPR_ACCESS_V8
, NULL
},
9568 {15, 0, 7, 10, 4, /* CP15DSB. */
9569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9570 DEPR_ACCESS_V8
, NULL
},
9571 {15, 0, 7, 5, 4, /* CP15ISB. */
9572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9573 DEPR_ACCESS_V8
, NULL
},
9574 {14, 6, 1, 0, 0, /* TEEHBR. */
9575 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9576 DEPR_ACCESS_V8
, NULL
},
9577 {14, 6, 0, 0, 0, /* TEECR. */
9578 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9579 DEPR_ACCESS_V8
, NULL
},
9582 #undef DEPR_ACCESS_V8
9584 static const size_t deprecated_coproc_reg_count
=
9585 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9593 Rd
= inst
.operands
[2].reg
;
9596 if (inst
.instruction
== 0xee000010
9597 || inst
.instruction
== 0xfe000010)
9599 reject_bad_reg (Rd
);
9600 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9602 constraint (Rd
== REG_SP
, BAD_SP
);
9607 if (inst
.instruction
== 0xe000010)
9608 constraint (Rd
== REG_PC
, BAD_PC
);
9611 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9613 const struct deprecated_coproc_regs_s
*r
=
9614 deprecated_coproc_regs
+ i
;
9616 if (inst
.operands
[0].reg
== r
->cp
9617 && inst
.operands
[1].imm
== r
->opc1
9618 && inst
.operands
[3].reg
== r
->crn
9619 && inst
.operands
[4].reg
== r
->crm
9620 && inst
.operands
[5].imm
== r
->opc2
)
9622 if (! ARM_CPU_IS_ANY (cpu_variant
)
9623 && warn_on_deprecated
9624 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9625 as_tsktsk ("%s", r
->dep_msg
);
9629 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9630 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9631 inst
.instruction
|= Rd
<< 12;
9632 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9633 inst
.instruction
|= inst
.operands
[4].reg
;
9634 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9637 /* Transfer between coprocessor register and pair of ARM registers.
9638 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9643 Two XScale instructions are special cases of these:
9645 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9646 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9648 Result unpredictable if Rd or Rn is R15. */
9655 Rd
= inst
.operands
[2].reg
;
9656 Rn
= inst
.operands
[3].reg
;
9660 reject_bad_reg (Rd
);
9661 reject_bad_reg (Rn
);
9665 constraint (Rd
== REG_PC
, BAD_PC
);
9666 constraint (Rn
== REG_PC
, BAD_PC
);
9669 /* Only check the MRRC{2} variants. */
9670 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9672 /* If Rd == Rn, error that the operation is
9673 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9674 constraint (Rd
== Rn
, BAD_OVERLAP
);
9677 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9678 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9679 inst
.instruction
|= Rd
<< 12;
9680 inst
.instruction
|= Rn
<< 16;
9681 inst
.instruction
|= inst
.operands
[4].reg
;
9687 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9688 if (inst
.operands
[1].present
)
9690 inst
.instruction
|= CPSI_MMOD
;
9691 inst
.instruction
|= inst
.operands
[1].imm
;
9698 inst
.instruction
|= inst
.operands
[0].imm
;
9704 unsigned Rd
, Rn
, Rm
;
9706 Rd
= inst
.operands
[0].reg
;
9707 Rn
= (inst
.operands
[1].present
9708 ? inst
.operands
[1].reg
: Rd
);
9709 Rm
= inst
.operands
[2].reg
;
9711 constraint ((Rd
== REG_PC
), BAD_PC
);
9712 constraint ((Rn
== REG_PC
), BAD_PC
);
9713 constraint ((Rm
== REG_PC
), BAD_PC
);
9715 inst
.instruction
|= Rd
<< 16;
9716 inst
.instruction
|= Rn
<< 0;
9717 inst
.instruction
|= Rm
<< 8;
9723 /* There is no IT instruction in ARM mode. We
9724 process it to do the validation as if in
9725 thumb mode, just in case the code gets
9726 assembled for thumb using the unified syntax. */
9731 set_pred_insn_type (IT_INSN
);
9732 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9733 now_pred
.cc
= inst
.operands
[0].imm
;
9737 /* If there is only one register in the register list,
9738 then return its register number. Otherwise return -1. */
9740 only_one_reg_in_list (int range
)
9742 int i
= ffs (range
) - 1;
9743 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9747 encode_ldmstm(int from_push_pop_mnem
)
9749 int base_reg
= inst
.operands
[0].reg
;
9750 int range
= inst
.operands
[1].imm
;
9753 inst
.instruction
|= base_reg
<< 16;
9754 inst
.instruction
|= range
;
9756 if (inst
.operands
[1].writeback
)
9757 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9759 if (inst
.operands
[0].writeback
)
9761 inst
.instruction
|= WRITE_BACK
;
9762 /* Check for unpredictable uses of writeback. */
9763 if (inst
.instruction
& LOAD_BIT
)
9765 /* Not allowed in LDM type 2. */
9766 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9767 && ((range
& (1 << REG_PC
)) == 0))
9768 as_warn (_("writeback of base register is UNPREDICTABLE"));
9769 /* Only allowed if base reg not in list for other types. */
9770 else if (range
& (1 << base_reg
))
9771 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9775 /* Not allowed for type 2. */
9776 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9777 as_warn (_("writeback of base register is UNPREDICTABLE"));
9778 /* Only allowed if base reg not in list, or first in list. */
9779 else if ((range
& (1 << base_reg
))
9780 && (range
& ((1 << base_reg
) - 1)))
9781 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9785 /* If PUSH/POP has only one register, then use the A2 encoding. */
9786 one_reg
= only_one_reg_in_list (range
);
9787 if (from_push_pop_mnem
&& one_reg
>= 0)
9789 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9791 if (is_push
&& one_reg
== 13 /* SP */)
9792 /* PR 22483: The A2 encoding cannot be used when
9793 pushing the stack pointer as this is UNPREDICTABLE. */
9796 inst
.instruction
&= A_COND_MASK
;
9797 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9798 inst
.instruction
|= one_reg
<< 12;
9805 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9808 /* ARMv5TE load-consecutive (argument parse)
9817 constraint (inst
.operands
[0].reg
% 2 != 0,
9818 _("first transfer register must be even"));
9819 constraint (inst
.operands
[1].present
9820 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9821 _("can only transfer two consecutive registers"));
9822 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9823 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9825 if (!inst
.operands
[1].present
)
9826 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9828 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9829 register and the first register written; we have to diagnose
9830 overlap between the base and the second register written here. */
9832 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9833 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9834 as_warn (_("base register written back, and overlaps "
9835 "second transfer register"));
9837 if (!(inst
.instruction
& V4_STR_BIT
))
9839 /* For an index-register load, the index register must not overlap the
9840 destination (even if not write-back). */
9841 if (inst
.operands
[2].immisreg
9842 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9843 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9844 as_warn (_("index register overlaps transfer register"));
9846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9847 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9853 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9854 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9855 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9856 || inst
.operands
[1].negative
9857 /* This can arise if the programmer has written
9859 or if they have mistakenly used a register name as the last
9862 It is very difficult to distinguish between these two cases
9863 because "rX" might actually be a label. ie the register
9864 name has been occluded by a symbol of the same name. So we
9865 just generate a general 'bad addressing mode' type error
9866 message and leave it up to the programmer to discover the
9867 true cause and fix their mistake. */
9868 || (inst
.operands
[1].reg
== REG_PC
),
9871 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9872 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9873 _("offset must be zero in ARM encoding"));
9875 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9879 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9885 constraint (inst
.operands
[0].reg
% 2 != 0,
9886 _("even register required"));
9887 constraint (inst
.operands
[1].present
9888 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9889 _("can only load two consecutive registers"));
9890 /* If op 1 were present and equal to PC, this function wouldn't
9891 have been called in the first place. */
9892 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9895 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9898 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9899 which is not a multiple of four is UNPREDICTABLE. */
9901 check_ldr_r15_aligned (void)
9903 constraint (!(inst
.operands
[1].immisreg
)
9904 && (inst
.operands
[0].reg
== REG_PC
9905 && inst
.operands
[1].reg
== REG_PC
9906 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9907 _("ldr to register 15 must be 4-byte aligned"));
9913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9914 if (!inst
.operands
[1].isreg
)
9915 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9917 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9918 check_ldr_r15_aligned ();
9924 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9926 if (inst
.operands
[1].preind
)
9928 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9929 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9930 _("this instruction requires a post-indexed address"));
9932 inst
.operands
[1].preind
= 0;
9933 inst
.operands
[1].postind
= 1;
9934 inst
.operands
[1].writeback
= 1;
9936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9937 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9940 /* Halfword and signed-byte load/store operations. */
9945 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 if (!inst
.operands
[1].isreg
)
9948 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9950 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9956 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9958 if (inst
.operands
[1].preind
)
9960 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9961 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9962 _("this instruction requires a post-indexed address"));
9964 inst
.operands
[1].preind
= 0;
9965 inst
.operands
[1].postind
= 1;
9966 inst
.operands
[1].writeback
= 1;
9968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9969 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9972 /* Co-processor register load/store.
9973 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9977 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9978 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9979 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9985 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9986 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9987 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9988 && !(inst
.instruction
& 0x00400000))
9989 as_tsktsk (_("Rd and Rm should be different in mla"));
9991 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9992 inst
.instruction
|= inst
.operands
[1].reg
;
9993 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9994 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10000 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10001 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10002 THUMB1_RELOC_ONLY
);
10003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10004 encode_arm_shifter_operand (1);
10007 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10014 top
= (inst
.instruction
& 0x00400000) != 0;
10015 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10016 _(":lower16: not allowed in this instruction"));
10017 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10018 _(":upper16: not allowed in this instruction"));
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10020 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10022 imm
= inst
.relocs
[0].exp
.X_add_number
;
10023 /* The value is in two pieces: 0:11, 16:19. */
10024 inst
.instruction
|= (imm
& 0x00000fff);
10025 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10030 do_vfp_nsyn_mrs (void)
10032 if (inst
.operands
[0].isvec
)
10034 if (inst
.operands
[1].reg
!= 1)
10035 first_error (_("operand 1 must be FPSCR"));
10036 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10037 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10038 do_vfp_nsyn_opcode ("fmstat");
10040 else if (inst
.operands
[1].isvec
)
10041 do_vfp_nsyn_opcode ("fmrx");
10049 do_vfp_nsyn_msr (void)
10051 if (inst
.operands
[0].isvec
)
10052 do_vfp_nsyn_opcode ("fmxr");
10062 unsigned Rt
= inst
.operands
[0].reg
;
10064 if (thumb_mode
&& Rt
== REG_SP
)
10066 inst
.error
= BAD_SP
;
10070 switch (inst
.operands
[1].reg
)
10072 /* MVFR2 is only valid for Armv8-A. */
10074 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10078 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10079 case 1: /* fpscr. */
10080 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10081 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10085 case 14: /* fpcxt_ns. */
10086 case 15: /* fpcxt_s. */
10087 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10088 _("selected processor does not support instruction"));
10091 case 2: /* fpscr_nzcvqc. */
10092 case 12: /* vpr. */
10094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10095 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10096 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10097 _("selected processor does not support instruction"));
10098 if (inst
.operands
[0].reg
!= 2
10099 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10100 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10107 /* APSR_ sets isvec. All other refs to PC are illegal. */
10108 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10110 inst
.error
= BAD_PC
;
10114 /* If we get through parsing the register name, we just insert the number
10115 generated into the instruction without further validation. */
10116 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10117 inst
.instruction
|= (Rt
<< 12);
10123 unsigned Rt
= inst
.operands
[1].reg
;
10126 reject_bad_reg (Rt
);
10127 else if (Rt
== REG_PC
)
10129 inst
.error
= BAD_PC
;
10133 switch (inst
.operands
[0].reg
)
10135 /* MVFR2 is only valid for Armv8-A. */
10137 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10141 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10142 case 1: /* fpcr. */
10143 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10144 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10148 case 14: /* fpcxt_ns. */
10149 case 15: /* fpcxt_s. */
10150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10151 _("selected processor does not support instruction"));
10154 case 2: /* fpscr_nzcvqc. */
10155 case 12: /* vpr. */
10157 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10158 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10159 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10160 _("selected processor does not support instruction"));
10161 if (inst
.operands
[0].reg
!= 2
10162 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10163 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10170 /* If we get through parsing the register name, we just insert the number
10171 generated into the instruction without further validation. */
10172 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10173 inst
.instruction
|= (Rt
<< 12);
10181 if (do_vfp_nsyn_mrs () == SUCCESS
)
10184 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10187 if (inst
.operands
[1].isreg
)
10189 br
= inst
.operands
[1].reg
;
10190 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10191 as_bad (_("bad register for mrs"));
10195 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10196 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10198 _("'APSR', 'CPSR' or 'SPSR' expected"));
10199 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10202 inst
.instruction
|= br
;
10205 /* Two possible forms:
10206 "{C|S}PSR_<field>, Rm",
10207 "{C|S}PSR_f, #expression". */
10212 if (do_vfp_nsyn_msr () == SUCCESS
)
10215 inst
.instruction
|= inst
.operands
[0].imm
;
10216 if (inst
.operands
[1].isreg
)
10217 inst
.instruction
|= inst
.operands
[1].reg
;
10220 inst
.instruction
|= INST_IMMEDIATE
;
10221 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10222 inst
.relocs
[0].pc_rel
= 0;
10229 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10231 if (!inst
.operands
[2].present
)
10232 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10233 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10234 inst
.instruction
|= inst
.operands
[1].reg
;
10235 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10237 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10238 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10239 as_tsktsk (_("Rd and Rm should be different in mul"));
10242 /* Long Multiply Parser
10243 UMULL RdLo, RdHi, Rm, Rs
10244 SMULL RdLo, RdHi, Rm, Rs
10245 UMLAL RdLo, RdHi, Rm, Rs
10246 SMLAL RdLo, RdHi, Rm, Rs. */
10251 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10252 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10253 inst
.instruction
|= inst
.operands
[2].reg
;
10254 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10256 /* rdhi and rdlo must be different. */
10257 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10258 as_tsktsk (_("rdhi and rdlo must be different"));
10260 /* rdhi, rdlo and rm must all be different before armv6. */
10261 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10262 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10263 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10264 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10270 if (inst
.operands
[0].present
10271 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10273 /* Architectural NOP hints are CPSR sets with no bits selected. */
10274 inst
.instruction
&= 0xf0000000;
10275 inst
.instruction
|= 0x0320f000;
10276 if (inst
.operands
[0].present
)
10277 inst
.instruction
|= inst
.operands
[0].imm
;
10281 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10282 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10283 Condition defaults to COND_ALWAYS.
10284 Error if Rd, Rn or Rm are R15. */
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10291 inst
.instruction
|= inst
.operands
[2].reg
;
10292 if (inst
.operands
[3].present
)
10293 encode_arm_shift (3);
10296 /* ARM V6 PKHTB (Argument Parse). */
10301 if (!inst
.operands
[3].present
)
10303 /* If the shift specifier is omitted, turn the instruction
10304 into pkhbt rd, rm, rn. */
10305 inst
.instruction
&= 0xfff00010;
10306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10307 inst
.instruction
|= inst
.operands
[1].reg
;
10308 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10313 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10314 inst
.instruction
|= inst
.operands
[2].reg
;
10315 encode_arm_shift (3);
10319 /* ARMv5TE: Preload-Cache
10320 MP Extensions: Preload for write
10324 Syntactically, like LDR with B=1, W=0, L=1. */
10329 constraint (!inst
.operands
[0].isreg
,
10330 _("'[' expected after PLD mnemonic"));
10331 constraint (inst
.operands
[0].postind
,
10332 _("post-indexed expression used in preload instruction"));
10333 constraint (inst
.operands
[0].writeback
,
10334 _("writeback used in preload instruction"));
10335 constraint (!inst
.operands
[0].preind
,
10336 _("unindexed addressing used in preload instruction"));
10337 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10340 /* ARMv7: PLI <addr_mode> */
10344 constraint (!inst
.operands
[0].isreg
,
10345 _("'[' expected after PLI mnemonic"));
10346 constraint (inst
.operands
[0].postind
,
10347 _("post-indexed expression used in preload instruction"));
10348 constraint (inst
.operands
[0].writeback
,
10349 _("writeback used in preload instruction"));
10350 constraint (!inst
.operands
[0].preind
,
10351 _("unindexed addressing used in preload instruction"));
10352 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10353 inst
.instruction
&= ~PRE_INDEX
;
10359 constraint (inst
.operands
[0].writeback
,
10360 _("push/pop do not support {reglist}^"));
10361 inst
.operands
[1] = inst
.operands
[0];
10362 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10363 inst
.operands
[0].isreg
= 1;
10364 inst
.operands
[0].writeback
= 1;
10365 inst
.operands
[0].reg
= REG_SP
;
10366 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10369 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10370 word at the specified address and the following word
10372 Unconditionally executed.
10373 Error if Rn is R15. */
10378 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10379 if (inst
.operands
[0].writeback
)
10380 inst
.instruction
|= WRITE_BACK
;
10383 /* ARM V6 ssat (argument parse). */
10388 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10389 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10390 inst
.instruction
|= inst
.operands
[2].reg
;
10392 if (inst
.operands
[3].present
)
10393 encode_arm_shift (3);
10396 /* ARM V6 usat (argument parse). */
10401 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10402 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10403 inst
.instruction
|= inst
.operands
[2].reg
;
10405 if (inst
.operands
[3].present
)
10406 encode_arm_shift (3);
10409 /* ARM V6 ssat16 (argument parse). */
10414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10415 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10416 inst
.instruction
|= inst
.operands
[2].reg
;
10422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10423 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10424 inst
.instruction
|= inst
.operands
[2].reg
;
10427 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10428 preserving the other bits.
10430 setend <endian_specifier>, where <endian_specifier> is either
10436 if (warn_on_deprecated
10437 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10438 as_tsktsk (_("setend use is deprecated for ARMv8"));
10440 if (inst
.operands
[0].imm
)
10441 inst
.instruction
|= 0x200;
10447 unsigned int Rm
= (inst
.operands
[1].present
10448 ? inst
.operands
[1].reg
10449 : inst
.operands
[0].reg
);
10451 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10452 inst
.instruction
|= Rm
;
10453 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10455 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10456 inst
.instruction
|= SHIFT_BY_REG
;
10457 /* PR 12854: Error on extraneous shifts. */
10458 constraint (inst
.operands
[2].shifted
,
10459 _("extraneous shift as part of operand to shift insn"));
10462 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10468 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10469 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10471 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10472 inst
.relocs
[0].pc_rel
= 0;
10478 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10479 inst
.relocs
[0].pc_rel
= 0;
10485 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10486 inst
.relocs
[0].pc_rel
= 0;
10492 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10493 _("selected processor does not support SETPAN instruction"));
10495 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10501 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10502 _("selected processor does not support SETPAN instruction"));
10504 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10507 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10508 SMLAxy{cond} Rd,Rm,Rs,Rn
10509 SMLAWy{cond} Rd,Rm,Rs,Rn
10510 Error if any register is R15. */
10515 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10516 inst
.instruction
|= inst
.operands
[1].reg
;
10517 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10518 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10521 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10522 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10523 Error if any register is R15.
10524 Warning if Rdlo == Rdhi. */
10529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10530 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10531 inst
.instruction
|= inst
.operands
[2].reg
;
10532 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10534 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10535 as_tsktsk (_("rdhi and rdlo must be different"));
10538 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10539 SMULxy{cond} Rd,Rm,Rs
10540 Error if any register is R15. */
10545 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10546 inst
.instruction
|= inst
.operands
[1].reg
;
10547 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10550 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10551 the same for both ARM and Thumb-2. */
10558 if (inst
.operands
[0].present
)
10560 reg
= inst
.operands
[0].reg
;
10561 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10566 inst
.instruction
|= reg
<< 16;
10567 inst
.instruction
|= inst
.operands
[1].imm
;
10568 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10569 inst
.instruction
|= WRITE_BACK
;
10572 /* ARM V6 strex (argument parse). */
10577 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10578 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10579 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10580 || inst
.operands
[2].negative
10581 /* See comment in do_ldrex(). */
10582 || (inst
.operands
[2].reg
== REG_PC
),
10585 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10586 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10588 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10589 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10590 _("offset must be zero in ARM encoding"));
10592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10593 inst
.instruction
|= inst
.operands
[1].reg
;
10594 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10595 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10599 do_t_strexbh (void)
10601 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10602 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10603 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10604 || inst
.operands
[2].negative
,
10607 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10608 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10616 constraint (inst
.operands
[1].reg
% 2 != 0,
10617 _("even register required"));
10618 constraint (inst
.operands
[2].present
10619 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10620 _("can only store two consecutive registers"));
10621 /* If op 2 were present and equal to PC, this function wouldn't
10622 have been called in the first place. */
10623 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10625 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10626 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10627 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10631 inst
.instruction
|= inst
.operands
[1].reg
;
10632 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10639 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10640 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10648 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10649 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10654 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10655 extends it to 32-bits, and adds the result to a value in another
10656 register. You can specify a rotation by 0, 8, 16, or 24 bits
10657 before extracting the 16-bit value.
10658 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10659 Condition defaults to COND_ALWAYS.
10660 Error if any register uses R15. */
10665 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10666 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10667 inst
.instruction
|= inst
.operands
[2].reg
;
10668 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10673 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10674 Condition defaults to COND_ALWAYS.
10675 Error if any register uses R15. */
10680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10681 inst
.instruction
|= inst
.operands
[1].reg
;
10682 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10685 /* VFP instructions. In a logical order: SP variant first, monad
10686 before dyad, arithmetic then move then load/store. */
10689 do_vfp_sp_monadic (void)
10691 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10692 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10696 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10700 do_vfp_sp_dyadic (void)
10702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10704 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10708 do_vfp_sp_compare_z (void)
10710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10714 do_vfp_dp_sp_cvt (void)
10716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10717 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10721 do_vfp_sp_dp_cvt (void)
10723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10724 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10728 do_vfp_reg_from_sp (void)
10730 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10731 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10734 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10735 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10739 do_vfp_reg2_from_sp2 (void)
10741 constraint (inst
.operands
[2].imm
!= 2,
10742 _("only two consecutive VFP SP registers allowed here"));
10743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10744 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10745 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10749 do_vfp_sp_from_reg (void)
10751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10752 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10756 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10760 do_vfp_sp2_from_reg2 (void)
10762 constraint (inst
.operands
[0].imm
!= 2,
10763 _("only two consecutive VFP SP registers allowed here"));
10764 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10765 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10766 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10770 do_vfp_sp_ldst (void)
10772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10773 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10777 do_vfp_dp_ldst (void)
10779 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10780 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10785 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10787 if (inst
.operands
[0].writeback
)
10788 inst
.instruction
|= WRITE_BACK
;
10790 constraint (ldstm_type
!= VFP_LDSTMIA
,
10791 _("this addressing mode requires base-register writeback"));
10792 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10793 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10794 inst
.instruction
|= inst
.operands
[1].imm
;
10798 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10802 if (inst
.operands
[0].writeback
)
10803 inst
.instruction
|= WRITE_BACK
;
10805 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10806 _("this addressing mode requires base-register writeback"));
10808 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10809 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10811 count
= inst
.operands
[1].imm
<< 1;
10812 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10815 inst
.instruction
|= count
;
10819 do_vfp_sp_ldstmia (void)
10821 vfp_sp_ldstm (VFP_LDSTMIA
);
10825 do_vfp_sp_ldstmdb (void)
10827 vfp_sp_ldstm (VFP_LDSTMDB
);
10831 do_vfp_dp_ldstmia (void)
10833 vfp_dp_ldstm (VFP_LDSTMIA
);
10837 do_vfp_dp_ldstmdb (void)
10839 vfp_dp_ldstm (VFP_LDSTMDB
);
10843 do_vfp_xp_ldstmia (void)
10845 vfp_dp_ldstm (VFP_LDSTMIAX
);
10849 do_vfp_xp_ldstmdb (void)
10851 vfp_dp_ldstm (VFP_LDSTMDBX
);
10855 do_vfp_dp_rd_rm (void)
10857 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10858 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10861 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10862 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10866 do_vfp_dp_rn_rd (void)
10868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10869 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10873 do_vfp_dp_rd_rn (void)
10875 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10876 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10880 do_vfp_dp_rd_rn_rm (void)
10882 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10883 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10886 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10887 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10888 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10892 do_vfp_dp_rd (void)
10894 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10898 do_vfp_dp_rm_rd_rn (void)
10900 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10901 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10904 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10905 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10906 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10909 /* VFPv3 instructions. */
10911 do_vfp_sp_const (void)
10913 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10914 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10915 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10919 do_vfp_dp_const (void)
10921 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10922 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10923 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10927 vfp_conv (int srcsize
)
10929 int immbits
= srcsize
- inst
.operands
[1].imm
;
10931 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10933 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10934 i.e. immbits must be in range 0 - 16. */
10935 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10938 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10940 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10941 i.e. immbits must be in range 0 - 31. */
10942 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10946 inst
.instruction
|= (immbits
& 1) << 5;
10947 inst
.instruction
|= (immbits
>> 1);
10951 do_vfp_sp_conv_16 (void)
10953 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10958 do_vfp_dp_conv_16 (void)
10960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10965 do_vfp_sp_conv_32 (void)
10967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10972 do_vfp_dp_conv_32 (void)
10974 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10978 /* FPA instructions. Also in a logical order. */
10983 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10984 inst
.instruction
|= inst
.operands
[1].reg
;
10988 do_fpa_ldmstm (void)
10990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10991 switch (inst
.operands
[1].imm
)
10993 case 1: inst
.instruction
|= CP_T_X
; break;
10994 case 2: inst
.instruction
|= CP_T_Y
; break;
10995 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
11000 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
11002 /* The instruction specified "ea" or "fd", so we can only accept
11003 [Rn]{!}. The instruction does not really support stacking or
11004 unstacking, so we have to emulate these by setting appropriate
11005 bits and offsets. */
11006 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11007 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11008 _("this instruction does not support indexing"));
11010 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11011 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11013 if (!(inst
.instruction
& INDEX_UP
))
11014 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11016 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11018 inst
.operands
[2].preind
= 0;
11019 inst
.operands
[2].postind
= 1;
11023 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11026 /* iWMMXt instructions: strictly in alphabetical order. */
11029 do_iwmmxt_tandorc (void)
11031 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11035 do_iwmmxt_textrc (void)
11037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11038 inst
.instruction
|= inst
.operands
[1].imm
;
11042 do_iwmmxt_textrm (void)
11044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11045 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11046 inst
.instruction
|= inst
.operands
[2].imm
;
11050 do_iwmmxt_tinsr (void)
11052 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11053 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11054 inst
.instruction
|= inst
.operands
[2].imm
;
11058 do_iwmmxt_tmia (void)
11060 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11061 inst
.instruction
|= inst
.operands
[1].reg
;
11062 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11066 do_iwmmxt_waligni (void)
11068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11069 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11070 inst
.instruction
|= inst
.operands
[2].reg
;
11071 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11075 do_iwmmxt_wmerge (void)
11077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11078 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11079 inst
.instruction
|= inst
.operands
[2].reg
;
11080 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11084 do_iwmmxt_wmov (void)
11086 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11089 inst
.instruction
|= inst
.operands
[1].reg
;
11093 do_iwmmxt_wldstbh (void)
11096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11098 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11100 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11101 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11105 do_iwmmxt_wldstw (void)
11107 /* RIWR_RIWC clears .isreg for a control register. */
11108 if (!inst
.operands
[0].isreg
)
11110 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11111 inst
.instruction
|= 0xf0000000;
11114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11115 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11119 do_iwmmxt_wldstd (void)
11121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11122 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11123 && inst
.operands
[1].immisreg
)
11125 inst
.instruction
&= ~0x1a000ff;
11126 inst
.instruction
|= (0xfU
<< 28);
11127 if (inst
.operands
[1].preind
)
11128 inst
.instruction
|= PRE_INDEX
;
11129 if (!inst
.operands
[1].negative
)
11130 inst
.instruction
|= INDEX_UP
;
11131 if (inst
.operands
[1].writeback
)
11132 inst
.instruction
|= WRITE_BACK
;
11133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11134 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11135 inst
.instruction
|= inst
.operands
[1].imm
;
11138 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11142 do_iwmmxt_wshufh (void)
11144 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11145 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11146 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11147 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11151 do_iwmmxt_wzero (void)
11153 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11154 inst
.instruction
|= inst
.operands
[0].reg
;
11155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11156 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11160 do_iwmmxt_wrwrwr_or_imm5 (void)
11162 if (inst
.operands
[2].isreg
)
11165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11166 _("immediate operand requires iWMMXt2"));
11168 if (inst
.operands
[2].imm
== 0)
11170 switch ((inst
.instruction
>> 20) & 0xf)
11176 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11177 inst
.operands
[2].imm
= 16;
11178 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11184 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11185 inst
.operands
[2].imm
= 32;
11186 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11193 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11195 wrn
= (inst
.instruction
>> 16) & 0xf;
11196 inst
.instruction
&= 0xff0fff0f;
11197 inst
.instruction
|= wrn
;
11198 /* Bail out here; the instruction is now assembled. */
11203 /* Map 32 -> 0, etc. */
11204 inst
.operands
[2].imm
&= 0x1f;
11205 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11209 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11210 operations first, then control, shift, and load/store. */
11212 /* Insns like "foo X,Y,Z". */
11215 do_mav_triple (void)
11217 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11218 inst
.instruction
|= inst
.operands
[1].reg
;
11219 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11222 /* Insns like "foo W,X,Y,Z".
11223 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11228 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11229 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11230 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11231 inst
.instruction
|= inst
.operands
[3].reg
;
11234 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11236 do_mav_dspsc (void)
11238 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11241 /* Maverick shift immediate instructions.
11242 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11243 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11246 do_mav_shift (void)
11248 int imm
= inst
.operands
[2].imm
;
11250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11253 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11254 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11255 Bit 4 should be 0. */
11256 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11258 inst
.instruction
|= imm
;
11261 /* XScale instructions. Also sorted arithmetic before move. */
11263 /* Xscale multiply-accumulate (argument parse)
11266 MIAxycc acc0,Rm,Rs. */
11271 inst
.instruction
|= inst
.operands
[1].reg
;
11272 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11275 /* Xscale move-accumulator-register (argument parse)
11277 MARcc acc0,RdLo,RdHi. */
11282 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11283 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11286 /* Xscale move-register-accumulator (argument parse)
11288 MRAcc RdLo,RdHi,acc0. */
11293 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11295 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11298 /* Encoding functions relevant only to Thumb. */
11300 /* inst.operands[i] is a shifted-register operand; encode
11301 it into inst.instruction in the format used by Thumb32. */
11304 encode_thumb32_shifted_operand (int i
)
11306 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11307 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11309 constraint (inst
.operands
[i
].immisreg
,
11310 _("shift by register not allowed in thumb mode"));
11311 inst
.instruction
|= inst
.operands
[i
].reg
;
11312 if (shift
== SHIFT_RRX
)
11313 inst
.instruction
|= SHIFT_ROR
<< 4;
11316 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11317 _("expression too complex"));
11319 constraint (value
> 32
11320 || (value
== 32 && (shift
== SHIFT_LSL
11321 || shift
== SHIFT_ROR
)),
11322 _("shift expression is too large"));
11326 else if (value
== 32)
11329 inst
.instruction
|= shift
<< 4;
11330 inst
.instruction
|= (value
& 0x1c) << 10;
11331 inst
.instruction
|= (value
& 0x03) << 6;
11336 /* inst.operands[i] was set up by parse_address. Encode it into a
11337 Thumb32 format load or store instruction. Reject forms that cannot
11338 be used with such instructions. If is_t is true, reject forms that
11339 cannot be used with a T instruction; if is_d is true, reject forms
11340 that cannot be used with a D instruction. If it is a store insn,
11341 reject PC in Rn. */
11344 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11346 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11348 constraint (!inst
.operands
[i
].isreg
,
11349 _("Instruction does not support =N addresses"));
11351 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11352 if (inst
.operands
[i
].immisreg
)
11354 constraint (is_pc
, BAD_PC_ADDRESSING
);
11355 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11356 constraint (inst
.operands
[i
].negative
,
11357 _("Thumb does not support negative register indexing"));
11358 constraint (inst
.operands
[i
].postind
,
11359 _("Thumb does not support register post-indexing"));
11360 constraint (inst
.operands
[i
].writeback
,
11361 _("Thumb does not support register indexing with writeback"));
11362 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11363 _("Thumb supports only LSL in shifted register indexing"));
11365 inst
.instruction
|= inst
.operands
[i
].imm
;
11366 if (inst
.operands
[i
].shifted
)
11368 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11369 _("expression too complex"));
11370 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11371 || inst
.relocs
[0].exp
.X_add_number
> 3,
11372 _("shift out of range"));
11373 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11375 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11377 else if (inst
.operands
[i
].preind
)
11379 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11380 constraint (is_t
&& inst
.operands
[i
].writeback
,
11381 _("cannot use writeback with this instruction"));
11382 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11383 BAD_PC_ADDRESSING
);
11387 inst
.instruction
|= 0x01000000;
11388 if (inst
.operands
[i
].writeback
)
11389 inst
.instruction
|= 0x00200000;
11393 inst
.instruction
|= 0x00000c00;
11394 if (inst
.operands
[i
].writeback
)
11395 inst
.instruction
|= 0x00000100;
11397 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11399 else if (inst
.operands
[i
].postind
)
11401 gas_assert (inst
.operands
[i
].writeback
);
11402 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11403 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11406 inst
.instruction
|= 0x00200000;
11408 inst
.instruction
|= 0x00000900;
11409 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11411 else /* unindexed - only for coprocessor */
11412 inst
.error
= _("instruction does not accept unindexed addressing");
11415 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11416 encodings (the latter only in post-V6T2 cores). The index is the
11417 value used in the insns table below. When there is more than one
11418 possible 16-bit encoding for the instruction, this table always
11420 Also contains several pseudo-instructions used during relaxation. */
11421 #define T16_32_TAB \
11422 X(_adc, 4140, eb400000), \
11423 X(_adcs, 4140, eb500000), \
11424 X(_add, 1c00, eb000000), \
11425 X(_adds, 1c00, eb100000), \
11426 X(_addi, 0000, f1000000), \
11427 X(_addis, 0000, f1100000), \
11428 X(_add_pc,000f, f20f0000), \
11429 X(_add_sp,000d, f10d0000), \
11430 X(_adr, 000f, f20f0000), \
11431 X(_and, 4000, ea000000), \
11432 X(_ands, 4000, ea100000), \
11433 X(_asr, 1000, fa40f000), \
11434 X(_asrs, 1000, fa50f000), \
11435 X(_b, e000, f000b000), \
11436 X(_bcond, d000, f0008000), \
11437 X(_bf, 0000, f040e001), \
11438 X(_bfcsel,0000, f000e001), \
11439 X(_bfx, 0000, f060e001), \
11440 X(_bfl, 0000, f000c001), \
11441 X(_bflx, 0000, f070e001), \
11442 X(_bic, 4380, ea200000), \
11443 X(_bics, 4380, ea300000), \
11444 X(_cinc, 0000, ea509000), \
11445 X(_cinv, 0000, ea50a000), \
11446 X(_cmn, 42c0, eb100f00), \
11447 X(_cmp, 2800, ebb00f00), \
11448 X(_cneg, 0000, ea50b000), \
11449 X(_cpsie, b660, f3af8400), \
11450 X(_cpsid, b670, f3af8600), \
11451 X(_cpy, 4600, ea4f0000), \
11452 X(_csel, 0000, ea508000), \
11453 X(_cset, 0000, ea5f900f), \
11454 X(_csetm, 0000, ea5fa00f), \
11455 X(_csinc, 0000, ea509000), \
11456 X(_csinv, 0000, ea50a000), \
11457 X(_csneg, 0000, ea50b000), \
11458 X(_dec_sp,80dd, f1ad0d00), \
11459 X(_dls, 0000, f040e001), \
11460 X(_dlstp, 0000, f000e001), \
11461 X(_eor, 4040, ea800000), \
11462 X(_eors, 4040, ea900000), \
11463 X(_inc_sp,00dd, f10d0d00), \
11464 X(_lctp, 0000, f00fe001), \
11465 X(_ldmia, c800, e8900000), \
11466 X(_ldr, 6800, f8500000), \
11467 X(_ldrb, 7800, f8100000), \
11468 X(_ldrh, 8800, f8300000), \
11469 X(_ldrsb, 5600, f9100000), \
11470 X(_ldrsh, 5e00, f9300000), \
11471 X(_ldr_pc,4800, f85f0000), \
11472 X(_ldr_pc2,4800, f85f0000), \
11473 X(_ldr_sp,9800, f85d0000), \
11474 X(_le, 0000, f00fc001), \
11475 X(_letp, 0000, f01fc001), \
11476 X(_lsl, 0000, fa00f000), \
11477 X(_lsls, 0000, fa10f000), \
11478 X(_lsr, 0800, fa20f000), \
11479 X(_lsrs, 0800, fa30f000), \
11480 X(_mov, 2000, ea4f0000), \
11481 X(_movs, 2000, ea5f0000), \
11482 X(_mul, 4340, fb00f000), \
11483 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11484 X(_mvn, 43c0, ea6f0000), \
11485 X(_mvns, 43c0, ea7f0000), \
11486 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11487 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11488 X(_orr, 4300, ea400000), \
11489 X(_orrs, 4300, ea500000), \
11490 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11491 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11492 X(_rev, ba00, fa90f080), \
11493 X(_rev16, ba40, fa90f090), \
11494 X(_revsh, bac0, fa90f0b0), \
11495 X(_ror, 41c0, fa60f000), \
11496 X(_rors, 41c0, fa70f000), \
11497 X(_sbc, 4180, eb600000), \
11498 X(_sbcs, 4180, eb700000), \
11499 X(_stmia, c000, e8800000), \
11500 X(_str, 6000, f8400000), \
11501 X(_strb, 7000, f8000000), \
11502 X(_strh, 8000, f8200000), \
11503 X(_str_sp,9000, f84d0000), \
11504 X(_sub, 1e00, eba00000), \
11505 X(_subs, 1e00, ebb00000), \
11506 X(_subi, 8000, f1a00000), \
11507 X(_subis, 8000, f1b00000), \
11508 X(_sxtb, b240, fa4ff080), \
11509 X(_sxth, b200, fa0ff080), \
11510 X(_tst, 4200, ea100f00), \
11511 X(_uxtb, b2c0, fa5ff080), \
11512 X(_uxth, b280, fa1ff080), \
11513 X(_nop, bf00, f3af8000), \
11514 X(_yield, bf10, f3af8001), \
11515 X(_wfe, bf20, f3af8002), \
11516 X(_wfi, bf30, f3af8003), \
11517 X(_wls, 0000, f040c001), \
11518 X(_wlstp, 0000, f000c001), \
11519 X(_sev, bf40, f3af8004), \
11520 X(_sevl, bf50, f3af8005), \
11521 X(_udf, de00, f7f0a000)
11523 /* To catch errors in encoding functions, the codes are all offset by
11524 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11525 as 16-bit instructions. */
11526 #define X(a,b,c) T_MNEM##a
11527 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11530 #define X(a,b,c) 0x##b
11531 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11532 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11535 #define X(a,b,c) 0x##c
11536 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11537 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11538 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11542 /* Thumb instruction encoders, in alphabetical order. */
11544 /* ADDW or SUBW. */
11547 do_t_add_sub_w (void)
11551 Rd
= inst
.operands
[0].reg
;
11552 Rn
= inst
.operands
[1].reg
;
11554 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11555 is the SP-{plus,minus}-immediate form of the instruction. */
11557 constraint (Rd
== REG_PC
, BAD_PC
);
11559 reject_bad_reg (Rd
);
11561 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11562 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11565 /* Parse an add or subtract instruction. We get here with inst.instruction
11566 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11569 do_t_add_sub (void)
11573 Rd
= inst
.operands
[0].reg
;
11574 Rs
= (inst
.operands
[1].present
11575 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11576 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11579 set_pred_insn_type_last ();
11581 if (unified_syntax
)
11584 bfd_boolean narrow
;
11587 flags
= (inst
.instruction
== T_MNEM_adds
11588 || inst
.instruction
== T_MNEM_subs
);
11590 narrow
= !in_pred_block ();
11592 narrow
= in_pred_block ();
11593 if (!inst
.operands
[2].isreg
)
11597 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11598 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11600 add
= (inst
.instruction
== T_MNEM_add
11601 || inst
.instruction
== T_MNEM_adds
);
11603 if (inst
.size_req
!= 4)
11605 /* Attempt to use a narrow opcode, with relaxation if
11607 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11608 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11609 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11610 opcode
= T_MNEM_add_sp
;
11611 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11612 opcode
= T_MNEM_add_pc
;
11613 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11616 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11618 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11622 inst
.instruction
= THUMB_OP16(opcode
);
11623 inst
.instruction
|= (Rd
<< 4) | Rs
;
11624 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11625 || (inst
.relocs
[0].type
11626 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11628 if (inst
.size_req
== 2)
11629 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11631 inst
.relax
= opcode
;
11635 constraint (inst
.size_req
== 2, BAD_HIREG
);
11637 if (inst
.size_req
== 4
11638 || (inst
.size_req
!= 2 && !opcode
))
11640 constraint ((inst
.relocs
[0].type
11641 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11642 && (inst
.relocs
[0].type
11643 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11644 THUMB1_RELOC_ONLY
);
11647 constraint (add
, BAD_PC
);
11648 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11649 _("only SUBS PC, LR, #const allowed"));
11650 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11651 _("expression too complex"));
11652 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11653 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11654 _("immediate value out of range"));
11655 inst
.instruction
= T2_SUBS_PC_LR
11656 | inst
.relocs
[0].exp
.X_add_number
;
11657 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11660 else if (Rs
== REG_PC
)
11662 /* Always use addw/subw. */
11663 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11664 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11669 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11672 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11674 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11676 inst
.instruction
|= Rd
<< 8;
11677 inst
.instruction
|= Rs
<< 16;
11682 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11683 unsigned int shift
= inst
.operands
[2].shift_kind
;
11685 Rn
= inst
.operands
[2].reg
;
11686 /* See if we can do this with a 16-bit instruction. */
11687 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11689 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11694 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11695 || inst
.instruction
== T_MNEM_add
)
11697 : T_OPCODE_SUB_R3
);
11698 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11702 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11704 /* Thumb-1 cores (except v6-M) require at least one high
11705 register in a narrow non flag setting add. */
11706 if (Rd
> 7 || Rn
> 7
11707 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11708 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11715 inst
.instruction
= T_OPCODE_ADD_HI
;
11716 inst
.instruction
|= (Rd
& 8) << 4;
11717 inst
.instruction
|= (Rd
& 7);
11718 inst
.instruction
|= Rn
<< 3;
11724 constraint (Rd
== REG_PC
, BAD_PC
);
11725 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11726 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11727 constraint (Rs
== REG_PC
, BAD_PC
);
11728 reject_bad_reg (Rn
);
11730 /* If we get here, it can't be done in 16 bits. */
11731 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11732 _("shift must be constant"));
11733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11734 inst
.instruction
|= Rd
<< 8;
11735 inst
.instruction
|= Rs
<< 16;
11736 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11737 _("shift value over 3 not allowed in thumb mode"));
11738 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11739 _("only LSL shift allowed in thumb mode"));
11740 encode_thumb32_shifted_operand (2);
11745 constraint (inst
.instruction
== T_MNEM_adds
11746 || inst
.instruction
== T_MNEM_subs
,
11749 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11751 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11752 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11755 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11756 ? 0x0000 : 0x8000);
11757 inst
.instruction
|= (Rd
<< 4) | Rs
;
11758 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11762 Rn
= inst
.operands
[2].reg
;
11763 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11765 /* We now have Rd, Rs, and Rn set to registers. */
11766 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11768 /* Can't do this for SUB. */
11769 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11770 inst
.instruction
= T_OPCODE_ADD_HI
;
11771 inst
.instruction
|= (Rd
& 8) << 4;
11772 inst
.instruction
|= (Rd
& 7);
11774 inst
.instruction
|= Rn
<< 3;
11776 inst
.instruction
|= Rs
<< 3;
11778 constraint (1, _("dest must overlap one source register"));
11782 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11783 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11784 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11794 Rd
= inst
.operands
[0].reg
;
11795 reject_bad_reg (Rd
);
11797 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11799 /* Defer to section relaxation. */
11800 inst
.relax
= inst
.instruction
;
11801 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11802 inst
.instruction
|= Rd
<< 4;
11804 else if (unified_syntax
&& inst
.size_req
!= 2)
11806 /* Generate a 32-bit opcode. */
11807 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11808 inst
.instruction
|= Rd
<< 8;
11809 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11810 inst
.relocs
[0].pc_rel
= 1;
11814 /* Generate a 16-bit opcode. */
11815 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11816 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11817 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11818 inst
.relocs
[0].pc_rel
= 1;
11819 inst
.instruction
|= Rd
<< 4;
11822 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11823 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11824 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11825 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11826 inst
.relocs
[0].exp
.X_add_number
+= 1;
11829 /* Arithmetic instructions for which there is just one 16-bit
11830 instruction encoding, and it allows only two low registers.
11831 For maximal compatibility with ARM syntax, we allow three register
11832 operands even when Thumb-32 instructions are not available, as long
11833 as the first two are identical. For instance, both "sbc r0,r1" and
11834 "sbc r0,r0,r1" are allowed. */
11840 Rd
= inst
.operands
[0].reg
;
11841 Rs
= (inst
.operands
[1].present
11842 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11843 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11844 Rn
= inst
.operands
[2].reg
;
11846 reject_bad_reg (Rd
);
11847 reject_bad_reg (Rs
);
11848 if (inst
.operands
[2].isreg
)
11849 reject_bad_reg (Rn
);
11851 if (unified_syntax
)
11853 if (!inst
.operands
[2].isreg
)
11855 /* For an immediate, we always generate a 32-bit opcode;
11856 section relaxation will shrink it later if possible. */
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11859 inst
.instruction
|= Rd
<< 8;
11860 inst
.instruction
|= Rs
<< 16;
11861 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11865 bfd_boolean narrow
;
11867 /* See if we can do this with a 16-bit instruction. */
11868 if (THUMB_SETS_FLAGS (inst
.instruction
))
11869 narrow
= !in_pred_block ();
11871 narrow
= in_pred_block ();
11873 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11875 if (inst
.operands
[2].shifted
)
11877 if (inst
.size_req
== 4)
11883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11884 inst
.instruction
|= Rd
;
11885 inst
.instruction
|= Rn
<< 3;
11889 /* If we get here, it can't be done in 16 bits. */
11890 constraint (inst
.operands
[2].shifted
11891 && inst
.operands
[2].immisreg
,
11892 _("shift must be constant"));
11893 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11894 inst
.instruction
|= Rd
<< 8;
11895 inst
.instruction
|= Rs
<< 16;
11896 encode_thumb32_shifted_operand (2);
11901 /* On its face this is a lie - the instruction does set the
11902 flags. However, the only supported mnemonic in this mode
11903 says it doesn't. */
11904 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11906 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11907 _("unshifted register required"));
11908 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11909 constraint (Rd
!= Rs
,
11910 _("dest and source1 must be the same register"));
11912 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11913 inst
.instruction
|= Rd
;
11914 inst
.instruction
|= Rn
<< 3;
11918 /* Similarly, but for instructions where the arithmetic operation is
11919 commutative, so we can allow either of them to be different from
11920 the destination operand in a 16-bit instruction. For instance, all
11921 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11928 Rd
= inst
.operands
[0].reg
;
11929 Rs
= (inst
.operands
[1].present
11930 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11931 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11932 Rn
= inst
.operands
[2].reg
;
11934 reject_bad_reg (Rd
);
11935 reject_bad_reg (Rs
);
11936 if (inst
.operands
[2].isreg
)
11937 reject_bad_reg (Rn
);
11939 if (unified_syntax
)
11941 if (!inst
.operands
[2].isreg
)
11943 /* For an immediate, we always generate a 32-bit opcode;
11944 section relaxation will shrink it later if possible. */
11945 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11946 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11947 inst
.instruction
|= Rd
<< 8;
11948 inst
.instruction
|= Rs
<< 16;
11949 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11953 bfd_boolean narrow
;
11955 /* See if we can do this with a 16-bit instruction. */
11956 if (THUMB_SETS_FLAGS (inst
.instruction
))
11957 narrow
= !in_pred_block ();
11959 narrow
= in_pred_block ();
11961 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11963 if (inst
.operands
[2].shifted
)
11965 if (inst
.size_req
== 4)
11972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11973 inst
.instruction
|= Rd
;
11974 inst
.instruction
|= Rn
<< 3;
11979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11980 inst
.instruction
|= Rd
;
11981 inst
.instruction
|= Rs
<< 3;
11986 /* If we get here, it can't be done in 16 bits. */
11987 constraint (inst
.operands
[2].shifted
11988 && inst
.operands
[2].immisreg
,
11989 _("shift must be constant"));
11990 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11991 inst
.instruction
|= Rd
<< 8;
11992 inst
.instruction
|= Rs
<< 16;
11993 encode_thumb32_shifted_operand (2);
11998 /* On its face this is a lie - the instruction does set the
11999 flags. However, the only supported mnemonic in this mode
12000 says it doesn't. */
12001 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12003 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
12004 _("unshifted register required"));
12005 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12007 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12008 inst
.instruction
|= Rd
;
12011 inst
.instruction
|= Rn
<< 3;
12013 inst
.instruction
|= Rs
<< 3;
12015 constraint (1, _("dest must overlap one source register"));
12023 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12024 constraint (msb
> 32, _("bit-field extends past end of register"));
12025 /* The instruction encoding stores the LSB and MSB,
12026 not the LSB and width. */
12027 Rd
= inst
.operands
[0].reg
;
12028 reject_bad_reg (Rd
);
12029 inst
.instruction
|= Rd
<< 8;
12030 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12031 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12032 inst
.instruction
|= msb
- 1;
12041 Rd
= inst
.operands
[0].reg
;
12042 reject_bad_reg (Rd
);
12044 /* #0 in second position is alternative syntax for bfc, which is
12045 the same instruction but with REG_PC in the Rm field. */
12046 if (!inst
.operands
[1].isreg
)
12050 Rn
= inst
.operands
[1].reg
;
12051 reject_bad_reg (Rn
);
12054 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12055 constraint (msb
> 32, _("bit-field extends past end of register"));
12056 /* The instruction encoding stores the LSB and MSB,
12057 not the LSB and width. */
12058 inst
.instruction
|= Rd
<< 8;
12059 inst
.instruction
|= Rn
<< 16;
12060 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12061 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12062 inst
.instruction
|= msb
- 1;
12070 Rd
= inst
.operands
[0].reg
;
12071 Rn
= inst
.operands
[1].reg
;
12073 reject_bad_reg (Rd
);
12074 reject_bad_reg (Rn
);
12076 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12077 _("bit-field extends past end of register"));
12078 inst
.instruction
|= Rd
<< 8;
12079 inst
.instruction
|= Rn
<< 16;
12080 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12081 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12082 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12085 /* ARM V5 Thumb BLX (argument parse)
12086 BLX <target_addr> which is BLX(1)
12087 BLX <Rm> which is BLX(2)
12088 Unfortunately, there are two different opcodes for this mnemonic.
12089 So, the insns[].value is not used, and the code here zaps values
12090 into inst.instruction.
12092 ??? How to take advantage of the additional two bits of displacement
12093 available in Thumb32 mode? Need new relocation? */
12098 set_pred_insn_type_last ();
12100 if (inst
.operands
[0].isreg
)
12102 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12103 /* We have a register, so this is BLX(2). */
12104 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12108 /* No register. This must be BLX(1). */
12109 inst
.instruction
= 0xf000e800;
12110 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12119 bfd_reloc_code_real_type reloc
;
12122 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12124 if (in_pred_block ())
12126 /* Conditional branches inside IT blocks are encoded as unconditional
12128 cond
= COND_ALWAYS
;
12133 if (cond
!= COND_ALWAYS
)
12134 opcode
= T_MNEM_bcond
;
12136 opcode
= inst
.instruction
;
12139 && (inst
.size_req
== 4
12140 || (inst
.size_req
!= 2
12141 && (inst
.operands
[0].hasreloc
12142 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12144 inst
.instruction
= THUMB_OP32(opcode
);
12145 if (cond
== COND_ALWAYS
)
12146 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12150 _("selected architecture does not support "
12151 "wide conditional branch instruction"));
12153 gas_assert (cond
!= 0xF);
12154 inst
.instruction
|= cond
<< 22;
12155 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12160 inst
.instruction
= THUMB_OP16(opcode
);
12161 if (cond
== COND_ALWAYS
)
12162 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12165 inst
.instruction
|= cond
<< 8;
12166 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12168 /* Allow section relaxation. */
12169 if (unified_syntax
&& inst
.size_req
!= 2)
12170 inst
.relax
= opcode
;
12172 inst
.relocs
[0].type
= reloc
;
12173 inst
.relocs
[0].pc_rel
= 1;
12176 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12177 between the two is the maximum immediate allowed - which is passed in
12180 do_t_bkpt_hlt1 (int range
)
12182 constraint (inst
.cond
!= COND_ALWAYS
,
12183 _("instruction is always unconditional"));
12184 if (inst
.operands
[0].present
)
12186 constraint (inst
.operands
[0].imm
> range
,
12187 _("immediate value out of range"));
12188 inst
.instruction
|= inst
.operands
[0].imm
;
12191 set_pred_insn_type (NEUTRAL_IT_INSN
);
12197 do_t_bkpt_hlt1 (63);
12203 do_t_bkpt_hlt1 (255);
12207 do_t_branch23 (void)
12209 set_pred_insn_type_last ();
12210 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12212 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12213 this file. We used to simply ignore the PLT reloc type here --
12214 the branch encoding is now needed to deal with TLSCALL relocs.
12215 So if we see a PLT reloc now, put it back to how it used to be to
12216 keep the preexisting behaviour. */
12217 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12218 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12220 #if defined(OBJ_COFF)
12221 /* If the destination of the branch is a defined symbol which does not have
12222 the THUMB_FUNC attribute, then we must be calling a function which has
12223 the (interfacearm) attribute. We look for the Thumb entry point to that
12224 function and change the branch to refer to that function instead. */
12225 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12226 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12227 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12228 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12229 inst
.relocs
[0].exp
.X_add_symbol
12230 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12237 set_pred_insn_type_last ();
12238 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12239 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12240 should cause the alignment to be checked once it is known. This is
12241 because BX PC only works if the instruction is word aligned. */
12249 set_pred_insn_type_last ();
12250 Rm
= inst
.operands
[0].reg
;
12251 reject_bad_reg (Rm
);
12252 inst
.instruction
|= Rm
<< 16;
12261 Rd
= inst
.operands
[0].reg
;
12262 Rm
= inst
.operands
[1].reg
;
12264 reject_bad_reg (Rd
);
12265 reject_bad_reg (Rm
);
12267 inst
.instruction
|= Rd
<< 8;
12268 inst
.instruction
|= Rm
<< 16;
12269 inst
.instruction
|= Rm
;
12272 /* For the Armv8.1-M conditional instructions. */
12276 unsigned Rd
, Rn
, Rm
;
12279 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12281 Rd
= inst
.operands
[0].reg
;
12282 switch (inst
.instruction
)
12288 Rn
= inst
.operands
[1].reg
;
12289 Rm
= inst
.operands
[2].reg
;
12290 cond
= inst
.operands
[3].imm
;
12291 constraint (Rn
== REG_SP
, BAD_SP
);
12292 constraint (Rm
== REG_SP
, BAD_SP
);
12298 Rn
= inst
.operands
[1].reg
;
12299 cond
= inst
.operands
[2].imm
;
12300 /* Invert the last bit to invert the cond. */
12301 cond
= TOGGLE_BIT (cond
, 0);
12302 constraint (Rn
== REG_SP
, BAD_SP
);
12308 cond
= inst
.operands
[1].imm
;
12309 /* Invert the last bit to invert the cond. */
12310 cond
= TOGGLE_BIT (cond
, 0);
12318 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12319 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12320 inst
.instruction
|= Rd
<< 8;
12321 inst
.instruction
|= Rn
<< 16;
12322 inst
.instruction
|= Rm
;
12323 inst
.instruction
|= cond
<< 4;
12329 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12335 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12336 inst
.instruction
|= inst
.operands
[0].imm
;
12342 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12344 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12345 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12347 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12348 inst
.instruction
= 0xf3af8000;
12349 inst
.instruction
|= imod
<< 9;
12350 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12351 if (inst
.operands
[1].present
)
12352 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12356 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12357 && (inst
.operands
[0].imm
& 4),
12358 _("selected processor does not support 'A' form "
12359 "of this instruction"));
12360 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12361 _("Thumb does not support the 2-argument "
12362 "form of this instruction"));
12363 inst
.instruction
|= inst
.operands
[0].imm
;
12367 /* THUMB CPY instruction (argument parse). */
12372 if (inst
.size_req
== 4)
12374 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12375 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12376 inst
.instruction
|= inst
.operands
[1].reg
;
12380 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12381 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12382 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12389 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12390 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12391 inst
.instruction
|= inst
.operands
[0].reg
;
12392 inst
.relocs
[0].pc_rel
= 1;
12393 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12399 inst
.instruction
|= inst
.operands
[0].imm
;
12405 unsigned Rd
, Rn
, Rm
;
12407 Rd
= inst
.operands
[0].reg
;
12408 Rn
= (inst
.operands
[1].present
12409 ? inst
.operands
[1].reg
: Rd
);
12410 Rm
= inst
.operands
[2].reg
;
12412 reject_bad_reg (Rd
);
12413 reject_bad_reg (Rn
);
12414 reject_bad_reg (Rm
);
12416 inst
.instruction
|= Rd
<< 8;
12417 inst
.instruction
|= Rn
<< 16;
12418 inst
.instruction
|= Rm
;
12424 if (unified_syntax
&& inst
.size_req
== 4)
12425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12427 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12433 unsigned int cond
= inst
.operands
[0].imm
;
12435 set_pred_insn_type (IT_INSN
);
12436 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12437 now_pred
.cc
= cond
;
12438 now_pred
.warn_deprecated
= FALSE
;
12439 now_pred
.type
= SCALAR_PRED
;
12441 /* If the condition is a negative condition, invert the mask. */
12442 if ((cond
& 0x1) == 0x0)
12444 unsigned int mask
= inst
.instruction
& 0x000f;
12446 if ((mask
& 0x7) == 0)
12448 /* No conversion needed. */
12449 now_pred
.block_length
= 1;
12451 else if ((mask
& 0x3) == 0)
12454 now_pred
.block_length
= 2;
12456 else if ((mask
& 0x1) == 0)
12459 now_pred
.block_length
= 3;
12464 now_pred
.block_length
= 4;
12467 inst
.instruction
&= 0xfff0;
12468 inst
.instruction
|= mask
;
12471 inst
.instruction
|= cond
<< 4;
12474 /* Helper function used for both push/pop and ldm/stm. */
12476 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12477 bfd_boolean writeback
)
12479 bfd_boolean load
, store
;
12481 gas_assert (base
!= -1 || !do_io
);
12482 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12483 store
= do_io
&& !load
;
12485 if (mask
& (1 << 13))
12486 inst
.error
= _("SP not allowed in register list");
12488 if (do_io
&& (mask
& (1 << base
)) != 0
12490 inst
.error
= _("having the base register in the register list when "
12491 "using write back is UNPREDICTABLE");
12495 if (mask
& (1 << 15))
12497 if (mask
& (1 << 14))
12498 inst
.error
= _("LR and PC should not both be in register list");
12500 set_pred_insn_type_last ();
12505 if (mask
& (1 << 15))
12506 inst
.error
= _("PC not allowed in register list");
12509 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12511 /* Single register transfers implemented as str/ldr. */
12514 if (inst
.instruction
& (1 << 23))
12515 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12517 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12521 if (inst
.instruction
& (1 << 23))
12522 inst
.instruction
= 0x00800000; /* ia -> [base] */
12524 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12527 inst
.instruction
|= 0xf8400000;
12529 inst
.instruction
|= 0x00100000;
12531 mask
= ffs (mask
) - 1;
12534 else if (writeback
)
12535 inst
.instruction
|= WRITE_BACK
;
12537 inst
.instruction
|= mask
;
12539 inst
.instruction
|= base
<< 16;
12545 /* This really doesn't seem worth it. */
12546 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12547 _("expression too complex"));
12548 constraint (inst
.operands
[1].writeback
,
12549 _("Thumb load/store multiple does not support {reglist}^"));
12551 if (unified_syntax
)
12553 bfd_boolean narrow
;
12557 /* See if we can use a 16-bit instruction. */
12558 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12559 && inst
.size_req
!= 4
12560 && !(inst
.operands
[1].imm
& ~0xff))
12562 mask
= 1 << inst
.operands
[0].reg
;
12564 if (inst
.operands
[0].reg
<= 7)
12566 if (inst
.instruction
== T_MNEM_stmia
12567 ? inst
.operands
[0].writeback
12568 : (inst
.operands
[0].writeback
12569 == !(inst
.operands
[1].imm
& mask
)))
12571 if (inst
.instruction
== T_MNEM_stmia
12572 && (inst
.operands
[1].imm
& mask
)
12573 && (inst
.operands
[1].imm
& (mask
- 1)))
12574 as_warn (_("value stored for r%d is UNKNOWN"),
12575 inst
.operands
[0].reg
);
12577 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12578 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12579 inst
.instruction
|= inst
.operands
[1].imm
;
12582 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12584 /* This means 1 register in reg list one of 3 situations:
12585 1. Instruction is stmia, but without writeback.
12586 2. lmdia without writeback, but with Rn not in
12588 3. ldmia with writeback, but with Rn in reglist.
12589 Case 3 is UNPREDICTABLE behaviour, so we handle
12590 case 1 and 2 which can be converted into a 16-bit
12591 str or ldr. The SP cases are handled below. */
12592 unsigned long opcode
;
12593 /* First, record an error for Case 3. */
12594 if (inst
.operands
[1].imm
& mask
12595 && inst
.operands
[0].writeback
)
12597 _("having the base register in the register list when "
12598 "using write back is UNPREDICTABLE");
12600 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12602 inst
.instruction
= THUMB_OP16 (opcode
);
12603 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12604 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12608 else if (inst
.operands
[0] .reg
== REG_SP
)
12610 if (inst
.operands
[0].writeback
)
12613 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12614 ? T_MNEM_push
: T_MNEM_pop
);
12615 inst
.instruction
|= inst
.operands
[1].imm
;
12618 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12621 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12622 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12623 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12631 if (inst
.instruction
< 0xffff)
12632 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12634 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12635 inst
.operands
[1].imm
,
12636 inst
.operands
[0].writeback
);
12641 constraint (inst
.operands
[0].reg
> 7
12642 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12643 constraint (inst
.instruction
!= T_MNEM_ldmia
12644 && inst
.instruction
!= T_MNEM_stmia
,
12645 _("Thumb-2 instruction only valid in unified syntax"));
12646 if (inst
.instruction
== T_MNEM_stmia
)
12648 if (!inst
.operands
[0].writeback
)
12649 as_warn (_("this instruction will write back the base register"));
12650 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12651 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12652 as_warn (_("value stored for r%d is UNKNOWN"),
12653 inst
.operands
[0].reg
);
12657 if (!inst
.operands
[0].writeback
12658 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12659 as_warn (_("this instruction will write back the base register"));
12660 else if (inst
.operands
[0].writeback
12661 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12662 as_warn (_("this instruction will not write back the base register"));
12665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12666 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12667 inst
.instruction
|= inst
.operands
[1].imm
;
12674 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12675 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12676 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12677 || inst
.operands
[1].negative
,
12680 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12683 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12684 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12690 if (!inst
.operands
[1].present
)
12692 constraint (inst
.operands
[0].reg
== REG_LR
,
12693 _("r14 not allowed as first register "
12694 "when second register is omitted"));
12695 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12697 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12701 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12702 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12708 unsigned long opcode
;
12711 if (inst
.operands
[0].isreg
12712 && !inst
.operands
[0].preind
12713 && inst
.operands
[0].reg
== REG_PC
)
12714 set_pred_insn_type_last ();
12716 opcode
= inst
.instruction
;
12717 if (unified_syntax
)
12719 if (!inst
.operands
[1].isreg
)
12721 if (opcode
<= 0xffff)
12722 inst
.instruction
= THUMB_OP32 (opcode
);
12723 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12726 if (inst
.operands
[1].isreg
12727 && !inst
.operands
[1].writeback
12728 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12729 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12730 && opcode
<= 0xffff
12731 && inst
.size_req
!= 4)
12733 /* Insn may have a 16-bit form. */
12734 Rn
= inst
.operands
[1].reg
;
12735 if (inst
.operands
[1].immisreg
)
12737 inst
.instruction
= THUMB_OP16 (opcode
);
12739 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12741 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12742 reject_bad_reg (inst
.operands
[1].imm
);
12744 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12745 && opcode
!= T_MNEM_ldrsb
)
12746 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12747 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12754 if (inst
.relocs
[0].pc_rel
)
12755 opcode
= T_MNEM_ldr_pc2
;
12757 opcode
= T_MNEM_ldr_pc
;
12761 if (opcode
== T_MNEM_ldr
)
12762 opcode
= T_MNEM_ldr_sp
;
12764 opcode
= T_MNEM_str_sp
;
12766 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12770 inst
.instruction
= inst
.operands
[0].reg
;
12771 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12773 inst
.instruction
|= THUMB_OP16 (opcode
);
12774 if (inst
.size_req
== 2)
12775 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12777 inst
.relax
= opcode
;
12781 /* Definitely a 32-bit variant. */
12783 /* Warning for Erratum 752419. */
12784 if (opcode
== T_MNEM_ldr
12785 && inst
.operands
[0].reg
== REG_SP
12786 && inst
.operands
[1].writeback
== 1
12787 && !inst
.operands
[1].immisreg
)
12789 if (no_cpu_selected ()
12790 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12791 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12792 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12793 as_warn (_("This instruction may be unpredictable "
12794 "if executed on M-profile cores "
12795 "with interrupts enabled."));
12798 /* Do some validations regarding addressing modes. */
12799 if (inst
.operands
[1].immisreg
)
12800 reject_bad_reg (inst
.operands
[1].imm
);
12802 constraint (inst
.operands
[1].writeback
== 1
12803 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12806 inst
.instruction
= THUMB_OP32 (opcode
);
12807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12808 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12809 check_ldr_r15_aligned ();
12813 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12815 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12817 /* Only [Rn,Rm] is acceptable. */
12818 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12819 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12820 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12821 || inst
.operands
[1].negative
,
12822 _("Thumb does not support this addressing mode"));
12823 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12827 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12828 if (!inst
.operands
[1].isreg
)
12829 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12832 constraint (!inst
.operands
[1].preind
12833 || inst
.operands
[1].shifted
12834 || inst
.operands
[1].writeback
,
12835 _("Thumb does not support this addressing mode"));
12836 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12838 constraint (inst
.instruction
& 0x0600,
12839 _("byte or halfword not valid for base register"));
12840 constraint (inst
.operands
[1].reg
== REG_PC
12841 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12842 _("r15 based store not allowed"));
12843 constraint (inst
.operands
[1].immisreg
,
12844 _("invalid base register for register offset"));
12846 if (inst
.operands
[1].reg
== REG_PC
)
12847 inst
.instruction
= T_OPCODE_LDR_PC
;
12848 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12849 inst
.instruction
= T_OPCODE_LDR_SP
;
12851 inst
.instruction
= T_OPCODE_STR_SP
;
12853 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12854 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12858 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12859 if (!inst
.operands
[1].immisreg
)
12861 /* Immediate offset. */
12862 inst
.instruction
|= inst
.operands
[0].reg
;
12863 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12864 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12868 /* Register offset. */
12869 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12870 constraint (inst
.operands
[1].negative
,
12871 _("Thumb does not support this addressing mode"));
12874 switch (inst
.instruction
)
12876 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12877 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12878 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12879 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12880 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12881 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12882 case 0x5600 /* ldrsb */:
12883 case 0x5e00 /* ldrsh */: break;
12887 inst
.instruction
|= inst
.operands
[0].reg
;
12888 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12889 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12895 if (!inst
.operands
[1].present
)
12897 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12898 constraint (inst
.operands
[0].reg
== REG_LR
,
12899 _("r14 not allowed here"));
12900 constraint (inst
.operands
[0].reg
== REG_R12
,
12901 _("r12 not allowed here"));
12904 if (inst
.operands
[2].writeback
12905 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12906 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12907 as_warn (_("base register written back, and overlaps "
12908 "one of transfer registers"));
12910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12911 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12912 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12919 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12925 unsigned Rd
, Rn
, Rm
, Ra
;
12927 Rd
= inst
.operands
[0].reg
;
12928 Rn
= inst
.operands
[1].reg
;
12929 Rm
= inst
.operands
[2].reg
;
12930 Ra
= inst
.operands
[3].reg
;
12932 reject_bad_reg (Rd
);
12933 reject_bad_reg (Rn
);
12934 reject_bad_reg (Rm
);
12935 reject_bad_reg (Ra
);
12937 inst
.instruction
|= Rd
<< 8;
12938 inst
.instruction
|= Rn
<< 16;
12939 inst
.instruction
|= Rm
;
12940 inst
.instruction
|= Ra
<< 12;
12946 unsigned RdLo
, RdHi
, Rn
, Rm
;
12948 RdLo
= inst
.operands
[0].reg
;
12949 RdHi
= inst
.operands
[1].reg
;
12950 Rn
= inst
.operands
[2].reg
;
12951 Rm
= inst
.operands
[3].reg
;
12953 reject_bad_reg (RdLo
);
12954 reject_bad_reg (RdHi
);
12955 reject_bad_reg (Rn
);
12956 reject_bad_reg (Rm
);
12958 inst
.instruction
|= RdLo
<< 12;
12959 inst
.instruction
|= RdHi
<< 8;
12960 inst
.instruction
|= Rn
<< 16;
12961 inst
.instruction
|= Rm
;
12965 do_t_mov_cmp (void)
12969 Rn
= inst
.operands
[0].reg
;
12970 Rm
= inst
.operands
[1].reg
;
12973 set_pred_insn_type_last ();
12975 if (unified_syntax
)
12977 int r0off
= (inst
.instruction
== T_MNEM_mov
12978 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12979 unsigned long opcode
;
12980 bfd_boolean narrow
;
12981 bfd_boolean low_regs
;
12983 low_regs
= (Rn
<= 7 && Rm
<= 7);
12984 opcode
= inst
.instruction
;
12985 if (in_pred_block ())
12986 narrow
= opcode
!= T_MNEM_movs
;
12988 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12989 if (inst
.size_req
== 4
12990 || inst
.operands
[1].shifted
)
12993 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12994 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12995 && !inst
.operands
[1].shifted
12999 inst
.instruction
= T2_SUBS_PC_LR
;
13003 if (opcode
== T_MNEM_cmp
)
13005 constraint (Rn
== REG_PC
, BAD_PC
);
13008 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13010 warn_deprecated_sp (Rm
);
13011 /* R15 was documented as a valid choice for Rm in ARMv6,
13012 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13013 tools reject R15, so we do too. */
13014 constraint (Rm
== REG_PC
, BAD_PC
);
13017 reject_bad_reg (Rm
);
13019 else if (opcode
== T_MNEM_mov
13020 || opcode
== T_MNEM_movs
)
13022 if (inst
.operands
[1].isreg
)
13024 if (opcode
== T_MNEM_movs
)
13026 reject_bad_reg (Rn
);
13027 reject_bad_reg (Rm
);
13031 /* This is mov.n. */
13032 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13033 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13035 as_tsktsk (_("Use of r%u as a source register is "
13036 "deprecated when r%u is the destination "
13037 "register."), Rm
, Rn
);
13042 /* This is mov.w. */
13043 constraint (Rn
== REG_PC
, BAD_PC
);
13044 constraint (Rm
== REG_PC
, BAD_PC
);
13045 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13046 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13050 reject_bad_reg (Rn
);
13053 if (!inst
.operands
[1].isreg
)
13055 /* Immediate operand. */
13056 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13058 if (low_regs
&& narrow
)
13060 inst
.instruction
= THUMB_OP16 (opcode
);
13061 inst
.instruction
|= Rn
<< 8;
13062 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13063 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13065 if (inst
.size_req
== 2)
13066 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13068 inst
.relax
= opcode
;
13073 constraint ((inst
.relocs
[0].type
13074 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13075 && (inst
.relocs
[0].type
13076 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13077 THUMB1_RELOC_ONLY
);
13079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13080 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13081 inst
.instruction
|= Rn
<< r0off
;
13082 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13085 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13086 && (inst
.instruction
== T_MNEM_mov
13087 || inst
.instruction
== T_MNEM_movs
))
13089 /* Register shifts are encoded as separate shift instructions. */
13090 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13092 if (in_pred_block ())
13097 if (inst
.size_req
== 4)
13100 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13106 switch (inst
.operands
[1].shift_kind
)
13109 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13112 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13115 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13118 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13124 inst
.instruction
= opcode
;
13127 inst
.instruction
|= Rn
;
13128 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13133 inst
.instruction
|= CONDS_BIT
;
13135 inst
.instruction
|= Rn
<< 8;
13136 inst
.instruction
|= Rm
<< 16;
13137 inst
.instruction
|= inst
.operands
[1].imm
;
13142 /* Some mov with immediate shift have narrow variants.
13143 Register shifts are handled above. */
13144 if (low_regs
&& inst
.operands
[1].shifted
13145 && (inst
.instruction
== T_MNEM_mov
13146 || inst
.instruction
== T_MNEM_movs
))
13148 if (in_pred_block ())
13149 narrow
= (inst
.instruction
== T_MNEM_mov
);
13151 narrow
= (inst
.instruction
== T_MNEM_movs
);
13156 switch (inst
.operands
[1].shift_kind
)
13158 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13159 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13160 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13161 default: narrow
= FALSE
; break;
13167 inst
.instruction
|= Rn
;
13168 inst
.instruction
|= Rm
<< 3;
13169 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13173 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13174 inst
.instruction
|= Rn
<< r0off
;
13175 encode_thumb32_shifted_operand (1);
13179 switch (inst
.instruction
)
13182 /* In v4t or v5t a move of two lowregs produces unpredictable
13183 results. Don't allow this. */
13186 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13187 "MOV Rd, Rs with two low registers is not "
13188 "permitted on this architecture");
13189 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13193 inst
.instruction
= T_OPCODE_MOV_HR
;
13194 inst
.instruction
|= (Rn
& 0x8) << 4;
13195 inst
.instruction
|= (Rn
& 0x7);
13196 inst
.instruction
|= Rm
<< 3;
13200 /* We know we have low registers at this point.
13201 Generate LSLS Rd, Rs, #0. */
13202 inst
.instruction
= T_OPCODE_LSL_I
;
13203 inst
.instruction
|= Rn
;
13204 inst
.instruction
|= Rm
<< 3;
13210 inst
.instruction
= T_OPCODE_CMP_LR
;
13211 inst
.instruction
|= Rn
;
13212 inst
.instruction
|= Rm
<< 3;
13216 inst
.instruction
= T_OPCODE_CMP_HR
;
13217 inst
.instruction
|= (Rn
& 0x8) << 4;
13218 inst
.instruction
|= (Rn
& 0x7);
13219 inst
.instruction
|= Rm
<< 3;
13226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13228 /* PR 10443: Do not silently ignore shifted operands. */
13229 constraint (inst
.operands
[1].shifted
,
13230 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13232 if (inst
.operands
[1].isreg
)
13234 if (Rn
< 8 && Rm
< 8)
13236 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13237 since a MOV instruction produces unpredictable results. */
13238 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13239 inst
.instruction
= T_OPCODE_ADD_I3
;
13241 inst
.instruction
= T_OPCODE_CMP_LR
;
13243 inst
.instruction
|= Rn
;
13244 inst
.instruction
|= Rm
<< 3;
13248 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13249 inst
.instruction
= T_OPCODE_MOV_HR
;
13251 inst
.instruction
= T_OPCODE_CMP_HR
;
13257 constraint (Rn
> 7,
13258 _("only lo regs allowed with immediate"));
13259 inst
.instruction
|= Rn
<< 8;
13260 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13271 top
= (inst
.instruction
& 0x00800000) != 0;
13272 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13274 constraint (top
, _(":lower16: not allowed in this instruction"));
13275 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13277 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13279 constraint (!top
, _(":upper16: not allowed in this instruction"));
13280 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13283 Rd
= inst
.operands
[0].reg
;
13284 reject_bad_reg (Rd
);
13286 inst
.instruction
|= Rd
<< 8;
13287 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13289 imm
= inst
.relocs
[0].exp
.X_add_number
;
13290 inst
.instruction
|= (imm
& 0xf000) << 4;
13291 inst
.instruction
|= (imm
& 0x0800) << 15;
13292 inst
.instruction
|= (imm
& 0x0700) << 4;
13293 inst
.instruction
|= (imm
& 0x00ff);
13298 do_t_mvn_tst (void)
13302 Rn
= inst
.operands
[0].reg
;
13303 Rm
= inst
.operands
[1].reg
;
13305 if (inst
.instruction
== T_MNEM_cmp
13306 || inst
.instruction
== T_MNEM_cmn
)
13307 constraint (Rn
== REG_PC
, BAD_PC
);
13309 reject_bad_reg (Rn
);
13310 reject_bad_reg (Rm
);
13312 if (unified_syntax
)
13314 int r0off
= (inst
.instruction
== T_MNEM_mvn
13315 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13316 bfd_boolean narrow
;
13318 if (inst
.size_req
== 4
13319 || inst
.instruction
> 0xffff
13320 || inst
.operands
[1].shifted
13321 || Rn
> 7 || Rm
> 7)
13323 else if (inst
.instruction
== T_MNEM_cmn
13324 || inst
.instruction
== T_MNEM_tst
)
13326 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13327 narrow
= !in_pred_block ();
13329 narrow
= in_pred_block ();
13331 if (!inst
.operands
[1].isreg
)
13333 /* For an immediate, we always generate a 32-bit opcode;
13334 section relaxation will shrink it later if possible. */
13335 if (inst
.instruction
< 0xffff)
13336 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13337 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13338 inst
.instruction
|= Rn
<< r0off
;
13339 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13343 /* See if we can do this with a 16-bit instruction. */
13346 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13347 inst
.instruction
|= Rn
;
13348 inst
.instruction
|= Rm
<< 3;
13352 constraint (inst
.operands
[1].shifted
13353 && inst
.operands
[1].immisreg
,
13354 _("shift must be constant"));
13355 if (inst
.instruction
< 0xffff)
13356 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13357 inst
.instruction
|= Rn
<< r0off
;
13358 encode_thumb32_shifted_operand (1);
13364 constraint (inst
.instruction
> 0xffff
13365 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13366 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13367 _("unshifted register required"));
13368 constraint (Rn
> 7 || Rm
> 7,
13371 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13372 inst
.instruction
|= Rn
;
13373 inst
.instruction
|= Rm
<< 3;
13382 if (do_vfp_nsyn_mrs () == SUCCESS
)
13385 Rd
= inst
.operands
[0].reg
;
13386 reject_bad_reg (Rd
);
13387 inst
.instruction
|= Rd
<< 8;
13389 if (inst
.operands
[1].isreg
)
13391 unsigned br
= inst
.operands
[1].reg
;
13392 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13393 as_bad (_("bad register for mrs"));
13395 inst
.instruction
|= br
& (0xf << 16);
13396 inst
.instruction
|= (br
& 0x300) >> 4;
13397 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13401 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13403 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13405 /* PR gas/12698: The constraint is only applied for m_profile.
13406 If the user has specified -march=all, we want to ignore it as
13407 we are building for any CPU type, including non-m variants. */
13408 bfd_boolean m_profile
=
13409 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13410 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13411 "not support requested special purpose register"));
13414 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13416 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13417 _("'APSR', 'CPSR' or 'SPSR' expected"));
13419 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13420 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13421 inst
.instruction
|= 0xf0000;
13431 if (do_vfp_nsyn_msr () == SUCCESS
)
13434 constraint (!inst
.operands
[1].isreg
,
13435 _("Thumb encoding does not support an immediate here"));
13437 if (inst
.operands
[0].isreg
)
13438 flags
= (int)(inst
.operands
[0].reg
);
13440 flags
= inst
.operands
[0].imm
;
13442 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13444 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13446 /* PR gas/12698: The constraint is only applied for m_profile.
13447 If the user has specified -march=all, we want to ignore it as
13448 we are building for any CPU type, including non-m variants. */
13449 bfd_boolean m_profile
=
13450 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13451 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13452 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13453 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13454 && bits
!= PSR_f
)) && m_profile
,
13455 _("selected processor does not support requested special "
13456 "purpose register"));
13459 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13460 "requested special purpose register"));
13462 Rn
= inst
.operands
[1].reg
;
13463 reject_bad_reg (Rn
);
13465 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13466 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13467 inst
.instruction
|= (flags
& 0x300) >> 4;
13468 inst
.instruction
|= (flags
& 0xff);
13469 inst
.instruction
|= Rn
<< 16;
13475 bfd_boolean narrow
;
13476 unsigned Rd
, Rn
, Rm
;
13478 if (!inst
.operands
[2].present
)
13479 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13481 Rd
= inst
.operands
[0].reg
;
13482 Rn
= inst
.operands
[1].reg
;
13483 Rm
= inst
.operands
[2].reg
;
13485 if (unified_syntax
)
13487 if (inst
.size_req
== 4
13493 else if (inst
.instruction
== T_MNEM_muls
)
13494 narrow
= !in_pred_block ();
13496 narrow
= in_pred_block ();
13500 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13501 constraint (Rn
> 7 || Rm
> 7,
13508 /* 16-bit MULS/Conditional MUL. */
13509 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13510 inst
.instruction
|= Rd
;
13513 inst
.instruction
|= Rm
<< 3;
13515 inst
.instruction
|= Rn
<< 3;
13517 constraint (1, _("dest must overlap one source register"));
13521 constraint (inst
.instruction
!= T_MNEM_mul
,
13522 _("Thumb-2 MUL must not set flags"));
13524 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13525 inst
.instruction
|= Rd
<< 8;
13526 inst
.instruction
|= Rn
<< 16;
13527 inst
.instruction
|= Rm
<< 0;
13529 reject_bad_reg (Rd
);
13530 reject_bad_reg (Rn
);
13531 reject_bad_reg (Rm
);
13538 unsigned RdLo
, RdHi
, Rn
, Rm
;
13540 RdLo
= inst
.operands
[0].reg
;
13541 RdHi
= inst
.operands
[1].reg
;
13542 Rn
= inst
.operands
[2].reg
;
13543 Rm
= inst
.operands
[3].reg
;
13545 reject_bad_reg (RdLo
);
13546 reject_bad_reg (RdHi
);
13547 reject_bad_reg (Rn
);
13548 reject_bad_reg (Rm
);
13550 inst
.instruction
|= RdLo
<< 12;
13551 inst
.instruction
|= RdHi
<< 8;
13552 inst
.instruction
|= Rn
<< 16;
13553 inst
.instruction
|= Rm
;
13556 as_tsktsk (_("rdhi and rdlo must be different"));
13562 set_pred_insn_type (NEUTRAL_IT_INSN
);
13564 if (unified_syntax
)
13566 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13568 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13569 inst
.instruction
|= inst
.operands
[0].imm
;
13573 /* PR9722: Check for Thumb2 availability before
13574 generating a thumb2 nop instruction. */
13575 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13577 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13578 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13581 inst
.instruction
= 0x46c0;
13586 constraint (inst
.operands
[0].present
,
13587 _("Thumb does not support NOP with hints"));
13588 inst
.instruction
= 0x46c0;
13595 if (unified_syntax
)
13597 bfd_boolean narrow
;
13599 if (THUMB_SETS_FLAGS (inst
.instruction
))
13600 narrow
= !in_pred_block ();
13602 narrow
= in_pred_block ();
13603 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13605 if (inst
.size_req
== 4)
13610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13611 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13612 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13616 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13617 inst
.instruction
|= inst
.operands
[0].reg
;
13618 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13623 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13625 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13627 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13628 inst
.instruction
|= inst
.operands
[0].reg
;
13629 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13638 Rd
= inst
.operands
[0].reg
;
13639 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13641 reject_bad_reg (Rd
);
13642 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13643 reject_bad_reg (Rn
);
13645 inst
.instruction
|= Rd
<< 8;
13646 inst
.instruction
|= Rn
<< 16;
13648 if (!inst
.operands
[2].isreg
)
13650 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13651 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13657 Rm
= inst
.operands
[2].reg
;
13658 reject_bad_reg (Rm
);
13660 constraint (inst
.operands
[2].shifted
13661 && inst
.operands
[2].immisreg
,
13662 _("shift must be constant"));
13663 encode_thumb32_shifted_operand (2);
13670 unsigned Rd
, Rn
, Rm
;
13672 Rd
= inst
.operands
[0].reg
;
13673 Rn
= inst
.operands
[1].reg
;
13674 Rm
= inst
.operands
[2].reg
;
13676 reject_bad_reg (Rd
);
13677 reject_bad_reg (Rn
);
13678 reject_bad_reg (Rm
);
13680 inst
.instruction
|= Rd
<< 8;
13681 inst
.instruction
|= Rn
<< 16;
13682 inst
.instruction
|= Rm
;
13683 if (inst
.operands
[3].present
)
13685 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13686 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13687 _("expression too complex"));
13688 inst
.instruction
|= (val
& 0x1c) << 10;
13689 inst
.instruction
|= (val
& 0x03) << 6;
13696 if (!inst
.operands
[3].present
)
13700 inst
.instruction
&= ~0x00000020;
13702 /* PR 10168. Swap the Rm and Rn registers. */
13703 Rtmp
= inst
.operands
[1].reg
;
13704 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13705 inst
.operands
[2].reg
= Rtmp
;
13713 if (inst
.operands
[0].immisreg
)
13714 reject_bad_reg (inst
.operands
[0].imm
);
13716 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13720 do_t_push_pop (void)
13724 constraint (inst
.operands
[0].writeback
,
13725 _("push/pop do not support {reglist}^"));
13726 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13727 _("expression too complex"));
13729 mask
= inst
.operands
[0].imm
;
13730 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13731 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13732 else if (inst
.size_req
!= 4
13733 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13734 ? REG_LR
: REG_PC
)))
13736 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13737 inst
.instruction
|= THUMB_PP_PC_LR
;
13738 inst
.instruction
|= mask
& 0xff;
13740 else if (unified_syntax
)
13742 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13743 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13747 inst
.error
= _("invalid register list to push/pop instruction");
13755 if (unified_syntax
)
13756 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13759 inst
.error
= _("invalid register list to push/pop instruction");
13765 do_t_vscclrm (void)
13767 if (inst
.operands
[0].issingle
)
13769 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13770 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13771 inst
.instruction
|= inst
.operands
[0].imm
;
13775 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13776 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13777 inst
.instruction
|= 1 << 8;
13778 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13787 Rd
= inst
.operands
[0].reg
;
13788 Rm
= inst
.operands
[1].reg
;
13790 reject_bad_reg (Rd
);
13791 reject_bad_reg (Rm
);
13793 inst
.instruction
|= Rd
<< 8;
13794 inst
.instruction
|= Rm
<< 16;
13795 inst
.instruction
|= Rm
;
13803 Rd
= inst
.operands
[0].reg
;
13804 Rm
= inst
.operands
[1].reg
;
13806 reject_bad_reg (Rd
);
13807 reject_bad_reg (Rm
);
13809 if (Rd
<= 7 && Rm
<= 7
13810 && inst
.size_req
!= 4)
13812 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13813 inst
.instruction
|= Rd
;
13814 inst
.instruction
|= Rm
<< 3;
13816 else if (unified_syntax
)
13818 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13819 inst
.instruction
|= Rd
<< 8;
13820 inst
.instruction
|= Rm
<< 16;
13821 inst
.instruction
|= Rm
;
13824 inst
.error
= BAD_HIREG
;
13832 Rd
= inst
.operands
[0].reg
;
13833 Rm
= inst
.operands
[1].reg
;
13835 reject_bad_reg (Rd
);
13836 reject_bad_reg (Rm
);
13838 inst
.instruction
|= Rd
<< 8;
13839 inst
.instruction
|= Rm
;
13847 Rd
= inst
.operands
[0].reg
;
13848 Rs
= (inst
.operands
[1].present
13849 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13850 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13852 reject_bad_reg (Rd
);
13853 reject_bad_reg (Rs
);
13854 if (inst
.operands
[2].isreg
)
13855 reject_bad_reg (inst
.operands
[2].reg
);
13857 inst
.instruction
|= Rd
<< 8;
13858 inst
.instruction
|= Rs
<< 16;
13859 if (!inst
.operands
[2].isreg
)
13861 bfd_boolean narrow
;
13863 if ((inst
.instruction
& 0x00100000) != 0)
13864 narrow
= !in_pred_block ();
13866 narrow
= in_pred_block ();
13868 if (Rd
> 7 || Rs
> 7)
13871 if (inst
.size_req
== 4 || !unified_syntax
)
13874 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13875 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13878 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13879 relaxation, but it doesn't seem worth the hassle. */
13882 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13883 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13884 inst
.instruction
|= Rs
<< 3;
13885 inst
.instruction
|= Rd
;
13889 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13890 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13894 encode_thumb32_shifted_operand (2);
13900 if (warn_on_deprecated
13901 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13902 as_tsktsk (_("setend use is deprecated for ARMv8"));
13904 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13905 if (inst
.operands
[0].imm
)
13906 inst
.instruction
|= 0x8;
13912 if (!inst
.operands
[1].present
)
13913 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13915 if (unified_syntax
)
13917 bfd_boolean narrow
;
13920 switch (inst
.instruction
)
13923 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13925 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13927 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13929 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13933 if (THUMB_SETS_FLAGS (inst
.instruction
))
13934 narrow
= !in_pred_block ();
13936 narrow
= in_pred_block ();
13937 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13939 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13941 if (inst
.operands
[2].isreg
13942 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13943 || inst
.operands
[2].reg
> 7))
13945 if (inst
.size_req
== 4)
13948 reject_bad_reg (inst
.operands
[0].reg
);
13949 reject_bad_reg (inst
.operands
[1].reg
);
13953 if (inst
.operands
[2].isreg
)
13955 reject_bad_reg (inst
.operands
[2].reg
);
13956 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13957 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13958 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13959 inst
.instruction
|= inst
.operands
[2].reg
;
13961 /* PR 12854: Error on extraneous shifts. */
13962 constraint (inst
.operands
[2].shifted
,
13963 _("extraneous shift as part of operand to shift insn"));
13967 inst
.operands
[1].shifted
= 1;
13968 inst
.operands
[1].shift_kind
= shift_kind
;
13969 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13970 ? T_MNEM_movs
: T_MNEM_mov
);
13971 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13972 encode_thumb32_shifted_operand (1);
13973 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13974 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13979 if (inst
.operands
[2].isreg
)
13981 switch (shift_kind
)
13983 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13984 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13985 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13986 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13990 inst
.instruction
|= inst
.operands
[0].reg
;
13991 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13993 /* PR 12854: Error on extraneous shifts. */
13994 constraint (inst
.operands
[2].shifted
,
13995 _("extraneous shift as part of operand to shift insn"));
13999 switch (shift_kind
)
14001 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14002 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14003 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14006 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14007 inst
.instruction
|= inst
.operands
[0].reg
;
14008 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14014 constraint (inst
.operands
[0].reg
> 7
14015 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14016 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14018 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14020 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14021 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14022 _("source1 and dest must be same register"));
14024 switch (inst
.instruction
)
14026 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14027 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14028 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14029 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14033 inst
.instruction
|= inst
.operands
[0].reg
;
14034 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14036 /* PR 12854: Error on extraneous shifts. */
14037 constraint (inst
.operands
[2].shifted
,
14038 _("extraneous shift as part of operand to shift insn"));
14042 switch (inst
.instruction
)
14044 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14045 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14046 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14047 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14050 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14051 inst
.instruction
|= inst
.operands
[0].reg
;
14052 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14060 unsigned Rd
, Rn
, Rm
;
14062 Rd
= inst
.operands
[0].reg
;
14063 Rn
= inst
.operands
[1].reg
;
14064 Rm
= inst
.operands
[2].reg
;
14066 reject_bad_reg (Rd
);
14067 reject_bad_reg (Rn
);
14068 reject_bad_reg (Rm
);
14070 inst
.instruction
|= Rd
<< 8;
14071 inst
.instruction
|= Rn
<< 16;
14072 inst
.instruction
|= Rm
;
14078 unsigned Rd
, Rn
, Rm
;
14080 Rd
= inst
.operands
[0].reg
;
14081 Rm
= inst
.operands
[1].reg
;
14082 Rn
= inst
.operands
[2].reg
;
14084 reject_bad_reg (Rd
);
14085 reject_bad_reg (Rn
);
14086 reject_bad_reg (Rm
);
14088 inst
.instruction
|= Rd
<< 8;
14089 inst
.instruction
|= Rn
<< 16;
14090 inst
.instruction
|= Rm
;
14096 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14098 _("SMC is not permitted on this architecture"));
14099 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14100 _("expression too complex"));
14101 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14103 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14104 inst
.instruction
|= (value
& 0x000f) << 16;
14106 /* PR gas/15623: SMC instructions must be last in an IT block. */
14107 set_pred_insn_type_last ();
14113 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14115 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14116 inst
.instruction
|= (value
& 0x0fff);
14117 inst
.instruction
|= (value
& 0xf000) << 4;
14121 do_t_ssat_usat (int bias
)
14125 Rd
= inst
.operands
[0].reg
;
14126 Rn
= inst
.operands
[2].reg
;
14128 reject_bad_reg (Rd
);
14129 reject_bad_reg (Rn
);
14131 inst
.instruction
|= Rd
<< 8;
14132 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14133 inst
.instruction
|= Rn
<< 16;
14135 if (inst
.operands
[3].present
)
14137 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14139 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14141 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14142 _("expression too complex"));
14144 if (shift_amount
!= 0)
14146 constraint (shift_amount
> 31,
14147 _("shift expression is too large"));
14149 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14150 inst
.instruction
|= 0x00200000; /* sh bit. */
14152 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14153 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14161 do_t_ssat_usat (1);
14169 Rd
= inst
.operands
[0].reg
;
14170 Rn
= inst
.operands
[2].reg
;
14172 reject_bad_reg (Rd
);
14173 reject_bad_reg (Rn
);
14175 inst
.instruction
|= Rd
<< 8;
14176 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14177 inst
.instruction
|= Rn
<< 16;
14183 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14184 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14185 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14186 || inst
.operands
[2].negative
,
14189 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14191 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14192 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14193 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14194 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14200 if (!inst
.operands
[2].present
)
14201 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14203 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14204 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14205 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14208 inst
.instruction
|= inst
.operands
[0].reg
;
14209 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14210 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14211 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14217 unsigned Rd
, Rn
, Rm
;
14219 Rd
= inst
.operands
[0].reg
;
14220 Rn
= inst
.operands
[1].reg
;
14221 Rm
= inst
.operands
[2].reg
;
14223 reject_bad_reg (Rd
);
14224 reject_bad_reg (Rn
);
14225 reject_bad_reg (Rm
);
14227 inst
.instruction
|= Rd
<< 8;
14228 inst
.instruction
|= Rn
<< 16;
14229 inst
.instruction
|= Rm
;
14230 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14238 Rd
= inst
.operands
[0].reg
;
14239 Rm
= inst
.operands
[1].reg
;
14241 reject_bad_reg (Rd
);
14242 reject_bad_reg (Rm
);
14244 if (inst
.instruction
<= 0xffff
14245 && inst
.size_req
!= 4
14246 && Rd
<= 7 && Rm
<= 7
14247 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14249 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14250 inst
.instruction
|= Rd
;
14251 inst
.instruction
|= Rm
<< 3;
14253 else if (unified_syntax
)
14255 if (inst
.instruction
<= 0xffff)
14256 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14257 inst
.instruction
|= Rd
<< 8;
14258 inst
.instruction
|= Rm
;
14259 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14263 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14264 _("Thumb encoding does not support rotation"));
14265 constraint (1, BAD_HIREG
);
14272 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14281 half
= (inst
.instruction
& 0x10) != 0;
14282 set_pred_insn_type_last ();
14283 constraint (inst
.operands
[0].immisreg
,
14284 _("instruction requires register index"));
14286 Rn
= inst
.operands
[0].reg
;
14287 Rm
= inst
.operands
[0].imm
;
14289 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14290 constraint (Rn
== REG_SP
, BAD_SP
);
14291 reject_bad_reg (Rm
);
14293 constraint (!half
&& inst
.operands
[0].shifted
,
14294 _("instruction does not allow shifted index"));
14295 inst
.instruction
|= (Rn
<< 16) | Rm
;
14301 if (!inst
.operands
[0].present
)
14302 inst
.operands
[0].imm
= 0;
14304 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14306 constraint (inst
.size_req
== 2,
14307 _("immediate value out of range"));
14308 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14309 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14310 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14315 inst
.instruction
|= inst
.operands
[0].imm
;
14318 set_pred_insn_type (NEUTRAL_IT_INSN
);
14325 do_t_ssat_usat (0);
14333 Rd
= inst
.operands
[0].reg
;
14334 Rn
= inst
.operands
[2].reg
;
14336 reject_bad_reg (Rd
);
14337 reject_bad_reg (Rn
);
14339 inst
.instruction
|= Rd
<< 8;
14340 inst
.instruction
|= inst
.operands
[1].imm
;
14341 inst
.instruction
|= Rn
<< 16;
14344 /* Checking the range of the branch offset (VAL) with NBITS bits
14345 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14347 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14349 gas_assert (nbits
> 0 && nbits
<= 32);
14352 int cmp
= (1 << (nbits
- 1));
14353 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14358 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14364 /* For branches in Armv8.1-M Mainline. */
14366 do_t_branch_future (void)
14368 unsigned long insn
= inst
.instruction
;
14370 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14371 if (inst
.operands
[0].hasreloc
== 0)
14373 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14374 as_bad (BAD_BRANCH_OFF
);
14376 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14380 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14381 inst
.relocs
[0].pc_rel
= 1;
14387 if (inst
.operands
[1].hasreloc
== 0)
14389 int val
= inst
.operands
[1].imm
;
14390 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14391 as_bad (BAD_BRANCH_OFF
);
14393 int immA
= (val
& 0x0001f000) >> 12;
14394 int immB
= (val
& 0x00000ffc) >> 2;
14395 int immC
= (val
& 0x00000002) >> 1;
14396 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14400 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14401 inst
.relocs
[1].pc_rel
= 1;
14406 if (inst
.operands
[1].hasreloc
== 0)
14408 int val
= inst
.operands
[1].imm
;
14409 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14410 as_bad (BAD_BRANCH_OFF
);
14412 int immA
= (val
& 0x0007f000) >> 12;
14413 int immB
= (val
& 0x00000ffc) >> 2;
14414 int immC
= (val
& 0x00000002) >> 1;
14415 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14419 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14420 inst
.relocs
[1].pc_rel
= 1;
14424 case T_MNEM_bfcsel
:
14426 if (inst
.operands
[1].hasreloc
== 0)
14428 int val
= inst
.operands
[1].imm
;
14429 int immA
= (val
& 0x00001000) >> 12;
14430 int immB
= (val
& 0x00000ffc) >> 2;
14431 int immC
= (val
& 0x00000002) >> 1;
14432 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14436 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14437 inst
.relocs
[1].pc_rel
= 1;
14441 if (inst
.operands
[2].hasreloc
== 0)
14443 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14444 int val2
= inst
.operands
[2].imm
;
14445 int val0
= inst
.operands
[0].imm
& 0x1f;
14446 int diff
= val2
- val0
;
14448 inst
.instruction
|= 1 << 17; /* T bit. */
14449 else if (diff
!= 2)
14450 as_bad (_("out of range label-relative fixup value"));
14454 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14455 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14456 inst
.relocs
[2].pc_rel
= 1;
14460 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14461 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14473 /* Helper function for do_t_loloop to handle relocations. */
14475 v8_1_loop_reloc (int is_le
)
14477 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14479 int value
= inst
.relocs
[0].exp
.X_add_number
;
14480 value
= (is_le
) ? -value
: value
;
14482 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14483 as_bad (BAD_BRANCH_OFF
);
14487 immh
= (value
& 0x00000ffc) >> 2;
14488 imml
= (value
& 0x00000002) >> 1;
14490 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14494 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14495 inst
.relocs
[0].pc_rel
= 1;
14499 /* For shifts with four operands in MVE. */
14501 do_mve_scalar_shift1 (void)
14503 unsigned int value
= inst
.operands
[2].imm
;
14505 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14506 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14508 /* Setting the bit for saturation. */
14509 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14511 /* Assuming Rm is already checked not to be 11x1. */
14512 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14513 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14514 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14517 /* For shifts in MVE. */
14519 do_mve_scalar_shift (void)
14521 if (!inst
.operands
[2].present
)
14523 inst
.operands
[2] = inst
.operands
[1];
14524 inst
.operands
[1].reg
= 0xf;
14527 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14528 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14530 if (inst
.operands
[2].isreg
)
14532 /* Assuming Rm is already checked not to be 11x1. */
14533 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14534 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14535 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14539 /* Assuming imm is already checked as [1,32]. */
14540 unsigned int value
= inst
.operands
[2].imm
;
14541 inst
.instruction
|= (value
& 0x1c) << 10;
14542 inst
.instruction
|= (value
& 0x03) << 6;
14543 /* Change last 4 bits from 0xd to 0xf. */
14544 inst
.instruction
|= 0x2;
14548 /* MVE instruction encoder helpers. */
14549 #define M_MNEM_vabav 0xee800f01
14550 #define M_MNEM_vmladav 0xeef00e00
14551 #define M_MNEM_vmladava 0xeef00e20
14552 #define M_MNEM_vmladavx 0xeef01e00
14553 #define M_MNEM_vmladavax 0xeef01e20
14554 #define M_MNEM_vmlsdav 0xeef00e01
14555 #define M_MNEM_vmlsdava 0xeef00e21
14556 #define M_MNEM_vmlsdavx 0xeef01e01
14557 #define M_MNEM_vmlsdavax 0xeef01e21
14558 #define M_MNEM_vmullt 0xee011e00
14559 #define M_MNEM_vmullb 0xee010e00
14560 #define M_MNEM_vctp 0xf000e801
14561 #define M_MNEM_vst20 0xfc801e00
14562 #define M_MNEM_vst21 0xfc801e20
14563 #define M_MNEM_vst40 0xfc801e01
14564 #define M_MNEM_vst41 0xfc801e21
14565 #define M_MNEM_vst42 0xfc801e41
14566 #define M_MNEM_vst43 0xfc801e61
14567 #define M_MNEM_vld20 0xfc901e00
14568 #define M_MNEM_vld21 0xfc901e20
14569 #define M_MNEM_vld40 0xfc901e01
14570 #define M_MNEM_vld41 0xfc901e21
14571 #define M_MNEM_vld42 0xfc901e41
14572 #define M_MNEM_vld43 0xfc901e61
14573 #define M_MNEM_vstrb 0xec000e00
14574 #define M_MNEM_vstrh 0xec000e10
14575 #define M_MNEM_vstrw 0xec000e40
14576 #define M_MNEM_vstrd 0xec000e50
14577 #define M_MNEM_vldrb 0xec100e00
14578 #define M_MNEM_vldrh 0xec100e10
14579 #define M_MNEM_vldrw 0xec100e40
14580 #define M_MNEM_vldrd 0xec100e50
14581 #define M_MNEM_vmovlt 0xeea01f40
14582 #define M_MNEM_vmovlb 0xeea00f40
14583 #define M_MNEM_vmovnt 0xfe311e81
14584 #define M_MNEM_vmovnb 0xfe310e81
14585 #define M_MNEM_vadc 0xee300f00
14586 #define M_MNEM_vadci 0xee301f00
14587 #define M_MNEM_vbrsr 0xfe011e60
14588 #define M_MNEM_vaddlv 0xee890f00
14589 #define M_MNEM_vaddlva 0xee890f20
14590 #define M_MNEM_vaddv 0xeef10f00
14591 #define M_MNEM_vaddva 0xeef10f20
14592 #define M_MNEM_vddup 0xee011f6e
14593 #define M_MNEM_vdwdup 0xee011f60
14594 #define M_MNEM_vidup 0xee010f6e
14595 #define M_MNEM_viwdup 0xee010f60
14596 #define M_MNEM_vmaxv 0xeee20f00
14597 #define M_MNEM_vmaxav 0xeee00f00
14598 #define M_MNEM_vminv 0xeee20f80
14599 #define M_MNEM_vminav 0xeee00f80
14600 #define M_MNEM_vmlaldav 0xee800e00
14601 #define M_MNEM_vmlaldava 0xee800e20
14602 #define M_MNEM_vmlaldavx 0xee801e00
14603 #define M_MNEM_vmlaldavax 0xee801e20
14604 #define M_MNEM_vmlsldav 0xee800e01
14605 #define M_MNEM_vmlsldava 0xee800e21
14606 #define M_MNEM_vmlsldavx 0xee801e01
14607 #define M_MNEM_vmlsldavax 0xee801e21
14608 #define M_MNEM_vrmlaldavhx 0xee801f00
14609 #define M_MNEM_vrmlaldavhax 0xee801f20
14610 #define M_MNEM_vrmlsldavh 0xfe800e01
14611 #define M_MNEM_vrmlsldavha 0xfe800e21
14612 #define M_MNEM_vrmlsldavhx 0xfe801e01
14613 #define M_MNEM_vrmlsldavhax 0xfe801e21
14614 #define M_MNEM_vqmovnt 0xee331e01
14615 #define M_MNEM_vqmovnb 0xee330e01
14616 #define M_MNEM_vqmovunt 0xee311e81
14617 #define M_MNEM_vqmovunb 0xee310e81
14618 #define M_MNEM_vshrnt 0xee801fc1
14619 #define M_MNEM_vshrnb 0xee800fc1
14620 #define M_MNEM_vrshrnt 0xfe801fc1
14621 #define M_MNEM_vqshrnt 0xee801f40
14622 #define M_MNEM_vqshrnb 0xee800f40
14623 #define M_MNEM_vqshrunt 0xee801fc0
14624 #define M_MNEM_vqshrunb 0xee800fc0
14625 #define M_MNEM_vrshrnb 0xfe800fc1
14626 #define M_MNEM_vqrshrnt 0xee801f41
14627 #define M_MNEM_vqrshrnb 0xee800f41
14628 #define M_MNEM_vqrshrunt 0xfe801fc0
14629 #define M_MNEM_vqrshrunb 0xfe800fc0
14631 /* Bfloat16 instruction encoder helpers. */
14632 #define B_MNEM_vfmat 0xfc300850
14633 #define B_MNEM_vfmab 0xfc300810
14635 /* Neon instruction encoder helpers. */
14637 /* Encodings for the different types for various Neon opcodes. */
14639 /* An "invalid" code for the following tables. */
14642 struct neon_tab_entry
14645 unsigned float_or_poly
;
14646 unsigned scalar_or_imm
;
14649 /* Map overloaded Neon opcodes to their respective encodings. */
14650 #define NEON_ENC_TAB \
14651 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14652 X(vabdl, 0x0800700, N_INV, N_INV), \
14653 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14654 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14655 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14656 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14657 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14658 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14659 X(vaddl, 0x0800000, N_INV, N_INV), \
14660 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14661 X(vsubl, 0x0800200, N_INV, N_INV), \
14662 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14663 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14664 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14665 /* Register variants of the following two instructions are encoded as
14666 vcge / vcgt with the operands reversed. */ \
14667 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14668 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14669 X(vfma, N_INV, 0x0000c10, N_INV), \
14670 X(vfms, N_INV, 0x0200c10, N_INV), \
14671 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14672 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14673 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14674 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14675 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14676 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14677 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14678 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14679 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14680 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14681 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14682 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14683 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14684 X(vshl, 0x0000400, N_INV, 0x0800510), \
14685 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14686 X(vand, 0x0000110, N_INV, 0x0800030), \
14687 X(vbic, 0x0100110, N_INV, 0x0800030), \
14688 X(veor, 0x1000110, N_INV, N_INV), \
14689 X(vorn, 0x0300110, N_INV, 0x0800010), \
14690 X(vorr, 0x0200110, N_INV, 0x0800010), \
14691 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14692 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14693 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14694 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14695 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14696 X(vst1, 0x0000000, 0x0800000, N_INV), \
14697 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14698 X(vst2, 0x0000100, 0x0800100, N_INV), \
14699 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14700 X(vst3, 0x0000200, 0x0800200, N_INV), \
14701 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14702 X(vst4, 0x0000300, 0x0800300, N_INV), \
14703 X(vmovn, 0x1b20200, N_INV, N_INV), \
14704 X(vtrn, 0x1b20080, N_INV, N_INV), \
14705 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14706 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14707 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14708 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14709 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14710 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14711 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14712 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14713 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14714 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14715 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14716 X(vseleq, 0xe000a00, N_INV, N_INV), \
14717 X(vselvs, 0xe100a00, N_INV, N_INV), \
14718 X(vselge, 0xe200a00, N_INV, N_INV), \
14719 X(vselgt, 0xe300a00, N_INV, N_INV), \
14720 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14721 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14722 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14723 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14724 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14725 X(aes, 0x3b00300, N_INV, N_INV), \
14726 X(sha3op, 0x2000c00, N_INV, N_INV), \
14727 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14728 X(sha2op, 0x3ba0380, N_INV, N_INV)
14732 #define X(OPC,I,F,S) N_MNEM_##OPC
14737 static const struct neon_tab_entry neon_enc_tab
[] =
14739 #define X(OPC,I,F,S) { (I), (F), (S) }
14744 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14745 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14746 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14747 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14748 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14749 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14750 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14751 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14752 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14753 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14754 #define NEON_ENC_SINGLE_(X) \
14755 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14756 #define NEON_ENC_DOUBLE_(X) \
14757 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14758 #define NEON_ENC_FPV8_(X) \
14759 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14761 #define NEON_ENCODE(type, inst) \
14764 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14765 inst.is_neon = 1; \
14769 #define check_neon_suffixes \
14772 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14774 as_bad (_("invalid neon suffix for non neon instruction")); \
14780 /* Define shapes for instruction operands. The following mnemonic characters
14781 are used in this table:
14783 F - VFP S<n> register
14784 D - Neon D<n> register
14785 Q - Neon Q<n> register
14789 L - D<n> register list
14791 This table is used to generate various data:
14792 - enumerations of the form NS_DDR to be used as arguments to
14794 - a table classifying shapes into single, double, quad, mixed.
14795 - a table used to drive neon_select_shape. */
14797 #define NEON_SHAPE_DEF \
14798 X(4, (R, R, Q, Q), QUAD), \
14799 X(4, (Q, R, R, I), QUAD), \
14800 X(4, (R, R, S, S), QUAD), \
14801 X(4, (S, S, R, R), QUAD), \
14802 X(3, (Q, R, I), QUAD), \
14803 X(3, (I, Q, Q), QUAD), \
14804 X(3, (I, Q, R), QUAD), \
14805 X(3, (R, Q, Q), QUAD), \
14806 X(3, (D, D, D), DOUBLE), \
14807 X(3, (Q, Q, Q), QUAD), \
14808 X(3, (D, D, I), DOUBLE), \
14809 X(3, (Q, Q, I), QUAD), \
14810 X(3, (D, D, S), DOUBLE), \
14811 X(3, (Q, Q, S), QUAD), \
14812 X(3, (Q, Q, R), QUAD), \
14813 X(3, (R, R, Q), QUAD), \
14814 X(2, (R, Q), QUAD), \
14815 X(2, (D, D), DOUBLE), \
14816 X(2, (Q, Q), QUAD), \
14817 X(2, (D, S), DOUBLE), \
14818 X(2, (Q, S), QUAD), \
14819 X(2, (D, R), DOUBLE), \
14820 X(2, (Q, R), QUAD), \
14821 X(2, (D, I), DOUBLE), \
14822 X(2, (Q, I), QUAD), \
14823 X(3, (P, F, I), SINGLE), \
14824 X(3, (P, D, I), DOUBLE), \
14825 X(3, (P, Q, I), QUAD), \
14826 X(4, (P, F, F, I), SINGLE), \
14827 X(4, (P, D, D, I), DOUBLE), \
14828 X(4, (P, Q, Q, I), QUAD), \
14829 X(5, (P, F, F, F, I), SINGLE), \
14830 X(5, (P, D, D, D, I), DOUBLE), \
14831 X(5, (P, Q, Q, Q, I), QUAD), \
14832 X(3, (D, L, D), DOUBLE), \
14833 X(2, (D, Q), MIXED), \
14834 X(2, (Q, D), MIXED), \
14835 X(3, (D, Q, I), MIXED), \
14836 X(3, (Q, D, I), MIXED), \
14837 X(3, (Q, D, D), MIXED), \
14838 X(3, (D, Q, Q), MIXED), \
14839 X(3, (Q, Q, D), MIXED), \
14840 X(3, (Q, D, S), MIXED), \
14841 X(3, (D, Q, S), MIXED), \
14842 X(4, (D, D, D, I), DOUBLE), \
14843 X(4, (Q, Q, Q, I), QUAD), \
14844 X(4, (D, D, S, I), DOUBLE), \
14845 X(4, (Q, Q, S, I), QUAD), \
14846 X(2, (F, F), SINGLE), \
14847 X(3, (F, F, F), SINGLE), \
14848 X(2, (F, I), SINGLE), \
14849 X(2, (F, D), MIXED), \
14850 X(2, (D, F), MIXED), \
14851 X(3, (F, F, I), MIXED), \
14852 X(4, (R, R, F, F), SINGLE), \
14853 X(4, (F, F, R, R), SINGLE), \
14854 X(3, (D, R, R), DOUBLE), \
14855 X(3, (R, R, D), DOUBLE), \
14856 X(2, (S, R), SINGLE), \
14857 X(2, (R, S), SINGLE), \
14858 X(2, (F, R), SINGLE), \
14859 X(2, (R, F), SINGLE), \
14860 /* Used for MVE tail predicated loop instructions. */\
14861 X(2, (R, R), QUAD), \
14862 /* Half float shape supported so far. */\
14863 X (2, (H, D), MIXED), \
14864 X (2, (D, H), MIXED), \
14865 X (2, (H, F), MIXED), \
14866 X (2, (F, H), MIXED), \
14867 X (2, (H, H), HALF), \
14868 X (2, (H, R), HALF), \
14869 X (2, (R, H), HALF), \
14870 X (2, (H, I), HALF), \
14871 X (3, (H, H, H), HALF), \
14872 X (3, (H, F, I), MIXED), \
14873 X (3, (F, H, I), MIXED), \
14874 X (3, (D, H, H), MIXED), \
14875 X (3, (D, H, S), MIXED)
14877 #define S2(A,B) NS_##A##B
14878 #define S3(A,B,C) NS_##A##B##C
14879 #define S4(A,B,C,D) NS_##A##B##C##D
14880 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14882 #define X(N, L, C) S##N L
14896 enum neon_shape_class
14905 #define X(N, L, C) SC_##C
14907 static enum neon_shape_class neon_shape_class
[] =
14927 /* Register widths of above. */
14928 static unsigned neon_shape_el_size
[] =
14941 struct neon_shape_info
14944 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14947 #define S2(A,B) { SE_##A, SE_##B }
14948 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14949 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14950 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14952 #define X(N, L, C) { N, S##N L }
14954 static struct neon_shape_info neon_shape_tab
[] =
14965 /* Bit masks used in type checking given instructions.
14966 'N_EQK' means the type must be the same as (or based on in some way) the key
14967 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14968 set, various other bits can be set as well in order to modify the meaning of
14969 the type constraint. */
14971 enum neon_type_mask
14995 N_BF16
= 0x0400000,
14996 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14997 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14998 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14999 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
15000 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
15001 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
15002 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15003 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15004 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15005 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15006 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15008 N_MAX_NONSPECIAL
= N_P64
15011 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15013 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15014 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15015 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15016 #define N_S_32 (N_S8 | N_S16 | N_S32)
15017 #define N_F_16_32 (N_F16 | N_F32)
15018 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15019 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15020 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15021 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15022 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15023 #define N_F_MVE (N_F16 | N_F32)
15024 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15026 /* Pass this as the first type argument to neon_check_type to ignore types
15028 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15030 /* Select a "shape" for the current instruction (describing register types or
15031 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15032 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15033 function of operand parsing, so this function doesn't need to be called.
15034 Shapes should be listed in order of decreasing length. */
15036 static enum neon_shape
15037 neon_select_shape (enum neon_shape shape
, ...)
15040 enum neon_shape first_shape
= shape
;
15042 /* Fix missing optional operands. FIXME: we don't know at this point how
15043 many arguments we should have, so this makes the assumption that we have
15044 > 1. This is true of all current Neon opcodes, I think, but may not be
15045 true in the future. */
15046 if (!inst
.operands
[1].present
)
15047 inst
.operands
[1] = inst
.operands
[0];
15049 va_start (ap
, shape
);
15051 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15056 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15058 if (!inst
.operands
[j
].present
)
15064 switch (neon_shape_tab
[shape
].el
[j
])
15066 /* If a .f16, .16, .u16, .s16 type specifier is given over
15067 a VFP single precision register operand, it's essentially
15068 means only half of the register is used.
15070 If the type specifier is given after the mnemonics, the
15071 information is stored in inst.vectype. If the type specifier
15072 is given after register operand, the information is stored
15073 in inst.operands[].vectype.
15075 When there is only one type specifier, and all the register
15076 operands are the same type of hardware register, the type
15077 specifier applies to all register operands.
15079 If no type specifier is given, the shape is inferred from
15080 operand information.
15083 vadd.f16 s0, s1, s2: NS_HHH
15084 vabs.f16 s0, s1: NS_HH
15085 vmov.f16 s0, r1: NS_HR
15086 vmov.f16 r0, s1: NS_RH
15087 vcvt.f16 r0, s1: NS_RH
15088 vcvt.f16.s32 s2, s2, #29: NS_HFI
15089 vcvt.f16.s32 s2, s2: NS_HF
15092 if (!(inst
.operands
[j
].isreg
15093 && inst
.operands
[j
].isvec
15094 && inst
.operands
[j
].issingle
15095 && !inst
.operands
[j
].isquad
15096 && ((inst
.vectype
.elems
== 1
15097 && inst
.vectype
.el
[0].size
== 16)
15098 || (inst
.vectype
.elems
> 1
15099 && inst
.vectype
.el
[j
].size
== 16)
15100 || (inst
.vectype
.elems
== 0
15101 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15102 && inst
.operands
[j
].vectype
.size
== 16))))
15107 if (!(inst
.operands
[j
].isreg
15108 && inst
.operands
[j
].isvec
15109 && inst
.operands
[j
].issingle
15110 && !inst
.operands
[j
].isquad
15111 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15112 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15113 || (inst
.vectype
.elems
== 0
15114 && (inst
.operands
[j
].vectype
.size
== 32
15115 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15120 if (!(inst
.operands
[j
].isreg
15121 && inst
.operands
[j
].isvec
15122 && !inst
.operands
[j
].isquad
15123 && !inst
.operands
[j
].issingle
))
15128 if (!(inst
.operands
[j
].isreg
15129 && !inst
.operands
[j
].isvec
))
15134 if (!(inst
.operands
[j
].isreg
15135 && inst
.operands
[j
].isvec
15136 && inst
.operands
[j
].isquad
15137 && !inst
.operands
[j
].issingle
))
15142 if (!(!inst
.operands
[j
].isreg
15143 && !inst
.operands
[j
].isscalar
))
15148 if (!(!inst
.operands
[j
].isreg
15149 && inst
.operands
[j
].isscalar
))
15160 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15161 /* We've matched all the entries in the shape table, and we don't
15162 have any left over operands which have not been matched. */
15168 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15169 first_error (_("invalid instruction shape"));
15174 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15175 means the Q bit should be set). */
15178 neon_quad (enum neon_shape shape
)
15180 return neon_shape_class
[shape
] == SC_QUAD
;
15184 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15187 /* Allow modification to be made to types which are constrained to be
15188 based on the key element, based on bits set alongside N_EQK. */
15189 if ((typebits
& N_EQK
) != 0)
15191 if ((typebits
& N_HLF
) != 0)
15193 else if ((typebits
& N_DBL
) != 0)
15195 if ((typebits
& N_SGN
) != 0)
15196 *g_type
= NT_signed
;
15197 else if ((typebits
& N_UNS
) != 0)
15198 *g_type
= NT_unsigned
;
15199 else if ((typebits
& N_INT
) != 0)
15200 *g_type
= NT_integer
;
15201 else if ((typebits
& N_FLT
) != 0)
15202 *g_type
= NT_float
;
15203 else if ((typebits
& N_SIZ
) != 0)
15204 *g_type
= NT_untyped
;
15208 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15209 operand type, i.e. the single type specified in a Neon instruction when it
15210 is the only one given. */
15212 static struct neon_type_el
15213 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15215 struct neon_type_el dest
= *key
;
15217 gas_assert ((thisarg
& N_EQK
) != 0);
15219 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15224 /* Convert Neon type and size into compact bitmask representation. */
15226 static enum neon_type_mask
15227 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15234 case 8: return N_8
;
15235 case 16: return N_16
;
15236 case 32: return N_32
;
15237 case 64: return N_64
;
15245 case 8: return N_I8
;
15246 case 16: return N_I16
;
15247 case 32: return N_I32
;
15248 case 64: return N_I64
;
15256 case 16: return N_F16
;
15257 case 32: return N_F32
;
15258 case 64: return N_F64
;
15266 case 8: return N_P8
;
15267 case 16: return N_P16
;
15268 case 64: return N_P64
;
15276 case 8: return N_S8
;
15277 case 16: return N_S16
;
15278 case 32: return N_S32
;
15279 case 64: return N_S64
;
15287 case 8: return N_U8
;
15288 case 16: return N_U16
;
15289 case 32: return N_U32
;
15290 case 64: return N_U64
;
15296 if (size
== 16) return N_BF16
;
15305 /* Convert compact Neon bitmask type representation to a type and size. Only
15306 handles the case where a single bit is set in the mask. */
15309 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15310 enum neon_type_mask mask
)
15312 if ((mask
& N_EQK
) != 0)
15315 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15317 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15320 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15322 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15327 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15329 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15330 *type
= NT_unsigned
;
15331 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15332 *type
= NT_integer
;
15333 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15334 *type
= NT_untyped
;
15335 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15337 else if ((mask
& (N_F_ALL
)) != 0)
15339 else if ((mask
& (N_BF16
)) != 0)
15347 /* Modify a bitmask of allowed types. This is only needed for type
15351 modify_types_allowed (unsigned allowed
, unsigned mods
)
15354 enum neon_el_type type
;
15360 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15362 if (el_type_of_type_chk (&type
, &size
,
15363 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15365 neon_modify_type_size (mods
, &type
, &size
);
15366 destmask
|= type_chk_of_el_type (type
, size
);
15373 /* Check type and return type classification.
15374 The manual states (paraphrase): If one datatype is given, it indicates the
15376 - the second operand, if there is one
15377 - the operand, if there is no second operand
15378 - the result, if there are no operands.
15379 This isn't quite good enough though, so we use a concept of a "key" datatype
15380 which is set on a per-instruction basis, which is the one which matters when
15381 only one data type is written.
15382 Note: this function has side-effects (e.g. filling in missing operands). All
15383 Neon instructions should call it before performing bit encoding. */
15385 static struct neon_type_el
15386 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15389 unsigned i
, pass
, key_el
= 0;
15390 unsigned types
[NEON_MAX_TYPE_ELS
];
15391 enum neon_el_type k_type
= NT_invtype
;
15392 unsigned k_size
= -1u;
15393 struct neon_type_el badtype
= {NT_invtype
, -1};
15394 unsigned key_allowed
= 0;
15396 /* Optional registers in Neon instructions are always (not) in operand 1.
15397 Fill in the missing operand here, if it was omitted. */
15398 if (els
> 1 && !inst
.operands
[1].present
)
15399 inst
.operands
[1] = inst
.operands
[0];
15401 /* Suck up all the varargs. */
15403 for (i
= 0; i
< els
; i
++)
15405 unsigned thisarg
= va_arg (ap
, unsigned);
15406 if (thisarg
== N_IGNORE_TYPE
)
15411 types
[i
] = thisarg
;
15412 if ((thisarg
& N_KEY
) != 0)
15417 if (inst
.vectype
.elems
> 0)
15418 for (i
= 0; i
< els
; i
++)
15419 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15421 first_error (_("types specified in both the mnemonic and operands"));
15425 /* Duplicate inst.vectype elements here as necessary.
15426 FIXME: No idea if this is exactly the same as the ARM assembler,
15427 particularly when an insn takes one register and one non-register
15429 if (inst
.vectype
.elems
== 1 && els
> 1)
15432 inst
.vectype
.elems
= els
;
15433 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15434 for (j
= 0; j
< els
; j
++)
15436 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15439 else if (inst
.vectype
.elems
== 0 && els
> 0)
15442 /* No types were given after the mnemonic, so look for types specified
15443 after each operand. We allow some flexibility here; as long as the
15444 "key" operand has a type, we can infer the others. */
15445 for (j
= 0; j
< els
; j
++)
15446 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15447 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15449 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15451 for (j
= 0; j
< els
; j
++)
15452 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15453 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15458 first_error (_("operand types can't be inferred"));
15462 else if (inst
.vectype
.elems
!= els
)
15464 first_error (_("type specifier has the wrong number of parts"));
15468 for (pass
= 0; pass
< 2; pass
++)
15470 for (i
= 0; i
< els
; i
++)
15472 unsigned thisarg
= types
[i
];
15473 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15474 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15475 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15476 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15478 /* Decay more-specific signed & unsigned types to sign-insensitive
15479 integer types if sign-specific variants are unavailable. */
15480 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15481 && (types_allowed
& N_SU_ALL
) == 0)
15482 g_type
= NT_integer
;
15484 /* If only untyped args are allowed, decay any more specific types to
15485 them. Some instructions only care about signs for some element
15486 sizes, so handle that properly. */
15487 if (((types_allowed
& N_UNT
) == 0)
15488 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15489 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15490 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15491 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15492 g_type
= NT_untyped
;
15496 if ((thisarg
& N_KEY
) != 0)
15500 key_allowed
= thisarg
& ~N_KEY
;
15502 /* Check architecture constraint on FP16 extension. */
15504 && k_type
== NT_float
15505 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15507 inst
.error
= _(BAD_FP16
);
15514 if ((thisarg
& N_VFP
) != 0)
15516 enum neon_shape_el regshape
;
15517 unsigned regwidth
, match
;
15519 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15522 first_error (_("invalid instruction shape"));
15525 regshape
= neon_shape_tab
[ns
].el
[i
];
15526 regwidth
= neon_shape_el_size
[regshape
];
15528 /* In VFP mode, operands must match register widths. If we
15529 have a key operand, use its width, else use the width of
15530 the current operand. */
15536 /* FP16 will use a single precision register. */
15537 if (regwidth
== 32 && match
== 16)
15539 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15543 inst
.error
= _(BAD_FP16
);
15548 if (regwidth
!= match
)
15550 first_error (_("operand size must match register width"));
15555 if ((thisarg
& N_EQK
) == 0)
15557 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15559 if ((given_type
& types_allowed
) == 0)
15561 first_error (BAD_SIMD_TYPE
);
15567 enum neon_el_type mod_k_type
= k_type
;
15568 unsigned mod_k_size
= k_size
;
15569 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15570 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15572 first_error (_("inconsistent types in Neon instruction"));
15580 return inst
.vectype
.el
[key_el
];
15583 /* Neon-style VFP instruction forwarding. */
15585 /* Thumb VFP instructions have 0xE in the condition field. */
15588 do_vfp_cond_or_thumb (void)
15593 inst
.instruction
|= 0xe0000000;
15595 inst
.instruction
|= inst
.cond
<< 28;
15598 /* Look up and encode a simple mnemonic, for use as a helper function for the
15599 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15600 etc. It is assumed that operand parsing has already been done, and that the
15601 operands are in the form expected by the given opcode (this isn't necessarily
15602 the same as the form in which they were parsed, hence some massaging must
15603 take place before this function is called).
15604 Checks current arch version against that in the looked-up opcode. */
15607 do_vfp_nsyn_opcode (const char *opname
)
15609 const struct asm_opcode
*opcode
;
15611 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15616 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15617 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15624 inst
.instruction
= opcode
->tvalue
;
15625 opcode
->tencode ();
15629 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15630 opcode
->aencode ();
15635 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15637 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15639 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15642 do_vfp_nsyn_opcode ("fadds");
15644 do_vfp_nsyn_opcode ("fsubs");
15646 /* ARMv8.2 fp16 instruction. */
15648 do_scalar_fp16_v82_encode ();
15653 do_vfp_nsyn_opcode ("faddd");
15655 do_vfp_nsyn_opcode ("fsubd");
15659 /* Check operand types to see if this is a VFP instruction, and if so call
15663 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15665 enum neon_shape rs
;
15666 struct neon_type_el et
;
15671 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15672 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15676 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15677 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15678 N_F_ALL
| N_KEY
| N_VFP
);
15685 if (et
.type
!= NT_invtype
)
15696 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15698 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15700 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15703 do_vfp_nsyn_opcode ("fmacs");
15705 do_vfp_nsyn_opcode ("fnmacs");
15707 /* ARMv8.2 fp16 instruction. */
15709 do_scalar_fp16_v82_encode ();
15714 do_vfp_nsyn_opcode ("fmacd");
15716 do_vfp_nsyn_opcode ("fnmacd");
15721 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15723 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15725 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15728 do_vfp_nsyn_opcode ("ffmas");
15730 do_vfp_nsyn_opcode ("ffnmas");
15732 /* ARMv8.2 fp16 instruction. */
15734 do_scalar_fp16_v82_encode ();
15739 do_vfp_nsyn_opcode ("ffmad");
15741 do_vfp_nsyn_opcode ("ffnmad");
15746 do_vfp_nsyn_mul (enum neon_shape rs
)
15748 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15750 do_vfp_nsyn_opcode ("fmuls");
15752 /* ARMv8.2 fp16 instruction. */
15754 do_scalar_fp16_v82_encode ();
15757 do_vfp_nsyn_opcode ("fmuld");
15761 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15763 int is_neg
= (inst
.instruction
& 0x80) != 0;
15764 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15766 if (rs
== NS_FF
|| rs
== NS_HH
)
15769 do_vfp_nsyn_opcode ("fnegs");
15771 do_vfp_nsyn_opcode ("fabss");
15773 /* ARMv8.2 fp16 instruction. */
15775 do_scalar_fp16_v82_encode ();
15780 do_vfp_nsyn_opcode ("fnegd");
15782 do_vfp_nsyn_opcode ("fabsd");
15786 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15787 insns belong to Neon, and are handled elsewhere. */
15790 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15792 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15796 do_vfp_nsyn_opcode ("fldmdbs");
15798 do_vfp_nsyn_opcode ("fldmias");
15803 do_vfp_nsyn_opcode ("fstmdbs");
15805 do_vfp_nsyn_opcode ("fstmias");
15810 do_vfp_nsyn_sqrt (void)
15812 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15813 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15815 if (rs
== NS_FF
|| rs
== NS_HH
)
15817 do_vfp_nsyn_opcode ("fsqrts");
15819 /* ARMv8.2 fp16 instruction. */
15821 do_scalar_fp16_v82_encode ();
15824 do_vfp_nsyn_opcode ("fsqrtd");
15828 do_vfp_nsyn_div (void)
15830 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15831 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15832 N_F_ALL
| N_KEY
| N_VFP
);
15834 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15836 do_vfp_nsyn_opcode ("fdivs");
15838 /* ARMv8.2 fp16 instruction. */
15840 do_scalar_fp16_v82_encode ();
15843 do_vfp_nsyn_opcode ("fdivd");
15847 do_vfp_nsyn_nmul (void)
15849 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15850 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15851 N_F_ALL
| N_KEY
| N_VFP
);
15853 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15855 NEON_ENCODE (SINGLE
, inst
);
15856 do_vfp_sp_dyadic ();
15858 /* ARMv8.2 fp16 instruction. */
15860 do_scalar_fp16_v82_encode ();
15864 NEON_ENCODE (DOUBLE
, inst
);
15865 do_vfp_dp_rd_rn_rm ();
15867 do_vfp_cond_or_thumb ();
15871 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15875 neon_logbits (unsigned x
)
15877 return ffs (x
) - 4;
15880 #define LOW4(R) ((R) & 0xf)
15881 #define HI1(R) (((R) >> 4) & 1)
15882 #define LOW1(R) ((R) & 0x1)
15883 #define HI4(R) (((R) >> 1) & 0xf)
15886 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15891 first_error (BAD_EL_TYPE
);
15894 switch (inst
.operands
[0].imm
)
15897 first_error (_("invalid condition"));
15919 /* only accept eq and ne. */
15920 if (inst
.operands
[0].imm
> 1)
15922 first_error (_("invalid condition"));
15925 return inst
.operands
[0].imm
;
15927 if (inst
.operands
[0].imm
== 0x2)
15929 else if (inst
.operands
[0].imm
== 0x8)
15933 first_error (_("invalid condition"));
15937 switch (inst
.operands
[0].imm
)
15940 first_error (_("invalid condition"));
15956 /* Should be unreachable. */
15960 /* For VCTP (create vector tail predicate) in MVE. */
15965 unsigned size
= 0x0;
15967 if (inst
.cond
> COND_ALWAYS
)
15968 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15970 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15972 /* This is a typical MVE instruction which has no type but have size 8, 16,
15973 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15974 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15975 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15976 dt
= inst
.vectype
.el
[0].size
;
15978 /* Setting this does not indicate an actual NEON instruction, but only
15979 indicates that the mnemonic accepts neon-style type suffixes. */
15993 first_error (_("Type is not allowed for this instruction"));
15995 inst
.instruction
|= size
<< 20;
15996 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16002 /* We are dealing with a vector predicated block. */
16003 if (inst
.operands
[0].present
)
16005 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16006 struct neon_type_el et
16007 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16010 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16012 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16014 if (et
.type
== NT_invtype
)
16017 if (et
.type
== NT_float
)
16019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16021 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16022 inst
.instruction
|= (et
.size
== 16) << 28;
16023 inst
.instruction
|= 0x3 << 20;
16027 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16029 inst
.instruction
|= 1 << 28;
16030 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16033 if (inst
.operands
[2].isquad
)
16035 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16036 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16037 inst
.instruction
|= (fcond
& 0x2) >> 1;
16041 if (inst
.operands
[2].reg
== REG_SP
)
16042 as_tsktsk (MVE_BAD_SP
);
16043 inst
.instruction
|= 1 << 6;
16044 inst
.instruction
|= (fcond
& 0x2) << 4;
16045 inst
.instruction
|= inst
.operands
[2].reg
;
16047 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16048 inst
.instruction
|= (fcond
& 0x4) << 10;
16049 inst
.instruction
|= (fcond
& 0x1) << 7;
16052 set_pred_insn_type (VPT_INSN
);
16054 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16055 | ((inst
.instruction
& 0xe000) >> 13);
16056 now_pred
.warn_deprecated
= FALSE
;
16057 now_pred
.type
= VECTOR_PRED
;
16064 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16065 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16066 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16067 if (!inst
.operands
[2].present
)
16068 first_error (_("MVE vector or ARM register expected"));
16069 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16071 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16072 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16073 && inst
.operands
[1].isquad
)
16075 inst
.instruction
= N_MNEM_vcmp
;
16079 if (inst
.cond
> COND_ALWAYS
)
16080 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16082 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16084 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16085 struct neon_type_el et
16086 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16089 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16090 && !inst
.operands
[2].iszr
, BAD_PC
);
16092 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16094 inst
.instruction
= 0xee010f00;
16095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16096 inst
.instruction
|= (fcond
& 0x4) << 10;
16097 inst
.instruction
|= (fcond
& 0x1) << 7;
16098 if (et
.type
== NT_float
)
16100 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16102 inst
.instruction
|= (et
.size
== 16) << 28;
16103 inst
.instruction
|= 0x3 << 20;
16107 inst
.instruction
|= 1 << 28;
16108 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16110 if (inst
.operands
[2].isquad
)
16112 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16113 inst
.instruction
|= (fcond
& 0x2) >> 1;
16114 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16118 if (inst
.operands
[2].reg
== REG_SP
)
16119 as_tsktsk (MVE_BAD_SP
);
16120 inst
.instruction
|= 1 << 6;
16121 inst
.instruction
|= (fcond
& 0x2) << 4;
16122 inst
.instruction
|= inst
.operands
[2].reg
;
16130 do_mve_vmaxa_vmina (void)
16132 if (inst
.cond
> COND_ALWAYS
)
16133 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16135 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16137 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16138 struct neon_type_el et
16139 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16142 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16144 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16150 do_mve_vfmas (void)
16152 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16153 struct neon_type_el et
16154 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16156 if (inst
.cond
> COND_ALWAYS
)
16157 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16159 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16161 if (inst
.operands
[2].reg
== REG_SP
)
16162 as_tsktsk (MVE_BAD_SP
);
16163 else if (inst
.operands
[2].reg
== REG_PC
)
16164 as_tsktsk (MVE_BAD_PC
);
16166 inst
.instruction
|= (et
.size
== 16) << 28;
16167 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16168 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16169 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16170 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16171 inst
.instruction
|= inst
.operands
[2].reg
;
16176 do_mve_viddup (void)
16178 if (inst
.cond
> COND_ALWAYS
)
16179 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16181 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16183 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16184 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16185 _("immediate must be either 1, 2, 4 or 8"));
16187 enum neon_shape rs
;
16188 struct neon_type_el et
;
16190 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16192 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16193 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16198 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16199 if (inst
.operands
[2].reg
== REG_SP
)
16200 as_tsktsk (MVE_BAD_SP
);
16201 else if (inst
.operands
[2].reg
== REG_PC
)
16202 first_error (BAD_PC
);
16204 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16205 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16206 Rm
= inst
.operands
[2].reg
>> 1;
16208 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16209 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16210 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16212 inst
.instruction
|= (imm
> 2) << 7;
16213 inst
.instruction
|= Rm
<< 1;
16214 inst
.instruction
|= (imm
== 2 || imm
== 8);
16219 do_mve_vmlas (void)
16221 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16222 struct neon_type_el et
16223 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16225 if (inst
.operands
[2].reg
== REG_PC
)
16226 as_tsktsk (MVE_BAD_PC
);
16227 else if (inst
.operands
[2].reg
== REG_SP
)
16228 as_tsktsk (MVE_BAD_SP
);
16230 if (inst
.cond
> COND_ALWAYS
)
16231 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16233 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16235 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16236 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16237 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16238 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16241 inst
.instruction
|= inst
.operands
[2].reg
;
16246 do_mve_vshll (void)
16248 struct neon_type_el et
16249 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16251 if (inst
.cond
> COND_ALWAYS
)
16252 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16254 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16256 int imm
= inst
.operands
[2].imm
;
16257 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16258 _("immediate value out of range"));
16260 if ((unsigned)imm
== et
.size
)
16262 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16263 inst
.instruction
|= 0x110001;
16267 inst
.instruction
|= (et
.size
+ imm
) << 16;
16268 inst
.instruction
|= 0x800140;
16271 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16273 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16274 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16275 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16280 do_mve_vshlc (void)
16282 if (inst
.cond
> COND_ALWAYS
)
16283 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16285 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16287 if (inst
.operands
[1].reg
== REG_PC
)
16288 as_tsktsk (MVE_BAD_PC
);
16289 else if (inst
.operands
[1].reg
== REG_SP
)
16290 as_tsktsk (MVE_BAD_SP
);
16292 int imm
= inst
.operands
[2].imm
;
16293 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16295 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16296 inst
.instruction
|= (imm
& 0x1f) << 16;
16297 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16298 inst
.instruction
|= inst
.operands
[1].reg
;
16303 do_mve_vshrn (void)
16306 switch (inst
.instruction
)
16308 case M_MNEM_vshrnt
:
16309 case M_MNEM_vshrnb
:
16310 case M_MNEM_vrshrnt
:
16311 case M_MNEM_vrshrnb
:
16312 types
= N_I16
| N_I32
;
16314 case M_MNEM_vqshrnt
:
16315 case M_MNEM_vqshrnb
:
16316 case M_MNEM_vqrshrnt
:
16317 case M_MNEM_vqrshrnb
:
16318 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16320 case M_MNEM_vqshrunt
:
16321 case M_MNEM_vqshrunb
:
16322 case M_MNEM_vqrshrunt
:
16323 case M_MNEM_vqrshrunb
:
16324 types
= N_S16
| N_S32
;
16330 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16332 if (inst
.cond
> COND_ALWAYS
)
16333 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16335 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16337 unsigned Qd
= inst
.operands
[0].reg
;
16338 unsigned Qm
= inst
.operands
[1].reg
;
16339 unsigned imm
= inst
.operands
[2].imm
;
16340 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16342 ? _("immediate operand expected in the range [1,8]")
16343 : _("immediate operand expected in the range [1,16]"));
16345 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16346 inst
.instruction
|= HI1 (Qd
) << 22;
16347 inst
.instruction
|= (et
.size
- imm
) << 16;
16348 inst
.instruction
|= LOW4 (Qd
) << 12;
16349 inst
.instruction
|= HI1 (Qm
) << 5;
16350 inst
.instruction
|= LOW4 (Qm
);
16355 do_mve_vqmovn (void)
16357 struct neon_type_el et
;
16358 if (inst
.instruction
== M_MNEM_vqmovnt
16359 || inst
.instruction
== M_MNEM_vqmovnb
)
16360 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16361 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16363 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16365 if (inst
.cond
> COND_ALWAYS
)
16366 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16368 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16370 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16371 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16372 inst
.instruction
|= (et
.size
== 32) << 18;
16373 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16374 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16375 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16380 do_mve_vpsel (void)
16382 neon_select_shape (NS_QQQ
, NS_NULL
);
16384 if (inst
.cond
> COND_ALWAYS
)
16385 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16387 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16389 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16390 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16392 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16393 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16394 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16399 do_mve_vpnot (void)
16401 if (inst
.cond
> COND_ALWAYS
)
16402 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16404 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16408 do_mve_vmaxnma_vminnma (void)
16410 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16411 struct neon_type_el et
16412 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16414 if (inst
.cond
> COND_ALWAYS
)
16415 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16417 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16419 inst
.instruction
|= (et
.size
== 16) << 28;
16420 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16421 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16423 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16428 do_mve_vcmul (void)
16430 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16431 struct neon_type_el et
16432 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16434 if (inst
.cond
> COND_ALWAYS
)
16435 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16437 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16439 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16440 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16441 _("immediate out of range"));
16443 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16444 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16445 as_tsktsk (BAD_MVE_SRCDEST
);
16447 inst
.instruction
|= (et
.size
== 32) << 28;
16448 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16449 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16450 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16451 inst
.instruction
|= (rot
> 90) << 12;
16452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16453 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16454 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16455 inst
.instruction
|= (rot
== 90 || rot
== 270);
16459 /* To handle the Low Overhead Loop instructions
16460 in Armv8.1-M Mainline and MVE. */
16464 unsigned long insn
= inst
.instruction
;
16466 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16468 if (insn
== T_MNEM_lctp
)
16471 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16473 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16475 struct neon_type_el et
16476 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16477 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16484 constraint (!inst
.operands
[0].present
,
16486 /* fall through. */
16489 if (!inst
.operands
[0].present
)
16490 inst
.instruction
|= 1 << 21;
16492 v8_1_loop_reloc (TRUE
);
16497 v8_1_loop_reloc (FALSE
);
16498 /* fall through. */
16501 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16503 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16504 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16505 else if (inst
.operands
[1].reg
== REG_PC
)
16506 as_tsktsk (MVE_BAD_PC
);
16507 if (inst
.operands
[1].reg
== REG_SP
)
16508 as_tsktsk (MVE_BAD_SP
);
16510 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16520 do_vfp_nsyn_cmp (void)
16522 enum neon_shape rs
;
16523 if (!inst
.operands
[0].isreg
)
16530 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16531 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16535 if (inst
.operands
[1].isreg
)
16537 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16538 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16540 if (rs
== NS_FF
|| rs
== NS_HH
)
16542 NEON_ENCODE (SINGLE
, inst
);
16543 do_vfp_sp_monadic ();
16547 NEON_ENCODE (DOUBLE
, inst
);
16548 do_vfp_dp_rd_rm ();
16553 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16554 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16556 switch (inst
.instruction
& 0x0fffffff)
16559 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16562 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16568 if (rs
== NS_FI
|| rs
== NS_HI
)
16570 NEON_ENCODE (SINGLE
, inst
);
16571 do_vfp_sp_compare_z ();
16575 NEON_ENCODE (DOUBLE
, inst
);
16579 do_vfp_cond_or_thumb ();
16581 /* ARMv8.2 fp16 instruction. */
16582 if (rs
== NS_HI
|| rs
== NS_HH
)
16583 do_scalar_fp16_v82_encode ();
16587 nsyn_insert_sp (void)
16589 inst
.operands
[1] = inst
.operands
[0];
16590 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16591 inst
.operands
[0].reg
= REG_SP
;
16592 inst
.operands
[0].isreg
= 1;
16593 inst
.operands
[0].writeback
= 1;
16594 inst
.operands
[0].present
= 1;
16597 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16598 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16601 neon_dp_fixup (struct arm_it
* insn
)
16603 unsigned int i
= insn
->instruction
;
16608 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16619 insn
->instruction
= i
;
16623 mve_encode_qqr (int size
, int U
, int fp
)
16625 if (inst
.operands
[2].reg
== REG_SP
)
16626 as_tsktsk (MVE_BAD_SP
);
16627 else if (inst
.operands
[2].reg
== REG_PC
)
16628 as_tsktsk (MVE_BAD_PC
);
16633 if (((unsigned)inst
.instruction
) == 0xd00)
16634 inst
.instruction
= 0xee300f40;
16636 else if (((unsigned)inst
.instruction
) == 0x200d00)
16637 inst
.instruction
= 0xee301f40;
16639 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16640 inst
.instruction
= 0xee310e60;
16642 /* Setting size which is 1 for F16 and 0 for F32. */
16643 inst
.instruction
|= (size
== 16) << 28;
16648 if (((unsigned)inst
.instruction
) == 0x800)
16649 inst
.instruction
= 0xee010f40;
16651 else if (((unsigned)inst
.instruction
) == 0x1000800)
16652 inst
.instruction
= 0xee011f40;
16654 else if (((unsigned)inst
.instruction
) == 0)
16655 inst
.instruction
= 0xee000f40;
16657 else if (((unsigned)inst
.instruction
) == 0x200)
16658 inst
.instruction
= 0xee001f40;
16660 else if (((unsigned)inst
.instruction
) == 0x900)
16661 inst
.instruction
= 0xee010e40;
16663 else if (((unsigned)inst
.instruction
) == 0x910)
16664 inst
.instruction
= 0xee011e60;
16666 else if (((unsigned)inst
.instruction
) == 0x10)
16667 inst
.instruction
= 0xee000f60;
16669 else if (((unsigned)inst
.instruction
) == 0x210)
16670 inst
.instruction
= 0xee001f60;
16672 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16673 inst
.instruction
= 0xee000e40;
16675 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16676 inst
.instruction
= 0xee010e60;
16678 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16679 inst
.instruction
= 0xfe010e60;
16682 inst
.instruction
|= U
<< 28;
16684 /* Setting bits for size. */
16685 inst
.instruction
|= neon_logbits (size
) << 20;
16687 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16688 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16689 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16690 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16691 inst
.instruction
|= inst
.operands
[2].reg
;
16696 mve_encode_rqq (unsigned bit28
, unsigned size
)
16698 inst
.instruction
|= bit28
<< 28;
16699 inst
.instruction
|= neon_logbits (size
) << 20;
16700 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16701 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16702 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16703 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16704 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16709 mve_encode_qqq (int ubit
, int size
)
16712 inst
.instruction
|= (ubit
!= 0) << 28;
16713 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16714 inst
.instruction
|= neon_logbits (size
) << 20;
16715 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16716 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16717 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16718 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16719 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16725 mve_encode_rq (unsigned bit28
, unsigned size
)
16727 inst
.instruction
|= bit28
<< 28;
16728 inst
.instruction
|= neon_logbits (size
) << 18;
16729 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16730 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16735 mve_encode_rrqq (unsigned U
, unsigned size
)
16737 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16739 inst
.instruction
|= U
<< 28;
16740 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16741 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16742 inst
.instruction
|= (size
== 32) << 16;
16743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16744 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16745 inst
.instruction
|= inst
.operands
[3].reg
;
16749 /* Helper function for neon_three_same handling the operands. */
16751 neon_three_args (int isquad
)
16753 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16754 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16755 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16756 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16757 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16758 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16759 inst
.instruction
|= (isquad
!= 0) << 6;
16763 /* Encode insns with bit pattern:
16765 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16766 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16768 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16769 different meaning for some instruction. */
16772 neon_three_same (int isquad
, int ubit
, int size
)
16774 neon_three_args (isquad
);
16775 inst
.instruction
|= (ubit
!= 0) << 24;
16777 inst
.instruction
|= neon_logbits (size
) << 20;
16779 neon_dp_fixup (&inst
);
16782 /* Encode instructions of the form:
16784 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16785 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16787 Don't write size if SIZE == -1. */
16790 neon_two_same (int qbit
, int ubit
, int size
)
16792 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16793 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16794 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16795 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16796 inst
.instruction
|= (qbit
!= 0) << 6;
16797 inst
.instruction
|= (ubit
!= 0) << 24;
16800 inst
.instruction
|= neon_logbits (size
) << 18;
16802 neon_dp_fixup (&inst
);
16805 enum vfp_or_neon_is_neon_bits
16808 NEON_CHECK_ARCH
= 2,
16809 NEON_CHECK_ARCH8
= 4
16812 /* Call this function if an instruction which may have belonged to the VFP or
16813 Neon instruction sets, but turned out to be a Neon instruction (due to the
16814 operand types involved, etc.). We have to check and/or fix-up a couple of
16817 - Make sure the user hasn't attempted to make a Neon instruction
16819 - Alter the value in the condition code field if necessary.
16820 - Make sure that the arch supports Neon instructions.
16822 Which of these operations take place depends on bits from enum
16823 vfp_or_neon_is_neon_bits.
16825 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16826 current instruction's condition is COND_ALWAYS, the condition field is
16827 changed to inst.uncond_value. This is necessary because instructions shared
16828 between VFP and Neon may be conditional for the VFP variants only, and the
16829 unconditional Neon version must have, e.g., 0xF in the condition field. */
16832 vfp_or_neon_is_neon (unsigned check
)
16834 /* Conditions are always legal in Thumb mode (IT blocks). */
16835 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16837 if (inst
.cond
!= COND_ALWAYS
)
16839 first_error (_(BAD_COND
));
16842 if (inst
.uncond_value
!= -1)
16843 inst
.instruction
|= inst
.uncond_value
<< 28;
16847 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16848 || ((check
& NEON_CHECK_ARCH8
)
16849 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16851 first_error (_(BAD_FPU
));
16859 /* Return TRUE if the SIMD instruction is available for the current
16860 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16861 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16862 vfp_or_neon_is_neon for the NEON specific checks. */
16865 check_simd_pred_availability (int fp
, unsigned check
)
16867 if (inst
.cond
> COND_ALWAYS
)
16869 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16871 inst
.error
= BAD_FPU
;
16874 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16876 else if (inst
.cond
< COND_ALWAYS
)
16878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16879 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16880 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16885 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16886 && vfp_or_neon_is_neon (check
) == FAIL
)
16889 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16890 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16895 /* Neon instruction encoders, in approximate order of appearance. */
16898 do_neon_dyadic_i_su (void)
16900 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16903 enum neon_shape rs
;
16904 struct neon_type_el et
;
16905 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16906 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16908 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16910 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16914 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16916 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16920 do_neon_dyadic_i64_su (void)
16922 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16924 enum neon_shape rs
;
16925 struct neon_type_el et
;
16926 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16928 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16929 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16933 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16934 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16937 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16939 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16943 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16946 unsigned size
= et
.size
>> 3;
16947 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16948 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16949 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16950 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16951 inst
.instruction
|= (isquad
!= 0) << 6;
16952 inst
.instruction
|= immbits
<< 16;
16953 inst
.instruction
|= (size
>> 3) << 7;
16954 inst
.instruction
|= (size
& 0x7) << 19;
16956 inst
.instruction
|= (uval
!= 0) << 24;
16958 neon_dp_fixup (&inst
);
16964 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16967 if (!inst
.operands
[2].isreg
)
16969 enum neon_shape rs
;
16970 struct neon_type_el et
;
16971 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16973 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16974 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16978 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16979 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16981 int imm
= inst
.operands
[2].imm
;
16983 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16984 _("immediate out of range for shift"));
16985 NEON_ENCODE (IMMED
, inst
);
16986 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16990 enum neon_shape rs
;
16991 struct neon_type_el et
;
16992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16994 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16995 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16999 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17000 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17006 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17007 _("invalid instruction shape"));
17008 if (inst
.operands
[2].reg
== REG_SP
)
17009 as_tsktsk (MVE_BAD_SP
);
17010 else if (inst
.operands
[2].reg
== REG_PC
)
17011 as_tsktsk (MVE_BAD_PC
);
17013 inst
.instruction
= 0xee311e60;
17014 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17016 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17017 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17018 inst
.instruction
|= inst
.operands
[2].reg
;
17025 /* VSHL/VQSHL 3-register variants have syntax such as:
17027 whereas other 3-register operations encoded by neon_three_same have
17030 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17031 operands[2].reg here. */
17032 tmp
= inst
.operands
[2].reg
;
17033 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17034 inst
.operands
[1].reg
= tmp
;
17035 NEON_ENCODE (INTEGER
, inst
);
17036 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17042 do_neon_qshl (void)
17044 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17047 if (!inst
.operands
[2].isreg
)
17049 enum neon_shape rs
;
17050 struct neon_type_el et
;
17051 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17053 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17054 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17058 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17059 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17061 int imm
= inst
.operands
[2].imm
;
17063 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17064 _("immediate out of range for shift"));
17065 NEON_ENCODE (IMMED
, inst
);
17066 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17070 enum neon_shape rs
;
17071 struct neon_type_el et
;
17073 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17075 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17076 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17080 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17081 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17086 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17087 _("invalid instruction shape"));
17088 if (inst
.operands
[2].reg
== REG_SP
)
17089 as_tsktsk (MVE_BAD_SP
);
17090 else if (inst
.operands
[2].reg
== REG_PC
)
17091 as_tsktsk (MVE_BAD_PC
);
17093 inst
.instruction
= 0xee311ee0;
17094 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17095 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17096 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17097 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17098 inst
.instruction
|= inst
.operands
[2].reg
;
17105 /* See note in do_neon_shl. */
17106 tmp
= inst
.operands
[2].reg
;
17107 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17108 inst
.operands
[1].reg
= tmp
;
17109 NEON_ENCODE (INTEGER
, inst
);
17110 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17116 do_neon_rshl (void)
17118 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17121 enum neon_shape rs
;
17122 struct neon_type_el et
;
17123 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17125 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17126 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17130 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17131 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17138 if (inst
.operands
[2].reg
== REG_PC
)
17139 as_tsktsk (MVE_BAD_PC
);
17140 else if (inst
.operands
[2].reg
== REG_SP
)
17141 as_tsktsk (MVE_BAD_SP
);
17143 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17144 _("invalid instruction shape"));
17146 if (inst
.instruction
== 0x0000510)
17147 /* We are dealing with vqrshl. */
17148 inst
.instruction
= 0xee331ee0;
17150 /* We are dealing with vrshl. */
17151 inst
.instruction
= 0xee331e60;
17153 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17154 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17155 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17156 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17157 inst
.instruction
|= inst
.operands
[2].reg
;
17162 tmp
= inst
.operands
[2].reg
;
17163 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17164 inst
.operands
[1].reg
= tmp
;
17165 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17170 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17172 /* Handle .I8 pseudo-instructions. */
17175 /* Unfortunately, this will make everything apart from zero out-of-range.
17176 FIXME is this the intended semantics? There doesn't seem much point in
17177 accepting .I8 if so. */
17178 immediate
|= immediate
<< 8;
17184 if (immediate
== (immediate
& 0x000000ff))
17186 *immbits
= immediate
;
17189 else if (immediate
== (immediate
& 0x0000ff00))
17191 *immbits
= immediate
>> 8;
17194 else if (immediate
== (immediate
& 0x00ff0000))
17196 *immbits
= immediate
>> 16;
17199 else if (immediate
== (immediate
& 0xff000000))
17201 *immbits
= immediate
>> 24;
17204 if ((immediate
& 0xffff) != (immediate
>> 16))
17205 goto bad_immediate
;
17206 immediate
&= 0xffff;
17209 if (immediate
== (immediate
& 0x000000ff))
17211 *immbits
= immediate
;
17214 else if (immediate
== (immediate
& 0x0000ff00))
17216 *immbits
= immediate
>> 8;
17221 first_error (_("immediate value out of range"));
17226 do_neon_logic (void)
17228 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17230 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17232 && !check_simd_pred_availability (FALSE
,
17233 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17235 else if (rs
!= NS_QQQ
17236 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17237 first_error (BAD_FPU
);
17239 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17240 /* U bit and size field were set as part of the bitmask. */
17241 NEON_ENCODE (INTEGER
, inst
);
17242 neon_three_same (neon_quad (rs
), 0, -1);
17246 const int three_ops_form
= (inst
.operands
[2].present
17247 && !inst
.operands
[2].isreg
);
17248 const int immoperand
= (three_ops_form
? 2 : 1);
17249 enum neon_shape rs
= (three_ops_form
17250 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17251 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17252 /* Because neon_select_shape makes the second operand a copy of the first
17253 if the second operand is not present. */
17255 && !check_simd_pred_availability (FALSE
,
17256 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17258 else if (rs
!= NS_QQI
17259 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17260 first_error (BAD_FPU
);
17262 struct neon_type_el et
;
17263 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17264 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17266 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17269 if (et
.type
== NT_invtype
)
17271 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17276 if (three_ops_form
)
17277 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17278 _("first and second operands shall be the same register"));
17280 NEON_ENCODE (IMMED
, inst
);
17282 immbits
= inst
.operands
[immoperand
].imm
;
17285 /* .i64 is a pseudo-op, so the immediate must be a repeating
17287 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17288 inst
.operands
[immoperand
].reg
: 0))
17290 /* Set immbits to an invalid constant. */
17291 immbits
= 0xdeadbeef;
17298 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17302 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17306 /* Pseudo-instruction for VBIC. */
17307 neon_invert_size (&immbits
, 0, et
.size
);
17308 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17312 /* Pseudo-instruction for VORR. */
17313 neon_invert_size (&immbits
, 0, et
.size
);
17314 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17324 inst
.instruction
|= neon_quad (rs
) << 6;
17325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17327 inst
.instruction
|= cmode
<< 8;
17328 neon_write_immbits (immbits
);
17330 neon_dp_fixup (&inst
);
17335 do_neon_bitfield (void)
17337 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17338 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17339 neon_three_same (neon_quad (rs
), 0, -1);
17343 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17346 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17347 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17349 if (et
.type
== NT_float
)
17351 NEON_ENCODE (FLOAT
, inst
);
17353 mve_encode_qqr (et
.size
, 0, 1);
17355 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17359 NEON_ENCODE (INTEGER
, inst
);
17361 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17363 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17369 do_neon_dyadic_if_su_d (void)
17371 /* This version only allow D registers, but that constraint is enforced during
17372 operand parsing so we don't need to do anything extra here. */
17373 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17377 do_neon_dyadic_if_i_d (void)
17379 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17380 affected if we specify unsigned args. */
17381 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17385 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17387 constraint (size
< 32, BAD_ADDR_MODE
);
17388 constraint (size
!= elsize
, BAD_EL_TYPE
);
17389 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17390 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17391 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17392 _("destination register and offset register may not be the"
17395 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17402 constraint ((imm
% (size
/ 8) != 0)
17403 || imm
> (0x7f << neon_logbits (size
)),
17404 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17405 " range of +/-[0,508]")
17406 : _("immediate must be a multiple of 8 in the"
17407 " range of +/-[0,1016]"));
17408 inst
.instruction
|= 0x11 << 24;
17409 inst
.instruction
|= add
<< 23;
17410 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17411 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17412 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17413 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17414 inst
.instruction
|= 1 << 12;
17415 inst
.instruction
|= (size
== 64) << 8;
17416 inst
.instruction
&= 0xffffff00;
17417 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17418 inst
.instruction
|= imm
>> neon_logbits (size
);
17422 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17424 unsigned os
= inst
.operands
[1].imm
>> 5;
17425 unsigned type
= inst
.vectype
.el
[0].type
;
17426 constraint (os
!= 0 && size
== 8,
17427 _("can not shift offsets when accessing less than half-word"));
17428 constraint (os
&& os
!= neon_logbits (size
),
17429 _("shift immediate must be 1, 2 or 3 for half-word, word"
17430 " or double-word accesses respectively"));
17431 if (inst
.operands
[1].reg
== REG_PC
)
17432 as_tsktsk (MVE_BAD_PC
);
17437 constraint (elsize
>= 64, BAD_EL_TYPE
);
17440 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17444 constraint (elsize
!= size
, BAD_EL_TYPE
);
17449 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17453 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17454 _("destination register and offset register may not be"
17456 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17457 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17459 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17463 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17466 inst
.instruction
|= 1 << 23;
17467 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17468 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17469 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17470 inst
.instruction
|= neon_logbits (elsize
) << 7;
17471 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17472 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17473 inst
.instruction
|= !!os
;
17477 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17479 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17481 constraint (size
>= 64, BAD_ADDR_MODE
);
17485 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17488 constraint (elsize
!= size
, BAD_EL_TYPE
);
17495 constraint (elsize
!= size
&& type
!= NT_unsigned
17496 && type
!= NT_signed
, BAD_EL_TYPE
);
17500 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17503 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17511 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17516 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17519 constraint (1, _("immediate must be a multiple of 2 in the"
17520 " range of +/-[0,254]"));
17523 constraint (1, _("immediate must be a multiple of 4 in the"
17524 " range of +/-[0,508]"));
17529 if (size
!= elsize
)
17531 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17532 constraint (inst
.operands
[0].reg
> 14,
17533 _("MVE vector register in the range [Q0..Q7] expected"));
17534 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17535 inst
.instruction
|= (size
== 16) << 19;
17536 inst
.instruction
|= neon_logbits (elsize
) << 7;
17540 if (inst
.operands
[1].reg
== REG_PC
)
17541 as_tsktsk (MVE_BAD_PC
);
17542 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17543 as_tsktsk (MVE_BAD_SP
);
17544 inst
.instruction
|= 1 << 12;
17545 inst
.instruction
|= neon_logbits (size
) << 7;
17547 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17548 inst
.instruction
|= add
<< 23;
17549 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17550 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17551 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17552 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17553 inst
.instruction
&= 0xffffff80;
17554 inst
.instruction
|= imm
>> neon_logbits (size
);
17559 do_mve_vstr_vldr (void)
17564 if (inst
.cond
> COND_ALWAYS
)
17565 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17567 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17569 switch (inst
.instruction
)
17576 /* fall through. */
17582 /* fall through. */
17588 /* fall through. */
17594 /* fall through. */
17599 unsigned elsize
= inst
.vectype
.el
[0].size
;
17601 if (inst
.operands
[1].isquad
)
17603 /* We are dealing with [Q, imm]{!} cases. */
17604 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17608 if (inst
.operands
[1].immisreg
== 2)
17610 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17611 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17613 else if (!inst
.operands
[1].immisreg
)
17615 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17616 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17619 constraint (1, BAD_ADDR_MODE
);
17626 do_mve_vst_vld (void)
17628 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17631 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17632 || inst
.relocs
[0].exp
.X_add_number
!= 0
17633 || inst
.operands
[1].immisreg
!= 0,
17635 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17636 if (inst
.operands
[1].reg
== REG_PC
)
17637 as_tsktsk (MVE_BAD_PC
);
17638 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17639 as_tsktsk (MVE_BAD_SP
);
17642 /* These instructions are one of the "exceptions" mentioned in
17643 handle_pred_state. They are MVE instructions that are not VPT compatible
17644 and do not accept a VPT code, thus appending such a code is a syntax
17646 if (inst
.cond
> COND_ALWAYS
)
17647 first_error (BAD_SYNTAX
);
17648 /* If we append a scalar condition code we can set this to
17649 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17650 else if (inst
.cond
< COND_ALWAYS
)
17651 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17653 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17655 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17656 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17657 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17658 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17659 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17664 do_mve_vaddlv (void)
17666 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17667 struct neon_type_el et
17668 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17670 if (et
.type
== NT_invtype
)
17671 first_error (BAD_EL_TYPE
);
17673 if (inst
.cond
> COND_ALWAYS
)
17674 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17676 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17678 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17680 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17681 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17683 inst
.instruction
|= inst
.operands
[2].reg
;
17688 do_neon_dyadic_if_su (void)
17690 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17691 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17694 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17695 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17696 && et
.type
== NT_float
17697 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17699 if (!check_simd_pred_availability (et
.type
== NT_float
,
17700 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17703 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17707 do_neon_addsub_if_i (void)
17709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17710 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17713 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17714 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17715 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17717 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17718 /* If we are parsing Q registers and the element types match MVE, which NEON
17719 also supports, then we must check whether this is an instruction that can
17720 be used by both MVE/NEON. This distinction can be made based on whether
17721 they are predicated or not. */
17722 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17724 if (!check_simd_pred_availability (et
.type
== NT_float
,
17725 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17730 /* If they are either in a D register or are using an unsupported. */
17732 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17736 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17737 affected if we specify unsigned args. */
17738 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17741 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17743 V<op> A,B (A is operand 0, B is operand 2)
17748 so handle that case specially. */
17751 neon_exchange_operands (void)
17753 if (inst
.operands
[1].present
)
17755 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17757 /* Swap operands[1] and operands[2]. */
17758 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17759 inst
.operands
[1] = inst
.operands
[2];
17760 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17765 inst
.operands
[1] = inst
.operands
[2];
17766 inst
.operands
[2] = inst
.operands
[0];
17771 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17773 if (inst
.operands
[2].isreg
)
17776 neon_exchange_operands ();
17777 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17781 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17782 struct neon_type_el et
= neon_check_type (2, rs
,
17783 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17785 NEON_ENCODE (IMMED
, inst
);
17786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17790 inst
.instruction
|= neon_quad (rs
) << 6;
17791 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17792 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17794 neon_dp_fixup (&inst
);
17801 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17805 do_neon_cmp_inv (void)
17807 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17813 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17816 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17817 scalars, which are encoded in 5 bits, M : Rm.
17818 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17819 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17822 Dot Product instructions are similar to multiply instructions except elsize
17823 should always be 32.
17825 This function translates SCALAR, which is GAS's internal encoding of indexed
17826 scalar register, to raw encoding. There is also register and index range
17827 check based on ELSIZE. */
17830 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17832 unsigned regno
= NEON_SCALAR_REG (scalar
);
17833 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17838 if (regno
> 7 || elno
> 3)
17840 return regno
| (elno
<< 3);
17843 if (regno
> 15 || elno
> 1)
17845 return regno
| (elno
<< 4);
17849 first_error (_("scalar out of range for multiply instruction"));
17855 /* Encode multiply / multiply-accumulate scalar instructions. */
17858 neon_mul_mac (struct neon_type_el et
, int ubit
)
17862 /* Give a more helpful error message if we have an invalid type. */
17863 if (et
.type
== NT_invtype
)
17866 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17867 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17868 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17869 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17870 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17871 inst
.instruction
|= LOW4 (scalar
);
17872 inst
.instruction
|= HI1 (scalar
) << 5;
17873 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17874 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17875 inst
.instruction
|= (ubit
!= 0) << 24;
17877 neon_dp_fixup (&inst
);
17881 do_neon_mac_maybe_scalar (void)
17883 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17886 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17889 if (inst
.operands
[2].isscalar
)
17891 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17892 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17893 struct neon_type_el et
= neon_check_type (3, rs
,
17894 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17895 NEON_ENCODE (SCALAR
, inst
);
17896 neon_mul_mac (et
, neon_quad (rs
));
17898 else if (!inst
.operands
[2].isvec
)
17900 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17902 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17903 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17905 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17909 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17910 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17911 affected if we specify unsigned args. */
17912 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17917 do_bfloat_vfma (void)
17919 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17920 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17921 enum neon_shape rs
;
17924 if (inst
.instruction
!= B_MNEM_vfmab
)
17927 inst
.instruction
= B_MNEM_vfmat
;
17930 if (inst
.operands
[2].isscalar
)
17932 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17933 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17935 inst
.instruction
|= (1 << 25);
17936 int index
= inst
.operands
[2].reg
& 0xf;
17937 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17938 inst
.operands
[2].reg
>>= 4;
17939 constraint (!(inst
.operands
[2].reg
< 8),
17940 _("indexed register must be less than 8"));
17941 neon_three_args (t_bit
);
17942 inst
.instruction
|= ((index
& 1) << 3);
17943 inst
.instruction
|= ((index
& 2) << 4);
17947 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17948 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17949 neon_three_args (t_bit
);
17955 do_neon_fmac (void)
17957 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17958 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17961 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17964 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17966 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17967 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17973 if (inst
.operands
[2].reg
== REG_SP
)
17974 as_tsktsk (MVE_BAD_SP
);
17975 else if (inst
.operands
[2].reg
== REG_PC
)
17976 as_tsktsk (MVE_BAD_PC
);
17978 inst
.instruction
= 0xee310e40;
17979 inst
.instruction
|= (et
.size
== 16) << 28;
17980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17981 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17982 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17983 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17984 inst
.instruction
|= inst
.operands
[2].reg
;
17991 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17994 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
18000 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
18001 inst
.cond
== COND_ALWAYS
)
18003 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18004 inst
.instruction
= N_MNEM_vfma
;
18005 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18007 return do_neon_fmac();
18018 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18019 struct neon_type_el et
= neon_check_type (3, rs
,
18020 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18021 neon_three_same (neon_quad (rs
), 0, et
.size
);
18024 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18025 same types as the MAC equivalents. The polynomial type for this instruction
18026 is encoded the same as the integer type. */
18031 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18034 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18037 if (inst
.operands
[2].isscalar
)
18039 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18040 do_neon_mac_maybe_scalar ();
18044 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18046 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18047 struct neon_type_el et
18048 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18049 if (et
.type
== NT_float
)
18050 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18053 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18057 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18058 neon_dyadic_misc (NT_poly
,
18059 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18065 do_neon_qdmulh (void)
18067 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18070 if (inst
.operands
[2].isscalar
)
18072 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18073 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18074 struct neon_type_el et
= neon_check_type (3, rs
,
18075 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18076 NEON_ENCODE (SCALAR
, inst
);
18077 neon_mul_mac (et
, neon_quad (rs
));
18081 enum neon_shape rs
;
18082 struct neon_type_el et
;
18083 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18085 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18086 et
= neon_check_type (3, rs
,
18087 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18091 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18092 et
= neon_check_type (3, rs
,
18093 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18096 NEON_ENCODE (INTEGER
, inst
);
18098 mve_encode_qqr (et
.size
, 0, 0);
18100 /* The U bit (rounding) comes from bit mask. */
18101 neon_three_same (neon_quad (rs
), 0, et
.size
);
18106 do_mve_vaddv (void)
18108 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18109 struct neon_type_el et
18110 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18112 if (et
.type
== NT_invtype
)
18113 first_error (BAD_EL_TYPE
);
18115 if (inst
.cond
> COND_ALWAYS
)
18116 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18118 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18120 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18122 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18126 do_mve_vhcadd (void)
18128 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18129 struct neon_type_el et
18130 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18132 if (inst
.cond
> COND_ALWAYS
)
18133 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18135 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18137 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18138 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18140 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18141 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18142 "operand makes instruction UNPREDICTABLE"));
18144 mve_encode_qqq (0, et
.size
);
18145 inst
.instruction
|= (rot
== 270) << 12;
18150 do_mve_vqdmull (void)
18152 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18153 struct neon_type_el et
18154 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18157 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18158 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18159 as_tsktsk (BAD_MVE_SRCDEST
);
18161 if (inst
.cond
> COND_ALWAYS
)
18162 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18164 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18168 mve_encode_qqq (et
.size
== 32, 64);
18169 inst
.instruction
|= 1;
18173 mve_encode_qqr (64, et
.size
== 32, 0);
18174 inst
.instruction
|= 0x3 << 5;
18181 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18182 struct neon_type_el et
18183 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18185 if (et
.type
== NT_invtype
)
18186 first_error (BAD_EL_TYPE
);
18188 if (inst
.cond
> COND_ALWAYS
)
18189 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18191 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18193 mve_encode_qqq (0, 64);
18197 do_mve_vbrsr (void)
18199 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18200 struct neon_type_el et
18201 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18203 if (inst
.cond
> COND_ALWAYS
)
18204 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18206 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18208 mve_encode_qqr (et
.size
, 0, 0);
18214 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18216 if (inst
.cond
> COND_ALWAYS
)
18217 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18219 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18221 mve_encode_qqq (1, 64);
18225 do_mve_vmulh (void)
18227 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18228 struct neon_type_el et
18229 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18231 if (inst
.cond
> COND_ALWAYS
)
18232 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18234 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18236 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18240 do_mve_vqdmlah (void)
18242 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18243 struct neon_type_el et
18244 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18246 if (inst
.cond
> COND_ALWAYS
)
18247 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18249 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18251 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18255 do_mve_vqdmladh (void)
18257 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18258 struct neon_type_el et
18259 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18261 if (inst
.cond
> COND_ALWAYS
)
18262 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18264 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18266 mve_encode_qqq (0, et
.size
);
18271 do_mve_vmull (void)
18274 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18275 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18276 if (inst
.cond
== COND_ALWAYS
18277 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18282 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18289 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18290 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18291 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18293 /* We are dealing with MVE's vmullt. */
18295 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18296 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18297 as_tsktsk (BAD_MVE_SRCDEST
);
18299 if (inst
.cond
> COND_ALWAYS
)
18300 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18302 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18304 if (et
.type
== NT_poly
)
18305 mve_encode_qqq (neon_logbits (et
.size
), 64);
18307 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18312 inst
.instruction
= N_MNEM_vmul
;
18315 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18320 do_mve_vabav (void)
18322 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18327 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18330 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18331 | N_S16
| N_S32
| N_U8
| N_U16
18334 if (inst
.cond
> COND_ALWAYS
)
18335 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18337 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18339 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18343 do_mve_vmladav (void)
18345 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18346 struct neon_type_el et
= neon_check_type (3, rs
,
18347 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18349 if (et
.type
== NT_unsigned
18350 && (inst
.instruction
== M_MNEM_vmladavx
18351 || inst
.instruction
== M_MNEM_vmladavax
18352 || inst
.instruction
== M_MNEM_vmlsdav
18353 || inst
.instruction
== M_MNEM_vmlsdava
18354 || inst
.instruction
== M_MNEM_vmlsdavx
18355 || inst
.instruction
== M_MNEM_vmlsdavax
))
18356 first_error (BAD_SIMD_TYPE
);
18358 constraint (inst
.operands
[2].reg
> 14,
18359 _("MVE vector register in the range [Q0..Q7] expected"));
18361 if (inst
.cond
> COND_ALWAYS
)
18362 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18364 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18366 if (inst
.instruction
== M_MNEM_vmlsdav
18367 || inst
.instruction
== M_MNEM_vmlsdava
18368 || inst
.instruction
== M_MNEM_vmlsdavx
18369 || inst
.instruction
== M_MNEM_vmlsdavax
)
18370 inst
.instruction
|= (et
.size
== 8) << 28;
18372 inst
.instruction
|= (et
.size
== 8) << 8;
18374 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18375 inst
.instruction
|= (et
.size
== 32) << 16;
18379 do_mve_vmlaldav (void)
18381 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18382 struct neon_type_el et
18383 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18384 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18386 if (et
.type
== NT_unsigned
18387 && (inst
.instruction
== M_MNEM_vmlsldav
18388 || inst
.instruction
== M_MNEM_vmlsldava
18389 || inst
.instruction
== M_MNEM_vmlsldavx
18390 || inst
.instruction
== M_MNEM_vmlsldavax
))
18391 first_error (BAD_SIMD_TYPE
);
18393 if (inst
.cond
> COND_ALWAYS
)
18394 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18396 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18398 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18402 do_mve_vrmlaldavh (void)
18404 struct neon_type_el et
;
18405 if (inst
.instruction
== M_MNEM_vrmlsldavh
18406 || inst
.instruction
== M_MNEM_vrmlsldavha
18407 || inst
.instruction
== M_MNEM_vrmlsldavhx
18408 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18410 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18411 if (inst
.operands
[1].reg
== REG_SP
)
18412 as_tsktsk (MVE_BAD_SP
);
18416 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18417 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18418 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18420 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18421 N_U32
| N_S32
| N_KEY
);
18422 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18423 with vmax/min instructions, making the use of SP in assembly really
18424 nonsensical, so instead of issuing a warning like we do for other uses
18425 of SP for the odd register operand we error out. */
18426 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18429 /* Make sure we still check the second operand is an odd one and that PC is
18430 disallowed. This because we are parsing for any GPR operand, to be able
18431 to distinguish between giving a warning or an error for SP as described
18433 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18434 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18436 if (inst
.cond
> COND_ALWAYS
)
18437 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18439 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18441 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18446 do_mve_vmaxnmv (void)
18448 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18449 struct neon_type_el et
18450 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18452 if (inst
.cond
> COND_ALWAYS
)
18453 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18455 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18457 if (inst
.operands
[0].reg
== REG_SP
)
18458 as_tsktsk (MVE_BAD_SP
);
18459 else if (inst
.operands
[0].reg
== REG_PC
)
18460 as_tsktsk (MVE_BAD_PC
);
18462 mve_encode_rq (et
.size
== 16, 64);
18466 do_mve_vmaxv (void)
18468 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18469 struct neon_type_el et
;
18471 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18472 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18474 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18476 if (inst
.cond
> COND_ALWAYS
)
18477 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18479 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18481 if (inst
.operands
[0].reg
== REG_SP
)
18482 as_tsktsk (MVE_BAD_SP
);
18483 else if (inst
.operands
[0].reg
== REG_PC
)
18484 as_tsktsk (MVE_BAD_PC
);
18486 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18491 do_neon_qrdmlah (void)
18493 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18495 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18497 /* Check we're on the correct architecture. */
18498 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18500 = _("instruction form not available on this architecture.");
18501 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18503 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18504 record_feature_use (&fpu_neon_ext_v8_1
);
18506 if (inst
.operands
[2].isscalar
)
18508 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18509 struct neon_type_el et
= neon_check_type (3, rs
,
18510 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18511 NEON_ENCODE (SCALAR
, inst
);
18512 neon_mul_mac (et
, neon_quad (rs
));
18516 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18517 struct neon_type_el et
= neon_check_type (3, rs
,
18518 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18519 NEON_ENCODE (INTEGER
, inst
);
18520 /* The U bit (rounding) comes from bit mask. */
18521 neon_three_same (neon_quad (rs
), 0, et
.size
);
18526 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18527 struct neon_type_el et
18528 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18530 NEON_ENCODE (INTEGER
, inst
);
18531 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18536 do_neon_fcmp_absolute (void)
18538 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18539 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18540 N_F_16_32
| N_KEY
);
18541 /* Size field comes from bit mask. */
18542 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18546 do_neon_fcmp_absolute_inv (void)
18548 neon_exchange_operands ();
18549 do_neon_fcmp_absolute ();
18553 do_neon_step (void)
18555 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18556 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18557 N_F_16_32
| N_KEY
);
18558 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18562 do_neon_abs_neg (void)
18564 enum neon_shape rs
;
18565 struct neon_type_el et
;
18567 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18570 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18571 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18573 if (!check_simd_pred_availability (et
.type
== NT_float
,
18574 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18577 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18578 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18579 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18580 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18581 inst
.instruction
|= neon_quad (rs
) << 6;
18582 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18583 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18585 neon_dp_fixup (&inst
);
18591 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18594 enum neon_shape rs
;
18595 struct neon_type_el et
;
18596 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18598 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18599 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18603 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18604 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18608 int imm
= inst
.operands
[2].imm
;
18609 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18610 _("immediate out of range for insert"));
18611 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18617 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18620 enum neon_shape rs
;
18621 struct neon_type_el et
;
18622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18624 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18625 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18629 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18630 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18633 int imm
= inst
.operands
[2].imm
;
18634 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18635 _("immediate out of range for insert"));
18636 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18640 do_neon_qshlu_imm (void)
18642 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18645 enum neon_shape rs
;
18646 struct neon_type_el et
;
18647 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18649 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18650 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18654 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18655 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18656 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18659 int imm
= inst
.operands
[2].imm
;
18660 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18661 _("immediate out of range for shift"));
18662 /* Only encodes the 'U present' variant of the instruction.
18663 In this case, signed types have OP (bit 8) set to 0.
18664 Unsigned types have OP set to 1. */
18665 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18666 /* The rest of the bits are the same as other immediate shifts. */
18667 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18671 do_neon_qmovn (void)
18673 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18674 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18675 /* Saturating move where operands can be signed or unsigned, and the
18676 destination has the same signedness. */
18677 NEON_ENCODE (INTEGER
, inst
);
18678 if (et
.type
== NT_unsigned
)
18679 inst
.instruction
|= 0xc0;
18681 inst
.instruction
|= 0x80;
18682 neon_two_same (0, 1, et
.size
/ 2);
18686 do_neon_qmovun (void)
18688 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18689 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18690 /* Saturating move with unsigned results. Operands must be signed. */
18691 NEON_ENCODE (INTEGER
, inst
);
18692 neon_two_same (0, 1, et
.size
/ 2);
18696 do_neon_rshift_sat_narrow (void)
18698 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18699 or unsigned. If operands are unsigned, results must also be unsigned. */
18700 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18701 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18702 int imm
= inst
.operands
[2].imm
;
18703 /* This gets the bounds check, size encoding and immediate bits calculation
18707 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18708 VQMOVN.I<size> <Dd>, <Qm>. */
18711 inst
.operands
[2].present
= 0;
18712 inst
.instruction
= N_MNEM_vqmovn
;
18717 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18718 _("immediate out of range"));
18719 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18723 do_neon_rshift_sat_narrow_u (void)
18725 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18726 or unsigned. If operands are unsigned, results must also be unsigned. */
18727 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18728 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18729 int imm
= inst
.operands
[2].imm
;
18730 /* This gets the bounds check, size encoding and immediate bits calculation
18734 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18735 VQMOVUN.I<size> <Dd>, <Qm>. */
18738 inst
.operands
[2].present
= 0;
18739 inst
.instruction
= N_MNEM_vqmovun
;
18744 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18745 _("immediate out of range"));
18746 /* FIXME: The manual is kind of unclear about what value U should have in
18747 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18749 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18753 do_neon_movn (void)
18755 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18756 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18757 NEON_ENCODE (INTEGER
, inst
);
18758 neon_two_same (0, 1, et
.size
/ 2);
18762 do_neon_rshift_narrow (void)
18764 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18765 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18766 int imm
= inst
.operands
[2].imm
;
18767 /* This gets the bounds check, size encoding and immediate bits calculation
18771 /* If immediate is zero then we are a pseudo-instruction for
18772 VMOVN.I<size> <Dd>, <Qm> */
18775 inst
.operands
[2].present
= 0;
18776 inst
.instruction
= N_MNEM_vmovn
;
18781 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18782 _("immediate out of range for narrowing operation"));
18783 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18787 do_neon_shll (void)
18789 /* FIXME: Type checking when lengthening. */
18790 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18791 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18792 unsigned imm
= inst
.operands
[2].imm
;
18794 if (imm
== et
.size
)
18796 /* Maximum shift variant. */
18797 NEON_ENCODE (INTEGER
, inst
);
18798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18800 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18801 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18802 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18804 neon_dp_fixup (&inst
);
18808 /* A more-specific type check for non-max versions. */
18809 et
= neon_check_type (2, NS_QDI
,
18810 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18811 NEON_ENCODE (IMMED
, inst
);
18812 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18816 /* Check the various types for the VCVT instruction, and return which version
18817 the current instruction is. */
18819 #define CVT_FLAVOUR_VAR \
18820 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18821 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18822 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18823 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18824 /* Half-precision conversions. */ \
18825 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18827 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18828 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18829 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18830 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18831 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18832 Compared with single/double precision variants, only the co-processor \
18833 field is different, so the encoding flow is reused here. */ \
18834 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18835 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18836 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18837 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18838 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18839 /* VFP instructions. */ \
18840 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18841 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18842 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18843 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18844 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18845 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18846 /* VFP instructions with bitshift. */ \
18847 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18848 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18849 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18850 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18851 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18852 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18853 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18854 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18856 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18857 neon_cvt_flavour_##C,
18859 /* The different types of conversions we can do. */
18860 enum neon_cvt_flavour
18863 neon_cvt_flavour_invalid
,
18864 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18869 static enum neon_cvt_flavour
18870 get_neon_cvt_flavour (enum neon_shape rs
)
18872 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18873 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18874 if (et.type != NT_invtype) \
18876 inst.error = NULL; \
18877 return (neon_cvt_flavour_##C); \
18880 struct neon_type_el et
;
18881 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18882 || rs
== NS_FF
) ? N_VFP
: 0;
18883 /* The instruction versions which take an immediate take one register
18884 argument, which is extended to the width of the full register. Thus the
18885 "source" and "destination" registers must have the same width. Hack that
18886 here by making the size equal to the key (wider, in this case) operand. */
18887 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18891 return neon_cvt_flavour_invalid
;
18906 /* Neon-syntax VFP conversions. */
18909 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18911 const char *opname
= 0;
18913 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18914 || rs
== NS_FHI
|| rs
== NS_HFI
)
18916 /* Conversions with immediate bitshift. */
18917 const char *enc
[] =
18919 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18925 if (flavour
< (int) ARRAY_SIZE (enc
))
18927 opname
= enc
[flavour
];
18928 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18929 _("operands 0 and 1 must be the same register"));
18930 inst
.operands
[1] = inst
.operands
[2];
18931 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18936 /* Conversions without bitshift. */
18937 const char *enc
[] =
18939 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18945 if (flavour
< (int) ARRAY_SIZE (enc
))
18946 opname
= enc
[flavour
];
18950 do_vfp_nsyn_opcode (opname
);
18952 /* ARMv8.2 fp16 VCVT instruction. */
18953 if (flavour
== neon_cvt_flavour_s32_f16
18954 || flavour
== neon_cvt_flavour_u32_f16
18955 || flavour
== neon_cvt_flavour_f16_u32
18956 || flavour
== neon_cvt_flavour_f16_s32
)
18957 do_scalar_fp16_v82_encode ();
18961 do_vfp_nsyn_cvtz (void)
18963 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18964 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18965 const char *enc
[] =
18967 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18973 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18974 do_vfp_nsyn_opcode (enc
[flavour
]);
18978 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18979 enum neon_cvt_mode mode
)
18984 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18985 D register operands. */
18986 if (flavour
== neon_cvt_flavour_s32_f64
18987 || flavour
== neon_cvt_flavour_u32_f64
)
18988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18991 if (flavour
== neon_cvt_flavour_s32_f16
18992 || flavour
== neon_cvt_flavour_u32_f16
)
18993 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18996 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19000 case neon_cvt_flavour_s32_f64
:
19004 case neon_cvt_flavour_s32_f32
:
19008 case neon_cvt_flavour_s32_f16
:
19012 case neon_cvt_flavour_u32_f64
:
19016 case neon_cvt_flavour_u32_f32
:
19020 case neon_cvt_flavour_u32_f16
:
19025 first_error (_("invalid instruction shape"));
19031 case neon_cvt_mode_a
: rm
= 0; break;
19032 case neon_cvt_mode_n
: rm
= 1; break;
19033 case neon_cvt_mode_p
: rm
= 2; break;
19034 case neon_cvt_mode_m
: rm
= 3; break;
19035 default: first_error (_("invalid rounding mode")); return;
19038 NEON_ENCODE (FPV8
, inst
);
19039 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19040 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19041 inst
.instruction
|= sz
<< 8;
19043 /* ARMv8.2 fp16 VCVT instruction. */
19044 if (flavour
== neon_cvt_flavour_s32_f16
19045 ||flavour
== neon_cvt_flavour_u32_f16
)
19046 do_scalar_fp16_v82_encode ();
19047 inst
.instruction
|= op
<< 7;
19048 inst
.instruction
|= rm
<< 16;
19049 inst
.instruction
|= 0xf0000000;
19050 inst
.is_neon
= TRUE
;
19054 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19056 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19057 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19058 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19060 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19062 if (flavour
== neon_cvt_flavour_invalid
)
19065 /* PR11109: Handle round-to-zero for VCVT conversions. */
19066 if (mode
== neon_cvt_mode_z
19067 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19068 && (flavour
== neon_cvt_flavour_s16_f16
19069 || flavour
== neon_cvt_flavour_u16_f16
19070 || flavour
== neon_cvt_flavour_s32_f32
19071 || flavour
== neon_cvt_flavour_u32_f32
19072 || flavour
== neon_cvt_flavour_s32_f64
19073 || flavour
== neon_cvt_flavour_u32_f64
)
19074 && (rs
== NS_FD
|| rs
== NS_FF
))
19076 do_vfp_nsyn_cvtz ();
19080 /* ARMv8.2 fp16 VCVT conversions. */
19081 if (mode
== neon_cvt_mode_z
19082 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19083 && (flavour
== neon_cvt_flavour_s32_f16
19084 || flavour
== neon_cvt_flavour_u32_f16
)
19087 do_vfp_nsyn_cvtz ();
19088 do_scalar_fp16_v82_encode ();
19092 /* VFP rather than Neon conversions. */
19093 if (flavour
>= neon_cvt_flavour_first_fp
)
19095 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19096 do_vfp_nsyn_cvt (rs
, flavour
);
19098 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19106 if (mode
== neon_cvt_mode_z
19107 && (flavour
== neon_cvt_flavour_f16_s16
19108 || flavour
== neon_cvt_flavour_f16_u16
19109 || flavour
== neon_cvt_flavour_s16_f16
19110 || flavour
== neon_cvt_flavour_u16_f16
19111 || flavour
== neon_cvt_flavour_f32_u32
19112 || flavour
== neon_cvt_flavour_f32_s32
19113 || flavour
== neon_cvt_flavour_s32_f32
19114 || flavour
== neon_cvt_flavour_u32_f32
))
19116 if (!check_simd_pred_availability (TRUE
,
19117 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19120 else if (mode
== neon_cvt_mode_n
)
19122 /* We are dealing with vcvt with the 'ne' condition. */
19124 inst
.instruction
= N_MNEM_vcvt
;
19125 do_neon_cvt_1 (neon_cvt_mode_z
);
19128 /* fall through. */
19132 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19133 0x0000100, 0x1000100, 0x0, 0x1000000};
19135 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19136 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19139 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19141 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19142 _("immediate value out of range"));
19145 case neon_cvt_flavour_f16_s16
:
19146 case neon_cvt_flavour_f16_u16
:
19147 case neon_cvt_flavour_s16_f16
:
19148 case neon_cvt_flavour_u16_f16
:
19149 constraint (inst
.operands
[2].imm
> 16,
19150 _("immediate value out of range"));
19152 case neon_cvt_flavour_f32_u32
:
19153 case neon_cvt_flavour_f32_s32
:
19154 case neon_cvt_flavour_s32_f32
:
19155 case neon_cvt_flavour_u32_f32
:
19156 constraint (inst
.operands
[2].imm
> 32,
19157 _("immediate value out of range"));
19160 inst
.error
= BAD_FPU
;
19165 /* Fixed-point conversion with #0 immediate is encoded as an
19166 integer conversion. */
19167 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19169 NEON_ENCODE (IMMED
, inst
);
19170 if (flavour
!= neon_cvt_flavour_invalid
)
19171 inst
.instruction
|= enctab
[flavour
];
19172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19173 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19174 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19175 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19176 inst
.instruction
|= neon_quad (rs
) << 6;
19177 inst
.instruction
|= 1 << 21;
19178 if (flavour
< neon_cvt_flavour_s16_f16
)
19180 inst
.instruction
|= 1 << 21;
19181 immbits
= 32 - inst
.operands
[2].imm
;
19182 inst
.instruction
|= immbits
<< 16;
19186 inst
.instruction
|= 3 << 20;
19187 immbits
= 16 - inst
.operands
[2].imm
;
19188 inst
.instruction
|= immbits
<< 16;
19189 inst
.instruction
&= ~(1 << 9);
19192 neon_dp_fixup (&inst
);
19197 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19198 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19199 && (flavour
== neon_cvt_flavour_s16_f16
19200 || flavour
== neon_cvt_flavour_u16_f16
19201 || flavour
== neon_cvt_flavour_s32_f32
19202 || flavour
== neon_cvt_flavour_u32_f32
))
19204 if (!check_simd_pred_availability (TRUE
,
19205 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19208 else if (mode
== neon_cvt_mode_z
19209 && (flavour
== neon_cvt_flavour_f16_s16
19210 || flavour
== neon_cvt_flavour_f16_u16
19211 || flavour
== neon_cvt_flavour_s16_f16
19212 || flavour
== neon_cvt_flavour_u16_f16
19213 || flavour
== neon_cvt_flavour_f32_u32
19214 || flavour
== neon_cvt_flavour_f32_s32
19215 || flavour
== neon_cvt_flavour_s32_f32
19216 || flavour
== neon_cvt_flavour_u32_f32
))
19218 if (!check_simd_pred_availability (TRUE
,
19219 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19222 /* fall through. */
19224 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19227 NEON_ENCODE (FLOAT
, inst
);
19228 if (!check_simd_pred_availability (TRUE
,
19229 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19234 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19235 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19236 inst
.instruction
|= neon_quad (rs
) << 6;
19237 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19238 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19239 inst
.instruction
|= mode
<< 8;
19240 if (flavour
== neon_cvt_flavour_u16_f16
19241 || flavour
== neon_cvt_flavour_s16_f16
)
19242 /* Mask off the original size bits and reencode them. */
19243 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19246 inst
.instruction
|= 0xfc000000;
19248 inst
.instruction
|= 0xf0000000;
19254 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19255 0x100, 0x180, 0x0, 0x080};
19257 NEON_ENCODE (INTEGER
, inst
);
19259 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19261 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19265 if (flavour
!= neon_cvt_flavour_invalid
)
19266 inst
.instruction
|= enctab
[flavour
];
19268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19269 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19270 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19271 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19272 inst
.instruction
|= neon_quad (rs
) << 6;
19273 if (flavour
>= neon_cvt_flavour_s16_f16
19274 && flavour
<= neon_cvt_flavour_f16_u16
)
19275 /* Half precision. */
19276 inst
.instruction
|= 1 << 18;
19278 inst
.instruction
|= 2 << 18;
19280 neon_dp_fixup (&inst
);
19285 /* Half-precision conversions for Advanced SIMD -- neon. */
19288 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19292 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19294 as_bad (_("operand size must match register width"));
19299 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19301 as_bad (_("operand size must match register width"));
19307 if (flavour
== neon_cvt_flavour_bf16_f32
)
19309 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19311 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19312 /* VCVT.bf16.f32. */
19313 inst
.instruction
= 0x11b60640;
19316 /* VCVT.f16.f32. */
19317 inst
.instruction
= 0x3b60600;
19320 /* VCVT.f32.f16. */
19321 inst
.instruction
= 0x3b60700;
19323 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19325 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19326 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19327 neon_dp_fixup (&inst
);
19331 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19332 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19333 do_vfp_nsyn_cvt (rs
, flavour
);
19335 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19340 do_neon_cvtr (void)
19342 do_neon_cvt_1 (neon_cvt_mode_x
);
19348 do_neon_cvt_1 (neon_cvt_mode_z
);
19352 do_neon_cvta (void)
19354 do_neon_cvt_1 (neon_cvt_mode_a
);
19358 do_neon_cvtn (void)
19360 do_neon_cvt_1 (neon_cvt_mode_n
);
19364 do_neon_cvtp (void)
19366 do_neon_cvt_1 (neon_cvt_mode_p
);
19370 do_neon_cvtm (void)
19372 do_neon_cvt_1 (neon_cvt_mode_m
);
19376 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19379 mark_feature_used (&fpu_vfp_ext_armv8
);
19381 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19382 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19383 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19384 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19385 inst
.instruction
|= to
? 0x10000 : 0;
19386 inst
.instruction
|= t
? 0x80 : 0;
19387 inst
.instruction
|= is_double
? 0x100 : 0;
19388 do_vfp_cond_or_thumb ();
19392 do_neon_cvttb_1 (bfd_boolean t
)
19394 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19395 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19399 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19401 int single_to_half
= 0;
19402 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19405 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19407 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19408 && (flavour
== neon_cvt_flavour_u16_f16
19409 || flavour
== neon_cvt_flavour_s16_f16
19410 || flavour
== neon_cvt_flavour_f16_s16
19411 || flavour
== neon_cvt_flavour_f16_u16
19412 || flavour
== neon_cvt_flavour_u32_f32
19413 || flavour
== neon_cvt_flavour_s32_f32
19414 || flavour
== neon_cvt_flavour_f32_s32
19415 || flavour
== neon_cvt_flavour_f32_u32
))
19418 inst
.instruction
= N_MNEM_vcvt
;
19419 set_pred_insn_type (INSIDE_VPT_INSN
);
19420 do_neon_cvt_1 (neon_cvt_mode_z
);
19423 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19424 single_to_half
= 1;
19425 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19427 first_error (BAD_FPU
);
19431 inst
.instruction
= 0xee3f0e01;
19432 inst
.instruction
|= single_to_half
<< 28;
19433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19434 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19435 inst
.instruction
|= t
<< 12;
19436 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19437 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19440 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19443 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19445 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19448 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19450 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19452 /* The VCVTB and VCVTT instructions with D-register operands
19453 don't work for SP only targets. */
19454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19458 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19460 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19462 /* The VCVTB and VCVTT instructions with D-register operands
19463 don't work for SP only targets. */
19464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19468 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19470 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19472 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19474 inst
.instruction
|= (1 << 8);
19475 inst
.instruction
&= ~(1 << 9);
19476 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19483 do_neon_cvtb (void)
19485 do_neon_cvttb_1 (FALSE
);
19490 do_neon_cvtt (void)
19492 do_neon_cvttb_1 (TRUE
);
19496 neon_move_immediate (void)
19498 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19499 struct neon_type_el et
= neon_check_type (2, rs
,
19500 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19501 unsigned immlo
, immhi
= 0, immbits
;
19502 int op
, cmode
, float_p
;
19504 constraint (et
.type
== NT_invtype
,
19505 _("operand size must be specified for immediate VMOV"));
19507 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19508 op
= (inst
.instruction
& (1 << 5)) != 0;
19510 immlo
= inst
.operands
[1].imm
;
19511 if (inst
.operands
[1].regisimm
)
19512 immhi
= inst
.operands
[1].reg
;
19514 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19515 _("immediate has bits set outside the operand size"));
19517 float_p
= inst
.operands
[1].immisfloat
;
19519 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19520 et
.size
, et
.type
)) == FAIL
)
19522 /* Invert relevant bits only. */
19523 neon_invert_size (&immlo
, &immhi
, et
.size
);
19524 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19525 with one or the other; those cases are caught by
19526 neon_cmode_for_move_imm. */
19528 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19529 &op
, et
.size
, et
.type
)) == FAIL
)
19531 first_error (_("immediate out of range"));
19536 inst
.instruction
&= ~(1 << 5);
19537 inst
.instruction
|= op
<< 5;
19539 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19541 inst
.instruction
|= neon_quad (rs
) << 6;
19542 inst
.instruction
|= cmode
<< 8;
19544 neon_write_immbits (immbits
);
19550 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19553 if (inst
.operands
[1].isreg
)
19555 enum neon_shape rs
;
19556 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19557 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19559 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19561 NEON_ENCODE (INTEGER
, inst
);
19562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19566 inst
.instruction
|= neon_quad (rs
) << 6;
19570 NEON_ENCODE (IMMED
, inst
);
19571 neon_move_immediate ();
19574 neon_dp_fixup (&inst
);
19576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19578 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19582 /* Encode instructions of form:
19584 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19585 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19588 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19594 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19595 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19596 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19597 inst
.instruction
|= neon_logbits (size
) << 20;
19599 neon_dp_fixup (&inst
);
19603 do_neon_dyadic_long (void)
19605 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19608 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19611 NEON_ENCODE (INTEGER
, inst
);
19612 /* FIXME: Type checking for lengthening op. */
19613 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19614 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19615 neon_mixed_length (et
, et
.size
);
19617 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19618 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19620 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19621 in an IT block with le/lt conditions. */
19623 if (inst
.cond
== 0xf)
19625 else if (inst
.cond
== 0x10)
19628 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19630 if (inst
.instruction
== N_MNEM_vaddl
)
19632 inst
.instruction
= N_MNEM_vadd
;
19633 do_neon_addsub_if_i ();
19635 else if (inst
.instruction
== N_MNEM_vsubl
)
19637 inst
.instruction
= N_MNEM_vsub
;
19638 do_neon_addsub_if_i ();
19640 else if (inst
.instruction
== N_MNEM_vabdl
)
19642 inst
.instruction
= N_MNEM_vabd
;
19643 do_neon_dyadic_if_su ();
19647 first_error (BAD_FPU
);
19651 do_neon_abal (void)
19653 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19654 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19655 neon_mixed_length (et
, et
.size
);
19659 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19661 if (inst
.operands
[2].isscalar
)
19663 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19664 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19665 NEON_ENCODE (SCALAR
, inst
);
19666 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19670 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19671 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19672 NEON_ENCODE (INTEGER
, inst
);
19673 neon_mixed_length (et
, et
.size
);
19678 do_neon_mac_maybe_scalar_long (void)
19680 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19683 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19684 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19687 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19689 unsigned regno
= NEON_SCALAR_REG (scalar
);
19690 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19694 if (regno
> 7 || elno
> 3)
19697 return ((regno
& 0x7)
19698 | ((elno
& 0x1) << 3)
19699 | (((elno
>> 1) & 0x1) << 5));
19703 if (regno
> 15 || elno
> 1)
19706 return (((regno
& 0x1) << 5)
19707 | ((regno
>> 1) & 0x7)
19708 | ((elno
& 0x1) << 3));
19712 first_error (_("scalar out of range for multiply instruction"));
19717 do_neon_fmac_maybe_scalar_long (int subtype
)
19719 enum neon_shape rs
;
19721 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19722 field (bits[21:20]) has different meaning. For scalar index variant, it's
19723 used to differentiate add and subtract, otherwise it's with fixed value
19727 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19728 be a scalar index register. */
19729 if (inst
.operands
[2].isscalar
)
19731 high8
= 0xfe000000;
19734 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19738 high8
= 0xfc000000;
19741 inst
.instruction
|= (0x1 << 23);
19742 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19746 if (inst
.cond
!= COND_ALWAYS
)
19747 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19748 "behaviour is UNPREDICTABLE"));
19750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19756 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19757 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19758 so we simply pass -1 as size. */
19759 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19760 neon_three_same (quad_p
, 0, size
);
19762 /* Undo neon_dp_fixup. Redo the high eight bits. */
19763 inst
.instruction
&= 0x00ffffff;
19764 inst
.instruction
|= high8
;
19766 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19767 whether the instruction is in Q form and whether Vm is a scalar indexed
19769 if (inst
.operands
[2].isscalar
)
19772 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19773 inst
.instruction
&= 0xffffffd0;
19774 inst
.instruction
|= rm
;
19778 /* Redo Rn as well. */
19779 inst
.instruction
&= 0xfff0ff7f;
19780 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19781 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19786 /* Redo Rn and Rm. */
19787 inst
.instruction
&= 0xfff0ff50;
19788 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19789 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19790 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19791 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19796 do_neon_vfmal (void)
19798 return do_neon_fmac_maybe_scalar_long (0);
19802 do_neon_vfmsl (void)
19804 return do_neon_fmac_maybe_scalar_long (1);
19808 do_neon_dyadic_wide (void)
19810 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19811 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19812 neon_mixed_length (et
, et
.size
);
19816 do_neon_dyadic_narrow (void)
19818 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19819 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19820 /* Operand sign is unimportant, and the U bit is part of the opcode,
19821 so force the operand type to integer. */
19822 et
.type
= NT_integer
;
19823 neon_mixed_length (et
, et
.size
/ 2);
19827 do_neon_mul_sat_scalar_long (void)
19829 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19833 do_neon_vmull (void)
19835 if (inst
.operands
[2].isscalar
)
19836 do_neon_mac_maybe_scalar_long ();
19839 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19840 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19842 if (et
.type
== NT_poly
)
19843 NEON_ENCODE (POLY
, inst
);
19845 NEON_ENCODE (INTEGER
, inst
);
19847 /* For polynomial encoding the U bit must be zero, and the size must
19848 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19849 obviously, as 0b10). */
19852 /* Check we're on the correct architecture. */
19853 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19855 _("Instruction form not available on this architecture.");
19860 neon_mixed_length (et
, et
.size
);
19867 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19868 struct neon_type_el et
= neon_check_type (3, rs
,
19869 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19870 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19872 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19873 _("shift out of range"));
19874 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19875 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19876 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19877 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19878 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19879 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19880 inst
.instruction
|= neon_quad (rs
) << 6;
19881 inst
.instruction
|= imm
<< 8;
19883 neon_dp_fixup (&inst
);
19889 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19892 enum neon_shape rs
;
19893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19894 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19896 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19898 struct neon_type_el et
= neon_check_type (2, rs
,
19899 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19901 unsigned op
= (inst
.instruction
>> 7) & 3;
19902 /* N (width of reversed regions) is encoded as part of the bitmask. We
19903 extract it here to check the elements to be reversed are smaller.
19904 Otherwise we'd get a reserved instruction. */
19905 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19908 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19909 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19910 " operands makes instruction UNPREDICTABLE"));
19912 gas_assert (elsize
!= 0);
19913 constraint (et
.size
>= elsize
,
19914 _("elements must be smaller than reversal region"));
19915 neon_two_same (neon_quad (rs
), 1, et
.size
);
19921 if (inst
.operands
[1].isscalar
)
19923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19925 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19926 struct neon_type_el et
= neon_check_type (2, rs
,
19927 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19928 unsigned sizebits
= et
.size
>> 3;
19929 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19930 int logsize
= neon_logbits (et
.size
);
19931 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19933 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19936 NEON_ENCODE (SCALAR
, inst
);
19937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19939 inst
.instruction
|= LOW4 (dm
);
19940 inst
.instruction
|= HI1 (dm
) << 5;
19941 inst
.instruction
|= neon_quad (rs
) << 6;
19942 inst
.instruction
|= x
<< 17;
19943 inst
.instruction
|= sizebits
<< 16;
19945 neon_dp_fixup (&inst
);
19949 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19950 struct neon_type_el et
= neon_check_type (2, rs
,
19951 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19954 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19963 if (inst
.operands
[1].reg
== REG_SP
)
19964 as_tsktsk (MVE_BAD_SP
);
19965 else if (inst
.operands
[1].reg
== REG_PC
)
19966 as_tsktsk (MVE_BAD_PC
);
19969 /* Duplicate ARM register to lanes of vector. */
19970 NEON_ENCODE (ARMREG
, inst
);
19973 case 8: inst
.instruction
|= 0x400000; break;
19974 case 16: inst
.instruction
|= 0x000020; break;
19975 case 32: inst
.instruction
|= 0x000000; break;
19978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19981 inst
.instruction
|= neon_quad (rs
) << 21;
19982 /* The encoding for this instruction is identical for the ARM and Thumb
19983 variants, except for the condition field. */
19984 do_vfp_cond_or_thumb ();
19989 do_mve_mov (int toQ
)
19991 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19993 if (inst
.cond
> COND_ALWAYS
)
19994 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19996 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20005 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20006 _("Index one must be [2,3] and index two must be two less than"
20008 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20009 _("General purpose registers may not be the same"));
20010 constraint (inst
.operands
[Rt
].reg
== REG_SP
20011 || inst
.operands
[Rt2
].reg
== REG_SP
,
20013 constraint (inst
.operands
[Rt
].reg
== REG_PC
20014 || inst
.operands
[Rt2
].reg
== REG_PC
,
20017 inst
.instruction
= 0xec000f00;
20018 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20019 inst
.instruction
|= !!toQ
<< 20;
20020 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20021 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20022 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20023 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20029 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20032 if (inst
.cond
> COND_ALWAYS
)
20033 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20035 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20037 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20040 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20041 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20049 /* VMOV has particularly many variations. It can be one of:
20050 0. VMOV<c><q> <Qd>, <Qm>
20051 1. VMOV<c><q> <Dd>, <Dm>
20052 (Register operations, which are VORR with Rm = Rn.)
20053 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20054 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20056 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20057 (ARM register to scalar.)
20058 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20059 (Two ARM registers to vector.)
20060 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20061 (Scalar to ARM register.)
20062 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20063 (Vector to two ARM registers.)
20064 8. VMOV.F32 <Sd>, <Sm>
20065 9. VMOV.F64 <Dd>, <Dm>
20066 (VFP register moves.)
20067 10. VMOV.F32 <Sd>, #imm
20068 11. VMOV.F64 <Dd>, #imm
20069 (VFP float immediate load.)
20070 12. VMOV <Rd>, <Sm>
20071 (VFP single to ARM reg.)
20072 13. VMOV <Sd>, <Rm>
20073 (ARM reg to VFP single.)
20074 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20075 (Two ARM regs to two VFP singles.)
20076 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20077 (Two VFP singles to two ARM regs.)
20078 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20079 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20080 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20081 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20083 These cases can be disambiguated using neon_select_shape, except cases 1/9
20084 and 3/11 which depend on the operand type too.
20086 All the encoded bits are hardcoded by this function.
20088 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20089 Cases 5, 7 may be used with VFPv2 and above.
20091 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20092 can specify a type where it doesn't make sense to, and is ignored). */
20097 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20098 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20099 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20100 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20102 struct neon_type_el et
;
20103 const char *ldconst
= 0;
20107 case NS_DD
: /* case 1/9. */
20108 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20109 /* It is not an error here if no type is given. */
20112 /* In MVE we interpret the following instructions as same, so ignoring
20113 the following type (float) and size (64) checks.
20114 a: VMOV<c><q> <Dd>, <Dm>
20115 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20116 if ((et
.type
== NT_float
&& et
.size
== 64)
20117 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20119 do_vfp_nsyn_opcode ("fcpyd");
20122 /* fall through. */
20124 case NS_QQ
: /* case 0/1. */
20126 if (!check_simd_pred_availability (FALSE
,
20127 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20129 /* The architecture manual I have doesn't explicitly state which
20130 value the U bit should have for register->register moves, but
20131 the equivalent VORR instruction has U = 0, so do that. */
20132 inst
.instruction
= 0x0200110;
20133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20136 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20137 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20138 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20139 inst
.instruction
|= neon_quad (rs
) << 6;
20141 neon_dp_fixup (&inst
);
20145 case NS_DI
: /* case 3/11. */
20146 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20148 if (et
.type
== NT_float
&& et
.size
== 64)
20150 /* case 11 (fconstd). */
20151 ldconst
= "fconstd";
20152 goto encode_fconstd
;
20154 /* fall through. */
20156 case NS_QI
: /* case 2/3. */
20157 if (!check_simd_pred_availability (FALSE
,
20158 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20160 inst
.instruction
= 0x0800010;
20161 neon_move_immediate ();
20162 neon_dp_fixup (&inst
);
20165 case NS_SR
: /* case 4. */
20167 unsigned bcdebits
= 0;
20169 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20170 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20172 /* .<size> is optional here, defaulting to .32. */
20173 if (inst
.vectype
.elems
== 0
20174 && inst
.operands
[0].vectype
.type
== NT_invtype
20175 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20177 inst
.vectype
.el
[0].type
= NT_untyped
;
20178 inst
.vectype
.el
[0].size
= 32;
20179 inst
.vectype
.elems
= 1;
20182 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20183 logsize
= neon_logbits (et
.size
);
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20188 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20194 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20198 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20200 if (inst
.operands
[1].reg
== REG_SP
)
20201 as_tsktsk (MVE_BAD_SP
);
20202 else if (inst
.operands
[1].reg
== REG_PC
)
20203 as_tsktsk (MVE_BAD_PC
);
20205 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20207 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20208 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20213 case 8: bcdebits
= 0x8; break;
20214 case 16: bcdebits
= 0x1; break;
20215 case 32: bcdebits
= 0x0; break;
20219 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20221 inst
.instruction
= 0xe000b10;
20222 do_vfp_cond_or_thumb ();
20223 inst
.instruction
|= LOW4 (dn
) << 16;
20224 inst
.instruction
|= HI1 (dn
) << 7;
20225 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20226 inst
.instruction
|= (bcdebits
& 3) << 5;
20227 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20228 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20232 case NS_DRR
: /* case 5 (fmdrr). */
20233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20234 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20237 inst
.instruction
= 0xc400b10;
20238 do_vfp_cond_or_thumb ();
20239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20242 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20245 case NS_RS
: /* case 6. */
20248 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20249 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20250 unsigned abcdebits
= 0;
20252 /* .<dt> is optional here, defaulting to .32. */
20253 if (inst
.vectype
.elems
== 0
20254 && inst
.operands
[0].vectype
.type
== NT_invtype
20255 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20257 inst
.vectype
.el
[0].type
= NT_untyped
;
20258 inst
.vectype
.el
[0].size
= 32;
20259 inst
.vectype
.elems
= 1;
20262 et
= neon_check_type (2, NS_NULL
,
20263 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20264 logsize
= neon_logbits (et
.size
);
20268 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20269 && vfp_or_neon_is_neon (NEON_CHECK_CC
20270 | NEON_CHECK_ARCH
) == FAIL
)
20275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20276 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20280 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20282 if (inst
.operands
[0].reg
== REG_SP
)
20283 as_tsktsk (MVE_BAD_SP
);
20284 else if (inst
.operands
[0].reg
== REG_PC
)
20285 as_tsktsk (MVE_BAD_PC
);
20288 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20290 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20291 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20295 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20296 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20297 case 32: abcdebits
= 0x00; break;
20301 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20302 inst
.instruction
= 0xe100b10;
20303 do_vfp_cond_or_thumb ();
20304 inst
.instruction
|= LOW4 (dn
) << 16;
20305 inst
.instruction
|= HI1 (dn
) << 7;
20306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20307 inst
.instruction
|= (abcdebits
& 3) << 5;
20308 inst
.instruction
|= (abcdebits
>> 2) << 21;
20309 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20313 case NS_RRD
: /* case 7 (fmrrd). */
20314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20318 inst
.instruction
= 0xc500b10;
20319 do_vfp_cond_or_thumb ();
20320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20322 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20323 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20326 case NS_FF
: /* case 8 (fcpys). */
20327 do_vfp_nsyn_opcode ("fcpys");
20331 case NS_FI
: /* case 10 (fconsts). */
20332 ldconst
= "fconsts";
20334 if (!inst
.operands
[1].immisfloat
)
20337 /* Immediate has to fit in 8 bits so float is enough. */
20338 float imm
= (float) inst
.operands
[1].imm
;
20339 memcpy (&new_imm
, &imm
, sizeof (float));
20340 /* But the assembly may have been written to provide an integer
20341 bit pattern that equates to a float, so check that the
20342 conversion has worked. */
20343 if (is_quarter_float (new_imm
))
20345 if (is_quarter_float (inst
.operands
[1].imm
))
20346 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20348 inst
.operands
[1].imm
= new_imm
;
20349 inst
.operands
[1].immisfloat
= 1;
20353 if (is_quarter_float (inst
.operands
[1].imm
))
20355 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20356 do_vfp_nsyn_opcode (ldconst
);
20358 /* ARMv8.2 fp16 vmov.f16 instruction. */
20360 do_scalar_fp16_v82_encode ();
20363 first_error (_("immediate out of range"));
20367 case NS_RF
: /* case 12 (fmrs). */
20368 do_vfp_nsyn_opcode ("fmrs");
20369 /* ARMv8.2 fp16 vmov.f16 instruction. */
20371 do_scalar_fp16_v82_encode ();
20375 case NS_FR
: /* case 13 (fmsr). */
20376 do_vfp_nsyn_opcode ("fmsr");
20377 /* ARMv8.2 fp16 vmov.f16 instruction. */
20379 do_scalar_fp16_v82_encode ();
20389 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20390 (one of which is a list), but we have parsed four. Do some fiddling to
20391 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20393 case NS_RRFF
: /* case 14 (fmrrs). */
20394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20395 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20397 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20398 _("VFP registers must be adjacent"));
20399 inst
.operands
[2].imm
= 2;
20400 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20401 do_vfp_nsyn_opcode ("fmrrs");
20404 case NS_FFRR
: /* case 15 (fmsrr). */
20405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20406 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20408 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20409 _("VFP registers must be adjacent"));
20410 inst
.operands
[1] = inst
.operands
[2];
20411 inst
.operands
[2] = inst
.operands
[3];
20412 inst
.operands
[0].imm
= 2;
20413 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20414 do_vfp_nsyn_opcode ("fmsrr");
20418 /* neon_select_shape has determined that the instruction
20419 shape is wrong and has already set the error message. */
20430 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20431 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20432 && !inst
.operands
[2].present
))
20434 inst
.instruction
= 0;
20437 set_pred_insn_type (INSIDE_IT_INSN
);
20442 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20445 if (inst
.cond
!= COND_ALWAYS
)
20446 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20448 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20449 | N_S16
| N_U16
| N_KEY
);
20451 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20453 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20454 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20456 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20461 do_neon_rshift_round_imm (void)
20463 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20466 enum neon_shape rs
;
20467 struct neon_type_el et
;
20469 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20471 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20472 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20476 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20477 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20479 int imm
= inst
.operands
[2].imm
;
20481 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20484 inst
.operands
[2].present
= 0;
20489 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20490 _("immediate out of range for shift"));
20491 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20496 do_neon_movhf (void)
20498 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20499 constraint (rs
!= NS_HH
, _("invalid suffix"));
20501 if (inst
.cond
!= COND_ALWAYS
)
20505 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20506 " the behaviour is UNPREDICTABLE"));
20510 inst
.error
= BAD_COND
;
20515 do_vfp_sp_monadic ();
20518 inst
.instruction
|= 0xf0000000;
20522 do_neon_movl (void)
20524 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20525 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20526 unsigned sizebits
= et
.size
>> 3;
20527 inst
.instruction
|= sizebits
<< 19;
20528 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20534 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20535 struct neon_type_el et
= neon_check_type (2, rs
,
20536 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20537 NEON_ENCODE (INTEGER
, inst
);
20538 neon_two_same (neon_quad (rs
), 1, et
.size
);
20542 do_neon_zip_uzp (void)
20544 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20545 struct neon_type_el et
= neon_check_type (2, rs
,
20546 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20547 if (rs
== NS_DD
&& et
.size
== 32)
20549 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20550 inst
.instruction
= N_MNEM_vtrn
;
20554 neon_two_same (neon_quad (rs
), 1, et
.size
);
20558 do_neon_sat_abs_neg (void)
20560 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20563 enum neon_shape rs
;
20564 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20565 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20567 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20568 struct neon_type_el et
= neon_check_type (2, rs
,
20569 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20570 neon_two_same (neon_quad (rs
), 1, et
.size
);
20574 do_neon_pair_long (void)
20576 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20577 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20578 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20579 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20580 neon_two_same (neon_quad (rs
), 1, et
.size
);
20584 do_neon_recip_est (void)
20586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20587 struct neon_type_el et
= neon_check_type (2, rs
,
20588 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20589 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20590 neon_two_same (neon_quad (rs
), 1, et
.size
);
20596 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20599 enum neon_shape rs
;
20600 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20601 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20603 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20605 struct neon_type_el et
= neon_check_type (2, rs
,
20606 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20607 neon_two_same (neon_quad (rs
), 1, et
.size
);
20613 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20616 enum neon_shape rs
;
20617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20618 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20620 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20622 struct neon_type_el et
= neon_check_type (2, rs
,
20623 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20624 neon_two_same (neon_quad (rs
), 1, et
.size
);
20630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20631 struct neon_type_el et
= neon_check_type (2, rs
,
20632 N_EQK
| N_INT
, N_8
| N_KEY
);
20633 neon_two_same (neon_quad (rs
), 1, et
.size
);
20639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20640 neon_two_same (neon_quad (rs
), 1, -1);
20644 do_neon_tbl_tbx (void)
20646 unsigned listlenbits
;
20647 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20649 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20651 first_error (_("bad list length for table lookup"));
20655 listlenbits
= inst
.operands
[1].imm
- 1;
20656 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20657 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20658 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20659 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20660 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20661 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20662 inst
.instruction
|= listlenbits
<< 8;
20664 neon_dp_fixup (&inst
);
20668 do_neon_ldm_stm (void)
20670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20671 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20673 /* P, U and L bits are part of bitmask. */
20674 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20675 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20677 if (inst
.operands
[1].issingle
)
20679 do_vfp_nsyn_ldm_stm (is_dbmode
);
20683 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20684 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20686 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20687 _("register list must contain at least 1 and at most 16 "
20690 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20691 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20695 inst
.instruction
|= offsetbits
;
20697 do_vfp_cond_or_thumb ();
20701 do_vfp_nsyn_pop (void)
20704 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20705 return do_vfp_nsyn_opcode ("vldm");
20708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20711 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20712 _("register list must contain at least 1 and at most 16 "
20715 if (inst
.operands
[1].issingle
)
20716 do_vfp_nsyn_opcode ("fldmias");
20718 do_vfp_nsyn_opcode ("fldmiad");
20722 do_vfp_nsyn_push (void)
20725 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20726 return do_vfp_nsyn_opcode ("vstmdb");
20729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20732 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20733 _("register list must contain at least 1 and at most 16 "
20736 if (inst
.operands
[1].issingle
)
20737 do_vfp_nsyn_opcode ("fstmdbs");
20739 do_vfp_nsyn_opcode ("fstmdbd");
20744 do_neon_ldr_str (void)
20746 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20748 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20749 And is UNPREDICTABLE in thumb mode. */
20751 && inst
.operands
[1].reg
== REG_PC
20752 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20755 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20756 else if (warn_on_deprecated
)
20757 as_tsktsk (_("Use of PC here is deprecated"));
20760 if (inst
.operands
[0].issingle
)
20763 do_vfp_nsyn_opcode ("flds");
20765 do_vfp_nsyn_opcode ("fsts");
20767 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20768 if (inst
.vectype
.el
[0].size
== 16)
20769 do_scalar_fp16_v82_encode ();
20774 do_vfp_nsyn_opcode ("fldd");
20776 do_vfp_nsyn_opcode ("fstd");
20781 do_t_vldr_vstr_sysreg (void)
20783 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20784 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20786 /* Use of PC is UNPREDICTABLE. */
20787 if (inst
.operands
[1].reg
== REG_PC
)
20788 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20790 if (inst
.operands
[1].immisreg
)
20791 inst
.error
= _("instruction does not accept register index");
20793 if (!inst
.operands
[1].isreg
)
20794 inst
.error
= _("instruction does not accept PC-relative addressing");
20796 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20797 inst
.error
= _("immediate value out of range");
20799 inst
.instruction
= 0xec000f80;
20801 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20802 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20803 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20804 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20808 do_vldr_vstr (void)
20810 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20812 /* VLDR/VSTR (System Register). */
20815 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20816 as_bad (_("Instruction not permitted on this architecture"));
20818 do_t_vldr_vstr_sysreg ();
20823 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20824 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20825 as_bad (_("Instruction not permitted on this architecture"));
20826 do_neon_ldr_str ();
20830 /* "interleave" version also handles non-interleaving register VLD1/VST1
20834 do_neon_ld_st_interleave (void)
20836 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20837 N_8
| N_16
| N_32
| N_64
);
20838 unsigned alignbits
= 0;
20840 /* The bits in this table go:
20841 0: register stride of one (0) or two (1)
20842 1,2: register list length, minus one (1, 2, 3, 4).
20843 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20844 We use -1 for invalid entries. */
20845 const int typetable
[] =
20847 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20848 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20849 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20850 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20854 if (et
.type
== NT_invtype
)
20857 if (inst
.operands
[1].immisalign
)
20858 switch (inst
.operands
[1].imm
>> 8)
20860 case 64: alignbits
= 1; break;
20862 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20863 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20864 goto bad_alignment
;
20868 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20869 goto bad_alignment
;
20874 first_error (_("bad alignment"));
20878 inst
.instruction
|= alignbits
<< 4;
20879 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20881 /* Bits [4:6] of the immediate in a list specifier encode register stride
20882 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20883 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20884 up the right value for "type" in a table based on this value and the given
20885 list style, then stick it back. */
20886 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20887 | (((inst
.instruction
>> 8) & 3) << 3);
20889 typebits
= typetable
[idx
];
20891 constraint (typebits
== -1, _("bad list type for instruction"));
20892 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20895 inst
.instruction
&= ~0xf00;
20896 inst
.instruction
|= typebits
<< 8;
20899 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20900 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20901 otherwise. The variable arguments are a list of pairs of legal (size, align)
20902 values, terminated with -1. */
20905 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20908 int result
= FAIL
, thissize
, thisalign
;
20910 if (!inst
.operands
[1].immisalign
)
20916 va_start (ap
, do_alignment
);
20920 thissize
= va_arg (ap
, int);
20921 if (thissize
== -1)
20923 thisalign
= va_arg (ap
, int);
20925 if (size
== thissize
&& align
== thisalign
)
20928 while (result
!= SUCCESS
);
20932 if (result
== SUCCESS
)
20935 first_error (_("unsupported alignment for instruction"));
20941 do_neon_ld_st_lane (void)
20943 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20944 int align_good
, do_alignment
= 0;
20945 int logsize
= neon_logbits (et
.size
);
20946 int align
= inst
.operands
[1].imm
>> 8;
20947 int n
= (inst
.instruction
>> 8) & 3;
20948 int max_el
= 64 / et
.size
;
20950 if (et
.type
== NT_invtype
)
20953 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20954 _("bad list length"));
20955 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20956 _("scalar index out of range"));
20957 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20959 _("stride of 2 unavailable when element size is 8"));
20963 case 0: /* VLD1 / VST1. */
20964 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20966 if (align_good
== FAIL
)
20970 unsigned alignbits
= 0;
20973 case 16: alignbits
= 0x1; break;
20974 case 32: alignbits
= 0x3; break;
20977 inst
.instruction
|= alignbits
<< 4;
20981 case 1: /* VLD2 / VST2. */
20982 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20983 16, 32, 32, 64, -1);
20984 if (align_good
== FAIL
)
20987 inst
.instruction
|= 1 << 4;
20990 case 2: /* VLD3 / VST3. */
20991 constraint (inst
.operands
[1].immisalign
,
20992 _("can't use alignment with this instruction"));
20995 case 3: /* VLD4 / VST4. */
20996 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20997 16, 64, 32, 64, 32, 128, -1);
20998 if (align_good
== FAIL
)
21002 unsigned alignbits
= 0;
21005 case 8: alignbits
= 0x1; break;
21006 case 16: alignbits
= 0x1; break;
21007 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21010 inst
.instruction
|= alignbits
<< 4;
21017 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21018 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21019 inst
.instruction
|= 1 << (4 + logsize
);
21021 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21022 inst
.instruction
|= logsize
<< 10;
21025 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21028 do_neon_ld_dup (void)
21030 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21031 int align_good
, do_alignment
= 0;
21033 if (et
.type
== NT_invtype
)
21036 switch ((inst
.instruction
>> 8) & 3)
21038 case 0: /* VLD1. */
21039 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21040 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21041 &do_alignment
, 16, 16, 32, 32, -1);
21042 if (align_good
== FAIL
)
21044 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21047 case 2: inst
.instruction
|= 1 << 5; break;
21048 default: first_error (_("bad list length")); return;
21050 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21053 case 1: /* VLD2. */
21054 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21055 &do_alignment
, 8, 16, 16, 32, 32, 64,
21057 if (align_good
== FAIL
)
21059 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21060 _("bad list length"));
21061 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21062 inst
.instruction
|= 1 << 5;
21063 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21066 case 2: /* VLD3. */
21067 constraint (inst
.operands
[1].immisalign
,
21068 _("can't use alignment with this instruction"));
21069 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21070 _("bad list length"));
21071 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21072 inst
.instruction
|= 1 << 5;
21073 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21076 case 3: /* VLD4. */
21078 int align
= inst
.operands
[1].imm
>> 8;
21079 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21080 16, 64, 32, 64, 32, 128, -1);
21081 if (align_good
== FAIL
)
21083 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21084 _("bad list length"));
21085 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21086 inst
.instruction
|= 1 << 5;
21087 if (et
.size
== 32 && align
== 128)
21088 inst
.instruction
|= 0x3 << 6;
21090 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21097 inst
.instruction
|= do_alignment
<< 4;
21100 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21101 apart from bits [11:4]. */
21104 do_neon_ldx_stx (void)
21106 if (inst
.operands
[1].isreg
)
21107 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21109 switch (NEON_LANE (inst
.operands
[0].imm
))
21111 case NEON_INTERLEAVE_LANES
:
21112 NEON_ENCODE (INTERLV
, inst
);
21113 do_neon_ld_st_interleave ();
21116 case NEON_ALL_LANES
:
21117 NEON_ENCODE (DUP
, inst
);
21118 if (inst
.instruction
== N_INV
)
21120 first_error ("only loads support such operands");
21127 NEON_ENCODE (LANE
, inst
);
21128 do_neon_ld_st_lane ();
21131 /* L bit comes from bit mask. */
21132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21136 if (inst
.operands
[1].postind
)
21138 int postreg
= inst
.operands
[1].imm
& 0xf;
21139 constraint (!inst
.operands
[1].immisreg
,
21140 _("post-index must be a register"));
21141 constraint (postreg
== 0xd || postreg
== 0xf,
21142 _("bad register for post-index"));
21143 inst
.instruction
|= postreg
;
21147 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21148 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21149 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21152 if (inst
.operands
[1].writeback
)
21154 inst
.instruction
|= 0xd;
21157 inst
.instruction
|= 0xf;
21161 inst
.instruction
|= 0xf9000000;
21163 inst
.instruction
|= 0xf4000000;
21168 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21170 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21171 D register operands. */
21172 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21173 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21176 NEON_ENCODE (FPV8
, inst
);
21178 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21180 do_vfp_sp_dyadic ();
21182 /* ARMv8.2 fp16 instruction. */
21184 do_scalar_fp16_v82_encode ();
21187 do_vfp_dp_rd_rn_rm ();
21190 inst
.instruction
|= 0x100;
21192 inst
.instruction
|= 0xf0000000;
21198 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21200 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21201 first_error (_("invalid instruction shape"));
21207 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21208 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21210 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21213 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21216 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21220 do_vrint_1 (enum neon_cvt_mode mode
)
21222 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21223 struct neon_type_el et
;
21228 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21229 D register operands. */
21230 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21234 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21236 if (et
.type
!= NT_invtype
)
21238 /* VFP encodings. */
21239 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21240 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21241 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21243 NEON_ENCODE (FPV8
, inst
);
21244 if (rs
== NS_FF
|| rs
== NS_HH
)
21245 do_vfp_sp_monadic ();
21247 do_vfp_dp_rd_rm ();
21251 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21252 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21253 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21254 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21255 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21256 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21257 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21261 inst
.instruction
|= (rs
== NS_DD
) << 8;
21262 do_vfp_cond_or_thumb ();
21264 /* ARMv8.2 fp16 vrint instruction. */
21266 do_scalar_fp16_v82_encode ();
21270 /* Neon encodings (or something broken...). */
21272 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21274 if (et
.type
== NT_invtype
)
21277 if (!check_simd_pred_availability (TRUE
,
21278 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21281 NEON_ENCODE (FLOAT
, inst
);
21283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21287 inst
.instruction
|= neon_quad (rs
) << 6;
21288 /* Mask off the original size bits and reencode them. */
21289 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21290 | neon_logbits (et
.size
) << 18);
21294 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21295 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21296 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21297 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21298 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21299 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21300 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21305 inst
.instruction
|= 0xfc000000;
21307 inst
.instruction
|= 0xf0000000;
21314 do_vrint_1 (neon_cvt_mode_x
);
21320 do_vrint_1 (neon_cvt_mode_z
);
21326 do_vrint_1 (neon_cvt_mode_r
);
21332 do_vrint_1 (neon_cvt_mode_a
);
21338 do_vrint_1 (neon_cvt_mode_n
);
21344 do_vrint_1 (neon_cvt_mode_p
);
21350 do_vrint_1 (neon_cvt_mode_m
);
21354 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21356 unsigned regno
= NEON_SCALAR_REG (opnd
);
21357 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21359 if (elsize
== 16 && elno
< 2 && regno
< 16)
21360 return regno
| (elno
<< 4);
21361 else if (elsize
== 32 && elno
== 0)
21364 first_error (_("scalar out of range"));
21371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21372 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21373 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21374 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21375 _("expression too complex"));
21376 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21377 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21378 _("immediate out of range"));
21381 if (!check_simd_pred_availability (TRUE
,
21382 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21385 if (inst
.operands
[2].isscalar
)
21387 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21388 first_error (_("invalid instruction shape"));
21389 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21390 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21391 N_KEY
| N_F16
| N_F32
).size
;
21392 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21394 inst
.instruction
= 0xfe000800;
21395 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21396 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21397 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21398 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21399 inst
.instruction
|= LOW4 (m
);
21400 inst
.instruction
|= HI1 (m
) << 5;
21401 inst
.instruction
|= neon_quad (rs
) << 6;
21402 inst
.instruction
|= rot
<< 20;
21403 inst
.instruction
|= (size
== 32) << 23;
21407 enum neon_shape rs
;
21408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21409 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21411 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21413 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21414 N_KEY
| N_F16
| N_F32
).size
;
21415 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21416 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21417 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21418 as_tsktsk (BAD_MVE_SRCDEST
);
21420 neon_three_same (neon_quad (rs
), 0, -1);
21421 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21422 inst
.instruction
|= 0xfc200800;
21423 inst
.instruction
|= rot
<< 23;
21424 inst
.instruction
|= (size
== 32) << 20;
21431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21432 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21433 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21434 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21435 _("expression too complex"));
21437 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21438 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21439 enum neon_shape rs
;
21440 struct neon_type_el et
;
21441 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21443 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21444 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21448 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21449 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21451 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21452 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21453 "operand makes instruction UNPREDICTABLE"));
21456 if (et
.type
== NT_invtype
)
21459 if (!check_simd_pred_availability (et
.type
== NT_float
,
21460 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21463 if (et
.type
== NT_float
)
21465 neon_three_same (neon_quad (rs
), 0, -1);
21466 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21467 inst
.instruction
|= 0xfc800800;
21468 inst
.instruction
|= (rot
== 270) << 24;
21469 inst
.instruction
|= (et
.size
== 32) << 20;
21473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21474 inst
.instruction
= 0xfe000f00;
21475 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21476 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21478 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21479 inst
.instruction
|= (rot
== 270) << 12;
21480 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21481 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21482 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21487 /* Dot Product instructions encoding support. */
21490 do_neon_dotproduct (int unsigned_p
)
21492 enum neon_shape rs
;
21493 unsigned scalar_oprd2
= 0;
21496 if (inst
.cond
!= COND_ALWAYS
)
21497 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21498 "is UNPREDICTABLE"));
21500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21503 /* Dot Product instructions are in three-same D/Q register format or the third
21504 operand can be a scalar index register. */
21505 if (inst
.operands
[2].isscalar
)
21507 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21508 high8
= 0xfe000000;
21509 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21513 high8
= 0xfc000000;
21514 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21518 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21520 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21522 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21523 Product instruction, so we pass 0 as the "ubit" parameter. And the
21524 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21525 neon_three_same (neon_quad (rs
), 0, 32);
21527 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21528 different NEON three-same encoding. */
21529 inst
.instruction
&= 0x00ffffff;
21530 inst
.instruction
|= high8
;
21531 /* Encode 'U' bit which indicates signedness. */
21532 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21533 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21534 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21535 the instruction encoding. */
21536 if (inst
.operands
[2].isscalar
)
21538 inst
.instruction
&= 0xffffffd0;
21539 inst
.instruction
|= LOW4 (scalar_oprd2
);
21540 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21544 /* Dot Product instructions for signed integer. */
21547 do_neon_dotproduct_s (void)
21549 return do_neon_dotproduct (0);
21552 /* Dot Product instructions for unsigned integer. */
21555 do_neon_dotproduct_u (void)
21557 return do_neon_dotproduct (1);
21563 enum neon_shape rs
;
21564 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21565 if (inst
.operands
[2].isscalar
)
21567 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21568 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21570 inst
.instruction
|= (1 << 25);
21571 int index
= inst
.operands
[2].reg
& 0xf;
21572 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21573 inst
.operands
[2].reg
>>= 4;
21574 constraint (!(inst
.operands
[2].reg
< 16),
21575 _("indexed register must be less than 16"));
21576 neon_three_args (rs
== NS_QQS
);
21577 inst
.instruction
|= (index
<< 5);
21581 inst
.instruction
|= (1 << 21);
21582 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21583 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21584 neon_three_args (rs
== NS_QQQ
);
21591 enum neon_shape rs
;
21592 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21593 if (inst
.operands
[2].isscalar
)
21595 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21596 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21598 inst
.instruction
|= (1 << 25);
21599 int index
= inst
.operands
[2].reg
& 0xf;
21600 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21601 inst
.operands
[2].reg
>>= 4;
21602 constraint (!(inst
.operands
[2].reg
< 16),
21603 _("indexed register must be less than 16"));
21604 neon_three_args (rs
== NS_QQS
);
21605 inst
.instruction
|= (index
<< 5);
21612 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21613 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21615 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21617 neon_three_args (1);
21624 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21625 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21627 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21629 neon_three_args (1);
21634 check_cde_operand (size_t index
, int is_dual
)
21636 unsigned Rx
= inst
.operands
[index
].reg
;
21637 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21638 if (is_dual
== 0 && thumb_mode
)
21640 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21641 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21643 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21644 _("Register must be an even register between r0-r10."));
21648 cde_coproc_enabled (unsigned coproc
)
21652 case 0: return mark_feature_used (&arm_ext_cde0
);
21653 case 1: return mark_feature_used (&arm_ext_cde1
);
21654 case 2: return mark_feature_used (&arm_ext_cde2
);
21655 case 3: return mark_feature_used (&arm_ext_cde3
);
21656 case 4: return mark_feature_used (&arm_ext_cde4
);
21657 case 5: return mark_feature_used (&arm_ext_cde5
);
21658 case 6: return mark_feature_used (&arm_ext_cde6
);
21659 case 7: return mark_feature_used (&arm_ext_cde7
);
21660 default: return FALSE
;
21664 #define cde_coproc_pos 8
21666 cde_handle_coproc (void)
21668 unsigned coproc
= inst
.operands
[0].reg
;
21669 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21670 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21671 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21673 #undef cde_coproc_pos
21676 cxn_handle_predication (bfd_boolean is_accum
)
21678 if (is_accum
&& conditional_insn ())
21679 set_pred_insn_type (INSIDE_IT_INSN
);
21680 else if (conditional_insn ())
21681 /* conditional_insn essentially checks for a suffix, not whether the
21682 instruction is inside an IT block or not.
21683 The non-accumulator versions should not have suffixes. */
21684 inst
.error
= BAD_SYNTAX
;
21686 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21690 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21693 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21697 Rd
= inst
.operands
[1].reg
;
21698 check_cde_operand (1, is_dual
);
21702 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21703 _("cx1d requires consecutive destination registers."));
21704 imm
= inst
.operands
[3].imm
;
21706 else if (is_dual
== 0)
21707 imm
= inst
.operands
[2].imm
;
21711 inst
.instruction
|= Rd
<< 12;
21712 inst
.instruction
|= (imm
& 0x1F80) << 9;
21713 inst
.instruction
|= (imm
& 0x0040) << 1;
21714 inst
.instruction
|= (imm
& 0x003f);
21716 cde_handle_coproc ();
21717 cxn_handle_predication (is_accum
);
21721 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21724 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21726 unsigned imm
, Rd
, Rn
;
21728 Rd
= inst
.operands
[1].reg
;
21732 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21733 _("cx2d requires consecutive destination registers."));
21734 imm
= inst
.operands
[4].imm
;
21735 Rn
= inst
.operands
[3].reg
;
21737 else if (is_dual
== 0)
21739 imm
= inst
.operands
[3].imm
;
21740 Rn
= inst
.operands
[2].reg
;
21745 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21746 check_cde_operand (1, is_dual
);
21748 inst
.instruction
|= Rd
<< 12;
21749 inst
.instruction
|= Rn
<< 16;
21751 inst
.instruction
|= (imm
& 0x0380) << 13;
21752 inst
.instruction
|= (imm
& 0x0040) << 1;
21753 inst
.instruction
|= (imm
& 0x003f);
21755 cde_handle_coproc ();
21756 cxn_handle_predication (is_accum
);
21760 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21763 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21765 unsigned imm
, Rd
, Rn
, Rm
;
21767 Rd
= inst
.operands
[1].reg
;
21771 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21772 _("cx3d requires consecutive destination registers."));
21773 imm
= inst
.operands
[5].imm
;
21774 Rn
= inst
.operands
[3].reg
;
21775 Rm
= inst
.operands
[4].reg
;
21777 else if (is_dual
== 0)
21779 imm
= inst
.operands
[4].imm
;
21780 Rn
= inst
.operands
[2].reg
;
21781 Rm
= inst
.operands
[3].reg
;
21786 check_cde_operand (1, is_dual
);
21787 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21788 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21790 inst
.instruction
|= Rd
;
21791 inst
.instruction
|= Rn
<< 16;
21792 inst
.instruction
|= Rm
<< 12;
21794 inst
.instruction
|= (imm
& 0x0038) << 17;
21795 inst
.instruction
|= (imm
& 0x0004) << 5;
21796 inst
.instruction
|= (imm
& 0x0003) << 4;
21798 cde_handle_coproc ();
21799 cxn_handle_predication (is_accum
);
21805 return do_custom_instruction_1 (0, 0);
21811 return do_custom_instruction_1 (0, 1);
21817 return do_custom_instruction_1 (1, 0);
21823 return do_custom_instruction_1 (1, 1);
21829 return do_custom_instruction_2 (0, 0);
21835 return do_custom_instruction_2 (0, 1);
21841 return do_custom_instruction_2 (1, 0);
21847 return do_custom_instruction_2 (1, 1);
21853 return do_custom_instruction_3 (0, 0);
21859 return do_custom_instruction_3 (0, 1);
21865 return do_custom_instruction_3 (1, 0);
21871 return do_custom_instruction_3 (1, 1);
21875 vcx_assign_vec_d (unsigned regnum
)
21877 inst
.instruction
|= HI4 (regnum
) << 12;
21878 inst
.instruction
|= LOW1 (regnum
) << 22;
21882 vcx_assign_vec_m (unsigned regnum
)
21884 inst
.instruction
|= HI4 (regnum
);
21885 inst
.instruction
|= LOW1 (regnum
) << 5;
21889 vcx_assign_vec_n (unsigned regnum
)
21891 inst
.instruction
|= HI4 (regnum
) << 16;
21892 inst
.instruction
|= LOW1 (regnum
) << 7;
21895 enum vcx_reg_type
{
21901 static enum vcx_reg_type
21902 vcx_get_reg_type (enum neon_shape ns
)
21904 gas_assert (ns
== NS_PQI
21912 || ns
== NS_PFFFI
);
21913 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21915 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21920 #define vcx_size_pos 24
21921 #define vcx_vec_pos 6
21923 vcx_handle_shape (enum vcx_reg_type reg_type
)
21926 if (reg_type
== q_reg
)
21927 inst
.instruction
|= 1 << vcx_vec_pos
;
21928 else if (reg_type
== d_reg
)
21929 inst
.instruction
|= 1 << vcx_size_pos
;
21933 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21934 bits (or equivalent for N and M registers).
21935 Similarly the D registers are encoded as N in D:Vd bits.
21936 While the S registers are encoded as N in the Vd:D bits.
21938 Taking into account the maximum values of these registers we can see a
21939 nicer pattern for calculation:
21940 Q -> 7, D -> 15, S -> 31
21942 If we say that everything is encoded in the Vd:D bits, then we can say
21943 that Q is encoded as 4*N, and D is encoded as 2*N.
21944 This way the bits will end up the same, and calculation is simpler.
21945 (calculation is now:
21946 1. Multiply by a number determined by the register letter.
21947 2. Encode resulting number in Vd:D bits.)
21949 This is made a little more complicated by automatic handling of 'Q'
21950 registers elsewhere, which means the register number is already 2*N where
21951 N is the number the user wrote after the register letter.
21956 #undef vcx_size_pos
21959 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21961 if (reg_type
== q_reg
)
21963 gas_assert (R
% 2 == 0);
21964 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21966 else if (reg_type
== d_reg
)
21967 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21969 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21972 static void (*vcx_assign_vec
[3]) (unsigned) = {
21979 vcx_handle_register_arguments (unsigned num_registers
,
21980 enum vcx_reg_type reg_type
)
21983 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21984 for (i
= 0; i
< num_registers
; i
++)
21986 R
= inst
.operands
[i
+1].reg
;
21987 vcx_ensure_register_in_range (R
, reg_type
);
21988 if (num_registers
== 3 && i
> 0)
21991 vcx_assign_vec
[1] (R
* reg_mult
);
21993 vcx_assign_vec
[2] (R
* reg_mult
);
21996 vcx_assign_vec
[i
](R
* reg_mult
);
22001 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22003 if (reg_type
== q_reg
)
22004 if (inst
.cond
> COND_ALWAYS
)
22005 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22007 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22008 else if (inst
.cond
== COND_ALWAYS
)
22009 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22011 inst
.error
= BAD_NOT_IT
;
22015 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22017 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22018 cde_handle_coproc ();
22019 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22020 vcx_handle_register_arguments (num_args
, reg_type
);
22021 vcx_handle_insn_block (reg_type
);
22022 if (reg_type
== q_reg
)
22023 constraint (!mark_feature_used (&mve_ext
),
22024 _("vcx instructions with Q registers require MVE"));
22026 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22027 && mark_feature_used (&armv8m_fp
))
22028 && !mark_feature_used (&mve_ext
),
22029 _("vcx instructions with S or D registers require either MVE"
22030 " or Armv8-M floating point etension."));
22036 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22037 vcx_handle_common_checks (1, rs
);
22039 unsigned imm
= inst
.operands
[2].imm
;
22040 inst
.instruction
|= (imm
& 0x03f);
22041 inst
.instruction
|= (imm
& 0x040) << 1;
22042 inst
.instruction
|= (imm
& 0x780) << 9;
22044 constraint (imm
>= 2048,
22045 _("vcx1 with S or D registers takes immediate within 0-2047"));
22046 inst
.instruction
|= (imm
& 0x800) << 13;
22052 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22053 vcx_handle_common_checks (2, rs
);
22055 unsigned imm
= inst
.operands
[3].imm
;
22056 inst
.instruction
|= (imm
& 0x01) << 4;
22057 inst
.instruction
|= (imm
& 0x02) << 6;
22058 inst
.instruction
|= (imm
& 0x3c) << 14;
22060 constraint (imm
>= 64,
22061 _("vcx2 with S or D registers takes immediate within 0-63"));
22062 inst
.instruction
|= (imm
& 0x40) << 18;
22068 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22069 vcx_handle_common_checks (3, rs
);
22071 unsigned imm
= inst
.operands
[4].imm
;
22072 inst
.instruction
|= (imm
& 0x1) << 4;
22073 inst
.instruction
|= (imm
& 0x6) << 19;
22074 if (rs
!= NS_PQQQI
)
22075 constraint (imm
>= 8,
22076 _("vcx2 with S or D registers takes immediate within 0-7"));
22077 inst
.instruction
|= (imm
& 0x8) << 21;
22080 /* Crypto v1 instructions. */
22082 do_crypto_2op_1 (unsigned elttype
, int op
)
22084 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22086 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22092 NEON_ENCODE (INTEGER
, inst
);
22093 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22096 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22098 inst
.instruction
|= op
<< 6;
22101 inst
.instruction
|= 0xfc000000;
22103 inst
.instruction
|= 0xf0000000;
22107 do_crypto_3op_1 (int u
, int op
)
22109 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22111 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22112 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22117 NEON_ENCODE (INTEGER
, inst
);
22118 neon_three_same (1, u
, 8 << op
);
22124 do_crypto_2op_1 (N_8
, 0);
22130 do_crypto_2op_1 (N_8
, 1);
22136 do_crypto_2op_1 (N_8
, 2);
22142 do_crypto_2op_1 (N_8
, 3);
22148 do_crypto_3op_1 (0, 0);
22154 do_crypto_3op_1 (0, 1);
22160 do_crypto_3op_1 (0, 2);
22166 do_crypto_3op_1 (0, 3);
22172 do_crypto_3op_1 (1, 0);
22178 do_crypto_3op_1 (1, 1);
22182 do_sha256su1 (void)
22184 do_crypto_3op_1 (1, 2);
22190 do_crypto_2op_1 (N_32
, -1);
22196 do_crypto_2op_1 (N_32
, 0);
22200 do_sha256su0 (void)
22202 do_crypto_2op_1 (N_32
, 1);
22206 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22208 unsigned int Rd
= inst
.operands
[0].reg
;
22209 unsigned int Rn
= inst
.operands
[1].reg
;
22210 unsigned int Rm
= inst
.operands
[2].reg
;
22212 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22213 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22214 inst
.instruction
|= LOW4 (Rn
) << 16;
22215 inst
.instruction
|= LOW4 (Rm
);
22216 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22217 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22219 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22220 as_warn (UNPRED_REG ("r15"));
22262 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22264 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22265 do_vfp_sp_dp_cvt ();
22266 do_vfp_cond_or_thumb ();
22272 enum neon_shape rs
;
22273 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22274 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22275 if (inst
.operands
[2].isscalar
)
22277 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22278 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22280 inst
.instruction
|= (1 << 25);
22281 int index
= inst
.operands
[2].reg
& 0xf;
22282 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22283 inst
.operands
[2].reg
>>= 4;
22284 constraint (!(inst
.operands
[2].reg
< 16),
22285 _("indexed register must be less than 16"));
22286 neon_three_args (rs
== NS_QQS
);
22287 inst
.instruction
|= (index
<< 5);
22291 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22292 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22293 neon_three_args (rs
== NS_QQQ
);
22300 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22301 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22303 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22304 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22306 neon_three_args (1);
22310 /* Overall per-instruction processing. */
22312 /* We need to be able to fix up arbitrary expressions in some statements.
22313 This is so that we can handle symbols that are an arbitrary distance from
22314 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22315 which returns part of an address in a form which will be valid for
22316 a data instruction. We do this by pushing the expression into a symbol
22317 in the expr_section, and creating a fix for that. */
22320 fix_new_arm (fragS
* frag
,
22334 /* Create an absolute valued symbol, so we have something to
22335 refer to in the object file. Unfortunately for us, gas's
22336 generic expression parsing will already have folded out
22337 any use of .set foo/.type foo %function that may have
22338 been used to set type information of the target location,
22339 that's being specified symbolically. We have to presume
22340 the user knows what they are doing. */
22344 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22346 symbol
= symbol_find_or_make (name
);
22347 S_SET_SEGMENT (symbol
, absolute_section
);
22348 symbol_set_frag (symbol
, &zero_address_frag
);
22349 S_SET_VALUE (symbol
, exp
->X_add_number
);
22350 exp
->X_op
= O_symbol
;
22351 exp
->X_add_symbol
= symbol
;
22352 exp
->X_add_number
= 0;
22358 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22359 (enum bfd_reloc_code_real
) reloc
);
22363 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22364 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22368 /* Mark whether the fix is to a THUMB instruction, or an ARM
22370 new_fix
->tc_fix_data
= thumb_mode
;
22373 /* Create a frg for an instruction requiring relaxation. */
22375 output_relax_insn (void)
22381 /* The size of the instruction is unknown, so tie the debug info to the
22382 start of the instruction. */
22383 dwarf2_emit_insn (0);
22385 switch (inst
.relocs
[0].exp
.X_op
)
22388 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22389 offset
= inst
.relocs
[0].exp
.X_add_number
;
22393 offset
= inst
.relocs
[0].exp
.X_add_number
;
22396 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22400 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22401 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22402 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22405 /* Write a 32-bit thumb instruction to buf. */
22407 put_thumb32_insn (char * buf
, unsigned long insn
)
22409 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22410 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22414 output_inst (const char * str
)
22420 as_bad ("%s -- `%s'", inst
.error
, str
);
22425 output_relax_insn ();
22428 if (inst
.size
== 0)
22431 to
= frag_more (inst
.size
);
22432 /* PR 9814: Record the thumb mode into the current frag so that we know
22433 what type of NOP padding to use, if necessary. We override any previous
22434 setting so that if the mode has changed then the NOPS that we use will
22435 match the encoding of the last instruction in the frag. */
22436 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22438 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22440 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22441 put_thumb32_insn (to
, inst
.instruction
);
22443 else if (inst
.size
> INSN_SIZE
)
22445 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22446 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22447 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22450 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22453 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22455 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22456 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22457 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22458 inst
.relocs
[r
].type
);
22461 dwarf2_emit_insn (inst
.size
);
22465 output_it_inst (int cond
, int mask
, char * to
)
22467 unsigned long instruction
= 0xbf00;
22470 instruction
|= mask
;
22471 instruction
|= cond
<< 4;
22475 to
= frag_more (2);
22477 dwarf2_emit_insn (2);
22481 md_number_to_chars (to
, instruction
, 2);
22486 /* Tag values used in struct asm_opcode's tag field. */
22489 OT_unconditional
, /* Instruction cannot be conditionalized.
22490 The ARM condition field is still 0xE. */
22491 OT_unconditionalF
, /* Instruction cannot be conditionalized
22492 and carries 0xF in its ARM condition field. */
22493 OT_csuffix
, /* Instruction takes a conditional suffix. */
22494 OT_csuffixF
, /* Some forms of the instruction take a scalar
22495 conditional suffix, others place 0xF where the
22496 condition field would be, others take a vector
22497 conditional suffix. */
22498 OT_cinfix3
, /* Instruction takes a conditional infix,
22499 beginning at character index 3. (In
22500 unified mode, it becomes a suffix.) */
22501 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22502 tsts, cmps, cmns, and teqs. */
22503 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22504 character index 3, even in unified mode. Used for
22505 legacy instructions where suffix and infix forms
22506 may be ambiguous. */
22507 OT_csuf_or_in3
, /* Instruction takes either a conditional
22508 suffix or an infix at character index 3. */
22509 OT_odd_infix_unc
, /* This is the unconditional variant of an
22510 instruction that takes a conditional infix
22511 at an unusual position. In unified mode,
22512 this variant will accept a suffix. */
22513 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22514 are the conditional variants of instructions that
22515 take conditional infixes in unusual positions.
22516 The infix appears at character index
22517 (tag - OT_odd_infix_0). These are not accepted
22518 in unified mode. */
22521 /* Subroutine of md_assemble, responsible for looking up the primary
22522 opcode from the mnemonic the user wrote. STR points to the
22523 beginning of the mnemonic.
22525 This is not simply a hash table lookup, because of conditional
22526 variants. Most instructions have conditional variants, which are
22527 expressed with a _conditional affix_ to the mnemonic. If we were
22528 to encode each conditional variant as a literal string in the opcode
22529 table, it would have approximately 20,000 entries.
22531 Most mnemonics take this affix as a suffix, and in unified syntax,
22532 'most' is upgraded to 'all'. However, in the divided syntax, some
22533 instructions take the affix as an infix, notably the s-variants of
22534 the arithmetic instructions. Of those instructions, all but six
22535 have the infix appear after the third character of the mnemonic.
22537 Accordingly, the algorithm for looking up primary opcodes given
22540 1. Look up the identifier in the opcode table.
22541 If we find a match, go to step U.
22543 2. Look up the last two characters of the identifier in the
22544 conditions table. If we find a match, look up the first N-2
22545 characters of the identifier in the opcode table. If we
22546 find a match, go to step CE.
22548 3. Look up the fourth and fifth characters of the identifier in
22549 the conditions table. If we find a match, extract those
22550 characters from the identifier, and look up the remaining
22551 characters in the opcode table. If we find a match, go
22556 U. Examine the tag field of the opcode structure, in case this is
22557 one of the six instructions with its conditional infix in an
22558 unusual place. If it is, the tag tells us where to find the
22559 infix; look it up in the conditions table and set inst.cond
22560 accordingly. Otherwise, this is an unconditional instruction.
22561 Again set inst.cond accordingly. Return the opcode structure.
22563 CE. Examine the tag field to make sure this is an instruction that
22564 should receive a conditional suffix. If it is not, fail.
22565 Otherwise, set inst.cond from the suffix we already looked up,
22566 and return the opcode structure.
22568 CM. Examine the tag field to make sure this is an instruction that
22569 should receive a conditional infix after the third character.
22570 If it is not, fail. Otherwise, undo the edits to the current
22571 line of input and proceed as for case CE. */
22573 static const struct asm_opcode
*
22574 opcode_lookup (char **str
)
22578 const struct asm_opcode
*opcode
;
22579 const struct asm_cond
*cond
;
22582 /* Scan up to the end of the mnemonic, which must end in white space,
22583 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22584 for (base
= end
= *str
; *end
!= '\0'; end
++)
22585 if (*end
== ' ' || *end
== '.')
22591 /* Handle a possible width suffix and/or Neon type suffix. */
22596 /* The .w and .n suffixes are only valid if the unified syntax is in
22598 if (unified_syntax
&& end
[1] == 'w')
22600 else if (unified_syntax
&& end
[1] == 'n')
22605 inst
.vectype
.elems
= 0;
22607 *str
= end
+ offset
;
22609 if (end
[offset
] == '.')
22611 /* See if we have a Neon type suffix (possible in either unified or
22612 non-unified ARM syntax mode). */
22613 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22616 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22622 /* Look for unaffixed or special-case affixed mnemonic. */
22623 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22628 if (opcode
->tag
< OT_odd_infix_0
)
22630 inst
.cond
= COND_ALWAYS
;
22634 if (warn_on_deprecated
&& unified_syntax
)
22635 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22636 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22637 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22640 inst
.cond
= cond
->value
;
22643 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22645 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22647 if (end
- base
< 2)
22650 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
22651 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22653 /* If this opcode can not be vector predicated then don't accept it with a
22654 vector predication code. */
22655 if (opcode
&& !opcode
->mayBeVecPred
)
22658 if (!opcode
|| !cond
)
22660 /* Cannot have a conditional suffix on a mnemonic of less than two
22662 if (end
- base
< 3)
22665 /* Look for suffixed mnemonic. */
22667 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22668 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22672 if (opcode
&& cond
)
22675 switch (opcode
->tag
)
22677 case OT_cinfix3_legacy
:
22678 /* Ignore conditional suffixes matched on infix only mnemonics. */
22682 case OT_cinfix3_deprecated
:
22683 case OT_odd_infix_unc
:
22684 if (!unified_syntax
)
22686 /* Fall through. */
22690 case OT_csuf_or_in3
:
22691 inst
.cond
= cond
->value
;
22694 case OT_unconditional
:
22695 case OT_unconditionalF
:
22697 inst
.cond
= cond
->value
;
22700 /* Delayed diagnostic. */
22701 inst
.error
= BAD_COND
;
22702 inst
.cond
= COND_ALWAYS
;
22711 /* Cannot have a usual-position infix on a mnemonic of less than
22712 six characters (five would be a suffix). */
22713 if (end
- base
< 6)
22716 /* Look for infixed mnemonic in the usual position. */
22718 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22722 memcpy (save
, affix
, 2);
22723 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22724 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22726 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22727 memcpy (affix
, save
, 2);
22730 && (opcode
->tag
== OT_cinfix3
22731 || opcode
->tag
== OT_cinfix3_deprecated
22732 || opcode
->tag
== OT_csuf_or_in3
22733 || opcode
->tag
== OT_cinfix3_legacy
))
22736 if (warn_on_deprecated
&& unified_syntax
22737 && (opcode
->tag
== OT_cinfix3
22738 || opcode
->tag
== OT_cinfix3_deprecated
))
22739 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22741 inst
.cond
= cond
->value
;
22748 /* This function generates an initial IT instruction, leaving its block
22749 virtually open for the new instructions. Eventually,
22750 the mask will be updated by now_pred_add_mask () each time
22751 a new instruction needs to be included in the IT block.
22752 Finally, the block is closed with close_automatic_it_block ().
22753 The block closure can be requested either from md_assemble (),
22754 a tencode (), or due to a label hook. */
22757 new_automatic_it_block (int cond
)
22759 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22760 now_pred
.mask
= 0x18;
22761 now_pred
.cc
= cond
;
22762 now_pred
.block_length
= 1;
22763 mapping_state (MAP_THUMB
);
22764 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22765 now_pred
.warn_deprecated
= FALSE
;
22766 now_pred
.insn_cond
= TRUE
;
22769 /* Close an automatic IT block.
22770 See comments in new_automatic_it_block (). */
22773 close_automatic_it_block (void)
22775 now_pred
.mask
= 0x10;
22776 now_pred
.block_length
= 0;
22779 /* Update the mask of the current automatically-generated IT
22780 instruction. See comments in new_automatic_it_block (). */
22783 now_pred_add_mask (int cond
)
22785 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22786 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22787 | ((bitvalue) << (nbit)))
22788 const int resulting_bit
= (cond
& 1);
22790 now_pred
.mask
&= 0xf;
22791 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22793 (5 - now_pred
.block_length
));
22794 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22796 ((5 - now_pred
.block_length
) - 1));
22797 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22800 #undef SET_BIT_VALUE
22803 /* The IT blocks handling machinery is accessed through the these functions:
22804 it_fsm_pre_encode () from md_assemble ()
22805 set_pred_insn_type () optional, from the tencode functions
22806 set_pred_insn_type_last () ditto
22807 in_pred_block () ditto
22808 it_fsm_post_encode () from md_assemble ()
22809 force_automatic_it_block_close () from label handling functions
22812 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22813 initializing the IT insn type with a generic initial value depending
22814 on the inst.condition.
22815 2) During the tencode function, two things may happen:
22816 a) The tencode function overrides the IT insn type by
22817 calling either set_pred_insn_type (type) or
22818 set_pred_insn_type_last ().
22819 b) The tencode function queries the IT block state by
22820 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22822 Both set_pred_insn_type and in_pred_block run the internal FSM state
22823 handling function (handle_pred_state), because: a) setting the IT insn
22824 type may incur in an invalid state (exiting the function),
22825 and b) querying the state requires the FSM to be updated.
22826 Specifically we want to avoid creating an IT block for conditional
22827 branches, so it_fsm_pre_encode is actually a guess and we can't
22828 determine whether an IT block is required until the tencode () routine
22829 has decided what type of instruction this actually it.
22830 Because of this, if set_pred_insn_type and in_pred_block have to be
22831 used, set_pred_insn_type has to be called first.
22833 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22834 that determines the insn IT type depending on the inst.cond code.
22835 When a tencode () routine encodes an instruction that can be
22836 either outside an IT block, or, in the case of being inside, has to be
22837 the last one, set_pred_insn_type_last () will determine the proper
22838 IT instruction type based on the inst.cond code. Otherwise,
22839 set_pred_insn_type can be called for overriding that logic or
22840 for covering other cases.
22842 Calling handle_pred_state () may not transition the IT block state to
22843 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22844 still queried. Instead, if the FSM determines that the state should
22845 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22846 after the tencode () function: that's what it_fsm_post_encode () does.
22848 Since in_pred_block () calls the state handling function to get an
22849 updated state, an error may occur (due to invalid insns combination).
22850 In that case, inst.error is set.
22851 Therefore, inst.error has to be checked after the execution of
22852 the tencode () routine.
22854 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22855 any pending state change (if any) that didn't take place in
22856 handle_pred_state () as explained above. */
22859 it_fsm_pre_encode (void)
22861 if (inst
.cond
!= COND_ALWAYS
)
22862 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22864 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22866 now_pred
.state_handled
= 0;
22869 /* IT state FSM handling function. */
22870 /* MVE instructions and non-MVE instructions are handled differently because of
22871 the introduction of VPT blocks.
22872 Specifications say that any non-MVE instruction inside a VPT block is
22873 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22874 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22875 few exceptions we have MVE_UNPREDICABLE_INSN.
22876 The error messages provided depending on the different combinations possible
22877 are described in the cases below:
22878 For 'most' MVE instructions:
22879 1) In an IT block, with an IT code: syntax error
22880 2) In an IT block, with a VPT code: error: must be in a VPT block
22881 3) In an IT block, with no code: warning: UNPREDICTABLE
22882 4) In a VPT block, with an IT code: syntax error
22883 5) In a VPT block, with a VPT code: OK!
22884 6) In a VPT block, with no code: error: missing code
22885 7) Outside a pred block, with an IT code: error: syntax error
22886 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22887 9) Outside a pred block, with no code: OK!
22888 For non-MVE instructions:
22889 10) In an IT block, with an IT code: OK!
22890 11) In an IT block, with a VPT code: syntax error
22891 12) In an IT block, with no code: error: missing code
22892 13) In a VPT block, with an IT code: error: should be in an IT block
22893 14) In a VPT block, with a VPT code: syntax error
22894 15) In a VPT block, with no code: UNPREDICTABLE
22895 16) Outside a pred block, with an IT code: error: should be in an IT block
22896 17) Outside a pred block, with a VPT code: syntax error
22897 18) Outside a pred block, with no code: OK!
22902 handle_pred_state (void)
22904 now_pred
.state_handled
= 1;
22905 now_pred
.insn_cond
= FALSE
;
22907 switch (now_pred
.state
)
22909 case OUTSIDE_PRED_BLOCK
:
22910 switch (inst
.pred_insn_type
)
22912 case MVE_UNPREDICABLE_INSN
:
22913 case MVE_OUTSIDE_PRED_INSN
:
22914 if (inst
.cond
< COND_ALWAYS
)
22916 /* Case 7: Outside a pred block, with an IT code: error: syntax
22918 inst
.error
= BAD_SYNTAX
;
22921 /* Case 9: Outside a pred block, with no code: OK! */
22923 case OUTSIDE_PRED_INSN
:
22924 if (inst
.cond
> COND_ALWAYS
)
22926 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22928 inst
.error
= BAD_SYNTAX
;
22931 /* Case 18: Outside a pred block, with no code: OK! */
22934 case INSIDE_VPT_INSN
:
22935 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22937 inst
.error
= BAD_OUT_VPT
;
22940 case INSIDE_IT_INSN
:
22941 case INSIDE_IT_LAST_INSN
:
22942 if (inst
.cond
< COND_ALWAYS
)
22944 /* Case 16: Outside a pred block, with an IT code: error: should
22945 be in an IT block. */
22946 if (thumb_mode
== 0)
22949 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22950 as_tsktsk (_("Warning: conditional outside an IT block"\
22955 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22956 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22958 /* Automatically generate the IT instruction. */
22959 new_automatic_it_block (inst
.cond
);
22960 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22961 close_automatic_it_block ();
22965 inst
.error
= BAD_OUT_IT
;
22971 else if (inst
.cond
> COND_ALWAYS
)
22973 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22975 inst
.error
= BAD_SYNTAX
;
22980 case IF_INSIDE_IT_LAST_INSN
:
22981 case NEUTRAL_IT_INSN
:
22985 if (inst
.cond
!= COND_ALWAYS
)
22986 first_error (BAD_SYNTAX
);
22987 now_pred
.state
= MANUAL_PRED_BLOCK
;
22988 now_pred
.block_length
= 0;
22989 now_pred
.type
= VECTOR_PRED
;
22993 now_pred
.state
= MANUAL_PRED_BLOCK
;
22994 now_pred
.block_length
= 0;
22995 now_pred
.type
= SCALAR_PRED
;
23000 case AUTOMATIC_PRED_BLOCK
:
23001 /* Three things may happen now:
23002 a) We should increment current it block size;
23003 b) We should close current it block (closing insn or 4 insns);
23004 c) We should close current it block and start a new one (due
23005 to incompatible conditions or
23006 4 insns-length block reached). */
23008 switch (inst
.pred_insn_type
)
23010 case INSIDE_VPT_INSN
:
23012 case MVE_UNPREDICABLE_INSN
:
23013 case MVE_OUTSIDE_PRED_INSN
:
23015 case OUTSIDE_PRED_INSN
:
23016 /* The closure of the block shall happen immediately,
23017 so any in_pred_block () call reports the block as closed. */
23018 force_automatic_it_block_close ();
23021 case INSIDE_IT_INSN
:
23022 case INSIDE_IT_LAST_INSN
:
23023 case IF_INSIDE_IT_LAST_INSN
:
23024 now_pred
.block_length
++;
23026 if (now_pred
.block_length
> 4
23027 || !now_pred_compatible (inst
.cond
))
23029 force_automatic_it_block_close ();
23030 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23031 new_automatic_it_block (inst
.cond
);
23035 now_pred
.insn_cond
= TRUE
;
23036 now_pred_add_mask (inst
.cond
);
23039 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23040 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23041 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23042 close_automatic_it_block ();
23046 case NEUTRAL_IT_INSN
:
23047 now_pred
.block_length
++;
23048 now_pred
.insn_cond
= TRUE
;
23050 if (now_pred
.block_length
> 4)
23051 force_automatic_it_block_close ();
23053 now_pred_add_mask (now_pred
.cc
& 1);
23057 close_automatic_it_block ();
23058 now_pred
.state
= MANUAL_PRED_BLOCK
;
23063 case MANUAL_PRED_BLOCK
:
23066 if (now_pred
.type
== SCALAR_PRED
)
23068 /* Check conditional suffixes. */
23069 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23070 now_pred
.mask
<<= 1;
23071 now_pred
.mask
&= 0x1f;
23072 is_last
= (now_pred
.mask
== 0x10);
23076 now_pred
.cc
^= (now_pred
.mask
>> 4);
23077 cond
= now_pred
.cc
+ 0xf;
23078 now_pred
.mask
<<= 1;
23079 now_pred
.mask
&= 0x1f;
23080 is_last
= now_pred
.mask
== 0x10;
23082 now_pred
.insn_cond
= TRUE
;
23084 switch (inst
.pred_insn_type
)
23086 case OUTSIDE_PRED_INSN
:
23087 if (now_pred
.type
== SCALAR_PRED
)
23089 if (inst
.cond
== COND_ALWAYS
)
23091 /* Case 12: In an IT block, with no code: error: missing
23093 inst
.error
= BAD_NOT_IT
;
23096 else if (inst
.cond
> COND_ALWAYS
)
23098 /* Case 11: In an IT block, with a VPT code: syntax error.
23100 inst
.error
= BAD_SYNTAX
;
23103 else if (thumb_mode
)
23105 /* This is for some special cases where a non-MVE
23106 instruction is not allowed in an IT block, such as cbz,
23107 but are put into one with a condition code.
23108 You could argue this should be a syntax error, but we
23109 gave the 'not allowed in IT block' diagnostic in the
23110 past so we will keep doing so. */
23111 inst
.error
= BAD_NOT_IT
;
23118 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23119 as_tsktsk (MVE_NOT_VPT
);
23122 case MVE_OUTSIDE_PRED_INSN
:
23123 if (now_pred
.type
== SCALAR_PRED
)
23125 if (inst
.cond
== COND_ALWAYS
)
23127 /* Case 3: In an IT block, with no code: warning:
23129 as_tsktsk (MVE_NOT_IT
);
23132 else if (inst
.cond
< COND_ALWAYS
)
23134 /* Case 1: In an IT block, with an IT code: syntax error.
23136 inst
.error
= BAD_SYNTAX
;
23144 if (inst
.cond
< COND_ALWAYS
)
23146 /* Case 4: In a VPT block, with an IT code: syntax error.
23148 inst
.error
= BAD_SYNTAX
;
23151 else if (inst
.cond
== COND_ALWAYS
)
23153 /* Case 6: In a VPT block, with no code: error: missing
23155 inst
.error
= BAD_NOT_VPT
;
23163 case MVE_UNPREDICABLE_INSN
:
23164 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23166 case INSIDE_IT_INSN
:
23167 if (inst
.cond
> COND_ALWAYS
)
23169 /* Case 11: In an IT block, with a VPT code: syntax error. */
23170 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23171 inst
.error
= BAD_SYNTAX
;
23174 else if (now_pred
.type
== SCALAR_PRED
)
23176 /* Case 10: In an IT block, with an IT code: OK! */
23177 if (cond
!= inst
.cond
)
23179 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23186 /* Case 13: In a VPT block, with an IT code: error: should be
23188 inst
.error
= BAD_OUT_IT
;
23193 case INSIDE_VPT_INSN
:
23194 if (now_pred
.type
== SCALAR_PRED
)
23196 /* Case 2: In an IT block, with a VPT code: error: must be in a
23198 inst
.error
= BAD_OUT_VPT
;
23201 /* Case 5: In a VPT block, with a VPT code: OK! */
23202 else if (cond
!= inst
.cond
)
23204 inst
.error
= BAD_VPT_COND
;
23208 case INSIDE_IT_LAST_INSN
:
23209 case IF_INSIDE_IT_LAST_INSN
:
23210 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23212 /* Case 4: In a VPT block, with an IT code: syntax error. */
23213 /* Case 11: In an IT block, with a VPT code: syntax error. */
23214 inst
.error
= BAD_SYNTAX
;
23217 else if (cond
!= inst
.cond
)
23219 inst
.error
= BAD_IT_COND
;
23224 inst
.error
= BAD_BRANCH
;
23229 case NEUTRAL_IT_INSN
:
23230 /* The BKPT instruction is unconditional even in a IT or VPT
23235 if (now_pred
.type
== SCALAR_PRED
)
23237 inst
.error
= BAD_IT_IT
;
23240 /* fall through. */
23242 if (inst
.cond
== COND_ALWAYS
)
23244 /* Executing a VPT/VPST instruction inside an IT block or a
23245 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23247 if (now_pred
.type
== SCALAR_PRED
)
23248 as_tsktsk (MVE_NOT_IT
);
23250 as_tsktsk (MVE_NOT_VPT
);
23255 /* VPT/VPST do not accept condition codes. */
23256 inst
.error
= BAD_SYNTAX
;
23267 struct depr_insn_mask
23269 unsigned long pattern
;
23270 unsigned long mask
;
23271 const char* description
;
23274 /* List of 16-bit instruction patterns deprecated in an IT block in
23276 static const struct depr_insn_mask depr_it_insns
[] = {
23277 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23278 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23279 { 0xa000, 0xb800, N_("ADR") },
23280 { 0x4800, 0xf800, N_("Literal loads") },
23281 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23282 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23283 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23284 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23285 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23290 it_fsm_post_encode (void)
23294 if (!now_pred
.state_handled
)
23295 handle_pred_state ();
23297 if (now_pred
.insn_cond
23298 && warn_on_restrict_it
23299 && !now_pred
.warn_deprecated
23300 && warn_on_deprecated
23301 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23302 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23304 if (inst
.instruction
>= 0x10000)
23306 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23307 "performance deprecated in ARMv8-A and ARMv8-R"));
23308 now_pred
.warn_deprecated
= TRUE
;
23312 const struct depr_insn_mask
*p
= depr_it_insns
;
23314 while (p
->mask
!= 0)
23316 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23318 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23319 "instructions of the following class are "
23320 "performance deprecated in ARMv8-A and "
23321 "ARMv8-R: %s"), p
->description
);
23322 now_pred
.warn_deprecated
= TRUE
;
23330 if (now_pred
.block_length
> 1)
23332 as_tsktsk (_("IT blocks containing more than one conditional "
23333 "instruction are performance deprecated in ARMv8-A and "
23335 now_pred
.warn_deprecated
= TRUE
;
23339 is_last
= (now_pred
.mask
== 0x10);
23342 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23348 force_automatic_it_block_close (void)
23350 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23352 close_automatic_it_block ();
23353 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23359 in_pred_block (void)
23361 if (!now_pred
.state_handled
)
23362 handle_pred_state ();
23364 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23367 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23368 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23369 here, hence the "known" in the function name. */
23372 known_t32_only_insn (const struct asm_opcode
*opcode
)
23374 /* Original Thumb-1 wide instruction. */
23375 if (opcode
->tencode
== do_t_blx
23376 || opcode
->tencode
== do_t_branch23
23377 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23378 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23381 /* Wide-only instruction added to ARMv8-M Baseline. */
23382 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23383 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23384 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23385 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23391 /* Whether wide instruction variant can be used if available for a valid OPCODE
23395 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23397 if (known_t32_only_insn (opcode
))
23400 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23401 of variant T3 of B.W is checked in do_t_branch. */
23402 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23403 && opcode
->tencode
== do_t_branch
)
23406 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23407 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23408 && opcode
->tencode
== do_t_mov_cmp
23409 /* Make sure CMP instruction is not affected. */
23410 && opcode
->aencode
== do_mov
)
23413 /* Wide instruction variants of all instructions with narrow *and* wide
23414 variants become available with ARMv6t2. Other opcodes are either
23415 narrow-only or wide-only and are thus available if OPCODE is valid. */
23416 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23419 /* OPCODE with narrow only instruction variant or wide variant not
23425 md_assemble (char *str
)
23428 const struct asm_opcode
* opcode
;
23430 /* Align the previous label if needed. */
23431 if (last_label_seen
!= NULL
)
23433 symbol_set_frag (last_label_seen
, frag_now
);
23434 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23435 S_SET_SEGMENT (last_label_seen
, now_seg
);
23438 memset (&inst
, '\0', sizeof (inst
));
23440 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23441 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23443 opcode
= opcode_lookup (&p
);
23446 /* It wasn't an instruction, but it might be a register alias of
23447 the form alias .req reg, or a Neon .dn/.qn directive. */
23448 if (! create_register_alias (str
, p
)
23449 && ! create_neon_reg_alias (str
, p
))
23450 as_bad (_("bad instruction `%s'"), str
);
23455 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23456 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23458 /* The value which unconditional instructions should have in place of the
23459 condition field. */
23460 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
23464 arm_feature_set variant
;
23466 variant
= cpu_variant
;
23467 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23468 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23469 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23470 /* Check that this instruction is supported for this CPU. */
23471 if (!opcode
->tvariant
23472 || (thumb_mode
== 1
23473 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23475 if (opcode
->tencode
== do_t_swi
)
23476 as_bad (_("SVC is not permitted on this architecture"));
23478 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23481 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23482 && opcode
->tencode
!= do_t_branch
)
23484 as_bad (_("Thumb does not support conditional execution"));
23488 /* Two things are addressed here:
23489 1) Implicit require narrow instructions on Thumb-1.
23490 This avoids relaxation accidentally introducing Thumb-2
23492 2) Reject wide instructions in non Thumb-2 cores.
23494 Only instructions with narrow and wide variants need to be handled
23495 but selecting all non wide-only instructions is easier. */
23496 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23497 && !t32_insn_ok (variant
, opcode
))
23499 if (inst
.size_req
== 0)
23501 else if (inst
.size_req
== 4)
23503 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23504 as_bad (_("selected processor does not support 32bit wide "
23505 "variant of instruction `%s'"), str
);
23507 as_bad (_("selected processor does not support `%s' in "
23508 "Thumb-2 mode"), str
);
23513 inst
.instruction
= opcode
->tvalue
;
23515 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23517 /* Prepare the pred_insn_type for those encodings that don't set
23519 it_fsm_pre_encode ();
23521 opcode
->tencode ();
23523 it_fsm_post_encode ();
23526 if (!(inst
.error
|| inst
.relax
))
23528 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23529 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23530 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23532 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23537 /* Something has gone badly wrong if we try to relax a fixed size
23539 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23541 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23542 *opcode
->tvariant
);
23543 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23544 set those bits when Thumb-2 32-bit instructions are seen. The impact
23545 of relaxable instructions will be considered later after we finish all
23547 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23548 variant
= arm_arch_none
;
23550 variant
= cpu_variant
;
23551 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23552 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23555 check_neon_suffixes
;
23559 mapping_state (MAP_THUMB
);
23562 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23566 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23567 is_bx
= (opcode
->aencode
== do_bx
);
23569 /* Check that this instruction is supported for this CPU. */
23570 if (!(is_bx
&& fix_v4bx
)
23571 && !(opcode
->avariant
&&
23572 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23574 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23579 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23583 inst
.instruction
= opcode
->avalue
;
23584 if (opcode
->tag
== OT_unconditionalF
)
23585 inst
.instruction
|= 0xFU
<< 28;
23587 inst
.instruction
|= inst
.cond
<< 28;
23588 inst
.size
= INSN_SIZE
;
23589 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23591 it_fsm_pre_encode ();
23592 opcode
->aencode ();
23593 it_fsm_post_encode ();
23595 /* Arm mode bx is marked as both v4T and v5 because it's still required
23596 on a hypothetical non-thumb v5 core. */
23598 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23601 *opcode
->avariant
);
23603 check_neon_suffixes
;
23607 mapping_state (MAP_ARM
);
23612 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23620 check_pred_blocks_finished (void)
23625 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23626 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23627 == MANUAL_PRED_BLOCK
)
23629 if (now_pred
.type
== SCALAR_PRED
)
23630 as_warn (_("section '%s' finished with an open IT block."),
23633 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23637 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23639 if (now_pred
.type
== SCALAR_PRED
)
23640 as_warn (_("file finished with an open IT block."));
23642 as_warn (_("file finished with an open VPT/VPST block."));
23647 /* Various frobbings of labels and their addresses. */
23650 arm_start_line_hook (void)
23652 last_label_seen
= NULL
;
23656 arm_frob_label (symbolS
* sym
)
23658 last_label_seen
= sym
;
23660 ARM_SET_THUMB (sym
, thumb_mode
);
23662 #if defined OBJ_COFF || defined OBJ_ELF
23663 ARM_SET_INTERWORK (sym
, support_interwork
);
23666 force_automatic_it_block_close ();
23668 /* Note - do not allow local symbols (.Lxxx) to be labelled
23669 as Thumb functions. This is because these labels, whilst
23670 they exist inside Thumb code, are not the entry points for
23671 possible ARM->Thumb calls. Also, these labels can be used
23672 as part of a computed goto or switch statement. eg gcc
23673 can generate code that looks like this:
23675 ldr r2, [pc, .Laaa]
23685 The first instruction loads the address of the jump table.
23686 The second instruction converts a table index into a byte offset.
23687 The third instruction gets the jump address out of the table.
23688 The fourth instruction performs the jump.
23690 If the address stored at .Laaa is that of a symbol which has the
23691 Thumb_Func bit set, then the linker will arrange for this address
23692 to have the bottom bit set, which in turn would mean that the
23693 address computation performed by the third instruction would end
23694 up with the bottom bit set. Since the ARM is capable of unaligned
23695 word loads, the instruction would then load the incorrect address
23696 out of the jump table, and chaos would ensue. */
23697 if (label_is_thumb_function_name
23698 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23699 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23701 /* When the address of a Thumb function is taken the bottom
23702 bit of that address should be set. This will allow
23703 interworking between Arm and Thumb functions to work
23706 THUMB_SET_FUNC (sym
, 1);
23708 label_is_thumb_function_name
= FALSE
;
23711 dwarf2_emit_label (sym
);
23715 arm_data_in_code (void)
23717 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23719 *input_line_pointer
= '/';
23720 input_line_pointer
+= 5;
23721 *input_line_pointer
= 0;
23729 arm_canonicalize_symbol_name (char * name
)
23733 if (thumb_mode
&& (len
= strlen (name
)) > 5
23734 && streq (name
+ len
- 5, "/data"))
23735 *(name
+ len
- 5) = 0;
23740 /* Table of all register names defined by default. The user can
23741 define additional names with .req. Note that all register names
23742 should appear in both upper and lowercase variants. Some registers
23743 also have mixed-case names. */
23745 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23746 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23747 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23748 #define REGSET(p,t) \
23749 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23750 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23751 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23752 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23753 #define REGSETH(p,t) \
23754 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23755 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23756 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23757 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23758 #define REGSET2(p,t) \
23759 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23760 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23761 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23762 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23763 #define SPLRBANK(base,bank,t) \
23764 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23765 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23766 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23767 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23768 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23769 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23771 static const struct reg_entry reg_names
[] =
23773 /* ARM integer registers. */
23774 REGSET(r
, RN
), REGSET(R
, RN
),
23776 /* ATPCS synonyms. */
23777 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23778 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23779 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23781 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23782 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23783 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23785 /* Well-known aliases. */
23786 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23787 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23789 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23790 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23792 /* Defining the new Zero register from ARMv8.1-M. */
23796 /* Coprocessor numbers. */
23797 REGSET(p
, CP
), REGSET(P
, CP
),
23799 /* Coprocessor register numbers. The "cr" variants are for backward
23801 REGSET(c
, CN
), REGSET(C
, CN
),
23802 REGSET(cr
, CN
), REGSET(CR
, CN
),
23804 /* ARM banked registers. */
23805 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23806 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23807 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23808 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23809 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23810 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23811 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23813 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23814 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23815 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23816 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23817 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23818 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23819 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23820 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23822 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23823 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23824 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23825 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23826 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23827 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23828 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23829 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23830 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23832 /* FPA registers. */
23833 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23834 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23836 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23837 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23839 /* VFP SP registers. */
23840 REGSET(s
,VFS
), REGSET(S
,VFS
),
23841 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23843 /* VFP DP Registers. */
23844 REGSET(d
,VFD
), REGSET(D
,VFD
),
23845 /* Extra Neon DP registers. */
23846 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23848 /* Neon QP registers. */
23849 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23851 /* VFP control registers. */
23852 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23853 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23854 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23855 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23856 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23857 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23858 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23859 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23860 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23861 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23862 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23864 /* Maverick DSP coprocessor registers. */
23865 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23866 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23868 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23869 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23870 REGDEF(dspsc
,0,DSPSC
),
23872 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23873 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23874 REGDEF(DSPSC
,0,DSPSC
),
23876 /* iWMMXt data registers - p0, c0-15. */
23877 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23879 /* iWMMXt control registers - p1, c0-3. */
23880 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23881 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23882 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23883 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23885 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23886 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23887 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23888 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23889 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23891 /* XScale accumulator registers. */
23892 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23898 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23899 within psr_required_here. */
23900 static const struct asm_psr psrs
[] =
23902 /* Backward compatibility notation. Note that "all" is no longer
23903 truly all possible PSR bits. */
23904 {"all", PSR_c
| PSR_f
},
23908 /* Individual flags. */
23914 /* Combinations of flags. */
23915 {"fs", PSR_f
| PSR_s
},
23916 {"fx", PSR_f
| PSR_x
},
23917 {"fc", PSR_f
| PSR_c
},
23918 {"sf", PSR_s
| PSR_f
},
23919 {"sx", PSR_s
| PSR_x
},
23920 {"sc", PSR_s
| PSR_c
},
23921 {"xf", PSR_x
| PSR_f
},
23922 {"xs", PSR_x
| PSR_s
},
23923 {"xc", PSR_x
| PSR_c
},
23924 {"cf", PSR_c
| PSR_f
},
23925 {"cs", PSR_c
| PSR_s
},
23926 {"cx", PSR_c
| PSR_x
},
23927 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23928 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23929 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23930 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23931 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23932 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23933 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23934 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23935 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23936 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23937 {"scf", PSR_s
| PSR_c
| PSR_f
},
23938 {"scx", PSR_s
| PSR_c
| PSR_x
},
23939 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23940 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23941 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23942 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23943 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23944 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23945 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23946 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23947 {"csf", PSR_c
| PSR_s
| PSR_f
},
23948 {"csx", PSR_c
| PSR_s
| PSR_x
},
23949 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23950 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23951 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23952 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23953 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23954 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23955 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23956 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23957 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23958 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23959 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23960 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23961 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23962 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23963 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23964 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23965 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23966 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23967 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23968 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23969 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23970 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23971 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23972 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23973 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23974 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23977 /* Table of V7M psr names. */
23978 static const struct asm_psr v7m_psrs
[] =
23980 {"apsr", 0x0 }, {"APSR", 0x0 },
23981 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23982 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23983 {"psr", 0x3 }, {"PSR", 0x3 },
23984 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23985 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23986 {"epsr", 0x6 }, {"EPSR", 0x6 },
23987 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23988 {"msp", 0x8 }, {"MSP", 0x8 },
23989 {"psp", 0x9 }, {"PSP", 0x9 },
23990 {"msplim", 0xa }, {"MSPLIM", 0xa },
23991 {"psplim", 0xb }, {"PSPLIM", 0xb },
23992 {"primask", 0x10}, {"PRIMASK", 0x10},
23993 {"basepri", 0x11}, {"BASEPRI", 0x11},
23994 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23995 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23996 {"control", 0x14}, {"CONTROL", 0x14},
23997 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23998 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23999 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24000 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24001 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24002 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24003 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24004 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24005 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24008 /* Table of all shift-in-operand names. */
24009 static const struct asm_shift_name shift_names
[] =
24011 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24012 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24013 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24014 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24015 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24016 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24017 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24020 /* Table of all explicit relocation names. */
24022 static struct reloc_entry reloc_names
[] =
24024 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24025 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24026 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24027 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24028 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24029 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24030 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24031 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24032 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24033 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24034 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24035 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24036 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24037 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24038 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24039 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24040 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24041 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24042 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24043 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24044 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24045 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24046 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24047 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24048 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24049 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24050 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24054 /* Table of all conditional affixes. */
24055 static const struct asm_cond conds
[] =
24059 {"cs", 0x2}, {"hs", 0x2},
24060 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24073 static const struct asm_cond vconds
[] =
24079 #define UL_BARRIER(L,U,CODE,FEAT) \
24080 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24081 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24083 static struct asm_barrier_opt barrier_opt_names
[] =
24085 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24086 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24087 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24088 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24089 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24090 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24091 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24092 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24093 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24094 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24095 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24096 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24097 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24098 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24099 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24105 /* Table of ARM-format instructions. */
24107 /* Macros for gluing together operand strings. N.B. In all cases
24108 other than OPS0, the trailing OP_stop comes from default
24109 zero-initialization of the unspecified elements of the array. */
24110 #define OPS0() { OP_stop, }
24111 #define OPS1(a) { OP_##a, }
24112 #define OPS2(a,b) { OP_##a,OP_##b, }
24113 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24114 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24115 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24116 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24118 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24119 This is useful when mixing operands for ARM and THUMB, i.e. using the
24120 MIX_ARM_THUMB_OPERANDS macro.
24121 In order to use these macros, prefix the number of operands with _
24123 #define OPS_1(a) { a, }
24124 #define OPS_2(a,b) { a,b, }
24125 #define OPS_3(a,b,c) { a,b,c, }
24126 #define OPS_4(a,b,c,d) { a,b,c,d, }
24127 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24128 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24130 /* These macros abstract out the exact format of the mnemonic table and
24131 save some repeated characters. */
24133 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24134 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24135 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24136 THUMB_VARIANT, do_##ae, do_##te, 0 }
24138 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24139 a T_MNEM_xyz enumerator. */
24140 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24141 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24142 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24143 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24145 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24146 infix after the third character. */
24147 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24148 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24149 THUMB_VARIANT, do_##ae, do_##te, 0 }
24150 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24151 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24152 THUMB_VARIANT, do_##ae, do_##te, 0 }
24153 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24154 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24155 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24156 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24157 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24158 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24159 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24160 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24162 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24163 field is still 0xE. Many of the Thumb variants can be executed
24164 conditionally, so this is checked separately. */
24165 #define TUE(mnem, op, top, nops, ops, ae, te) \
24166 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24167 THUMB_VARIANT, do_##ae, do_##te, 0 }
24169 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24170 Used by mnemonics that have very minimal differences in the encoding for
24171 ARM and Thumb variants and can be handled in a common function. */
24172 #define TUEc(mnem, op, top, nops, ops, en) \
24173 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24174 THUMB_VARIANT, do_##en, do_##en, 0 }
24176 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24177 condition code field. */
24178 #define TUF(mnem, op, top, nops, ops, ae, te) \
24179 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24180 THUMB_VARIANT, do_##ae, do_##te, 0 }
24182 /* ARM-only variants of all the above. */
24183 #define CE(mnem, op, nops, ops, ae) \
24184 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24186 #define C3(mnem, op, nops, ops, ae) \
24187 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24189 /* Thumb-only variants of TCE and TUE. */
24190 #define ToC(mnem, top, nops, ops, te) \
24191 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24194 #define ToU(mnem, top, nops, ops, te) \
24195 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24198 /* T_MNEM_xyz enumerator variants of ToC. */
24199 #define toC(mnem, top, nops, ops, te) \
24200 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24203 /* T_MNEM_xyz enumerator variants of ToU. */
24204 #define toU(mnem, top, nops, ops, te) \
24205 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24208 /* Legacy mnemonics that always have conditional infix after the third
24210 #define CL(mnem, op, nops, ops, ae) \
24211 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24212 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24214 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24215 #define cCE(mnem, op, nops, ops, ae) \
24216 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24218 /* mov instructions that are shared between coprocessor and MVE. */
24219 #define mcCE(mnem, op, nops, ops, ae) \
24220 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24222 /* Legacy coprocessor instructions where conditional infix and conditional
24223 suffix are ambiguous. For consistency this includes all FPA instructions,
24224 not just the potentially ambiguous ones. */
24225 #define cCL(mnem, op, nops, ops, ae) \
24226 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24227 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24229 /* Coprocessor, takes either a suffix or a position-3 infix
24230 (for an FPA corner case). */
24231 #define C3E(mnem, op, nops, ops, ae) \
24232 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24233 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24235 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24236 { m1 #m2 m3, OPS##nops ops, \
24237 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24238 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24240 #define CM(m1, m2, op, nops, ops, ae) \
24241 xCM_ (m1, , m2, op, nops, ops, ae), \
24242 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24243 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24244 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24245 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24246 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24247 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24248 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24249 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24250 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24251 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24252 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24253 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24254 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24255 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24256 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24257 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24258 xCM_ (m1, le, m2, op, nops, ops, ae), \
24259 xCM_ (m1, al, m2, op, nops, ops, ae)
24261 #define UE(mnem, op, nops, ops, ae) \
24262 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24264 #define UF(mnem, op, nops, ops, ae) \
24265 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24267 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24268 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24269 use the same encoding function for each. */
24270 #define NUF(mnem, op, nops, ops, enc) \
24271 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24272 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24274 /* Neon data processing, version which indirects through neon_enc_tab for
24275 the various overloaded versions of opcodes. */
24276 #define nUF(mnem, op, nops, ops, enc) \
24277 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24278 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24280 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24282 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24283 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24284 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24286 #define NCE(mnem, op, nops, ops, enc) \
24287 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24289 #define NCEF(mnem, op, nops, ops, enc) \
24290 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24292 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24293 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24294 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24295 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24297 #define nCE(mnem, op, nops, ops, enc) \
24298 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24300 #define nCEF(mnem, op, nops, ops, enc) \
24301 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24304 #define mCEF(mnem, op, nops, ops, enc) \
24305 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24306 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24309 /* nCEF but for MVE predicated instructions. */
24310 #define mnCEF(mnem, op, nops, ops, enc) \
24311 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24313 /* nCE but for MVE predicated instructions. */
24314 #define mnCE(mnem, op, nops, ops, enc) \
24315 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24317 /* NUF but for potentially MVE predicated instructions. */
24318 #define MNUF(mnem, op, nops, ops, enc) \
24319 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24320 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24322 /* nUF but for potentially MVE predicated instructions. */
24323 #define mnUF(mnem, op, nops, ops, enc) \
24324 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24325 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24327 /* ToC but for potentially MVE predicated instructions. */
24328 #define mToC(mnem, top, nops, ops, te) \
24329 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24332 /* NCE but for MVE predicated instructions. */
24333 #define MNCE(mnem, op, nops, ops, enc) \
24334 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24336 /* NCEF but for MVE predicated instructions. */
24337 #define MNCEF(mnem, op, nops, ops, enc) \
24338 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24341 static const struct asm_opcode insns
[] =
24343 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24344 #define THUMB_VARIANT & arm_ext_v4t
24345 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24346 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24347 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24348 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24349 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24350 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24351 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24352 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24353 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24354 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24355 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24356 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24357 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24358 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24360 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24362 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24363 for setting PSR flag bits. They are obsolete in V6 and do not
24364 have Thumb equivalents. */
24365 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24366 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24367 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24368 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24369 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24370 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24371 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24372 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24373 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24375 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24376 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24377 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24378 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24380 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24381 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24382 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24384 OP_ADDRGLDR
),ldst
, t_ldst
),
24385 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24387 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24388 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24389 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24390 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24391 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24392 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24394 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24395 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24398 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24399 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24400 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24401 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24403 /* Thumb-compatibility pseudo ops. */
24404 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24405 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24406 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24407 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24408 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24409 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24410 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24411 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24412 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24413 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24414 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24415 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24417 /* These may simplify to neg. */
24418 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24419 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24421 #undef THUMB_VARIANT
24422 #define THUMB_VARIANT & arm_ext_os
24424 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24425 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24427 #undef THUMB_VARIANT
24428 #define THUMB_VARIANT & arm_ext_v6
24430 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24432 /* V1 instructions with no Thumb analogue prior to V6T2. */
24433 #undef THUMB_VARIANT
24434 #define THUMB_VARIANT & arm_ext_v6t2
24436 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24437 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24438 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24440 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24441 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24442 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24443 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24445 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24446 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24448 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24449 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24451 /* V1 instructions with no Thumb analogue at all. */
24452 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24453 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24455 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24456 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24457 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24458 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24459 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24460 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24461 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24462 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24465 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24466 #undef THUMB_VARIANT
24467 #define THUMB_VARIANT & arm_ext_v4t
24469 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24470 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24472 #undef THUMB_VARIANT
24473 #define THUMB_VARIANT & arm_ext_v6t2
24475 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24476 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24478 /* Generic coprocessor instructions. */
24479 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24480 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24481 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24482 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24483 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24484 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24485 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24488 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24490 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24491 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24494 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24495 #undef THUMB_VARIANT
24496 #define THUMB_VARIANT & arm_ext_msr
24498 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24499 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24502 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24503 #undef THUMB_VARIANT
24504 #define THUMB_VARIANT & arm_ext_v6t2
24506 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24507 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24508 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24509 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24510 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24511 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24512 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24513 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24516 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24517 #undef THUMB_VARIANT
24518 #define THUMB_VARIANT & arm_ext_v4t
24520 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24521 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24522 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24523 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24524 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24525 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24528 #define ARM_VARIANT & arm_ext_v4t_5
24530 /* ARM Architecture 4T. */
24531 /* Note: bx (and blx) are required on V5, even if the processor does
24532 not support Thumb. */
24533 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24536 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24537 #undef THUMB_VARIANT
24538 #define THUMB_VARIANT & arm_ext_v5t
24540 /* Note: blx has 2 variants; the .value coded here is for
24541 BLX(2). Only this variant has conditional execution. */
24542 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24543 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24545 #undef THUMB_VARIANT
24546 #define THUMB_VARIANT & arm_ext_v6t2
24548 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24549 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24550 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24551 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24552 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24553 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24554 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24555 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24558 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24559 #undef THUMB_VARIANT
24560 #define THUMB_VARIANT & arm_ext_v5exp
24562 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24563 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24564 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24565 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24567 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24568 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24570 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24571 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24572 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24573 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24575 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24576 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24577 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24578 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24580 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24581 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24583 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24584 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24585 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24586 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24589 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24590 #undef THUMB_VARIANT
24591 #define THUMB_VARIANT & arm_ext_v6t2
24593 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24594 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24596 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24597 ADDRGLDRS
), ldrd
, t_ldstd
),
24599 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24600 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24603 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24605 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24608 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24609 #undef THUMB_VARIANT
24610 #define THUMB_VARIANT & arm_ext_v6
24612 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24613 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24614 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24615 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24616 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24617 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24618 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24619 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24620 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24621 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24623 #undef THUMB_VARIANT
24624 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24626 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24627 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24629 #undef THUMB_VARIANT
24630 #define THUMB_VARIANT & arm_ext_v6t2
24632 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24633 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24635 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24636 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24638 /* ARM V6 not included in V7M. */
24639 #undef THUMB_VARIANT
24640 #define THUMB_VARIANT & arm_ext_v6_notm
24641 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24642 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24643 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24644 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24645 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24646 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24647 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24648 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24649 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24650 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24651 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24652 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24653 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24654 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24655 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24656 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24657 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24658 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24659 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24661 /* ARM V6 not included in V7M (eg. integer SIMD). */
24662 #undef THUMB_VARIANT
24663 #define THUMB_VARIANT & arm_ext_v6_dsp
24664 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24665 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24666 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24667 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24668 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24669 /* Old name for QASX. */
24670 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24671 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24672 /* Old name for QSAX. */
24673 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24674 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24675 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24676 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24677 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24678 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24679 /* Old name for SASX. */
24680 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24681 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 /* Old name for SHASX. */
24685 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24686 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 /* Old name for SHSAX. */
24688 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24689 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 /* Old name for SSAX. */
24693 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 /* Old name for UASX. */
24700 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 /* Old name for UHASX. */
24705 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 /* Old name for UHSAX. */
24708 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 /* Old name for UQASX. */
24715 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 /* Old name for UQSAX. */
24718 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24720 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 /* Old name for USAX. */
24724 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24727 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24728 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24729 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24730 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24731 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24732 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24733 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24734 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24735 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24736 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24737 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24738 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24739 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24740 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24741 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24742 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24743 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24744 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24745 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24746 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24747 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24748 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24749 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24750 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24751 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24752 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24753 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24754 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24755 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24756 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24757 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24760 #define ARM_VARIANT & arm_ext_v6k_v6t2
24761 #undef THUMB_VARIANT
24762 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24764 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24765 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24766 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24767 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24769 #undef THUMB_VARIANT
24770 #define THUMB_VARIANT & arm_ext_v6_notm
24771 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24773 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24774 RRnpcb
), strexd
, t_strexd
),
24776 #undef THUMB_VARIANT
24777 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24778 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24780 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24782 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24784 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24786 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24789 #define ARM_VARIANT & arm_ext_sec
24790 #undef THUMB_VARIANT
24791 #define THUMB_VARIANT & arm_ext_sec
24793 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24796 #define ARM_VARIANT & arm_ext_virt
24797 #undef THUMB_VARIANT
24798 #define THUMB_VARIANT & arm_ext_virt
24800 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24801 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24804 #define ARM_VARIANT & arm_ext_pan
24805 #undef THUMB_VARIANT
24806 #define THUMB_VARIANT & arm_ext_pan
24808 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24811 #define ARM_VARIANT & arm_ext_v6t2
24812 #undef THUMB_VARIANT
24813 #define THUMB_VARIANT & arm_ext_v6t2
24815 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24816 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24817 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24818 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24820 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24821 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24823 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24824 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24825 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24826 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24829 #define ARM_VARIANT & arm_ext_v3
24830 #undef THUMB_VARIANT
24831 #define THUMB_VARIANT & arm_ext_v6t2
24833 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24834 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24835 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24838 #define ARM_VARIANT & arm_ext_v6t2
24839 #undef THUMB_VARIANT
24840 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24841 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24842 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24844 /* Thumb-only instructions. */
24846 #define ARM_VARIANT NULL
24847 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24848 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24850 /* ARM does not really have an IT instruction, so always allow it.
24851 The opcode is copied from Thumb in order to allow warnings in
24852 -mimplicit-it=[never | arm] modes. */
24854 #define ARM_VARIANT & arm_ext_v1
24855 #undef THUMB_VARIANT
24856 #define THUMB_VARIANT & arm_ext_v6t2
24858 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24859 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24860 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24861 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24862 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24863 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24864 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24865 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24866 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24867 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24868 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24869 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24870 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24871 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24872 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24873 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24874 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24875 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24877 /* Thumb2 only instructions. */
24879 #define ARM_VARIANT NULL
24881 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24882 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24883 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24884 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24885 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24886 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24888 /* Hardware division instructions. */
24890 #define ARM_VARIANT & arm_ext_adiv
24891 #undef THUMB_VARIANT
24892 #define THUMB_VARIANT & arm_ext_div
24894 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24895 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24897 /* ARM V6M/V7 instructions. */
24899 #define ARM_VARIANT & arm_ext_barrier
24900 #undef THUMB_VARIANT
24901 #define THUMB_VARIANT & arm_ext_barrier
24903 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24904 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24905 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24907 /* ARM V7 instructions. */
24909 #define ARM_VARIANT & arm_ext_v7
24910 #undef THUMB_VARIANT
24911 #define THUMB_VARIANT & arm_ext_v7
24913 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24914 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24917 #define ARM_VARIANT & arm_ext_mp
24918 #undef THUMB_VARIANT
24919 #define THUMB_VARIANT & arm_ext_mp
24921 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24923 /* AArchv8 instructions. */
24925 #define ARM_VARIANT & arm_ext_v8
24927 /* Instructions shared between armv8-a and armv8-m. */
24928 #undef THUMB_VARIANT
24929 #define THUMB_VARIANT & arm_ext_atomics
24931 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24932 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24933 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24934 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24935 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24936 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24937 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24938 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24939 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24940 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24942 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24944 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24946 #undef THUMB_VARIANT
24947 #define THUMB_VARIANT & arm_ext_v8
24949 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24950 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24952 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24955 /* Defined in V8 but is in undefined encoding space for earlier
24956 architectures. However earlier architectures are required to treat
24957 this instuction as a semihosting trap as well. Hence while not explicitly
24958 defined as such, it is in fact correct to define the instruction for all
24960 #undef THUMB_VARIANT
24961 #define THUMB_VARIANT & arm_ext_v1
24963 #define ARM_VARIANT & arm_ext_v1
24964 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24966 /* ARMv8 T32 only. */
24968 #define ARM_VARIANT NULL
24969 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24970 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24971 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24973 /* FP for ARMv8. */
24975 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24976 #undef THUMB_VARIANT
24977 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24979 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24980 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24981 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24982 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24983 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24984 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24985 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24986 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24987 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24988 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24989 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24991 /* Crypto v1 extensions. */
24993 #define ARM_VARIANT & fpu_crypto_ext_armv8
24994 #undef THUMB_VARIANT
24995 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24997 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24998 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24999 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25000 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25001 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25002 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25003 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25004 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25005 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25006 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25007 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25008 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25009 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25010 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25013 #define ARM_VARIANT & arm_ext_crc
25014 #undef THUMB_VARIANT
25015 #define THUMB_VARIANT & arm_ext_crc
25016 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25017 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25018 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25019 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25020 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25021 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25023 /* ARMv8.2 RAS extension. */
25025 #define ARM_VARIANT & arm_ext_ras
25026 #undef THUMB_VARIANT
25027 #define THUMB_VARIANT & arm_ext_ras
25028 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25031 #define ARM_VARIANT & arm_ext_v8_3
25032 #undef THUMB_VARIANT
25033 #define THUMB_VARIANT & arm_ext_v8_3
25034 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25037 #define ARM_VARIANT & fpu_neon_ext_dotprod
25038 #undef THUMB_VARIANT
25039 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25040 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25041 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25044 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25045 #undef THUMB_VARIANT
25046 #define THUMB_VARIANT NULL
25048 cCE("wfs", e200110
, 1, (RR
), rd
),
25049 cCE("rfs", e300110
, 1, (RR
), rd
),
25050 cCE("wfc", e400110
, 1, (RR
), rd
),
25051 cCE("rfc", e500110
, 1, (RR
), rd
),
25053 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25054 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25055 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25056 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25058 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25059 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25060 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25061 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25063 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25064 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25065 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25066 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25067 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25068 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25069 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25070 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25071 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25072 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25073 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25074 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25076 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25077 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25078 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25082 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25083 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25095 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25272 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25273 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25274 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25275 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25276 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25277 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25278 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25279 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25280 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25281 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25282 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25284 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25285 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25286 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25290 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25291 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25303 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25441 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25442 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25443 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25445 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25446 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25447 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25448 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25449 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25450 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25451 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25452 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25453 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25454 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25455 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25456 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25458 /* The implementation of the FIX instruction is broken on some
25459 assemblers, in that it accepts a precision specifier as well as a
25460 rounding specifier, despite the fact that this is meaningless.
25461 To be more compatible, we accept it as well, though of course it
25462 does not set any bits. */
25463 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25464 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25465 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25466 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25467 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25468 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25469 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25470 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25471 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25472 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25473 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25474 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25475 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25477 /* Instructions that were new with the real FPA, call them V2. */
25479 #define ARM_VARIANT & fpu_fpa_ext_v2
25481 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25482 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25483 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25484 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25485 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25486 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25489 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25490 #undef THUMB_VARIANT
25491 #define THUMB_VARIANT & arm_ext_v6t2
25492 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25493 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25494 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25495 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25496 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25497 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25499 /* Memory operations. */
25500 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25501 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25502 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25503 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25504 #undef THUMB_VARIANT
25506 /* Moves and type conversions. */
25507 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25508 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25509 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25510 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25511 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25512 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25513 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25514 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25515 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25517 /* Memory operations. */
25518 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25519 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25520 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25521 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25522 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25523 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25524 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25525 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25526 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25527 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25528 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25529 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25531 /* Monadic operations. */
25532 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25533 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25534 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25536 /* Dyadic operations. */
25537 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25538 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25539 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25540 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25541 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25542 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25543 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25544 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25545 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25548 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25549 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25550 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25551 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25553 /* Double precision load/store are still present on single precision
25554 implementations. */
25555 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25556 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25557 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25558 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25559 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25560 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25561 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25562 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25565 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25567 /* Moves and type conversions. */
25568 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25569 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25570 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25571 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25572 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25573 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25574 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25575 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25576 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25577 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25578 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25579 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25581 /* Monadic operations. */
25582 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25583 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25584 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25586 /* Dyadic operations. */
25587 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25588 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25589 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25590 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25591 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25592 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25593 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25594 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25595 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25598 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25599 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25600 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25601 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25603 /* Instructions which may belong to either the Neon or VFP instruction sets.
25604 Individual encoder functions perform additional architecture checks. */
25606 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25607 #undef THUMB_VARIANT
25608 #define THUMB_VARIANT & arm_ext_v6t2
25610 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25611 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25612 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25613 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25614 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25615 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25617 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25618 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25620 #undef THUMB_VARIANT
25621 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25623 /* These mnemonics are unique to VFP. */
25624 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25625 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25626 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25627 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25628 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25629 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25631 /* Mnemonics shared by Neon and VFP. */
25632 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25634 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25635 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25636 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25637 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25640 /* NOTE: All VMOV encoding is special-cased! */
25641 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25643 #undef THUMB_VARIANT
25644 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25645 by different feature bits. Since we are setting the Thumb guard, we can
25646 require Thumb-1 which makes it a nop guard and set the right feature bit in
25647 do_vldr_vstr (). */
25648 #define THUMB_VARIANT & arm_ext_v4t
25649 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25650 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25653 #define ARM_VARIANT & arm_ext_fp16
25654 #undef THUMB_VARIANT
25655 #define THUMB_VARIANT & arm_ext_fp16
25656 /* New instructions added from v8.2, allowing the extraction and insertion of
25657 the upper 16 bits of a 32-bit vector register. */
25658 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25659 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25661 /* New backported fma/fms instructions optional in v8.2. */
25662 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25663 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25665 #undef THUMB_VARIANT
25666 #define THUMB_VARIANT & fpu_neon_ext_v1
25668 #define ARM_VARIANT & fpu_neon_ext_v1
25670 /* Data processing with three registers of the same length. */
25671 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25672 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25673 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25674 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25675 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25676 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25677 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25678 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25679 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25680 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25681 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25682 /* If not immediate, fall back to neon_dyadic_i64_su.
25683 shl should accept I8 I16 I32 I64,
25684 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25685 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25686 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25687 /* Logic ops, types optional & ignored. */
25688 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25689 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25690 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25691 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25692 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25693 /* Bitfield ops, untyped. */
25694 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25695 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25696 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25697 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25698 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25699 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25700 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25701 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25702 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25703 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25704 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25705 back to neon_dyadic_if_su. */
25706 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25707 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25708 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25709 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25710 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25711 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25712 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25713 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25714 /* Comparison. Type I8 I16 I32 F32. */
25715 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25716 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25717 /* As above, D registers only. */
25718 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25719 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25720 /* Int and float variants, signedness unimportant. */
25721 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25722 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25723 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25724 /* Add/sub take types I8 I16 I32 I64 F32. */
25725 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25726 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25727 /* vtst takes sizes 8, 16, 32. */
25728 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25729 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25730 /* VMUL takes I8 I16 I32 F32 P8. */
25731 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25732 /* VQD{R}MULH takes S16 S32. */
25733 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25734 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25735 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25736 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25737 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25738 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25739 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25740 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25741 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25742 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25743 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25744 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25745 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25746 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25747 /* ARM v8.1 extension. */
25748 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25749 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25750 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25752 /* Two address, int/float. Types S8 S16 S32 F32. */
25753 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25754 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25756 /* Data processing with two registers and a shift amount. */
25757 /* Right shifts, and variants with rounding.
25758 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25759 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25760 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25761 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25762 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25763 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25764 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25765 /* Shift and insert. Sizes accepted 8 16 32 64. */
25766 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25767 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25768 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25769 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25770 /* Right shift immediate, saturating & narrowing, with rounding variants.
25771 Types accepted S16 S32 S64 U16 U32 U64. */
25772 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25773 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25774 /* As above, unsigned. Types accepted S16 S32 S64. */
25775 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25776 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25777 /* Right shift narrowing. Types accepted I16 I32 I64. */
25778 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25779 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25780 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25781 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25782 /* CVT with optional immediate for fixed-point variant. */
25783 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25785 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25787 /* Data processing, three registers of different lengths. */
25788 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25789 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25790 /* If not scalar, fall back to neon_dyadic_long.
25791 Vector types as above, scalar types S16 S32 U16 U32. */
25792 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25793 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25794 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25795 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25796 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25797 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25798 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25799 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25800 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25801 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25802 /* Saturating doubling multiplies. Types S16 S32. */
25803 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25804 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25805 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25806 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25807 S16 S32 U16 U32. */
25808 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25810 /* Extract. Size 8. */
25811 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25812 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25814 /* Two registers, miscellaneous. */
25815 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25816 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25817 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25818 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25819 /* Vector replicate. Sizes 8 16 32. */
25820 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25821 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25822 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25823 /* VMOVN. Types I16 I32 I64. */
25824 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25825 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25826 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25827 /* VQMOVUN. Types S16 S32 S64. */
25828 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25829 /* VZIP / VUZP. Sizes 8 16 32. */
25830 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25831 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25832 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25833 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25834 /* VQABS / VQNEG. Types S8 S16 S32. */
25835 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25836 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25837 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25838 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25839 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25840 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25841 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25842 /* Reciprocal estimates. Types U32 F16 F32. */
25843 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25844 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25845 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25846 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25847 /* VCLS. Types S8 S16 S32. */
25848 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25849 /* VCLZ. Types I8 I16 I32. */
25850 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25851 /* VCNT. Size 8. */
25852 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25853 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25854 /* Two address, untyped. */
25855 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25856 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25857 /* VTRN. Sizes 8 16 32. */
25858 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25859 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25861 /* Table lookup. Size 8. */
25862 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25863 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25865 #undef THUMB_VARIANT
25866 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25868 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25870 /* Neon element/structure load/store. */
25871 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25872 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25873 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25874 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25875 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25876 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25877 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25878 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25880 #undef THUMB_VARIANT
25881 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25883 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25884 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25885 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25886 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25887 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25888 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25889 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25890 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25891 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25892 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25894 #undef THUMB_VARIANT
25895 #define THUMB_VARIANT & fpu_vfp_ext_v3
25897 #define ARM_VARIANT & fpu_vfp_ext_v3
25899 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25900 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25901 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25902 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25903 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25904 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25905 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25906 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25907 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25910 #define ARM_VARIANT & fpu_vfp_ext_fma
25911 #undef THUMB_VARIANT
25912 #define THUMB_VARIANT & fpu_vfp_ext_fma
25913 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25914 VFP FMA variant; NEON and VFP FMA always includes the NEON
25915 FMA instructions. */
25916 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25917 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25918 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25920 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25921 the v form should always be used. */
25922 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25923 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25924 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25925 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25926 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25927 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25929 #undef THUMB_VARIANT
25931 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25933 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25934 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25935 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25936 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25937 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25938 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25939 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25940 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25943 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25945 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25946 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25947 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25948 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25949 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25950 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25951 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25952 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25953 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25954 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25955 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25956 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25957 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25958 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25959 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25960 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25961 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25962 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25963 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25964 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25965 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25966 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25967 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25968 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25969 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25970 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25971 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25972 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25973 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25974 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25975 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25976 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25977 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25978 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25979 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25980 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25981 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25982 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25983 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25984 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25985 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25986 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25987 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25988 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25989 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25990 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25991 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25992 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25993 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25994 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25995 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25996 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25997 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25999 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26000 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26012 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26013 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26014 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26015 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26026 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26034 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26046 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26047 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26048 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26049 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26050 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26051 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26054 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26056 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26057 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26058 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26059 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26060 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26061 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26062 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26063 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26064 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26065 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26066 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26067 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26068 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26069 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26070 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26071 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26072 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26073 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26074 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26075 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26076 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26077 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26078 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26079 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26080 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26081 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26082 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26083 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26084 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26085 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26086 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26087 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26088 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26089 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26090 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26091 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26092 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26093 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26095 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26096 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26097 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26098 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26099 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26100 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26101 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26102 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26103 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26104 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26105 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26106 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26109 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26111 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26112 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26113 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26114 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26115 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26116 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26117 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26118 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26119 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26120 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26121 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26122 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26123 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26124 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26125 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26126 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26127 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26128 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26129 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26131 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26132 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26172 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26173 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26174 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26175 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26176 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26177 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26178 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26179 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26180 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26181 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26182 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26183 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26184 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26185 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26186 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26187 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26188 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26189 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26190 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26191 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26192 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26193 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26194 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26195 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26196 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26197 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26198 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26199 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26200 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26201 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26202 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26203 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26204 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26205 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26206 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26207 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26208 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26209 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26210 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26211 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26212 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26213 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26214 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26215 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26216 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26217 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26218 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26219 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26220 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26221 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26222 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26223 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26224 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26225 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26226 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26227 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26228 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26229 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26230 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26231 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26232 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26233 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26234 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26235 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26236 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26237 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26238 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26239 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26240 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26241 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26242 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26243 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26244 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26245 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26246 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26247 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26249 /* ARMv8.5-A instructions. */
26251 #define ARM_VARIANT & arm_ext_sb
26252 #undef THUMB_VARIANT
26253 #define THUMB_VARIANT & arm_ext_sb
26254 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26257 #define ARM_VARIANT & arm_ext_predres
26258 #undef THUMB_VARIANT
26259 #define THUMB_VARIANT & arm_ext_predres
26260 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26261 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26262 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26264 /* ARMv8-M instructions. */
26266 #define ARM_VARIANT NULL
26267 #undef THUMB_VARIANT
26268 #define THUMB_VARIANT & arm_ext_v8m
26269 ToU("sg", e97fe97f
, 0, (), noargs
),
26270 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26271 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26272 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26273 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26274 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26275 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26277 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26278 instructions behave as nop if no VFP is present. */
26279 #undef THUMB_VARIANT
26280 #define THUMB_VARIANT & arm_ext_v8m_main
26281 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26282 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26284 /* Armv8.1-M Mainline instructions. */
26285 #undef THUMB_VARIANT
26286 #define THUMB_VARIANT & arm_ext_v8_1m_main
26287 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26288 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26289 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26290 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26291 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26292 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26293 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26294 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26295 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26297 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26298 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26299 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26300 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26301 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26303 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26304 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26305 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26307 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26308 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26310 #undef THUMB_VARIANT
26311 #define THUMB_VARIANT & mve_ext
26312 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26313 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26314 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26315 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26316 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26317 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26318 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26319 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26320 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26321 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26322 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26323 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26324 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26325 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26326 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26328 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26329 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26330 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26331 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26332 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26333 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26334 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26335 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26336 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26337 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26338 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26339 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26340 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26341 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26342 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26345 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26346 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26347 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26348 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26349 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26350 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26351 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26352 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26353 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26354 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26355 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26356 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26357 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26358 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26360 /* MVE and MVE FP only. */
26361 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26362 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26363 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26364 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26365 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26366 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26367 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26368 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26369 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26370 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26371 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26372 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26373 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26374 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26375 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26376 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26377 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26378 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26380 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26381 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26382 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26383 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26384 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26385 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26386 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26387 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26388 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26389 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26390 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26391 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26392 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26393 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26394 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26395 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26396 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26397 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26398 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26399 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26401 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26402 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26403 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26404 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26405 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26406 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26407 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26408 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26409 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26410 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26411 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26412 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26413 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26414 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26415 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26416 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26417 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26419 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26420 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26421 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26422 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26423 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26424 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26425 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26426 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26427 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26428 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26429 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26430 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26431 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26432 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26433 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26434 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26435 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26436 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26437 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26438 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26440 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26441 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26442 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26443 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26444 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26446 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26447 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26448 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26449 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26450 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26451 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26452 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26453 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26454 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26455 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26456 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26457 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26458 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26459 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26460 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26461 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26462 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26464 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26465 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26466 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26467 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26468 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26469 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26470 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26471 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26472 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26473 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26474 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26475 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26477 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26478 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26479 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26481 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26482 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26483 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26484 toU("lctp", _lctp
, 0, (), t_loloop
),
26486 #undef THUMB_VARIANT
26487 #define THUMB_VARIANT & mve_fp_ext
26488 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26489 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26490 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26491 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26492 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26493 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26494 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26495 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26498 #define ARM_VARIANT & fpu_vfp_ext_v1
26499 #undef THUMB_VARIANT
26500 #define THUMB_VARIANT & arm_ext_v6t2
26501 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26502 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26504 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26507 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26509 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26510 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26511 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26512 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26514 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26515 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26516 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26518 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26519 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26521 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26522 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26524 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26525 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26528 #define ARM_VARIANT & fpu_vfp_ext_v2
26530 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26531 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26532 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26533 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26536 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26537 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26538 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26539 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26540 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26541 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26542 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26545 #define ARM_VARIANT & fpu_neon_ext_v1
26546 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26547 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26548 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26549 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26550 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26551 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26552 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26553 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26554 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26555 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26556 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26557 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26558 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26559 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26560 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26561 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26562 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26563 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26564 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26565 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26566 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26567 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26568 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26569 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26570 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26571 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26572 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26573 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26574 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26575 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26576 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26577 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26578 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26579 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26580 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26581 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26582 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26585 #define ARM_VARIANT & arm_ext_v8_3
26586 #undef THUMB_VARIANT
26587 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26588 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26589 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26592 #define ARM_VARIANT &arm_ext_bf16
26593 #undef THUMB_VARIANT
26594 #define THUMB_VARIANT &arm_ext_bf16
26595 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26596 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26597 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26600 #define ARM_VARIANT &arm_ext_i8mm
26601 #undef THUMB_VARIANT
26602 #define THUMB_VARIANT &arm_ext_i8mm
26603 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26604 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26605 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26606 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26607 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26610 #undef THUMB_VARIANT
26611 #define THUMB_VARIANT &arm_ext_cde
26612 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26613 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26614 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26615 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26617 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26618 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26619 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26620 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26622 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26623 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26624 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26625 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26627 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26628 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26630 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26631 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26633 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26634 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26638 #undef THUMB_VARIANT
26670 /* MD interface: bits in the object file. */
26672 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26673 for use in the a.out file, and stores them in the array pointed to by buf.
26674 This knows about the endian-ness of the target machine and does
26675 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26676 2 (short) and 4 (long) Floating numbers are put out as a series of
26677 LITTLENUMS (shorts, here at least). */
26680 md_number_to_chars (char * buf
, valueT val
, int n
)
26682 if (target_big_endian
)
26683 number_to_chars_bigendian (buf
, val
, n
);
26685 number_to_chars_littleendian (buf
, val
, n
);
26689 md_chars_to_number (char * buf
, int n
)
26692 unsigned char * where
= (unsigned char *) buf
;
26694 if (target_big_endian
)
26699 result
|= (*where
++ & 255);
26707 result
|= (where
[n
] & 255);
26714 /* MD interface: Sections. */
26716 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26717 that an rs_machine_dependent frag may reach. */
26720 arm_frag_max_var (fragS
*fragp
)
26722 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26723 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26725 Note that we generate relaxable instructions even for cases that don't
26726 really need it, like an immediate that's a trivial constant. So we're
26727 overestimating the instruction size for some of those cases. Rather
26728 than putting more intelligence here, it would probably be better to
26729 avoid generating a relaxation frag in the first place when it can be
26730 determined up front that a short instruction will suffice. */
26732 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26736 /* Estimate the size of a frag before relaxing. Assume everything fits in
26740 md_estimate_size_before_relax (fragS
* fragp
,
26741 segT segtype ATTRIBUTE_UNUSED
)
26747 /* Convert a machine dependent frag. */
26750 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26752 unsigned long insn
;
26753 unsigned long old_op
;
26761 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26763 old_op
= bfd_get_16(abfd
, buf
);
26764 if (fragp
->fr_symbol
)
26766 exp
.X_op
= O_symbol
;
26767 exp
.X_add_symbol
= fragp
->fr_symbol
;
26771 exp
.X_op
= O_constant
;
26773 exp
.X_add_number
= fragp
->fr_offset
;
26774 opcode
= fragp
->fr_subtype
;
26777 case T_MNEM_ldr_pc
:
26778 case T_MNEM_ldr_pc2
:
26779 case T_MNEM_ldr_sp
:
26780 case T_MNEM_str_sp
:
26787 if (fragp
->fr_var
== 4)
26789 insn
= THUMB_OP32 (opcode
);
26790 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26792 insn
|= (old_op
& 0x700) << 4;
26796 insn
|= (old_op
& 7) << 12;
26797 insn
|= (old_op
& 0x38) << 13;
26799 insn
|= 0x00000c00;
26800 put_thumb32_insn (buf
, insn
);
26801 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26805 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26807 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26810 if (fragp
->fr_var
== 4)
26812 insn
= THUMB_OP32 (opcode
);
26813 insn
|= (old_op
& 0xf0) << 4;
26814 put_thumb32_insn (buf
, insn
);
26815 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26819 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26820 exp
.X_add_number
-= 4;
26828 if (fragp
->fr_var
== 4)
26830 int r0off
= (opcode
== T_MNEM_mov
26831 || opcode
== T_MNEM_movs
) ? 0 : 8;
26832 insn
= THUMB_OP32 (opcode
);
26833 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26834 insn
|= (old_op
& 0x700) << r0off
;
26835 put_thumb32_insn (buf
, insn
);
26836 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26840 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26845 if (fragp
->fr_var
== 4)
26847 insn
= THUMB_OP32(opcode
);
26848 put_thumb32_insn (buf
, insn
);
26849 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26852 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26856 if (fragp
->fr_var
== 4)
26858 insn
= THUMB_OP32(opcode
);
26859 insn
|= (old_op
& 0xf00) << 14;
26860 put_thumb32_insn (buf
, insn
);
26861 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26864 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26867 case T_MNEM_add_sp
:
26868 case T_MNEM_add_pc
:
26869 case T_MNEM_inc_sp
:
26870 case T_MNEM_dec_sp
:
26871 if (fragp
->fr_var
== 4)
26873 /* ??? Choose between add and addw. */
26874 insn
= THUMB_OP32 (opcode
);
26875 insn
|= (old_op
& 0xf0) << 4;
26876 put_thumb32_insn (buf
, insn
);
26877 if (opcode
== T_MNEM_add_pc
)
26878 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26880 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26883 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26891 if (fragp
->fr_var
== 4)
26893 insn
= THUMB_OP32 (opcode
);
26894 insn
|= (old_op
& 0xf0) << 4;
26895 insn
|= (old_op
& 0xf) << 16;
26896 put_thumb32_insn (buf
, insn
);
26897 if (insn
& (1 << 20))
26898 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26900 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26903 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26909 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26910 (enum bfd_reloc_code_real
) reloc_type
);
26911 fixp
->fx_file
= fragp
->fr_file
;
26912 fixp
->fx_line
= fragp
->fr_line
;
26913 fragp
->fr_fix
+= fragp
->fr_var
;
26915 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26916 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26917 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26918 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26921 /* Return the size of a relaxable immediate operand instruction.
26922 SHIFT and SIZE specify the form of the allowable immediate. */
26924 relax_immediate (fragS
*fragp
, int size
, int shift
)
26930 /* ??? Should be able to do better than this. */
26931 if (fragp
->fr_symbol
)
26934 low
= (1 << shift
) - 1;
26935 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26936 offset
= fragp
->fr_offset
;
26937 /* Force misaligned offsets to 32-bit variant. */
26940 if (offset
& ~mask
)
26945 /* Get the address of a symbol during relaxation. */
26947 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26953 sym
= fragp
->fr_symbol
;
26954 sym_frag
= symbol_get_frag (sym
);
26955 know (S_GET_SEGMENT (sym
) != absolute_section
26956 || sym_frag
== &zero_address_frag
);
26957 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26959 /* If frag has yet to be reached on this pass, assume it will
26960 move by STRETCH just as we did. If this is not so, it will
26961 be because some frag between grows, and that will force
26965 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26969 /* Adjust stretch for any alignment frag. Note that if have
26970 been expanding the earlier code, the symbol may be
26971 defined in what appears to be an earlier frag. FIXME:
26972 This doesn't handle the fr_subtype field, which specifies
26973 a maximum number of bytes to skip when doing an
26975 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26977 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26980 stretch
= - ((- stretch
)
26981 & ~ ((1 << (int) f
->fr_offset
) - 1));
26983 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26995 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26998 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27003 /* Assume worst case for symbols not known to be in the same section. */
27004 if (fragp
->fr_symbol
== NULL
27005 || !S_IS_DEFINED (fragp
->fr_symbol
)
27006 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27007 || S_IS_WEAK (fragp
->fr_symbol
))
27010 val
= relaxed_symbol_addr (fragp
, stretch
);
27011 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27012 addr
= (addr
+ 4) & ~3;
27013 /* Force misaligned targets to 32-bit variant. */
27017 if (val
< 0 || val
> 1020)
27022 /* Return the size of a relaxable add/sub immediate instruction. */
27024 relax_addsub (fragS
*fragp
, asection
*sec
)
27029 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27030 op
= bfd_get_16(sec
->owner
, buf
);
27031 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27032 return relax_immediate (fragp
, 8, 0);
27034 return relax_immediate (fragp
, 3, 0);
27037 /* Return TRUE iff the definition of symbol S could be pre-empted
27038 (overridden) at link or load time. */
27040 symbol_preemptible (symbolS
*s
)
27042 /* Weak symbols can always be pre-empted. */
27046 /* Non-global symbols cannot be pre-empted. */
27047 if (! S_IS_EXTERNAL (s
))
27051 /* In ELF, a global symbol can be marked protected, or private. In that
27052 case it can't be pre-empted (other definitions in the same link unit
27053 would violate the ODR). */
27054 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27058 /* Other global symbols might be pre-empted. */
27062 /* Return the size of a relaxable branch instruction. BITS is the
27063 size of the offset field in the narrow instruction. */
27066 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27072 /* Assume worst case for symbols not known to be in the same section. */
27073 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27074 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27075 || S_IS_WEAK (fragp
->fr_symbol
))
27079 /* A branch to a function in ARM state will require interworking. */
27080 if (S_IS_DEFINED (fragp
->fr_symbol
)
27081 && ARM_IS_FUNC (fragp
->fr_symbol
))
27085 if (symbol_preemptible (fragp
->fr_symbol
))
27088 val
= relaxed_symbol_addr (fragp
, stretch
);
27089 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27092 /* Offset is a signed value *2 */
27094 if (val
>= limit
|| val
< -limit
)
27100 /* Relax a machine dependent frag. This returns the amount by which
27101 the current size of the frag should change. */
27104 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27109 oldsize
= fragp
->fr_var
;
27110 switch (fragp
->fr_subtype
)
27112 case T_MNEM_ldr_pc2
:
27113 newsize
= relax_adr (fragp
, sec
, stretch
);
27115 case T_MNEM_ldr_pc
:
27116 case T_MNEM_ldr_sp
:
27117 case T_MNEM_str_sp
:
27118 newsize
= relax_immediate (fragp
, 8, 2);
27122 newsize
= relax_immediate (fragp
, 5, 2);
27126 newsize
= relax_immediate (fragp
, 5, 1);
27130 newsize
= relax_immediate (fragp
, 5, 0);
27133 newsize
= relax_adr (fragp
, sec
, stretch
);
27139 newsize
= relax_immediate (fragp
, 8, 0);
27142 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27145 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27147 case T_MNEM_add_sp
:
27148 case T_MNEM_add_pc
:
27149 newsize
= relax_immediate (fragp
, 8, 2);
27151 case T_MNEM_inc_sp
:
27152 case T_MNEM_dec_sp
:
27153 newsize
= relax_immediate (fragp
, 7, 2);
27159 newsize
= relax_addsub (fragp
, sec
);
27165 fragp
->fr_var
= newsize
;
27166 /* Freeze wide instructions that are at or before the same location as
27167 in the previous pass. This avoids infinite loops.
27168 Don't freeze them unconditionally because targets may be artificially
27169 misaligned by the expansion of preceding frags. */
27170 if (stretch
<= 0 && newsize
> 2)
27172 md_convert_frag (sec
->owner
, sec
, fragp
);
27176 return newsize
- oldsize
;
27179 /* Round up a section size to the appropriate boundary. */
27182 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27188 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27189 of an rs_align_code fragment. */
27192 arm_handle_align (fragS
* fragP
)
27194 static unsigned char const arm_noop
[2][2][4] =
27197 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27198 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27201 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27202 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27205 static unsigned char const thumb_noop
[2][2][2] =
27208 {0xc0, 0x46}, /* LE */
27209 {0x46, 0xc0}, /* BE */
27212 {0x00, 0xbf}, /* LE */
27213 {0xbf, 0x00} /* BE */
27216 static unsigned char const wide_thumb_noop
[2][4] =
27217 { /* Wide Thumb-2 */
27218 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27219 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27222 unsigned bytes
, fix
, noop_size
;
27224 const unsigned char * noop
;
27225 const unsigned char *narrow_noop
= NULL
;
27230 if (fragP
->fr_type
!= rs_align_code
)
27233 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27234 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27237 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27238 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27240 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27242 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27244 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27245 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27247 narrow_noop
= thumb_noop
[1][target_big_endian
];
27248 noop
= wide_thumb_noop
[target_big_endian
];
27251 noop
= thumb_noop
[0][target_big_endian
];
27259 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27260 ? selected_cpu
: arm_arch_none
,
27262 [target_big_endian
];
27269 fragP
->fr_var
= noop_size
;
27271 if (bytes
& (noop_size
- 1))
27273 fix
= bytes
& (noop_size
- 1);
27275 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27277 memset (p
, 0, fix
);
27284 if (bytes
& noop_size
)
27286 /* Insert a narrow noop. */
27287 memcpy (p
, narrow_noop
, noop_size
);
27289 bytes
-= noop_size
;
27293 /* Use wide noops for the remainder */
27297 while (bytes
>= noop_size
)
27299 memcpy (p
, noop
, noop_size
);
27301 bytes
-= noop_size
;
27305 fragP
->fr_fix
+= fix
;
27308 /* Called from md_do_align. Used to create an alignment
27309 frag in a code section. */
27312 arm_frag_align_code (int n
, int max
)
27316 /* We assume that there will never be a requirement
27317 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27318 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27323 _("alignments greater than %d bytes not supported in .text sections."),
27324 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27325 as_fatal ("%s", err_msg
);
27328 p
= frag_var (rs_align_code
,
27329 MAX_MEM_FOR_RS_ALIGN_CODE
,
27331 (relax_substateT
) max
,
27338 /* Perform target specific initialisation of a frag.
27339 Note - despite the name this initialisation is not done when the frag
27340 is created, but only when its type is assigned. A frag can be created
27341 and used a long time before its type is set, so beware of assuming that
27342 this initialisation is performed first. */
27346 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27348 /* Record whether this frag is in an ARM or a THUMB area. */
27349 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27352 #else /* OBJ_ELF is defined. */
27354 arm_init_frag (fragS
* fragP
, int max_chars
)
27356 bfd_boolean frag_thumb_mode
;
27358 /* If the current ARM vs THUMB mode has not already
27359 been recorded into this frag then do so now. */
27360 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27361 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27363 /* PR 21809: Do not set a mapping state for debug sections
27364 - it just confuses other tools. */
27365 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27368 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27370 /* Record a mapping symbol for alignment frags. We will delete this
27371 later if the alignment ends up empty. */
27372 switch (fragP
->fr_type
)
27375 case rs_align_test
:
27377 mapping_state_2 (MAP_DATA
, max_chars
);
27379 case rs_align_code
:
27380 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27387 /* When we change sections we need to issue a new mapping symbol. */
27390 arm_elf_change_section (void)
27392 /* Link an unlinked unwind index table section to the .text section. */
27393 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27394 && elf_linked_to_section (now_seg
) == NULL
)
27395 elf_linked_to_section (now_seg
) = text_section
;
27399 arm_elf_section_type (const char * str
, size_t len
)
27401 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27402 return SHT_ARM_EXIDX
;
27407 /* Code to deal with unwinding tables. */
27409 static void add_unwind_adjustsp (offsetT
);
27411 /* Generate any deferred unwind frame offset. */
27414 flush_pending_unwind (void)
27418 offset
= unwind
.pending_offset
;
27419 unwind
.pending_offset
= 0;
27421 add_unwind_adjustsp (offset
);
27424 /* Add an opcode to this list for this function. Two-byte opcodes should
27425 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27429 add_unwind_opcode (valueT op
, int length
)
27431 /* Add any deferred stack adjustment. */
27432 if (unwind
.pending_offset
)
27433 flush_pending_unwind ();
27435 unwind
.sp_restored
= 0;
27437 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27439 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27440 if (unwind
.opcodes
)
27441 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27442 unwind
.opcode_alloc
);
27444 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27449 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27451 unwind
.opcode_count
++;
27455 /* Add unwind opcodes to adjust the stack pointer. */
27458 add_unwind_adjustsp (offsetT offset
)
27462 if (offset
> 0x200)
27464 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27469 /* Long form: 0xb2, uleb128. */
27470 /* This might not fit in a word so add the individual bytes,
27471 remembering the list is built in reverse order. */
27472 o
= (valueT
) ((offset
- 0x204) >> 2);
27474 add_unwind_opcode (0, 1);
27476 /* Calculate the uleb128 encoding of the offset. */
27480 bytes
[n
] = o
& 0x7f;
27486 /* Add the insn. */
27488 add_unwind_opcode (bytes
[n
- 1], 1);
27489 add_unwind_opcode (0xb2, 1);
27491 else if (offset
> 0x100)
27493 /* Two short opcodes. */
27494 add_unwind_opcode (0x3f, 1);
27495 op
= (offset
- 0x104) >> 2;
27496 add_unwind_opcode (op
, 1);
27498 else if (offset
> 0)
27500 /* Short opcode. */
27501 op
= (offset
- 4) >> 2;
27502 add_unwind_opcode (op
, 1);
27504 else if (offset
< 0)
27507 while (offset
> 0x100)
27509 add_unwind_opcode (0x7f, 1);
27512 op
= ((offset
- 4) >> 2) | 0x40;
27513 add_unwind_opcode (op
, 1);
27517 /* Finish the list of unwind opcodes for this function. */
27520 finish_unwind_opcodes (void)
27524 if (unwind
.fp_used
)
27526 /* Adjust sp as necessary. */
27527 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27528 flush_pending_unwind ();
27530 /* After restoring sp from the frame pointer. */
27531 op
= 0x90 | unwind
.fp_reg
;
27532 add_unwind_opcode (op
, 1);
27535 flush_pending_unwind ();
27539 /* Start an exception table entry. If idx is nonzero this is an index table
27543 start_unwind_section (const segT text_seg
, int idx
)
27545 const char * text_name
;
27546 const char * prefix
;
27547 const char * prefix_once
;
27548 struct elf_section_match match
;
27556 prefix
= ELF_STRING_ARM_unwind
;
27557 prefix_once
= ELF_STRING_ARM_unwind_once
;
27558 type
= SHT_ARM_EXIDX
;
27562 prefix
= ELF_STRING_ARM_unwind_info
;
27563 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27564 type
= SHT_PROGBITS
;
27567 text_name
= segment_name (text_seg
);
27568 if (streq (text_name
, ".text"))
27571 if (strncmp (text_name
, ".gnu.linkonce.t.",
27572 strlen (".gnu.linkonce.t.")) == 0)
27574 prefix
= prefix_once
;
27575 text_name
+= strlen (".gnu.linkonce.t.");
27578 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27582 memset (&match
, 0, sizeof (match
));
27584 /* Handle COMDAT group. */
27585 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27587 match
.group_name
= elf_group_name (text_seg
);
27588 if (match
.group_name
== NULL
)
27590 as_bad (_("Group section `%s' has no group signature"),
27591 segment_name (text_seg
));
27592 ignore_rest_of_line ();
27595 flags
|= SHF_GROUP
;
27599 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27602 /* Set the section link for index tables. */
27604 elf_linked_to_section (now_seg
) = text_seg
;
27608 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27609 personality routine data. Returns zero, or the index table value for
27610 an inline entry. */
27613 create_unwind_entry (int have_data
)
27618 /* The current word of data. */
27620 /* The number of bytes left in this word. */
27623 finish_unwind_opcodes ();
27625 /* Remember the current text section. */
27626 unwind
.saved_seg
= now_seg
;
27627 unwind
.saved_subseg
= now_subseg
;
27629 start_unwind_section (now_seg
, 0);
27631 if (unwind
.personality_routine
== NULL
)
27633 if (unwind
.personality_index
== -2)
27636 as_bad (_("handlerdata in cantunwind frame"));
27637 return 1; /* EXIDX_CANTUNWIND. */
27640 /* Use a default personality routine if none is specified. */
27641 if (unwind
.personality_index
== -1)
27643 if (unwind
.opcode_count
> 3)
27644 unwind
.personality_index
= 1;
27646 unwind
.personality_index
= 0;
27649 /* Space for the personality routine entry. */
27650 if (unwind
.personality_index
== 0)
27652 if (unwind
.opcode_count
> 3)
27653 as_bad (_("too many unwind opcodes for personality routine 0"));
27657 /* All the data is inline in the index table. */
27660 while (unwind
.opcode_count
> 0)
27662 unwind
.opcode_count
--;
27663 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27667 /* Pad with "finish" opcodes. */
27669 data
= (data
<< 8) | 0xb0;
27676 /* We get two opcodes "free" in the first word. */
27677 size
= unwind
.opcode_count
- 2;
27681 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27682 if (unwind
.personality_index
!= -1)
27684 as_bad (_("attempt to recreate an unwind entry"));
27688 /* An extra byte is required for the opcode count. */
27689 size
= unwind
.opcode_count
+ 1;
27692 size
= (size
+ 3) >> 2;
27694 as_bad (_("too many unwind opcodes"));
27696 frag_align (2, 0, 0);
27697 record_alignment (now_seg
, 2);
27698 unwind
.table_entry
= expr_build_dot ();
27700 /* Allocate the table entry. */
27701 ptr
= frag_more ((size
<< 2) + 4);
27702 /* PR 13449: Zero the table entries in case some of them are not used. */
27703 memset (ptr
, 0, (size
<< 2) + 4);
27704 where
= frag_now_fix () - ((size
<< 2) + 4);
27706 switch (unwind
.personality_index
)
27709 /* ??? Should this be a PLT generating relocation? */
27710 /* Custom personality routine. */
27711 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27712 BFD_RELOC_ARM_PREL31
);
27717 /* Set the first byte to the number of additional words. */
27718 data
= size
> 0 ? size
- 1 : 0;
27722 /* ABI defined personality routines. */
27724 /* Three opcodes bytes are packed into the first word. */
27731 /* The size and first two opcode bytes go in the first word. */
27732 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27737 /* Should never happen. */
27741 /* Pack the opcodes into words (MSB first), reversing the list at the same
27743 while (unwind
.opcode_count
> 0)
27747 md_number_to_chars (ptr
, data
, 4);
27752 unwind
.opcode_count
--;
27754 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27757 /* Finish off the last word. */
27760 /* Pad with "finish" opcodes. */
27762 data
= (data
<< 8) | 0xb0;
27764 md_number_to_chars (ptr
, data
, 4);
27769 /* Add an empty descriptor if there is no user-specified data. */
27770 ptr
= frag_more (4);
27771 md_number_to_chars (ptr
, 0, 4);
27778 /* Initialize the DWARF-2 unwind information for this procedure. */
27781 tc_arm_frame_initial_instructions (void)
27783 cfi_add_CFA_def_cfa (REG_SP
, 0);
27785 #endif /* OBJ_ELF */
27787 /* Convert REGNAME to a DWARF-2 register number. */
27790 tc_arm_regname_to_dw2regnum (char *regname
)
27792 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27796 /* PR 16694: Allow VFP registers as well. */
27797 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27801 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27810 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27814 exp
.X_op
= O_secrel
;
27815 exp
.X_add_symbol
= symbol
;
27816 exp
.X_add_number
= 0;
27817 emit_expr (&exp
, size
);
27821 /* MD interface: Symbol and relocation handling. */
27823 /* Return the address within the segment that a PC-relative fixup is
27824 relative to. For ARM, PC-relative fixups applied to instructions
27825 are generally relative to the location of the fixup plus 8 bytes.
27826 Thumb branches are offset by 4, and Thumb loads relative to PC
27827 require special handling. */
27830 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27832 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27834 /* If this is pc-relative and we are going to emit a relocation
27835 then we just want to put out any pipeline compensation that the linker
27836 will need. Otherwise we want to use the calculated base.
27837 For WinCE we skip the bias for externals as well, since this
27838 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27840 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27841 || (arm_force_relocation (fixP
)
27843 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27849 switch (fixP
->fx_r_type
)
27851 /* PC relative addressing on the Thumb is slightly odd as the
27852 bottom two bits of the PC are forced to zero for the
27853 calculation. This happens *after* application of the
27854 pipeline offset. However, Thumb adrl already adjusts for
27855 this, so we need not do it again. */
27856 case BFD_RELOC_ARM_THUMB_ADD
:
27859 case BFD_RELOC_ARM_THUMB_OFFSET
:
27860 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27861 case BFD_RELOC_ARM_T32_ADD_PC12
:
27862 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27863 return (base
+ 4) & ~3;
27865 /* Thumb branches are simply offset by +4. */
27866 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27867 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27868 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27869 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27870 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27871 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27872 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27873 case BFD_RELOC_ARM_THUMB_BF17
:
27874 case BFD_RELOC_ARM_THUMB_BF19
:
27875 case BFD_RELOC_ARM_THUMB_BF13
:
27876 case BFD_RELOC_ARM_THUMB_LOOP12
:
27879 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27881 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27882 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27883 && ARM_IS_FUNC (fixP
->fx_addsy
)
27884 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27885 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27888 /* BLX is like branches above, but forces the low two bits of PC to
27890 case BFD_RELOC_THUMB_PCREL_BLX
:
27892 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27893 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27894 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27895 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27896 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27897 return (base
+ 4) & ~3;
27899 /* ARM mode branches are offset by +8. However, the Windows CE
27900 loader expects the relocation not to take this into account. */
27901 case BFD_RELOC_ARM_PCREL_BLX
:
27903 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27904 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27905 && ARM_IS_FUNC (fixP
->fx_addsy
)
27906 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27907 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27910 case BFD_RELOC_ARM_PCREL_CALL
:
27912 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27913 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27914 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27915 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27916 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27919 case BFD_RELOC_ARM_PCREL_BRANCH
:
27920 case BFD_RELOC_ARM_PCREL_JUMP
:
27921 case BFD_RELOC_ARM_PLT32
:
27923 /* When handling fixups immediately, because we have already
27924 discovered the value of a symbol, or the address of the frag involved
27925 we must account for the offset by +8, as the OS loader will never see the reloc.
27926 see fixup_segment() in write.c
27927 The S_IS_EXTERNAL test handles the case of global symbols.
27928 Those need the calculated base, not just the pipe compensation the linker will need. */
27930 && fixP
->fx_addsy
!= NULL
27931 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27932 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27940 /* ARM mode loads relative to PC are also offset by +8. Unlike
27941 branches, the Windows CE loader *does* expect the relocation
27942 to take this into account. */
27943 case BFD_RELOC_ARM_OFFSET_IMM
:
27944 case BFD_RELOC_ARM_OFFSET_IMM8
:
27945 case BFD_RELOC_ARM_HWLITERAL
:
27946 case BFD_RELOC_ARM_LITERAL
:
27947 case BFD_RELOC_ARM_CP_OFF_IMM
:
27951 /* Other PC-relative relocations are un-offset. */
27957 static bfd_boolean flag_warn_syms
= TRUE
;
27960 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27962 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27963 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27964 does mean that the resulting code might be very confusing to the reader.
27965 Also this warning can be triggered if the user omits an operand before
27966 an immediate address, eg:
27970 GAS treats this as an assignment of the value of the symbol foo to a
27971 symbol LDR, and so (without this code) it will not issue any kind of
27972 warning or error message.
27974 Note - ARM instructions are case-insensitive but the strings in the hash
27975 table are all stored in lower case, so we must first ensure that name is
27977 if (flag_warn_syms
&& arm_ops_hsh
)
27979 char * nbuf
= strdup (name
);
27982 for (p
= nbuf
; *p
; p
++)
27984 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27986 static struct hash_control
* already_warned
= NULL
;
27988 if (already_warned
== NULL
)
27989 already_warned
= hash_new ();
27990 /* Only warn about the symbol once. To keep the code
27991 simple we let hash_insert do the lookup for us. */
27992 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27993 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28002 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28003 Otherwise we have no need to default values of symbols. */
28006 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28009 if (name
[0] == '_' && name
[1] == 'G'
28010 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28014 if (symbol_find (name
))
28015 as_bad (_("GOT already in the symbol table"));
28017 GOT_symbol
= symbol_new (name
, undefined_section
,
28018 (valueT
) 0, & zero_address_frag
);
28028 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28029 computed as two separate immediate values, added together. We
28030 already know that this value cannot be computed by just one ARM
28033 static unsigned int
28034 validate_immediate_twopart (unsigned int val
,
28035 unsigned int * highpart
)
28040 for (i
= 0; i
< 32; i
+= 2)
28041 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28047 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28049 else if (a
& 0xff0000)
28051 if (a
& 0xff000000)
28053 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28057 gas_assert (a
& 0xff000000);
28058 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28061 return (a
& 0xff) | (i
<< 7);
28068 validate_offset_imm (unsigned int val
, int hwse
)
28070 if ((hwse
&& val
> 255) || val
> 4095)
28075 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28076 negative immediate constant by altering the instruction. A bit of
28081 by inverting the second operand, and
28084 by negating the second operand. */
28087 negate_data_op (unsigned long * instruction
,
28088 unsigned long value
)
28091 unsigned long negated
, inverted
;
28093 negated
= encode_arm_immediate (-value
);
28094 inverted
= encode_arm_immediate (~value
);
28096 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28099 /* First negates. */
28100 case OPCODE_SUB
: /* ADD <-> SUB */
28101 new_inst
= OPCODE_ADD
;
28106 new_inst
= OPCODE_SUB
;
28110 case OPCODE_CMP
: /* CMP <-> CMN */
28111 new_inst
= OPCODE_CMN
;
28116 new_inst
= OPCODE_CMP
;
28120 /* Now Inverted ops. */
28121 case OPCODE_MOV
: /* MOV <-> MVN */
28122 new_inst
= OPCODE_MVN
;
28127 new_inst
= OPCODE_MOV
;
28131 case OPCODE_AND
: /* AND <-> BIC */
28132 new_inst
= OPCODE_BIC
;
28137 new_inst
= OPCODE_AND
;
28141 case OPCODE_ADC
: /* ADC <-> SBC */
28142 new_inst
= OPCODE_SBC
;
28147 new_inst
= OPCODE_ADC
;
28151 /* We cannot do anything. */
28156 if (value
== (unsigned) FAIL
)
28159 *instruction
&= OPCODE_MASK
;
28160 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28164 /* Like negate_data_op, but for Thumb-2. */
28166 static unsigned int
28167 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
28171 unsigned int negated
, inverted
;
28173 negated
= encode_thumb32_immediate (-value
);
28174 inverted
= encode_thumb32_immediate (~value
);
28176 rd
= (*instruction
>> 8) & 0xf;
28177 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28180 /* ADD <-> SUB. Includes CMP <-> CMN. */
28181 case T2_OPCODE_SUB
:
28182 new_inst
= T2_OPCODE_ADD
;
28186 case T2_OPCODE_ADD
:
28187 new_inst
= T2_OPCODE_SUB
;
28191 /* ORR <-> ORN. Includes MOV <-> MVN. */
28192 case T2_OPCODE_ORR
:
28193 new_inst
= T2_OPCODE_ORN
;
28197 case T2_OPCODE_ORN
:
28198 new_inst
= T2_OPCODE_ORR
;
28202 /* AND <-> BIC. TST has no inverted equivalent. */
28203 case T2_OPCODE_AND
:
28204 new_inst
= T2_OPCODE_BIC
;
28211 case T2_OPCODE_BIC
:
28212 new_inst
= T2_OPCODE_AND
;
28217 case T2_OPCODE_ADC
:
28218 new_inst
= T2_OPCODE_SBC
;
28222 case T2_OPCODE_SBC
:
28223 new_inst
= T2_OPCODE_ADC
;
28227 /* We cannot do anything. */
28232 if (value
== (unsigned int)FAIL
)
28235 *instruction
&= T2_OPCODE_MASK
;
28236 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28240 /* Read a 32-bit thumb instruction from buf. */
28242 static unsigned long
28243 get_thumb32_insn (char * buf
)
28245 unsigned long insn
;
28246 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28247 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28252 /* We usually want to set the low bit on the address of thumb function
28253 symbols. In particular .word foo - . should have the low bit set.
28254 Generic code tries to fold the difference of two symbols to
28255 a constant. Prevent this and force a relocation when the first symbols
28256 is a thumb function. */
28259 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28261 if (op
== O_subtract
28262 && l
->X_op
== O_symbol
28263 && r
->X_op
== O_symbol
28264 && THUMB_IS_FUNC (l
->X_add_symbol
))
28266 l
->X_op
= O_subtract
;
28267 l
->X_op_symbol
= r
->X_add_symbol
;
28268 l
->X_add_number
-= r
->X_add_number
;
28272 /* Process as normal. */
28276 /* Encode Thumb2 unconditional branches and calls. The encoding
28277 for the 2 are identical for the immediate values. */
28280 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28282 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28285 addressT S
, I1
, I2
, lo
, hi
;
28287 S
= (value
>> 24) & 0x01;
28288 I1
= (value
>> 23) & 0x01;
28289 I2
= (value
>> 22) & 0x01;
28290 hi
= (value
>> 12) & 0x3ff;
28291 lo
= (value
>> 1) & 0x7ff;
28292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28293 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28294 newval
|= (S
<< 10) | hi
;
28295 newval2
&= ~T2I1I2MASK
;
28296 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28297 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28298 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28302 md_apply_fix (fixS
* fixP
,
28306 offsetT value
= * valP
;
28308 unsigned int newimm
;
28309 unsigned long temp
;
28311 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28313 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28315 /* Note whether this will delete the relocation. */
28317 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28320 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28321 consistency with the behaviour on 32-bit hosts. Remember value
28323 value
&= 0xffffffff;
28324 value
^= 0x80000000;
28325 value
-= 0x80000000;
28328 fixP
->fx_addnumber
= value
;
28330 /* Same treatment for fixP->fx_offset. */
28331 fixP
->fx_offset
&= 0xffffffff;
28332 fixP
->fx_offset
^= 0x80000000;
28333 fixP
->fx_offset
-= 0x80000000;
28335 switch (fixP
->fx_r_type
)
28337 case BFD_RELOC_NONE
:
28338 /* This will need to go in the object file. */
28342 case BFD_RELOC_ARM_IMMEDIATE
:
28343 /* We claim that this fixup has been processed here,
28344 even if in fact we generate an error because we do
28345 not have a reloc for it, so tc_gen_reloc will reject it. */
28348 if (fixP
->fx_addsy
)
28350 const char *msg
= 0;
28352 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28353 msg
= _("undefined symbol %s used as an immediate value");
28354 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28355 msg
= _("symbol %s is in a different section");
28356 else if (S_IS_WEAK (fixP
->fx_addsy
))
28357 msg
= _("symbol %s is weak and may be overridden later");
28361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28362 msg
, S_GET_NAME (fixP
->fx_addsy
));
28367 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28369 /* If the offset is negative, we should use encoding A2 for ADR. */
28370 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
28371 newimm
= negate_data_op (&temp
, value
);
28374 newimm
= encode_arm_immediate (value
);
28376 /* If the instruction will fail, see if we can fix things up by
28377 changing the opcode. */
28378 if (newimm
== (unsigned int) FAIL
)
28379 newimm
= negate_data_op (&temp
, value
);
28380 /* MOV accepts both ARM modified immediate (A1 encoding) and
28381 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28382 When disassembling, MOV is preferred when there is no encoding
28384 if (newimm
== (unsigned int) FAIL
28385 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28386 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28387 && !((temp
>> SBIT_SHIFT
) & 0x1)
28388 && value
>= 0 && value
<= 0xffff)
28390 /* Clear bits[23:20] to change encoding from A1 to A2. */
28391 temp
&= 0xff0fffff;
28392 /* Encoding high 4bits imm. Code below will encode the remaining
28394 temp
|= (value
& 0x0000f000) << 4;
28395 newimm
= value
& 0x00000fff;
28399 if (newimm
== (unsigned int) FAIL
)
28401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28402 _("invalid constant (%lx) after fixup"),
28403 (unsigned long) value
);
28407 newimm
|= (temp
& 0xfffff000);
28408 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28411 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28413 unsigned int highpart
= 0;
28414 unsigned int newinsn
= 0xe1a00000; /* nop. */
28416 if (fixP
->fx_addsy
)
28418 const char *msg
= 0;
28420 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28421 msg
= _("undefined symbol %s used as an immediate value");
28422 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28423 msg
= _("symbol %s is in a different section");
28424 else if (S_IS_WEAK (fixP
->fx_addsy
))
28425 msg
= _("symbol %s is weak and may be overridden later");
28429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28430 msg
, S_GET_NAME (fixP
->fx_addsy
));
28435 newimm
= encode_arm_immediate (value
);
28436 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28438 /* If the instruction will fail, see if we can fix things up by
28439 changing the opcode. */
28440 if (newimm
== (unsigned int) FAIL
28441 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28443 /* No ? OK - try using two ADD instructions to generate
28445 newimm
= validate_immediate_twopart (value
, & highpart
);
28447 /* Yes - then make sure that the second instruction is
28449 if (newimm
!= (unsigned int) FAIL
)
28451 /* Still No ? Try using a negated value. */
28452 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28453 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28454 /* Otherwise - give up. */
28457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28458 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28463 /* Replace the first operand in the 2nd instruction (which
28464 is the PC) with the destination register. We have
28465 already added in the PC in the first instruction and we
28466 do not want to do it again. */
28467 newinsn
&= ~ 0xf0000;
28468 newinsn
|= ((newinsn
& 0x0f000) << 4);
28471 newimm
|= (temp
& 0xfffff000);
28472 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28474 highpart
|= (newinsn
& 0xfffff000);
28475 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28479 case BFD_RELOC_ARM_OFFSET_IMM
:
28480 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28482 /* Fall through. */
28484 case BFD_RELOC_ARM_LITERAL
:
28490 if (validate_offset_imm (value
, 0) == FAIL
)
28492 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28494 _("invalid literal constant: pool needs to be closer"));
28496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28497 _("bad immediate value for offset (%ld)"),
28502 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28504 newval
&= 0xfffff000;
28507 newval
&= 0xff7ff000;
28508 newval
|= value
| (sign
? INDEX_UP
: 0);
28510 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28513 case BFD_RELOC_ARM_OFFSET_IMM8
:
28514 case BFD_RELOC_ARM_HWLITERAL
:
28520 if (validate_offset_imm (value
, 1) == FAIL
)
28522 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28524 _("invalid literal constant: pool needs to be closer"));
28526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28527 _("bad immediate value for 8-bit offset (%ld)"),
28532 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28534 newval
&= 0xfffff0f0;
28537 newval
&= 0xff7ff0f0;
28538 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28540 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28543 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28544 if (value
< 0 || value
> 1020 || value
% 4 != 0)
28545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28546 _("bad immediate value for offset (%ld)"), (long) value
);
28549 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28551 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28554 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28555 /* This is a complicated relocation used for all varieties of Thumb32
28556 load/store instruction with immediate offset:
28558 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28559 *4, optional writeback(W)
28560 (doubleword load/store)
28562 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28563 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28564 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28565 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28566 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28568 Uppercase letters indicate bits that are already encoded at
28569 this point. Lowercase letters are our problem. For the
28570 second block of instructions, the secondary opcode nybble
28571 (bits 8..11) is present, and bit 23 is zero, even if this is
28572 a PC-relative operation. */
28573 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28575 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28577 if ((newval
& 0xf0000000) == 0xe0000000)
28579 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28581 newval
|= (1 << 23);
28584 if (value
% 4 != 0)
28586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28587 _("offset not a multiple of 4"));
28593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28594 _("offset out of range"));
28599 else if ((newval
& 0x000f0000) == 0x000f0000)
28601 /* PC-relative, 12-bit offset. */
28603 newval
|= (1 << 23);
28608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28609 _("offset out of range"));
28614 else if ((newval
& 0x00000100) == 0x00000100)
28616 /* Writeback: 8-bit, +/- offset. */
28618 newval
|= (1 << 9);
28623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28624 _("offset out of range"));
28629 else if ((newval
& 0x00000f00) == 0x00000e00)
28631 /* T-instruction: positive 8-bit offset. */
28632 if (value
< 0 || value
> 0xff)
28634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28635 _("offset out of range"));
28643 /* Positive 12-bit or negative 8-bit offset. */
28647 newval
|= (1 << 23);
28657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28658 _("offset out of range"));
28665 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28666 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28669 case BFD_RELOC_ARM_SHIFT_IMM
:
28670 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28671 if (((unsigned long) value
) > 32
28673 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28676 _("shift expression is too large"));
28681 /* Shifts of zero must be done as lsl. */
28683 else if (value
== 32)
28685 newval
&= 0xfffff07f;
28686 newval
|= (value
& 0x1f) << 7;
28687 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28690 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28691 case BFD_RELOC_ARM_T32_ADD_IMM
:
28692 case BFD_RELOC_ARM_T32_IMM12
:
28693 case BFD_RELOC_ARM_T32_ADD_PC12
:
28694 /* We claim that this fixup has been processed here,
28695 even if in fact we generate an error because we do
28696 not have a reloc for it, so tc_gen_reloc will reject it. */
28700 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28703 _("undefined symbol %s used as an immediate value"),
28704 S_GET_NAME (fixP
->fx_addsy
));
28708 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28710 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28713 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28714 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28715 Thumb2 modified immediate encoding (T2). */
28716 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28717 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28719 newimm
= encode_thumb32_immediate (value
);
28720 if (newimm
== (unsigned int) FAIL
)
28721 newimm
= thumb32_negate_data_op (&newval
, value
);
28723 if (newimm
== (unsigned int) FAIL
)
28725 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28727 /* Turn add/sum into addw/subw. */
28728 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28729 newval
= (newval
& 0xfeffffff) | 0x02000000;
28730 /* No flat 12-bit imm encoding for addsw/subsw. */
28731 if ((newval
& 0x00100000) == 0)
28733 /* 12 bit immediate for addw/subw. */
28737 newval
^= 0x00a00000;
28740 newimm
= (unsigned int) FAIL
;
28747 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28748 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28749 disassembling, MOV is preferred when there is no encoding
28751 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28752 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28753 but with the Rn field [19:16] set to 1111. */
28754 && (((newval
>> 16) & 0xf) == 0xf)
28755 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28756 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28757 && value
>= 0 && value
<= 0xffff)
28759 /* Toggle bit[25] to change encoding from T2 to T3. */
28761 /* Clear bits[19:16]. */
28762 newval
&= 0xfff0ffff;
28763 /* Encoding high 4bits imm. Code below will encode the
28764 remaining low 12bits. */
28765 newval
|= (value
& 0x0000f000) << 4;
28766 newimm
= value
& 0x00000fff;
28771 if (newimm
== (unsigned int)FAIL
)
28773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28774 _("invalid constant (%lx) after fixup"),
28775 (unsigned long) value
);
28779 newval
|= (newimm
& 0x800) << 15;
28780 newval
|= (newimm
& 0x700) << 4;
28781 newval
|= (newimm
& 0x0ff);
28783 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28784 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28787 case BFD_RELOC_ARM_SMC
:
28788 if (((unsigned long) value
) > 0xf)
28789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28790 _("invalid smc expression"));
28792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28793 newval
|= (value
& 0xf);
28794 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28797 case BFD_RELOC_ARM_HVC
:
28798 if (((unsigned long) value
) > 0xffff)
28799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28800 _("invalid hvc expression"));
28801 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28802 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28803 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28806 case BFD_RELOC_ARM_SWI
:
28807 if (fixP
->tc_fix_data
!= 0)
28809 if (((unsigned long) value
) > 0xff)
28810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28811 _("invalid swi expression"));
28812 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28814 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28818 if (((unsigned long) value
) > 0x00ffffff)
28819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28820 _("invalid swi expression"));
28821 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28823 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28827 case BFD_RELOC_ARM_MULTI
:
28828 if (((unsigned long) value
) > 0xffff)
28829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28830 _("invalid expression in load/store multiple"));
28831 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28832 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28836 case BFD_RELOC_ARM_PCREL_CALL
:
28838 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28840 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28841 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28842 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28843 /* Flip the bl to blx. This is a simple flip
28844 bit here because we generate PCREL_CALL for
28845 unconditional bls. */
28847 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28848 newval
= newval
| 0x10000000;
28849 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28855 goto arm_branch_common
;
28857 case BFD_RELOC_ARM_PCREL_JUMP
:
28858 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28860 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28861 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28862 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28864 /* This would map to a bl<cond>, b<cond>,
28865 b<always> to a Thumb function. We
28866 need to force a relocation for this particular
28868 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28871 /* Fall through. */
28873 case BFD_RELOC_ARM_PLT32
:
28875 case BFD_RELOC_ARM_PCREL_BRANCH
:
28877 goto arm_branch_common
;
28879 case BFD_RELOC_ARM_PCREL_BLX
:
28882 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28884 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28885 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28886 && ARM_IS_FUNC (fixP
->fx_addsy
))
28888 /* Flip the blx to a bl and warn. */
28889 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28890 newval
= 0xeb000000;
28891 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28892 _("blx to '%s' an ARM ISA state function changed to bl"),
28894 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28900 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28901 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28905 /* We are going to store value (shifted right by two) in the
28906 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28907 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28911 _("misaligned branch destination"));
28912 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28913 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28918 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28919 newval
|= (value
>> 2) & 0x00ffffff;
28920 /* Set the H bit on BLX instructions. */
28924 newval
|= 0x01000000;
28926 newval
&= ~0x01000000;
28928 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28932 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28933 /* CBZ can only branch forward. */
28935 /* Attempts to use CBZ to branch to the next instruction
28936 (which, strictly speaking, are prohibited) will be turned into
28939 FIXME: It may be better to remove the instruction completely and
28940 perform relaxation. */
28943 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28944 newval
= 0xbf00; /* NOP encoding T1 */
28945 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28952 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28954 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28955 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28956 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28961 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28962 if (out_of_range_p (value
, 8))
28963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28965 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28967 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28968 newval
|= (value
& 0x1ff) >> 1;
28969 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28973 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28974 if (out_of_range_p (value
, 11))
28975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28977 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28979 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28980 newval
|= (value
& 0xfff) >> 1;
28981 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28985 /* This relocation is misnamed, it should be BRANCH21. */
28986 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28988 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28989 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28990 && ARM_IS_FUNC (fixP
->fx_addsy
)
28991 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28993 /* Force a relocation for a branch 20 bits wide. */
28996 if (out_of_range_p (value
, 20))
28997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28998 _("conditional branch out of range"));
29000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29003 addressT S
, J1
, J2
, lo
, hi
;
29005 S
= (value
& 0x00100000) >> 20;
29006 J2
= (value
& 0x00080000) >> 19;
29007 J1
= (value
& 0x00040000) >> 18;
29008 hi
= (value
& 0x0003f000) >> 12;
29009 lo
= (value
& 0x00000ffe) >> 1;
29011 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29012 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29013 newval
|= (S
<< 10) | hi
;
29014 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29015 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29016 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29020 case BFD_RELOC_THUMB_PCREL_BLX
:
29021 /* If there is a blx from a thumb state function to
29022 another thumb function flip this to a bl and warn
29026 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29027 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29028 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29030 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29031 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29032 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29034 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29035 newval
= newval
| 0x1000;
29036 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29037 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29042 goto thumb_bl_common
;
29044 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29045 /* A bl from Thumb state ISA to an internal ARM state function
29046 is converted to a blx. */
29048 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29049 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29050 && ARM_IS_FUNC (fixP
->fx_addsy
)
29051 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29053 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29054 newval
= newval
& ~0x1000;
29055 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29056 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29062 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29063 /* For a BLX instruction, make sure that the relocation is rounded up
29064 to a word boundary. This follows the semantics of the instruction
29065 which specifies that bit 1 of the target address will come from bit
29066 1 of the base address. */
29067 value
= (value
+ 3) & ~ 3;
29070 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29071 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29072 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29075 if (out_of_range_p (value
, 22))
29077 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29079 else if (out_of_range_p (value
, 24))
29080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29081 _("Thumb2 branch out of range"));
29084 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29085 encode_thumb2_b_bl_offset (buf
, value
);
29089 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29090 if (out_of_range_p (value
, 24))
29091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29093 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29094 encode_thumb2_b_bl_offset (buf
, value
);
29099 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29105 md_number_to_chars (buf
, value
, 2);
29109 case BFD_RELOC_ARM_TLS_CALL
:
29110 case BFD_RELOC_ARM_THM_TLS_CALL
:
29111 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29112 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29113 case BFD_RELOC_ARM_TLS_GOTDESC
:
29114 case BFD_RELOC_ARM_TLS_GD32
:
29115 case BFD_RELOC_ARM_TLS_LE32
:
29116 case BFD_RELOC_ARM_TLS_IE32
:
29117 case BFD_RELOC_ARM_TLS_LDM32
:
29118 case BFD_RELOC_ARM_TLS_LDO32
:
29119 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29122 /* Same handling as above, but with the arm_fdpic guard. */
29123 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29124 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29125 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29128 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29133 _("Relocation supported only in FDPIC mode"));
29137 case BFD_RELOC_ARM_GOT32
:
29138 case BFD_RELOC_ARM_GOTOFF
:
29141 case BFD_RELOC_ARM_GOT_PREL
:
29142 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29143 md_number_to_chars (buf
, value
, 4);
29146 case BFD_RELOC_ARM_TARGET2
:
29147 /* TARGET2 is not partial-inplace, so we need to write the
29148 addend here for REL targets, because it won't be written out
29149 during reloc processing later. */
29150 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29151 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29154 /* Relocations for FDPIC. */
29155 case BFD_RELOC_ARM_GOTFUNCDESC
:
29156 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29157 case BFD_RELOC_ARM_FUNCDESC
:
29160 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29161 md_number_to_chars (buf
, 0, 4);
29165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29166 _("Relocation supported only in FDPIC mode"));
29171 case BFD_RELOC_RVA
:
29173 case BFD_RELOC_ARM_TARGET1
:
29174 case BFD_RELOC_ARM_ROSEGREL32
:
29175 case BFD_RELOC_ARM_SBREL32
:
29176 case BFD_RELOC_32_PCREL
:
29178 case BFD_RELOC_32_SECREL
:
29180 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29182 /* For WinCE we only do this for pcrel fixups. */
29183 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29185 md_number_to_chars (buf
, value
, 4);
29189 case BFD_RELOC_ARM_PREL31
:
29190 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29192 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29193 if ((value
^ (value
>> 1)) & 0x40000000)
29195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29196 _("rel31 relocation overflow"));
29198 newval
|= value
& 0x7fffffff;
29199 md_number_to_chars (buf
, newval
, 4);
29204 case BFD_RELOC_ARM_CP_OFF_IMM
:
29205 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29206 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29207 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29208 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29210 newval
= get_thumb32_insn (buf
);
29211 if ((newval
& 0x0f200f00) == 0x0d000900)
29213 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29214 has permitted values that are multiples of 2, in the range 0
29216 if (value
< -510 || value
> 510 || (value
& 1))
29217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29218 _("co-processor offset out of range"));
29220 else if ((newval
& 0xfe001f80) == 0xec000f80)
29222 if (value
< -511 || value
> 512 || (value
& 3))
29223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29224 _("co-processor offset out of range"));
29226 else if (value
< -1023 || value
> 1023 || (value
& 3))
29227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29228 _("co-processor offset out of range"));
29233 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29234 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29235 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29237 newval
= get_thumb32_insn (buf
);
29240 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29241 newval
&= 0xffffff80;
29243 newval
&= 0xffffff00;
29247 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29248 newval
&= 0xff7fff80;
29250 newval
&= 0xff7fff00;
29251 if ((newval
& 0x0f200f00) == 0x0d000900)
29253 /* This is a fp16 vstr/vldr.
29255 It requires the immediate offset in the instruction is shifted
29256 left by 1 to be a half-word offset.
29258 Here, left shift by 1 first, and later right shift by 2
29259 should get the right offset. */
29262 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29264 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29265 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29266 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29268 put_thumb32_insn (buf
, newval
);
29271 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29272 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29273 if (value
< -255 || value
> 255)
29274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29275 _("co-processor offset out of range"));
29277 goto cp_off_common
;
29279 case BFD_RELOC_ARM_THUMB_OFFSET
:
29280 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29281 /* Exactly what ranges, and where the offset is inserted depends
29282 on the type of instruction, we can establish this from the
29284 switch (newval
>> 12)
29286 case 4: /* PC load. */
29287 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29288 forced to zero for these loads; md_pcrel_from has already
29289 compensated for this. */
29291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29292 _("invalid offset, target not word aligned (0x%08lX)"),
29293 (((unsigned long) fixP
->fx_frag
->fr_address
29294 + (unsigned long) fixP
->fx_where
) & ~3)
29295 + (unsigned long) value
);
29296 else if (get_recorded_alignment (seg
) < 2)
29297 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29298 _("section does not have enough alignment to ensure safe PC-relative loads"));
29300 if (value
& ~0x3fc)
29301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29302 _("invalid offset, value too big (0x%08lX)"),
29305 newval
|= value
>> 2;
29308 case 9: /* SP load/store. */
29309 if (value
& ~0x3fc)
29310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29311 _("invalid offset, value too big (0x%08lX)"),
29313 newval
|= value
>> 2;
29316 case 6: /* Word load/store. */
29318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29319 _("invalid offset, value too big (0x%08lX)"),
29321 newval
|= value
<< 4; /* 6 - 2. */
29324 case 7: /* Byte load/store. */
29326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29327 _("invalid offset, value too big (0x%08lX)"),
29329 newval
|= value
<< 6;
29332 case 8: /* Halfword load/store. */
29334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29335 _("invalid offset, value too big (0x%08lX)"),
29337 newval
|= value
<< 5; /* 6 - 1. */
29341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29342 "Unable to process relocation for thumb opcode: %lx",
29343 (unsigned long) newval
);
29346 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29349 case BFD_RELOC_ARM_THUMB_ADD
:
29350 /* This is a complicated relocation, since we use it for all of
29351 the following immediate relocations:
29355 9bit ADD/SUB SP word-aligned
29356 10bit ADD PC/SP word-aligned
29358 The type of instruction being processed is encoded in the
29365 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29367 int rd
= (newval
>> 4) & 0xf;
29368 int rs
= newval
& 0xf;
29369 int subtract
= !!(newval
& 0x8000);
29371 /* Check for HI regs, only very restricted cases allowed:
29372 Adjusting SP, and using PC or SP to get an address. */
29373 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29374 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29376 _("invalid Hi register with immediate"));
29378 /* If value is negative, choose the opposite instruction. */
29382 subtract
= !subtract
;
29384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29385 _("immediate value out of range"));
29390 if (value
& ~0x1fc)
29391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29392 _("invalid immediate for stack address calculation"));
29393 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29394 newval
|= value
>> 2;
29396 else if (rs
== REG_PC
|| rs
== REG_SP
)
29398 /* PR gas/18541. If the addition is for a defined symbol
29399 within range of an ADR instruction then accept it. */
29402 && fixP
->fx_addsy
!= NULL
)
29406 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29407 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29408 || S_IS_WEAK (fixP
->fx_addsy
))
29410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29411 _("address calculation needs a strongly defined nearby symbol"));
29415 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29417 /* Round up to the next 4-byte boundary. */
29422 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29427 _("symbol too far away"));
29437 if (subtract
|| value
& ~0x3fc)
29438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29439 _("invalid immediate for address calculation (value = 0x%08lX)"),
29440 (unsigned long) (subtract
? - value
: value
));
29441 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29443 newval
|= value
>> 2;
29448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29449 _("immediate value out of range"));
29450 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29451 newval
|= (rd
<< 8) | value
;
29456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29457 _("immediate value out of range"));
29458 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29459 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29462 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29465 case BFD_RELOC_ARM_THUMB_IMM
:
29466 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29467 if (value
< 0 || value
> 255)
29468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29469 _("invalid immediate: %ld is out of range"),
29472 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29475 case BFD_RELOC_ARM_THUMB_SHIFT
:
29476 /* 5bit shift value (0..32). LSL cannot take 32. */
29477 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29478 temp
= newval
& 0xf800;
29479 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29481 _("invalid shift value: %ld"), (long) value
);
29482 /* Shifts of zero must be encoded as LSL. */
29484 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29485 /* Shifts of 32 are encoded as zero. */
29486 else if (value
== 32)
29488 newval
|= value
<< 6;
29489 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29492 case BFD_RELOC_VTABLE_INHERIT
:
29493 case BFD_RELOC_VTABLE_ENTRY
:
29497 case BFD_RELOC_ARM_MOVW
:
29498 case BFD_RELOC_ARM_MOVT
:
29499 case BFD_RELOC_ARM_THUMB_MOVW
:
29500 case BFD_RELOC_ARM_THUMB_MOVT
:
29501 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29503 /* REL format relocations are limited to a 16-bit addend. */
29504 if (!fixP
->fx_done
)
29506 if (value
< -0x8000 || value
> 0x7fff)
29507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29508 _("offset out of range"));
29510 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29511 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29516 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29517 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29519 newval
= get_thumb32_insn (buf
);
29520 newval
&= 0xfbf08f00;
29521 newval
|= (value
& 0xf000) << 4;
29522 newval
|= (value
& 0x0800) << 15;
29523 newval
|= (value
& 0x0700) << 4;
29524 newval
|= (value
& 0x00ff);
29525 put_thumb32_insn (buf
, newval
);
29529 newval
= md_chars_to_number (buf
, 4);
29530 newval
&= 0xfff0f000;
29531 newval
|= value
& 0x0fff;
29532 newval
|= (value
& 0xf000) << 4;
29533 md_number_to_chars (buf
, newval
, 4);
29538 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29539 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29540 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29541 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29542 gas_assert (!fixP
->fx_done
);
29545 bfd_boolean is_mov
;
29546 bfd_vma encoded_addend
= value
;
29548 /* Check that addend can be encoded in instruction. */
29549 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
29550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29551 _("the offset 0x%08lX is not representable"),
29552 (unsigned long) encoded_addend
);
29554 /* Extract the instruction. */
29555 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29556 is_mov
= (insn
& 0xf800) == 0x2000;
29561 if (!seg
->use_rela_p
)
29562 insn
|= encoded_addend
;
29568 /* Extract the instruction. */
29569 /* Encoding is the following
29574 /* The following conditions must be true :
29579 rd
= (insn
>> 4) & 0xf;
29581 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29583 _("Unable to process relocation for thumb opcode: %lx"),
29584 (unsigned long) insn
);
29586 /* Encode as ADD immediate8 thumb 1 code. */
29587 insn
= 0x3000 | (rd
<< 8);
29589 /* Place the encoded addend into the first 8 bits of the
29591 if (!seg
->use_rela_p
)
29592 insn
|= encoded_addend
;
29595 /* Update the instruction. */
29596 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29600 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29601 case BFD_RELOC_ARM_ALU_PC_G0
:
29602 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29603 case BFD_RELOC_ARM_ALU_PC_G1
:
29604 case BFD_RELOC_ARM_ALU_PC_G2
:
29605 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29606 case BFD_RELOC_ARM_ALU_SB_G0
:
29607 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29608 case BFD_RELOC_ARM_ALU_SB_G1
:
29609 case BFD_RELOC_ARM_ALU_SB_G2
:
29610 gas_assert (!fixP
->fx_done
);
29611 if (!seg
->use_rela_p
)
29614 bfd_vma encoded_addend
;
29615 bfd_vma addend_abs
= llabs (value
);
29617 /* Check that the absolute value of the addend can be
29618 expressed as an 8-bit constant plus a rotation. */
29619 encoded_addend
= encode_arm_immediate (addend_abs
);
29620 if (encoded_addend
== (unsigned int) FAIL
)
29621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29622 _("the offset 0x%08lX is not representable"),
29623 (unsigned long) addend_abs
);
29625 /* Extract the instruction. */
29626 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29628 /* If the addend is positive, use an ADD instruction.
29629 Otherwise use a SUB. Take care not to destroy the S bit. */
29630 insn
&= 0xff1fffff;
29636 /* Place the encoded addend into the first 12 bits of the
29638 insn
&= 0xfffff000;
29639 insn
|= encoded_addend
;
29641 /* Update the instruction. */
29642 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29646 case BFD_RELOC_ARM_LDR_PC_G0
:
29647 case BFD_RELOC_ARM_LDR_PC_G1
:
29648 case BFD_RELOC_ARM_LDR_PC_G2
:
29649 case BFD_RELOC_ARM_LDR_SB_G0
:
29650 case BFD_RELOC_ARM_LDR_SB_G1
:
29651 case BFD_RELOC_ARM_LDR_SB_G2
:
29652 gas_assert (!fixP
->fx_done
);
29653 if (!seg
->use_rela_p
)
29656 bfd_vma addend_abs
= llabs (value
);
29658 /* Check that the absolute value of the addend can be
29659 encoded in 12 bits. */
29660 if (addend_abs
>= 0x1000)
29661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29662 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29663 (unsigned long) addend_abs
);
29665 /* Extract the instruction. */
29666 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29668 /* If the addend is negative, clear bit 23 of the instruction.
29669 Otherwise set it. */
29671 insn
&= ~(1 << 23);
29675 /* Place the absolute value of the addend into the first 12 bits
29676 of the instruction. */
29677 insn
&= 0xfffff000;
29678 insn
|= addend_abs
;
29680 /* Update the instruction. */
29681 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29685 case BFD_RELOC_ARM_LDRS_PC_G0
:
29686 case BFD_RELOC_ARM_LDRS_PC_G1
:
29687 case BFD_RELOC_ARM_LDRS_PC_G2
:
29688 case BFD_RELOC_ARM_LDRS_SB_G0
:
29689 case BFD_RELOC_ARM_LDRS_SB_G1
:
29690 case BFD_RELOC_ARM_LDRS_SB_G2
:
29691 gas_assert (!fixP
->fx_done
);
29692 if (!seg
->use_rela_p
)
29695 bfd_vma addend_abs
= llabs (value
);
29697 /* Check that the absolute value of the addend can be
29698 encoded in 8 bits. */
29699 if (addend_abs
>= 0x100)
29700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29701 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29702 (unsigned long) addend_abs
);
29704 /* Extract the instruction. */
29705 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29707 /* If the addend is negative, clear bit 23 of the instruction.
29708 Otherwise set it. */
29710 insn
&= ~(1 << 23);
29714 /* Place the first four bits of the absolute value of the addend
29715 into the first 4 bits of the instruction, and the remaining
29716 four into bits 8 .. 11. */
29717 insn
&= 0xfffff0f0;
29718 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29720 /* Update the instruction. */
29721 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29725 case BFD_RELOC_ARM_LDC_PC_G0
:
29726 case BFD_RELOC_ARM_LDC_PC_G1
:
29727 case BFD_RELOC_ARM_LDC_PC_G2
:
29728 case BFD_RELOC_ARM_LDC_SB_G0
:
29729 case BFD_RELOC_ARM_LDC_SB_G1
:
29730 case BFD_RELOC_ARM_LDC_SB_G2
:
29731 gas_assert (!fixP
->fx_done
);
29732 if (!seg
->use_rela_p
)
29735 bfd_vma addend_abs
= llabs (value
);
29737 /* Check that the absolute value of the addend is a multiple of
29738 four and, when divided by four, fits in 8 bits. */
29739 if (addend_abs
& 0x3)
29740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29741 _("bad offset 0x%08lX (must be word-aligned)"),
29742 (unsigned long) addend_abs
);
29744 if ((addend_abs
>> 2) > 0xff)
29745 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29746 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29747 (unsigned long) addend_abs
);
29749 /* Extract the instruction. */
29750 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29752 /* If the addend is negative, clear bit 23 of the instruction.
29753 Otherwise set it. */
29755 insn
&= ~(1 << 23);
29759 /* Place the addend (divided by four) into the first eight
29760 bits of the instruction. */
29761 insn
&= 0xfffffff0;
29762 insn
|= addend_abs
>> 2;
29764 /* Update the instruction. */
29765 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29769 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29771 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29772 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29773 && ARM_IS_FUNC (fixP
->fx_addsy
)
29774 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29776 /* Force a relocation for a branch 5 bits wide. */
29779 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29783 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29785 addressT boff
= value
>> 1;
29787 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29788 newval
|= (boff
<< 7);
29789 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29793 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29795 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29796 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29797 && ARM_IS_FUNC (fixP
->fx_addsy
)
29798 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29802 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29804 _("branch out of range"));
29806 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29808 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29810 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29811 addressT diff
= value
- boff
;
29815 newval
|= 1 << 1; /* T bit. */
29817 else if (diff
!= 2)
29819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29820 _("out of range label-relative fixup value"));
29822 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29826 case BFD_RELOC_ARM_THUMB_BF17
:
29828 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29829 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29830 && ARM_IS_FUNC (fixP
->fx_addsy
)
29831 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29833 /* Force a relocation for a branch 17 bits wide. */
29837 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29841 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29844 addressT immA
, immB
, immC
;
29846 immA
= (value
& 0x0001f000) >> 12;
29847 immB
= (value
& 0x00000ffc) >> 2;
29848 immC
= (value
& 0x00000002) >> 1;
29850 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29851 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29853 newval2
|= (immC
<< 11) | (immB
<< 1);
29854 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29855 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29859 case BFD_RELOC_ARM_THUMB_BF19
:
29861 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29862 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29863 && ARM_IS_FUNC (fixP
->fx_addsy
)
29864 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29866 /* Force a relocation for a branch 19 bits wide. */
29870 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29874 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29877 addressT immA
, immB
, immC
;
29879 immA
= (value
& 0x0007f000) >> 12;
29880 immB
= (value
& 0x00000ffc) >> 2;
29881 immC
= (value
& 0x00000002) >> 1;
29883 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29884 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29886 newval2
|= (immC
<< 11) | (immB
<< 1);
29887 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29888 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29892 case BFD_RELOC_ARM_THUMB_BF13
:
29894 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29895 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29896 && ARM_IS_FUNC (fixP
->fx_addsy
)
29897 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29899 /* Force a relocation for a branch 13 bits wide. */
29903 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29910 addressT immA
, immB
, immC
;
29912 immA
= (value
& 0x00001000) >> 12;
29913 immB
= (value
& 0x00000ffc) >> 2;
29914 immC
= (value
& 0x00000002) >> 1;
29916 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29917 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29919 newval2
|= (immC
<< 11) | (immB
<< 1);
29920 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29921 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29925 case BFD_RELOC_ARM_THUMB_LOOP12
:
29927 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29928 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29929 && ARM_IS_FUNC (fixP
->fx_addsy
)
29930 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29932 /* Force a relocation for a branch 12 bits wide. */
29936 bfd_vma insn
= get_thumb32_insn (buf
);
29937 /* le lr, <label>, le <label> or letp lr, <label> */
29938 if (((insn
& 0xffffffff) == 0xf00fc001)
29939 || ((insn
& 0xffffffff) == 0xf02fc001)
29940 || ((insn
& 0xffffffff) == 0xf01fc001))
29943 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29946 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29948 addressT imml
, immh
;
29950 immh
= (value
& 0x00000ffc) >> 2;
29951 imml
= (value
& 0x00000002) >> 1;
29953 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29954 newval
|= (imml
<< 11) | (immh
<< 1);
29955 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29959 case BFD_RELOC_ARM_V4BX
:
29960 /* This will need to go in the object file. */
29964 case BFD_RELOC_UNUSED
:
29966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29967 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29971 /* Translate internal representation of relocation info to BFD target
29975 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29978 bfd_reloc_code_real_type code
;
29980 reloc
= XNEW (arelent
);
29982 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29983 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29984 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29986 if (fixp
->fx_pcrel
)
29988 if (section
->use_rela_p
)
29989 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29991 fixp
->fx_offset
= reloc
->address
;
29993 reloc
->addend
= fixp
->fx_offset
;
29995 switch (fixp
->fx_r_type
)
29998 if (fixp
->fx_pcrel
)
30000 code
= BFD_RELOC_8_PCREL
;
30003 /* Fall through. */
30006 if (fixp
->fx_pcrel
)
30008 code
= BFD_RELOC_16_PCREL
;
30011 /* Fall through. */
30014 if (fixp
->fx_pcrel
)
30016 code
= BFD_RELOC_32_PCREL
;
30019 /* Fall through. */
30021 case BFD_RELOC_ARM_MOVW
:
30022 if (fixp
->fx_pcrel
)
30024 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30027 /* Fall through. */
30029 case BFD_RELOC_ARM_MOVT
:
30030 if (fixp
->fx_pcrel
)
30032 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30035 /* Fall through. */
30037 case BFD_RELOC_ARM_THUMB_MOVW
:
30038 if (fixp
->fx_pcrel
)
30040 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30043 /* Fall through. */
30045 case BFD_RELOC_ARM_THUMB_MOVT
:
30046 if (fixp
->fx_pcrel
)
30048 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30051 /* Fall through. */
30053 case BFD_RELOC_NONE
:
30054 case BFD_RELOC_ARM_PCREL_BRANCH
:
30055 case BFD_RELOC_ARM_PCREL_BLX
:
30056 case BFD_RELOC_RVA
:
30057 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30058 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30059 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30060 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30061 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30062 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30063 case BFD_RELOC_VTABLE_ENTRY
:
30064 case BFD_RELOC_VTABLE_INHERIT
:
30066 case BFD_RELOC_32_SECREL
:
30068 code
= fixp
->fx_r_type
;
30071 case BFD_RELOC_THUMB_PCREL_BLX
:
30073 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30074 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30077 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30080 case BFD_RELOC_ARM_LITERAL
:
30081 case BFD_RELOC_ARM_HWLITERAL
:
30082 /* If this is called then the a literal has
30083 been referenced across a section boundary. */
30084 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30085 _("literal referenced across section boundary"));
30089 case BFD_RELOC_ARM_TLS_CALL
:
30090 case BFD_RELOC_ARM_THM_TLS_CALL
:
30091 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30092 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30093 case BFD_RELOC_ARM_GOT32
:
30094 case BFD_RELOC_ARM_GOTOFF
:
30095 case BFD_RELOC_ARM_GOT_PREL
:
30096 case BFD_RELOC_ARM_PLT32
:
30097 case BFD_RELOC_ARM_TARGET1
:
30098 case BFD_RELOC_ARM_ROSEGREL32
:
30099 case BFD_RELOC_ARM_SBREL32
:
30100 case BFD_RELOC_ARM_PREL31
:
30101 case BFD_RELOC_ARM_TARGET2
:
30102 case BFD_RELOC_ARM_TLS_LDO32
:
30103 case BFD_RELOC_ARM_PCREL_CALL
:
30104 case BFD_RELOC_ARM_PCREL_JUMP
:
30105 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30106 case BFD_RELOC_ARM_ALU_PC_G0
:
30107 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30108 case BFD_RELOC_ARM_ALU_PC_G1
:
30109 case BFD_RELOC_ARM_ALU_PC_G2
:
30110 case BFD_RELOC_ARM_LDR_PC_G0
:
30111 case BFD_RELOC_ARM_LDR_PC_G1
:
30112 case BFD_RELOC_ARM_LDR_PC_G2
:
30113 case BFD_RELOC_ARM_LDRS_PC_G0
:
30114 case BFD_RELOC_ARM_LDRS_PC_G1
:
30115 case BFD_RELOC_ARM_LDRS_PC_G2
:
30116 case BFD_RELOC_ARM_LDC_PC_G0
:
30117 case BFD_RELOC_ARM_LDC_PC_G1
:
30118 case BFD_RELOC_ARM_LDC_PC_G2
:
30119 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30120 case BFD_RELOC_ARM_ALU_SB_G0
:
30121 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30122 case BFD_RELOC_ARM_ALU_SB_G1
:
30123 case BFD_RELOC_ARM_ALU_SB_G2
:
30124 case BFD_RELOC_ARM_LDR_SB_G0
:
30125 case BFD_RELOC_ARM_LDR_SB_G1
:
30126 case BFD_RELOC_ARM_LDR_SB_G2
:
30127 case BFD_RELOC_ARM_LDRS_SB_G0
:
30128 case BFD_RELOC_ARM_LDRS_SB_G1
:
30129 case BFD_RELOC_ARM_LDRS_SB_G2
:
30130 case BFD_RELOC_ARM_LDC_SB_G0
:
30131 case BFD_RELOC_ARM_LDC_SB_G1
:
30132 case BFD_RELOC_ARM_LDC_SB_G2
:
30133 case BFD_RELOC_ARM_V4BX
:
30134 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30135 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30136 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30137 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30138 case BFD_RELOC_ARM_GOTFUNCDESC
:
30139 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30140 case BFD_RELOC_ARM_FUNCDESC
:
30141 case BFD_RELOC_ARM_THUMB_BF17
:
30142 case BFD_RELOC_ARM_THUMB_BF19
:
30143 case BFD_RELOC_ARM_THUMB_BF13
:
30144 code
= fixp
->fx_r_type
;
30147 case BFD_RELOC_ARM_TLS_GOTDESC
:
30148 case BFD_RELOC_ARM_TLS_GD32
:
30149 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30150 case BFD_RELOC_ARM_TLS_LE32
:
30151 case BFD_RELOC_ARM_TLS_IE32
:
30152 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30153 case BFD_RELOC_ARM_TLS_LDM32
:
30154 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30155 /* BFD will include the symbol's address in the addend.
30156 But we don't want that, so subtract it out again here. */
30157 if (!S_IS_COMMON (fixp
->fx_addsy
))
30158 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30159 code
= fixp
->fx_r_type
;
30163 case BFD_RELOC_ARM_IMMEDIATE
:
30164 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30165 _("internal relocation (type: IMMEDIATE) not fixed up"));
30168 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30169 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30170 _("ADRL used for a symbol not defined in the same file"));
30173 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30174 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30175 case BFD_RELOC_ARM_THUMB_LOOP12
:
30176 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30177 _("%s used for a symbol not defined in the same file"),
30178 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30181 case BFD_RELOC_ARM_OFFSET_IMM
:
30182 if (section
->use_rela_p
)
30184 code
= fixp
->fx_r_type
;
30188 if (fixp
->fx_addsy
!= NULL
30189 && !S_IS_DEFINED (fixp
->fx_addsy
)
30190 && S_IS_LOCAL (fixp
->fx_addsy
))
30192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30193 _("undefined local label `%s'"),
30194 S_GET_NAME (fixp
->fx_addsy
));
30198 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30199 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30206 switch (fixp
->fx_r_type
)
30208 case BFD_RELOC_NONE
: type
= "NONE"; break;
30209 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30210 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30211 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30212 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30213 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30214 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30215 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30216 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30217 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30218 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30219 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30220 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30221 default: type
= _("<unknown>"); break;
30223 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30224 _("cannot represent %s relocation in this object file format"),
30231 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30233 && fixp
->fx_addsy
== GOT_symbol
)
30235 code
= BFD_RELOC_ARM_GOTPC
;
30236 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30240 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30242 if (reloc
->howto
== NULL
)
30244 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30245 _("cannot represent %s relocation in this object file format"),
30246 bfd_get_reloc_code_name (code
));
30250 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30251 vtable entry to be used in the relocation's section offset. */
30252 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30253 reloc
->address
= fixp
->fx_offset
;
30258 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30261 cons_fix_new_arm (fragS
* frag
,
30265 bfd_reloc_code_real_type reloc
)
30270 FIXME: @@ Should look at CPU word size. */
30274 reloc
= BFD_RELOC_8
;
30277 reloc
= BFD_RELOC_16
;
30281 reloc
= BFD_RELOC_32
;
30284 reloc
= BFD_RELOC_64
;
30289 if (exp
->X_op
== O_secrel
)
30291 exp
->X_op
= O_symbol
;
30292 reloc
= BFD_RELOC_32_SECREL
;
30296 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30299 #if defined (OBJ_COFF)
30301 arm_validate_fix (fixS
* fixP
)
30303 /* If the destination of the branch is a defined symbol which does not have
30304 the THUMB_FUNC attribute, then we must be calling a function which has
30305 the (interfacearm) attribute. We look for the Thumb entry point to that
30306 function and change the branch to refer to that function instead. */
30307 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30308 && fixP
->fx_addsy
!= NULL
30309 && S_IS_DEFINED (fixP
->fx_addsy
)
30310 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30312 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30319 arm_force_relocation (struct fix
* fixp
)
30321 #if defined (OBJ_COFF) && defined (TE_PE)
30322 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30326 /* In case we have a call or a branch to a function in ARM ISA mode from
30327 a thumb function or vice-versa force the relocation. These relocations
30328 are cleared off for some cores that might have blx and simple transformations
30332 switch (fixp
->fx_r_type
)
30334 case BFD_RELOC_ARM_PCREL_JUMP
:
30335 case BFD_RELOC_ARM_PCREL_CALL
:
30336 case BFD_RELOC_THUMB_PCREL_BLX
:
30337 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30341 case BFD_RELOC_ARM_PCREL_BLX
:
30342 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30343 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30344 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30345 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30354 /* Resolve these relocations even if the symbol is extern or weak.
30355 Technically this is probably wrong due to symbol preemption.
30356 In practice these relocations do not have enough range to be useful
30357 at dynamic link time, and some code (e.g. in the Linux kernel)
30358 expects these references to be resolved. */
30359 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30360 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30361 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30362 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30363 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30364 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30365 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30366 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30367 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30368 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30369 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30370 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30371 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30372 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30375 /* Always leave these relocations for the linker. */
30376 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30377 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30381 /* Always generate relocations against function symbols. */
30382 if (fixp
->fx_r_type
== BFD_RELOC_32
30384 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30387 return generic_force_reloc (fixp
);
30390 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30391 /* Relocations against function names must be left unadjusted,
30392 so that the linker can use this information to generate interworking
30393 stubs. The MIPS version of this function
30394 also prevents relocations that are mips-16 specific, but I do not
30395 know why it does this.
30398 There is one other problem that ought to be addressed here, but
30399 which currently is not: Taking the address of a label (rather
30400 than a function) and then later jumping to that address. Such
30401 addresses also ought to have their bottom bit set (assuming that
30402 they reside in Thumb code), but at the moment they will not. */
30405 arm_fix_adjustable (fixS
* fixP
)
30407 if (fixP
->fx_addsy
== NULL
)
30410 /* Preserve relocations against symbols with function type. */
30411 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30414 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30415 && fixP
->fx_subsy
== NULL
)
30418 /* We need the symbol name for the VTABLE entries. */
30419 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30420 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30423 /* Don't allow symbols to be discarded on GOT related relocs. */
30424 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30425 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30426 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30427 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30428 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30429 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30430 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30431 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30432 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30433 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30434 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30435 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30436 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30437 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30438 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30439 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30443 /* Similarly for group relocations. */
30444 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30445 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30449 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30450 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30453 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30454 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30455 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30456 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30457 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30460 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30461 offsets, so keep these symbols. */
30462 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30463 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30468 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30472 elf32_arm_target_format (void)
30475 return (target_big_endian
30476 ? "elf32-bigarm-symbian"
30477 : "elf32-littlearm-symbian");
30478 #elif defined (TE_VXWORKS)
30479 return (target_big_endian
30480 ? "elf32-bigarm-vxworks"
30481 : "elf32-littlearm-vxworks");
30482 #elif defined (TE_NACL)
30483 return (target_big_endian
30484 ? "elf32-bigarm-nacl"
30485 : "elf32-littlearm-nacl");
30489 if (target_big_endian
)
30490 return "elf32-bigarm-fdpic";
30492 return "elf32-littlearm-fdpic";
30496 if (target_big_endian
)
30497 return "elf32-bigarm";
30499 return "elf32-littlearm";
30505 armelf_frob_symbol (symbolS
* symp
,
30508 elf_frob_symbol (symp
, puntp
);
30512 /* MD interface: Finalization. */
30517 literal_pool
* pool
;
30519 /* Ensure that all the predication blocks are properly closed. */
30520 check_pred_blocks_finished ();
30522 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30524 /* Put it at the end of the relevant section. */
30525 subseg_set (pool
->section
, pool
->sub_section
);
30527 arm_elf_change_section ();
30534 /* Remove any excess mapping symbols generated for alignment frags in
30535 SEC. We may have created a mapping symbol before a zero byte
30536 alignment; remove it if there's a mapping symbol after the
30539 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30540 void *dummy ATTRIBUTE_UNUSED
)
30542 segment_info_type
*seginfo
= seg_info (sec
);
30545 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30548 for (fragp
= seginfo
->frchainP
->frch_root
;
30550 fragp
= fragp
->fr_next
)
30552 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30553 fragS
*next
= fragp
->fr_next
;
30555 /* Variable-sized frags have been converted to fixed size by
30556 this point. But if this was variable-sized to start with,
30557 there will be a fixed-size frag after it. So don't handle
30559 if (sym
== NULL
|| next
== NULL
)
30562 if (S_GET_VALUE (sym
) < next
->fr_address
)
30563 /* Not at the end of this frag. */
30565 know (S_GET_VALUE (sym
) == next
->fr_address
);
30569 if (next
->tc_frag_data
.first_map
!= NULL
)
30571 /* Next frag starts with a mapping symbol. Discard this
30573 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30577 if (next
->fr_next
== NULL
)
30579 /* This mapping symbol is at the end of the section. Discard
30581 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30582 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30586 /* As long as we have empty frags without any mapping symbols,
30588 /* If the next frag is non-empty and does not start with a
30589 mapping symbol, then this mapping symbol is required. */
30590 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30593 next
= next
->fr_next
;
30595 while (next
!= NULL
);
30600 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30604 arm_adjust_symtab (void)
30609 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30611 if (ARM_IS_THUMB (sym
))
30613 if (THUMB_IS_FUNC (sym
))
30615 /* Mark the symbol as a Thumb function. */
30616 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30617 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30618 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30620 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30621 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30623 as_bad (_("%s: unexpected function type: %d"),
30624 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30626 else switch (S_GET_STORAGE_CLASS (sym
))
30629 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30632 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30635 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30643 if (ARM_IS_INTERWORK (sym
))
30644 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30651 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30653 if (ARM_IS_THUMB (sym
))
30655 elf_symbol_type
* elf_sym
;
30657 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30658 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30660 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30661 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30663 /* If it's a .thumb_func, declare it as so,
30664 otherwise tag label as .code 16. */
30665 if (THUMB_IS_FUNC (sym
))
30666 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30667 ST_BRANCH_TO_THUMB
);
30668 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30669 elf_sym
->internal_elf_sym
.st_info
=
30670 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30675 /* Remove any overlapping mapping symbols generated by alignment frags. */
30676 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30677 /* Now do generic ELF adjustments. */
30678 elf_adjust_symtab ();
30682 /* MD interface: Initialization. */
30685 set_constant_flonums (void)
30689 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30690 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30694 /* Auto-select Thumb mode if it's the only available instruction set for the
30695 given architecture. */
30698 autoselect_thumb_from_cpu_variant (void)
30700 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30701 opcode_select (16);
30710 if ( (arm_ops_hsh
= hash_new ()) == NULL
30711 || (arm_cond_hsh
= hash_new ()) == NULL
30712 || (arm_vcond_hsh
= hash_new ()) == NULL
30713 || (arm_shift_hsh
= hash_new ()) == NULL
30714 || (arm_psr_hsh
= hash_new ()) == NULL
30715 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
30716 || (arm_reg_hsh
= hash_new ()) == NULL
30717 || (arm_reloc_hsh
= hash_new ()) == NULL
30718 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
30719 as_fatal (_("virtual memory exhausted"));
30721 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30722 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30723 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30724 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30725 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30726 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30727 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30728 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30729 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30730 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30731 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30732 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30733 (void *) (v7m_psrs
+ i
));
30734 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30735 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30737 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30739 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30740 (void *) (barrier_opt_names
+ i
));
30742 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30744 struct reloc_entry
* entry
= reloc_names
+ i
;
30746 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30747 /* This makes encode_branch() use the EABI versions of this relocation. */
30748 entry
->reloc
= BFD_RELOC_UNUSED
;
30750 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30754 set_constant_flonums ();
30756 /* Set the cpu variant based on the command-line options. We prefer
30757 -mcpu= over -march= if both are set (as for GCC); and we prefer
30758 -mfpu= over any other way of setting the floating point unit.
30759 Use of legacy options with new options are faulted. */
30762 if (mcpu_cpu_opt
|| march_cpu_opt
)
30763 as_bad (_("use of old and new-style options to set CPU type"));
30765 selected_arch
= *legacy_cpu
;
30767 else if (mcpu_cpu_opt
)
30769 selected_arch
= *mcpu_cpu_opt
;
30770 selected_ext
= *mcpu_ext_opt
;
30772 else if (march_cpu_opt
)
30774 selected_arch
= *march_cpu_opt
;
30775 selected_ext
= *march_ext_opt
;
30777 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30782 as_bad (_("use of old and new-style options to set FPU type"));
30784 selected_fpu
= *legacy_fpu
;
30787 selected_fpu
= *mfpu_opt
;
30790 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30791 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30792 /* Some environments specify a default FPU. If they don't, infer it
30793 from the processor. */
30795 selected_fpu
= *mcpu_fpu_opt
;
30796 else if (march_fpu_opt
)
30797 selected_fpu
= *march_fpu_opt
;
30799 selected_fpu
= fpu_default
;
30803 if (ARM_FEATURE_ZERO (selected_fpu
))
30805 if (!no_cpu_selected ())
30806 selected_fpu
= fpu_default
;
30808 selected_fpu
= fpu_arch_fpa
;
30812 if (ARM_FEATURE_ZERO (selected_arch
))
30814 selected_arch
= cpu_default
;
30815 selected_cpu
= selected_arch
;
30817 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30819 /* Autodection of feature mode: allow all features in cpu_variant but leave
30820 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30821 after all instruction have been processed and we can decide what CPU
30822 should be selected. */
30823 if (ARM_FEATURE_ZERO (selected_arch
))
30824 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30826 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30829 autoselect_thumb_from_cpu_variant ();
30831 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30833 #if defined OBJ_COFF || defined OBJ_ELF
30835 unsigned int flags
= 0;
30837 #if defined OBJ_ELF
30838 flags
= meabi_flags
;
30840 switch (meabi_flags
)
30842 case EF_ARM_EABI_UNKNOWN
:
30844 /* Set the flags in the private structure. */
30845 if (uses_apcs_26
) flags
|= F_APCS26
;
30846 if (support_interwork
) flags
|= F_INTERWORK
;
30847 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30848 if (pic_code
) flags
|= F_PIC
;
30849 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30850 flags
|= F_SOFT_FLOAT
;
30852 switch (mfloat_abi_opt
)
30854 case ARM_FLOAT_ABI_SOFT
:
30855 case ARM_FLOAT_ABI_SOFTFP
:
30856 flags
|= F_SOFT_FLOAT
;
30859 case ARM_FLOAT_ABI_HARD
:
30860 if (flags
& F_SOFT_FLOAT
)
30861 as_bad (_("hard-float conflicts with specified fpu"));
30865 /* Using pure-endian doubles (even if soft-float). */
30866 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30867 flags
|= F_VFP_FLOAT
;
30869 #if defined OBJ_ELF
30870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30871 flags
|= EF_ARM_MAVERICK_FLOAT
;
30874 case EF_ARM_EABI_VER4
:
30875 case EF_ARM_EABI_VER5
:
30876 /* No additional flags to set. */
30883 bfd_set_private_flags (stdoutput
, flags
);
30885 /* We have run out flags in the COFF header to encode the
30886 status of ATPCS support, so instead we create a dummy,
30887 empty, debug section called .arm.atpcs. */
30892 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30896 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30897 bfd_set_section_size (sec
, 0);
30898 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30904 /* Record the CPU type as well. */
30905 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30906 mach
= bfd_mach_arm_iWMMXt2
;
30907 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30908 mach
= bfd_mach_arm_iWMMXt
;
30909 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30910 mach
= bfd_mach_arm_XScale
;
30911 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30912 mach
= bfd_mach_arm_ep9312
;
30913 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30914 mach
= bfd_mach_arm_5TE
;
30915 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30917 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30918 mach
= bfd_mach_arm_5T
;
30920 mach
= bfd_mach_arm_5
;
30922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30925 mach
= bfd_mach_arm_4T
;
30927 mach
= bfd_mach_arm_4
;
30929 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30930 mach
= bfd_mach_arm_3M
;
30931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30932 mach
= bfd_mach_arm_3
;
30933 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30934 mach
= bfd_mach_arm_2a
;
30935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30936 mach
= bfd_mach_arm_2
;
30938 mach
= bfd_mach_arm_unknown
;
30940 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30943 /* Command line processing. */
30946 Invocation line includes a switch not recognized by the base assembler.
30947 See if it's a processor-specific option.
30949 This routine is somewhat complicated by the need for backwards
30950 compatibility (since older releases of gcc can't be changed).
30951 The new options try to make the interface as compatible as
30954 New options (supported) are:
30956 -mcpu=<cpu name> Assemble for selected processor
30957 -march=<architecture name> Assemble for selected architecture
30958 -mfpu=<fpu architecture> Assemble for selected FPU.
30959 -EB/-mbig-endian Big-endian
30960 -EL/-mlittle-endian Little-endian
30961 -k Generate PIC code
30962 -mthumb Start in Thumb mode
30963 -mthumb-interwork Code supports ARM/Thumb interworking
30965 -m[no-]warn-deprecated Warn about deprecated features
30966 -m[no-]warn-syms Warn when symbols match instructions
30968 For now we will also provide support for:
30970 -mapcs-32 32-bit Program counter
30971 -mapcs-26 26-bit Program counter
30972 -macps-float Floats passed in FP registers
30973 -mapcs-reentrant Reentrant code
30975 (sometime these will probably be replaced with -mapcs=<list of options>
30976 and -matpcs=<list of options>)
30978 The remaining options are only supported for back-wards compatibility.
30979 Cpu variants, the arm part is optional:
30980 -m[arm]1 Currently not supported.
30981 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30982 -m[arm]3 Arm 3 processor
30983 -m[arm]6[xx], Arm 6 processors
30984 -m[arm]7[xx][t][[d]m] Arm 7 processors
30985 -m[arm]8[10] Arm 8 processors
30986 -m[arm]9[20][tdmi] Arm 9 processors
30987 -mstrongarm[110[0]] StrongARM processors
30988 -mxscale XScale processors
30989 -m[arm]v[2345[t[e]]] Arm architectures
30990 -mall All (except the ARM1)
30992 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30993 -mfpe-old (No float load/store multiples)
30994 -mvfpxd VFP Single precision
30996 -mno-fpu Disable all floating point instructions
30998 The following CPU names are recognized:
30999 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31000 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31001 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31002 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31003 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31004 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31005 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31009 const char * md_shortopts
= "m:k";
31011 #ifdef ARM_BI_ENDIAN
31012 #define OPTION_EB (OPTION_MD_BASE + 0)
31013 #define OPTION_EL (OPTION_MD_BASE + 1)
31015 #if TARGET_BYTES_BIG_ENDIAN
31016 #define OPTION_EB (OPTION_MD_BASE + 0)
31018 #define OPTION_EL (OPTION_MD_BASE + 1)
31021 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31022 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31024 struct option md_longopts
[] =
31027 {"EB", no_argument
, NULL
, OPTION_EB
},
31030 {"EL", no_argument
, NULL
, OPTION_EL
},
31032 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31034 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31036 {NULL
, no_argument
, NULL
, 0}
31039 size_t md_longopts_size
= sizeof (md_longopts
);
31041 struct arm_option_table
31043 const char * option
; /* Option name to match. */
31044 const char * help
; /* Help information. */
31045 int * var
; /* Variable to change. */
31046 int value
; /* What to change it to. */
31047 const char * deprecated
; /* If non-null, print this message. */
31050 struct arm_option_table arm_opts
[] =
31052 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31053 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31054 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31055 &support_interwork
, 1, NULL
},
31056 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31057 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31058 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31060 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31061 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31062 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31063 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31066 /* These are recognized by the assembler, but have no affect on code. */
31067 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31068 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31070 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31071 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31072 &warn_on_deprecated
, 0, NULL
},
31074 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31075 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31076 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31078 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31079 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31080 {NULL
, NULL
, NULL
, 0, NULL
}
31083 struct arm_legacy_option_table
31085 const char * option
; /* Option name to match. */
31086 const arm_feature_set
** var
; /* Variable to change. */
31087 const arm_feature_set value
; /* What to change it to. */
31088 const char * deprecated
; /* If non-null, print this message. */
31091 const struct arm_legacy_option_table arm_legacy_opts
[] =
31093 /* DON'T add any new processors to this list -- we want the whole list
31094 to go away... Add them to the processors table instead. */
31095 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31096 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31097 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31098 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31099 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31100 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31101 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31102 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31103 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31104 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31105 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31106 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31107 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31108 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31109 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31110 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31111 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31112 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31113 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31114 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31115 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31116 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31117 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31118 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31119 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31120 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31121 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31122 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31123 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31124 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31125 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31126 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31127 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31128 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31129 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31130 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31131 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31132 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31133 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31134 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31135 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31136 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31137 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31138 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31139 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31140 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31141 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31142 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31143 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31144 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31145 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31146 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31147 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31148 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31149 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31150 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31151 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31152 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31153 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31154 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31155 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31156 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31157 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31158 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31159 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31160 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31161 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31162 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31163 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31164 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31165 N_("use -mcpu=strongarm110")},
31166 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31167 N_("use -mcpu=strongarm1100")},
31168 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31169 N_("use -mcpu=strongarm1110")},
31170 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31171 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31172 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31174 /* Architecture variants -- don't add any more to this list either. */
31175 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31176 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31177 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31178 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31179 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31180 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31181 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31182 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31183 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31184 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31185 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31186 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31187 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31188 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31189 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31190 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31191 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31192 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31194 /* Floating point variants -- don't add any more to this list either. */
31195 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31196 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31197 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31198 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31199 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31201 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31204 struct arm_cpu_option_table
31208 const arm_feature_set value
;
31209 const arm_feature_set ext
;
31210 /* For some CPUs we assume an FPU unless the user explicitly sets
31212 const arm_feature_set default_fpu
;
31213 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31215 const char * canonical_name
;
31218 /* This list should, at a minimum, contain all the cpu names
31219 recognized by GCC. */
31220 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31222 static const struct arm_cpu_option_table arm_cpus
[] =
31224 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31227 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31230 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31233 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31236 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31239 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31242 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31245 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31248 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31251 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31254 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31257 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31260 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31263 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31266 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31269 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31272 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31275 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31278 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31281 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31284 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31287 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31290 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31293 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31296 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31299 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31302 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31305 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31308 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31311 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31314 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31317 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31320 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31323 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31326 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31329 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31332 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31335 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31338 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31341 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31344 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31347 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31350 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31353 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31356 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31359 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31363 /* For V5 or later processors we default to using VFP; but the user
31364 should really set the FPU type explicitly. */
31365 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31368 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31371 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31374 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31377 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31380 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31383 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31386 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31389 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31392 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31395 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31398 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31401 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31404 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31407 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31410 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31413 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31416 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31419 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31422 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31425 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31428 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31431 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31434 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31437 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31440 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31443 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31446 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31449 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31452 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31455 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31458 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31461 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31464 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31467 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31470 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31473 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31474 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31476 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31478 FPU_ARCH_NEON_VFP_V4
),
31479 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31480 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31481 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31482 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31483 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31484 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31485 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31487 FPU_ARCH_NEON_VFP_V4
),
31488 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31490 FPU_ARCH_NEON_VFP_V4
),
31491 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31493 FPU_ARCH_NEON_VFP_V4
),
31494 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31495 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31496 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31497 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31498 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31499 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31500 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31501 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31502 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31503 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31504 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31505 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31506 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31507 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31508 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31509 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31510 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31511 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31512 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31514 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31515 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31516 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31518 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31519 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31521 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31523 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31524 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31525 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31526 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31527 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31528 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31529 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31530 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31533 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31535 FPU_ARCH_VFP_V3D16
),
31536 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31537 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31539 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31540 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31541 FPU_ARCH_VFP_V3D16
),
31542 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31543 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31544 FPU_ARCH_VFP_V3D16
),
31545 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31546 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31547 FPU_ARCH_NEON_VFP_ARMV8
),
31548 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31549 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31551 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31552 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31554 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31557 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31560 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31563 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31566 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31569 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31572 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31575 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31576 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31577 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31578 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31579 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31580 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31581 /* ??? XSCALE is really an architecture. */
31582 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31586 /* ??? iwmmxt is not a processor. */
31587 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31590 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31593 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31598 ARM_CPU_OPT ("ep9312", "ARM920T",
31599 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31600 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31602 /* Marvell processors. */
31603 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31604 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31605 FPU_ARCH_VFP_V3D16
),
31606 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31607 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31608 FPU_ARCH_NEON_VFP_V4
),
31610 /* APM X-Gene family. */
31611 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31613 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31614 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31615 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31616 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31618 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31622 struct arm_ext_table
31626 const arm_feature_set merge
;
31627 const arm_feature_set clear
;
31630 struct arm_arch_option_table
31634 const arm_feature_set value
;
31635 const arm_feature_set default_fpu
;
31636 const struct arm_ext_table
* ext_table
;
31639 /* Used to add support for +E and +noE extension. */
31640 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31641 /* Used to add support for a +E extension. */
31642 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31643 /* Used to add support for a +noE extension. */
31644 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31646 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31647 ~0 & ~FPU_ENDIAN_PURE)
31649 static const struct arm_ext_table armv5te_ext_table
[] =
31651 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31652 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31655 static const struct arm_ext_table armv7_ext_table
[] =
31657 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31658 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31661 static const struct arm_ext_table armv7ve_ext_table
[] =
31663 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31664 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31665 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31666 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31667 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31668 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31669 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31671 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31672 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31674 /* Aliases for +simd. */
31675 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31677 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31678 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31679 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31681 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31684 static const struct arm_ext_table armv7a_ext_table
[] =
31686 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31687 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31688 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31689 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31690 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31691 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31692 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31694 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31695 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31697 /* Aliases for +simd. */
31698 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31699 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31701 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31702 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31704 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31705 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31706 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31709 static const struct arm_ext_table armv7r_ext_table
[] =
31711 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31712 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31713 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31714 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31715 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31716 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31717 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31718 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31719 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31722 static const struct arm_ext_table armv7em_ext_table
[] =
31724 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31725 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31726 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31727 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31728 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31729 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31730 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31733 static const struct arm_ext_table armv8a_ext_table
[] =
31735 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31736 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31737 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31738 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31740 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31741 should use the +simd option to turn on FP. */
31742 ARM_REMOVE ("fp", ALL_FP
),
31743 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31744 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31745 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31749 static const struct arm_ext_table armv81a_ext_table
[] =
31751 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31752 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31753 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31755 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31756 should use the +simd option to turn on FP. */
31757 ARM_REMOVE ("fp", ALL_FP
),
31758 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31759 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31760 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31763 static const struct arm_ext_table armv82a_ext_table
[] =
31765 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31766 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31767 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31768 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31769 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31770 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31771 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31772 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31774 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31775 should use the +simd option to turn on FP. */
31776 ARM_REMOVE ("fp", ALL_FP
),
31777 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31778 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31779 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31782 static const struct arm_ext_table armv84a_ext_table
[] =
31784 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31785 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31786 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31787 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31788 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31789 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31791 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31792 should use the +simd option to turn on FP. */
31793 ARM_REMOVE ("fp", ALL_FP
),
31794 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31795 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31796 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31799 static const struct arm_ext_table armv85a_ext_table
[] =
31801 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31802 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31803 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31804 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31805 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31806 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31808 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31809 should use the +simd option to turn on FP. */
31810 ARM_REMOVE ("fp", ALL_FP
),
31811 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31814 static const struct arm_ext_table armv86a_ext_table
[] =
31816 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31817 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31820 #define CDE_EXTENSIONS \
31821 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31822 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31823 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31824 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31825 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31826 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31827 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31828 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31830 static const struct arm_ext_table armv8m_main_ext_table
[] =
31832 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31833 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31834 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31835 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31837 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31841 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31843 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31844 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31846 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31847 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31850 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31851 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31852 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31853 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31855 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31856 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31857 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31859 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31862 #undef CDE_EXTENSIONS
31864 static const struct arm_ext_table armv8r_ext_table
[] =
31866 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31867 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31868 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31869 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31870 ARM_REMOVE ("fp", ALL_FP
),
31871 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31872 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31875 /* This list should, at a minimum, contain all the architecture names
31876 recognized by GCC. */
31877 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31878 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31879 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31881 static const struct arm_arch_option_table arm_archs
[] =
31883 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31884 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31885 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31886 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31887 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31888 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31889 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31890 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31891 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31892 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31893 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31894 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31895 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31896 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31897 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31898 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31899 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31900 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31901 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31902 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31903 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31904 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31905 kept to preserve existing behaviour. */
31906 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31907 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31908 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31909 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31910 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31911 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31912 kept to preserve existing behaviour. */
31913 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31914 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31915 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31916 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31917 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31918 /* The official spelling of the ARMv7 profile variants is the dashed form.
31919 Accept the non-dashed form for compatibility with old toolchains. */
31920 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31921 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31922 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31923 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31924 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31925 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31926 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31927 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31928 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31929 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31931 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31933 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31934 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31935 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31936 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31937 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31938 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31939 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31940 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31941 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31942 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31943 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31944 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31946 #undef ARM_ARCH_OPT
31948 /* ISA extensions in the co-processor and main instruction set space. */
31950 struct arm_option_extension_value_table
31954 const arm_feature_set merge_value
;
31955 const arm_feature_set clear_value
;
31956 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31957 indicates that an extension is available for all architectures while
31958 ARM_ANY marks an empty entry. */
31959 const arm_feature_set allowed_archs
[2];
31962 /* The following table must be in alphabetical order with a NULL last entry. */
31964 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31965 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31967 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31968 use the context sensitive approach using arm_ext_table's. */
31969 static const struct arm_option_extension_value_table arm_extensions
[] =
31971 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31972 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31973 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31974 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31975 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31976 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31977 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31978 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31980 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31981 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31982 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31983 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31984 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31985 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31986 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31988 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31989 | ARM_EXT2_FP16_FML
),
31990 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31991 | ARM_EXT2_FP16_FML
),
31993 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31994 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31995 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31996 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31997 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31998 Thumb divide instruction. Due to this having the same name as the
31999 previous entry, this will be ignored when doing command-line parsing and
32000 only considered by build attribute selection code. */
32001 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32002 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32003 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32004 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32005 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32006 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32007 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32008 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32009 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32010 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32011 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32012 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32013 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32014 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32016 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32017 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32018 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32019 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32020 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32021 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32023 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32024 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32025 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32026 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32027 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32028 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32029 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32030 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32032 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32033 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32034 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32035 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32036 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32037 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32038 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32039 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32041 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32042 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32043 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32044 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32045 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32049 /* ISA floating-point and Advanced SIMD extensions. */
32050 struct arm_option_fpu_value_table
32053 const arm_feature_set value
;
32056 /* This list should, at a minimum, contain all the fpu names
32057 recognized by GCC. */
32058 static const struct arm_option_fpu_value_table arm_fpus
[] =
32060 {"softfpa", FPU_NONE
},
32061 {"fpe", FPU_ARCH_FPE
},
32062 {"fpe2", FPU_ARCH_FPE
},
32063 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32064 {"fpa", FPU_ARCH_FPA
},
32065 {"fpa10", FPU_ARCH_FPA
},
32066 {"fpa11", FPU_ARCH_FPA
},
32067 {"arm7500fe", FPU_ARCH_FPA
},
32068 {"softvfp", FPU_ARCH_VFP
},
32069 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32070 {"vfp", FPU_ARCH_VFP_V2
},
32071 {"vfp9", FPU_ARCH_VFP_V2
},
32072 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32073 {"vfp10", FPU_ARCH_VFP_V2
},
32074 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32075 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32076 {"vfpv2", FPU_ARCH_VFP_V2
},
32077 {"vfpv3", FPU_ARCH_VFP_V3
},
32078 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32079 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32080 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32081 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32082 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32083 {"arm1020t", FPU_ARCH_VFP_V1
},
32084 {"arm1020e", FPU_ARCH_VFP_V2
},
32085 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32086 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32087 {"maverick", FPU_ARCH_MAVERICK
},
32088 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32089 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32090 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32091 {"vfpv4", FPU_ARCH_VFP_V4
},
32092 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32093 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32094 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32095 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32096 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32097 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32098 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32099 {"crypto-neon-fp-armv8",
32100 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32101 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32102 {"crypto-neon-fp-armv8.1",
32103 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32104 {NULL
, ARM_ARCH_NONE
}
32107 struct arm_option_value_table
32113 static const struct arm_option_value_table arm_float_abis
[] =
32115 {"hard", ARM_FLOAT_ABI_HARD
},
32116 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32117 {"soft", ARM_FLOAT_ABI_SOFT
},
32122 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32123 static const struct arm_option_value_table arm_eabis
[] =
32125 {"gnu", EF_ARM_EABI_UNKNOWN
},
32126 {"4", EF_ARM_EABI_VER4
},
32127 {"5", EF_ARM_EABI_VER5
},
32132 struct arm_long_option_table
32134 const char * option
; /* Substring to match. */
32135 const char * help
; /* Help information. */
32136 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32137 const char * deprecated
; /* If non-null, print this message. */
32141 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32142 arm_feature_set
*ext_set
,
32143 const struct arm_ext_table
*ext_table
)
32145 /* We insist on extensions being specified in alphabetical order, and with
32146 extensions being added before being removed. We achieve this by having
32147 the global ARM_EXTENSIONS table in alphabetical order, and using the
32148 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32149 or removing it (0) and only allowing it to change in the order
32151 const struct arm_option_extension_value_table
* opt
= NULL
;
32152 const arm_feature_set arm_any
= ARM_ANY
;
32153 int adding_value
= -1;
32155 while (str
!= NULL
&& *str
!= 0)
32162 as_bad (_("invalid architectural extension"));
32167 ext
= strchr (str
, '+');
32172 len
= strlen (str
);
32174 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32176 if (adding_value
!= 0)
32179 opt
= arm_extensions
;
32187 if (adding_value
== -1)
32190 opt
= arm_extensions
;
32192 else if (adding_value
!= 1)
32194 as_bad (_("must specify extensions to add before specifying "
32195 "those to remove"));
32202 as_bad (_("missing architectural extension"));
32206 gas_assert (adding_value
!= -1);
32207 gas_assert (opt
!= NULL
);
32209 if (ext_table
!= NULL
)
32211 const struct arm_ext_table
* ext_opt
= ext_table
;
32212 bfd_boolean found
= FALSE
;
32213 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32214 if (ext_opt
->name_len
== len
32215 && strncmp (ext_opt
->name
, str
, len
) == 0)
32219 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32220 /* TODO: Option not supported. When we remove the
32221 legacy table this case should error out. */
32224 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32228 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32229 /* TODO: Option not supported. When we remove the
32230 legacy table this case should error out. */
32232 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32244 /* Scan over the options table trying to find an exact match. */
32245 for (; opt
->name
!= NULL
; opt
++)
32246 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32248 int i
, nb_allowed_archs
=
32249 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32250 /* Check we can apply the extension to this architecture. */
32251 for (i
= 0; i
< nb_allowed_archs
; i
++)
32254 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32256 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32259 if (i
== nb_allowed_archs
)
32261 as_bad (_("extension does not apply to the base architecture"));
32265 /* Add or remove the extension. */
32267 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32269 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32271 /* Allowing Thumb division instructions for ARMv7 in autodetection
32272 rely on this break so that duplicate extensions (extensions
32273 with the same name as a previous extension in the list) are not
32274 considered for command-line parsing. */
32278 if (opt
->name
== NULL
)
32280 /* Did we fail to find an extension because it wasn't specified in
32281 alphabetical order, or because it does not exist? */
32283 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32284 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32287 if (opt
->name
== NULL
)
32288 as_bad (_("unknown architectural extension `%s'"), str
);
32290 as_bad (_("architectural extensions must be specified in "
32291 "alphabetical order"));
32297 /* We should skip the extension we've just matched the next time
32309 arm_parse_fp16_opt (const char *str
)
32311 if (strcasecmp (str
, "ieee") == 0)
32312 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32313 else if (strcasecmp (str
, "alternative") == 0)
32314 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32317 as_bad (_("unrecognised float16 format \"%s\""), str
);
32325 arm_parse_cpu (const char *str
)
32327 const struct arm_cpu_option_table
*opt
;
32328 const char *ext
= strchr (str
, '+');
32334 len
= strlen (str
);
32338 as_bad (_("missing cpu name `%s'"), str
);
32342 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32343 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32345 mcpu_cpu_opt
= &opt
->value
;
32346 if (mcpu_ext_opt
== NULL
)
32347 mcpu_ext_opt
= XNEW (arm_feature_set
);
32348 *mcpu_ext_opt
= opt
->ext
;
32349 mcpu_fpu_opt
= &opt
->default_fpu
;
32350 if (opt
->canonical_name
)
32352 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32353 strcpy (selected_cpu_name
, opt
->canonical_name
);
32359 if (len
>= sizeof selected_cpu_name
)
32360 len
= (sizeof selected_cpu_name
) - 1;
32362 for (i
= 0; i
< len
; i
++)
32363 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32364 selected_cpu_name
[i
] = 0;
32368 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32373 as_bad (_("unknown cpu `%s'"), str
);
32378 arm_parse_arch (const char *str
)
32380 const struct arm_arch_option_table
*opt
;
32381 const char *ext
= strchr (str
, '+');
32387 len
= strlen (str
);
32391 as_bad (_("missing architecture name `%s'"), str
);
32395 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32396 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32398 march_cpu_opt
= &opt
->value
;
32399 if (march_ext_opt
== NULL
)
32400 march_ext_opt
= XNEW (arm_feature_set
);
32401 *march_ext_opt
= arm_arch_none
;
32402 march_fpu_opt
= &opt
->default_fpu
;
32403 selected_ctx_ext_table
= opt
->ext_table
;
32404 strcpy (selected_cpu_name
, opt
->name
);
32407 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32413 as_bad (_("unknown architecture `%s'\n"), str
);
32418 arm_parse_fpu (const char * str
)
32420 const struct arm_option_fpu_value_table
* opt
;
32422 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32423 if (streq (opt
->name
, str
))
32425 mfpu_opt
= &opt
->value
;
32429 as_bad (_("unknown floating point format `%s'\n"), str
);
32434 arm_parse_float_abi (const char * str
)
32436 const struct arm_option_value_table
* opt
;
32438 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32439 if (streq (opt
->name
, str
))
32441 mfloat_abi_opt
= opt
->value
;
32445 as_bad (_("unknown floating point abi `%s'\n"), str
);
32451 arm_parse_eabi (const char * str
)
32453 const struct arm_option_value_table
*opt
;
32455 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32456 if (streq (opt
->name
, str
))
32458 meabi_flags
= opt
->value
;
32461 as_bad (_("unknown EABI `%s'\n"), str
);
32467 arm_parse_it_mode (const char * str
)
32469 bfd_boolean ret
= TRUE
;
32471 if (streq ("arm", str
))
32472 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32473 else if (streq ("thumb", str
))
32474 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32475 else if (streq ("always", str
))
32476 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32477 else if (streq ("never", str
))
32478 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32481 as_bad (_("unknown implicit IT mode `%s', should be "\
32482 "arm, thumb, always, or never."), str
);
32490 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32492 codecomposer_syntax
= TRUE
;
32493 arm_comment_chars
[0] = ';';
32494 arm_line_separator_chars
[0] = 0;
32498 struct arm_long_option_table arm_long_opts
[] =
32500 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32501 arm_parse_cpu
, NULL
},
32502 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32503 arm_parse_arch
, NULL
},
32504 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32505 arm_parse_fpu
, NULL
},
32506 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32507 arm_parse_float_abi
, NULL
},
32509 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32510 arm_parse_eabi
, NULL
},
32512 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32513 arm_parse_it_mode
, NULL
},
32514 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32515 arm_ccs_mode
, NULL
},
32517 N_("[ieee|alternative]\n\
32518 set the encoding for half precision floating point "
32519 "numbers to IEEE\n\
32520 or Arm alternative format."),
32521 arm_parse_fp16_opt
, NULL
},
32522 {NULL
, NULL
, 0, NULL
}
32526 md_parse_option (int c
, const char * arg
)
32528 struct arm_option_table
*opt
;
32529 const struct arm_legacy_option_table
*fopt
;
32530 struct arm_long_option_table
*lopt
;
32536 target_big_endian
= 1;
32542 target_big_endian
= 0;
32546 case OPTION_FIX_V4BX
:
32554 #endif /* OBJ_ELF */
32557 /* Listing option. Just ignore these, we don't support additional
32562 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32564 if (c
== opt
->option
[0]
32565 && ((arg
== NULL
&& opt
->option
[1] == 0)
32566 || streq (arg
, opt
->option
+ 1)))
32568 /* If the option is deprecated, tell the user. */
32569 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32570 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32571 arg
? arg
: "", _(opt
->deprecated
));
32573 if (opt
->var
!= NULL
)
32574 *opt
->var
= opt
->value
;
32580 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32582 if (c
== fopt
->option
[0]
32583 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32584 || streq (arg
, fopt
->option
+ 1)))
32586 /* If the option is deprecated, tell the user. */
32587 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32588 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32589 arg
? arg
: "", _(fopt
->deprecated
));
32591 if (fopt
->var
!= NULL
)
32592 *fopt
->var
= &fopt
->value
;
32598 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32600 /* These options are expected to have an argument. */
32601 if (c
== lopt
->option
[0]
32603 && strncmp (arg
, lopt
->option
+ 1,
32604 strlen (lopt
->option
+ 1)) == 0)
32606 /* If the option is deprecated, tell the user. */
32607 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32608 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32609 _(lopt
->deprecated
));
32611 /* Call the sup-option parser. */
32612 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32623 md_show_usage (FILE * fp
)
32625 struct arm_option_table
*opt
;
32626 struct arm_long_option_table
*lopt
;
32628 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32630 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32631 if (opt
->help
!= NULL
)
32632 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32634 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32635 if (lopt
->help
!= NULL
)
32636 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32640 -EB assemble code for a big-endian cpu\n"));
32645 -EL assemble code for a little-endian cpu\n"));
32649 --fix-v4bx Allow BX in ARMv4 code\n"));
32653 --fdpic generate an FDPIC object file\n"));
32654 #endif /* OBJ_ELF */
32662 arm_feature_set flags
;
32663 } cpu_arch_ver_table
;
32665 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32666 chronologically for architectures, with an exception for ARMv6-M and
32667 ARMv6S-M due to legacy reasons. No new architecture should have a
32668 special case. This allows for build attribute selection results to be
32669 stable when new architectures are added. */
32670 static const cpu_arch_ver_table cpu_arch_ver
[] =
32672 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32673 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32674 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32675 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32676 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32677 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32678 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32679 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32680 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32681 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32682 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32683 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32684 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32685 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32686 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32687 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32688 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32689 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32690 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32691 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32692 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32693 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32694 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32695 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32697 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32698 always selected build attributes to match those of ARMv6-M
32699 (resp. ARMv6S-M). However, due to these architectures being a strict
32700 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32701 would be selected when fully respecting chronology of architectures.
32702 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32703 move them before ARMv7 architectures. */
32704 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32705 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32707 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32708 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32709 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32710 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32711 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32712 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32713 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32714 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32715 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32716 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32717 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32718 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32719 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32720 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32721 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32722 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32723 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32724 {-1, ARM_ARCH_NONE
}
32727 /* Set an attribute if it has not already been set by the user. */
32730 aeabi_set_attribute_int (int tag
, int value
)
32733 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32734 || !attributes_set_explicitly
[tag
])
32735 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32739 aeabi_set_attribute_string (int tag
, const char *value
)
32742 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32743 || !attributes_set_explicitly
[tag
])
32744 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32747 /* Return whether features in the *NEEDED feature set are available via
32748 extensions for the architecture whose feature set is *ARCH_FSET. */
32751 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32752 const arm_feature_set
*needed
)
32754 int i
, nb_allowed_archs
;
32755 arm_feature_set ext_fset
;
32756 const struct arm_option_extension_value_table
*opt
;
32758 ext_fset
= arm_arch_none
;
32759 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32761 /* Extension does not provide any feature we need. */
32762 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32766 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32767 for (i
= 0; i
< nb_allowed_archs
; i
++)
32770 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32773 /* Extension is available, add it. */
32774 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32775 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32779 /* Can we enable all features in *needed? */
32780 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32783 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32784 a given architecture feature set *ARCH_EXT_FSET including extension feature
32785 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32786 - if true, check for an exact match of the architecture modulo extensions;
32787 - otherwise, select build attribute value of the first superset
32788 architecture released so that results remains stable when new architectures
32790 For -march/-mcpu=all the build attribute value of the most featureful
32791 architecture is returned. Tag_CPU_arch_profile result is returned in
32795 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32796 const arm_feature_set
*ext_fset
,
32797 char *profile
, int exact_match
)
32799 arm_feature_set arch_fset
;
32800 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32802 /* Select most featureful architecture with all its extensions if building
32803 for -march=all as the feature sets used to set build attributes. */
32804 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32806 /* Force revisiting of decision for each new architecture. */
32807 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32809 return TAG_CPU_ARCH_V8
;
32812 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32814 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32816 arm_feature_set known_arch_fset
;
32818 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32821 /* Base architecture match user-specified architecture and
32822 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32823 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32828 /* Base architecture match user-specified architecture only
32829 (eg. ARMv6-M in the same case as above). Record it in case we
32830 find a match with above condition. */
32831 else if (p_ver_ret
== NULL
32832 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32838 /* Architecture has all features wanted. */
32839 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32841 arm_feature_set added_fset
;
32843 /* Compute features added by this architecture over the one
32844 recorded in p_ver_ret. */
32845 if (p_ver_ret
!= NULL
)
32846 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32848 /* First architecture that match incl. with extensions, or the
32849 only difference in features over the recorded match is
32850 features that were optional and are now mandatory. */
32851 if (p_ver_ret
== NULL
32852 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32858 else if (p_ver_ret
== NULL
)
32860 arm_feature_set needed_ext_fset
;
32862 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32864 /* Architecture has all features needed when using some
32865 extensions. Record it and continue searching in case there
32866 exist an architecture providing all needed features without
32867 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32869 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32876 if (p_ver_ret
== NULL
)
32880 /* Tag_CPU_arch_profile. */
32881 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32882 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32883 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32884 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
32886 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
32888 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32892 return p_ver_ret
->val
;
32895 /* Set the public EABI object attributes. */
32898 aeabi_set_public_attributes (void)
32900 char profile
= '\0';
32903 int fp16_optional
= 0;
32904 int skip_exact_match
= 0;
32905 arm_feature_set flags
, flags_arch
, flags_ext
;
32907 /* Autodetection mode, choose the architecture based the instructions
32909 if (no_cpu_selected ())
32911 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32913 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32914 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32916 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32917 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32919 /* Code run during relaxation relies on selected_cpu being set. */
32920 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32921 flags_ext
= arm_arch_none
;
32922 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32923 selected_ext
= flags_ext
;
32924 selected_cpu
= flags
;
32926 /* Otherwise, choose the architecture based on the capabilities of the
32930 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32931 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32932 flags_ext
= selected_ext
;
32933 flags
= selected_cpu
;
32935 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32937 /* Allow the user to override the reported architecture. */
32938 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32940 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32941 flags_ext
= arm_arch_none
;
32944 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32946 /* When this function is run again after relaxation has happened there is no
32947 way to determine whether an architecture or CPU was specified by the user:
32948 - selected_cpu is set above for relaxation to work;
32949 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32950 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32951 Therefore, if not in -march=all case we first try an exact match and fall
32952 back to autodetection. */
32953 if (!skip_exact_match
)
32954 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32956 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32958 as_bad (_("no architecture contains all the instructions used\n"));
32960 /* Tag_CPU_name. */
32961 if (selected_cpu_name
[0])
32965 q
= selected_cpu_name
;
32966 if (strncmp (q
, "armv", 4) == 0)
32971 for (i
= 0; q
[i
]; i
++)
32972 q
[i
] = TOUPPER (q
[i
]);
32974 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32977 /* Tag_CPU_arch. */
32978 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32980 /* Tag_CPU_arch_profile. */
32981 if (profile
!= '\0')
32982 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32984 /* Tag_DSP_extension. */
32985 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32986 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32988 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32989 /* Tag_ARM_ISA_use. */
32990 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32991 || ARM_FEATURE_ZERO (flags_arch
))
32992 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32994 /* Tag_THUMB_ISA_use. */
32995 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32996 || ARM_FEATURE_ZERO (flags_arch
))
33000 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33001 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33003 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33007 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33010 /* Tag_VFP_arch. */
33011 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33012 aeabi_set_attribute_int (Tag_VFP_arch
,
33013 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33015 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33016 aeabi_set_attribute_int (Tag_VFP_arch
,
33017 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33019 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33022 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33024 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33026 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33029 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33030 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33031 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33032 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33033 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33035 /* Tag_ABI_HardFP_use. */
33036 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33037 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33038 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33040 /* Tag_WMMX_arch. */
33041 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33042 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33043 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33044 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33046 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33047 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33048 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33049 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33050 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33051 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33053 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33055 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33059 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33064 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33065 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33066 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33067 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33069 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33070 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33071 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33075 We set Tag_DIV_use to two when integer divide instructions have been used
33076 in ARM state, or when Thumb integer divide instructions have been used,
33077 but we have no architecture profile set, nor have we any ARM instructions.
33079 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33080 by the base architecture.
33082 For new architectures we will have to check these tests. */
33083 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33084 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33085 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33086 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33087 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33088 || (profile
== '\0'
33089 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33090 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33091 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33093 /* Tag_MP_extension_use. */
33094 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33095 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33097 /* Tag Virtualization_use. */
33098 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33100 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33103 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33105 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33106 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33109 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33110 finished and free extension feature bits which will not be used anymore. */
33113 arm_md_post_relax (void)
33115 aeabi_set_public_attributes ();
33116 XDELETE (mcpu_ext_opt
);
33117 mcpu_ext_opt
= NULL
;
33118 XDELETE (march_ext_opt
);
33119 march_ext_opt
= NULL
;
33122 /* Add the default contents for the .ARM.attributes section. */
33127 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33130 aeabi_set_public_attributes ();
33132 #endif /* OBJ_ELF */
33134 /* Parse a .cpu directive. */
33137 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33139 const struct arm_cpu_option_table
*opt
;
33143 name
= input_line_pointer
;
33144 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33145 input_line_pointer
++;
33146 saved_char
= *input_line_pointer
;
33147 *input_line_pointer
= 0;
33149 /* Skip the first "all" entry. */
33150 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33151 if (streq (opt
->name
, name
))
33153 selected_arch
= opt
->value
;
33154 selected_ext
= opt
->ext
;
33155 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33156 if (opt
->canonical_name
)
33157 strcpy (selected_cpu_name
, opt
->canonical_name
);
33161 for (i
= 0; opt
->name
[i
]; i
++)
33162 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33164 selected_cpu_name
[i
] = 0;
33166 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33168 *input_line_pointer
= saved_char
;
33169 demand_empty_rest_of_line ();
33172 as_bad (_("unknown cpu `%s'"), name
);
33173 *input_line_pointer
= saved_char
;
33174 ignore_rest_of_line ();
33177 /* Parse a .arch directive. */
33180 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33182 const struct arm_arch_option_table
*opt
;
33186 name
= input_line_pointer
;
33187 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33188 input_line_pointer
++;
33189 saved_char
= *input_line_pointer
;
33190 *input_line_pointer
= 0;
33192 /* Skip the first "all" entry. */
33193 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33194 if (streq (opt
->name
, name
))
33196 selected_arch
= opt
->value
;
33197 selected_ctx_ext_table
= opt
->ext_table
;
33198 selected_ext
= arm_arch_none
;
33199 selected_cpu
= selected_arch
;
33200 strcpy (selected_cpu_name
, opt
->name
);
33201 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33202 *input_line_pointer
= saved_char
;
33203 demand_empty_rest_of_line ();
33207 as_bad (_("unknown architecture `%s'\n"), name
);
33208 *input_line_pointer
= saved_char
;
33209 ignore_rest_of_line ();
33212 /* Parse a .object_arch directive. */
33215 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33217 const struct arm_arch_option_table
*opt
;
33221 name
= input_line_pointer
;
33222 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33223 input_line_pointer
++;
33224 saved_char
= *input_line_pointer
;
33225 *input_line_pointer
= 0;
33227 /* Skip the first "all" entry. */
33228 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33229 if (streq (opt
->name
, name
))
33231 selected_object_arch
= opt
->value
;
33232 *input_line_pointer
= saved_char
;
33233 demand_empty_rest_of_line ();
33237 as_bad (_("unknown architecture `%s'\n"), name
);
33238 *input_line_pointer
= saved_char
;
33239 ignore_rest_of_line ();
33242 /* Parse a .arch_extension directive. */
33245 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33247 const struct arm_option_extension_value_table
*opt
;
33250 int adding_value
= 1;
33252 name
= input_line_pointer
;
33253 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33254 input_line_pointer
++;
33255 saved_char
= *input_line_pointer
;
33256 *input_line_pointer
= 0;
33258 if (strlen (name
) >= 2
33259 && strncmp (name
, "no", 2) == 0)
33265 /* Check the context specific extension table */
33266 if (selected_ctx_ext_table
)
33268 const struct arm_ext_table
* ext_opt
;
33269 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33271 if (streq (ext_opt
->name
, name
))
33275 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33276 /* TODO: Option not supported. When we remove the
33277 legacy table this case should error out. */
33279 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33283 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33285 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33286 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33287 *input_line_pointer
= saved_char
;
33288 demand_empty_rest_of_line ();
33294 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33295 if (streq (opt
->name
, name
))
33297 int i
, nb_allowed_archs
=
33298 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33299 for (i
= 0; i
< nb_allowed_archs
; i
++)
33302 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33304 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33308 if (i
== nb_allowed_archs
)
33310 as_bad (_("architectural extension `%s' is not allowed for the "
33311 "current base architecture"), name
);
33316 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33319 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33321 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33322 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33323 *input_line_pointer
= saved_char
;
33324 demand_empty_rest_of_line ();
33325 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33326 on this return so that duplicate extensions (extensions with the
33327 same name as a previous extension in the list) are not considered
33328 for command-line parsing. */
33332 if (opt
->name
== NULL
)
33333 as_bad (_("unknown architecture extension `%s'\n"), name
);
33335 *input_line_pointer
= saved_char
;
33336 ignore_rest_of_line ();
33339 /* Parse a .fpu directive. */
33342 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33344 const struct arm_option_fpu_value_table
*opt
;
33348 name
= input_line_pointer
;
33349 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33350 input_line_pointer
++;
33351 saved_char
= *input_line_pointer
;
33352 *input_line_pointer
= 0;
33354 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33355 if (streq (opt
->name
, name
))
33357 selected_fpu
= opt
->value
;
33358 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33359 #ifndef CPU_DEFAULT
33360 if (no_cpu_selected ())
33361 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33364 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33365 *input_line_pointer
= saved_char
;
33366 demand_empty_rest_of_line ();
33370 as_bad (_("unknown floating point format `%s'\n"), name
);
33371 *input_line_pointer
= saved_char
;
33372 ignore_rest_of_line ();
33375 /* Copy symbol information. */
33378 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33380 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33384 /* Given a symbolic attribute NAME, return the proper integer value.
33385 Returns -1 if the attribute is not known. */
33388 arm_convert_symbolic_attribute (const char *name
)
33390 static const struct
33395 attribute_table
[] =
33397 /* When you modify this table you should
33398 also modify the list in doc/c-arm.texi. */
33399 #define T(tag) {#tag, tag}
33400 T (Tag_CPU_raw_name
),
33403 T (Tag_CPU_arch_profile
),
33404 T (Tag_ARM_ISA_use
),
33405 T (Tag_THUMB_ISA_use
),
33409 T (Tag_Advanced_SIMD_arch
),
33410 T (Tag_PCS_config
),
33411 T (Tag_ABI_PCS_R9_use
),
33412 T (Tag_ABI_PCS_RW_data
),
33413 T (Tag_ABI_PCS_RO_data
),
33414 T (Tag_ABI_PCS_GOT_use
),
33415 T (Tag_ABI_PCS_wchar_t
),
33416 T (Tag_ABI_FP_rounding
),
33417 T (Tag_ABI_FP_denormal
),
33418 T (Tag_ABI_FP_exceptions
),
33419 T (Tag_ABI_FP_user_exceptions
),
33420 T (Tag_ABI_FP_number_model
),
33421 T (Tag_ABI_align_needed
),
33422 T (Tag_ABI_align8_needed
),
33423 T (Tag_ABI_align_preserved
),
33424 T (Tag_ABI_align8_preserved
),
33425 T (Tag_ABI_enum_size
),
33426 T (Tag_ABI_HardFP_use
),
33427 T (Tag_ABI_VFP_args
),
33428 T (Tag_ABI_WMMX_args
),
33429 T (Tag_ABI_optimization_goals
),
33430 T (Tag_ABI_FP_optimization_goals
),
33431 T (Tag_compatibility
),
33432 T (Tag_CPU_unaligned_access
),
33433 T (Tag_FP_HP_extension
),
33434 T (Tag_VFP_HP_extension
),
33435 T (Tag_ABI_FP_16bit_format
),
33436 T (Tag_MPextension_use
),
33438 T (Tag_nodefaults
),
33439 T (Tag_also_compatible_with
),
33440 T (Tag_conformance
),
33442 T (Tag_Virtualization_use
),
33443 T (Tag_DSP_extension
),
33445 /* We deliberately do not include Tag_MPextension_use_legacy. */
33453 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33454 if (streq (name
, attribute_table
[i
].name
))
33455 return attribute_table
[i
].tag
;
33460 /* Apply sym value for relocations only in the case that they are for
33461 local symbols in the same segment as the fixup and you have the
33462 respective architectural feature for blx and simple switches. */
33465 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33468 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33469 /* PR 17444: If the local symbol is in a different section then a reloc
33470 will always be generated for it, so applying the symbol value now
33471 will result in a double offset being stored in the relocation. */
33472 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33473 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33475 switch (fixP
->fx_r_type
)
33477 case BFD_RELOC_ARM_PCREL_BLX
:
33478 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33479 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33483 case BFD_RELOC_ARM_PCREL_CALL
:
33484 case BFD_RELOC_THUMB_PCREL_BLX
:
33485 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33496 #endif /* OBJ_ELF */