1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNSDQ
, /* Neon single, double or quad precision register */
6906 OP_RNSC
, /* Neon scalar D[X] */
6907 OP_RVC
, /* VFP control register */
6908 OP_RMF
, /* Maverick F register */
6909 OP_RMD
, /* Maverick D register */
6910 OP_RMFX
, /* Maverick FX register */
6911 OP_RMDX
, /* Maverick DX register */
6912 OP_RMAX
, /* Maverick AX register */
6913 OP_RMDS
, /* Maverick DSPSC register */
6914 OP_RIWR
, /* iWMMXt wR register */
6915 OP_RIWC
, /* iWMMXt wC register */
6916 OP_RIWG
, /* iWMMXt wCG register */
6917 OP_RXA
, /* XScale accumulator register */
6919 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6921 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6923 OP_RMQ
, /* MVE vector register. */
6924 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 /* New operands for Armv8.1-M Mainline. */
6927 OP_LR
, /* ARM LR register */
6928 OP_RRe
, /* ARM register, only even numbered. */
6929 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6930 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6932 OP_REGLST
, /* ARM register list */
6933 OP_CLRMLST
, /* CLRM register list */
6934 OP_VRSLST
, /* VFP single-precision register list */
6935 OP_VRDLST
, /* VFP double-precision register list */
6936 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6937 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6938 OP_NSTRLST
, /* Neon element/structure list */
6939 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6940 OP_MSTRLST2
, /* MVE vector list with two elements. */
6941 OP_MSTRLST4
, /* MVE vector list with four elements. */
6943 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6944 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6945 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6946 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6948 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6949 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6950 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6953 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6954 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6955 OP_VMOV
, /* Neon VMOV operands. */
6956 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6957 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6958 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6959 OP_VLDR
, /* VLDR operand. */
6961 OP_I0
, /* immediate zero */
6962 OP_I7
, /* immediate value 0 .. 7 */
6963 OP_I15
, /* 0 .. 15 */
6964 OP_I16
, /* 1 .. 16 */
6965 OP_I16z
, /* 0 .. 16 */
6966 OP_I31
, /* 0 .. 31 */
6967 OP_I31w
, /* 0 .. 31, optional trailing ! */
6968 OP_I32
, /* 1 .. 32 */
6969 OP_I32z
, /* 0 .. 32 */
6970 OP_I63
, /* 0 .. 63 */
6971 OP_I63s
, /* -64 .. 63 */
6972 OP_I64
, /* 1 .. 64 */
6973 OP_I64z
, /* 0 .. 64 */
6974 OP_I255
, /* 0 .. 255 */
6976 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6977 OP_I7b
, /* 0 .. 7 */
6978 OP_I15b
, /* 0 .. 15 */
6979 OP_I31b
, /* 0 .. 31 */
6981 OP_SH
, /* shifter operand */
6982 OP_SHG
, /* shifter operand with possible group relocation */
6983 OP_ADDR
, /* Memory address expression (any mode) */
6984 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6985 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6986 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6987 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6988 OP_EXP
, /* arbitrary expression */
6989 OP_EXPi
, /* same, with optional immediate prefix */
6990 OP_EXPr
, /* same, with optional relocation suffix */
6991 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6992 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6993 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6994 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6996 OP_CPSF
, /* CPS flags */
6997 OP_ENDI
, /* Endianness specifier */
6998 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6999 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7000 OP_COND
, /* conditional code */
7001 OP_TB
, /* Table branch. */
7003 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7005 OP_RRnpc_I0
, /* ARM register or literal 0 */
7006 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7007 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7008 OP_RF_IF
, /* FPA register or immediate */
7009 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7010 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7012 /* Optional operands. */
7013 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7014 OP_oI31b
, /* 0 .. 31 */
7015 OP_oI32b
, /* 1 .. 32 */
7016 OP_oI32z
, /* 0 .. 32 */
7017 OP_oIffffb
, /* 0 .. 65535 */
7018 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7020 OP_oRR
, /* ARM register */
7021 OP_oLR
, /* ARM LR register */
7022 OP_oRRnpc
, /* ARM register, not the PC */
7023 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7024 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7025 OP_oRND
, /* Optional Neon double precision register */
7026 OP_oRNQ
, /* Optional Neon quad precision register */
7027 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7028 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7029 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7030 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7032 OP_oSHll
, /* LSL immediate */
7033 OP_oSHar
, /* ASR immediate */
7034 OP_oSHllar
, /* LSL or ASR immediate */
7035 OP_oROR
, /* ROR 0/8/16/24 */
7036 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7038 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7040 /* Some pre-defined mixed (ARM/THUMB) operands. */
7041 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7042 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7043 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7045 OP_FIRST_OPTIONAL
= OP_oI7b
7048 /* Generic instruction operand parser. This does no encoding and no
7049 semantic validation; it merely squirrels values away in the inst
7050 structure. Returns SUCCESS or FAIL depending on whether the
7051 specified grammar matched. */
7053 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7055 unsigned const int *upat
= pattern
;
7056 char *backtrack_pos
= 0;
7057 const char *backtrack_error
= 0;
7058 int i
, val
= 0, backtrack_index
= 0;
7059 enum arm_reg_type rtype
;
7060 parse_operand_result result
;
7061 unsigned int op_parse_code
;
7062 bfd_boolean partial_match
;
7064 #define po_char_or_fail(chr) \
7067 if (skip_past_char (&str, chr) == FAIL) \
7072 #define po_reg_or_fail(regtype) \
7075 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7076 & inst.operands[i].vectype); \
7079 first_error (_(reg_expected_msgs[regtype])); \
7082 inst.operands[i].reg = val; \
7083 inst.operands[i].isreg = 1; \
7084 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7085 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7086 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7087 || rtype == REG_TYPE_VFD \
7088 || rtype == REG_TYPE_NQ); \
7089 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7093 #define po_reg_or_goto(regtype, label) \
7096 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7097 & inst.operands[i].vectype); \
7101 inst.operands[i].reg = val; \
7102 inst.operands[i].isreg = 1; \
7103 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7104 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7105 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7106 || rtype == REG_TYPE_VFD \
7107 || rtype == REG_TYPE_NQ); \
7108 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7112 #define po_imm_or_fail(min, max, popt) \
7115 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7117 inst.operands[i].imm = val; \
7121 #define po_scalar_or_goto(elsz, label, reg_type) \
7124 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7128 inst.operands[i].reg = val; \
7129 inst.operands[i].isscalar = 1; \
7133 #define po_misc_or_fail(expr) \
7141 #define po_misc_or_fail_no_backtrack(expr) \
7145 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7146 backtrack_pos = 0; \
7147 if (result != PARSE_OPERAND_SUCCESS) \
7152 #define po_barrier_or_imm(str) \
7155 val = parse_barrier (&str); \
7156 if (val == FAIL && ! ISALPHA (*str)) \
7159 /* ISB can only take SY as an option. */ \
7160 || ((inst.instruction & 0xf0) == 0x60 \
7163 inst.error = _("invalid barrier type"); \
7164 backtrack_pos = 0; \
7170 skip_whitespace (str
);
7172 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7174 op_parse_code
= upat
[i
];
7175 if (op_parse_code
>= 1<<16)
7176 op_parse_code
= thumb
? (op_parse_code
>> 16)
7177 : (op_parse_code
& ((1<<16)-1));
7179 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7181 /* Remember where we are in case we need to backtrack. */
7182 backtrack_pos
= str
;
7183 backtrack_error
= inst
.error
;
7184 backtrack_index
= i
;
7187 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7188 po_char_or_fail (',');
7190 switch (op_parse_code
)
7202 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7203 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7204 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7205 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7206 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7207 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7210 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7214 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7217 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7219 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7221 /* Also accept generic coprocessor regs for unknown registers. */
7223 po_reg_or_fail (REG_TYPE_CN
);
7225 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7226 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7227 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7228 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7229 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7230 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7231 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7232 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7233 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7234 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7237 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7240 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7241 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7244 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7248 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7250 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7253 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7255 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7258 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7260 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7265 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7268 po_reg_or_fail (REG_TYPE_NSDQ
);
7272 po_reg_or_fail (REG_TYPE_MQ
);
7274 /* Neon scalar. Using an element size of 8 means that some invalid
7275 scalars are accepted here, so deal with those in later code. */
7276 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7280 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7283 po_imm_or_fail (0, 0, TRUE
);
7288 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7292 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7297 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7300 if (parse_ifimm_zero (&str
))
7301 inst
.operands
[i
].imm
= 0;
7305 = _("only floating point zero is allowed as immediate value");
7313 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7316 po_reg_or_fail (REG_TYPE_RN
);
7320 case OP_RNSDQ_RNSC_MQ
:
7321 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7326 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7330 po_reg_or_fail (REG_TYPE_NSDQ
);
7337 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7340 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7343 po_reg_or_fail (REG_TYPE_NSD
);
7349 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7352 po_reg_or_fail (REG_TYPE_NDQ
);
7358 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7361 po_reg_or_fail (REG_TYPE_VFD
);
7366 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7367 not careful then bad things might happen. */
7368 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7373 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7376 /* There's a possibility of getting a 64-bit immediate here, so
7377 we need special handling. */
7378 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7381 inst
.error
= _("immediate value is out of range");
7389 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7392 po_imm_or_fail (0, 63, TRUE
);
7397 po_char_or_fail ('[');
7398 po_reg_or_fail (REG_TYPE_RN
);
7399 po_char_or_fail (']');
7405 po_reg_or_fail (REG_TYPE_RN
);
7406 if (skip_past_char (&str
, '!') == SUCCESS
)
7407 inst
.operands
[i
].writeback
= 1;
7411 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7412 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7413 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7414 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7415 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7416 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7417 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7418 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7419 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7420 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7421 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7422 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7424 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7426 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7427 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7429 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7430 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7431 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7432 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7434 /* Immediate variants */
7436 po_char_or_fail ('{');
7437 po_imm_or_fail (0, 255, TRUE
);
7438 po_char_or_fail ('}');
7442 /* The expression parser chokes on a trailing !, so we have
7443 to find it first and zap it. */
7446 while (*s
&& *s
!= ',')
7451 inst
.operands
[i
].writeback
= 1;
7453 po_imm_or_fail (0, 31, TRUE
);
7461 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7466 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7471 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7473 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7475 val
= parse_reloc (&str
);
7478 inst
.error
= _("unrecognized relocation suffix");
7481 else if (val
!= BFD_RELOC_UNUSED
)
7483 inst
.operands
[i
].imm
= val
;
7484 inst
.operands
[i
].hasreloc
= 1;
7490 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7492 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7494 inst
.operands
[i
].hasreloc
= 1;
7496 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7498 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7499 inst
.operands
[i
].hasreloc
= 0;
7503 /* Operand for MOVW or MOVT. */
7505 po_misc_or_fail (parse_half (&str
));
7508 /* Register or expression. */
7509 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7510 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7512 /* Register or immediate. */
7513 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7514 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7516 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7518 if (!is_immediate_prefix (*str
))
7521 val
= parse_fpa_immediate (&str
);
7524 /* FPA immediates are encoded as registers 8-15.
7525 parse_fpa_immediate has already applied the offset. */
7526 inst
.operands
[i
].reg
= val
;
7527 inst
.operands
[i
].isreg
= 1;
7530 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7531 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7533 /* Two kinds of register. */
7536 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7538 || (rege
->type
!= REG_TYPE_MMXWR
7539 && rege
->type
!= REG_TYPE_MMXWC
7540 && rege
->type
!= REG_TYPE_MMXWCG
))
7542 inst
.error
= _("iWMMXt data or control register expected");
7545 inst
.operands
[i
].reg
= rege
->number
;
7546 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7552 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7554 || (rege
->type
!= REG_TYPE_MMXWC
7555 && rege
->type
!= REG_TYPE_MMXWCG
))
7557 inst
.error
= _("iWMMXt control register expected");
7560 inst
.operands
[i
].reg
= rege
->number
;
7561 inst
.operands
[i
].isreg
= 1;
7566 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7567 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7568 case OP_oROR
: val
= parse_ror (&str
); break;
7570 case OP_COND
: val
= parse_cond (&str
); break;
7571 case OP_oBARRIER_I15
:
7572 po_barrier_or_imm (str
); break;
7574 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7580 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7581 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7583 inst
.error
= _("Banked registers are not available with this "
7589 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7593 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7596 val
= parse_sys_vldr_vstr (&str
);
7600 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7603 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7605 if (strncasecmp (str
, "APSR_", 5) == 0)
7612 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7613 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7614 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7615 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7616 default: found
= 16;
7620 inst
.operands
[i
].isvec
= 1;
7621 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7622 inst
.operands
[i
].reg
= REG_PC
;
7629 po_misc_or_fail (parse_tb (&str
));
7632 /* Register lists. */
7634 val
= parse_reg_list (&str
, REGLIST_RN
);
7637 inst
.operands
[i
].writeback
= 1;
7643 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7647 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7652 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7657 /* Allow Q registers too. */
7658 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7659 REGLIST_NEON_D
, &partial_match
);
7663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7664 REGLIST_VFP_S
, &partial_match
);
7665 inst
.operands
[i
].issingle
= 1;
7670 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7671 REGLIST_VFP_D_VPR
, &partial_match
);
7672 if (val
== FAIL
&& !partial_match
)
7675 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7676 REGLIST_VFP_S_VPR
, &partial_match
);
7677 inst
.operands
[i
].issingle
= 1;
7682 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7683 REGLIST_NEON_D
, &partial_match
);
7688 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7689 1, &inst
.operands
[i
].vectype
);
7690 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7694 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7695 0, &inst
.operands
[i
].vectype
);
7698 /* Addressing modes */
7700 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7704 po_misc_or_fail (parse_address (&str
, i
));
7708 po_misc_or_fail_no_backtrack (
7709 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7713 po_misc_or_fail_no_backtrack (
7714 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7718 po_misc_or_fail_no_backtrack (
7719 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7723 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7727 po_misc_or_fail_no_backtrack (
7728 parse_shifter_operand_group_reloc (&str
, i
));
7732 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7736 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7740 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7745 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7748 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7751 po_reg_or_fail (REG_TYPE_ZR
);
7755 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7758 /* Various value-based sanity checks and shared operations. We
7759 do not signal immediate failures for the register constraints;
7760 this allows a syntax error to take precedence. */
7761 switch (op_parse_code
)
7769 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7770 inst
.error
= BAD_PC
;
7775 if (inst
.operands
[i
].isreg
)
7777 if (inst
.operands
[i
].reg
== REG_PC
)
7778 inst
.error
= BAD_PC
;
7779 else if (inst
.operands
[i
].reg
== REG_SP
7780 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7781 relaxed since ARMv8-A. */
7782 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7785 inst
.error
= BAD_SP
;
7791 if (inst
.operands
[i
].isreg
7792 && inst
.operands
[i
].reg
== REG_PC
7793 && (inst
.operands
[i
].writeback
|| thumb
))
7794 inst
.error
= BAD_PC
;
7799 if (inst
.operands
[i
].isreg
)
7809 case OP_oBARRIER_I15
:
7822 inst
.operands
[i
].imm
= val
;
7827 if (inst
.operands
[i
].reg
!= REG_LR
)
7828 inst
.error
= _("operand must be LR register");
7833 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7834 inst
.error
= BAD_PC
;
7838 if (inst
.operands
[i
].isreg
7839 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7840 inst
.error
= BAD_ODD
;
7844 if (inst
.operands
[i
].isreg
)
7846 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7847 inst
.error
= BAD_EVEN
;
7848 else if (inst
.operands
[i
].reg
== REG_SP
)
7849 as_tsktsk (MVE_BAD_SP
);
7850 else if (inst
.operands
[i
].reg
== REG_PC
)
7851 inst
.error
= BAD_PC
;
7859 /* If we get here, this operand was successfully parsed. */
7860 inst
.operands
[i
].present
= 1;
7864 inst
.error
= BAD_ARGS
;
7869 /* The parse routine should already have set inst.error, but set a
7870 default here just in case. */
7872 inst
.error
= BAD_SYNTAX
;
7876 /* Do not backtrack over a trailing optional argument that
7877 absorbed some text. We will only fail again, with the
7878 'garbage following instruction' error message, which is
7879 probably less helpful than the current one. */
7880 if (backtrack_index
== i
&& backtrack_pos
!= str
7881 && upat
[i
+1] == OP_stop
)
7884 inst
.error
= BAD_SYNTAX
;
7888 /* Try again, skipping the optional argument at backtrack_pos. */
7889 str
= backtrack_pos
;
7890 inst
.error
= backtrack_error
;
7891 inst
.operands
[backtrack_index
].present
= 0;
7892 i
= backtrack_index
;
7896 /* Check that we have parsed all the arguments. */
7897 if (*str
!= '\0' && !inst
.error
)
7898 inst
.error
= _("garbage following instruction");
7900 return inst
.error
? FAIL
: SUCCESS
;
7903 #undef po_char_or_fail
7904 #undef po_reg_or_fail
7905 #undef po_reg_or_goto
7906 #undef po_imm_or_fail
7907 #undef po_scalar_or_fail
7908 #undef po_barrier_or_imm
7910 /* Shorthand macro for instruction encoding functions issuing errors. */
7911 #define constraint(expr, err) \
7922 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7923 instructions are unpredictable if these registers are used. This
7924 is the BadReg predicate in ARM's Thumb-2 documentation.
7926 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7927 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7928 #define reject_bad_reg(reg) \
7930 if (reg == REG_PC) \
7932 inst.error = BAD_PC; \
7935 else if (reg == REG_SP \
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7938 inst.error = BAD_SP; \
7943 /* If REG is R13 (the stack pointer), warn that its use is
7945 #define warn_deprecated_sp(reg) \
7947 if (warn_on_deprecated && reg == REG_SP) \
7948 as_tsktsk (_("use of r13 is deprecated")); \
7951 /* Functions for operand encoding. ARM, then Thumb. */
7953 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7955 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7957 The only binary encoding difference is the Coprocessor number. Coprocessor
7958 9 is used for half-precision calculations or conversions. The format of the
7959 instruction is the same as the equivalent Coprocessor 10 instruction that
7960 exists for Single-Precision operation. */
7963 do_scalar_fp16_v82_encode (void)
7965 if (inst
.cond
< COND_ALWAYS
)
7966 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7967 " the behaviour is UNPREDICTABLE"));
7968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7971 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7972 mark_feature_used (&arm_ext_fp16
);
7975 /* If VAL can be encoded in the immediate field of an ARM instruction,
7976 return the encoded form. Otherwise, return FAIL. */
7979 encode_arm_immediate (unsigned int val
)
7986 for (i
= 2; i
< 32; i
+= 2)
7987 if ((a
= rotate_left (val
, i
)) <= 0xff)
7988 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7993 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7994 return the encoded form. Otherwise, return FAIL. */
7996 encode_thumb32_immediate (unsigned int val
)
8003 for (i
= 1; i
<= 24; i
++)
8006 if ((val
& ~(0xff << i
)) == 0)
8007 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8011 if (val
== ((a
<< 16) | a
))
8013 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8017 if (val
== ((a
<< 16) | a
))
8018 return 0x200 | (a
>> 8);
8022 /* Encode a VFP SP or DP register number into inst.instruction. */
8025 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8027 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8033 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8036 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8041 first_error (_("D register out of range for selected VFP version"));
8049 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8053 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8057 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8061 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8065 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8069 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8077 /* Encode a <shift> in an ARM-format instruction. The immediate,
8078 if any, is handled by md_apply_fix. */
8080 encode_arm_shift (int i
)
8082 /* register-shifted register. */
8083 if (inst
.operands
[i
].immisreg
)
8086 for (op_index
= 0; op_index
<= i
; ++op_index
)
8088 /* Check the operand only when it's presented. In pre-UAL syntax,
8089 if the destination register is the same as the first operand, two
8090 register form of the instruction can be used. */
8091 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8092 && inst
.operands
[op_index
].reg
== REG_PC
)
8093 as_warn (UNPRED_REG ("r15"));
8096 if (inst
.operands
[i
].imm
== REG_PC
)
8097 as_warn (UNPRED_REG ("r15"));
8100 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8101 inst
.instruction
|= SHIFT_ROR
<< 5;
8104 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8105 if (inst
.operands
[i
].immisreg
)
8107 inst
.instruction
|= SHIFT_BY_REG
;
8108 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8111 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8116 encode_arm_shifter_operand (int i
)
8118 if (inst
.operands
[i
].isreg
)
8120 inst
.instruction
|= inst
.operands
[i
].reg
;
8121 encode_arm_shift (i
);
8125 inst
.instruction
|= INST_IMMEDIATE
;
8126 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8127 inst
.instruction
|= inst
.operands
[i
].imm
;
8131 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8133 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8136 Generate an error if the operand is not a register. */
8137 constraint (!inst
.operands
[i
].isreg
,
8138 _("Instruction does not support =N addresses"));
8140 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8142 if (inst
.operands
[i
].preind
)
8146 inst
.error
= _("instruction does not accept preindexed addressing");
8149 inst
.instruction
|= PRE_INDEX
;
8150 if (inst
.operands
[i
].writeback
)
8151 inst
.instruction
|= WRITE_BACK
;
8154 else if (inst
.operands
[i
].postind
)
8156 gas_assert (inst
.operands
[i
].writeback
);
8158 inst
.instruction
|= WRITE_BACK
;
8160 else /* unindexed - only for coprocessor */
8162 inst
.error
= _("instruction does not accept unindexed addressing");
8166 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8167 && (((inst
.instruction
& 0x000f0000) >> 16)
8168 == ((inst
.instruction
& 0x0000f000) >> 12)))
8169 as_warn ((inst
.instruction
& LOAD_BIT
)
8170 ? _("destination register same as write-back base")
8171 : _("source register same as write-back base"));
8174 /* inst.operands[i] was set up by parse_address. Encode it into an
8175 ARM-format mode 2 load or store instruction. If is_t is true,
8176 reject forms that cannot be used with a T instruction (i.e. not
8179 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8181 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8183 encode_arm_addr_mode_common (i
, is_t
);
8185 if (inst
.operands
[i
].immisreg
)
8187 constraint ((inst
.operands
[i
].imm
== REG_PC
8188 || (is_pc
&& inst
.operands
[i
].writeback
)),
8190 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8191 inst
.instruction
|= inst
.operands
[i
].imm
;
8192 if (!inst
.operands
[i
].negative
)
8193 inst
.instruction
|= INDEX_UP
;
8194 if (inst
.operands
[i
].shifted
)
8196 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8197 inst
.instruction
|= SHIFT_ROR
<< 5;
8200 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8201 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8205 else /* immediate offset in inst.relocs[0] */
8207 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8209 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8211 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8212 cannot use PC in addressing.
8213 PC cannot be used in writeback addressing, either. */
8214 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8217 /* Use of PC in str is deprecated for ARMv7. */
8218 if (warn_on_deprecated
8220 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8221 as_tsktsk (_("use of PC in this instruction is deprecated"));
8224 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8226 /* Prefer + for zero encoded value. */
8227 if (!inst
.operands
[i
].negative
)
8228 inst
.instruction
|= INDEX_UP
;
8229 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8234 /* inst.operands[i] was set up by parse_address. Encode it into an
8235 ARM-format mode 3 load or store instruction. Reject forms that
8236 cannot be used with such instructions. If is_t is true, reject
8237 forms that cannot be used with a T instruction (i.e. not
8240 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8242 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8244 inst
.error
= _("instruction does not accept scaled register index");
8248 encode_arm_addr_mode_common (i
, is_t
);
8250 if (inst
.operands
[i
].immisreg
)
8252 constraint ((inst
.operands
[i
].imm
== REG_PC
8253 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8255 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8257 inst
.instruction
|= inst
.operands
[i
].imm
;
8258 if (!inst
.operands
[i
].negative
)
8259 inst
.instruction
|= INDEX_UP
;
8261 else /* immediate offset in inst.relocs[0] */
8263 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8264 && inst
.operands
[i
].writeback
),
8266 inst
.instruction
|= HWOFFSET_IMM
;
8267 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8269 /* Prefer + for zero encoded value. */
8270 if (!inst
.operands
[i
].negative
)
8271 inst
.instruction
|= INDEX_UP
;
8273 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8278 /* Write immediate bits [7:0] to the following locations:
8280 |28/24|23 19|18 16|15 4|3 0|
8281 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8283 This function is used by VMOV/VMVN/VORR/VBIC. */
8286 neon_write_immbits (unsigned immbits
)
8288 inst
.instruction
|= immbits
& 0xf;
8289 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8290 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8293 /* Invert low-order SIZE bits of XHI:XLO. */
8296 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8298 unsigned immlo
= xlo
? *xlo
: 0;
8299 unsigned immhi
= xhi
? *xhi
: 0;
8304 immlo
= (~immlo
) & 0xff;
8308 immlo
= (~immlo
) & 0xffff;
8312 immhi
= (~immhi
) & 0xffffffff;
8316 immlo
= (~immlo
) & 0xffffffff;
8330 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8334 neon_bits_same_in_bytes (unsigned imm
)
8336 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8337 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8338 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8339 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8342 /* For immediate of above form, return 0bABCD. */
8345 neon_squash_bits (unsigned imm
)
8347 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8348 | ((imm
& 0x01000000) >> 21);
8351 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8354 neon_qfloat_bits (unsigned imm
)
8356 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8359 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8360 the instruction. *OP is passed as the initial value of the op field, and
8361 may be set to a different value depending on the constant (i.e.
8362 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8363 MVN). If the immediate looks like a repeated pattern then also
8364 try smaller element sizes. */
8367 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8368 unsigned *immbits
, int *op
, int size
,
8369 enum neon_el_type type
)
8371 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8373 if (type
== NT_float
&& !float_p
)
8376 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8378 if (size
!= 32 || *op
== 1)
8380 *immbits
= neon_qfloat_bits (immlo
);
8386 if (neon_bits_same_in_bytes (immhi
)
8387 && neon_bits_same_in_bytes (immlo
))
8391 *immbits
= (neon_squash_bits (immhi
) << 4)
8392 | neon_squash_bits (immlo
);
8403 if (immlo
== (immlo
& 0x000000ff))
8408 else if (immlo
== (immlo
& 0x0000ff00))
8410 *immbits
= immlo
>> 8;
8413 else if (immlo
== (immlo
& 0x00ff0000))
8415 *immbits
= immlo
>> 16;
8418 else if (immlo
== (immlo
& 0xff000000))
8420 *immbits
= immlo
>> 24;
8423 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8425 *immbits
= (immlo
>> 8) & 0xff;
8428 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8430 *immbits
= (immlo
>> 16) & 0xff;
8434 if ((immlo
& 0xffff) != (immlo
>> 16))
8441 if (immlo
== (immlo
& 0x000000ff))
8446 else if (immlo
== (immlo
& 0x0000ff00))
8448 *immbits
= immlo
>> 8;
8452 if ((immlo
& 0xff) != (immlo
>> 8))
8457 if (immlo
== (immlo
& 0x000000ff))
8459 /* Don't allow MVN with 8-bit immediate. */
8469 #if defined BFD_HOST_64_BIT
8470 /* Returns TRUE if double precision value V may be cast
8471 to single precision without loss of accuracy. */
8474 is_double_a_single (bfd_int64_t v
)
8476 int exp
= (int)((v
>> 52) & 0x7FF);
8477 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8479 return (exp
== 0 || exp
== 0x7FF
8480 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8481 && (mantissa
& 0x1FFFFFFFl
) == 0;
8484 /* Returns a double precision value casted to single precision
8485 (ignoring the least significant bits in exponent and mantissa). */
8488 double_to_single (bfd_int64_t v
)
8490 int sign
= (int) ((v
>> 63) & 1l);
8491 int exp
= (int) ((v
>> 52) & 0x7FF);
8492 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8498 exp
= exp
- 1023 + 127;
8507 /* No denormalized numbers. */
8513 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8515 #endif /* BFD_HOST_64_BIT */
8524 static void do_vfp_nsyn_opcode (const char *);
8526 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8527 Determine whether it can be performed with a move instruction; if
8528 it can, convert inst.instruction to that move instruction and
8529 return TRUE; if it can't, convert inst.instruction to a literal-pool
8530 load and return FALSE. If this is not a valid thing to do in the
8531 current context, set inst.error and return TRUE.
8533 inst.operands[i] describes the destination register. */
8536 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8539 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8540 bfd_boolean arm_p
= (t
== CONST_ARM
);
8543 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8547 if ((inst
.instruction
& tbit
) == 0)
8549 inst
.error
= _("invalid pseudo operation");
8553 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8554 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8555 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8557 inst
.error
= _("constant expression expected");
8561 if (inst
.relocs
[0].exp
.X_op
== O_constant
8562 || inst
.relocs
[0].exp
.X_op
== O_big
)
8564 #if defined BFD_HOST_64_BIT
8569 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8571 LITTLENUM_TYPE w
[X_PRECISION
];
8574 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8576 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8578 /* FIXME: Should we check words w[2..5] ? */
8583 #if defined BFD_HOST_64_BIT
8585 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8586 << LITTLENUM_NUMBER_OF_BITS
)
8587 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8588 << LITTLENUM_NUMBER_OF_BITS
)
8589 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8590 << LITTLENUM_NUMBER_OF_BITS
)
8591 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8593 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8594 | (l
[0] & LITTLENUM_MASK
);
8598 v
= inst
.relocs
[0].exp
.X_add_number
;
8600 if (!inst
.operands
[i
].issingle
)
8604 /* LDR should not use lead in a flag-setting instruction being
8605 chosen so we do not check whether movs can be used. */
8607 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8608 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8609 && inst
.operands
[i
].reg
!= 13
8610 && inst
.operands
[i
].reg
!= 15)
8612 /* Check if on thumb2 it can be done with a mov.w, mvn or
8613 movw instruction. */
8614 unsigned int newimm
;
8615 bfd_boolean isNegated
;
8617 newimm
= encode_thumb32_immediate (v
);
8618 if (newimm
!= (unsigned int) FAIL
)
8622 newimm
= encode_thumb32_immediate (~v
);
8623 if (newimm
!= (unsigned int) FAIL
)
8627 /* The number can be loaded with a mov.w or mvn
8629 if (newimm
!= (unsigned int) FAIL
8630 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8632 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8633 | (inst
.operands
[i
].reg
<< 8));
8634 /* Change to MOVN. */
8635 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8636 inst
.instruction
|= (newimm
& 0x800) << 15;
8637 inst
.instruction
|= (newimm
& 0x700) << 4;
8638 inst
.instruction
|= (newimm
& 0x0ff);
8641 /* The number can be loaded with a movw instruction. */
8642 else if ((v
& ~0xFFFF) == 0
8643 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8645 int imm
= v
& 0xFFFF;
8647 inst
.instruction
= 0xf2400000; /* MOVW. */
8648 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8649 inst
.instruction
|= (imm
& 0xf000) << 4;
8650 inst
.instruction
|= (imm
& 0x0800) << 15;
8651 inst
.instruction
|= (imm
& 0x0700) << 4;
8652 inst
.instruction
|= (imm
& 0x00ff);
8659 int value
= encode_arm_immediate (v
);
8663 /* This can be done with a mov instruction. */
8664 inst
.instruction
&= LITERAL_MASK
;
8665 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8666 inst
.instruction
|= value
& 0xfff;
8670 value
= encode_arm_immediate (~ v
);
8673 /* This can be done with a mvn instruction. */
8674 inst
.instruction
&= LITERAL_MASK
;
8675 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8676 inst
.instruction
|= value
& 0xfff;
8680 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8683 unsigned immbits
= 0;
8684 unsigned immlo
= inst
.operands
[1].imm
;
8685 unsigned immhi
= inst
.operands
[1].regisimm
8686 ? inst
.operands
[1].reg
8687 : inst
.relocs
[0].exp
.X_unsigned
8689 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8690 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8691 &op
, 64, NT_invtype
);
8695 neon_invert_size (&immlo
, &immhi
, 64);
8697 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8698 &op
, 64, NT_invtype
);
8703 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8709 /* Fill other bits in vmov encoding for both thumb and arm. */
8711 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8713 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8714 neon_write_immbits (immbits
);
8722 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8723 if (inst
.operands
[i
].issingle
8724 && is_quarter_float (inst
.operands
[1].imm
)
8725 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8727 inst
.operands
[1].imm
=
8728 neon_qfloat_bits (v
);
8729 do_vfp_nsyn_opcode ("fconsts");
8733 /* If our host does not support a 64-bit type then we cannot perform
8734 the following optimization. This mean that there will be a
8735 discrepancy between the output produced by an assembler built for
8736 a 32-bit-only host and the output produced from a 64-bit host, but
8737 this cannot be helped. */
8738 #if defined BFD_HOST_64_BIT
8739 else if (!inst
.operands
[1].issingle
8740 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8742 if (is_double_a_single (v
)
8743 && is_quarter_float (double_to_single (v
)))
8745 inst
.operands
[1].imm
=
8746 neon_qfloat_bits (double_to_single (v
));
8747 do_vfp_nsyn_opcode ("fconstd");
8755 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8756 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8759 inst
.operands
[1].reg
= REG_PC
;
8760 inst
.operands
[1].isreg
= 1;
8761 inst
.operands
[1].preind
= 1;
8762 inst
.relocs
[0].pc_rel
= 1;
8763 inst
.relocs
[0].type
= (thumb_p
8764 ? BFD_RELOC_ARM_THUMB_OFFSET
8766 ? BFD_RELOC_ARM_HWLITERAL
8767 : BFD_RELOC_ARM_LITERAL
));
8771 /* inst.operands[i] was set up by parse_address. Encode it into an
8772 ARM-format instruction. Reject all forms which cannot be encoded
8773 into a coprocessor load/store instruction. If wb_ok is false,
8774 reject use of writeback; if unind_ok is false, reject use of
8775 unindexed addressing. If reloc_override is not 0, use it instead
8776 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8777 (in which case it is preserved). */
8780 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8782 if (!inst
.operands
[i
].isreg
)
8785 if (! inst
.operands
[0].isvec
)
8787 inst
.error
= _("invalid co-processor operand");
8790 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8794 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8796 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8798 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8800 gas_assert (!inst
.operands
[i
].writeback
);
8803 inst
.error
= _("instruction does not support unindexed addressing");
8806 inst
.instruction
|= inst
.operands
[i
].imm
;
8807 inst
.instruction
|= INDEX_UP
;
8811 if (inst
.operands
[i
].preind
)
8812 inst
.instruction
|= PRE_INDEX
;
8814 if (inst
.operands
[i
].writeback
)
8816 if (inst
.operands
[i
].reg
== REG_PC
)
8818 inst
.error
= _("pc may not be used with write-back");
8823 inst
.error
= _("instruction does not support writeback");
8826 inst
.instruction
|= WRITE_BACK
;
8830 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8831 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8832 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8833 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8836 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8838 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8841 /* Prefer + for zero encoded value. */
8842 if (!inst
.operands
[i
].negative
)
8843 inst
.instruction
|= INDEX_UP
;
8848 /* Functions for instruction encoding, sorted by sub-architecture.
8849 First some generics; their names are taken from the conventional
8850 bit positions for register arguments in ARM format instructions. */
8860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8866 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8873 inst
.instruction
|= inst
.operands
[1].reg
;
8879 inst
.instruction
|= inst
.operands
[0].reg
;
8880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8887 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8893 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8894 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8900 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8901 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8905 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8907 if (ARM_CPU_IS_ANY (cpu_variant
))
8909 as_tsktsk ("%s", msg
);
8912 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8924 unsigned Rn
= inst
.operands
[2].reg
;
8925 /* Enforce restrictions on SWP instruction. */
8926 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8928 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8929 _("Rn must not overlap other operands"));
8931 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8933 if (!check_obsolete (&arm_ext_v8
,
8934 _("swp{b} use is obsoleted for ARMv8 and later"))
8935 && warn_on_deprecated
8936 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8937 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8941 inst
.instruction
|= inst
.operands
[1].reg
;
8942 inst
.instruction
|= Rn
<< 16;
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8950 inst
.instruction
|= inst
.operands
[2].reg
;
8956 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8957 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8958 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8959 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8961 inst
.instruction
|= inst
.operands
[0].reg
;
8962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8963 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8969 inst
.instruction
|= inst
.operands
[0].imm
;
8975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8976 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8979 /* ARM instructions, in alphabetical order by function name (except
8980 that wrapper functions appear immediately after the function they
8983 /* This is a pseudo-op of the form "adr rd, label" to be converted
8984 into a relative address of the form "add rd, pc, #label-.-8". */
8989 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8991 /* Frag hacking will turn this into a sub instruction if the offset turns
8992 out to be negative. */
8993 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8994 inst
.relocs
[0].pc_rel
= 1;
8995 inst
.relocs
[0].exp
.X_add_number
-= 8;
8997 if (support_interwork
8998 && inst
.relocs
[0].exp
.X_op
== O_symbol
8999 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9000 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9001 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9002 inst
.relocs
[0].exp
.X_add_number
|= 1;
9005 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9006 into a relative address of the form:
9007 add rd, pc, #low(label-.-8)"
9008 add rd, rd, #high(label-.-8)" */
9013 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9015 /* Frag hacking will turn this into a sub instruction if the offset turns
9016 out to be negative. */
9017 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9018 inst
.relocs
[0].pc_rel
= 1;
9019 inst
.size
= INSN_SIZE
* 2;
9020 inst
.relocs
[0].exp
.X_add_number
-= 8;
9022 if (support_interwork
9023 && inst
.relocs
[0].exp
.X_op
== O_symbol
9024 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9025 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9026 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9027 inst
.relocs
[0].exp
.X_add_number
|= 1;
9033 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9034 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9036 if (!inst
.operands
[1].present
)
9037 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9040 encode_arm_shifter_operand (2);
9046 if (inst
.operands
[0].present
)
9047 inst
.instruction
|= inst
.operands
[0].imm
;
9049 inst
.instruction
|= 0xf;
9055 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9056 constraint (msb
> 32, _("bit-field extends past end of register"));
9057 /* The instruction encoding stores the LSB and MSB,
9058 not the LSB and width. */
9059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9060 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9061 inst
.instruction
|= (msb
- 1) << 16;
9069 /* #0 in second position is alternative syntax for bfc, which is
9070 the same instruction but with REG_PC in the Rm field. */
9071 if (!inst
.operands
[1].isreg
)
9072 inst
.operands
[1].reg
= REG_PC
;
9074 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9075 constraint (msb
> 32, _("bit-field extends past end of register"));
9076 /* The instruction encoding stores the LSB and MSB,
9077 not the LSB and width. */
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 inst
.instruction
|= inst
.operands
[1].reg
;
9080 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9081 inst
.instruction
|= (msb
- 1) << 16;
9087 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9088 _("bit-field extends past end of register"));
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9090 inst
.instruction
|= inst
.operands
[1].reg
;
9091 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9092 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9095 /* ARM V5 breakpoint instruction (argument parse)
9096 BKPT <16 bit unsigned immediate>
9097 Instruction is not conditional.
9098 The bit pattern given in insns[] has the COND_ALWAYS condition,
9099 and it is an error if the caller tried to override that. */
9104 /* Top 12 of 16 bits to bits 19:8. */
9105 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9107 /* Bottom 4 of 16 bits to bits 3:0. */
9108 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9112 encode_branch (int default_reloc
)
9114 if (inst
.operands
[0].hasreloc
)
9116 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9117 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9118 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9119 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9120 ? BFD_RELOC_ARM_PLT32
9121 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9124 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9125 inst
.relocs
[0].pc_rel
= 1;
9132 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9133 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9136 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9143 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9145 if (inst
.cond
== COND_ALWAYS
)
9146 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9148 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9152 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9155 /* ARM V5 branch-link-exchange instruction (argument parse)
9156 BLX <target_addr> ie BLX(1)
9157 BLX{<condition>} <Rm> ie BLX(2)
9158 Unfortunately, there are two different opcodes for this mnemonic.
9159 So, the insns[].value is not used, and the code here zaps values
9160 into inst.instruction.
9161 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9166 if (inst
.operands
[0].isreg
)
9168 /* Arg is a register; the opcode provided by insns[] is correct.
9169 It is not illegal to do "blx pc", just useless. */
9170 if (inst
.operands
[0].reg
== REG_PC
)
9171 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9173 inst
.instruction
|= inst
.operands
[0].reg
;
9177 /* Arg is an address; this instruction cannot be executed
9178 conditionally, and the opcode must be adjusted.
9179 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9180 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9181 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9182 inst
.instruction
= 0xfa000000;
9183 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9190 bfd_boolean want_reloc
;
9192 if (inst
.operands
[0].reg
== REG_PC
)
9193 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9195 inst
.instruction
|= inst
.operands
[0].reg
;
9196 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9197 it is for ARMv4t or earlier. */
9198 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9199 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9200 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9204 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9209 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9213 /* ARM v5TEJ. Jump to Jazelle code. */
9218 if (inst
.operands
[0].reg
== REG_PC
)
9219 as_tsktsk (_("use of r15 in bxj is not really useful"));
9221 inst
.instruction
|= inst
.operands
[0].reg
;
9224 /* Co-processor data operation:
9225 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9226 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9230 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9231 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9232 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9233 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9234 inst
.instruction
|= inst
.operands
[4].reg
;
9235 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9242 encode_arm_shifter_operand (1);
9245 /* Transfer between coprocessor and ARM registers.
9246 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9251 No special properties. */
9253 struct deprecated_coproc_regs_s
9260 arm_feature_set deprecated
;
9261 arm_feature_set obsoleted
;
9262 const char *dep_msg
;
9263 const char *obs_msg
;
9266 #define DEPR_ACCESS_V8 \
9267 N_("This coprocessor register access is deprecated in ARMv8")
9269 /* Table of all deprecated coprocessor registers. */
9270 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9272 {15, 0, 7, 10, 5, /* CP15DMB. */
9273 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9274 DEPR_ACCESS_V8
, NULL
},
9275 {15, 0, 7, 10, 4, /* CP15DSB. */
9276 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9277 DEPR_ACCESS_V8
, NULL
},
9278 {15, 0, 7, 5, 4, /* CP15ISB. */
9279 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9280 DEPR_ACCESS_V8
, NULL
},
9281 {14, 6, 1, 0, 0, /* TEEHBR. */
9282 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9283 DEPR_ACCESS_V8
, NULL
},
9284 {14, 6, 0, 0, 0, /* TEECR. */
9285 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9286 DEPR_ACCESS_V8
, NULL
},
9289 #undef DEPR_ACCESS_V8
9291 static const size_t deprecated_coproc_reg_count
=
9292 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9300 Rd
= inst
.operands
[2].reg
;
9303 if (inst
.instruction
== 0xee000010
9304 || inst
.instruction
== 0xfe000010)
9306 reject_bad_reg (Rd
);
9307 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9309 constraint (Rd
== REG_SP
, BAD_SP
);
9314 if (inst
.instruction
== 0xe000010)
9315 constraint (Rd
== REG_PC
, BAD_PC
);
9318 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9320 const struct deprecated_coproc_regs_s
*r
=
9321 deprecated_coproc_regs
+ i
;
9323 if (inst
.operands
[0].reg
== r
->cp
9324 && inst
.operands
[1].imm
== r
->opc1
9325 && inst
.operands
[3].reg
== r
->crn
9326 && inst
.operands
[4].reg
== r
->crm
9327 && inst
.operands
[5].imm
== r
->opc2
)
9329 if (! ARM_CPU_IS_ANY (cpu_variant
)
9330 && warn_on_deprecated
9331 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9332 as_tsktsk ("%s", r
->dep_msg
);
9336 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9337 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9338 inst
.instruction
|= Rd
<< 12;
9339 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9340 inst
.instruction
|= inst
.operands
[4].reg
;
9341 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9344 /* Transfer between coprocessor register and pair of ARM registers.
9345 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9350 Two XScale instructions are special cases of these:
9352 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9353 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9355 Result unpredictable if Rd or Rn is R15. */
9362 Rd
= inst
.operands
[2].reg
;
9363 Rn
= inst
.operands
[3].reg
;
9367 reject_bad_reg (Rd
);
9368 reject_bad_reg (Rn
);
9372 constraint (Rd
== REG_PC
, BAD_PC
);
9373 constraint (Rn
== REG_PC
, BAD_PC
);
9376 /* Only check the MRRC{2} variants. */
9377 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9379 /* If Rd == Rn, error that the operation is
9380 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9381 constraint (Rd
== Rn
, BAD_OVERLAP
);
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9385 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9386 inst
.instruction
|= Rd
<< 12;
9387 inst
.instruction
|= Rn
<< 16;
9388 inst
.instruction
|= inst
.operands
[4].reg
;
9394 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9395 if (inst
.operands
[1].present
)
9397 inst
.instruction
|= CPSI_MMOD
;
9398 inst
.instruction
|= inst
.operands
[1].imm
;
9405 inst
.instruction
|= inst
.operands
[0].imm
;
9411 unsigned Rd
, Rn
, Rm
;
9413 Rd
= inst
.operands
[0].reg
;
9414 Rn
= (inst
.operands
[1].present
9415 ? inst
.operands
[1].reg
: Rd
);
9416 Rm
= inst
.operands
[2].reg
;
9418 constraint ((Rd
== REG_PC
), BAD_PC
);
9419 constraint ((Rn
== REG_PC
), BAD_PC
);
9420 constraint ((Rm
== REG_PC
), BAD_PC
);
9422 inst
.instruction
|= Rd
<< 16;
9423 inst
.instruction
|= Rn
<< 0;
9424 inst
.instruction
|= Rm
<< 8;
9430 /* There is no IT instruction in ARM mode. We
9431 process it to do the validation as if in
9432 thumb mode, just in case the code gets
9433 assembled for thumb using the unified syntax. */
9438 set_pred_insn_type (IT_INSN
);
9439 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9440 now_pred
.cc
= inst
.operands
[0].imm
;
9444 /* If there is only one register in the register list,
9445 then return its register number. Otherwise return -1. */
9447 only_one_reg_in_list (int range
)
9449 int i
= ffs (range
) - 1;
9450 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9454 encode_ldmstm(int from_push_pop_mnem
)
9456 int base_reg
= inst
.operands
[0].reg
;
9457 int range
= inst
.operands
[1].imm
;
9460 inst
.instruction
|= base_reg
<< 16;
9461 inst
.instruction
|= range
;
9463 if (inst
.operands
[1].writeback
)
9464 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9466 if (inst
.operands
[0].writeback
)
9468 inst
.instruction
|= WRITE_BACK
;
9469 /* Check for unpredictable uses of writeback. */
9470 if (inst
.instruction
& LOAD_BIT
)
9472 /* Not allowed in LDM type 2. */
9473 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9474 && ((range
& (1 << REG_PC
)) == 0))
9475 as_warn (_("writeback of base register is UNPREDICTABLE"));
9476 /* Only allowed if base reg not in list for other types. */
9477 else if (range
& (1 << base_reg
))
9478 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9482 /* Not allowed for type 2. */
9483 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9484 as_warn (_("writeback of base register is UNPREDICTABLE"));
9485 /* Only allowed if base reg not in list, or first in list. */
9486 else if ((range
& (1 << base_reg
))
9487 && (range
& ((1 << base_reg
) - 1)))
9488 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9492 /* If PUSH/POP has only one register, then use the A2 encoding. */
9493 one_reg
= only_one_reg_in_list (range
);
9494 if (from_push_pop_mnem
&& one_reg
>= 0)
9496 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9498 if (is_push
&& one_reg
== 13 /* SP */)
9499 /* PR 22483: The A2 encoding cannot be used when
9500 pushing the stack pointer as this is UNPREDICTABLE. */
9503 inst
.instruction
&= A_COND_MASK
;
9504 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9505 inst
.instruction
|= one_reg
<< 12;
9512 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9515 /* ARMv5TE load-consecutive (argument parse)
9524 constraint (inst
.operands
[0].reg
% 2 != 0,
9525 _("first transfer register must be even"));
9526 constraint (inst
.operands
[1].present
9527 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9528 _("can only transfer two consecutive registers"));
9529 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9530 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9532 if (!inst
.operands
[1].present
)
9533 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9535 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9536 register and the first register written; we have to diagnose
9537 overlap between the base and the second register written here. */
9539 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9540 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9541 as_warn (_("base register written back, and overlaps "
9542 "second transfer register"));
9544 if (!(inst
.instruction
& V4_STR_BIT
))
9546 /* For an index-register load, the index register must not overlap the
9547 destination (even if not write-back). */
9548 if (inst
.operands
[2].immisreg
9549 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9550 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9551 as_warn (_("index register overlaps transfer register"));
9553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9554 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9560 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9561 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9562 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9563 || inst
.operands
[1].negative
9564 /* This can arise if the programmer has written
9566 or if they have mistakenly used a register name as the last
9569 It is very difficult to distinguish between these two cases
9570 because "rX" might actually be a label. ie the register
9571 name has been occluded by a symbol of the same name. So we
9572 just generate a general 'bad addressing mode' type error
9573 message and leave it up to the programmer to discover the
9574 true cause and fix their mistake. */
9575 || (inst
.operands
[1].reg
== REG_PC
),
9578 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9579 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9580 _("offset must be zero in ARM encoding"));
9582 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9585 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9586 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9592 constraint (inst
.operands
[0].reg
% 2 != 0,
9593 _("even register required"));
9594 constraint (inst
.operands
[1].present
9595 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9596 _("can only load two consecutive registers"));
9597 /* If op 1 were present and equal to PC, this function wouldn't
9598 have been called in the first place. */
9599 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9602 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9605 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9606 which is not a multiple of four is UNPREDICTABLE. */
9608 check_ldr_r15_aligned (void)
9610 constraint (!(inst
.operands
[1].immisreg
)
9611 && (inst
.operands
[0].reg
== REG_PC
9612 && inst
.operands
[1].reg
== REG_PC
9613 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9614 _("ldr to register 15 must be 4-byte aligned"));
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9621 if (!inst
.operands
[1].isreg
)
9622 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9624 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9625 check_ldr_r15_aligned ();
9631 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9633 if (inst
.operands
[1].preind
)
9635 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9636 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9637 _("this instruction requires a post-indexed address"));
9639 inst
.operands
[1].preind
= 0;
9640 inst
.operands
[1].postind
= 1;
9641 inst
.operands
[1].writeback
= 1;
9643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9644 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9647 /* Halfword and signed-byte load/store operations. */
9652 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9654 if (!inst
.operands
[1].isreg
)
9655 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9657 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9663 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9665 if (inst
.operands
[1].preind
)
9667 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9668 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9669 _("this instruction requires a post-indexed address"));
9671 inst
.operands
[1].preind
= 0;
9672 inst
.operands
[1].postind
= 1;
9673 inst
.operands
[1].writeback
= 1;
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9679 /* Co-processor register load/store.
9680 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9684 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9685 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9686 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9692 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9693 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9694 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9695 && !(inst
.instruction
& 0x00400000))
9696 as_tsktsk (_("Rd and Rm should be different in mla"));
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9699 inst
.instruction
|= inst
.operands
[1].reg
;
9700 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9701 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9707 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9708 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9711 encode_arm_shifter_operand (1);
9714 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9721 top
= (inst
.instruction
& 0x00400000) != 0;
9722 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9723 _(":lower16: not allowed in this instruction"));
9724 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9725 _(":upper16: not allowed in this instruction"));
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9727 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9729 imm
= inst
.relocs
[0].exp
.X_add_number
;
9730 /* The value is in two pieces: 0:11, 16:19. */
9731 inst
.instruction
|= (imm
& 0x00000fff);
9732 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9737 do_vfp_nsyn_mrs (void)
9739 if (inst
.operands
[0].isvec
)
9741 if (inst
.operands
[1].reg
!= 1)
9742 first_error (_("operand 1 must be FPSCR"));
9743 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9744 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9745 do_vfp_nsyn_opcode ("fmstat");
9747 else if (inst
.operands
[1].isvec
)
9748 do_vfp_nsyn_opcode ("fmrx");
9756 do_vfp_nsyn_msr (void)
9758 if (inst
.operands
[0].isvec
)
9759 do_vfp_nsyn_opcode ("fmxr");
9769 unsigned Rt
= inst
.operands
[0].reg
;
9771 if (thumb_mode
&& Rt
== REG_SP
)
9773 inst
.error
= BAD_SP
;
9777 /* MVFR2 is only valid at ARMv8-A. */
9778 if (inst
.operands
[1].reg
== 5)
9779 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9782 /* APSR_ sets isvec. All other refs to PC are illegal. */
9783 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9785 inst
.error
= BAD_PC
;
9789 /* If we get through parsing the register name, we just insert the number
9790 generated into the instruction without further validation. */
9791 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9792 inst
.instruction
|= (Rt
<< 12);
9798 unsigned Rt
= inst
.operands
[1].reg
;
9801 reject_bad_reg (Rt
);
9802 else if (Rt
== REG_PC
)
9804 inst
.error
= BAD_PC
;
9808 /* MVFR2 is only valid for ARMv8-A. */
9809 if (inst
.operands
[0].reg
== 5)
9810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9813 /* If we get through parsing the register name, we just insert the number
9814 generated into the instruction without further validation. */
9815 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9816 inst
.instruction
|= (Rt
<< 12);
9824 if (do_vfp_nsyn_mrs () == SUCCESS
)
9827 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9830 if (inst
.operands
[1].isreg
)
9832 br
= inst
.operands
[1].reg
;
9833 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9834 as_bad (_("bad register for mrs"));
9838 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9839 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9841 _("'APSR', 'CPSR' or 'SPSR' expected"));
9842 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9845 inst
.instruction
|= br
;
9848 /* Two possible forms:
9849 "{C|S}PSR_<field>, Rm",
9850 "{C|S}PSR_f, #expression". */
9855 if (do_vfp_nsyn_msr () == SUCCESS
)
9858 inst
.instruction
|= inst
.operands
[0].imm
;
9859 if (inst
.operands
[1].isreg
)
9860 inst
.instruction
|= inst
.operands
[1].reg
;
9863 inst
.instruction
|= INST_IMMEDIATE
;
9864 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9865 inst
.relocs
[0].pc_rel
= 0;
9872 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9874 if (!inst
.operands
[2].present
)
9875 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9876 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9877 inst
.instruction
|= inst
.operands
[1].reg
;
9878 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9880 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9881 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9882 as_tsktsk (_("Rd and Rm should be different in mul"));
9885 /* Long Multiply Parser
9886 UMULL RdLo, RdHi, Rm, Rs
9887 SMULL RdLo, RdHi, Rm, Rs
9888 UMLAL RdLo, RdHi, Rm, Rs
9889 SMLAL RdLo, RdHi, Rm, Rs. */
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9896 inst
.instruction
|= inst
.operands
[2].reg
;
9897 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9899 /* rdhi and rdlo must be different. */
9900 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9901 as_tsktsk (_("rdhi and rdlo must be different"));
9903 /* rdhi, rdlo and rm must all be different before armv6. */
9904 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9905 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9906 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9907 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9913 if (inst
.operands
[0].present
9914 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9916 /* Architectural NOP hints are CPSR sets with no bits selected. */
9917 inst
.instruction
&= 0xf0000000;
9918 inst
.instruction
|= 0x0320f000;
9919 if (inst
.operands
[0].present
)
9920 inst
.instruction
|= inst
.operands
[0].imm
;
9924 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9925 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9926 Condition defaults to COND_ALWAYS.
9927 Error if Rd, Rn or Rm are R15. */
9932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9933 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9934 inst
.instruction
|= inst
.operands
[2].reg
;
9935 if (inst
.operands
[3].present
)
9936 encode_arm_shift (3);
9939 /* ARM V6 PKHTB (Argument Parse). */
9944 if (!inst
.operands
[3].present
)
9946 /* If the shift specifier is omitted, turn the instruction
9947 into pkhbt rd, rm, rn. */
9948 inst
.instruction
&= 0xfff00010;
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 inst
.instruction
|= inst
.operands
[1].reg
;
9951 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9958 encode_arm_shift (3);
9962 /* ARMv5TE: Preload-Cache
9963 MP Extensions: Preload for write
9967 Syntactically, like LDR with B=1, W=0, L=1. */
9972 constraint (!inst
.operands
[0].isreg
,
9973 _("'[' expected after PLD mnemonic"));
9974 constraint (inst
.operands
[0].postind
,
9975 _("post-indexed expression used in preload instruction"));
9976 constraint (inst
.operands
[0].writeback
,
9977 _("writeback used in preload instruction"));
9978 constraint (!inst
.operands
[0].preind
,
9979 _("unindexed addressing used in preload instruction"));
9980 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9983 /* ARMv7: PLI <addr_mode> */
9987 constraint (!inst
.operands
[0].isreg
,
9988 _("'[' expected after PLI mnemonic"));
9989 constraint (inst
.operands
[0].postind
,
9990 _("post-indexed expression used in preload instruction"));
9991 constraint (inst
.operands
[0].writeback
,
9992 _("writeback used in preload instruction"));
9993 constraint (!inst
.operands
[0].preind
,
9994 _("unindexed addressing used in preload instruction"));
9995 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9996 inst
.instruction
&= ~PRE_INDEX
;
10002 constraint (inst
.operands
[0].writeback
,
10003 _("push/pop do not support {reglist}^"));
10004 inst
.operands
[1] = inst
.operands
[0];
10005 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10006 inst
.operands
[0].isreg
= 1;
10007 inst
.operands
[0].writeback
= 1;
10008 inst
.operands
[0].reg
= REG_SP
;
10009 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10012 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10013 word at the specified address and the following word
10015 Unconditionally executed.
10016 Error if Rn is R15. */
10021 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10022 if (inst
.operands
[0].writeback
)
10023 inst
.instruction
|= WRITE_BACK
;
10026 /* ARM V6 ssat (argument parse). */
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10032 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10033 inst
.instruction
|= inst
.operands
[2].reg
;
10035 if (inst
.operands
[3].present
)
10036 encode_arm_shift (3);
10039 /* ARM V6 usat (argument parse). */
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10045 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10046 inst
.instruction
|= inst
.operands
[2].reg
;
10048 if (inst
.operands
[3].present
)
10049 encode_arm_shift (3);
10052 /* ARM V6 ssat16 (argument parse). */
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10058 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10059 inst
.instruction
|= inst
.operands
[2].reg
;
10065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10066 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10067 inst
.instruction
|= inst
.operands
[2].reg
;
10070 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10071 preserving the other bits.
10073 setend <endian_specifier>, where <endian_specifier> is either
10079 if (warn_on_deprecated
10080 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10081 as_tsktsk (_("setend use is deprecated for ARMv8"));
10083 if (inst
.operands
[0].imm
)
10084 inst
.instruction
|= 0x200;
10090 unsigned int Rm
= (inst
.operands
[1].present
10091 ? inst
.operands
[1].reg
10092 : inst
.operands
[0].reg
);
10094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10095 inst
.instruction
|= Rm
;
10096 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10098 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10099 inst
.instruction
|= SHIFT_BY_REG
;
10100 /* PR 12854: Error on extraneous shifts. */
10101 constraint (inst
.operands
[2].shifted
,
10102 _("extraneous shift as part of operand to shift insn"));
10105 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10111 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10112 inst
.relocs
[0].pc_rel
= 0;
10118 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10119 inst
.relocs
[0].pc_rel
= 0;
10125 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10126 inst
.relocs
[0].pc_rel
= 0;
10132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10133 _("selected processor does not support SETPAN instruction"));
10135 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10141 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10142 _("selected processor does not support SETPAN instruction"));
10144 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10147 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10148 SMLAxy{cond} Rd,Rm,Rs,Rn
10149 SMLAWy{cond} Rd,Rm,Rs,Rn
10150 Error if any register is R15. */
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10156 inst
.instruction
|= inst
.operands
[1].reg
;
10157 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10158 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10161 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10162 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10163 Error if any register is R15.
10164 Warning if Rdlo == Rdhi. */
10169 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10170 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10171 inst
.instruction
|= inst
.operands
[2].reg
;
10172 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10174 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10175 as_tsktsk (_("rdhi and rdlo must be different"));
10178 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10179 SMULxy{cond} Rd,Rm,Rs
10180 Error if any register is R15. */
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10186 inst
.instruction
|= inst
.operands
[1].reg
;
10187 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10190 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10191 the same for both ARM and Thumb-2. */
10198 if (inst
.operands
[0].present
)
10200 reg
= inst
.operands
[0].reg
;
10201 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10206 inst
.instruction
|= reg
<< 16;
10207 inst
.instruction
|= inst
.operands
[1].imm
;
10208 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10209 inst
.instruction
|= WRITE_BACK
;
10212 /* ARM V6 strex (argument parse). */
10217 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10218 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10219 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10220 || inst
.operands
[2].negative
10221 /* See comment in do_ldrex(). */
10222 || (inst
.operands
[2].reg
== REG_PC
),
10225 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10226 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10228 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10229 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10230 _("offset must be zero in ARM encoding"));
10232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10233 inst
.instruction
|= inst
.operands
[1].reg
;
10234 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10235 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10239 do_t_strexbh (void)
10241 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10242 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10243 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10244 || inst
.operands
[2].negative
,
10247 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10248 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10256 constraint (inst
.operands
[1].reg
% 2 != 0,
10257 _("even register required"));
10258 constraint (inst
.operands
[2].present
10259 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10260 _("can only store two consecutive registers"));
10261 /* If op 2 were present and equal to PC, this function wouldn't
10262 have been called in the first place. */
10263 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10265 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10266 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10267 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10271 inst
.instruction
|= inst
.operands
[1].reg
;
10272 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10279 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10280 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10288 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10289 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10294 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10295 extends it to 32-bits, and adds the result to a value in another
10296 register. You can specify a rotation by 0, 8, 16, or 24 bits
10297 before extracting the 16-bit value.
10298 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10299 Condition defaults to COND_ALWAYS.
10300 Error if any register uses R15. */
10305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10307 inst
.instruction
|= inst
.operands
[2].reg
;
10308 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10313 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10314 Condition defaults to COND_ALWAYS.
10315 Error if any register uses R15. */
10320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10321 inst
.instruction
|= inst
.operands
[1].reg
;
10322 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10325 /* VFP instructions. In a logical order: SP variant first, monad
10326 before dyad, arithmetic then move then load/store. */
10329 do_vfp_sp_monadic (void)
10331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10332 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10335 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10336 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10340 do_vfp_sp_dyadic (void)
10342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10344 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10348 do_vfp_sp_compare_z (void)
10350 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10354 do_vfp_dp_sp_cvt (void)
10356 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10357 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10361 do_vfp_sp_dp_cvt (void)
10363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10364 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10368 do_vfp_reg_from_sp (void)
10370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10371 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10375 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10379 do_vfp_reg2_from_sp2 (void)
10381 constraint (inst
.operands
[2].imm
!= 2,
10382 _("only two consecutive VFP SP registers allowed here"));
10383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10384 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10385 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10389 do_vfp_sp_from_reg (void)
10391 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10392 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10395 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10396 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10400 do_vfp_sp2_from_reg2 (void)
10402 constraint (inst
.operands
[0].imm
!= 2,
10403 _("only two consecutive VFP SP registers allowed here"));
10404 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10405 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10406 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10410 do_vfp_sp_ldst (void)
10412 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10413 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10417 do_vfp_dp_ldst (void)
10419 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10420 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10425 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10427 if (inst
.operands
[0].writeback
)
10428 inst
.instruction
|= WRITE_BACK
;
10430 constraint (ldstm_type
!= VFP_LDSTMIA
,
10431 _("this addressing mode requires base-register writeback"));
10432 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10433 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10434 inst
.instruction
|= inst
.operands
[1].imm
;
10438 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10442 if (inst
.operands
[0].writeback
)
10443 inst
.instruction
|= WRITE_BACK
;
10445 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10446 _("this addressing mode requires base-register writeback"));
10448 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10449 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10451 count
= inst
.operands
[1].imm
<< 1;
10452 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10455 inst
.instruction
|= count
;
10459 do_vfp_sp_ldstmia (void)
10461 vfp_sp_ldstm (VFP_LDSTMIA
);
10465 do_vfp_sp_ldstmdb (void)
10467 vfp_sp_ldstm (VFP_LDSTMDB
);
10471 do_vfp_dp_ldstmia (void)
10473 vfp_dp_ldstm (VFP_LDSTMIA
);
10477 do_vfp_dp_ldstmdb (void)
10479 vfp_dp_ldstm (VFP_LDSTMDB
);
10483 do_vfp_xp_ldstmia (void)
10485 vfp_dp_ldstm (VFP_LDSTMIAX
);
10489 do_vfp_xp_ldstmdb (void)
10491 vfp_dp_ldstm (VFP_LDSTMDBX
);
10495 do_vfp_dp_rd_rm (void)
10497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10498 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10501 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10502 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10506 do_vfp_dp_rn_rd (void)
10508 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10509 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10513 do_vfp_dp_rd_rn (void)
10515 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10516 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10520 do_vfp_dp_rd_rn_rm (void)
10522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10523 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10526 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10527 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10528 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10532 do_vfp_dp_rd (void)
10534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10538 do_vfp_dp_rm_rd_rn (void)
10540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10541 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10544 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10546 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10549 /* VFPv3 instructions. */
10551 do_vfp_sp_const (void)
10553 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10554 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10555 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10559 do_vfp_dp_const (void)
10561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10562 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10563 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10567 vfp_conv (int srcsize
)
10569 int immbits
= srcsize
- inst
.operands
[1].imm
;
10571 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10573 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10574 i.e. immbits must be in range 0 - 16. */
10575 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10578 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10580 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10581 i.e. immbits must be in range 0 - 31. */
10582 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10586 inst
.instruction
|= (immbits
& 1) << 5;
10587 inst
.instruction
|= (immbits
>> 1);
10591 do_vfp_sp_conv_16 (void)
10593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10598 do_vfp_dp_conv_16 (void)
10600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10605 do_vfp_sp_conv_32 (void)
10607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10612 do_vfp_dp_conv_32 (void)
10614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10618 /* FPA instructions. Also in a logical order. */
10623 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10624 inst
.instruction
|= inst
.operands
[1].reg
;
10628 do_fpa_ldmstm (void)
10630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10631 switch (inst
.operands
[1].imm
)
10633 case 1: inst
.instruction
|= CP_T_X
; break;
10634 case 2: inst
.instruction
|= CP_T_Y
; break;
10635 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10640 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10642 /* The instruction specified "ea" or "fd", so we can only accept
10643 [Rn]{!}. The instruction does not really support stacking or
10644 unstacking, so we have to emulate these by setting appropriate
10645 bits and offsets. */
10646 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10647 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10648 _("this instruction does not support indexing"));
10650 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10651 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10653 if (!(inst
.instruction
& INDEX_UP
))
10654 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10656 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10658 inst
.operands
[2].preind
= 0;
10659 inst
.operands
[2].postind
= 1;
10663 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10666 /* iWMMXt instructions: strictly in alphabetical order. */
10669 do_iwmmxt_tandorc (void)
10671 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10675 do_iwmmxt_textrc (void)
10677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10678 inst
.instruction
|= inst
.operands
[1].imm
;
10682 do_iwmmxt_textrm (void)
10684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10685 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10686 inst
.instruction
|= inst
.operands
[2].imm
;
10690 do_iwmmxt_tinsr (void)
10692 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10693 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10694 inst
.instruction
|= inst
.operands
[2].imm
;
10698 do_iwmmxt_tmia (void)
10700 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10701 inst
.instruction
|= inst
.operands
[1].reg
;
10702 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10706 do_iwmmxt_waligni (void)
10708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10709 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10710 inst
.instruction
|= inst
.operands
[2].reg
;
10711 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10715 do_iwmmxt_wmerge (void)
10717 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10718 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10719 inst
.instruction
|= inst
.operands
[2].reg
;
10720 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10724 do_iwmmxt_wmov (void)
10726 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10728 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10729 inst
.instruction
|= inst
.operands
[1].reg
;
10733 do_iwmmxt_wldstbh (void)
10736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10738 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10740 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10741 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10745 do_iwmmxt_wldstw (void)
10747 /* RIWR_RIWC clears .isreg for a control register. */
10748 if (!inst
.operands
[0].isreg
)
10750 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10751 inst
.instruction
|= 0xf0000000;
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10755 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10759 do_iwmmxt_wldstd (void)
10761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10762 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10763 && inst
.operands
[1].immisreg
)
10765 inst
.instruction
&= ~0x1a000ff;
10766 inst
.instruction
|= (0xfU
<< 28);
10767 if (inst
.operands
[1].preind
)
10768 inst
.instruction
|= PRE_INDEX
;
10769 if (!inst
.operands
[1].negative
)
10770 inst
.instruction
|= INDEX_UP
;
10771 if (inst
.operands
[1].writeback
)
10772 inst
.instruction
|= WRITE_BACK
;
10773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10774 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10775 inst
.instruction
|= inst
.operands
[1].imm
;
10778 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10782 do_iwmmxt_wshufh (void)
10784 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10785 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10786 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10787 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10791 do_iwmmxt_wzero (void)
10793 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10794 inst
.instruction
|= inst
.operands
[0].reg
;
10795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10796 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10800 do_iwmmxt_wrwrwr_or_imm5 (void)
10802 if (inst
.operands
[2].isreg
)
10805 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10806 _("immediate operand requires iWMMXt2"));
10808 if (inst
.operands
[2].imm
== 0)
10810 switch ((inst
.instruction
>> 20) & 0xf)
10816 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10817 inst
.operands
[2].imm
= 16;
10818 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10824 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10825 inst
.operands
[2].imm
= 32;
10826 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10833 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10835 wrn
= (inst
.instruction
>> 16) & 0xf;
10836 inst
.instruction
&= 0xff0fff0f;
10837 inst
.instruction
|= wrn
;
10838 /* Bail out here; the instruction is now assembled. */
10843 /* Map 32 -> 0, etc. */
10844 inst
.operands
[2].imm
&= 0x1f;
10845 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10849 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10850 operations first, then control, shift, and load/store. */
10852 /* Insns like "foo X,Y,Z". */
10855 do_mav_triple (void)
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10858 inst
.instruction
|= inst
.operands
[1].reg
;
10859 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10862 /* Insns like "foo W,X,Y,Z".
10863 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10868 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10869 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10870 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10871 inst
.instruction
|= inst
.operands
[3].reg
;
10874 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10876 do_mav_dspsc (void)
10878 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10881 /* Maverick shift immediate instructions.
10882 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10883 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10886 do_mav_shift (void)
10888 int imm
= inst
.operands
[2].imm
;
10890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10893 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10894 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10895 Bit 4 should be 0. */
10896 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10898 inst
.instruction
|= imm
;
10901 /* XScale instructions. Also sorted arithmetic before move. */
10903 /* Xscale multiply-accumulate (argument parse)
10906 MIAxycc acc0,Rm,Rs. */
10911 inst
.instruction
|= inst
.operands
[1].reg
;
10912 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10915 /* Xscale move-accumulator-register (argument parse)
10917 MARcc acc0,RdLo,RdHi. */
10922 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10923 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10926 /* Xscale move-register-accumulator (argument parse)
10928 MRAcc RdLo,RdHi,acc0. */
10933 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10935 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10938 /* Encoding functions relevant only to Thumb. */
10940 /* inst.operands[i] is a shifted-register operand; encode
10941 it into inst.instruction in the format used by Thumb32. */
10944 encode_thumb32_shifted_operand (int i
)
10946 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10947 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10949 constraint (inst
.operands
[i
].immisreg
,
10950 _("shift by register not allowed in thumb mode"));
10951 inst
.instruction
|= inst
.operands
[i
].reg
;
10952 if (shift
== SHIFT_RRX
)
10953 inst
.instruction
|= SHIFT_ROR
<< 4;
10956 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10957 _("expression too complex"));
10959 constraint (value
> 32
10960 || (value
== 32 && (shift
== SHIFT_LSL
10961 || shift
== SHIFT_ROR
)),
10962 _("shift expression is too large"));
10966 else if (value
== 32)
10969 inst
.instruction
|= shift
<< 4;
10970 inst
.instruction
|= (value
& 0x1c) << 10;
10971 inst
.instruction
|= (value
& 0x03) << 6;
10976 /* inst.operands[i] was set up by parse_address. Encode it into a
10977 Thumb32 format load or store instruction. Reject forms that cannot
10978 be used with such instructions. If is_t is true, reject forms that
10979 cannot be used with a T instruction; if is_d is true, reject forms
10980 that cannot be used with a D instruction. If it is a store insn,
10981 reject PC in Rn. */
10984 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10986 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10988 constraint (!inst
.operands
[i
].isreg
,
10989 _("Instruction does not support =N addresses"));
10991 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10992 if (inst
.operands
[i
].immisreg
)
10994 constraint (is_pc
, BAD_PC_ADDRESSING
);
10995 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10996 constraint (inst
.operands
[i
].negative
,
10997 _("Thumb does not support negative register indexing"));
10998 constraint (inst
.operands
[i
].postind
,
10999 _("Thumb does not support register post-indexing"));
11000 constraint (inst
.operands
[i
].writeback
,
11001 _("Thumb does not support register indexing with writeback"));
11002 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11003 _("Thumb supports only LSL in shifted register indexing"));
11005 inst
.instruction
|= inst
.operands
[i
].imm
;
11006 if (inst
.operands
[i
].shifted
)
11008 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11009 _("expression too complex"));
11010 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11011 || inst
.relocs
[0].exp
.X_add_number
> 3,
11012 _("shift out of range"));
11013 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11015 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11017 else if (inst
.operands
[i
].preind
)
11019 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11020 constraint (is_t
&& inst
.operands
[i
].writeback
,
11021 _("cannot use writeback with this instruction"));
11022 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11023 BAD_PC_ADDRESSING
);
11027 inst
.instruction
|= 0x01000000;
11028 if (inst
.operands
[i
].writeback
)
11029 inst
.instruction
|= 0x00200000;
11033 inst
.instruction
|= 0x00000c00;
11034 if (inst
.operands
[i
].writeback
)
11035 inst
.instruction
|= 0x00000100;
11037 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11039 else if (inst
.operands
[i
].postind
)
11041 gas_assert (inst
.operands
[i
].writeback
);
11042 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11043 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11046 inst
.instruction
|= 0x00200000;
11048 inst
.instruction
|= 0x00000900;
11049 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11051 else /* unindexed - only for coprocessor */
11052 inst
.error
= _("instruction does not accept unindexed addressing");
11055 /* Table of Thumb instructions which exist in both 16- and 32-bit
11056 encodings (the latter only in post-V6T2 cores). The index is the
11057 value used in the insns table below. When there is more than one
11058 possible 16-bit encoding for the instruction, this table always
11060 Also contains several pseudo-instructions used during relaxation. */
11061 #define T16_32_TAB \
11062 X(_adc, 4140, eb400000), \
11063 X(_adcs, 4140, eb500000), \
11064 X(_add, 1c00, eb000000), \
11065 X(_adds, 1c00, eb100000), \
11066 X(_addi, 0000, f1000000), \
11067 X(_addis, 0000, f1100000), \
11068 X(_add_pc,000f, f20f0000), \
11069 X(_add_sp,000d, f10d0000), \
11070 X(_adr, 000f, f20f0000), \
11071 X(_and, 4000, ea000000), \
11072 X(_ands, 4000, ea100000), \
11073 X(_asr, 1000, fa40f000), \
11074 X(_asrs, 1000, fa50f000), \
11075 X(_b, e000, f000b000), \
11076 X(_bcond, d000, f0008000), \
11077 X(_bf, 0000, f040e001), \
11078 X(_bfcsel,0000, f000e001), \
11079 X(_bfx, 0000, f060e001), \
11080 X(_bfl, 0000, f000c001), \
11081 X(_bflx, 0000, f070e001), \
11082 X(_bic, 4380, ea200000), \
11083 X(_bics, 4380, ea300000), \
11084 X(_cmn, 42c0, eb100f00), \
11085 X(_cmp, 2800, ebb00f00), \
11086 X(_cpsie, b660, f3af8400), \
11087 X(_cpsid, b670, f3af8600), \
11088 X(_cpy, 4600, ea4f0000), \
11089 X(_dec_sp,80dd, f1ad0d00), \
11090 X(_dls, 0000, f040e001), \
11091 X(_eor, 4040, ea800000), \
11092 X(_eors, 4040, ea900000), \
11093 X(_inc_sp,00dd, f10d0d00), \
11094 X(_ldmia, c800, e8900000), \
11095 X(_ldr, 6800, f8500000), \
11096 X(_ldrb, 7800, f8100000), \
11097 X(_ldrh, 8800, f8300000), \
11098 X(_ldrsb, 5600, f9100000), \
11099 X(_ldrsh, 5e00, f9300000), \
11100 X(_ldr_pc,4800, f85f0000), \
11101 X(_ldr_pc2,4800, f85f0000), \
11102 X(_ldr_sp,9800, f85d0000), \
11103 X(_le, 0000, f00fc001), \
11104 X(_lsl, 0000, fa00f000), \
11105 X(_lsls, 0000, fa10f000), \
11106 X(_lsr, 0800, fa20f000), \
11107 X(_lsrs, 0800, fa30f000), \
11108 X(_mov, 2000, ea4f0000), \
11109 X(_movs, 2000, ea5f0000), \
11110 X(_mul, 4340, fb00f000), \
11111 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11112 X(_mvn, 43c0, ea6f0000), \
11113 X(_mvns, 43c0, ea7f0000), \
11114 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11115 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11116 X(_orr, 4300, ea400000), \
11117 X(_orrs, 4300, ea500000), \
11118 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11119 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11120 X(_rev, ba00, fa90f080), \
11121 X(_rev16, ba40, fa90f090), \
11122 X(_revsh, bac0, fa90f0b0), \
11123 X(_ror, 41c0, fa60f000), \
11124 X(_rors, 41c0, fa70f000), \
11125 X(_sbc, 4180, eb600000), \
11126 X(_sbcs, 4180, eb700000), \
11127 X(_stmia, c000, e8800000), \
11128 X(_str, 6000, f8400000), \
11129 X(_strb, 7000, f8000000), \
11130 X(_strh, 8000, f8200000), \
11131 X(_str_sp,9000, f84d0000), \
11132 X(_sub, 1e00, eba00000), \
11133 X(_subs, 1e00, ebb00000), \
11134 X(_subi, 8000, f1a00000), \
11135 X(_subis, 8000, f1b00000), \
11136 X(_sxtb, b240, fa4ff080), \
11137 X(_sxth, b200, fa0ff080), \
11138 X(_tst, 4200, ea100f00), \
11139 X(_uxtb, b2c0, fa5ff080), \
11140 X(_uxth, b280, fa1ff080), \
11141 X(_nop, bf00, f3af8000), \
11142 X(_yield, bf10, f3af8001), \
11143 X(_wfe, bf20, f3af8002), \
11144 X(_wfi, bf30, f3af8003), \
11145 X(_wls, 0000, f040c001), \
11146 X(_sev, bf40, f3af8004), \
11147 X(_sevl, bf50, f3af8005), \
11148 X(_udf, de00, f7f0a000)
11150 /* To catch errors in encoding functions, the codes are all offset by
11151 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11152 as 16-bit instructions. */
11153 #define X(a,b,c) T_MNEM##a
11154 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11157 #define X(a,b,c) 0x##b
11158 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11159 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11162 #define X(a,b,c) 0x##c
11163 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11164 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11165 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11169 /* Thumb instruction encoders, in alphabetical order. */
11171 /* ADDW or SUBW. */
11174 do_t_add_sub_w (void)
11178 Rd
= inst
.operands
[0].reg
;
11179 Rn
= inst
.operands
[1].reg
;
11181 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11182 is the SP-{plus,minus}-immediate form of the instruction. */
11184 constraint (Rd
== REG_PC
, BAD_PC
);
11186 reject_bad_reg (Rd
);
11188 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11189 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11192 /* Parse an add or subtract instruction. We get here with inst.instruction
11193 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11196 do_t_add_sub (void)
11200 Rd
= inst
.operands
[0].reg
;
11201 Rs
= (inst
.operands
[1].present
11202 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11203 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11206 set_pred_insn_type_last ();
11208 if (unified_syntax
)
11211 bfd_boolean narrow
;
11214 flags
= (inst
.instruction
== T_MNEM_adds
11215 || inst
.instruction
== T_MNEM_subs
);
11217 narrow
= !in_pred_block ();
11219 narrow
= in_pred_block ();
11220 if (!inst
.operands
[2].isreg
)
11224 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11225 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11227 add
= (inst
.instruction
== T_MNEM_add
11228 || inst
.instruction
== T_MNEM_adds
);
11230 if (inst
.size_req
!= 4)
11232 /* Attempt to use a narrow opcode, with relaxation if
11234 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11235 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11236 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11237 opcode
= T_MNEM_add_sp
;
11238 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11239 opcode
= T_MNEM_add_pc
;
11240 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11243 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11245 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11249 inst
.instruction
= THUMB_OP16(opcode
);
11250 inst
.instruction
|= (Rd
<< 4) | Rs
;
11251 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11252 || (inst
.relocs
[0].type
11253 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11255 if (inst
.size_req
== 2)
11256 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11258 inst
.relax
= opcode
;
11262 constraint (inst
.size_req
== 2, BAD_HIREG
);
11264 if (inst
.size_req
== 4
11265 || (inst
.size_req
!= 2 && !opcode
))
11267 constraint ((inst
.relocs
[0].type
11268 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11269 && (inst
.relocs
[0].type
11270 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11271 THUMB1_RELOC_ONLY
);
11274 constraint (add
, BAD_PC
);
11275 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11276 _("only SUBS PC, LR, #const allowed"));
11277 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11278 _("expression too complex"));
11279 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11280 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11281 _("immediate value out of range"));
11282 inst
.instruction
= T2_SUBS_PC_LR
11283 | inst
.relocs
[0].exp
.X_add_number
;
11284 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11287 else if (Rs
== REG_PC
)
11289 /* Always use addw/subw. */
11290 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11291 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11295 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11296 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11299 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11301 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11303 inst
.instruction
|= Rd
<< 8;
11304 inst
.instruction
|= Rs
<< 16;
11309 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11310 unsigned int shift
= inst
.operands
[2].shift_kind
;
11312 Rn
= inst
.operands
[2].reg
;
11313 /* See if we can do this with a 16-bit instruction. */
11314 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11316 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11321 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11322 || inst
.instruction
== T_MNEM_add
)
11324 : T_OPCODE_SUB_R3
);
11325 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11329 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11331 /* Thumb-1 cores (except v6-M) require at least one high
11332 register in a narrow non flag setting add. */
11333 if (Rd
> 7 || Rn
> 7
11334 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11335 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11342 inst
.instruction
= T_OPCODE_ADD_HI
;
11343 inst
.instruction
|= (Rd
& 8) << 4;
11344 inst
.instruction
|= (Rd
& 7);
11345 inst
.instruction
|= Rn
<< 3;
11351 constraint (Rd
== REG_PC
, BAD_PC
);
11352 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11353 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11354 constraint (Rs
== REG_PC
, BAD_PC
);
11355 reject_bad_reg (Rn
);
11357 /* If we get here, it can't be done in 16 bits. */
11358 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11359 _("shift must be constant"));
11360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11361 inst
.instruction
|= Rd
<< 8;
11362 inst
.instruction
|= Rs
<< 16;
11363 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11364 _("shift value over 3 not allowed in thumb mode"));
11365 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11366 _("only LSL shift allowed in thumb mode"));
11367 encode_thumb32_shifted_operand (2);
11372 constraint (inst
.instruction
== T_MNEM_adds
11373 || inst
.instruction
== T_MNEM_subs
,
11376 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11378 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11379 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11382 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11383 ? 0x0000 : 0x8000);
11384 inst
.instruction
|= (Rd
<< 4) | Rs
;
11385 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11389 Rn
= inst
.operands
[2].reg
;
11390 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11392 /* We now have Rd, Rs, and Rn set to registers. */
11393 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11395 /* Can't do this for SUB. */
11396 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11397 inst
.instruction
= T_OPCODE_ADD_HI
;
11398 inst
.instruction
|= (Rd
& 8) << 4;
11399 inst
.instruction
|= (Rd
& 7);
11401 inst
.instruction
|= Rn
<< 3;
11403 inst
.instruction
|= Rs
<< 3;
11405 constraint (1, _("dest must overlap one source register"));
11409 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11410 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11411 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11421 Rd
= inst
.operands
[0].reg
;
11422 reject_bad_reg (Rd
);
11424 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11426 /* Defer to section relaxation. */
11427 inst
.relax
= inst
.instruction
;
11428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11429 inst
.instruction
|= Rd
<< 4;
11431 else if (unified_syntax
&& inst
.size_req
!= 2)
11433 /* Generate a 32-bit opcode. */
11434 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11435 inst
.instruction
|= Rd
<< 8;
11436 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11437 inst
.relocs
[0].pc_rel
= 1;
11441 /* Generate a 16-bit opcode. */
11442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11443 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11444 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11445 inst
.relocs
[0].pc_rel
= 1;
11446 inst
.instruction
|= Rd
<< 4;
11449 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11450 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11451 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11452 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11453 inst
.relocs
[0].exp
.X_add_number
+= 1;
11456 /* Arithmetic instructions for which there is just one 16-bit
11457 instruction encoding, and it allows only two low registers.
11458 For maximal compatibility with ARM syntax, we allow three register
11459 operands even when Thumb-32 instructions are not available, as long
11460 as the first two are identical. For instance, both "sbc r0,r1" and
11461 "sbc r0,r0,r1" are allowed. */
11467 Rd
= inst
.operands
[0].reg
;
11468 Rs
= (inst
.operands
[1].present
11469 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11470 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11471 Rn
= inst
.operands
[2].reg
;
11473 reject_bad_reg (Rd
);
11474 reject_bad_reg (Rs
);
11475 if (inst
.operands
[2].isreg
)
11476 reject_bad_reg (Rn
);
11478 if (unified_syntax
)
11480 if (!inst
.operands
[2].isreg
)
11482 /* For an immediate, we always generate a 32-bit opcode;
11483 section relaxation will shrink it later if possible. */
11484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11485 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11486 inst
.instruction
|= Rd
<< 8;
11487 inst
.instruction
|= Rs
<< 16;
11488 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11492 bfd_boolean narrow
;
11494 /* See if we can do this with a 16-bit instruction. */
11495 if (THUMB_SETS_FLAGS (inst
.instruction
))
11496 narrow
= !in_pred_block ();
11498 narrow
= in_pred_block ();
11500 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11502 if (inst
.operands
[2].shifted
)
11504 if (inst
.size_req
== 4)
11510 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11511 inst
.instruction
|= Rd
;
11512 inst
.instruction
|= Rn
<< 3;
11516 /* If we get here, it can't be done in 16 bits. */
11517 constraint (inst
.operands
[2].shifted
11518 && inst
.operands
[2].immisreg
,
11519 _("shift must be constant"));
11520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11521 inst
.instruction
|= Rd
<< 8;
11522 inst
.instruction
|= Rs
<< 16;
11523 encode_thumb32_shifted_operand (2);
11528 /* On its face this is a lie - the instruction does set the
11529 flags. However, the only supported mnemonic in this mode
11530 says it doesn't. */
11531 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11533 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11534 _("unshifted register required"));
11535 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11536 constraint (Rd
!= Rs
,
11537 _("dest and source1 must be the same register"));
11539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11540 inst
.instruction
|= Rd
;
11541 inst
.instruction
|= Rn
<< 3;
11545 /* Similarly, but for instructions where the arithmetic operation is
11546 commutative, so we can allow either of them to be different from
11547 the destination operand in a 16-bit instruction. For instance, all
11548 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11555 Rd
= inst
.operands
[0].reg
;
11556 Rs
= (inst
.operands
[1].present
11557 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11558 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11559 Rn
= inst
.operands
[2].reg
;
11561 reject_bad_reg (Rd
);
11562 reject_bad_reg (Rs
);
11563 if (inst
.operands
[2].isreg
)
11564 reject_bad_reg (Rn
);
11566 if (unified_syntax
)
11568 if (!inst
.operands
[2].isreg
)
11570 /* For an immediate, we always generate a 32-bit opcode;
11571 section relaxation will shrink it later if possible. */
11572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11573 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11574 inst
.instruction
|= Rd
<< 8;
11575 inst
.instruction
|= Rs
<< 16;
11576 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11580 bfd_boolean narrow
;
11582 /* See if we can do this with a 16-bit instruction. */
11583 if (THUMB_SETS_FLAGS (inst
.instruction
))
11584 narrow
= !in_pred_block ();
11586 narrow
= in_pred_block ();
11588 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11590 if (inst
.operands
[2].shifted
)
11592 if (inst
.size_req
== 4)
11599 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11600 inst
.instruction
|= Rd
;
11601 inst
.instruction
|= Rn
<< 3;
11606 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11607 inst
.instruction
|= Rd
;
11608 inst
.instruction
|= Rs
<< 3;
11613 /* If we get here, it can't be done in 16 bits. */
11614 constraint (inst
.operands
[2].shifted
11615 && inst
.operands
[2].immisreg
,
11616 _("shift must be constant"));
11617 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11618 inst
.instruction
|= Rd
<< 8;
11619 inst
.instruction
|= Rs
<< 16;
11620 encode_thumb32_shifted_operand (2);
11625 /* On its face this is a lie - the instruction does set the
11626 flags. However, the only supported mnemonic in this mode
11627 says it doesn't. */
11628 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11630 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11631 _("unshifted register required"));
11632 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11635 inst
.instruction
|= Rd
;
11638 inst
.instruction
|= Rn
<< 3;
11640 inst
.instruction
|= Rs
<< 3;
11642 constraint (1, _("dest must overlap one source register"));
11650 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11651 constraint (msb
> 32, _("bit-field extends past end of register"));
11652 /* The instruction encoding stores the LSB and MSB,
11653 not the LSB and width. */
11654 Rd
= inst
.operands
[0].reg
;
11655 reject_bad_reg (Rd
);
11656 inst
.instruction
|= Rd
<< 8;
11657 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11658 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11659 inst
.instruction
|= msb
- 1;
11668 Rd
= inst
.operands
[0].reg
;
11669 reject_bad_reg (Rd
);
11671 /* #0 in second position is alternative syntax for bfc, which is
11672 the same instruction but with REG_PC in the Rm field. */
11673 if (!inst
.operands
[1].isreg
)
11677 Rn
= inst
.operands
[1].reg
;
11678 reject_bad_reg (Rn
);
11681 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11682 constraint (msb
> 32, _("bit-field extends past end of register"));
11683 /* The instruction encoding stores the LSB and MSB,
11684 not the LSB and width. */
11685 inst
.instruction
|= Rd
<< 8;
11686 inst
.instruction
|= Rn
<< 16;
11687 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11688 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11689 inst
.instruction
|= msb
- 1;
11697 Rd
= inst
.operands
[0].reg
;
11698 Rn
= inst
.operands
[1].reg
;
11700 reject_bad_reg (Rd
);
11701 reject_bad_reg (Rn
);
11703 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11704 _("bit-field extends past end of register"));
11705 inst
.instruction
|= Rd
<< 8;
11706 inst
.instruction
|= Rn
<< 16;
11707 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11708 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11709 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11712 /* ARM V5 Thumb BLX (argument parse)
11713 BLX <target_addr> which is BLX(1)
11714 BLX <Rm> which is BLX(2)
11715 Unfortunately, there are two different opcodes for this mnemonic.
11716 So, the insns[].value is not used, and the code here zaps values
11717 into inst.instruction.
11719 ??? How to take advantage of the additional two bits of displacement
11720 available in Thumb32 mode? Need new relocation? */
11725 set_pred_insn_type_last ();
11727 if (inst
.operands
[0].isreg
)
11729 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11730 /* We have a register, so this is BLX(2). */
11731 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11735 /* No register. This must be BLX(1). */
11736 inst
.instruction
= 0xf000e800;
11737 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11746 bfd_reloc_code_real_type reloc
;
11749 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11751 if (in_pred_block ())
11753 /* Conditional branches inside IT blocks are encoded as unconditional
11755 cond
= COND_ALWAYS
;
11760 if (cond
!= COND_ALWAYS
)
11761 opcode
= T_MNEM_bcond
;
11763 opcode
= inst
.instruction
;
11766 && (inst
.size_req
== 4
11767 || (inst
.size_req
!= 2
11768 && (inst
.operands
[0].hasreloc
11769 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11771 inst
.instruction
= THUMB_OP32(opcode
);
11772 if (cond
== COND_ALWAYS
)
11773 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11777 _("selected architecture does not support "
11778 "wide conditional branch instruction"));
11780 gas_assert (cond
!= 0xF);
11781 inst
.instruction
|= cond
<< 22;
11782 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11787 inst
.instruction
= THUMB_OP16(opcode
);
11788 if (cond
== COND_ALWAYS
)
11789 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11792 inst
.instruction
|= cond
<< 8;
11793 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11795 /* Allow section relaxation. */
11796 if (unified_syntax
&& inst
.size_req
!= 2)
11797 inst
.relax
= opcode
;
11799 inst
.relocs
[0].type
= reloc
;
11800 inst
.relocs
[0].pc_rel
= 1;
11803 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11804 between the two is the maximum immediate allowed - which is passed in
11807 do_t_bkpt_hlt1 (int range
)
11809 constraint (inst
.cond
!= COND_ALWAYS
,
11810 _("instruction is always unconditional"));
11811 if (inst
.operands
[0].present
)
11813 constraint (inst
.operands
[0].imm
> range
,
11814 _("immediate value out of range"));
11815 inst
.instruction
|= inst
.operands
[0].imm
;
11818 set_pred_insn_type (NEUTRAL_IT_INSN
);
11824 do_t_bkpt_hlt1 (63);
11830 do_t_bkpt_hlt1 (255);
11834 do_t_branch23 (void)
11836 set_pred_insn_type_last ();
11837 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11839 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11840 this file. We used to simply ignore the PLT reloc type here --
11841 the branch encoding is now needed to deal with TLSCALL relocs.
11842 So if we see a PLT reloc now, put it back to how it used to be to
11843 keep the preexisting behaviour. */
11844 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11845 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11847 #if defined(OBJ_COFF)
11848 /* If the destination of the branch is a defined symbol which does not have
11849 the THUMB_FUNC attribute, then we must be calling a function which has
11850 the (interfacearm) attribute. We look for the Thumb entry point to that
11851 function and change the branch to refer to that function instead. */
11852 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11853 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11854 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11855 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11856 inst
.relocs
[0].exp
.X_add_symbol
11857 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11864 set_pred_insn_type_last ();
11865 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11866 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11867 should cause the alignment to be checked once it is known. This is
11868 because BX PC only works if the instruction is word aligned. */
11876 set_pred_insn_type_last ();
11877 Rm
= inst
.operands
[0].reg
;
11878 reject_bad_reg (Rm
);
11879 inst
.instruction
|= Rm
<< 16;
11888 Rd
= inst
.operands
[0].reg
;
11889 Rm
= inst
.operands
[1].reg
;
11891 reject_bad_reg (Rd
);
11892 reject_bad_reg (Rm
);
11894 inst
.instruction
|= Rd
<< 8;
11895 inst
.instruction
|= Rm
<< 16;
11896 inst
.instruction
|= Rm
;
11902 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11908 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11909 inst
.instruction
|= inst
.operands
[0].imm
;
11915 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11917 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11918 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11920 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11921 inst
.instruction
= 0xf3af8000;
11922 inst
.instruction
|= imod
<< 9;
11923 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11924 if (inst
.operands
[1].present
)
11925 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11930 && (inst
.operands
[0].imm
& 4),
11931 _("selected processor does not support 'A' form "
11932 "of this instruction"));
11933 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11934 _("Thumb does not support the 2-argument "
11935 "form of this instruction"));
11936 inst
.instruction
|= inst
.operands
[0].imm
;
11940 /* THUMB CPY instruction (argument parse). */
11945 if (inst
.size_req
== 4)
11947 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11948 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11949 inst
.instruction
|= inst
.operands
[1].reg
;
11953 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11954 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11955 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11962 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11963 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11964 inst
.instruction
|= inst
.operands
[0].reg
;
11965 inst
.relocs
[0].pc_rel
= 1;
11966 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11972 inst
.instruction
|= inst
.operands
[0].imm
;
11978 unsigned Rd
, Rn
, Rm
;
11980 Rd
= inst
.operands
[0].reg
;
11981 Rn
= (inst
.operands
[1].present
11982 ? inst
.operands
[1].reg
: Rd
);
11983 Rm
= inst
.operands
[2].reg
;
11985 reject_bad_reg (Rd
);
11986 reject_bad_reg (Rn
);
11987 reject_bad_reg (Rm
);
11989 inst
.instruction
|= Rd
<< 8;
11990 inst
.instruction
|= Rn
<< 16;
11991 inst
.instruction
|= Rm
;
11997 if (unified_syntax
&& inst
.size_req
== 4)
11998 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12006 unsigned int cond
= inst
.operands
[0].imm
;
12008 set_pred_insn_type (IT_INSN
);
12009 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12010 now_pred
.cc
= cond
;
12011 now_pred
.warn_deprecated
= FALSE
;
12012 now_pred
.type
= SCALAR_PRED
;
12014 /* If the condition is a negative condition, invert the mask. */
12015 if ((cond
& 0x1) == 0x0)
12017 unsigned int mask
= inst
.instruction
& 0x000f;
12019 if ((mask
& 0x7) == 0)
12021 /* No conversion needed. */
12022 now_pred
.block_length
= 1;
12024 else if ((mask
& 0x3) == 0)
12027 now_pred
.block_length
= 2;
12029 else if ((mask
& 0x1) == 0)
12032 now_pred
.block_length
= 3;
12037 now_pred
.block_length
= 4;
12040 inst
.instruction
&= 0xfff0;
12041 inst
.instruction
|= mask
;
12044 inst
.instruction
|= cond
<< 4;
12047 /* Helper function used for both push/pop and ldm/stm. */
12049 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12050 bfd_boolean writeback
)
12052 bfd_boolean load
, store
;
12054 gas_assert (base
!= -1 || !do_io
);
12055 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12056 store
= do_io
&& !load
;
12058 if (mask
& (1 << 13))
12059 inst
.error
= _("SP not allowed in register list");
12061 if (do_io
&& (mask
& (1 << base
)) != 0
12063 inst
.error
= _("having the base register in the register list when "
12064 "using write back is UNPREDICTABLE");
12068 if (mask
& (1 << 15))
12070 if (mask
& (1 << 14))
12071 inst
.error
= _("LR and PC should not both be in register list");
12073 set_pred_insn_type_last ();
12078 if (mask
& (1 << 15))
12079 inst
.error
= _("PC not allowed in register list");
12082 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12084 /* Single register transfers implemented as str/ldr. */
12087 if (inst
.instruction
& (1 << 23))
12088 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12090 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12094 if (inst
.instruction
& (1 << 23))
12095 inst
.instruction
= 0x00800000; /* ia -> [base] */
12097 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12100 inst
.instruction
|= 0xf8400000;
12102 inst
.instruction
|= 0x00100000;
12104 mask
= ffs (mask
) - 1;
12107 else if (writeback
)
12108 inst
.instruction
|= WRITE_BACK
;
12110 inst
.instruction
|= mask
;
12112 inst
.instruction
|= base
<< 16;
12118 /* This really doesn't seem worth it. */
12119 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12120 _("expression too complex"));
12121 constraint (inst
.operands
[1].writeback
,
12122 _("Thumb load/store multiple does not support {reglist}^"));
12124 if (unified_syntax
)
12126 bfd_boolean narrow
;
12130 /* See if we can use a 16-bit instruction. */
12131 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12132 && inst
.size_req
!= 4
12133 && !(inst
.operands
[1].imm
& ~0xff))
12135 mask
= 1 << inst
.operands
[0].reg
;
12137 if (inst
.operands
[0].reg
<= 7)
12139 if (inst
.instruction
== T_MNEM_stmia
12140 ? inst
.operands
[0].writeback
12141 : (inst
.operands
[0].writeback
12142 == !(inst
.operands
[1].imm
& mask
)))
12144 if (inst
.instruction
== T_MNEM_stmia
12145 && (inst
.operands
[1].imm
& mask
)
12146 && (inst
.operands
[1].imm
& (mask
- 1)))
12147 as_warn (_("value stored for r%d is UNKNOWN"),
12148 inst
.operands
[0].reg
);
12150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12151 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12152 inst
.instruction
|= inst
.operands
[1].imm
;
12155 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12157 /* This means 1 register in reg list one of 3 situations:
12158 1. Instruction is stmia, but without writeback.
12159 2. lmdia without writeback, but with Rn not in
12161 3. ldmia with writeback, but with Rn in reglist.
12162 Case 3 is UNPREDICTABLE behaviour, so we handle
12163 case 1 and 2 which can be converted into a 16-bit
12164 str or ldr. The SP cases are handled below. */
12165 unsigned long opcode
;
12166 /* First, record an error for Case 3. */
12167 if (inst
.operands
[1].imm
& mask
12168 && inst
.operands
[0].writeback
)
12170 _("having the base register in the register list when "
12171 "using write back is UNPREDICTABLE");
12173 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12175 inst
.instruction
= THUMB_OP16 (opcode
);
12176 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12177 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12181 else if (inst
.operands
[0] .reg
== REG_SP
)
12183 if (inst
.operands
[0].writeback
)
12186 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12187 ? T_MNEM_push
: T_MNEM_pop
);
12188 inst
.instruction
|= inst
.operands
[1].imm
;
12191 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12194 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12195 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12196 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12204 if (inst
.instruction
< 0xffff)
12205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12207 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12208 inst
.operands
[1].imm
,
12209 inst
.operands
[0].writeback
);
12214 constraint (inst
.operands
[0].reg
> 7
12215 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12216 constraint (inst
.instruction
!= T_MNEM_ldmia
12217 && inst
.instruction
!= T_MNEM_stmia
,
12218 _("Thumb-2 instruction only valid in unified syntax"));
12219 if (inst
.instruction
== T_MNEM_stmia
)
12221 if (!inst
.operands
[0].writeback
)
12222 as_warn (_("this instruction will write back the base register"));
12223 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12224 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12225 as_warn (_("value stored for r%d is UNKNOWN"),
12226 inst
.operands
[0].reg
);
12230 if (!inst
.operands
[0].writeback
12231 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12232 as_warn (_("this instruction will write back the base register"));
12233 else if (inst
.operands
[0].writeback
12234 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12235 as_warn (_("this instruction will not write back the base register"));
12238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12239 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12240 inst
.instruction
|= inst
.operands
[1].imm
;
12247 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12248 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12249 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12250 || inst
.operands
[1].negative
,
12253 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12256 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12257 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12263 if (!inst
.operands
[1].present
)
12265 constraint (inst
.operands
[0].reg
== REG_LR
,
12266 _("r14 not allowed as first register "
12267 "when second register is omitted"));
12268 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12270 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12274 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12275 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12281 unsigned long opcode
;
12284 if (inst
.operands
[0].isreg
12285 && !inst
.operands
[0].preind
12286 && inst
.operands
[0].reg
== REG_PC
)
12287 set_pred_insn_type_last ();
12289 opcode
= inst
.instruction
;
12290 if (unified_syntax
)
12292 if (!inst
.operands
[1].isreg
)
12294 if (opcode
<= 0xffff)
12295 inst
.instruction
= THUMB_OP32 (opcode
);
12296 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12299 if (inst
.operands
[1].isreg
12300 && !inst
.operands
[1].writeback
12301 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12302 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12303 && opcode
<= 0xffff
12304 && inst
.size_req
!= 4)
12306 /* Insn may have a 16-bit form. */
12307 Rn
= inst
.operands
[1].reg
;
12308 if (inst
.operands
[1].immisreg
)
12310 inst
.instruction
= THUMB_OP16 (opcode
);
12312 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12314 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12315 reject_bad_reg (inst
.operands
[1].imm
);
12317 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12318 && opcode
!= T_MNEM_ldrsb
)
12319 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12320 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12327 if (inst
.relocs
[0].pc_rel
)
12328 opcode
= T_MNEM_ldr_pc2
;
12330 opcode
= T_MNEM_ldr_pc
;
12334 if (opcode
== T_MNEM_ldr
)
12335 opcode
= T_MNEM_ldr_sp
;
12337 opcode
= T_MNEM_str_sp
;
12339 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12343 inst
.instruction
= inst
.operands
[0].reg
;
12344 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12346 inst
.instruction
|= THUMB_OP16 (opcode
);
12347 if (inst
.size_req
== 2)
12348 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12350 inst
.relax
= opcode
;
12354 /* Definitely a 32-bit variant. */
12356 /* Warning for Erratum 752419. */
12357 if (opcode
== T_MNEM_ldr
12358 && inst
.operands
[0].reg
== REG_SP
12359 && inst
.operands
[1].writeback
== 1
12360 && !inst
.operands
[1].immisreg
)
12362 if (no_cpu_selected ()
12363 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12364 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12365 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12366 as_warn (_("This instruction may be unpredictable "
12367 "if executed on M-profile cores "
12368 "with interrupts enabled."));
12371 /* Do some validations regarding addressing modes. */
12372 if (inst
.operands
[1].immisreg
)
12373 reject_bad_reg (inst
.operands
[1].imm
);
12375 constraint (inst
.operands
[1].writeback
== 1
12376 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12379 inst
.instruction
= THUMB_OP32 (opcode
);
12380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12381 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12382 check_ldr_r15_aligned ();
12386 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12388 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12390 /* Only [Rn,Rm] is acceptable. */
12391 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12392 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12393 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12394 || inst
.operands
[1].negative
,
12395 _("Thumb does not support this addressing mode"));
12396 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12401 if (!inst
.operands
[1].isreg
)
12402 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12405 constraint (!inst
.operands
[1].preind
12406 || inst
.operands
[1].shifted
12407 || inst
.operands
[1].writeback
,
12408 _("Thumb does not support this addressing mode"));
12409 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12411 constraint (inst
.instruction
& 0x0600,
12412 _("byte or halfword not valid for base register"));
12413 constraint (inst
.operands
[1].reg
== REG_PC
12414 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12415 _("r15 based store not allowed"));
12416 constraint (inst
.operands
[1].immisreg
,
12417 _("invalid base register for register offset"));
12419 if (inst
.operands
[1].reg
== REG_PC
)
12420 inst
.instruction
= T_OPCODE_LDR_PC
;
12421 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12422 inst
.instruction
= T_OPCODE_LDR_SP
;
12424 inst
.instruction
= T_OPCODE_STR_SP
;
12426 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12427 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12431 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12432 if (!inst
.operands
[1].immisreg
)
12434 /* Immediate offset. */
12435 inst
.instruction
|= inst
.operands
[0].reg
;
12436 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12437 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12441 /* Register offset. */
12442 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12443 constraint (inst
.operands
[1].negative
,
12444 _("Thumb does not support this addressing mode"));
12447 switch (inst
.instruction
)
12449 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12450 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12451 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12452 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12453 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12454 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12455 case 0x5600 /* ldrsb */:
12456 case 0x5e00 /* ldrsh */: break;
12460 inst
.instruction
|= inst
.operands
[0].reg
;
12461 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12462 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12468 if (!inst
.operands
[1].present
)
12470 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12471 constraint (inst
.operands
[0].reg
== REG_LR
,
12472 _("r14 not allowed here"));
12473 constraint (inst
.operands
[0].reg
== REG_R12
,
12474 _("r12 not allowed here"));
12477 if (inst
.operands
[2].writeback
12478 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12479 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12480 as_warn (_("base register written back, and overlaps "
12481 "one of transfer registers"));
12483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12484 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12485 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12491 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12492 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12498 unsigned Rd
, Rn
, Rm
, Ra
;
12500 Rd
= inst
.operands
[0].reg
;
12501 Rn
= inst
.operands
[1].reg
;
12502 Rm
= inst
.operands
[2].reg
;
12503 Ra
= inst
.operands
[3].reg
;
12505 reject_bad_reg (Rd
);
12506 reject_bad_reg (Rn
);
12507 reject_bad_reg (Rm
);
12508 reject_bad_reg (Ra
);
12510 inst
.instruction
|= Rd
<< 8;
12511 inst
.instruction
|= Rn
<< 16;
12512 inst
.instruction
|= Rm
;
12513 inst
.instruction
|= Ra
<< 12;
12519 unsigned RdLo
, RdHi
, Rn
, Rm
;
12521 RdLo
= inst
.operands
[0].reg
;
12522 RdHi
= inst
.operands
[1].reg
;
12523 Rn
= inst
.operands
[2].reg
;
12524 Rm
= inst
.operands
[3].reg
;
12526 reject_bad_reg (RdLo
);
12527 reject_bad_reg (RdHi
);
12528 reject_bad_reg (Rn
);
12529 reject_bad_reg (Rm
);
12531 inst
.instruction
|= RdLo
<< 12;
12532 inst
.instruction
|= RdHi
<< 8;
12533 inst
.instruction
|= Rn
<< 16;
12534 inst
.instruction
|= Rm
;
12538 do_t_mov_cmp (void)
12542 Rn
= inst
.operands
[0].reg
;
12543 Rm
= inst
.operands
[1].reg
;
12546 set_pred_insn_type_last ();
12548 if (unified_syntax
)
12550 int r0off
= (inst
.instruction
== T_MNEM_mov
12551 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12552 unsigned long opcode
;
12553 bfd_boolean narrow
;
12554 bfd_boolean low_regs
;
12556 low_regs
= (Rn
<= 7 && Rm
<= 7);
12557 opcode
= inst
.instruction
;
12558 if (in_pred_block ())
12559 narrow
= opcode
!= T_MNEM_movs
;
12561 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12562 if (inst
.size_req
== 4
12563 || inst
.operands
[1].shifted
)
12566 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12567 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12568 && !inst
.operands
[1].shifted
12572 inst
.instruction
= T2_SUBS_PC_LR
;
12576 if (opcode
== T_MNEM_cmp
)
12578 constraint (Rn
== REG_PC
, BAD_PC
);
12581 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12583 warn_deprecated_sp (Rm
);
12584 /* R15 was documented as a valid choice for Rm in ARMv6,
12585 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12586 tools reject R15, so we do too. */
12587 constraint (Rm
== REG_PC
, BAD_PC
);
12590 reject_bad_reg (Rm
);
12592 else if (opcode
== T_MNEM_mov
12593 || opcode
== T_MNEM_movs
)
12595 if (inst
.operands
[1].isreg
)
12597 if (opcode
== T_MNEM_movs
)
12599 reject_bad_reg (Rn
);
12600 reject_bad_reg (Rm
);
12604 /* This is mov.n. */
12605 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12606 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12608 as_tsktsk (_("Use of r%u as a source register is "
12609 "deprecated when r%u is the destination "
12610 "register."), Rm
, Rn
);
12615 /* This is mov.w. */
12616 constraint (Rn
== REG_PC
, BAD_PC
);
12617 constraint (Rm
== REG_PC
, BAD_PC
);
12618 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12619 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12623 reject_bad_reg (Rn
);
12626 if (!inst
.operands
[1].isreg
)
12628 /* Immediate operand. */
12629 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12631 if (low_regs
&& narrow
)
12633 inst
.instruction
= THUMB_OP16 (opcode
);
12634 inst
.instruction
|= Rn
<< 8;
12635 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12636 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12638 if (inst
.size_req
== 2)
12639 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12641 inst
.relax
= opcode
;
12646 constraint ((inst
.relocs
[0].type
12647 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12648 && (inst
.relocs
[0].type
12649 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12650 THUMB1_RELOC_ONLY
);
12652 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12653 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12654 inst
.instruction
|= Rn
<< r0off
;
12655 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12658 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12659 && (inst
.instruction
== T_MNEM_mov
12660 || inst
.instruction
== T_MNEM_movs
))
12662 /* Register shifts are encoded as separate shift instructions. */
12663 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12665 if (in_pred_block ())
12670 if (inst
.size_req
== 4)
12673 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12679 switch (inst
.operands
[1].shift_kind
)
12682 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12685 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12688 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12691 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12697 inst
.instruction
= opcode
;
12700 inst
.instruction
|= Rn
;
12701 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12706 inst
.instruction
|= CONDS_BIT
;
12708 inst
.instruction
|= Rn
<< 8;
12709 inst
.instruction
|= Rm
<< 16;
12710 inst
.instruction
|= inst
.operands
[1].imm
;
12715 /* Some mov with immediate shift have narrow variants.
12716 Register shifts are handled above. */
12717 if (low_regs
&& inst
.operands
[1].shifted
12718 && (inst
.instruction
== T_MNEM_mov
12719 || inst
.instruction
== T_MNEM_movs
))
12721 if (in_pred_block ())
12722 narrow
= (inst
.instruction
== T_MNEM_mov
);
12724 narrow
= (inst
.instruction
== T_MNEM_movs
);
12729 switch (inst
.operands
[1].shift_kind
)
12731 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12732 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12733 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12734 default: narrow
= FALSE
; break;
12740 inst
.instruction
|= Rn
;
12741 inst
.instruction
|= Rm
<< 3;
12742 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12747 inst
.instruction
|= Rn
<< r0off
;
12748 encode_thumb32_shifted_operand (1);
12752 switch (inst
.instruction
)
12755 /* In v4t or v5t a move of two lowregs produces unpredictable
12756 results. Don't allow this. */
12759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12760 "MOV Rd, Rs with two low registers is not "
12761 "permitted on this architecture");
12762 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12766 inst
.instruction
= T_OPCODE_MOV_HR
;
12767 inst
.instruction
|= (Rn
& 0x8) << 4;
12768 inst
.instruction
|= (Rn
& 0x7);
12769 inst
.instruction
|= Rm
<< 3;
12773 /* We know we have low registers at this point.
12774 Generate LSLS Rd, Rs, #0. */
12775 inst
.instruction
= T_OPCODE_LSL_I
;
12776 inst
.instruction
|= Rn
;
12777 inst
.instruction
|= Rm
<< 3;
12783 inst
.instruction
= T_OPCODE_CMP_LR
;
12784 inst
.instruction
|= Rn
;
12785 inst
.instruction
|= Rm
<< 3;
12789 inst
.instruction
= T_OPCODE_CMP_HR
;
12790 inst
.instruction
|= (Rn
& 0x8) << 4;
12791 inst
.instruction
|= (Rn
& 0x7);
12792 inst
.instruction
|= Rm
<< 3;
12799 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12801 /* PR 10443: Do not silently ignore shifted operands. */
12802 constraint (inst
.operands
[1].shifted
,
12803 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12805 if (inst
.operands
[1].isreg
)
12807 if (Rn
< 8 && Rm
< 8)
12809 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12810 since a MOV instruction produces unpredictable results. */
12811 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12812 inst
.instruction
= T_OPCODE_ADD_I3
;
12814 inst
.instruction
= T_OPCODE_CMP_LR
;
12816 inst
.instruction
|= Rn
;
12817 inst
.instruction
|= Rm
<< 3;
12821 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12822 inst
.instruction
= T_OPCODE_MOV_HR
;
12824 inst
.instruction
= T_OPCODE_CMP_HR
;
12830 constraint (Rn
> 7,
12831 _("only lo regs allowed with immediate"));
12832 inst
.instruction
|= Rn
<< 8;
12833 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12844 top
= (inst
.instruction
& 0x00800000) != 0;
12845 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12847 constraint (top
, _(":lower16: not allowed in this instruction"));
12848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12850 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12852 constraint (!top
, _(":upper16: not allowed in this instruction"));
12853 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12856 Rd
= inst
.operands
[0].reg
;
12857 reject_bad_reg (Rd
);
12859 inst
.instruction
|= Rd
<< 8;
12860 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12862 imm
= inst
.relocs
[0].exp
.X_add_number
;
12863 inst
.instruction
|= (imm
& 0xf000) << 4;
12864 inst
.instruction
|= (imm
& 0x0800) << 15;
12865 inst
.instruction
|= (imm
& 0x0700) << 4;
12866 inst
.instruction
|= (imm
& 0x00ff);
12871 do_t_mvn_tst (void)
12875 Rn
= inst
.operands
[0].reg
;
12876 Rm
= inst
.operands
[1].reg
;
12878 if (inst
.instruction
== T_MNEM_cmp
12879 || inst
.instruction
== T_MNEM_cmn
)
12880 constraint (Rn
== REG_PC
, BAD_PC
);
12882 reject_bad_reg (Rn
);
12883 reject_bad_reg (Rm
);
12885 if (unified_syntax
)
12887 int r0off
= (inst
.instruction
== T_MNEM_mvn
12888 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12889 bfd_boolean narrow
;
12891 if (inst
.size_req
== 4
12892 || inst
.instruction
> 0xffff
12893 || inst
.operands
[1].shifted
12894 || Rn
> 7 || Rm
> 7)
12896 else if (inst
.instruction
== T_MNEM_cmn
12897 || inst
.instruction
== T_MNEM_tst
)
12899 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12900 narrow
= !in_pred_block ();
12902 narrow
= in_pred_block ();
12904 if (!inst
.operands
[1].isreg
)
12906 /* For an immediate, we always generate a 32-bit opcode;
12907 section relaxation will shrink it later if possible. */
12908 if (inst
.instruction
< 0xffff)
12909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12910 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12911 inst
.instruction
|= Rn
<< r0off
;
12912 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12916 /* See if we can do this with a 16-bit instruction. */
12919 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12920 inst
.instruction
|= Rn
;
12921 inst
.instruction
|= Rm
<< 3;
12925 constraint (inst
.operands
[1].shifted
12926 && inst
.operands
[1].immisreg
,
12927 _("shift must be constant"));
12928 if (inst
.instruction
< 0xffff)
12929 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12930 inst
.instruction
|= Rn
<< r0off
;
12931 encode_thumb32_shifted_operand (1);
12937 constraint (inst
.instruction
> 0xffff
12938 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12939 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12940 _("unshifted register required"));
12941 constraint (Rn
> 7 || Rm
> 7,
12944 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12945 inst
.instruction
|= Rn
;
12946 inst
.instruction
|= Rm
<< 3;
12955 if (do_vfp_nsyn_mrs () == SUCCESS
)
12958 Rd
= inst
.operands
[0].reg
;
12959 reject_bad_reg (Rd
);
12960 inst
.instruction
|= Rd
<< 8;
12962 if (inst
.operands
[1].isreg
)
12964 unsigned br
= inst
.operands
[1].reg
;
12965 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12966 as_bad (_("bad register for mrs"));
12968 inst
.instruction
|= br
& (0xf << 16);
12969 inst
.instruction
|= (br
& 0x300) >> 4;
12970 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12974 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12976 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12978 /* PR gas/12698: The constraint is only applied for m_profile.
12979 If the user has specified -march=all, we want to ignore it as
12980 we are building for any CPU type, including non-m variants. */
12981 bfd_boolean m_profile
=
12982 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12983 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12984 "not support requested special purpose register"));
12987 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12989 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12990 _("'APSR', 'CPSR' or 'SPSR' expected"));
12992 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12993 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12994 inst
.instruction
|= 0xf0000;
13004 if (do_vfp_nsyn_msr () == SUCCESS
)
13007 constraint (!inst
.operands
[1].isreg
,
13008 _("Thumb encoding does not support an immediate here"));
13010 if (inst
.operands
[0].isreg
)
13011 flags
= (int)(inst
.operands
[0].reg
);
13013 flags
= inst
.operands
[0].imm
;
13015 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13017 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13019 /* PR gas/12698: The constraint is only applied for m_profile.
13020 If the user has specified -march=all, we want to ignore it as
13021 we are building for any CPU type, including non-m variants. */
13022 bfd_boolean m_profile
=
13023 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13024 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13025 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13026 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13027 && bits
!= PSR_f
)) && m_profile
,
13028 _("selected processor does not support requested special "
13029 "purpose register"));
13032 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13033 "requested special purpose register"));
13035 Rn
= inst
.operands
[1].reg
;
13036 reject_bad_reg (Rn
);
13038 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13039 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13040 inst
.instruction
|= (flags
& 0x300) >> 4;
13041 inst
.instruction
|= (flags
& 0xff);
13042 inst
.instruction
|= Rn
<< 16;
13048 bfd_boolean narrow
;
13049 unsigned Rd
, Rn
, Rm
;
13051 if (!inst
.operands
[2].present
)
13052 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13054 Rd
= inst
.operands
[0].reg
;
13055 Rn
= inst
.operands
[1].reg
;
13056 Rm
= inst
.operands
[2].reg
;
13058 if (unified_syntax
)
13060 if (inst
.size_req
== 4
13066 else if (inst
.instruction
== T_MNEM_muls
)
13067 narrow
= !in_pred_block ();
13069 narrow
= in_pred_block ();
13073 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13074 constraint (Rn
> 7 || Rm
> 7,
13081 /* 16-bit MULS/Conditional MUL. */
13082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13083 inst
.instruction
|= Rd
;
13086 inst
.instruction
|= Rm
<< 3;
13088 inst
.instruction
|= Rn
<< 3;
13090 constraint (1, _("dest must overlap one source register"));
13094 constraint (inst
.instruction
!= T_MNEM_mul
,
13095 _("Thumb-2 MUL must not set flags"));
13097 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13098 inst
.instruction
|= Rd
<< 8;
13099 inst
.instruction
|= Rn
<< 16;
13100 inst
.instruction
|= Rm
<< 0;
13102 reject_bad_reg (Rd
);
13103 reject_bad_reg (Rn
);
13104 reject_bad_reg (Rm
);
13111 unsigned RdLo
, RdHi
, Rn
, Rm
;
13113 RdLo
= inst
.operands
[0].reg
;
13114 RdHi
= inst
.operands
[1].reg
;
13115 Rn
= inst
.operands
[2].reg
;
13116 Rm
= inst
.operands
[3].reg
;
13118 reject_bad_reg (RdLo
);
13119 reject_bad_reg (RdHi
);
13120 reject_bad_reg (Rn
);
13121 reject_bad_reg (Rm
);
13123 inst
.instruction
|= RdLo
<< 12;
13124 inst
.instruction
|= RdHi
<< 8;
13125 inst
.instruction
|= Rn
<< 16;
13126 inst
.instruction
|= Rm
;
13129 as_tsktsk (_("rdhi and rdlo must be different"));
13135 set_pred_insn_type (NEUTRAL_IT_INSN
);
13137 if (unified_syntax
)
13139 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13141 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13142 inst
.instruction
|= inst
.operands
[0].imm
;
13146 /* PR9722: Check for Thumb2 availability before
13147 generating a thumb2 nop instruction. */
13148 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13151 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13154 inst
.instruction
= 0x46c0;
13159 constraint (inst
.operands
[0].present
,
13160 _("Thumb does not support NOP with hints"));
13161 inst
.instruction
= 0x46c0;
13168 if (unified_syntax
)
13170 bfd_boolean narrow
;
13172 if (THUMB_SETS_FLAGS (inst
.instruction
))
13173 narrow
= !in_pred_block ();
13175 narrow
= in_pred_block ();
13176 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13178 if (inst
.size_req
== 4)
13183 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13189 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13190 inst
.instruction
|= inst
.operands
[0].reg
;
13191 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13196 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13198 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13201 inst
.instruction
|= inst
.operands
[0].reg
;
13202 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13211 Rd
= inst
.operands
[0].reg
;
13212 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13214 reject_bad_reg (Rd
);
13215 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13216 reject_bad_reg (Rn
);
13218 inst
.instruction
|= Rd
<< 8;
13219 inst
.instruction
|= Rn
<< 16;
13221 if (!inst
.operands
[2].isreg
)
13223 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13224 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13230 Rm
= inst
.operands
[2].reg
;
13231 reject_bad_reg (Rm
);
13233 constraint (inst
.operands
[2].shifted
13234 && inst
.operands
[2].immisreg
,
13235 _("shift must be constant"));
13236 encode_thumb32_shifted_operand (2);
13243 unsigned Rd
, Rn
, Rm
;
13245 Rd
= inst
.operands
[0].reg
;
13246 Rn
= inst
.operands
[1].reg
;
13247 Rm
= inst
.operands
[2].reg
;
13249 reject_bad_reg (Rd
);
13250 reject_bad_reg (Rn
);
13251 reject_bad_reg (Rm
);
13253 inst
.instruction
|= Rd
<< 8;
13254 inst
.instruction
|= Rn
<< 16;
13255 inst
.instruction
|= Rm
;
13256 if (inst
.operands
[3].present
)
13258 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13259 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13260 _("expression too complex"));
13261 inst
.instruction
|= (val
& 0x1c) << 10;
13262 inst
.instruction
|= (val
& 0x03) << 6;
13269 if (!inst
.operands
[3].present
)
13273 inst
.instruction
&= ~0x00000020;
13275 /* PR 10168. Swap the Rm and Rn registers. */
13276 Rtmp
= inst
.operands
[1].reg
;
13277 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13278 inst
.operands
[2].reg
= Rtmp
;
13286 if (inst
.operands
[0].immisreg
)
13287 reject_bad_reg (inst
.operands
[0].imm
);
13289 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13293 do_t_push_pop (void)
13297 constraint (inst
.operands
[0].writeback
,
13298 _("push/pop do not support {reglist}^"));
13299 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13300 _("expression too complex"));
13302 mask
= inst
.operands
[0].imm
;
13303 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13304 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13305 else if (inst
.size_req
!= 4
13306 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13307 ? REG_LR
: REG_PC
)))
13309 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13310 inst
.instruction
|= THUMB_PP_PC_LR
;
13311 inst
.instruction
|= mask
& 0xff;
13313 else if (unified_syntax
)
13315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13316 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13320 inst
.error
= _("invalid register list to push/pop instruction");
13328 if (unified_syntax
)
13329 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13332 inst
.error
= _("invalid register list to push/pop instruction");
13338 do_t_vscclrm (void)
13340 if (inst
.operands
[0].issingle
)
13342 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13343 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13344 inst
.instruction
|= inst
.operands
[0].imm
;
13348 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13349 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13350 inst
.instruction
|= 1 << 8;
13351 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13360 Rd
= inst
.operands
[0].reg
;
13361 Rm
= inst
.operands
[1].reg
;
13363 reject_bad_reg (Rd
);
13364 reject_bad_reg (Rm
);
13366 inst
.instruction
|= Rd
<< 8;
13367 inst
.instruction
|= Rm
<< 16;
13368 inst
.instruction
|= Rm
;
13376 Rd
= inst
.operands
[0].reg
;
13377 Rm
= inst
.operands
[1].reg
;
13379 reject_bad_reg (Rd
);
13380 reject_bad_reg (Rm
);
13382 if (Rd
<= 7 && Rm
<= 7
13383 && inst
.size_req
!= 4)
13385 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13386 inst
.instruction
|= Rd
;
13387 inst
.instruction
|= Rm
<< 3;
13389 else if (unified_syntax
)
13391 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13392 inst
.instruction
|= Rd
<< 8;
13393 inst
.instruction
|= Rm
<< 16;
13394 inst
.instruction
|= Rm
;
13397 inst
.error
= BAD_HIREG
;
13405 Rd
= inst
.operands
[0].reg
;
13406 Rm
= inst
.operands
[1].reg
;
13408 reject_bad_reg (Rd
);
13409 reject_bad_reg (Rm
);
13411 inst
.instruction
|= Rd
<< 8;
13412 inst
.instruction
|= Rm
;
13420 Rd
= inst
.operands
[0].reg
;
13421 Rs
= (inst
.operands
[1].present
13422 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13423 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13425 reject_bad_reg (Rd
);
13426 reject_bad_reg (Rs
);
13427 if (inst
.operands
[2].isreg
)
13428 reject_bad_reg (inst
.operands
[2].reg
);
13430 inst
.instruction
|= Rd
<< 8;
13431 inst
.instruction
|= Rs
<< 16;
13432 if (!inst
.operands
[2].isreg
)
13434 bfd_boolean narrow
;
13436 if ((inst
.instruction
& 0x00100000) != 0)
13437 narrow
= !in_pred_block ();
13439 narrow
= in_pred_block ();
13441 if (Rd
> 7 || Rs
> 7)
13444 if (inst
.size_req
== 4 || !unified_syntax
)
13447 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13448 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13451 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13452 relaxation, but it doesn't seem worth the hassle. */
13455 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13456 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13457 inst
.instruction
|= Rs
<< 3;
13458 inst
.instruction
|= Rd
;
13462 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13463 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13467 encode_thumb32_shifted_operand (2);
13473 if (warn_on_deprecated
13474 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13475 as_tsktsk (_("setend use is deprecated for ARMv8"));
13477 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13478 if (inst
.operands
[0].imm
)
13479 inst
.instruction
|= 0x8;
13485 if (!inst
.operands
[1].present
)
13486 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13488 if (unified_syntax
)
13490 bfd_boolean narrow
;
13493 switch (inst
.instruction
)
13496 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13498 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13500 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13502 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13506 if (THUMB_SETS_FLAGS (inst
.instruction
))
13507 narrow
= !in_pred_block ();
13509 narrow
= in_pred_block ();
13510 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13512 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13514 if (inst
.operands
[2].isreg
13515 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13516 || inst
.operands
[2].reg
> 7))
13518 if (inst
.size_req
== 4)
13521 reject_bad_reg (inst
.operands
[0].reg
);
13522 reject_bad_reg (inst
.operands
[1].reg
);
13526 if (inst
.operands
[2].isreg
)
13528 reject_bad_reg (inst
.operands
[2].reg
);
13529 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13530 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13532 inst
.instruction
|= inst
.operands
[2].reg
;
13534 /* PR 12854: Error on extraneous shifts. */
13535 constraint (inst
.operands
[2].shifted
,
13536 _("extraneous shift as part of operand to shift insn"));
13540 inst
.operands
[1].shifted
= 1;
13541 inst
.operands
[1].shift_kind
= shift_kind
;
13542 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13543 ? T_MNEM_movs
: T_MNEM_mov
);
13544 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13545 encode_thumb32_shifted_operand (1);
13546 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13547 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13552 if (inst
.operands
[2].isreg
)
13554 switch (shift_kind
)
13556 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13557 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13558 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13559 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13563 inst
.instruction
|= inst
.operands
[0].reg
;
13564 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13566 /* PR 12854: Error on extraneous shifts. */
13567 constraint (inst
.operands
[2].shifted
,
13568 _("extraneous shift as part of operand to shift insn"));
13572 switch (shift_kind
)
13574 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13575 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13576 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13579 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13580 inst
.instruction
|= inst
.operands
[0].reg
;
13581 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13587 constraint (inst
.operands
[0].reg
> 7
13588 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13589 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13591 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13593 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13594 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13595 _("source1 and dest must be same register"));
13597 switch (inst
.instruction
)
13599 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13600 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13601 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13602 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13606 inst
.instruction
|= inst
.operands
[0].reg
;
13607 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13609 /* PR 12854: Error on extraneous shifts. */
13610 constraint (inst
.operands
[2].shifted
,
13611 _("extraneous shift as part of operand to shift insn"));
13615 switch (inst
.instruction
)
13617 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13618 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13619 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13620 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13623 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13624 inst
.instruction
|= inst
.operands
[0].reg
;
13625 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13633 unsigned Rd
, Rn
, Rm
;
13635 Rd
= inst
.operands
[0].reg
;
13636 Rn
= inst
.operands
[1].reg
;
13637 Rm
= inst
.operands
[2].reg
;
13639 reject_bad_reg (Rd
);
13640 reject_bad_reg (Rn
);
13641 reject_bad_reg (Rm
);
13643 inst
.instruction
|= Rd
<< 8;
13644 inst
.instruction
|= Rn
<< 16;
13645 inst
.instruction
|= Rm
;
13651 unsigned Rd
, Rn
, Rm
;
13653 Rd
= inst
.operands
[0].reg
;
13654 Rm
= inst
.operands
[1].reg
;
13655 Rn
= inst
.operands
[2].reg
;
13657 reject_bad_reg (Rd
);
13658 reject_bad_reg (Rn
);
13659 reject_bad_reg (Rm
);
13661 inst
.instruction
|= Rd
<< 8;
13662 inst
.instruction
|= Rn
<< 16;
13663 inst
.instruction
|= Rm
;
13669 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13671 _("SMC is not permitted on this architecture"));
13672 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13673 _("expression too complex"));
13674 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13675 inst
.instruction
|= (value
& 0xf000) >> 12;
13676 inst
.instruction
|= (value
& 0x0ff0);
13677 inst
.instruction
|= (value
& 0x000f) << 16;
13678 /* PR gas/15623: SMC instructions must be last in an IT block. */
13679 set_pred_insn_type_last ();
13685 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13687 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13688 inst
.instruction
|= (value
& 0x0fff);
13689 inst
.instruction
|= (value
& 0xf000) << 4;
13693 do_t_ssat_usat (int bias
)
13697 Rd
= inst
.operands
[0].reg
;
13698 Rn
= inst
.operands
[2].reg
;
13700 reject_bad_reg (Rd
);
13701 reject_bad_reg (Rn
);
13703 inst
.instruction
|= Rd
<< 8;
13704 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13705 inst
.instruction
|= Rn
<< 16;
13707 if (inst
.operands
[3].present
)
13709 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13711 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13713 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13714 _("expression too complex"));
13716 if (shift_amount
!= 0)
13718 constraint (shift_amount
> 31,
13719 _("shift expression is too large"));
13721 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13722 inst
.instruction
|= 0x00200000; /* sh bit. */
13724 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13725 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13733 do_t_ssat_usat (1);
13741 Rd
= inst
.operands
[0].reg
;
13742 Rn
= inst
.operands
[2].reg
;
13744 reject_bad_reg (Rd
);
13745 reject_bad_reg (Rn
);
13747 inst
.instruction
|= Rd
<< 8;
13748 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13749 inst
.instruction
|= Rn
<< 16;
13755 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13756 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13757 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13758 || inst
.operands
[2].negative
,
13761 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13763 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13764 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13765 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13766 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13772 if (!inst
.operands
[2].present
)
13773 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13775 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13776 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13777 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13780 inst
.instruction
|= inst
.operands
[0].reg
;
13781 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13782 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13783 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13789 unsigned Rd
, Rn
, Rm
;
13791 Rd
= inst
.operands
[0].reg
;
13792 Rn
= inst
.operands
[1].reg
;
13793 Rm
= inst
.operands
[2].reg
;
13795 reject_bad_reg (Rd
);
13796 reject_bad_reg (Rn
);
13797 reject_bad_reg (Rm
);
13799 inst
.instruction
|= Rd
<< 8;
13800 inst
.instruction
|= Rn
<< 16;
13801 inst
.instruction
|= Rm
;
13802 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13810 Rd
= inst
.operands
[0].reg
;
13811 Rm
= inst
.operands
[1].reg
;
13813 reject_bad_reg (Rd
);
13814 reject_bad_reg (Rm
);
13816 if (inst
.instruction
<= 0xffff
13817 && inst
.size_req
!= 4
13818 && Rd
<= 7 && Rm
<= 7
13819 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13822 inst
.instruction
|= Rd
;
13823 inst
.instruction
|= Rm
<< 3;
13825 else if (unified_syntax
)
13827 if (inst
.instruction
<= 0xffff)
13828 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13829 inst
.instruction
|= Rd
<< 8;
13830 inst
.instruction
|= Rm
;
13831 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13835 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13836 _("Thumb encoding does not support rotation"));
13837 constraint (1, BAD_HIREG
);
13844 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13853 half
= (inst
.instruction
& 0x10) != 0;
13854 set_pred_insn_type_last ();
13855 constraint (inst
.operands
[0].immisreg
,
13856 _("instruction requires register index"));
13858 Rn
= inst
.operands
[0].reg
;
13859 Rm
= inst
.operands
[0].imm
;
13861 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13862 constraint (Rn
== REG_SP
, BAD_SP
);
13863 reject_bad_reg (Rm
);
13865 constraint (!half
&& inst
.operands
[0].shifted
,
13866 _("instruction does not allow shifted index"));
13867 inst
.instruction
|= (Rn
<< 16) | Rm
;
13873 if (!inst
.operands
[0].present
)
13874 inst
.operands
[0].imm
= 0;
13876 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13878 constraint (inst
.size_req
== 2,
13879 _("immediate value out of range"));
13880 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13881 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13882 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13887 inst
.instruction
|= inst
.operands
[0].imm
;
13890 set_pred_insn_type (NEUTRAL_IT_INSN
);
13897 do_t_ssat_usat (0);
13905 Rd
= inst
.operands
[0].reg
;
13906 Rn
= inst
.operands
[2].reg
;
13908 reject_bad_reg (Rd
);
13909 reject_bad_reg (Rn
);
13911 inst
.instruction
|= Rd
<< 8;
13912 inst
.instruction
|= inst
.operands
[1].imm
;
13913 inst
.instruction
|= Rn
<< 16;
13916 /* Checking the range of the branch offset (VAL) with NBITS bits
13917 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13919 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13921 gas_assert (nbits
> 0 && nbits
<= 32);
13924 int cmp
= (1 << (nbits
- 1));
13925 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13930 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13936 /* For branches in Armv8.1-M Mainline. */
13938 do_t_branch_future (void)
13940 unsigned long insn
= inst
.instruction
;
13942 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13943 if (inst
.operands
[0].hasreloc
== 0)
13945 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13946 as_bad (BAD_BRANCH_OFF
);
13948 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13952 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13953 inst
.relocs
[0].pc_rel
= 1;
13959 if (inst
.operands
[1].hasreloc
== 0)
13961 int val
= inst
.operands
[1].imm
;
13962 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13963 as_bad (BAD_BRANCH_OFF
);
13965 int immA
= (val
& 0x0001f000) >> 12;
13966 int immB
= (val
& 0x00000ffc) >> 2;
13967 int immC
= (val
& 0x00000002) >> 1;
13968 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13972 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13973 inst
.relocs
[1].pc_rel
= 1;
13978 if (inst
.operands
[1].hasreloc
== 0)
13980 int val
= inst
.operands
[1].imm
;
13981 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13982 as_bad (BAD_BRANCH_OFF
);
13984 int immA
= (val
& 0x0007f000) >> 12;
13985 int immB
= (val
& 0x00000ffc) >> 2;
13986 int immC
= (val
& 0x00000002) >> 1;
13987 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13991 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13992 inst
.relocs
[1].pc_rel
= 1;
13996 case T_MNEM_bfcsel
:
13998 if (inst
.operands
[1].hasreloc
== 0)
14000 int val
= inst
.operands
[1].imm
;
14001 int immA
= (val
& 0x00001000) >> 12;
14002 int immB
= (val
& 0x00000ffc) >> 2;
14003 int immC
= (val
& 0x00000002) >> 1;
14004 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14008 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14009 inst
.relocs
[1].pc_rel
= 1;
14013 if (inst
.operands
[2].hasreloc
== 0)
14015 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14016 int val2
= inst
.operands
[2].imm
;
14017 int val0
= inst
.operands
[0].imm
& 0x1f;
14018 int diff
= val2
- val0
;
14020 inst
.instruction
|= 1 << 17; /* T bit. */
14021 else if (diff
!= 2)
14022 as_bad (_("out of range label-relative fixup value"));
14026 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14027 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14028 inst
.relocs
[2].pc_rel
= 1;
14032 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14033 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14038 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14045 /* Helper function for do_t_loloop to handle relocations. */
14047 v8_1_loop_reloc (int is_le
)
14049 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14051 int value
= inst
.relocs
[0].exp
.X_add_number
;
14052 value
= (is_le
) ? -value
: value
;
14054 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14055 as_bad (BAD_BRANCH_OFF
);
14059 immh
= (value
& 0x00000ffc) >> 2;
14060 imml
= (value
& 0x00000002) >> 1;
14062 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14066 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14067 inst
.relocs
[0].pc_rel
= 1;
14071 /* To handle the Scalar Low Overhead Loop instructions
14072 in Armv8.1-M Mainline. */
14076 unsigned long insn
= inst
.instruction
;
14078 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14085 if (!inst
.operands
[0].present
)
14086 inst
.instruction
|= 1 << 21;
14088 v8_1_loop_reloc (TRUE
);
14092 v8_1_loop_reloc (FALSE
);
14093 /* Fall through. */
14095 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14096 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14103 /* MVE instruction encoder helpers. */
14104 #define M_MNEM_vabav 0xee800f01
14105 #define M_MNEM_vmladav 0xeef00e00
14106 #define M_MNEM_vmladava 0xeef00e20
14107 #define M_MNEM_vmladavx 0xeef01e00
14108 #define M_MNEM_vmladavax 0xeef01e20
14109 #define M_MNEM_vmlsdav 0xeef00e01
14110 #define M_MNEM_vmlsdava 0xeef00e21
14111 #define M_MNEM_vmlsdavx 0xeef01e01
14112 #define M_MNEM_vmlsdavax 0xeef01e21
14113 #define M_MNEM_vmullt 0xee011e00
14114 #define M_MNEM_vmullb 0xee010e00
14115 #define M_MNEM_vst20 0xfc801e00
14116 #define M_MNEM_vst21 0xfc801e20
14117 #define M_MNEM_vst40 0xfc801e01
14118 #define M_MNEM_vst41 0xfc801e21
14119 #define M_MNEM_vst42 0xfc801e41
14120 #define M_MNEM_vst43 0xfc801e61
14121 #define M_MNEM_vld20 0xfc901e00
14122 #define M_MNEM_vld21 0xfc901e20
14123 #define M_MNEM_vld40 0xfc901e01
14124 #define M_MNEM_vld41 0xfc901e21
14125 #define M_MNEM_vld42 0xfc901e41
14126 #define M_MNEM_vld43 0xfc901e61
14127 #define M_MNEM_vstrb 0xec000e00
14128 #define M_MNEM_vstrh 0xec000e10
14129 #define M_MNEM_vstrw 0xec000e40
14130 #define M_MNEM_vstrd 0xec000e50
14131 #define M_MNEM_vldrb 0xec100e00
14132 #define M_MNEM_vldrh 0xec100e10
14133 #define M_MNEM_vldrw 0xec100e40
14134 #define M_MNEM_vldrd 0xec100e50
14135 #define M_MNEM_vmovlt 0xeea01f40
14136 #define M_MNEM_vmovlb 0xeea00f40
14137 #define M_MNEM_vmovnt 0xfe311e81
14138 #define M_MNEM_vmovnb 0xfe310e81
14139 #define M_MNEM_vadc 0xee300f00
14140 #define M_MNEM_vadci 0xee301f00
14141 #define M_MNEM_vbrsr 0xfe011e60
14142 #define M_MNEM_vaddlv 0xee890f00
14143 #define M_MNEM_vaddlva 0xee890f20
14144 #define M_MNEM_vaddv 0xeef10f00
14145 #define M_MNEM_vaddva 0xeef10f20
14147 /* Neon instruction encoder helpers. */
14149 /* Encodings for the different types for various Neon opcodes. */
14151 /* An "invalid" code for the following tables. */
14154 struct neon_tab_entry
14157 unsigned float_or_poly
;
14158 unsigned scalar_or_imm
;
14161 /* Map overloaded Neon opcodes to their respective encodings. */
14162 #define NEON_ENC_TAB \
14163 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14164 X(vabdl, 0x0800700, N_INV, N_INV), \
14165 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14166 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14167 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14168 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14169 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14170 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14171 X(vaddl, 0x0800000, N_INV, N_INV), \
14172 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14173 X(vsubl, 0x0800200, N_INV, N_INV), \
14174 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14175 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14176 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14177 /* Register variants of the following two instructions are encoded as
14178 vcge / vcgt with the operands reversed. */ \
14179 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14180 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14181 X(vfma, N_INV, 0x0000c10, N_INV), \
14182 X(vfms, N_INV, 0x0200c10, N_INV), \
14183 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14184 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14185 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14186 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14187 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14188 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14189 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14190 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14191 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14192 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14193 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14194 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14195 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14196 X(vshl, 0x0000400, N_INV, 0x0800510), \
14197 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14198 X(vand, 0x0000110, N_INV, 0x0800030), \
14199 X(vbic, 0x0100110, N_INV, 0x0800030), \
14200 X(veor, 0x1000110, N_INV, N_INV), \
14201 X(vorn, 0x0300110, N_INV, 0x0800010), \
14202 X(vorr, 0x0200110, N_INV, 0x0800010), \
14203 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14204 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14205 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14206 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14207 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14208 X(vst1, 0x0000000, 0x0800000, N_INV), \
14209 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14210 X(vst2, 0x0000100, 0x0800100, N_INV), \
14211 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14212 X(vst3, 0x0000200, 0x0800200, N_INV), \
14213 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14214 X(vst4, 0x0000300, 0x0800300, N_INV), \
14215 X(vmovn, 0x1b20200, N_INV, N_INV), \
14216 X(vtrn, 0x1b20080, N_INV, N_INV), \
14217 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14218 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14219 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14220 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14221 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14222 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14223 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14224 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14225 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14226 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14227 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14228 X(vseleq, 0xe000a00, N_INV, N_INV), \
14229 X(vselvs, 0xe100a00, N_INV, N_INV), \
14230 X(vselge, 0xe200a00, N_INV, N_INV), \
14231 X(vselgt, 0xe300a00, N_INV, N_INV), \
14232 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14233 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14234 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14235 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14236 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14237 X(aes, 0x3b00300, N_INV, N_INV), \
14238 X(sha3op, 0x2000c00, N_INV, N_INV), \
14239 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14240 X(sha2op, 0x3ba0380, N_INV, N_INV)
14244 #define X(OPC,I,F,S) N_MNEM_##OPC
14249 static const struct neon_tab_entry neon_enc_tab
[] =
14251 #define X(OPC,I,F,S) { (I), (F), (S) }
14256 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14257 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14258 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14259 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14260 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14261 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14262 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14263 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14264 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14265 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14266 #define NEON_ENC_SINGLE_(X) \
14267 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14268 #define NEON_ENC_DOUBLE_(X) \
14269 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14270 #define NEON_ENC_FPV8_(X) \
14271 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14273 #define NEON_ENCODE(type, inst) \
14276 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14277 inst.is_neon = 1; \
14281 #define check_neon_suffixes \
14284 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14286 as_bad (_("invalid neon suffix for non neon instruction")); \
14292 /* Define shapes for instruction operands. The following mnemonic characters
14293 are used in this table:
14295 F - VFP S<n> register
14296 D - Neon D<n> register
14297 Q - Neon Q<n> register
14301 L - D<n> register list
14303 This table is used to generate various data:
14304 - enumerations of the form NS_DDR to be used as arguments to
14306 - a table classifying shapes into single, double, quad, mixed.
14307 - a table used to drive neon_select_shape. */
14309 #define NEON_SHAPE_DEF \
14310 X(4, (R, R, S, S), QUAD), \
14311 X(4, (S, S, R, R), QUAD), \
14312 X(3, (I, Q, Q), QUAD), \
14313 X(3, (I, Q, R), QUAD), \
14314 X(3, (R, Q, Q), QUAD), \
14315 X(3, (D, D, D), DOUBLE), \
14316 X(3, (Q, Q, Q), QUAD), \
14317 X(3, (D, D, I), DOUBLE), \
14318 X(3, (Q, Q, I), QUAD), \
14319 X(3, (D, D, S), DOUBLE), \
14320 X(3, (Q, Q, S), QUAD), \
14321 X(3, (Q, Q, R), QUAD), \
14322 X(3, (R, R, Q), QUAD), \
14323 X(2, (R, Q), QUAD), \
14324 X(2, (D, D), DOUBLE), \
14325 X(2, (Q, Q), QUAD), \
14326 X(2, (D, S), DOUBLE), \
14327 X(2, (Q, S), QUAD), \
14328 X(2, (D, R), DOUBLE), \
14329 X(2, (Q, R), QUAD), \
14330 X(2, (D, I), DOUBLE), \
14331 X(2, (Q, I), QUAD), \
14332 X(3, (D, L, D), DOUBLE), \
14333 X(2, (D, Q), MIXED), \
14334 X(2, (Q, D), MIXED), \
14335 X(3, (D, Q, I), MIXED), \
14336 X(3, (Q, D, I), MIXED), \
14337 X(3, (Q, D, D), MIXED), \
14338 X(3, (D, Q, Q), MIXED), \
14339 X(3, (Q, Q, D), MIXED), \
14340 X(3, (Q, D, S), MIXED), \
14341 X(3, (D, Q, S), MIXED), \
14342 X(4, (D, D, D, I), DOUBLE), \
14343 X(4, (Q, Q, Q, I), QUAD), \
14344 X(4, (D, D, S, I), DOUBLE), \
14345 X(4, (Q, Q, S, I), QUAD), \
14346 X(2, (F, F), SINGLE), \
14347 X(3, (F, F, F), SINGLE), \
14348 X(2, (F, I), SINGLE), \
14349 X(2, (F, D), MIXED), \
14350 X(2, (D, F), MIXED), \
14351 X(3, (F, F, I), MIXED), \
14352 X(4, (R, R, F, F), SINGLE), \
14353 X(4, (F, F, R, R), SINGLE), \
14354 X(3, (D, R, R), DOUBLE), \
14355 X(3, (R, R, D), DOUBLE), \
14356 X(2, (S, R), SINGLE), \
14357 X(2, (R, S), SINGLE), \
14358 X(2, (F, R), SINGLE), \
14359 X(2, (R, F), SINGLE), \
14360 /* Half float shape supported so far. */\
14361 X (2, (H, D), MIXED), \
14362 X (2, (D, H), MIXED), \
14363 X (2, (H, F), MIXED), \
14364 X (2, (F, H), MIXED), \
14365 X (2, (H, H), HALF), \
14366 X (2, (H, R), HALF), \
14367 X (2, (R, H), HALF), \
14368 X (2, (H, I), HALF), \
14369 X (3, (H, H, H), HALF), \
14370 X (3, (H, F, I), MIXED), \
14371 X (3, (F, H, I), MIXED), \
14372 X (3, (D, H, H), MIXED), \
14373 X (3, (D, H, S), MIXED)
14375 #define S2(A,B) NS_##A##B
14376 #define S3(A,B,C) NS_##A##B##C
14377 #define S4(A,B,C,D) NS_##A##B##C##D
14379 #define X(N, L, C) S##N L
14392 enum neon_shape_class
14401 #define X(N, L, C) SC_##C
14403 static enum neon_shape_class neon_shape_class
[] =
14422 /* Register widths of above. */
14423 static unsigned neon_shape_el_size
[] =
14435 struct neon_shape_info
14438 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14441 #define S2(A,B) { SE_##A, SE_##B }
14442 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14443 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14445 #define X(N, L, C) { N, S##N L }
14447 static struct neon_shape_info neon_shape_tab
[] =
14457 /* Bit masks used in type checking given instructions.
14458 'N_EQK' means the type must be the same as (or based on in some way) the key
14459 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14460 set, various other bits can be set as well in order to modify the meaning of
14461 the type constraint. */
14463 enum neon_type_mask
14487 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14488 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14489 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14490 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14491 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14492 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14493 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14494 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14495 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14496 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14497 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14499 N_MAX_NONSPECIAL
= N_P64
14502 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14504 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14505 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14506 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14507 #define N_S_32 (N_S8 | N_S16 | N_S32)
14508 #define N_F_16_32 (N_F16 | N_F32)
14509 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14510 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14511 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14512 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14513 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14514 #define N_F_MVE (N_F16 | N_F32)
14515 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14517 /* Pass this as the first type argument to neon_check_type to ignore types
14519 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14521 /* Select a "shape" for the current instruction (describing register types or
14522 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14523 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14524 function of operand parsing, so this function doesn't need to be called.
14525 Shapes should be listed in order of decreasing length. */
14527 static enum neon_shape
14528 neon_select_shape (enum neon_shape shape
, ...)
14531 enum neon_shape first_shape
= shape
;
14533 /* Fix missing optional operands. FIXME: we don't know at this point how
14534 many arguments we should have, so this makes the assumption that we have
14535 > 1. This is true of all current Neon opcodes, I think, but may not be
14536 true in the future. */
14537 if (!inst
.operands
[1].present
)
14538 inst
.operands
[1] = inst
.operands
[0];
14540 va_start (ap
, shape
);
14542 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14547 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14549 if (!inst
.operands
[j
].present
)
14555 switch (neon_shape_tab
[shape
].el
[j
])
14557 /* If a .f16, .16, .u16, .s16 type specifier is given over
14558 a VFP single precision register operand, it's essentially
14559 means only half of the register is used.
14561 If the type specifier is given after the mnemonics, the
14562 information is stored in inst.vectype. If the type specifier
14563 is given after register operand, the information is stored
14564 in inst.operands[].vectype.
14566 When there is only one type specifier, and all the register
14567 operands are the same type of hardware register, the type
14568 specifier applies to all register operands.
14570 If no type specifier is given, the shape is inferred from
14571 operand information.
14574 vadd.f16 s0, s1, s2: NS_HHH
14575 vabs.f16 s0, s1: NS_HH
14576 vmov.f16 s0, r1: NS_HR
14577 vmov.f16 r0, s1: NS_RH
14578 vcvt.f16 r0, s1: NS_RH
14579 vcvt.f16.s32 s2, s2, #29: NS_HFI
14580 vcvt.f16.s32 s2, s2: NS_HF
14583 if (!(inst
.operands
[j
].isreg
14584 && inst
.operands
[j
].isvec
14585 && inst
.operands
[j
].issingle
14586 && !inst
.operands
[j
].isquad
14587 && ((inst
.vectype
.elems
== 1
14588 && inst
.vectype
.el
[0].size
== 16)
14589 || (inst
.vectype
.elems
> 1
14590 && inst
.vectype
.el
[j
].size
== 16)
14591 || (inst
.vectype
.elems
== 0
14592 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14593 && inst
.operands
[j
].vectype
.size
== 16))))
14598 if (!(inst
.operands
[j
].isreg
14599 && inst
.operands
[j
].isvec
14600 && inst
.operands
[j
].issingle
14601 && !inst
.operands
[j
].isquad
14602 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14603 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14604 || (inst
.vectype
.elems
== 0
14605 && (inst
.operands
[j
].vectype
.size
== 32
14606 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14611 if (!(inst
.operands
[j
].isreg
14612 && inst
.operands
[j
].isvec
14613 && !inst
.operands
[j
].isquad
14614 && !inst
.operands
[j
].issingle
))
14619 if (!(inst
.operands
[j
].isreg
14620 && !inst
.operands
[j
].isvec
))
14625 if (!(inst
.operands
[j
].isreg
14626 && inst
.operands
[j
].isvec
14627 && inst
.operands
[j
].isquad
14628 && !inst
.operands
[j
].issingle
))
14633 if (!(!inst
.operands
[j
].isreg
14634 && !inst
.operands
[j
].isscalar
))
14639 if (!(!inst
.operands
[j
].isreg
14640 && inst
.operands
[j
].isscalar
))
14650 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14651 /* We've matched all the entries in the shape table, and we don't
14652 have any left over operands which have not been matched. */
14658 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14659 first_error (_("invalid instruction shape"));
14664 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14665 means the Q bit should be set). */
14668 neon_quad (enum neon_shape shape
)
14670 return neon_shape_class
[shape
] == SC_QUAD
;
14674 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14677 /* Allow modification to be made to types which are constrained to be
14678 based on the key element, based on bits set alongside N_EQK. */
14679 if ((typebits
& N_EQK
) != 0)
14681 if ((typebits
& N_HLF
) != 0)
14683 else if ((typebits
& N_DBL
) != 0)
14685 if ((typebits
& N_SGN
) != 0)
14686 *g_type
= NT_signed
;
14687 else if ((typebits
& N_UNS
) != 0)
14688 *g_type
= NT_unsigned
;
14689 else if ((typebits
& N_INT
) != 0)
14690 *g_type
= NT_integer
;
14691 else if ((typebits
& N_FLT
) != 0)
14692 *g_type
= NT_float
;
14693 else if ((typebits
& N_SIZ
) != 0)
14694 *g_type
= NT_untyped
;
14698 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14699 operand type, i.e. the single type specified in a Neon instruction when it
14700 is the only one given. */
14702 static struct neon_type_el
14703 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14705 struct neon_type_el dest
= *key
;
14707 gas_assert ((thisarg
& N_EQK
) != 0);
14709 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14714 /* Convert Neon type and size into compact bitmask representation. */
14716 static enum neon_type_mask
14717 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14724 case 8: return N_8
;
14725 case 16: return N_16
;
14726 case 32: return N_32
;
14727 case 64: return N_64
;
14735 case 8: return N_I8
;
14736 case 16: return N_I16
;
14737 case 32: return N_I32
;
14738 case 64: return N_I64
;
14746 case 16: return N_F16
;
14747 case 32: return N_F32
;
14748 case 64: return N_F64
;
14756 case 8: return N_P8
;
14757 case 16: return N_P16
;
14758 case 64: return N_P64
;
14766 case 8: return N_S8
;
14767 case 16: return N_S16
;
14768 case 32: return N_S32
;
14769 case 64: return N_S64
;
14777 case 8: return N_U8
;
14778 case 16: return N_U16
;
14779 case 32: return N_U32
;
14780 case 64: return N_U64
;
14791 /* Convert compact Neon bitmask type representation to a type and size. Only
14792 handles the case where a single bit is set in the mask. */
14795 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14796 enum neon_type_mask mask
)
14798 if ((mask
& N_EQK
) != 0)
14801 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14803 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14805 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14807 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14812 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14814 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14815 *type
= NT_unsigned
;
14816 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14817 *type
= NT_integer
;
14818 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14819 *type
= NT_untyped
;
14820 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14822 else if ((mask
& (N_F_ALL
)) != 0)
14830 /* Modify a bitmask of allowed types. This is only needed for type
14834 modify_types_allowed (unsigned allowed
, unsigned mods
)
14837 enum neon_el_type type
;
14843 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14845 if (el_type_of_type_chk (&type
, &size
,
14846 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14848 neon_modify_type_size (mods
, &type
, &size
);
14849 destmask
|= type_chk_of_el_type (type
, size
);
14856 /* Check type and return type classification.
14857 The manual states (paraphrase): If one datatype is given, it indicates the
14859 - the second operand, if there is one
14860 - the operand, if there is no second operand
14861 - the result, if there are no operands.
14862 This isn't quite good enough though, so we use a concept of a "key" datatype
14863 which is set on a per-instruction basis, which is the one which matters when
14864 only one data type is written.
14865 Note: this function has side-effects (e.g. filling in missing operands). All
14866 Neon instructions should call it before performing bit encoding. */
14868 static struct neon_type_el
14869 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14872 unsigned i
, pass
, key_el
= 0;
14873 unsigned types
[NEON_MAX_TYPE_ELS
];
14874 enum neon_el_type k_type
= NT_invtype
;
14875 unsigned k_size
= -1u;
14876 struct neon_type_el badtype
= {NT_invtype
, -1};
14877 unsigned key_allowed
= 0;
14879 /* Optional registers in Neon instructions are always (not) in operand 1.
14880 Fill in the missing operand here, if it was omitted. */
14881 if (els
> 1 && !inst
.operands
[1].present
)
14882 inst
.operands
[1] = inst
.operands
[0];
14884 /* Suck up all the varargs. */
14886 for (i
= 0; i
< els
; i
++)
14888 unsigned thisarg
= va_arg (ap
, unsigned);
14889 if (thisarg
== N_IGNORE_TYPE
)
14894 types
[i
] = thisarg
;
14895 if ((thisarg
& N_KEY
) != 0)
14900 if (inst
.vectype
.elems
> 0)
14901 for (i
= 0; i
< els
; i
++)
14902 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14904 first_error (_("types specified in both the mnemonic and operands"));
14908 /* Duplicate inst.vectype elements here as necessary.
14909 FIXME: No idea if this is exactly the same as the ARM assembler,
14910 particularly when an insn takes one register and one non-register
14912 if (inst
.vectype
.elems
== 1 && els
> 1)
14915 inst
.vectype
.elems
= els
;
14916 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14917 for (j
= 0; j
< els
; j
++)
14919 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14922 else if (inst
.vectype
.elems
== 0 && els
> 0)
14925 /* No types were given after the mnemonic, so look for types specified
14926 after each operand. We allow some flexibility here; as long as the
14927 "key" operand has a type, we can infer the others. */
14928 for (j
= 0; j
< els
; j
++)
14929 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14930 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14932 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14934 for (j
= 0; j
< els
; j
++)
14935 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14936 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14941 first_error (_("operand types can't be inferred"));
14945 else if (inst
.vectype
.elems
!= els
)
14947 first_error (_("type specifier has the wrong number of parts"));
14951 for (pass
= 0; pass
< 2; pass
++)
14953 for (i
= 0; i
< els
; i
++)
14955 unsigned thisarg
= types
[i
];
14956 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14957 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14958 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14959 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14961 /* Decay more-specific signed & unsigned types to sign-insensitive
14962 integer types if sign-specific variants are unavailable. */
14963 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14964 && (types_allowed
& N_SU_ALL
) == 0)
14965 g_type
= NT_integer
;
14967 /* If only untyped args are allowed, decay any more specific types to
14968 them. Some instructions only care about signs for some element
14969 sizes, so handle that properly. */
14970 if (((types_allowed
& N_UNT
) == 0)
14971 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14972 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14973 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14974 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14975 g_type
= NT_untyped
;
14979 if ((thisarg
& N_KEY
) != 0)
14983 key_allowed
= thisarg
& ~N_KEY
;
14985 /* Check architecture constraint on FP16 extension. */
14987 && k_type
== NT_float
14988 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14990 inst
.error
= _(BAD_FP16
);
14997 if ((thisarg
& N_VFP
) != 0)
14999 enum neon_shape_el regshape
;
15000 unsigned regwidth
, match
;
15002 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15005 first_error (_("invalid instruction shape"));
15008 regshape
= neon_shape_tab
[ns
].el
[i
];
15009 regwidth
= neon_shape_el_size
[regshape
];
15011 /* In VFP mode, operands must match register widths. If we
15012 have a key operand, use its width, else use the width of
15013 the current operand. */
15019 /* FP16 will use a single precision register. */
15020 if (regwidth
== 32 && match
== 16)
15022 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15026 inst
.error
= _(BAD_FP16
);
15031 if (regwidth
!= match
)
15033 first_error (_("operand size must match register width"));
15038 if ((thisarg
& N_EQK
) == 0)
15040 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15042 if ((given_type
& types_allowed
) == 0)
15044 first_error (BAD_SIMD_TYPE
);
15050 enum neon_el_type mod_k_type
= k_type
;
15051 unsigned mod_k_size
= k_size
;
15052 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15053 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15055 first_error (_("inconsistent types in Neon instruction"));
15063 return inst
.vectype
.el
[key_el
];
15066 /* Neon-style VFP instruction forwarding. */
15068 /* Thumb VFP instructions have 0xE in the condition field. */
15071 do_vfp_cond_or_thumb (void)
15076 inst
.instruction
|= 0xe0000000;
15078 inst
.instruction
|= inst
.cond
<< 28;
15081 /* Look up and encode a simple mnemonic, for use as a helper function for the
15082 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15083 etc. It is assumed that operand parsing has already been done, and that the
15084 operands are in the form expected by the given opcode (this isn't necessarily
15085 the same as the form in which they were parsed, hence some massaging must
15086 take place before this function is called).
15087 Checks current arch version against that in the looked-up opcode. */
15090 do_vfp_nsyn_opcode (const char *opname
)
15092 const struct asm_opcode
*opcode
;
15094 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15100 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15107 inst
.instruction
= opcode
->tvalue
;
15108 opcode
->tencode ();
15112 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15113 opcode
->aencode ();
15118 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15120 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15122 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15125 do_vfp_nsyn_opcode ("fadds");
15127 do_vfp_nsyn_opcode ("fsubs");
15129 /* ARMv8.2 fp16 instruction. */
15131 do_scalar_fp16_v82_encode ();
15136 do_vfp_nsyn_opcode ("faddd");
15138 do_vfp_nsyn_opcode ("fsubd");
15142 /* Check operand types to see if this is a VFP instruction, and if so call
15146 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15148 enum neon_shape rs
;
15149 struct neon_type_el et
;
15154 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15155 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15159 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15160 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15161 N_F_ALL
| N_KEY
| N_VFP
);
15168 if (et
.type
!= NT_invtype
)
15179 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15181 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15183 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15186 do_vfp_nsyn_opcode ("fmacs");
15188 do_vfp_nsyn_opcode ("fnmacs");
15190 /* ARMv8.2 fp16 instruction. */
15192 do_scalar_fp16_v82_encode ();
15197 do_vfp_nsyn_opcode ("fmacd");
15199 do_vfp_nsyn_opcode ("fnmacd");
15204 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15206 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15208 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15211 do_vfp_nsyn_opcode ("ffmas");
15213 do_vfp_nsyn_opcode ("ffnmas");
15215 /* ARMv8.2 fp16 instruction. */
15217 do_scalar_fp16_v82_encode ();
15222 do_vfp_nsyn_opcode ("ffmad");
15224 do_vfp_nsyn_opcode ("ffnmad");
15229 do_vfp_nsyn_mul (enum neon_shape rs
)
15231 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15233 do_vfp_nsyn_opcode ("fmuls");
15235 /* ARMv8.2 fp16 instruction. */
15237 do_scalar_fp16_v82_encode ();
15240 do_vfp_nsyn_opcode ("fmuld");
15244 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15246 int is_neg
= (inst
.instruction
& 0x80) != 0;
15247 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15249 if (rs
== NS_FF
|| rs
== NS_HH
)
15252 do_vfp_nsyn_opcode ("fnegs");
15254 do_vfp_nsyn_opcode ("fabss");
15256 /* ARMv8.2 fp16 instruction. */
15258 do_scalar_fp16_v82_encode ();
15263 do_vfp_nsyn_opcode ("fnegd");
15265 do_vfp_nsyn_opcode ("fabsd");
15269 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15270 insns belong to Neon, and are handled elsewhere. */
15273 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15275 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15279 do_vfp_nsyn_opcode ("fldmdbs");
15281 do_vfp_nsyn_opcode ("fldmias");
15286 do_vfp_nsyn_opcode ("fstmdbs");
15288 do_vfp_nsyn_opcode ("fstmias");
15293 do_vfp_nsyn_sqrt (void)
15295 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15296 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15298 if (rs
== NS_FF
|| rs
== NS_HH
)
15300 do_vfp_nsyn_opcode ("fsqrts");
15302 /* ARMv8.2 fp16 instruction. */
15304 do_scalar_fp16_v82_encode ();
15307 do_vfp_nsyn_opcode ("fsqrtd");
15311 do_vfp_nsyn_div (void)
15313 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15314 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15315 N_F_ALL
| N_KEY
| N_VFP
);
15317 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15319 do_vfp_nsyn_opcode ("fdivs");
15321 /* ARMv8.2 fp16 instruction. */
15323 do_scalar_fp16_v82_encode ();
15326 do_vfp_nsyn_opcode ("fdivd");
15330 do_vfp_nsyn_nmul (void)
15332 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15333 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15334 N_F_ALL
| N_KEY
| N_VFP
);
15336 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15338 NEON_ENCODE (SINGLE
, inst
);
15339 do_vfp_sp_dyadic ();
15341 /* ARMv8.2 fp16 instruction. */
15343 do_scalar_fp16_v82_encode ();
15347 NEON_ENCODE (DOUBLE
, inst
);
15348 do_vfp_dp_rd_rn_rm ();
15350 do_vfp_cond_or_thumb ();
15354 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15358 neon_logbits (unsigned x
)
15360 return ffs (x
) - 4;
15363 #define LOW4(R) ((R) & 0xf)
15364 #define HI1(R) (((R) >> 4) & 1)
15367 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15372 first_error (BAD_EL_TYPE
);
15375 switch (inst
.operands
[0].imm
)
15378 first_error (_("invalid condition"));
15400 /* only accept eq and ne. */
15401 if (inst
.operands
[0].imm
> 1)
15403 first_error (_("invalid condition"));
15406 return inst
.operands
[0].imm
;
15408 if (inst
.operands
[0].imm
== 0x2)
15410 else if (inst
.operands
[0].imm
== 0x8)
15414 first_error (_("invalid condition"));
15418 switch (inst
.operands
[0].imm
)
15421 first_error (_("invalid condition"));
15437 /* Should be unreachable. */
15444 /* We are dealing with a vector predicated block. */
15445 if (inst
.operands
[0].present
)
15447 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15448 struct neon_type_el et
15449 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15452 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15454 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15456 if (et
.type
== NT_invtype
)
15459 if (et
.type
== NT_float
)
15461 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15463 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15464 inst
.instruction
|= (et
.size
== 16) << 28;
15465 inst
.instruction
|= 0x3 << 20;
15469 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15471 inst
.instruction
|= 1 << 28;
15472 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15475 if (inst
.operands
[2].isquad
)
15477 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15478 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15479 inst
.instruction
|= (fcond
& 0x2) >> 1;
15483 if (inst
.operands
[2].reg
== REG_SP
)
15484 as_tsktsk (MVE_BAD_SP
);
15485 inst
.instruction
|= 1 << 6;
15486 inst
.instruction
|= (fcond
& 0x2) << 4;
15487 inst
.instruction
|= inst
.operands
[2].reg
;
15489 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15490 inst
.instruction
|= (fcond
& 0x4) << 10;
15491 inst
.instruction
|= (fcond
& 0x1) << 7;
15494 set_pred_insn_type (VPT_INSN
);
15496 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15497 | ((inst
.instruction
& 0xe000) >> 13);
15498 now_pred
.warn_deprecated
= FALSE
;
15499 now_pred
.type
= VECTOR_PRED
;
15506 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15507 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15508 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15509 if (!inst
.operands
[2].present
)
15510 first_error (_("MVE vector or ARM register expected"));
15511 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15513 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15514 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15515 && inst
.operands
[1].isquad
)
15517 inst
.instruction
= N_MNEM_vcmp
;
15521 if (inst
.cond
> COND_ALWAYS
)
15522 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15524 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15526 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15527 struct neon_type_el et
15528 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15531 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15532 && !inst
.operands
[2].iszr
, BAD_PC
);
15534 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15536 inst
.instruction
= 0xee010f00;
15537 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15538 inst
.instruction
|= (fcond
& 0x4) << 10;
15539 inst
.instruction
|= (fcond
& 0x1) << 7;
15540 if (et
.type
== NT_float
)
15542 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15544 inst
.instruction
|= (et
.size
== 16) << 28;
15545 inst
.instruction
|= 0x3 << 20;
15549 inst
.instruction
|= 1 << 28;
15550 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15552 if (inst
.operands
[2].isquad
)
15554 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15555 inst
.instruction
|= (fcond
& 0x2) >> 1;
15556 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15560 if (inst
.operands
[2].reg
== REG_SP
)
15561 as_tsktsk (MVE_BAD_SP
);
15562 inst
.instruction
|= 1 << 6;
15563 inst
.instruction
|= (fcond
& 0x2) << 4;
15564 inst
.instruction
|= inst
.operands
[2].reg
;
15572 do_vfp_nsyn_cmp (void)
15574 enum neon_shape rs
;
15575 if (!inst
.operands
[0].isreg
)
15582 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15583 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15587 if (inst
.operands
[1].isreg
)
15589 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15590 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15592 if (rs
== NS_FF
|| rs
== NS_HH
)
15594 NEON_ENCODE (SINGLE
, inst
);
15595 do_vfp_sp_monadic ();
15599 NEON_ENCODE (DOUBLE
, inst
);
15600 do_vfp_dp_rd_rm ();
15605 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15606 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15608 switch (inst
.instruction
& 0x0fffffff)
15611 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15614 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15620 if (rs
== NS_FI
|| rs
== NS_HI
)
15622 NEON_ENCODE (SINGLE
, inst
);
15623 do_vfp_sp_compare_z ();
15627 NEON_ENCODE (DOUBLE
, inst
);
15631 do_vfp_cond_or_thumb ();
15633 /* ARMv8.2 fp16 instruction. */
15634 if (rs
== NS_HI
|| rs
== NS_HH
)
15635 do_scalar_fp16_v82_encode ();
15639 nsyn_insert_sp (void)
15641 inst
.operands
[1] = inst
.operands
[0];
15642 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15643 inst
.operands
[0].reg
= REG_SP
;
15644 inst
.operands
[0].isreg
= 1;
15645 inst
.operands
[0].writeback
= 1;
15646 inst
.operands
[0].present
= 1;
15650 do_vfp_nsyn_push (void)
15654 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15655 _("register list must contain at least 1 and at most 16 "
15658 if (inst
.operands
[1].issingle
)
15659 do_vfp_nsyn_opcode ("fstmdbs");
15661 do_vfp_nsyn_opcode ("fstmdbd");
15665 do_vfp_nsyn_pop (void)
15669 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15670 _("register list must contain at least 1 and at most 16 "
15673 if (inst
.operands
[1].issingle
)
15674 do_vfp_nsyn_opcode ("fldmias");
15676 do_vfp_nsyn_opcode ("fldmiad");
15679 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15680 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15683 neon_dp_fixup (struct arm_it
* insn
)
15685 unsigned int i
= insn
->instruction
;
15690 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15701 insn
->instruction
= i
;
15705 mve_encode_qqr (int size
, int fp
)
15707 if (inst
.operands
[2].reg
== REG_SP
)
15708 as_tsktsk (MVE_BAD_SP
);
15709 else if (inst
.operands
[2].reg
== REG_PC
)
15710 as_tsktsk (MVE_BAD_PC
);
15715 if (((unsigned)inst
.instruction
) == 0xd00)
15716 inst
.instruction
= 0xee300f40;
15718 else if (((unsigned)inst
.instruction
) == 0x200d00)
15719 inst
.instruction
= 0xee301f40;
15721 /* Setting size which is 1 for F16 and 0 for F32. */
15722 inst
.instruction
|= (size
== 16) << 28;
15727 if (((unsigned)inst
.instruction
) == 0x800)
15728 inst
.instruction
= 0xee010f40;
15730 else if (((unsigned)inst
.instruction
) == 0x1000800)
15731 inst
.instruction
= 0xee011f40;
15732 /* Setting bits for size. */
15733 inst
.instruction
|= neon_logbits (size
) << 20;
15735 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15736 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15737 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15738 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15739 inst
.instruction
|= inst
.operands
[2].reg
;
15744 mve_encode_rqq (unsigned bit28
, unsigned size
)
15746 inst
.instruction
|= bit28
<< 28;
15747 inst
.instruction
|= neon_logbits (size
) << 20;
15748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15750 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15751 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15752 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15757 mve_encode_qqq (int ubit
, int size
)
15760 inst
.instruction
|= (ubit
!= 0) << 28;
15761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15762 inst
.instruction
|= neon_logbits (size
) << 20;
15763 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15764 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15765 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15766 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15767 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15773 mve_encode_rq (unsigned bit28
, unsigned size
)
15775 inst
.instruction
|= bit28
<< 28;
15776 inst
.instruction
|= neon_logbits (size
) << 18;
15777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15778 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15782 /* Encode insns with bit pattern:
15784 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15785 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15787 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15788 different meaning for some instruction. */
15791 neon_three_same (int isquad
, int ubit
, int size
)
15793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15794 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15796 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15797 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15798 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15799 inst
.instruction
|= (isquad
!= 0) << 6;
15800 inst
.instruction
|= (ubit
!= 0) << 24;
15802 inst
.instruction
|= neon_logbits (size
) << 20;
15804 neon_dp_fixup (&inst
);
15807 /* Encode instructions of the form:
15809 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15810 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15812 Don't write size if SIZE == -1. */
15815 neon_two_same (int qbit
, int ubit
, int size
)
15817 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15818 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15819 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15820 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15821 inst
.instruction
|= (qbit
!= 0) << 6;
15822 inst
.instruction
|= (ubit
!= 0) << 24;
15825 inst
.instruction
|= neon_logbits (size
) << 18;
15827 neon_dp_fixup (&inst
);
15830 /* Neon instruction encoders, in approximate order of appearance. */
15833 do_neon_dyadic_i_su (void)
15835 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15836 struct neon_type_el et
= neon_check_type (3, rs
,
15837 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15838 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15842 do_neon_dyadic_i64_su (void)
15844 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15845 struct neon_type_el et
= neon_check_type (3, rs
,
15846 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15847 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15851 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15854 unsigned size
= et
.size
>> 3;
15855 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15856 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15857 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15858 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15859 inst
.instruction
|= (isquad
!= 0) << 6;
15860 inst
.instruction
|= immbits
<< 16;
15861 inst
.instruction
|= (size
>> 3) << 7;
15862 inst
.instruction
|= (size
& 0x7) << 19;
15864 inst
.instruction
|= (uval
!= 0) << 24;
15866 neon_dp_fixup (&inst
);
15870 do_neon_shl_imm (void)
15872 if (!inst
.operands
[2].isreg
)
15874 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15875 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15876 int imm
= inst
.operands
[2].imm
;
15878 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15879 _("immediate out of range for shift"));
15880 NEON_ENCODE (IMMED
, inst
);
15881 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15885 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15886 struct neon_type_el et
= neon_check_type (3, rs
,
15887 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15890 /* VSHL/VQSHL 3-register variants have syntax such as:
15892 whereas other 3-register operations encoded by neon_three_same have
15895 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15897 tmp
= inst
.operands
[2].reg
;
15898 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15899 inst
.operands
[1].reg
= tmp
;
15900 NEON_ENCODE (INTEGER
, inst
);
15901 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15906 do_neon_qshl_imm (void)
15908 if (!inst
.operands
[2].isreg
)
15910 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15911 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15912 int imm
= inst
.operands
[2].imm
;
15914 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15915 _("immediate out of range for shift"));
15916 NEON_ENCODE (IMMED
, inst
);
15917 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15921 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15922 struct neon_type_el et
= neon_check_type (3, rs
,
15923 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15926 /* See note in do_neon_shl_imm. */
15927 tmp
= inst
.operands
[2].reg
;
15928 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15929 inst
.operands
[1].reg
= tmp
;
15930 NEON_ENCODE (INTEGER
, inst
);
15931 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15936 do_neon_rshl (void)
15938 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15939 struct neon_type_el et
= neon_check_type (3, rs
,
15940 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15943 tmp
= inst
.operands
[2].reg
;
15944 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15945 inst
.operands
[1].reg
= tmp
;
15946 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15950 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15952 /* Handle .I8 pseudo-instructions. */
15955 /* Unfortunately, this will make everything apart from zero out-of-range.
15956 FIXME is this the intended semantics? There doesn't seem much point in
15957 accepting .I8 if so. */
15958 immediate
|= immediate
<< 8;
15964 if (immediate
== (immediate
& 0x000000ff))
15966 *immbits
= immediate
;
15969 else if (immediate
== (immediate
& 0x0000ff00))
15971 *immbits
= immediate
>> 8;
15974 else if (immediate
== (immediate
& 0x00ff0000))
15976 *immbits
= immediate
>> 16;
15979 else if (immediate
== (immediate
& 0xff000000))
15981 *immbits
= immediate
>> 24;
15984 if ((immediate
& 0xffff) != (immediate
>> 16))
15985 goto bad_immediate
;
15986 immediate
&= 0xffff;
15989 if (immediate
== (immediate
& 0x000000ff))
15991 *immbits
= immediate
;
15994 else if (immediate
== (immediate
& 0x0000ff00))
15996 *immbits
= immediate
>> 8;
16001 first_error (_("immediate value out of range"));
16006 do_neon_logic (void)
16008 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16010 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16011 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16012 /* U bit and size field were set as part of the bitmask. */
16013 NEON_ENCODE (INTEGER
, inst
);
16014 neon_three_same (neon_quad (rs
), 0, -1);
16018 const int three_ops_form
= (inst
.operands
[2].present
16019 && !inst
.operands
[2].isreg
);
16020 const int immoperand
= (three_ops_form
? 2 : 1);
16021 enum neon_shape rs
= (three_ops_form
16022 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16023 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16024 struct neon_type_el et
= neon_check_type (2, rs
,
16025 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16026 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16030 if (et
.type
== NT_invtype
)
16033 if (three_ops_form
)
16034 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16035 _("first and second operands shall be the same register"));
16037 NEON_ENCODE (IMMED
, inst
);
16039 immbits
= inst
.operands
[immoperand
].imm
;
16042 /* .i64 is a pseudo-op, so the immediate must be a repeating
16044 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16045 inst
.operands
[immoperand
].reg
: 0))
16047 /* Set immbits to an invalid constant. */
16048 immbits
= 0xdeadbeef;
16055 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16059 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16063 /* Pseudo-instruction for VBIC. */
16064 neon_invert_size (&immbits
, 0, et
.size
);
16065 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16069 /* Pseudo-instruction for VORR. */
16070 neon_invert_size (&immbits
, 0, et
.size
);
16071 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16081 inst
.instruction
|= neon_quad (rs
) << 6;
16082 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16083 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16084 inst
.instruction
|= cmode
<< 8;
16085 neon_write_immbits (immbits
);
16087 neon_dp_fixup (&inst
);
16092 do_neon_bitfield (void)
16094 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16095 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16096 neon_three_same (neon_quad (rs
), 0, -1);
16100 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16103 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16104 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16106 if (et
.type
== NT_float
)
16108 NEON_ENCODE (FLOAT
, inst
);
16110 mve_encode_qqr (et
.size
, 1);
16112 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16116 NEON_ENCODE (INTEGER
, inst
);
16118 mve_encode_qqr (et
.size
, 0);
16120 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16126 do_neon_dyadic_if_su_d (void)
16128 /* This version only allow D registers, but that constraint is enforced during
16129 operand parsing so we don't need to do anything extra here. */
16130 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16134 do_neon_dyadic_if_i_d (void)
16136 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16137 affected if we specify unsigned args. */
16138 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16141 enum vfp_or_neon_is_neon_bits
16144 NEON_CHECK_ARCH
= 2,
16145 NEON_CHECK_ARCH8
= 4
16148 /* Call this function if an instruction which may have belonged to the VFP or
16149 Neon instruction sets, but turned out to be a Neon instruction (due to the
16150 operand types involved, etc.). We have to check and/or fix-up a couple of
16153 - Make sure the user hasn't attempted to make a Neon instruction
16155 - Alter the value in the condition code field if necessary.
16156 - Make sure that the arch supports Neon instructions.
16158 Which of these operations take place depends on bits from enum
16159 vfp_or_neon_is_neon_bits.
16161 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16162 current instruction's condition is COND_ALWAYS, the condition field is
16163 changed to inst.uncond_value. This is necessary because instructions shared
16164 between VFP and Neon may be conditional for the VFP variants only, and the
16165 unconditional Neon version must have, e.g., 0xF in the condition field. */
16168 vfp_or_neon_is_neon (unsigned check
)
16170 /* Conditions are always legal in Thumb mode (IT blocks). */
16171 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16173 if (inst
.cond
!= COND_ALWAYS
)
16175 first_error (_(BAD_COND
));
16178 if (inst
.uncond_value
!= -1)
16179 inst
.instruction
|= inst
.uncond_value
<< 28;
16183 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16184 || ((check
& NEON_CHECK_ARCH8
)
16185 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16187 first_error (_(BAD_FPU
));
16195 check_simd_pred_availability (int fp
, unsigned check
)
16197 if (inst
.cond
> COND_ALWAYS
)
16199 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16201 inst
.error
= BAD_FPU
;
16204 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16206 else if (inst
.cond
< COND_ALWAYS
)
16208 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16209 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16210 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16215 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16216 && vfp_or_neon_is_neon (check
) == FAIL
)
16219 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16220 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16226 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16228 constraint (size
< 32, BAD_ADDR_MODE
);
16229 constraint (size
!= elsize
, BAD_EL_TYPE
);
16230 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16231 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16232 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16233 _("destination register and offset register may not be the"
16236 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16243 constraint ((imm
% (size
/ 8) != 0)
16244 || imm
> (0x7f << neon_logbits (size
)),
16245 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16246 " range of +/-[0,508]")
16247 : _("immediate must be a multiple of 8 in the"
16248 " range of +/-[0,1016]"));
16249 inst
.instruction
|= 0x11 << 24;
16250 inst
.instruction
|= add
<< 23;
16251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16252 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16253 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16255 inst
.instruction
|= 1 << 12;
16256 inst
.instruction
|= (size
== 64) << 8;
16257 inst
.instruction
&= 0xffffff00;
16258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16259 inst
.instruction
|= imm
>> neon_logbits (size
);
16263 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16265 unsigned os
= inst
.operands
[1].imm
>> 5;
16266 constraint (os
!= 0 && size
== 8,
16267 _("can not shift offsets when accessing less than half-word"));
16268 constraint (os
&& os
!= neon_logbits (size
),
16269 _("shift immediate must be 1, 2 or 3 for half-word, word"
16270 " or double-word accesses respectively"));
16271 if (inst
.operands
[1].reg
== REG_PC
)
16272 as_tsktsk (MVE_BAD_PC
);
16277 constraint (elsize
>= 64, BAD_EL_TYPE
);
16280 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16284 constraint (elsize
!= size
, BAD_EL_TYPE
);
16289 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16293 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16294 _("destination register and offset register may not be"
16296 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16298 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16299 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16300 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16304 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16307 inst
.instruction
|= 1 << 23;
16308 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16309 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16310 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16311 inst
.instruction
|= neon_logbits (elsize
) << 7;
16312 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16313 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16314 inst
.instruction
|= !!os
;
16318 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16320 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16322 constraint (size
>= 64, BAD_ADDR_MODE
);
16326 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16329 constraint (elsize
!= size
, BAD_EL_TYPE
);
16336 constraint (elsize
!= size
&& type
!= NT_unsigned
16337 && type
!= NT_signed
, BAD_EL_TYPE
);
16341 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16344 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16352 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16357 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16360 constraint (1, _("immediate must be a multiple of 2 in the"
16361 " range of +/-[0,254]"));
16364 constraint (1, _("immediate must be a multiple of 4 in the"
16365 " range of +/-[0,508]"));
16370 if (size
!= elsize
)
16372 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16373 constraint (inst
.operands
[0].reg
> 14,
16374 _("MVE vector register in the range [Q0..Q7] expected"));
16375 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16376 inst
.instruction
|= (size
== 16) << 19;
16377 inst
.instruction
|= neon_logbits (elsize
) << 7;
16381 if (inst
.operands
[1].reg
== REG_PC
)
16382 as_tsktsk (MVE_BAD_PC
);
16383 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16384 as_tsktsk (MVE_BAD_SP
);
16385 inst
.instruction
|= 1 << 12;
16386 inst
.instruction
|= neon_logbits (size
) << 7;
16388 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16389 inst
.instruction
|= add
<< 23;
16390 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16391 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16392 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16394 inst
.instruction
&= 0xffffff80;
16395 inst
.instruction
|= imm
>> neon_logbits (size
);
16400 do_mve_vstr_vldr (void)
16405 if (inst
.cond
> COND_ALWAYS
)
16406 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16408 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16410 switch (inst
.instruction
)
16417 /* fall through. */
16423 /* fall through. */
16429 /* fall through. */
16435 /* fall through. */
16440 unsigned elsize
= inst
.vectype
.el
[0].size
;
16442 if (inst
.operands
[1].isquad
)
16444 /* We are dealing with [Q, imm]{!} cases. */
16445 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16449 if (inst
.operands
[1].immisreg
== 2)
16451 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16452 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16454 else if (!inst
.operands
[1].immisreg
)
16456 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16457 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16460 constraint (1, BAD_ADDR_MODE
);
16467 do_mve_vst_vld (void)
16469 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16472 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16473 || inst
.relocs
[0].exp
.X_add_number
!= 0
16474 || inst
.operands
[1].immisreg
!= 0,
16476 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16477 if (inst
.operands
[1].reg
== REG_PC
)
16478 as_tsktsk (MVE_BAD_PC
);
16479 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16480 as_tsktsk (MVE_BAD_SP
);
16483 /* These instructions are one of the "exceptions" mentioned in
16484 handle_pred_state. They are MVE instructions that are not VPT compatible
16485 and do not accept a VPT code, thus appending such a code is a syntax
16487 if (inst
.cond
> COND_ALWAYS
)
16488 first_error (BAD_SYNTAX
);
16489 /* If we append a scalar condition code we can set this to
16490 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16491 else if (inst
.cond
< COND_ALWAYS
)
16492 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16494 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16496 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16497 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16498 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16499 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16500 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16505 do_mve_vaddlv (void)
16507 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
16508 struct neon_type_el et
16509 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
16511 if (et
.type
== NT_invtype
)
16512 first_error (BAD_EL_TYPE
);
16514 if (inst
.cond
> COND_ALWAYS
)
16515 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16517 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16519 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16521 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16522 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
16523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16524 inst
.instruction
|= inst
.operands
[2].reg
;
16529 do_neon_dyadic_if_su (void)
16531 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16532 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16535 if (check_simd_pred_availability (et
.type
== NT_float
,
16536 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16539 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16543 do_neon_addsub_if_i (void)
16545 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16546 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16549 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16550 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16551 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16553 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16554 /* If we are parsing Q registers and the element types match MVE, which NEON
16555 also supports, then we must check whether this is an instruction that can
16556 be used by both MVE/NEON. This distinction can be made based on whether
16557 they are predicated or not. */
16558 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16560 if (check_simd_pred_availability (et
.type
== NT_float
,
16561 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16566 /* If they are either in a D register or are using an unsupported. */
16568 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16572 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16573 affected if we specify unsigned args. */
16574 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16577 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16579 V<op> A,B (A is operand 0, B is operand 2)
16584 so handle that case specially. */
16587 neon_exchange_operands (void)
16589 if (inst
.operands
[1].present
)
16591 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16593 /* Swap operands[1] and operands[2]. */
16594 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16595 inst
.operands
[1] = inst
.operands
[2];
16596 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16601 inst
.operands
[1] = inst
.operands
[2];
16602 inst
.operands
[2] = inst
.operands
[0];
16607 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16609 if (inst
.operands
[2].isreg
)
16612 neon_exchange_operands ();
16613 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16617 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16618 struct neon_type_el et
= neon_check_type (2, rs
,
16619 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16621 NEON_ENCODE (IMMED
, inst
);
16622 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16623 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16624 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16625 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16626 inst
.instruction
|= neon_quad (rs
) << 6;
16627 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16628 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16630 neon_dp_fixup (&inst
);
16637 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16641 do_neon_cmp_inv (void)
16643 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16649 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16652 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16653 scalars, which are encoded in 5 bits, M : Rm.
16654 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16655 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16658 Dot Product instructions are similar to multiply instructions except elsize
16659 should always be 32.
16661 This function translates SCALAR, which is GAS's internal encoding of indexed
16662 scalar register, to raw encoding. There is also register and index range
16663 check based on ELSIZE. */
16666 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16668 unsigned regno
= NEON_SCALAR_REG (scalar
);
16669 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16674 if (regno
> 7 || elno
> 3)
16676 return regno
| (elno
<< 3);
16679 if (regno
> 15 || elno
> 1)
16681 return regno
| (elno
<< 4);
16685 first_error (_("scalar out of range for multiply instruction"));
16691 /* Encode multiply / multiply-accumulate scalar instructions. */
16694 neon_mul_mac (struct neon_type_el et
, int ubit
)
16698 /* Give a more helpful error message if we have an invalid type. */
16699 if (et
.type
== NT_invtype
)
16702 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
16703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16707 inst
.instruction
|= LOW4 (scalar
);
16708 inst
.instruction
|= HI1 (scalar
) << 5;
16709 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16710 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16711 inst
.instruction
|= (ubit
!= 0) << 24;
16713 neon_dp_fixup (&inst
);
16717 do_neon_mac_maybe_scalar (void)
16719 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
16722 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16725 if (inst
.operands
[2].isscalar
)
16727 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16728 struct neon_type_el et
= neon_check_type (3, rs
,
16729 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
16730 NEON_ENCODE (SCALAR
, inst
);
16731 neon_mul_mac (et
, neon_quad (rs
));
16735 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16736 affected if we specify unsigned args. */
16737 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16742 do_neon_fmac (void)
16744 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
16747 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16750 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16756 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16757 struct neon_type_el et
= neon_check_type (3, rs
,
16758 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16759 neon_three_same (neon_quad (rs
), 0, et
.size
);
16762 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
16763 same types as the MAC equivalents. The polynomial type for this instruction
16764 is encoded the same as the integer type. */
16769 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
16772 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16775 if (inst
.operands
[2].isscalar
)
16776 do_neon_mac_maybe_scalar ();
16778 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
16782 do_neon_qdmulh (void)
16784 if (inst
.operands
[2].isscalar
)
16786 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16787 struct neon_type_el et
= neon_check_type (3, rs
,
16788 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16789 NEON_ENCODE (SCALAR
, inst
);
16790 neon_mul_mac (et
, neon_quad (rs
));
16794 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16795 struct neon_type_el et
= neon_check_type (3, rs
,
16796 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16797 NEON_ENCODE (INTEGER
, inst
);
16798 /* The U bit (rounding) comes from bit mask. */
16799 neon_three_same (neon_quad (rs
), 0, et
.size
);
16804 do_mve_vaddv (void)
16806 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
16807 struct neon_type_el et
16808 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16810 if (et
.type
== NT_invtype
)
16811 first_error (BAD_EL_TYPE
);
16813 if (inst
.cond
> COND_ALWAYS
)
16814 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16816 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16818 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16820 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
16826 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
16827 struct neon_type_el et
16828 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
16830 if (et
.type
== NT_invtype
)
16831 first_error (BAD_EL_TYPE
);
16833 if (inst
.cond
> COND_ALWAYS
)
16834 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16836 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16838 mve_encode_qqq (0, 64);
16842 do_mve_vbrsr (void)
16844 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16845 struct neon_type_el et
16846 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16848 if (inst
.cond
> COND_ALWAYS
)
16849 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16851 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16853 mve_encode_qqr (et
.size
, 0);
16859 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
16861 if (inst
.cond
> COND_ALWAYS
)
16862 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16864 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16866 mve_encode_qqq (1, 64);
16870 do_mve_vmull (void)
16873 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
16874 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
16875 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
16876 && inst
.cond
== COND_ALWAYS
16877 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
16882 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16883 N_SUF_32
| N_F64
| N_P8
16884 | N_P16
| N_I_MVE
| N_KEY
);
16885 if (((et
.type
== NT_poly
) && et
.size
== 8
16886 && ARM_CPU_IS_ANY (cpu_variant
))
16887 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
16894 constraint (rs
!= NS_QQQ
, BAD_FPU
);
16895 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16896 N_SU_32
| N_P8
| N_P16
| N_KEY
);
16898 /* We are dealing with MVE's vmullt. */
16900 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16901 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16902 as_tsktsk (BAD_MVE_SRCDEST
);
16904 if (inst
.cond
> COND_ALWAYS
)
16905 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16907 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16909 if (et
.type
== NT_poly
)
16910 mve_encode_qqq (neon_logbits (et
.size
), 64);
16912 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
16917 inst
.instruction
= N_MNEM_vmul
;
16920 inst
.pred_insn_type
= INSIDE_IT_INSN
;
16925 do_mve_vabav (void)
16927 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16932 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16935 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
16936 | N_S16
| N_S32
| N_U8
| N_U16
16939 if (inst
.cond
> COND_ALWAYS
)
16940 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16942 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16944 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
16948 do_mve_vmladav (void)
16950 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16951 struct neon_type_el et
= neon_check_type (3, rs
,
16952 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16954 if (et
.type
== NT_unsigned
16955 && (inst
.instruction
== M_MNEM_vmladavx
16956 || inst
.instruction
== M_MNEM_vmladavax
16957 || inst
.instruction
== M_MNEM_vmlsdav
16958 || inst
.instruction
== M_MNEM_vmlsdava
16959 || inst
.instruction
== M_MNEM_vmlsdavx
16960 || inst
.instruction
== M_MNEM_vmlsdavax
))
16961 first_error (BAD_SIMD_TYPE
);
16963 constraint (inst
.operands
[2].reg
> 14,
16964 _("MVE vector register in the range [Q0..Q7] expected"));
16966 if (inst
.cond
> COND_ALWAYS
)
16967 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16969 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16971 if (inst
.instruction
== M_MNEM_vmlsdav
16972 || inst
.instruction
== M_MNEM_vmlsdava
16973 || inst
.instruction
== M_MNEM_vmlsdavx
16974 || inst
.instruction
== M_MNEM_vmlsdavax
)
16975 inst
.instruction
|= (et
.size
== 8) << 28;
16977 inst
.instruction
|= (et
.size
== 8) << 8;
16979 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
16980 inst
.instruction
|= (et
.size
== 32) << 16;
16984 do_neon_qrdmlah (void)
16986 /* Check we're on the correct architecture. */
16987 if (!mark_feature_used (&fpu_neon_ext_armv8
))
16989 _("instruction form not available on this architecture.");
16990 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
16992 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
16993 record_feature_use (&fpu_neon_ext_v8_1
);
16996 if (inst
.operands
[2].isscalar
)
16998 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16999 struct neon_type_el et
= neon_check_type (3, rs
,
17000 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17001 NEON_ENCODE (SCALAR
, inst
);
17002 neon_mul_mac (et
, neon_quad (rs
));
17006 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17007 struct neon_type_el et
= neon_check_type (3, rs
,
17008 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17009 NEON_ENCODE (INTEGER
, inst
);
17010 /* The U bit (rounding) comes from bit mask. */
17011 neon_three_same (neon_quad (rs
), 0, et
.size
);
17016 do_neon_fcmp_absolute (void)
17018 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17019 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17020 N_F_16_32
| N_KEY
);
17021 /* Size field comes from bit mask. */
17022 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17026 do_neon_fcmp_absolute_inv (void)
17028 neon_exchange_operands ();
17029 do_neon_fcmp_absolute ();
17033 do_neon_step (void)
17035 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17036 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17037 N_F_16_32
| N_KEY
);
17038 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17042 do_neon_abs_neg (void)
17044 enum neon_shape rs
;
17045 struct neon_type_el et
;
17047 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
17050 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17051 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
17053 if (check_simd_pred_availability (et
.type
== NT_float
,
17054 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17057 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17061 inst
.instruction
|= neon_quad (rs
) << 6;
17062 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17063 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17065 neon_dp_fixup (&inst
);
17071 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17072 struct neon_type_el et
= neon_check_type (2, rs
,
17073 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17074 int imm
= inst
.operands
[2].imm
;
17075 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17076 _("immediate out of range for insert"));
17077 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17083 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17084 struct neon_type_el et
= neon_check_type (2, rs
,
17085 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17086 int imm
= inst
.operands
[2].imm
;
17087 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17088 _("immediate out of range for insert"));
17089 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
17093 do_neon_qshlu_imm (void)
17095 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17096 struct neon_type_el et
= neon_check_type (2, rs
,
17097 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
17098 int imm
= inst
.operands
[2].imm
;
17099 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17100 _("immediate out of range for shift"));
17101 /* Only encodes the 'U present' variant of the instruction.
17102 In this case, signed types have OP (bit 8) set to 0.
17103 Unsigned types have OP set to 1. */
17104 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
17105 /* The rest of the bits are the same as other immediate shifts. */
17106 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17110 do_neon_qmovn (void)
17112 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17113 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17114 /* Saturating move where operands can be signed or unsigned, and the
17115 destination has the same signedness. */
17116 NEON_ENCODE (INTEGER
, inst
);
17117 if (et
.type
== NT_unsigned
)
17118 inst
.instruction
|= 0xc0;
17120 inst
.instruction
|= 0x80;
17121 neon_two_same (0, 1, et
.size
/ 2);
17125 do_neon_qmovun (void)
17127 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17128 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17129 /* Saturating move with unsigned results. Operands must be signed. */
17130 NEON_ENCODE (INTEGER
, inst
);
17131 neon_two_same (0, 1, et
.size
/ 2);
17135 do_neon_rshift_sat_narrow (void)
17137 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17138 or unsigned. If operands are unsigned, results must also be unsigned. */
17139 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17140 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17141 int imm
= inst
.operands
[2].imm
;
17142 /* This gets the bounds check, size encoding and immediate bits calculation
17146 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17147 VQMOVN.I<size> <Dd>, <Qm>. */
17150 inst
.operands
[2].present
= 0;
17151 inst
.instruction
= N_MNEM_vqmovn
;
17156 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17157 _("immediate out of range"));
17158 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17162 do_neon_rshift_sat_narrow_u (void)
17164 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17165 or unsigned. If operands are unsigned, results must also be unsigned. */
17166 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17167 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17168 int imm
= inst
.operands
[2].imm
;
17169 /* This gets the bounds check, size encoding and immediate bits calculation
17173 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17174 VQMOVUN.I<size> <Dd>, <Qm>. */
17177 inst
.operands
[2].present
= 0;
17178 inst
.instruction
= N_MNEM_vqmovun
;
17183 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17184 _("immediate out of range"));
17185 /* FIXME: The manual is kind of unclear about what value U should have in
17186 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17188 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
17192 do_neon_movn (void)
17194 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17195 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17196 NEON_ENCODE (INTEGER
, inst
);
17197 neon_two_same (0, 1, et
.size
/ 2);
17201 do_neon_rshift_narrow (void)
17203 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17204 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17205 int imm
= inst
.operands
[2].imm
;
17206 /* This gets the bounds check, size encoding and immediate bits calculation
17210 /* If immediate is zero then we are a pseudo-instruction for
17211 VMOVN.I<size> <Dd>, <Qm> */
17214 inst
.operands
[2].present
= 0;
17215 inst
.instruction
= N_MNEM_vmovn
;
17220 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17221 _("immediate out of range for narrowing operation"));
17222 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
17226 do_neon_shll (void)
17228 /* FIXME: Type checking when lengthening. */
17229 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
17230 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
17231 unsigned imm
= inst
.operands
[2].imm
;
17233 if (imm
== et
.size
)
17235 /* Maximum shift variant. */
17236 NEON_ENCODE (INTEGER
, inst
);
17237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17238 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17241 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17243 neon_dp_fixup (&inst
);
17247 /* A more-specific type check for non-max versions. */
17248 et
= neon_check_type (2, NS_QDI
,
17249 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17250 NEON_ENCODE (IMMED
, inst
);
17251 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
17255 /* Check the various types for the VCVT instruction, and return which version
17256 the current instruction is. */
17258 #define CVT_FLAVOUR_VAR \
17259 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17260 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17261 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17262 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17263 /* Half-precision conversions. */ \
17264 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17265 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17266 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17267 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17268 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17269 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17270 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17271 Compared with single/double precision variants, only the co-processor \
17272 field is different, so the encoding flow is reused here. */ \
17273 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17274 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17275 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17276 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17277 /* VFP instructions. */ \
17278 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17279 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17280 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17281 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17282 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17283 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17284 /* VFP instructions with bitshift. */ \
17285 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17286 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17287 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17288 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17289 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17290 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17291 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17292 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17294 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17295 neon_cvt_flavour_##C,
17297 /* The different types of conversions we can do. */
17298 enum neon_cvt_flavour
17301 neon_cvt_flavour_invalid
,
17302 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
17307 static enum neon_cvt_flavour
17308 get_neon_cvt_flavour (enum neon_shape rs
)
17310 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17311 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17312 if (et.type != NT_invtype) \
17314 inst.error = NULL; \
17315 return (neon_cvt_flavour_##C); \
17318 struct neon_type_el et
;
17319 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
17320 || rs
== NS_FF
) ? N_VFP
: 0;
17321 /* The instruction versions which take an immediate take one register
17322 argument, which is extended to the width of the full register. Thus the
17323 "source" and "destination" registers must have the same width. Hack that
17324 here by making the size equal to the key (wider, in this case) operand. */
17325 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
17329 return neon_cvt_flavour_invalid
;
17344 /* Neon-syntax VFP conversions. */
17347 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
17349 const char *opname
= 0;
17351 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
17352 || rs
== NS_FHI
|| rs
== NS_HFI
)
17354 /* Conversions with immediate bitshift. */
17355 const char *enc
[] =
17357 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17363 if (flavour
< (int) ARRAY_SIZE (enc
))
17365 opname
= enc
[flavour
];
17366 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17367 _("operands 0 and 1 must be the same register"));
17368 inst
.operands
[1] = inst
.operands
[2];
17369 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17374 /* Conversions without bitshift. */
17375 const char *enc
[] =
17377 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17383 if (flavour
< (int) ARRAY_SIZE (enc
))
17384 opname
= enc
[flavour
];
17388 do_vfp_nsyn_opcode (opname
);
17390 /* ARMv8.2 fp16 VCVT instruction. */
17391 if (flavour
== neon_cvt_flavour_s32_f16
17392 || flavour
== neon_cvt_flavour_u32_f16
17393 || flavour
== neon_cvt_flavour_f16_u32
17394 || flavour
== neon_cvt_flavour_f16_s32
)
17395 do_scalar_fp16_v82_encode ();
17399 do_vfp_nsyn_cvtz (void)
17401 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17402 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17403 const char *enc
[] =
17405 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17411 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17412 do_vfp_nsyn_opcode (enc
[flavour
]);
17416 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17417 enum neon_cvt_mode mode
)
17422 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17423 D register operands. */
17424 if (flavour
== neon_cvt_flavour_s32_f64
17425 || flavour
== neon_cvt_flavour_u32_f64
)
17426 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17429 if (flavour
== neon_cvt_flavour_s32_f16
17430 || flavour
== neon_cvt_flavour_u32_f16
)
17431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17434 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17438 case neon_cvt_flavour_s32_f64
:
17442 case neon_cvt_flavour_s32_f32
:
17446 case neon_cvt_flavour_s32_f16
:
17450 case neon_cvt_flavour_u32_f64
:
17454 case neon_cvt_flavour_u32_f32
:
17458 case neon_cvt_flavour_u32_f16
:
17463 first_error (_("invalid instruction shape"));
17469 case neon_cvt_mode_a
: rm
= 0; break;
17470 case neon_cvt_mode_n
: rm
= 1; break;
17471 case neon_cvt_mode_p
: rm
= 2; break;
17472 case neon_cvt_mode_m
: rm
= 3; break;
17473 default: first_error (_("invalid rounding mode")); return;
17476 NEON_ENCODE (FPV8
, inst
);
17477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
17478 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
17479 inst
.instruction
|= sz
<< 8;
17481 /* ARMv8.2 fp16 VCVT instruction. */
17482 if (flavour
== neon_cvt_flavour_s32_f16
17483 ||flavour
== neon_cvt_flavour_u32_f16
)
17484 do_scalar_fp16_v82_encode ();
17485 inst
.instruction
|= op
<< 7;
17486 inst
.instruction
|= rm
<< 16;
17487 inst
.instruction
|= 0xf0000000;
17488 inst
.is_neon
= TRUE
;
17492 do_neon_cvt_1 (enum neon_cvt_mode mode
)
17494 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
17495 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
17496 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
17498 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17500 if (flavour
== neon_cvt_flavour_invalid
)
17503 /* PR11109: Handle round-to-zero for VCVT conversions. */
17504 if (mode
== neon_cvt_mode_z
17505 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
17506 && (flavour
== neon_cvt_flavour_s16_f16
17507 || flavour
== neon_cvt_flavour_u16_f16
17508 || flavour
== neon_cvt_flavour_s32_f32
17509 || flavour
== neon_cvt_flavour_u32_f32
17510 || flavour
== neon_cvt_flavour_s32_f64
17511 || flavour
== neon_cvt_flavour_u32_f64
)
17512 && (rs
== NS_FD
|| rs
== NS_FF
))
17514 do_vfp_nsyn_cvtz ();
17518 /* ARMv8.2 fp16 VCVT conversions. */
17519 if (mode
== neon_cvt_mode_z
17520 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
17521 && (flavour
== neon_cvt_flavour_s32_f16
17522 || flavour
== neon_cvt_flavour_u32_f16
)
17525 do_vfp_nsyn_cvtz ();
17526 do_scalar_fp16_v82_encode ();
17530 /* VFP rather than Neon conversions. */
17531 if (flavour
>= neon_cvt_flavour_first_fp
)
17533 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17534 do_vfp_nsyn_cvt (rs
, flavour
);
17536 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17544 if (mode
== neon_cvt_mode_z
17545 && (flavour
== neon_cvt_flavour_f16_s16
17546 || flavour
== neon_cvt_flavour_f16_u16
17547 || flavour
== neon_cvt_flavour_s16_f16
17548 || flavour
== neon_cvt_flavour_u16_f16
17549 || flavour
== neon_cvt_flavour_f32_u32
17550 || flavour
== neon_cvt_flavour_f32_s32
17551 || flavour
== neon_cvt_flavour_s32_f32
17552 || flavour
== neon_cvt_flavour_u32_f32
))
17554 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17557 else if (mode
== neon_cvt_mode_n
)
17559 /* We are dealing with vcvt with the 'ne' condition. */
17561 inst
.instruction
= N_MNEM_vcvt
;
17562 do_neon_cvt_1 (neon_cvt_mode_z
);
17565 /* fall through. */
17569 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17570 0x0000100, 0x1000100, 0x0, 0x1000000};
17572 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17573 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17578 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
17579 _("immediate value out of range"));
17582 case neon_cvt_flavour_f16_s16
:
17583 case neon_cvt_flavour_f16_u16
:
17584 case neon_cvt_flavour_s16_f16
:
17585 case neon_cvt_flavour_u16_f16
:
17586 constraint (inst
.operands
[2].imm
> 16,
17587 _("immediate value out of range"));
17589 case neon_cvt_flavour_f32_u32
:
17590 case neon_cvt_flavour_f32_s32
:
17591 case neon_cvt_flavour_s32_f32
:
17592 case neon_cvt_flavour_u32_f32
:
17593 constraint (inst
.operands
[2].imm
> 32,
17594 _("immediate value out of range"));
17597 inst
.error
= BAD_FPU
;
17602 /* Fixed-point conversion with #0 immediate is encoded as an
17603 integer conversion. */
17604 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
17606 NEON_ENCODE (IMMED
, inst
);
17607 if (flavour
!= neon_cvt_flavour_invalid
)
17608 inst
.instruction
|= enctab
[flavour
];
17609 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17610 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17611 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17612 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17613 inst
.instruction
|= neon_quad (rs
) << 6;
17614 inst
.instruction
|= 1 << 21;
17615 if (flavour
< neon_cvt_flavour_s16_f16
)
17617 inst
.instruction
|= 1 << 21;
17618 immbits
= 32 - inst
.operands
[2].imm
;
17619 inst
.instruction
|= immbits
<< 16;
17623 inst
.instruction
|= 3 << 20;
17624 immbits
= 16 - inst
.operands
[2].imm
;
17625 inst
.instruction
|= immbits
<< 16;
17626 inst
.instruction
&= ~(1 << 9);
17629 neon_dp_fixup (&inst
);
17634 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17635 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
17636 && (flavour
== neon_cvt_flavour_s16_f16
17637 || flavour
== neon_cvt_flavour_u16_f16
17638 || flavour
== neon_cvt_flavour_s32_f32
17639 || flavour
== neon_cvt_flavour_u32_f32
))
17641 if (check_simd_pred_availability (1,
17642 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17645 else if (mode
== neon_cvt_mode_z
17646 && (flavour
== neon_cvt_flavour_f16_s16
17647 || flavour
== neon_cvt_flavour_f16_u16
17648 || flavour
== neon_cvt_flavour_s16_f16
17649 || flavour
== neon_cvt_flavour_u16_f16
17650 || flavour
== neon_cvt_flavour_f32_u32
17651 || flavour
== neon_cvt_flavour_f32_s32
17652 || flavour
== neon_cvt_flavour_s32_f32
17653 || flavour
== neon_cvt_flavour_u32_f32
))
17655 if (check_simd_pred_availability (1,
17656 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17659 /* fall through. */
17661 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
17664 NEON_ENCODE (FLOAT
, inst
);
17665 if (check_simd_pred_availability (1,
17666 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17673 inst
.instruction
|= neon_quad (rs
) << 6;
17674 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
17675 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
17676 inst
.instruction
|= mode
<< 8;
17677 if (flavour
== neon_cvt_flavour_u16_f16
17678 || flavour
== neon_cvt_flavour_s16_f16
)
17679 /* Mask off the original size bits and reencode them. */
17680 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
17683 inst
.instruction
|= 0xfc000000;
17685 inst
.instruction
|= 0xf0000000;
17691 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
17692 0x100, 0x180, 0x0, 0x080};
17694 NEON_ENCODE (INTEGER
, inst
);
17696 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17698 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17702 if (flavour
!= neon_cvt_flavour_invalid
)
17703 inst
.instruction
|= enctab
[flavour
];
17705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17707 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17708 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17709 inst
.instruction
|= neon_quad (rs
) << 6;
17710 if (flavour
>= neon_cvt_flavour_s16_f16
17711 && flavour
<= neon_cvt_flavour_f16_u16
)
17712 /* Half precision. */
17713 inst
.instruction
|= 1 << 18;
17715 inst
.instruction
|= 2 << 18;
17717 neon_dp_fixup (&inst
);
17722 /* Half-precision conversions for Advanced SIMD -- neon. */
17725 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17729 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
17731 as_bad (_("operand size must match register width"));
17736 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
17738 as_bad (_("operand size must match register width"));
17743 inst
.instruction
= 0x3b60600;
17745 inst
.instruction
= 0x3b60700;
17747 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17748 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17749 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17750 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17751 neon_dp_fixup (&inst
);
17755 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
17756 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17757 do_vfp_nsyn_cvt (rs
, flavour
);
17759 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17764 do_neon_cvtr (void)
17766 do_neon_cvt_1 (neon_cvt_mode_x
);
17772 do_neon_cvt_1 (neon_cvt_mode_z
);
17776 do_neon_cvta (void)
17778 do_neon_cvt_1 (neon_cvt_mode_a
);
17782 do_neon_cvtn (void)
17784 do_neon_cvt_1 (neon_cvt_mode_n
);
17788 do_neon_cvtp (void)
17790 do_neon_cvt_1 (neon_cvt_mode_p
);
17794 do_neon_cvtm (void)
17796 do_neon_cvt_1 (neon_cvt_mode_m
);
17800 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
17803 mark_feature_used (&fpu_vfp_ext_armv8
);
17805 encode_arm_vfp_reg (inst
.operands
[0].reg
,
17806 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
17807 encode_arm_vfp_reg (inst
.operands
[1].reg
,
17808 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
17809 inst
.instruction
|= to
? 0x10000 : 0;
17810 inst
.instruction
|= t
? 0x80 : 0;
17811 inst
.instruction
|= is_double
? 0x100 : 0;
17812 do_vfp_cond_or_thumb ();
17816 do_neon_cvttb_1 (bfd_boolean t
)
17818 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
17819 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
17823 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
17825 int single_to_half
= 0;
17826 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
17829 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17831 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17832 && (flavour
== neon_cvt_flavour_u16_f16
17833 || flavour
== neon_cvt_flavour_s16_f16
17834 || flavour
== neon_cvt_flavour_f16_s16
17835 || flavour
== neon_cvt_flavour_f16_u16
17836 || flavour
== neon_cvt_flavour_u32_f32
17837 || flavour
== neon_cvt_flavour_s32_f32
17838 || flavour
== neon_cvt_flavour_f32_s32
17839 || flavour
== neon_cvt_flavour_f32_u32
))
17842 inst
.instruction
= N_MNEM_vcvt
;
17843 set_pred_insn_type (INSIDE_VPT_INSN
);
17844 do_neon_cvt_1 (neon_cvt_mode_z
);
17847 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
17848 single_to_half
= 1;
17849 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
17851 first_error (BAD_FPU
);
17855 inst
.instruction
= 0xee3f0e01;
17856 inst
.instruction
|= single_to_half
<< 28;
17857 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
17859 inst
.instruction
|= t
<< 12;
17860 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17861 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
17864 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
17867 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
17869 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
17872 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
17874 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
17876 /* The VCVTB and VCVTT instructions with D-register operands
17877 don't work for SP only targets. */
17878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17882 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
17884 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
17886 /* The VCVTB and VCVTT instructions with D-register operands
17887 don't work for SP only targets. */
17888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17892 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
17899 do_neon_cvtb (void)
17901 do_neon_cvttb_1 (FALSE
);
17906 do_neon_cvtt (void)
17908 do_neon_cvttb_1 (TRUE
);
17912 neon_move_immediate (void)
17914 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
17915 struct neon_type_el et
= neon_check_type (2, rs
,
17916 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
17917 unsigned immlo
, immhi
= 0, immbits
;
17918 int op
, cmode
, float_p
;
17920 constraint (et
.type
== NT_invtype
,
17921 _("operand size must be specified for immediate VMOV"));
17923 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
17924 op
= (inst
.instruction
& (1 << 5)) != 0;
17926 immlo
= inst
.operands
[1].imm
;
17927 if (inst
.operands
[1].regisimm
)
17928 immhi
= inst
.operands
[1].reg
;
17930 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
17931 _("immediate has bits set outside the operand size"));
17933 float_p
= inst
.operands
[1].immisfloat
;
17935 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
17936 et
.size
, et
.type
)) == FAIL
)
17938 /* Invert relevant bits only. */
17939 neon_invert_size (&immlo
, &immhi
, et
.size
);
17940 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
17941 with one or the other; those cases are caught by
17942 neon_cmode_for_move_imm. */
17944 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
17945 &op
, et
.size
, et
.type
)) == FAIL
)
17947 first_error (_("immediate out of range"));
17952 inst
.instruction
&= ~(1 << 5);
17953 inst
.instruction
|= op
<< 5;
17955 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17956 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17957 inst
.instruction
|= neon_quad (rs
) << 6;
17958 inst
.instruction
|= cmode
<< 8;
17960 neon_write_immbits (immbits
);
17966 if (inst
.operands
[1].isreg
)
17968 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17970 NEON_ENCODE (INTEGER
, inst
);
17971 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17972 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17973 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17974 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17975 inst
.instruction
|= neon_quad (rs
) << 6;
17979 NEON_ENCODE (IMMED
, inst
);
17980 neon_move_immediate ();
17983 neon_dp_fixup (&inst
);
17986 /* Encode instructions of form:
17988 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
17989 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
17992 neon_mixed_length (struct neon_type_el et
, unsigned size
)
17994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17995 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17996 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17997 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17998 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17999 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18000 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
18001 inst
.instruction
|= neon_logbits (size
) << 20;
18003 neon_dp_fixup (&inst
);
18007 do_neon_dyadic_long (void)
18009 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
18012 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
18015 NEON_ENCODE (INTEGER
, inst
);
18016 /* FIXME: Type checking for lengthening op. */
18017 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18018 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18019 neon_mixed_length (et
, et
.size
);
18021 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18022 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
18024 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18025 in an IT block with le/lt conditions. */
18027 if (inst
.cond
== 0xf)
18029 else if (inst
.cond
== 0x10)
18032 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18034 if (inst
.instruction
== N_MNEM_vaddl
)
18036 inst
.instruction
= N_MNEM_vadd
;
18037 do_neon_addsub_if_i ();
18039 else if (inst
.instruction
== N_MNEM_vsubl
)
18041 inst
.instruction
= N_MNEM_vsub
;
18042 do_neon_addsub_if_i ();
18044 else if (inst
.instruction
== N_MNEM_vabdl
)
18046 inst
.instruction
= N_MNEM_vabd
;
18047 do_neon_dyadic_if_su ();
18051 first_error (BAD_FPU
);
18055 do_neon_abal (void)
18057 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18058 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18059 neon_mixed_length (et
, et
.size
);
18063 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
18065 if (inst
.operands
[2].isscalar
)
18067 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
18068 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
18069 NEON_ENCODE (SCALAR
, inst
);
18070 neon_mul_mac (et
, et
.type
== NT_unsigned
);
18074 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18075 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
18076 NEON_ENCODE (INTEGER
, inst
);
18077 neon_mixed_length (et
, et
.size
);
18082 do_neon_mac_maybe_scalar_long (void)
18084 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
18087 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18088 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18091 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
18093 unsigned regno
= NEON_SCALAR_REG (scalar
);
18094 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
18098 if (regno
> 7 || elno
> 3)
18101 return ((regno
& 0x7)
18102 | ((elno
& 0x1) << 3)
18103 | (((elno
>> 1) & 0x1) << 5));
18107 if (regno
> 15 || elno
> 1)
18110 return (((regno
& 0x1) << 5)
18111 | ((regno
>> 1) & 0x7)
18112 | ((elno
& 0x1) << 3));
18116 first_error (_("scalar out of range for multiply instruction"));
18121 do_neon_fmac_maybe_scalar_long (int subtype
)
18123 enum neon_shape rs
;
18125 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18126 field (bits[21:20]) has different meaning. For scalar index variant, it's
18127 used to differentiate add and subtract, otherwise it's with fixed value
18131 if (inst
.cond
!= COND_ALWAYS
)
18132 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18133 "behaviour is UNPREDICTABLE"));
18135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18138 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18141 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18142 be a scalar index register. */
18143 if (inst
.operands
[2].isscalar
)
18145 high8
= 0xfe000000;
18148 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18152 high8
= 0xfc000000;
18155 inst
.instruction
|= (0x1 << 23);
18156 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
18159 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
18161 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18162 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18163 so we simply pass -1 as size. */
18164 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
18165 neon_three_same (quad_p
, 0, size
);
18167 /* Undo neon_dp_fixup. Redo the high eight bits. */
18168 inst
.instruction
&= 0x00ffffff;
18169 inst
.instruction
|= high8
;
18171 #define LOW1(R) ((R) & 0x1)
18172 #define HI4(R) (((R) >> 1) & 0xf)
18173 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18174 whether the instruction is in Q form and whether Vm is a scalar indexed
18176 if (inst
.operands
[2].isscalar
)
18179 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
18180 inst
.instruction
&= 0xffffffd0;
18181 inst
.instruction
|= rm
;
18185 /* Redo Rn as well. */
18186 inst
.instruction
&= 0xfff0ff7f;
18187 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18188 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18193 /* Redo Rn and Rm. */
18194 inst
.instruction
&= 0xfff0ff50;
18195 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18196 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18197 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
18198 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
18203 do_neon_vfmal (void)
18205 return do_neon_fmac_maybe_scalar_long (0);
18209 do_neon_vfmsl (void)
18211 return do_neon_fmac_maybe_scalar_long (1);
18215 do_neon_dyadic_wide (void)
18217 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
18218 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18219 neon_mixed_length (et
, et
.size
);
18223 do_neon_dyadic_narrow (void)
18225 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18226 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
18227 /* Operand sign is unimportant, and the U bit is part of the opcode,
18228 so force the operand type to integer. */
18229 et
.type
= NT_integer
;
18230 neon_mixed_length (et
, et
.size
/ 2);
18234 do_neon_mul_sat_scalar_long (void)
18236 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
18240 do_neon_vmull (void)
18242 if (inst
.operands
[2].isscalar
)
18243 do_neon_mac_maybe_scalar_long ();
18246 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18247 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
18249 if (et
.type
== NT_poly
)
18250 NEON_ENCODE (POLY
, inst
);
18252 NEON_ENCODE (INTEGER
, inst
);
18254 /* For polynomial encoding the U bit must be zero, and the size must
18255 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18256 obviously, as 0b10). */
18259 /* Check we're on the correct architecture. */
18260 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
18262 _("Instruction form not available on this architecture.");
18267 neon_mixed_length (et
, et
.size
);
18274 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18275 struct neon_type_el et
= neon_check_type (3, rs
,
18276 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18277 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
18279 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
18280 _("shift out of range"));
18281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18283 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18284 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18285 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18286 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18287 inst
.instruction
|= neon_quad (rs
) << 6;
18288 inst
.instruction
|= imm
<< 8;
18290 neon_dp_fixup (&inst
);
18296 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18297 struct neon_type_el et
= neon_check_type (2, rs
,
18298 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18299 unsigned op
= (inst
.instruction
>> 7) & 3;
18300 /* N (width of reversed regions) is encoded as part of the bitmask. We
18301 extract it here to check the elements to be reversed are smaller.
18302 Otherwise we'd get a reserved instruction. */
18303 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
18304 gas_assert (elsize
!= 0);
18305 constraint (et
.size
>= elsize
,
18306 _("elements must be smaller than reversal region"));
18307 neon_two_same (neon_quad (rs
), 1, et
.size
);
18313 if (inst
.operands
[1].isscalar
)
18315 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
18316 struct neon_type_el et
= neon_check_type (2, rs
,
18317 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18318 unsigned sizebits
= et
.size
>> 3;
18319 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18320 int logsize
= neon_logbits (et
.size
);
18321 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
18323 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
18326 NEON_ENCODE (SCALAR
, inst
);
18327 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18328 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18329 inst
.instruction
|= LOW4 (dm
);
18330 inst
.instruction
|= HI1 (dm
) << 5;
18331 inst
.instruction
|= neon_quad (rs
) << 6;
18332 inst
.instruction
|= x
<< 17;
18333 inst
.instruction
|= sizebits
<< 16;
18335 neon_dp_fixup (&inst
);
18339 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
18340 struct neon_type_el et
= neon_check_type (2, rs
,
18341 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18342 /* Duplicate ARM register to lanes of vector. */
18343 NEON_ENCODE (ARMREG
, inst
);
18346 case 8: inst
.instruction
|= 0x400000; break;
18347 case 16: inst
.instruction
|= 0x000020; break;
18348 case 32: inst
.instruction
|= 0x000000; break;
18351 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18352 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18354 inst
.instruction
|= neon_quad (rs
) << 21;
18355 /* The encoding for this instruction is identical for the ARM and Thumb
18356 variants, except for the condition field. */
18357 do_vfp_cond_or_thumb ();
18362 do_mve_mov (int toQ
)
18364 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18366 if (inst
.cond
> COND_ALWAYS
)
18367 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18369 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18378 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18379 _("Index one must be [2,3] and index two must be two less than"
18381 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18382 _("General purpose registers may not be the same"));
18383 constraint (inst
.operands
[Rt
].reg
== REG_SP
18384 || inst
.operands
[Rt2
].reg
== REG_SP
,
18386 constraint (inst
.operands
[Rt
].reg
== REG_PC
18387 || inst
.operands
[Rt2
].reg
== REG_PC
,
18390 inst
.instruction
= 0xec000f00;
18391 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18392 inst
.instruction
|= !!toQ
<< 20;
18393 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18394 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18395 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18396 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18402 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18405 if (inst
.cond
> COND_ALWAYS
)
18406 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18408 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18410 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18414 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18415 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18416 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18417 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18422 /* VMOV has particularly many variations. It can be one of:
18423 0. VMOV<c><q> <Qd>, <Qm>
18424 1. VMOV<c><q> <Dd>, <Dm>
18425 (Register operations, which are VORR with Rm = Rn.)
18426 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18427 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18429 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18430 (ARM register to scalar.)
18431 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18432 (Two ARM registers to vector.)
18433 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18434 (Scalar to ARM register.)
18435 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18436 (Vector to two ARM registers.)
18437 8. VMOV.F32 <Sd>, <Sm>
18438 9. VMOV.F64 <Dd>, <Dm>
18439 (VFP register moves.)
18440 10. VMOV.F32 <Sd>, #imm
18441 11. VMOV.F64 <Dd>, #imm
18442 (VFP float immediate load.)
18443 12. VMOV <Rd>, <Sm>
18444 (VFP single to ARM reg.)
18445 13. VMOV <Sd>, <Rm>
18446 (ARM reg to VFP single.)
18447 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18448 (Two ARM regs to two VFP singles.)
18449 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18450 (Two VFP singles to two ARM regs.)
18451 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18452 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18453 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18454 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18456 These cases can be disambiguated using neon_select_shape, except cases 1/9
18457 and 3/11 which depend on the operand type too.
18459 All the encoded bits are hardcoded by this function.
18461 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18462 Cases 5, 7 may be used with VFPv2 and above.
18464 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18465 can specify a type where it doesn't make sense to, and is ignored). */
18470 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
18471 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
18472 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
18473 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
18475 struct neon_type_el et
;
18476 const char *ldconst
= 0;
18480 case NS_DD
: /* case 1/9. */
18481 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18482 /* It is not an error here if no type is given. */
18484 if (et
.type
== NT_float
&& et
.size
== 64)
18486 do_vfp_nsyn_opcode ("fcpyd");
18489 /* fall through. */
18491 case NS_QQ
: /* case 0/1. */
18493 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18495 /* The architecture manual I have doesn't explicitly state which
18496 value the U bit should have for register->register moves, but
18497 the equivalent VORR instruction has U = 0, so do that. */
18498 inst
.instruction
= 0x0200110;
18499 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18500 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18501 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18502 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18503 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18504 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18505 inst
.instruction
|= neon_quad (rs
) << 6;
18507 neon_dp_fixup (&inst
);
18511 case NS_DI
: /* case 3/11. */
18512 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18514 if (et
.type
== NT_float
&& et
.size
== 64)
18516 /* case 11 (fconstd). */
18517 ldconst
= "fconstd";
18518 goto encode_fconstd
;
18520 /* fall through. */
18522 case NS_QI
: /* case 2/3. */
18523 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18525 inst
.instruction
= 0x0800010;
18526 neon_move_immediate ();
18527 neon_dp_fixup (&inst
);
18530 case NS_SR
: /* case 4. */
18532 unsigned bcdebits
= 0;
18534 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
18535 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
18537 /* .<size> is optional here, defaulting to .32. */
18538 if (inst
.vectype
.elems
== 0
18539 && inst
.operands
[0].vectype
.type
== NT_invtype
18540 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18542 inst
.vectype
.el
[0].type
= NT_untyped
;
18543 inst
.vectype
.el
[0].size
= 32;
18544 inst
.vectype
.elems
= 1;
18547 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18548 logsize
= neon_logbits (et
.size
);
18552 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18553 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
18558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18559 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18563 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18565 if (inst
.operands
[1].reg
== REG_SP
)
18566 as_tsktsk (MVE_BAD_SP
);
18567 else if (inst
.operands
[1].reg
== REG_PC
)
18568 as_tsktsk (MVE_BAD_PC
);
18570 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
18572 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18573 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18578 case 8: bcdebits
= 0x8; break;
18579 case 16: bcdebits
= 0x1; break;
18580 case 32: bcdebits
= 0x0; break;
18584 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18586 inst
.instruction
= 0xe000b10;
18587 do_vfp_cond_or_thumb ();
18588 inst
.instruction
|= LOW4 (dn
) << 16;
18589 inst
.instruction
|= HI1 (dn
) << 7;
18590 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18591 inst
.instruction
|= (bcdebits
& 3) << 5;
18592 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
18593 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18597 case NS_DRR
: /* case 5 (fmdrr). */
18598 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18599 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18602 inst
.instruction
= 0xc400b10;
18603 do_vfp_cond_or_thumb ();
18604 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
18605 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
18606 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18607 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
18610 case NS_RS
: /* case 6. */
18613 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18614 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
18615 unsigned abcdebits
= 0;
18617 /* .<dt> is optional here, defaulting to .32. */
18618 if (inst
.vectype
.elems
== 0
18619 && inst
.operands
[0].vectype
.type
== NT_invtype
18620 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18622 inst
.vectype
.el
[0].type
= NT_untyped
;
18623 inst
.vectype
.el
[0].size
= 32;
18624 inst
.vectype
.elems
= 1;
18627 et
= neon_check_type (2, NS_NULL
,
18628 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
18629 logsize
= neon_logbits (et
.size
);
18633 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18634 && vfp_or_neon_is_neon (NEON_CHECK_CC
18635 | NEON_CHECK_ARCH
) == FAIL
)
18640 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18641 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18645 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18647 if (inst
.operands
[0].reg
== REG_SP
)
18648 as_tsktsk (MVE_BAD_SP
);
18649 else if (inst
.operands
[0].reg
== REG_PC
)
18650 as_tsktsk (MVE_BAD_PC
);
18653 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
18655 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18656 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18660 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
18661 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
18662 case 32: abcdebits
= 0x00; break;
18666 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18667 inst
.instruction
= 0xe100b10;
18668 do_vfp_cond_or_thumb ();
18669 inst
.instruction
|= LOW4 (dn
) << 16;
18670 inst
.instruction
|= HI1 (dn
) << 7;
18671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18672 inst
.instruction
|= (abcdebits
& 3) << 5;
18673 inst
.instruction
|= (abcdebits
>> 2) << 21;
18674 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18678 case NS_RRD
: /* case 7 (fmrrd). */
18679 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18680 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18683 inst
.instruction
= 0xc500b10;
18684 do_vfp_cond_or_thumb ();
18685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18686 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
18687 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18688 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18691 case NS_FF
: /* case 8 (fcpys). */
18692 do_vfp_nsyn_opcode ("fcpys");
18696 case NS_FI
: /* case 10 (fconsts). */
18697 ldconst
= "fconsts";
18699 if (!inst
.operands
[1].immisfloat
)
18702 /* Immediate has to fit in 8 bits so float is enough. */
18703 float imm
= (float) inst
.operands
[1].imm
;
18704 memcpy (&new_imm
, &imm
, sizeof (float));
18705 /* But the assembly may have been written to provide an integer
18706 bit pattern that equates to a float, so check that the
18707 conversion has worked. */
18708 if (is_quarter_float (new_imm
))
18710 if (is_quarter_float (inst
.operands
[1].imm
))
18711 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
18713 inst
.operands
[1].imm
= new_imm
;
18714 inst
.operands
[1].immisfloat
= 1;
18718 if (is_quarter_float (inst
.operands
[1].imm
))
18720 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
18721 do_vfp_nsyn_opcode (ldconst
);
18723 /* ARMv8.2 fp16 vmov.f16 instruction. */
18725 do_scalar_fp16_v82_encode ();
18728 first_error (_("immediate out of range"));
18732 case NS_RF
: /* case 12 (fmrs). */
18733 do_vfp_nsyn_opcode ("fmrs");
18734 /* ARMv8.2 fp16 vmov.f16 instruction. */
18736 do_scalar_fp16_v82_encode ();
18740 case NS_FR
: /* case 13 (fmsr). */
18741 do_vfp_nsyn_opcode ("fmsr");
18742 /* ARMv8.2 fp16 vmov.f16 instruction. */
18744 do_scalar_fp16_v82_encode ();
18754 /* The encoders for the fmrrs and fmsrr instructions expect three operands
18755 (one of which is a list), but we have parsed four. Do some fiddling to
18756 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
18758 case NS_RRFF
: /* case 14 (fmrrs). */
18759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18760 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18762 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
18763 _("VFP registers must be adjacent"));
18764 inst
.operands
[2].imm
= 2;
18765 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18766 do_vfp_nsyn_opcode ("fmrrs");
18769 case NS_FFRR
: /* case 15 (fmsrr). */
18770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18771 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18773 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
18774 _("VFP registers must be adjacent"));
18775 inst
.operands
[1] = inst
.operands
[2];
18776 inst
.operands
[2] = inst
.operands
[3];
18777 inst
.operands
[0].imm
= 2;
18778 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18779 do_vfp_nsyn_opcode ("fmsrr");
18783 /* neon_select_shape has determined that the instruction
18784 shape is wrong and has already set the error message. */
18795 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
18796 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
18797 && !inst
.operands
[2].present
))
18799 inst
.instruction
= 0;
18802 set_pred_insn_type (INSIDE_IT_INSN
);
18807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18810 if (inst
.cond
!= COND_ALWAYS
)
18811 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18813 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
18814 | N_S16
| N_U16
| N_KEY
);
18816 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
18817 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18818 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
18819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18820 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18821 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18826 do_neon_rshift_round_imm (void)
18828 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18829 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
18830 int imm
= inst
.operands
[2].imm
;
18832 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
18835 inst
.operands
[2].present
= 0;
18840 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18841 _("immediate out of range for shift"));
18842 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
18847 do_neon_movhf (void)
18849 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
18850 constraint (rs
!= NS_HH
, _("invalid suffix"));
18852 if (inst
.cond
!= COND_ALWAYS
)
18856 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
18857 " the behaviour is UNPREDICTABLE"));
18861 inst
.error
= BAD_COND
;
18866 do_vfp_sp_monadic ();
18869 inst
.instruction
|= 0xf0000000;
18873 do_neon_movl (void)
18875 struct neon_type_el et
= neon_check_type (2, NS_QD
,
18876 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18877 unsigned sizebits
= et
.size
>> 3;
18878 inst
.instruction
|= sizebits
<< 19;
18879 neon_two_same (0, et
.type
== NT_unsigned
, -1);
18885 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18886 struct neon_type_el et
= neon_check_type (2, rs
,
18887 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18888 NEON_ENCODE (INTEGER
, inst
);
18889 neon_two_same (neon_quad (rs
), 1, et
.size
);
18893 do_neon_zip_uzp (void)
18895 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18896 struct neon_type_el et
= neon_check_type (2, rs
,
18897 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18898 if (rs
== NS_DD
&& et
.size
== 32)
18900 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
18901 inst
.instruction
= N_MNEM_vtrn
;
18905 neon_two_same (neon_quad (rs
), 1, et
.size
);
18909 do_neon_sat_abs_neg (void)
18911 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18912 struct neon_type_el et
= neon_check_type (2, rs
,
18913 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18914 neon_two_same (neon_quad (rs
), 1, et
.size
);
18918 do_neon_pair_long (void)
18920 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18921 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18922 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
18923 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
18924 neon_two_same (neon_quad (rs
), 1, et
.size
);
18928 do_neon_recip_est (void)
18930 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18931 struct neon_type_el et
= neon_check_type (2, rs
,
18932 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
18933 inst
.instruction
|= (et
.type
== NT_float
) << 8;
18934 neon_two_same (neon_quad (rs
), 1, et
.size
);
18940 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18941 struct neon_type_el et
= neon_check_type (2, rs
,
18942 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18943 neon_two_same (neon_quad (rs
), 1, et
.size
);
18949 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18950 struct neon_type_el et
= neon_check_type (2, rs
,
18951 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
18952 neon_two_same (neon_quad (rs
), 1, et
.size
);
18958 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18959 struct neon_type_el et
= neon_check_type (2, rs
,
18960 N_EQK
| N_INT
, N_8
| N_KEY
);
18961 neon_two_same (neon_quad (rs
), 1, et
.size
);
18967 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18968 neon_two_same (neon_quad (rs
), 1, -1);
18972 do_neon_tbl_tbx (void)
18974 unsigned listlenbits
;
18975 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
18977 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
18979 first_error (_("bad list length for table lookup"));
18983 listlenbits
= inst
.operands
[1].imm
- 1;
18984 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18985 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18986 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18987 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18988 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18989 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18990 inst
.instruction
|= listlenbits
<< 8;
18992 neon_dp_fixup (&inst
);
18996 do_neon_ldm_stm (void)
18998 /* P, U and L bits are part of bitmask. */
18999 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
19000 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
19002 if (inst
.operands
[1].issingle
)
19004 do_vfp_nsyn_ldm_stm (is_dbmode
);
19008 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
19009 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19011 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
19012 _("register list must contain at least 1 and at most 16 "
19015 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
19016 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
19017 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19018 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
19020 inst
.instruction
|= offsetbits
;
19022 do_vfp_cond_or_thumb ();
19026 do_neon_ldr_str (void)
19028 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
19030 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19031 And is UNPREDICTABLE in thumb mode. */
19033 && inst
.operands
[1].reg
== REG_PC
19034 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
19037 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19038 else if (warn_on_deprecated
)
19039 as_tsktsk (_("Use of PC here is deprecated"));
19042 if (inst
.operands
[0].issingle
)
19045 do_vfp_nsyn_opcode ("flds");
19047 do_vfp_nsyn_opcode ("fsts");
19049 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19050 if (inst
.vectype
.el
[0].size
== 16)
19051 do_scalar_fp16_v82_encode ();
19056 do_vfp_nsyn_opcode ("fldd");
19058 do_vfp_nsyn_opcode ("fstd");
19063 do_t_vldr_vstr_sysreg (void)
19065 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
19066 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
19068 /* Use of PC is UNPREDICTABLE. */
19069 if (inst
.operands
[1].reg
== REG_PC
)
19070 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19072 if (inst
.operands
[1].immisreg
)
19073 inst
.error
= _("instruction does not accept register index");
19075 if (!inst
.operands
[1].isreg
)
19076 inst
.error
= _("instruction does not accept PC-relative addressing");
19078 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
19079 inst
.error
= _("immediate value out of range");
19081 inst
.instruction
= 0xec000f80;
19083 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
19084 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
19085 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
19086 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
19090 do_vldr_vstr (void)
19092 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
19094 /* VLDR/VSTR (System Register). */
19097 if (!mark_feature_used (&arm_ext_v8_1m_main
))
19098 as_bad (_("Instruction not permitted on this architecture"));
19100 do_t_vldr_vstr_sysreg ();
19105 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
19106 as_bad (_("Instruction not permitted on this architecture"));
19107 do_neon_ldr_str ();
19111 /* "interleave" version also handles non-interleaving register VLD1/VST1
19115 do_neon_ld_st_interleave (void)
19117 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
19118 N_8
| N_16
| N_32
| N_64
);
19119 unsigned alignbits
= 0;
19121 /* The bits in this table go:
19122 0: register stride of one (0) or two (1)
19123 1,2: register list length, minus one (1, 2, 3, 4).
19124 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19125 We use -1 for invalid entries. */
19126 const int typetable
[] =
19128 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19129 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19130 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19131 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19135 if (et
.type
== NT_invtype
)
19138 if (inst
.operands
[1].immisalign
)
19139 switch (inst
.operands
[1].imm
>> 8)
19141 case 64: alignbits
= 1; break;
19143 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
19144 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19145 goto bad_alignment
;
19149 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19150 goto bad_alignment
;
19155 first_error (_("bad alignment"));
19159 inst
.instruction
|= alignbits
<< 4;
19160 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19162 /* Bits [4:6] of the immediate in a list specifier encode register stride
19163 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19164 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19165 up the right value for "type" in a table based on this value and the given
19166 list style, then stick it back. */
19167 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
19168 | (((inst
.instruction
>> 8) & 3) << 3);
19170 typebits
= typetable
[idx
];
19172 constraint (typebits
== -1, _("bad list type for instruction"));
19173 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
19176 inst
.instruction
&= ~0xf00;
19177 inst
.instruction
|= typebits
<< 8;
19180 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19181 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19182 otherwise. The variable arguments are a list of pairs of legal (size, align)
19183 values, terminated with -1. */
19186 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
19189 int result
= FAIL
, thissize
, thisalign
;
19191 if (!inst
.operands
[1].immisalign
)
19197 va_start (ap
, do_alignment
);
19201 thissize
= va_arg (ap
, int);
19202 if (thissize
== -1)
19204 thisalign
= va_arg (ap
, int);
19206 if (size
== thissize
&& align
== thisalign
)
19209 while (result
!= SUCCESS
);
19213 if (result
== SUCCESS
)
19216 first_error (_("unsupported alignment for instruction"));
19222 do_neon_ld_st_lane (void)
19224 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19225 int align_good
, do_alignment
= 0;
19226 int logsize
= neon_logbits (et
.size
);
19227 int align
= inst
.operands
[1].imm
>> 8;
19228 int n
= (inst
.instruction
>> 8) & 3;
19229 int max_el
= 64 / et
.size
;
19231 if (et
.type
== NT_invtype
)
19234 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
19235 _("bad list length"));
19236 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
19237 _("scalar index out of range"));
19238 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
19240 _("stride of 2 unavailable when element size is 8"));
19244 case 0: /* VLD1 / VST1. */
19245 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
19247 if (align_good
== FAIL
)
19251 unsigned alignbits
= 0;
19254 case 16: alignbits
= 0x1; break;
19255 case 32: alignbits
= 0x3; break;
19258 inst
.instruction
|= alignbits
<< 4;
19262 case 1: /* VLD2 / VST2. */
19263 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
19264 16, 32, 32, 64, -1);
19265 if (align_good
== FAIL
)
19268 inst
.instruction
|= 1 << 4;
19271 case 2: /* VLD3 / VST3. */
19272 constraint (inst
.operands
[1].immisalign
,
19273 _("can't use alignment with this instruction"));
19276 case 3: /* VLD4 / VST4. */
19277 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19278 16, 64, 32, 64, 32, 128, -1);
19279 if (align_good
== FAIL
)
19283 unsigned alignbits
= 0;
19286 case 8: alignbits
= 0x1; break;
19287 case 16: alignbits
= 0x1; break;
19288 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
19291 inst
.instruction
|= alignbits
<< 4;
19298 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19299 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19300 inst
.instruction
|= 1 << (4 + logsize
);
19302 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
19303 inst
.instruction
|= logsize
<< 10;
19306 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19309 do_neon_ld_dup (void)
19311 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19312 int align_good
, do_alignment
= 0;
19314 if (et
.type
== NT_invtype
)
19317 switch ((inst
.instruction
>> 8) & 3)
19319 case 0: /* VLD1. */
19320 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
19321 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19322 &do_alignment
, 16, 16, 32, 32, -1);
19323 if (align_good
== FAIL
)
19325 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
19328 case 2: inst
.instruction
|= 1 << 5; break;
19329 default: first_error (_("bad list length")); return;
19331 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19334 case 1: /* VLD2. */
19335 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19336 &do_alignment
, 8, 16, 16, 32, 32, 64,
19338 if (align_good
== FAIL
)
19340 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
19341 _("bad list length"));
19342 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19343 inst
.instruction
|= 1 << 5;
19344 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19347 case 2: /* VLD3. */
19348 constraint (inst
.operands
[1].immisalign
,
19349 _("can't use alignment with this instruction"));
19350 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
19351 _("bad list length"));
19352 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19353 inst
.instruction
|= 1 << 5;
19354 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19357 case 3: /* VLD4. */
19359 int align
= inst
.operands
[1].imm
>> 8;
19360 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19361 16, 64, 32, 64, 32, 128, -1);
19362 if (align_good
== FAIL
)
19364 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19365 _("bad list length"));
19366 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19367 inst
.instruction
|= 1 << 5;
19368 if (et
.size
== 32 && align
== 128)
19369 inst
.instruction
|= 0x3 << 6;
19371 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19378 inst
.instruction
|= do_alignment
<< 4;
19381 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19382 apart from bits [11:4]. */
19385 do_neon_ldx_stx (void)
19387 if (inst
.operands
[1].isreg
)
19388 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19390 switch (NEON_LANE (inst
.operands
[0].imm
))
19392 case NEON_INTERLEAVE_LANES
:
19393 NEON_ENCODE (INTERLV
, inst
);
19394 do_neon_ld_st_interleave ();
19397 case NEON_ALL_LANES
:
19398 NEON_ENCODE (DUP
, inst
);
19399 if (inst
.instruction
== N_INV
)
19401 first_error ("only loads support such operands");
19408 NEON_ENCODE (LANE
, inst
);
19409 do_neon_ld_st_lane ();
19412 /* L bit comes from bit mask. */
19413 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19414 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19415 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19417 if (inst
.operands
[1].postind
)
19419 int postreg
= inst
.operands
[1].imm
& 0xf;
19420 constraint (!inst
.operands
[1].immisreg
,
19421 _("post-index must be a register"));
19422 constraint (postreg
== 0xd || postreg
== 0xf,
19423 _("bad register for post-index"));
19424 inst
.instruction
|= postreg
;
19428 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
19429 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
19430 || inst
.relocs
[0].exp
.X_add_number
!= 0,
19433 if (inst
.operands
[1].writeback
)
19435 inst
.instruction
|= 0xd;
19438 inst
.instruction
|= 0xf;
19442 inst
.instruction
|= 0xf9000000;
19444 inst
.instruction
|= 0xf4000000;
19449 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
19451 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19452 D register operands. */
19453 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19457 NEON_ENCODE (FPV8
, inst
);
19459 if (rs
== NS_FFF
|| rs
== NS_HHH
)
19461 do_vfp_sp_dyadic ();
19463 /* ARMv8.2 fp16 instruction. */
19465 do_scalar_fp16_v82_encode ();
19468 do_vfp_dp_rd_rn_rm ();
19471 inst
.instruction
|= 0x100;
19473 inst
.instruction
|= 0xf0000000;
19479 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19481 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
19482 first_error (_("invalid instruction shape"));
19488 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19490 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
19493 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19496 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
19500 do_vrint_1 (enum neon_cvt_mode mode
)
19502 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
19503 struct neon_type_el et
;
19508 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19509 D register operands. */
19510 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19511 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19514 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
19516 if (et
.type
!= NT_invtype
)
19518 /* VFP encodings. */
19519 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19520 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
19521 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19523 NEON_ENCODE (FPV8
, inst
);
19524 if (rs
== NS_FF
|| rs
== NS_HH
)
19525 do_vfp_sp_monadic ();
19527 do_vfp_dp_rd_rm ();
19531 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
19532 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
19533 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
19534 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
19535 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
19536 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
19537 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
19541 inst
.instruction
|= (rs
== NS_DD
) << 8;
19542 do_vfp_cond_or_thumb ();
19544 /* ARMv8.2 fp16 vrint instruction. */
19546 do_scalar_fp16_v82_encode ();
19550 /* Neon encodings (or something broken...). */
19552 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
19554 if (et
.type
== NT_invtype
)
19557 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19558 NEON_ENCODE (FLOAT
, inst
);
19560 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19563 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19564 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19565 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19566 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19567 inst
.instruction
|= neon_quad (rs
) << 6;
19568 /* Mask off the original size bits and reencode them. */
19569 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
19570 | neon_logbits (et
.size
) << 18);
19574 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
19575 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
19576 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
19577 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
19578 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
19579 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
19580 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
19585 inst
.instruction
|= 0xfc000000;
19587 inst
.instruction
|= 0xf0000000;
19594 do_vrint_1 (neon_cvt_mode_x
);
19600 do_vrint_1 (neon_cvt_mode_z
);
19606 do_vrint_1 (neon_cvt_mode_r
);
19612 do_vrint_1 (neon_cvt_mode_a
);
19618 do_vrint_1 (neon_cvt_mode_n
);
19624 do_vrint_1 (neon_cvt_mode_p
);
19630 do_vrint_1 (neon_cvt_mode_m
);
19634 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
19636 unsigned regno
= NEON_SCALAR_REG (opnd
);
19637 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
19639 if (elsize
== 16 && elno
< 2 && regno
< 16)
19640 return regno
| (elno
<< 4);
19641 else if (elsize
== 32 && elno
== 0)
19644 first_error (_("scalar out of range"));
19651 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19653 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19654 _("expression too complex"));
19655 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19656 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
19657 _("immediate out of range"));
19659 if (inst
.operands
[2].isscalar
)
19661 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
19662 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19663 N_KEY
| N_F16
| N_F32
).size
;
19664 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
19666 inst
.instruction
= 0xfe000800;
19667 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19668 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19669 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19670 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19671 inst
.instruction
|= LOW4 (m
);
19672 inst
.instruction
|= HI1 (m
) << 5;
19673 inst
.instruction
|= neon_quad (rs
) << 6;
19674 inst
.instruction
|= rot
<< 20;
19675 inst
.instruction
|= (size
== 32) << 23;
19679 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19680 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19681 N_KEY
| N_F16
| N_F32
).size
;
19682 neon_three_same (neon_quad (rs
), 0, -1);
19683 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19684 inst
.instruction
|= 0xfc200800;
19685 inst
.instruction
|= rot
<< 23;
19686 inst
.instruction
|= (size
== 32) << 20;
19693 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19695 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19696 _("expression too complex"));
19697 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19698 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
19699 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19700 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19701 N_KEY
| N_F16
| N_F32
).size
;
19702 neon_three_same (neon_quad (rs
), 0, -1);
19703 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19704 inst
.instruction
|= 0xfc800800;
19705 inst
.instruction
|= (rot
== 270) << 24;
19706 inst
.instruction
|= (size
== 32) << 20;
19709 /* Dot Product instructions encoding support. */
19712 do_neon_dotproduct (int unsigned_p
)
19714 enum neon_shape rs
;
19715 unsigned scalar_oprd2
= 0;
19718 if (inst
.cond
!= COND_ALWAYS
)
19719 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
19720 "is UNPREDICTABLE"));
19722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19725 /* Dot Product instructions are in three-same D/Q register format or the third
19726 operand can be a scalar index register. */
19727 if (inst
.operands
[2].isscalar
)
19729 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
19730 high8
= 0xfe000000;
19731 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
19735 high8
= 0xfc000000;
19736 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
19740 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
19742 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
19744 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
19745 Product instruction, so we pass 0 as the "ubit" parameter. And the
19746 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
19747 neon_three_same (neon_quad (rs
), 0, 32);
19749 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
19750 different NEON three-same encoding. */
19751 inst
.instruction
&= 0x00ffffff;
19752 inst
.instruction
|= high8
;
19753 /* Encode 'U' bit which indicates signedness. */
19754 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
19755 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
19756 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
19757 the instruction encoding. */
19758 if (inst
.operands
[2].isscalar
)
19760 inst
.instruction
&= 0xffffffd0;
19761 inst
.instruction
|= LOW4 (scalar_oprd2
);
19762 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
19766 /* Dot Product instructions for signed integer. */
19769 do_neon_dotproduct_s (void)
19771 return do_neon_dotproduct (0);
19774 /* Dot Product instructions for unsigned integer. */
19777 do_neon_dotproduct_u (void)
19779 return do_neon_dotproduct (1);
19782 /* Crypto v1 instructions. */
19784 do_crypto_2op_1 (unsigned elttype
, int op
)
19786 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19788 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
19794 NEON_ENCODE (INTEGER
, inst
);
19795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19800 inst
.instruction
|= op
<< 6;
19803 inst
.instruction
|= 0xfc000000;
19805 inst
.instruction
|= 0xf0000000;
19809 do_crypto_3op_1 (int u
, int op
)
19811 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19813 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
19814 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
19819 NEON_ENCODE (INTEGER
, inst
);
19820 neon_three_same (1, u
, 8 << op
);
19826 do_crypto_2op_1 (N_8
, 0);
19832 do_crypto_2op_1 (N_8
, 1);
19838 do_crypto_2op_1 (N_8
, 2);
19844 do_crypto_2op_1 (N_8
, 3);
19850 do_crypto_3op_1 (0, 0);
19856 do_crypto_3op_1 (0, 1);
19862 do_crypto_3op_1 (0, 2);
19868 do_crypto_3op_1 (0, 3);
19874 do_crypto_3op_1 (1, 0);
19880 do_crypto_3op_1 (1, 1);
19884 do_sha256su1 (void)
19886 do_crypto_3op_1 (1, 2);
19892 do_crypto_2op_1 (N_32
, -1);
19898 do_crypto_2op_1 (N_32
, 0);
19902 do_sha256su0 (void)
19904 do_crypto_2op_1 (N_32
, 1);
19908 do_crc32_1 (unsigned int poly
, unsigned int sz
)
19910 unsigned int Rd
= inst
.operands
[0].reg
;
19911 unsigned int Rn
= inst
.operands
[1].reg
;
19912 unsigned int Rm
= inst
.operands
[2].reg
;
19914 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19915 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
19916 inst
.instruction
|= LOW4 (Rn
) << 16;
19917 inst
.instruction
|= LOW4 (Rm
);
19918 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
19919 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
19921 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
19922 as_warn (UNPRED_REG ("r15"));
19964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19966 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
19967 do_vfp_sp_dp_cvt ();
19968 do_vfp_cond_or_thumb ();
19972 /* Overall per-instruction processing. */
19974 /* We need to be able to fix up arbitrary expressions in some statements.
19975 This is so that we can handle symbols that are an arbitrary distance from
19976 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
19977 which returns part of an address in a form which will be valid for
19978 a data instruction. We do this by pushing the expression into a symbol
19979 in the expr_section, and creating a fix for that. */
19982 fix_new_arm (fragS
* frag
,
19996 /* Create an absolute valued symbol, so we have something to
19997 refer to in the object file. Unfortunately for us, gas's
19998 generic expression parsing will already have folded out
19999 any use of .set foo/.type foo %function that may have
20000 been used to set type information of the target location,
20001 that's being specified symbolically. We have to presume
20002 the user knows what they are doing. */
20006 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
20008 symbol
= symbol_find_or_make (name
);
20009 S_SET_SEGMENT (symbol
, absolute_section
);
20010 symbol_set_frag (symbol
, &zero_address_frag
);
20011 S_SET_VALUE (symbol
, exp
->X_add_number
);
20012 exp
->X_op
= O_symbol
;
20013 exp
->X_add_symbol
= symbol
;
20014 exp
->X_add_number
= 0;
20020 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
20021 (enum bfd_reloc_code_real
) reloc
);
20025 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
20026 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
20030 /* Mark whether the fix is to a THUMB instruction, or an ARM
20032 new_fix
->tc_fix_data
= thumb_mode
;
20035 /* Create a frg for an instruction requiring relaxation. */
20037 output_relax_insn (void)
20043 /* The size of the instruction is unknown, so tie the debug info to the
20044 start of the instruction. */
20045 dwarf2_emit_insn (0);
20047 switch (inst
.relocs
[0].exp
.X_op
)
20050 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
20051 offset
= inst
.relocs
[0].exp
.X_add_number
;
20055 offset
= inst
.relocs
[0].exp
.X_add_number
;
20058 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
20062 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
20063 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
20064 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
20067 /* Write a 32-bit thumb instruction to buf. */
20069 put_thumb32_insn (char * buf
, unsigned long insn
)
20071 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
20072 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
20076 output_inst (const char * str
)
20082 as_bad ("%s -- `%s'", inst
.error
, str
);
20087 output_relax_insn ();
20090 if (inst
.size
== 0)
20093 to
= frag_more (inst
.size
);
20094 /* PR 9814: Record the thumb mode into the current frag so that we know
20095 what type of NOP padding to use, if necessary. We override any previous
20096 setting so that if the mode has changed then the NOPS that we use will
20097 match the encoding of the last instruction in the frag. */
20098 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20100 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
20102 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
20103 put_thumb32_insn (to
, inst
.instruction
);
20105 else if (inst
.size
> INSN_SIZE
)
20107 gas_assert (inst
.size
== (2 * INSN_SIZE
));
20108 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
20109 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
20112 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
20115 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20117 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
20118 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
20119 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
20120 inst
.relocs
[r
].type
);
20123 dwarf2_emit_insn (inst
.size
);
20127 output_it_inst (int cond
, int mask
, char * to
)
20129 unsigned long instruction
= 0xbf00;
20132 instruction
|= mask
;
20133 instruction
|= cond
<< 4;
20137 to
= frag_more (2);
20139 dwarf2_emit_insn (2);
20143 md_number_to_chars (to
, instruction
, 2);
20148 /* Tag values used in struct asm_opcode's tag field. */
20151 OT_unconditional
, /* Instruction cannot be conditionalized.
20152 The ARM condition field is still 0xE. */
20153 OT_unconditionalF
, /* Instruction cannot be conditionalized
20154 and carries 0xF in its ARM condition field. */
20155 OT_csuffix
, /* Instruction takes a conditional suffix. */
20156 OT_csuffixF
, /* Some forms of the instruction take a scalar
20157 conditional suffix, others place 0xF where the
20158 condition field would be, others take a vector
20159 conditional suffix. */
20160 OT_cinfix3
, /* Instruction takes a conditional infix,
20161 beginning at character index 3. (In
20162 unified mode, it becomes a suffix.) */
20163 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
20164 tsts, cmps, cmns, and teqs. */
20165 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
20166 character index 3, even in unified mode. Used for
20167 legacy instructions where suffix and infix forms
20168 may be ambiguous. */
20169 OT_csuf_or_in3
, /* Instruction takes either a conditional
20170 suffix or an infix at character index 3. */
20171 OT_odd_infix_unc
, /* This is the unconditional variant of an
20172 instruction that takes a conditional infix
20173 at an unusual position. In unified mode,
20174 this variant will accept a suffix. */
20175 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
20176 are the conditional variants of instructions that
20177 take conditional infixes in unusual positions.
20178 The infix appears at character index
20179 (tag - OT_odd_infix_0). These are not accepted
20180 in unified mode. */
20183 /* Subroutine of md_assemble, responsible for looking up the primary
20184 opcode from the mnemonic the user wrote. STR points to the
20185 beginning of the mnemonic.
20187 This is not simply a hash table lookup, because of conditional
20188 variants. Most instructions have conditional variants, which are
20189 expressed with a _conditional affix_ to the mnemonic. If we were
20190 to encode each conditional variant as a literal string in the opcode
20191 table, it would have approximately 20,000 entries.
20193 Most mnemonics take this affix as a suffix, and in unified syntax,
20194 'most' is upgraded to 'all'. However, in the divided syntax, some
20195 instructions take the affix as an infix, notably the s-variants of
20196 the arithmetic instructions. Of those instructions, all but six
20197 have the infix appear after the third character of the mnemonic.
20199 Accordingly, the algorithm for looking up primary opcodes given
20202 1. Look up the identifier in the opcode table.
20203 If we find a match, go to step U.
20205 2. Look up the last two characters of the identifier in the
20206 conditions table. If we find a match, look up the first N-2
20207 characters of the identifier in the opcode table. If we
20208 find a match, go to step CE.
20210 3. Look up the fourth and fifth characters of the identifier in
20211 the conditions table. If we find a match, extract those
20212 characters from the identifier, and look up the remaining
20213 characters in the opcode table. If we find a match, go
20218 U. Examine the tag field of the opcode structure, in case this is
20219 one of the six instructions with its conditional infix in an
20220 unusual place. If it is, the tag tells us where to find the
20221 infix; look it up in the conditions table and set inst.cond
20222 accordingly. Otherwise, this is an unconditional instruction.
20223 Again set inst.cond accordingly. Return the opcode structure.
20225 CE. Examine the tag field to make sure this is an instruction that
20226 should receive a conditional suffix. If it is not, fail.
20227 Otherwise, set inst.cond from the suffix we already looked up,
20228 and return the opcode structure.
20230 CM. Examine the tag field to make sure this is an instruction that
20231 should receive a conditional infix after the third character.
20232 If it is not, fail. Otherwise, undo the edits to the current
20233 line of input and proceed as for case CE. */
20235 static const struct asm_opcode
*
20236 opcode_lookup (char **str
)
20240 const struct asm_opcode
*opcode
;
20241 const struct asm_cond
*cond
;
20244 /* Scan up to the end of the mnemonic, which must end in white space,
20245 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20246 for (base
= end
= *str
; *end
!= '\0'; end
++)
20247 if (*end
== ' ' || *end
== '.')
20253 /* Handle a possible width suffix and/or Neon type suffix. */
20258 /* The .w and .n suffixes are only valid if the unified syntax is in
20260 if (unified_syntax
&& end
[1] == 'w')
20262 else if (unified_syntax
&& end
[1] == 'n')
20267 inst
.vectype
.elems
= 0;
20269 *str
= end
+ offset
;
20271 if (end
[offset
] == '.')
20273 /* See if we have a Neon type suffix (possible in either unified or
20274 non-unified ARM syntax mode). */
20275 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
20278 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
20284 /* Look for unaffixed or special-case affixed mnemonic. */
20285 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20290 if (opcode
->tag
< OT_odd_infix_0
)
20292 inst
.cond
= COND_ALWAYS
;
20296 if (warn_on_deprecated
&& unified_syntax
)
20297 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20298 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
20299 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20302 inst
.cond
= cond
->value
;
20305 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20307 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20309 if (end
- base
< 2)
20312 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
20313 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20315 /* If this opcode can not be vector predicated then don't accept it with a
20316 vector predication code. */
20317 if (opcode
&& !opcode
->mayBeVecPred
)
20320 if (!opcode
|| !cond
)
20322 /* Cannot have a conditional suffix on a mnemonic of less than two
20324 if (end
- base
< 3)
20327 /* Look for suffixed mnemonic. */
20329 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20330 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20334 if (opcode
&& cond
)
20337 switch (opcode
->tag
)
20339 case OT_cinfix3_legacy
:
20340 /* Ignore conditional suffixes matched on infix only mnemonics. */
20344 case OT_cinfix3_deprecated
:
20345 case OT_odd_infix_unc
:
20346 if (!unified_syntax
)
20348 /* Fall through. */
20352 case OT_csuf_or_in3
:
20353 inst
.cond
= cond
->value
;
20356 case OT_unconditional
:
20357 case OT_unconditionalF
:
20359 inst
.cond
= cond
->value
;
20362 /* Delayed diagnostic. */
20363 inst
.error
= BAD_COND
;
20364 inst
.cond
= COND_ALWAYS
;
20373 /* Cannot have a usual-position infix on a mnemonic of less than
20374 six characters (five would be a suffix). */
20375 if (end
- base
< 6)
20378 /* Look for infixed mnemonic in the usual position. */
20380 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20384 memcpy (save
, affix
, 2);
20385 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
20386 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20388 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
20389 memcpy (affix
, save
, 2);
20392 && (opcode
->tag
== OT_cinfix3
20393 || opcode
->tag
== OT_cinfix3_deprecated
20394 || opcode
->tag
== OT_csuf_or_in3
20395 || opcode
->tag
== OT_cinfix3_legacy
))
20398 if (warn_on_deprecated
&& unified_syntax
20399 && (opcode
->tag
== OT_cinfix3
20400 || opcode
->tag
== OT_cinfix3_deprecated
))
20401 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20403 inst
.cond
= cond
->value
;
20410 /* This function generates an initial IT instruction, leaving its block
20411 virtually open for the new instructions. Eventually,
20412 the mask will be updated by now_pred_add_mask () each time
20413 a new instruction needs to be included in the IT block.
20414 Finally, the block is closed with close_automatic_it_block ().
20415 The block closure can be requested either from md_assemble (),
20416 a tencode (), or due to a label hook. */
20419 new_automatic_it_block (int cond
)
20421 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
20422 now_pred
.mask
= 0x18;
20423 now_pred
.cc
= cond
;
20424 now_pred
.block_length
= 1;
20425 mapping_state (MAP_THUMB
);
20426 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
20427 now_pred
.warn_deprecated
= FALSE
;
20428 now_pred
.insn_cond
= TRUE
;
20431 /* Close an automatic IT block.
20432 See comments in new_automatic_it_block (). */
20435 close_automatic_it_block (void)
20437 now_pred
.mask
= 0x10;
20438 now_pred
.block_length
= 0;
20441 /* Update the mask of the current automatically-generated IT
20442 instruction. See comments in new_automatic_it_block (). */
20445 now_pred_add_mask (int cond
)
20447 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20448 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20449 | ((bitvalue) << (nbit)))
20450 const int resulting_bit
= (cond
& 1);
20452 now_pred
.mask
&= 0xf;
20453 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20455 (5 - now_pred
.block_length
));
20456 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20458 ((5 - now_pred
.block_length
) - 1));
20459 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
20462 #undef SET_BIT_VALUE
20465 /* The IT blocks handling machinery is accessed through the these functions:
20466 it_fsm_pre_encode () from md_assemble ()
20467 set_pred_insn_type () optional, from the tencode functions
20468 set_pred_insn_type_last () ditto
20469 in_pred_block () ditto
20470 it_fsm_post_encode () from md_assemble ()
20471 force_automatic_it_block_close () from label handling functions
20474 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20475 initializing the IT insn type with a generic initial value depending
20476 on the inst.condition.
20477 2) During the tencode function, two things may happen:
20478 a) The tencode function overrides the IT insn type by
20479 calling either set_pred_insn_type (type) or
20480 set_pred_insn_type_last ().
20481 b) The tencode function queries the IT block state by
20482 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20484 Both set_pred_insn_type and in_pred_block run the internal FSM state
20485 handling function (handle_pred_state), because: a) setting the IT insn
20486 type may incur in an invalid state (exiting the function),
20487 and b) querying the state requires the FSM to be updated.
20488 Specifically we want to avoid creating an IT block for conditional
20489 branches, so it_fsm_pre_encode is actually a guess and we can't
20490 determine whether an IT block is required until the tencode () routine
20491 has decided what type of instruction this actually it.
20492 Because of this, if set_pred_insn_type and in_pred_block have to be
20493 used, set_pred_insn_type has to be called first.
20495 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
20496 that determines the insn IT type depending on the inst.cond code.
20497 When a tencode () routine encodes an instruction that can be
20498 either outside an IT block, or, in the case of being inside, has to be
20499 the last one, set_pred_insn_type_last () will determine the proper
20500 IT instruction type based on the inst.cond code. Otherwise,
20501 set_pred_insn_type can be called for overriding that logic or
20502 for covering other cases.
20504 Calling handle_pred_state () may not transition the IT block state to
20505 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
20506 still queried. Instead, if the FSM determines that the state should
20507 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
20508 after the tencode () function: that's what it_fsm_post_encode () does.
20510 Since in_pred_block () calls the state handling function to get an
20511 updated state, an error may occur (due to invalid insns combination).
20512 In that case, inst.error is set.
20513 Therefore, inst.error has to be checked after the execution of
20514 the tencode () routine.
20516 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
20517 any pending state change (if any) that didn't take place in
20518 handle_pred_state () as explained above. */
20521 it_fsm_pre_encode (void)
20523 if (inst
.cond
!= COND_ALWAYS
)
20524 inst
.pred_insn_type
= INSIDE_IT_INSN
;
20526 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
20528 now_pred
.state_handled
= 0;
20531 /* IT state FSM handling function. */
20532 /* MVE instructions and non-MVE instructions are handled differently because of
20533 the introduction of VPT blocks.
20534 Specifications say that any non-MVE instruction inside a VPT block is
20535 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
20536 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
20537 few exceptions we have MVE_UNPREDICABLE_INSN.
20538 The error messages provided depending on the different combinations possible
20539 are described in the cases below:
20540 For 'most' MVE instructions:
20541 1) In an IT block, with an IT code: syntax error
20542 2) In an IT block, with a VPT code: error: must be in a VPT block
20543 3) In an IT block, with no code: warning: UNPREDICTABLE
20544 4) In a VPT block, with an IT code: syntax error
20545 5) In a VPT block, with a VPT code: OK!
20546 6) In a VPT block, with no code: error: missing code
20547 7) Outside a pred block, with an IT code: error: syntax error
20548 8) Outside a pred block, with a VPT code: error: should be in a VPT block
20549 9) Outside a pred block, with no code: OK!
20550 For non-MVE instructions:
20551 10) In an IT block, with an IT code: OK!
20552 11) In an IT block, with a VPT code: syntax error
20553 12) In an IT block, with no code: error: missing code
20554 13) In a VPT block, with an IT code: error: should be in an IT block
20555 14) In a VPT block, with a VPT code: syntax error
20556 15) In a VPT block, with no code: UNPREDICTABLE
20557 16) Outside a pred block, with an IT code: error: should be in an IT block
20558 17) Outside a pred block, with a VPT code: syntax error
20559 18) Outside a pred block, with no code: OK!
20564 handle_pred_state (void)
20566 now_pred
.state_handled
= 1;
20567 now_pred
.insn_cond
= FALSE
;
20569 switch (now_pred
.state
)
20571 case OUTSIDE_PRED_BLOCK
:
20572 switch (inst
.pred_insn_type
)
20574 case MVE_UNPREDICABLE_INSN
:
20575 case MVE_OUTSIDE_PRED_INSN
:
20576 if (inst
.cond
< COND_ALWAYS
)
20578 /* Case 7: Outside a pred block, with an IT code: error: syntax
20580 inst
.error
= BAD_SYNTAX
;
20583 /* Case 9: Outside a pred block, with no code: OK! */
20585 case OUTSIDE_PRED_INSN
:
20586 if (inst
.cond
> COND_ALWAYS
)
20588 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20590 inst
.error
= BAD_SYNTAX
;
20593 /* Case 18: Outside a pred block, with no code: OK! */
20596 case INSIDE_VPT_INSN
:
20597 /* Case 8: Outside a pred block, with a VPT code: error: should be in
20599 inst
.error
= BAD_OUT_VPT
;
20602 case INSIDE_IT_INSN
:
20603 case INSIDE_IT_LAST_INSN
:
20604 if (inst
.cond
< COND_ALWAYS
)
20606 /* Case 16: Outside a pred block, with an IT code: error: should
20607 be in an IT block. */
20608 if (thumb_mode
== 0)
20611 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
20612 as_tsktsk (_("Warning: conditional outside an IT block"\
20617 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
20618 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
20620 /* Automatically generate the IT instruction. */
20621 new_automatic_it_block (inst
.cond
);
20622 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
20623 close_automatic_it_block ();
20627 inst
.error
= BAD_OUT_IT
;
20633 else if (inst
.cond
> COND_ALWAYS
)
20635 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20637 inst
.error
= BAD_SYNTAX
;
20642 case IF_INSIDE_IT_LAST_INSN
:
20643 case NEUTRAL_IT_INSN
:
20647 if (inst
.cond
!= COND_ALWAYS
)
20648 first_error (BAD_SYNTAX
);
20649 now_pred
.state
= MANUAL_PRED_BLOCK
;
20650 now_pred
.block_length
= 0;
20651 now_pred
.type
= VECTOR_PRED
;
20655 now_pred
.state
= MANUAL_PRED_BLOCK
;
20656 now_pred
.block_length
= 0;
20657 now_pred
.type
= SCALAR_PRED
;
20662 case AUTOMATIC_PRED_BLOCK
:
20663 /* Three things may happen now:
20664 a) We should increment current it block size;
20665 b) We should close current it block (closing insn or 4 insns);
20666 c) We should close current it block and start a new one (due
20667 to incompatible conditions or
20668 4 insns-length block reached). */
20670 switch (inst
.pred_insn_type
)
20672 case INSIDE_VPT_INSN
:
20674 case MVE_UNPREDICABLE_INSN
:
20675 case MVE_OUTSIDE_PRED_INSN
:
20677 case OUTSIDE_PRED_INSN
:
20678 /* The closure of the block shall happen immediately,
20679 so any in_pred_block () call reports the block as closed. */
20680 force_automatic_it_block_close ();
20683 case INSIDE_IT_INSN
:
20684 case INSIDE_IT_LAST_INSN
:
20685 case IF_INSIDE_IT_LAST_INSN
:
20686 now_pred
.block_length
++;
20688 if (now_pred
.block_length
> 4
20689 || !now_pred_compatible (inst
.cond
))
20691 force_automatic_it_block_close ();
20692 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
20693 new_automatic_it_block (inst
.cond
);
20697 now_pred
.insn_cond
= TRUE
;
20698 now_pred_add_mask (inst
.cond
);
20701 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
20702 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
20703 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
20704 close_automatic_it_block ();
20707 case NEUTRAL_IT_INSN
:
20708 now_pred
.block_length
++;
20709 now_pred
.insn_cond
= TRUE
;
20711 if (now_pred
.block_length
> 4)
20712 force_automatic_it_block_close ();
20714 now_pred_add_mask (now_pred
.cc
& 1);
20718 close_automatic_it_block ();
20719 now_pred
.state
= MANUAL_PRED_BLOCK
;
20724 case MANUAL_PRED_BLOCK
:
20727 if (now_pred
.type
== SCALAR_PRED
)
20729 /* Check conditional suffixes. */
20730 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
20731 now_pred
.mask
<<= 1;
20732 now_pred
.mask
&= 0x1f;
20733 is_last
= (now_pred
.mask
== 0x10);
20737 now_pred
.cc
^= (now_pred
.mask
>> 4);
20738 cond
= now_pred
.cc
+ 0xf;
20739 now_pred
.mask
<<= 1;
20740 now_pred
.mask
&= 0x1f;
20741 is_last
= now_pred
.mask
== 0x10;
20743 now_pred
.insn_cond
= TRUE
;
20745 switch (inst
.pred_insn_type
)
20747 case OUTSIDE_PRED_INSN
:
20748 if (now_pred
.type
== SCALAR_PRED
)
20750 if (inst
.cond
== COND_ALWAYS
)
20752 /* Case 12: In an IT block, with no code: error: missing
20754 inst
.error
= BAD_NOT_IT
;
20757 else if (inst
.cond
> COND_ALWAYS
)
20759 /* Case 11: In an IT block, with a VPT code: syntax error.
20761 inst
.error
= BAD_SYNTAX
;
20764 else if (thumb_mode
)
20766 /* This is for some special cases where a non-MVE
20767 instruction is not allowed in an IT block, such as cbz,
20768 but are put into one with a condition code.
20769 You could argue this should be a syntax error, but we
20770 gave the 'not allowed in IT block' diagnostic in the
20771 past so we will keep doing so. */
20772 inst
.error
= BAD_NOT_IT
;
20779 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
20780 as_tsktsk (MVE_NOT_VPT
);
20783 case MVE_OUTSIDE_PRED_INSN
:
20784 if (now_pred
.type
== SCALAR_PRED
)
20786 if (inst
.cond
== COND_ALWAYS
)
20788 /* Case 3: In an IT block, with no code: warning:
20790 as_tsktsk (MVE_NOT_IT
);
20793 else if (inst
.cond
< COND_ALWAYS
)
20795 /* Case 1: In an IT block, with an IT code: syntax error.
20797 inst
.error
= BAD_SYNTAX
;
20805 if (inst
.cond
< COND_ALWAYS
)
20807 /* Case 4: In a VPT block, with an IT code: syntax error.
20809 inst
.error
= BAD_SYNTAX
;
20812 else if (inst
.cond
== COND_ALWAYS
)
20814 /* Case 6: In a VPT block, with no code: error: missing
20816 inst
.error
= BAD_NOT_VPT
;
20824 case MVE_UNPREDICABLE_INSN
:
20825 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
20827 case INSIDE_IT_INSN
:
20828 if (inst
.cond
> COND_ALWAYS
)
20830 /* Case 11: In an IT block, with a VPT code: syntax error. */
20831 /* Case 14: In a VPT block, with a VPT code: syntax error. */
20832 inst
.error
= BAD_SYNTAX
;
20835 else if (now_pred
.type
== SCALAR_PRED
)
20837 /* Case 10: In an IT block, with an IT code: OK! */
20838 if (cond
!= inst
.cond
)
20840 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
20847 /* Case 13: In a VPT block, with an IT code: error: should be
20849 inst
.error
= BAD_OUT_IT
;
20854 case INSIDE_VPT_INSN
:
20855 if (now_pred
.type
== SCALAR_PRED
)
20857 /* Case 2: In an IT block, with a VPT code: error: must be in a
20859 inst
.error
= BAD_OUT_VPT
;
20862 /* Case 5: In a VPT block, with a VPT code: OK! */
20863 else if (cond
!= inst
.cond
)
20865 inst
.error
= BAD_VPT_COND
;
20869 case INSIDE_IT_LAST_INSN
:
20870 case IF_INSIDE_IT_LAST_INSN
:
20871 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
20873 /* Case 4: In a VPT block, with an IT code: syntax error. */
20874 /* Case 11: In an IT block, with a VPT code: syntax error. */
20875 inst
.error
= BAD_SYNTAX
;
20878 else if (cond
!= inst
.cond
)
20880 inst
.error
= BAD_IT_COND
;
20885 inst
.error
= BAD_BRANCH
;
20890 case NEUTRAL_IT_INSN
:
20891 /* The BKPT instruction is unconditional even in a IT or VPT
20896 if (now_pred
.type
== SCALAR_PRED
)
20898 inst
.error
= BAD_IT_IT
;
20901 /* fall through. */
20903 if (inst
.cond
== COND_ALWAYS
)
20905 /* Executing a VPT/VPST instruction inside an IT block or a
20906 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
20908 if (now_pred
.type
== SCALAR_PRED
)
20909 as_tsktsk (MVE_NOT_IT
);
20911 as_tsktsk (MVE_NOT_VPT
);
20916 /* VPT/VPST do not accept condition codes. */
20917 inst
.error
= BAD_SYNTAX
;
20928 struct depr_insn_mask
20930 unsigned long pattern
;
20931 unsigned long mask
;
20932 const char* description
;
20935 /* List of 16-bit instruction patterns deprecated in an IT block in
20937 static const struct depr_insn_mask depr_it_insns
[] = {
20938 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
20939 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
20940 { 0xa000, 0xb800, N_("ADR") },
20941 { 0x4800, 0xf800, N_("Literal loads") },
20942 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
20943 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
20944 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
20945 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
20946 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
20951 it_fsm_post_encode (void)
20955 if (!now_pred
.state_handled
)
20956 handle_pred_state ();
20958 if (now_pred
.insn_cond
20959 && !now_pred
.warn_deprecated
20960 && warn_on_deprecated
20961 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
20962 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
20964 if (inst
.instruction
>= 0x10000)
20966 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
20967 "performance deprecated in ARMv8-A and ARMv8-R"));
20968 now_pred
.warn_deprecated
= TRUE
;
20972 const struct depr_insn_mask
*p
= depr_it_insns
;
20974 while (p
->mask
!= 0)
20976 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
20978 as_tsktsk (_("IT blocks containing 16-bit Thumb "
20979 "instructions of the following class are "
20980 "performance deprecated in ARMv8-A and "
20981 "ARMv8-R: %s"), p
->description
);
20982 now_pred
.warn_deprecated
= TRUE
;
20990 if (now_pred
.block_length
> 1)
20992 as_tsktsk (_("IT blocks containing more than one conditional "
20993 "instruction are performance deprecated in ARMv8-A and "
20995 now_pred
.warn_deprecated
= TRUE
;
20999 is_last
= (now_pred
.mask
== 0x10);
21002 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21008 force_automatic_it_block_close (void)
21010 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
21012 close_automatic_it_block ();
21013 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21019 in_pred_block (void)
21021 if (!now_pred
.state_handled
)
21022 handle_pred_state ();
21024 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
21027 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21028 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21029 here, hence the "known" in the function name. */
21032 known_t32_only_insn (const struct asm_opcode
*opcode
)
21034 /* Original Thumb-1 wide instruction. */
21035 if (opcode
->tencode
== do_t_blx
21036 || opcode
->tencode
== do_t_branch23
21037 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
21038 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
21041 /* Wide-only instruction added to ARMv8-M Baseline. */
21042 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
21043 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
21044 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
21045 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
21051 /* Whether wide instruction variant can be used if available for a valid OPCODE
21055 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
21057 if (known_t32_only_insn (opcode
))
21060 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21061 of variant T3 of B.W is checked in do_t_branch. */
21062 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21063 && opcode
->tencode
== do_t_branch
)
21066 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21067 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21068 && opcode
->tencode
== do_t_mov_cmp
21069 /* Make sure CMP instruction is not affected. */
21070 && opcode
->aencode
== do_mov
)
21073 /* Wide instruction variants of all instructions with narrow *and* wide
21074 variants become available with ARMv6t2. Other opcodes are either
21075 narrow-only or wide-only and are thus available if OPCODE is valid. */
21076 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
21079 /* OPCODE with narrow only instruction variant or wide variant not
21085 md_assemble (char *str
)
21088 const struct asm_opcode
* opcode
;
21090 /* Align the previous label if needed. */
21091 if (last_label_seen
!= NULL
)
21093 symbol_set_frag (last_label_seen
, frag_now
);
21094 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
21095 S_SET_SEGMENT (last_label_seen
, now_seg
);
21098 memset (&inst
, '\0', sizeof (inst
));
21100 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21101 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
21103 opcode
= opcode_lookup (&p
);
21106 /* It wasn't an instruction, but it might be a register alias of
21107 the form alias .req reg, or a Neon .dn/.qn directive. */
21108 if (! create_register_alias (str
, p
)
21109 && ! create_neon_reg_alias (str
, p
))
21110 as_bad (_("bad instruction `%s'"), str
);
21115 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
21116 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21118 /* The value which unconditional instructions should have in place of the
21119 condition field. */
21120 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
21124 arm_feature_set variant
;
21126 variant
= cpu_variant
;
21127 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21128 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
21129 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
21130 /* Check that this instruction is supported for this CPU. */
21131 if (!opcode
->tvariant
21132 || (thumb_mode
== 1
21133 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
21135 if (opcode
->tencode
== do_t_swi
)
21136 as_bad (_("SVC is not permitted on this architecture"));
21138 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
21141 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
21142 && opcode
->tencode
!= do_t_branch
)
21144 as_bad (_("Thumb does not support conditional execution"));
21148 /* Two things are addressed here:
21149 1) Implicit require narrow instructions on Thumb-1.
21150 This avoids relaxation accidentally introducing Thumb-2
21152 2) Reject wide instructions in non Thumb-2 cores.
21154 Only instructions with narrow and wide variants need to be handled
21155 but selecting all non wide-only instructions is easier. */
21156 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
21157 && !t32_insn_ok (variant
, opcode
))
21159 if (inst
.size_req
== 0)
21161 else if (inst
.size_req
== 4)
21163 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
21164 as_bad (_("selected processor does not support 32bit wide "
21165 "variant of instruction `%s'"), str
);
21167 as_bad (_("selected processor does not support `%s' in "
21168 "Thumb-2 mode"), str
);
21173 inst
.instruction
= opcode
->tvalue
;
21175 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
21177 /* Prepare the pred_insn_type for those encodings that don't set
21179 it_fsm_pre_encode ();
21181 opcode
->tencode ();
21183 it_fsm_post_encode ();
21186 if (!(inst
.error
|| inst
.relax
))
21188 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
21189 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
21190 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
21192 as_bad (_("cannot honor width suffix -- `%s'"), str
);
21197 /* Something has gone badly wrong if we try to relax a fixed size
21199 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
21201 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21202 *opcode
->tvariant
);
21203 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21204 set those bits when Thumb-2 32-bit instructions are seen. The impact
21205 of relaxable instructions will be considered later after we finish all
21207 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
21208 variant
= arm_arch_none
;
21210 variant
= cpu_variant
;
21211 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
21212 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21215 check_neon_suffixes
;
21219 mapping_state (MAP_THUMB
);
21222 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21226 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21227 is_bx
= (opcode
->aencode
== do_bx
);
21229 /* Check that this instruction is supported for this CPU. */
21230 if (!(is_bx
&& fix_v4bx
)
21231 && !(opcode
->avariant
&&
21232 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
21234 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
21239 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
21243 inst
.instruction
= opcode
->avalue
;
21244 if (opcode
->tag
== OT_unconditionalF
)
21245 inst
.instruction
|= 0xFU
<< 28;
21247 inst
.instruction
|= inst
.cond
<< 28;
21248 inst
.size
= INSN_SIZE
;
21249 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
21251 it_fsm_pre_encode ();
21252 opcode
->aencode ();
21253 it_fsm_post_encode ();
21255 /* Arm mode bx is marked as both v4T and v5 because it's still required
21256 on a hypothetical non-thumb v5 core. */
21258 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
21260 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
21261 *opcode
->avariant
);
21263 check_neon_suffixes
;
21267 mapping_state (MAP_ARM
);
21272 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21280 check_pred_blocks_finished (void)
21285 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
21286 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
21287 == MANUAL_PRED_BLOCK
)
21289 if (now_pred
.type
== SCALAR_PRED
)
21290 as_warn (_("section '%s' finished with an open IT block."),
21293 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21297 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
21299 if (now_pred
.type
== SCALAR_PRED
)
21300 as_warn (_("file finished with an open IT block."));
21302 as_warn (_("file finished with an open VPT/VPST block."));
21307 /* Various frobbings of labels and their addresses. */
21310 arm_start_line_hook (void)
21312 last_label_seen
= NULL
;
21316 arm_frob_label (symbolS
* sym
)
21318 last_label_seen
= sym
;
21320 ARM_SET_THUMB (sym
, thumb_mode
);
21322 #if defined OBJ_COFF || defined OBJ_ELF
21323 ARM_SET_INTERWORK (sym
, support_interwork
);
21326 force_automatic_it_block_close ();
21328 /* Note - do not allow local symbols (.Lxxx) to be labelled
21329 as Thumb functions. This is because these labels, whilst
21330 they exist inside Thumb code, are not the entry points for
21331 possible ARM->Thumb calls. Also, these labels can be used
21332 as part of a computed goto or switch statement. eg gcc
21333 can generate code that looks like this:
21335 ldr r2, [pc, .Laaa]
21345 The first instruction loads the address of the jump table.
21346 The second instruction converts a table index into a byte offset.
21347 The third instruction gets the jump address out of the table.
21348 The fourth instruction performs the jump.
21350 If the address stored at .Laaa is that of a symbol which has the
21351 Thumb_Func bit set, then the linker will arrange for this address
21352 to have the bottom bit set, which in turn would mean that the
21353 address computation performed by the third instruction would end
21354 up with the bottom bit set. Since the ARM is capable of unaligned
21355 word loads, the instruction would then load the incorrect address
21356 out of the jump table, and chaos would ensue. */
21357 if (label_is_thumb_function_name
21358 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21359 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21361 /* When the address of a Thumb function is taken the bottom
21362 bit of that address should be set. This will allow
21363 interworking between Arm and Thumb functions to work
21366 THUMB_SET_FUNC (sym
, 1);
21368 label_is_thumb_function_name
= FALSE
;
21371 dwarf2_emit_label (sym
);
21375 arm_data_in_code (void)
21377 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
21379 *input_line_pointer
= '/';
21380 input_line_pointer
+= 5;
21381 *input_line_pointer
= 0;
21389 arm_canonicalize_symbol_name (char * name
)
21393 if (thumb_mode
&& (len
= strlen (name
)) > 5
21394 && streq (name
+ len
- 5, "/data"))
21395 *(name
+ len
- 5) = 0;
21400 /* Table of all register names defined by default. The user can
21401 define additional names with .req. Note that all register names
21402 should appear in both upper and lowercase variants. Some registers
21403 also have mixed-case names. */
21405 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21406 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21407 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21408 #define REGSET(p,t) \
21409 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21410 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21411 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21412 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21413 #define REGSETH(p,t) \
21414 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21415 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21416 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21417 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21418 #define REGSET2(p,t) \
21419 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21420 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21421 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21422 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21423 #define SPLRBANK(base,bank,t) \
21424 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21425 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21426 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21427 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21428 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21429 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21431 static const struct reg_entry reg_names
[] =
21433 /* ARM integer registers. */
21434 REGSET(r
, RN
), REGSET(R
, RN
),
21436 /* ATPCS synonyms. */
21437 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
21438 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
21439 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
21441 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
21442 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
21443 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
21445 /* Well-known aliases. */
21446 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
21447 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
21449 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
21450 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
21452 /* Defining the new Zero register from ARMv8.1-M. */
21456 /* Coprocessor numbers. */
21457 REGSET(p
, CP
), REGSET(P
, CP
),
21459 /* Coprocessor register numbers. The "cr" variants are for backward
21461 REGSET(c
, CN
), REGSET(C
, CN
),
21462 REGSET(cr
, CN
), REGSET(CR
, CN
),
21464 /* ARM banked registers. */
21465 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
21466 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
21467 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
21468 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
21469 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
21470 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
21471 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
21473 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
21474 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
21475 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
21476 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
21477 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
21478 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
21479 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
21480 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
21482 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
21483 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
21484 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
21485 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
21486 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
21487 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
21488 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
21489 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21490 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21492 /* FPA registers. */
21493 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
21494 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
21496 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
21497 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
21499 /* VFP SP registers. */
21500 REGSET(s
,VFS
), REGSET(S
,VFS
),
21501 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
21503 /* VFP DP Registers. */
21504 REGSET(d
,VFD
), REGSET(D
,VFD
),
21505 /* Extra Neon DP registers. */
21506 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
21508 /* Neon QP registers. */
21509 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
21511 /* VFP control registers. */
21512 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
21513 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
21514 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
21515 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
21516 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
21517 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
21518 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
21520 /* Maverick DSP coprocessor registers. */
21521 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
21522 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
21524 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
21525 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
21526 REGDEF(dspsc
,0,DSPSC
),
21528 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
21529 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
21530 REGDEF(DSPSC
,0,DSPSC
),
21532 /* iWMMXt data registers - p0, c0-15. */
21533 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
21535 /* iWMMXt control registers - p1, c0-3. */
21536 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
21537 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
21538 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
21539 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
21541 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
21542 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
21543 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
21544 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
21545 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
21547 /* XScale accumulator registers. */
21548 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
21554 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
21555 within psr_required_here. */
21556 static const struct asm_psr psrs
[] =
21558 /* Backward compatibility notation. Note that "all" is no longer
21559 truly all possible PSR bits. */
21560 {"all", PSR_c
| PSR_f
},
21564 /* Individual flags. */
21570 /* Combinations of flags. */
21571 {"fs", PSR_f
| PSR_s
},
21572 {"fx", PSR_f
| PSR_x
},
21573 {"fc", PSR_f
| PSR_c
},
21574 {"sf", PSR_s
| PSR_f
},
21575 {"sx", PSR_s
| PSR_x
},
21576 {"sc", PSR_s
| PSR_c
},
21577 {"xf", PSR_x
| PSR_f
},
21578 {"xs", PSR_x
| PSR_s
},
21579 {"xc", PSR_x
| PSR_c
},
21580 {"cf", PSR_c
| PSR_f
},
21581 {"cs", PSR_c
| PSR_s
},
21582 {"cx", PSR_c
| PSR_x
},
21583 {"fsx", PSR_f
| PSR_s
| PSR_x
},
21584 {"fsc", PSR_f
| PSR_s
| PSR_c
},
21585 {"fxs", PSR_f
| PSR_x
| PSR_s
},
21586 {"fxc", PSR_f
| PSR_x
| PSR_c
},
21587 {"fcs", PSR_f
| PSR_c
| PSR_s
},
21588 {"fcx", PSR_f
| PSR_c
| PSR_x
},
21589 {"sfx", PSR_s
| PSR_f
| PSR_x
},
21590 {"sfc", PSR_s
| PSR_f
| PSR_c
},
21591 {"sxf", PSR_s
| PSR_x
| PSR_f
},
21592 {"sxc", PSR_s
| PSR_x
| PSR_c
},
21593 {"scf", PSR_s
| PSR_c
| PSR_f
},
21594 {"scx", PSR_s
| PSR_c
| PSR_x
},
21595 {"xfs", PSR_x
| PSR_f
| PSR_s
},
21596 {"xfc", PSR_x
| PSR_f
| PSR_c
},
21597 {"xsf", PSR_x
| PSR_s
| PSR_f
},
21598 {"xsc", PSR_x
| PSR_s
| PSR_c
},
21599 {"xcf", PSR_x
| PSR_c
| PSR_f
},
21600 {"xcs", PSR_x
| PSR_c
| PSR_s
},
21601 {"cfs", PSR_c
| PSR_f
| PSR_s
},
21602 {"cfx", PSR_c
| PSR_f
| PSR_x
},
21603 {"csf", PSR_c
| PSR_s
| PSR_f
},
21604 {"csx", PSR_c
| PSR_s
| PSR_x
},
21605 {"cxf", PSR_c
| PSR_x
| PSR_f
},
21606 {"cxs", PSR_c
| PSR_x
| PSR_s
},
21607 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
21608 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
21609 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
21610 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
21611 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
21612 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
21613 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
21614 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
21615 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
21616 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
21617 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
21618 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
21619 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
21620 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
21621 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
21622 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
21623 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
21624 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
21625 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
21626 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
21627 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
21628 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
21629 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
21630 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
21633 /* Table of V7M psr names. */
21634 static const struct asm_psr v7m_psrs
[] =
21636 {"apsr", 0x0 }, {"APSR", 0x0 },
21637 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
21638 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
21639 {"psr", 0x3 }, {"PSR", 0x3 },
21640 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
21641 {"ipsr", 0x5 }, {"IPSR", 0x5 },
21642 {"epsr", 0x6 }, {"EPSR", 0x6 },
21643 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
21644 {"msp", 0x8 }, {"MSP", 0x8 },
21645 {"psp", 0x9 }, {"PSP", 0x9 },
21646 {"msplim", 0xa }, {"MSPLIM", 0xa },
21647 {"psplim", 0xb }, {"PSPLIM", 0xb },
21648 {"primask", 0x10}, {"PRIMASK", 0x10},
21649 {"basepri", 0x11}, {"BASEPRI", 0x11},
21650 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
21651 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
21652 {"control", 0x14}, {"CONTROL", 0x14},
21653 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
21654 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
21655 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
21656 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
21657 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
21658 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
21659 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
21660 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
21661 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
21664 /* Table of all shift-in-operand names. */
21665 static const struct asm_shift_name shift_names
[] =
21667 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
21668 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
21669 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
21670 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
21671 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
21672 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
21673 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
21676 /* Table of all explicit relocation names. */
21678 static struct reloc_entry reloc_names
[] =
21680 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
21681 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
21682 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
21683 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
21684 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
21685 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
21686 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
21687 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
21688 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
21689 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
21690 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
21691 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
21692 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
21693 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
21694 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
21695 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
21696 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
21697 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
21698 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
21699 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
21700 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21701 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21702 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
21703 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
21704 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
21705 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
21706 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
21710 /* Table of all conditional affixes. */
21711 static const struct asm_cond conds
[] =
21715 {"cs", 0x2}, {"hs", 0x2},
21716 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
21729 static const struct asm_cond vconds
[] =
21735 #define UL_BARRIER(L,U,CODE,FEAT) \
21736 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
21737 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
21739 static struct asm_barrier_opt barrier_opt_names
[] =
21741 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
21742 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
21743 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
21744 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
21745 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
21746 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
21747 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
21748 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
21749 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
21750 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
21751 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
21752 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
21753 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
21754 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
21755 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
21756 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
21761 /* Table of ARM-format instructions. */
21763 /* Macros for gluing together operand strings. N.B. In all cases
21764 other than OPS0, the trailing OP_stop comes from default
21765 zero-initialization of the unspecified elements of the array. */
21766 #define OPS0() { OP_stop, }
21767 #define OPS1(a) { OP_##a, }
21768 #define OPS2(a,b) { OP_##a,OP_##b, }
21769 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
21770 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
21771 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
21772 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
21774 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
21775 This is useful when mixing operands for ARM and THUMB, i.e. using the
21776 MIX_ARM_THUMB_OPERANDS macro.
21777 In order to use these macros, prefix the number of operands with _
21779 #define OPS_1(a) { a, }
21780 #define OPS_2(a,b) { a,b, }
21781 #define OPS_3(a,b,c) { a,b,c, }
21782 #define OPS_4(a,b,c,d) { a,b,c,d, }
21783 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
21784 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
21786 /* These macros abstract out the exact format of the mnemonic table and
21787 save some repeated characters. */
21789 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
21790 #define TxCE(mnem, op, top, nops, ops, ae, te) \
21791 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
21792 THUMB_VARIANT, do_##ae, do_##te, 0 }
21794 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
21795 a T_MNEM_xyz enumerator. */
21796 #define TCE(mnem, aop, top, nops, ops, ae, te) \
21797 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
21798 #define tCE(mnem, aop, top, nops, ops, ae, te) \
21799 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21801 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
21802 infix after the third character. */
21803 #define TxC3(mnem, op, top, nops, ops, ae, te) \
21804 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
21805 THUMB_VARIANT, do_##ae, do_##te, 0 }
21806 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
21807 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
21808 THUMB_VARIANT, do_##ae, do_##te, 0 }
21809 #define TC3(mnem, aop, top, nops, ops, ae, te) \
21810 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
21811 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
21812 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
21813 #define tC3(mnem, aop, top, nops, ops, ae, te) \
21814 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21815 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
21816 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21818 /* Mnemonic that cannot be conditionalized. The ARM condition-code
21819 field is still 0xE. Many of the Thumb variants can be executed
21820 conditionally, so this is checked separately. */
21821 #define TUE(mnem, op, top, nops, ops, ae, te) \
21822 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21823 THUMB_VARIANT, do_##ae, do_##te, 0 }
21825 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
21826 Used by mnemonics that have very minimal differences in the encoding for
21827 ARM and Thumb variants and can be handled in a common function. */
21828 #define TUEc(mnem, op, top, nops, ops, en) \
21829 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21830 THUMB_VARIANT, do_##en, do_##en, 0 }
21832 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
21833 condition code field. */
21834 #define TUF(mnem, op, top, nops, ops, ae, te) \
21835 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
21836 THUMB_VARIANT, do_##ae, do_##te, 0 }
21838 /* ARM-only variants of all the above. */
21839 #define CE(mnem, op, nops, ops, ae) \
21840 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21842 #define C3(mnem, op, nops, ops, ae) \
21843 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21845 /* Thumb-only variants of TCE and TUE. */
21846 #define ToC(mnem, top, nops, ops, te) \
21847 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21850 #define ToU(mnem, top, nops, ops, te) \
21851 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
21854 /* T_MNEM_xyz enumerator variants of ToC. */
21855 #define toC(mnem, top, nops, ops, te) \
21856 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
21859 /* T_MNEM_xyz enumerator variants of ToU. */
21860 #define toU(mnem, top, nops, ops, te) \
21861 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
21864 /* Legacy mnemonics that always have conditional infix after the third
21866 #define CL(mnem, op, nops, ops, ae) \
21867 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21868 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21870 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
21871 #define cCE(mnem, op, nops, ops, ae) \
21872 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21874 /* mov instructions that are shared between coprocessor and MVE. */
21875 #define mcCE(mnem, op, nops, ops, ae) \
21876 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
21878 /* Legacy coprocessor instructions where conditional infix and conditional
21879 suffix are ambiguous. For consistency this includes all FPA instructions,
21880 not just the potentially ambiguous ones. */
21881 #define cCL(mnem, op, nops, ops, ae) \
21882 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21883 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21885 /* Coprocessor, takes either a suffix or a position-3 infix
21886 (for an FPA corner case). */
21887 #define C3E(mnem, op, nops, ops, ae) \
21888 { mnem, OPS##nops ops, OT_csuf_or_in3, \
21889 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21891 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
21892 { m1 #m2 m3, OPS##nops ops, \
21893 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
21894 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21896 #define CM(m1, m2, op, nops, ops, ae) \
21897 xCM_ (m1, , m2, op, nops, ops, ae), \
21898 xCM_ (m1, eq, m2, op, nops, ops, ae), \
21899 xCM_ (m1, ne, m2, op, nops, ops, ae), \
21900 xCM_ (m1, cs, m2, op, nops, ops, ae), \
21901 xCM_ (m1, hs, m2, op, nops, ops, ae), \
21902 xCM_ (m1, cc, m2, op, nops, ops, ae), \
21903 xCM_ (m1, ul, m2, op, nops, ops, ae), \
21904 xCM_ (m1, lo, m2, op, nops, ops, ae), \
21905 xCM_ (m1, mi, m2, op, nops, ops, ae), \
21906 xCM_ (m1, pl, m2, op, nops, ops, ae), \
21907 xCM_ (m1, vs, m2, op, nops, ops, ae), \
21908 xCM_ (m1, vc, m2, op, nops, ops, ae), \
21909 xCM_ (m1, hi, m2, op, nops, ops, ae), \
21910 xCM_ (m1, ls, m2, op, nops, ops, ae), \
21911 xCM_ (m1, ge, m2, op, nops, ops, ae), \
21912 xCM_ (m1, lt, m2, op, nops, ops, ae), \
21913 xCM_ (m1, gt, m2, op, nops, ops, ae), \
21914 xCM_ (m1, le, m2, op, nops, ops, ae), \
21915 xCM_ (m1, al, m2, op, nops, ops, ae)
21917 #define UE(mnem, op, nops, ops, ae) \
21918 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21920 #define UF(mnem, op, nops, ops, ae) \
21921 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21923 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
21924 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
21925 use the same encoding function for each. */
21926 #define NUF(mnem, op, nops, ops, enc) \
21927 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21928 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21930 /* Neon data processing, version which indirects through neon_enc_tab for
21931 the various overloaded versions of opcodes. */
21932 #define nUF(mnem, op, nops, ops, enc) \
21933 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21934 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21936 /* Neon insn with conditional suffix for the ARM version, non-overloaded
21938 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21939 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
21940 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21942 #define NCE(mnem, op, nops, ops, enc) \
21943 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21945 #define NCEF(mnem, op, nops, ops, enc) \
21946 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21948 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
21949 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21950 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
21951 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21953 #define nCE(mnem, op, nops, ops, enc) \
21954 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21956 #define nCEF(mnem, op, nops, ops, enc) \
21957 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21960 #define mCEF(mnem, op, nops, ops, enc) \
21961 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
21962 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21965 /* nCEF but for MVE predicated instructions. */
21966 #define mnCEF(mnem, op, nops, ops, enc) \
21967 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21969 /* nCE but for MVE predicated instructions. */
21970 #define mnCE(mnem, op, nops, ops, enc) \
21971 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21973 /* NUF but for potentially MVE predicated instructions. */
21974 #define MNUF(mnem, op, nops, ops, enc) \
21975 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21976 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21978 /* nUF but for potentially MVE predicated instructions. */
21979 #define mnUF(mnem, op, nops, ops, enc) \
21980 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21981 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21983 /* ToC but for potentially MVE predicated instructions. */
21984 #define mToC(mnem, top, nops, ops, te) \
21985 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21988 /* NCE but for MVE predicated instructions. */
21989 #define MNCE(mnem, op, nops, ops, enc) \
21990 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21992 /* NCEF but for MVE predicated instructions. */
21993 #define MNCEF(mnem, op, nops, ops, enc) \
21994 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21997 static const struct asm_opcode insns
[] =
21999 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22000 #define THUMB_VARIANT & arm_ext_v4t
22001 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22002 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22003 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22004 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22005 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22006 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22007 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22008 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22009 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22010 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22011 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22012 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22013 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22014 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22015 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22016 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22018 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22019 for setting PSR flag bits. They are obsolete in V6 and do not
22020 have Thumb equivalents. */
22021 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22022 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22023 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
22024 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22025 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22026 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
22027 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22028 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22029 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
22031 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
22032 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
22033 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22034 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22036 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
22037 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22038 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
22040 OP_ADDRGLDR
),ldst
, t_ldst
),
22041 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22043 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22044 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22045 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22046 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22047 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22048 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22050 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
22051 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
22054 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
22055 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
22056 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
22057 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
22059 /* Thumb-compatibility pseudo ops. */
22060 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22061 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22062 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22063 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22064 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22065 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22066 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22067 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22068 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
22069 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
22070 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
22071 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
22073 /* These may simplify to neg. */
22074 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22075 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22077 #undef THUMB_VARIANT
22078 #define THUMB_VARIANT & arm_ext_os
22080 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22081 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22083 #undef THUMB_VARIANT
22084 #define THUMB_VARIANT & arm_ext_v6
22086 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
22088 /* V1 instructions with no Thumb analogue prior to V6T2. */
22089 #undef THUMB_VARIANT
22090 #define THUMB_VARIANT & arm_ext_v6t2
22092 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22093 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22094 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
22096 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22097 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22098 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
22099 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22101 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22102 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22104 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22105 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22107 /* V1 instructions with no Thumb analogue at all. */
22108 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
22109 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
22111 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22112 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22113 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22114 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22115 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22116 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22117 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22118 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22121 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22122 #undef THUMB_VARIANT
22123 #define THUMB_VARIANT & arm_ext_v4t
22125 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22126 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22128 #undef THUMB_VARIANT
22129 #define THUMB_VARIANT & arm_ext_v6t2
22131 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22132 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
22134 /* Generic coprocessor instructions. */
22135 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22136 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22137 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22138 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22139 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22140 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22141 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22144 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22146 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22147 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22150 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22151 #undef THUMB_VARIANT
22152 #define THUMB_VARIANT & arm_ext_msr
22154 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
22155 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
22158 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22159 #undef THUMB_VARIANT
22160 #define THUMB_VARIANT & arm_ext_v6t2
22162 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22163 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22164 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22165 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22166 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22167 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22168 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22169 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22172 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22173 #undef THUMB_VARIANT
22174 #define THUMB_VARIANT & arm_ext_v4t
22176 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22177 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22178 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22179 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22180 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22181 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22184 #define ARM_VARIANT & arm_ext_v4t_5
22186 /* ARM Architecture 4T. */
22187 /* Note: bx (and blx) are required on V5, even if the processor does
22188 not support Thumb. */
22189 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
22192 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22193 #undef THUMB_VARIANT
22194 #define THUMB_VARIANT & arm_ext_v5t
22196 /* Note: blx has 2 variants; the .value coded here is for
22197 BLX(2). Only this variant has conditional execution. */
22198 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
22199 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
22201 #undef THUMB_VARIANT
22202 #define THUMB_VARIANT & arm_ext_v6t2
22204 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
22205 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22206 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22207 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22208 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22209 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22210 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22211 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22214 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22215 #undef THUMB_VARIANT
22216 #define THUMB_VARIANT & arm_ext_v5exp
22218 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22219 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22220 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22221 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22223 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22224 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22226 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22227 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22228 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22229 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22231 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22232 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22233 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22234 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22236 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22237 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22239 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22240 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22241 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22242 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22245 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22246 #undef THUMB_VARIANT
22247 #define THUMB_VARIANT & arm_ext_v6t2
22249 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
22250 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
22252 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
22253 ADDRGLDRS
), ldrd
, t_ldstd
),
22255 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22256 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22259 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22261 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
22264 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22265 #undef THUMB_VARIANT
22266 #define THUMB_VARIANT & arm_ext_v6
22268 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22269 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22270 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22271 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22272 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22273 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22274 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22275 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22276 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22277 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
22279 #undef THUMB_VARIANT
22280 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22282 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
22283 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22285 #undef THUMB_VARIANT
22286 #define THUMB_VARIANT & arm_ext_v6t2
22288 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22289 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22291 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
22292 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
22294 /* ARM V6 not included in V7M. */
22295 #undef THUMB_VARIANT
22296 #define THUMB_VARIANT & arm_ext_v6_notm
22297 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22298 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22299 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
22300 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
22301 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22302 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22303 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
22304 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22305 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
22306 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22307 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22308 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22309 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22310 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22311 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
22312 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
22313 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22314 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22315 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
22317 /* ARM V6 not included in V7M (eg. integer SIMD). */
22318 #undef THUMB_VARIANT
22319 #define THUMB_VARIANT & arm_ext_v6_dsp
22320 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
22321 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
22322 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22323 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22324 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22325 /* Old name for QASX. */
22326 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22327 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22328 /* Old name for QSAX. */
22329 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22330 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22331 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22332 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22333 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22334 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22335 /* Old name for SASX. */
22336 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22337 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22338 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22339 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22340 /* Old name for SHASX. */
22341 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22342 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22343 /* Old name for SHSAX. */
22344 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22345 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22346 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22347 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22348 /* Old name for SSAX. */
22349 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22350 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22351 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22352 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22353 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22354 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22355 /* Old name for UASX. */
22356 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22357 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22358 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22359 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22360 /* Old name for UHASX. */
22361 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22362 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22363 /* Old name for UHSAX. */
22364 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22365 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22366 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22367 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22368 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22369 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22370 /* Old name for UQASX. */
22371 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22372 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22373 /* Old name for UQSAX. */
22374 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22375 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22376 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22377 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22378 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22379 /* Old name for USAX. */
22380 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22381 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22382 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22383 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22384 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22385 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22386 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22387 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22388 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22389 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22390 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22391 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22392 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22393 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22394 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22395 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22396 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22397 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22398 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22399 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22400 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22401 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22402 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22403 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22404 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22405 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22406 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22407 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22408 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22409 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
22410 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
22411 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22412 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22413 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
22416 #define ARM_VARIANT & arm_ext_v6k_v6t2
22417 #undef THUMB_VARIANT
22418 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22420 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
22421 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
22422 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
22423 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
22425 #undef THUMB_VARIANT
22426 #define THUMB_VARIANT & arm_ext_v6_notm
22427 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
22429 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
22430 RRnpcb
), strexd
, t_strexd
),
22432 #undef THUMB_VARIANT
22433 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22434 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
22436 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
22438 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22440 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22442 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
22445 #define ARM_VARIANT & arm_ext_sec
22446 #undef THUMB_VARIANT
22447 #define THUMB_VARIANT & arm_ext_sec
22449 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
22452 #define ARM_VARIANT & arm_ext_virt
22453 #undef THUMB_VARIANT
22454 #define THUMB_VARIANT & arm_ext_virt
22456 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
22457 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
22460 #define ARM_VARIANT & arm_ext_pan
22461 #undef THUMB_VARIANT
22462 #define THUMB_VARIANT & arm_ext_pan
22464 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
22467 #define ARM_VARIANT & arm_ext_v6t2
22468 #undef THUMB_VARIANT
22469 #define THUMB_VARIANT & arm_ext_v6t2
22471 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
22472 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
22473 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22474 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22476 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22477 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
22479 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22480 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22481 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22482 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22485 #define ARM_VARIANT & arm_ext_v3
22486 #undef THUMB_VARIANT
22487 #define THUMB_VARIANT & arm_ext_v6t2
22489 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
22490 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
22491 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
22494 #define ARM_VARIANT & arm_ext_v6t2
22495 #undef THUMB_VARIANT
22496 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22497 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22498 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22500 /* Thumb-only instructions. */
22502 #define ARM_VARIANT NULL
22503 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
22504 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
22506 /* ARM does not really have an IT instruction, so always allow it.
22507 The opcode is copied from Thumb in order to allow warnings in
22508 -mimplicit-it=[never | arm] modes. */
22510 #define ARM_VARIANT & arm_ext_v1
22511 #undef THUMB_VARIANT
22512 #define THUMB_VARIANT & arm_ext_v6t2
22514 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
22515 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
22516 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
22517 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
22518 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
22519 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
22520 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
22521 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
22522 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
22523 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
22524 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
22525 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
22526 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
22527 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
22528 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
22529 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
22530 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22531 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22533 /* Thumb2 only instructions. */
22535 #define ARM_VARIANT NULL
22537 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22538 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22539 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22540 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22541 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
22542 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
22544 /* Hardware division instructions. */
22546 #define ARM_VARIANT & arm_ext_adiv
22547 #undef THUMB_VARIANT
22548 #define THUMB_VARIANT & arm_ext_div
22550 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22551 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22553 /* ARM V6M/V7 instructions. */
22555 #define ARM_VARIANT & arm_ext_barrier
22556 #undef THUMB_VARIANT
22557 #define THUMB_VARIANT & arm_ext_barrier
22559 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
22560 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
22561 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
22563 /* ARM V7 instructions. */
22565 #define ARM_VARIANT & arm_ext_v7
22566 #undef THUMB_VARIANT
22567 #define THUMB_VARIANT & arm_ext_v7
22569 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
22570 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
22573 #define ARM_VARIANT & arm_ext_mp
22574 #undef THUMB_VARIANT
22575 #define THUMB_VARIANT & arm_ext_mp
22577 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
22579 /* AArchv8 instructions. */
22581 #define ARM_VARIANT & arm_ext_v8
22583 /* Instructions shared between armv8-a and armv8-m. */
22584 #undef THUMB_VARIANT
22585 #define THUMB_VARIANT & arm_ext_atomics
22587 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22588 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22589 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22590 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22591 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22592 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22593 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22594 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
22595 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22596 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22598 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22600 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22602 #undef THUMB_VARIANT
22603 #define THUMB_VARIANT & arm_ext_v8
22605 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
22606 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
22608 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
22611 /* Defined in V8 but is in undefined encoding space for earlier
22612 architectures. However earlier architectures are required to treat
22613 this instuction as a semihosting trap as well. Hence while not explicitly
22614 defined as such, it is in fact correct to define the instruction for all
22616 #undef THUMB_VARIANT
22617 #define THUMB_VARIANT & arm_ext_v1
22619 #define ARM_VARIANT & arm_ext_v1
22620 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
22622 /* ARMv8 T32 only. */
22624 #define ARM_VARIANT NULL
22625 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
22626 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
22627 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
22629 /* FP for ARMv8. */
22631 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
22632 #undef THUMB_VARIANT
22633 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
22635 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22636 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22637 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22638 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22639 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22640 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22641 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
22642 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
22643 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
22644 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
22645 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
22646 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
22647 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
22649 /* Crypto v1 extensions. */
22651 #define ARM_VARIANT & fpu_crypto_ext_armv8
22652 #undef THUMB_VARIANT
22653 #define THUMB_VARIANT & fpu_crypto_ext_armv8
22655 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
22656 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
22657 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
22658 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
22659 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
22660 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
22661 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
22662 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
22663 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
22664 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
22665 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
22666 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
22667 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
22668 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
22671 #define ARM_VARIANT & crc_ext_armv8
22672 #undef THUMB_VARIANT
22673 #define THUMB_VARIANT & crc_ext_armv8
22674 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
22675 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
22676 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
22677 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
22678 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
22679 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
22681 /* ARMv8.2 RAS extension. */
22683 #define ARM_VARIANT & arm_ext_ras
22684 #undef THUMB_VARIANT
22685 #define THUMB_VARIANT & arm_ext_ras
22686 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
22689 #define ARM_VARIANT & arm_ext_v8_3
22690 #undef THUMB_VARIANT
22691 #define THUMB_VARIANT & arm_ext_v8_3
22692 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
22693 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
22694 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
22697 #define ARM_VARIANT & fpu_neon_ext_dotprod
22698 #undef THUMB_VARIANT
22699 #define THUMB_VARIANT & fpu_neon_ext_dotprod
22700 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
22701 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
22704 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
22705 #undef THUMB_VARIANT
22706 #define THUMB_VARIANT NULL
22708 cCE("wfs", e200110
, 1, (RR
), rd
),
22709 cCE("rfs", e300110
, 1, (RR
), rd
),
22710 cCE("wfc", e400110
, 1, (RR
), rd
),
22711 cCE("rfc", e500110
, 1, (RR
), rd
),
22713 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22714 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22715 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22716 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22718 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22719 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22720 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22721 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22723 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
22724 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
22725 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
22726 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
22727 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
22728 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
22729 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
22730 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
22731 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
22732 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
22733 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
22734 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
22736 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
22737 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
22738 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
22739 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
22740 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
22741 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
22742 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
22743 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
22744 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
22745 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
22746 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
22747 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
22749 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
22750 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
22751 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
22752 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
22753 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
22754 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
22755 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
22756 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
22757 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
22758 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
22759 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
22760 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
22762 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
22763 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
22764 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
22765 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
22766 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
22767 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
22768 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
22769 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
22770 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
22771 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
22772 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
22773 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
22775 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
22776 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
22777 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
22778 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
22779 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
22780 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
22781 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
22782 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
22783 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
22784 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
22785 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
22786 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
22788 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
22789 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
22790 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
22791 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
22792 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
22793 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
22794 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
22795 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
22796 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
22797 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
22798 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
22799 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
22801 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
22802 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
22803 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
22804 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
22805 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
22806 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
22807 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
22808 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
22809 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
22810 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
22811 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
22812 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
22814 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
22815 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
22816 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
22817 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
22818 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
22819 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
22820 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
22821 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
22822 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
22823 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
22824 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
22825 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
22827 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
22828 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
22829 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
22830 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
22831 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
22832 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
22833 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
22834 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
22835 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
22836 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
22837 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
22838 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
22840 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
22841 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
22842 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
22843 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
22844 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
22845 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
22846 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
22847 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
22848 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
22849 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
22850 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
22851 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
22853 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
22854 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
22855 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
22856 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
22857 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
22858 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
22859 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
22860 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
22861 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
22862 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
22863 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
22864 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
22866 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
22867 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
22868 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
22869 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
22870 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
22871 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
22872 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
22873 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
22874 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
22875 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
22876 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
22877 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
22879 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
22880 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
22881 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
22882 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
22883 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
22884 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
22885 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
22886 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
22887 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
22888 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
22889 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
22890 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
22892 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
22893 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
22894 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
22895 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
22896 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
22897 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
22898 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
22899 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
22900 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
22901 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
22902 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
22903 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
22905 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
22906 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
22907 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
22908 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
22909 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
22910 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
22911 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
22912 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
22913 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
22914 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
22915 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
22916 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
22918 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
22919 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
22920 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
22921 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
22922 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
22923 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
22924 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
22925 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
22926 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
22927 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
22928 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
22929 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
22931 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22932 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22933 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22934 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22935 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22936 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22937 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22938 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22939 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22940 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22941 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22942 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22944 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22945 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22946 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22947 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22948 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22949 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22950 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22951 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22952 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22953 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22954 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22955 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22957 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22958 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22959 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22960 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22961 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22962 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22963 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22964 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22965 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22966 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22967 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22968 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22970 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22971 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22972 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22973 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22974 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22975 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22976 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22977 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22978 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22979 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22980 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22981 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22983 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22984 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22985 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22986 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22987 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22988 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22989 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22990 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22991 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22992 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22993 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22994 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22996 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22997 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22998 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22999 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23000 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23001 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23002 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23003 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23004 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23005 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23006 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23007 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23009 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23010 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23011 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23012 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23013 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23014 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23015 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23016 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23017 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23018 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23019 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23020 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23022 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23023 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23024 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23025 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23026 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23027 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23028 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23029 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23030 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23031 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23032 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23033 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23035 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23036 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23037 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23038 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23039 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23040 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23041 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23042 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23043 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23044 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23045 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23046 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23048 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23049 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23050 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23051 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23052 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23053 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23054 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23055 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23056 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23057 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23058 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23059 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23061 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23062 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23063 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23064 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23065 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23066 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23067 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23068 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23069 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23070 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23071 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23072 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23074 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23075 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23076 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23077 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23078 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23079 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23080 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23081 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23082 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23083 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23084 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23085 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23087 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23088 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23089 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23090 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23091 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23092 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23093 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23094 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23095 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23096 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23097 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23098 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23100 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23101 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23102 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23103 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23105 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
23106 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
23107 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
23108 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
23109 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
23110 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
23111 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
23112 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
23113 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
23114 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
23115 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
23116 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
23118 /* The implementation of the FIX instruction is broken on some
23119 assemblers, in that it accepts a precision specifier as well as a
23120 rounding specifier, despite the fact that this is meaningless.
23121 To be more compatible, we accept it as well, though of course it
23122 does not set any bits. */
23123 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
23124 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
23125 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
23126 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
23127 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
23128 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
23129 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
23130 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
23131 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
23132 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
23133 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
23134 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
23135 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
23137 /* Instructions that were new with the real FPA, call them V2. */
23139 #define ARM_VARIANT & fpu_fpa_ext_v2
23141 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23142 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23143 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23144 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23145 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23146 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23149 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23151 /* Moves and type conversions. */
23152 cCE("fmstat", ef1fa10
, 0, (), noargs
),
23153 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
23154 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
23155 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23156 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23157 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23158 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23159 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23160 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23161 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
23162 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
23164 /* Memory operations. */
23165 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23166 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23167 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23168 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23169 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23170 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23171 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23172 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23173 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23174 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23175 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23176 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23177 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23178 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23179 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23180 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23181 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23182 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23184 /* Monadic operations. */
23185 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23186 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23187 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23189 /* Dyadic operations. */
23190 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23191 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23192 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23193 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23194 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23195 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23196 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23197 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23198 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23201 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23202 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
23203 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23204 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
23206 /* Double precision load/store are still present on single precision
23207 implementations. */
23208 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23209 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23210 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23211 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23212 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23213 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23214 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23215 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23216 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23217 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23220 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23222 /* Moves and type conversions. */
23223 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23224 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23225 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23226 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23227 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23228 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23229 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23230 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23231 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23232 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23233 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23234 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23236 /* Monadic operations. */
23237 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23238 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23239 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23241 /* Dyadic operations. */
23242 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23243 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23244 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23245 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23246 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23247 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23248 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23249 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23250 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23253 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23254 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
23255 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23256 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
23258 /* Instructions which may belong to either the Neon or VFP instruction sets.
23259 Individual encoder functions perform additional architecture checks. */
23261 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23262 #undef THUMB_VARIANT
23263 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23265 /* These mnemonics are unique to VFP. */
23266 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
23267 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
23268 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23269 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23270 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23271 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
23272 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
23273 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
23275 /* Mnemonics shared by Neon and VFP. */
23276 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
23277 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23278 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23280 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23281 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23282 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23283 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23284 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23285 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23287 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
23288 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
23289 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
23290 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
23293 /* NOTE: All VMOV encoding is special-cased! */
23294 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
23296 #undef THUMB_VARIANT
23297 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23298 by different feature bits. Since we are setting the Thumb guard, we can
23299 require Thumb-1 which makes it a nop guard and set the right feature bit in
23300 do_vldr_vstr (). */
23301 #define THUMB_VARIANT & arm_ext_v4t
23302 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23303 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23306 #define ARM_VARIANT & arm_ext_fp16
23307 #undef THUMB_VARIANT
23308 #define THUMB_VARIANT & arm_ext_fp16
23309 /* New instructions added from v8.2, allowing the extraction and insertion of
23310 the upper 16 bits of a 32-bit vector register. */
23311 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
23312 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
23314 /* New backported fma/fms instructions optional in v8.2. */
23315 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
23316 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
23318 #undef THUMB_VARIANT
23319 #define THUMB_VARIANT & fpu_neon_ext_v1
23321 #define ARM_VARIANT & fpu_neon_ext_v1
23323 /* Data processing with three registers of the same length. */
23324 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23325 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
23326 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
23327 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23328 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23329 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23330 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23331 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23332 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23333 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23334 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23335 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23336 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23337 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23338 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23339 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23340 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23341 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23342 /* If not immediate, fall back to neon_dyadic_i64_su.
23343 shl_imm should accept I8 I16 I32 I64,
23344 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23345 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
23346 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
23347 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
23348 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
23349 /* Logic ops, types optional & ignored. */
23350 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23351 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23352 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23353 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23354 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23355 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23356 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23357 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23358 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
23359 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23360 /* Bitfield ops, untyped. */
23361 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23362 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23363 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23364 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23365 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23366 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23367 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23368 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23369 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23370 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23371 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23372 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23373 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23374 back to neon_dyadic_if_su. */
23375 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23376 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23377 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23378 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23379 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23380 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23381 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23382 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23383 /* Comparison. Type I8 I16 I32 F32. */
23384 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
23385 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
23386 /* As above, D registers only. */
23387 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23388 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23389 /* Int and float variants, signedness unimportant. */
23390 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23391 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23392 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
23393 /* Add/sub take types I8 I16 I32 I64 F32. */
23394 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23395 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23396 /* vtst takes sizes 8, 16, 32. */
23397 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
23398 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
23399 /* VMUL takes I8 I16 I32 F32 P8. */
23400 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
23401 /* VQD{R}MULH takes S16 S32. */
23402 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23403 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23404 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23405 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23406 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23407 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23408 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23409 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23410 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23411 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23412 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23413 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23414 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23415 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23416 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23417 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23418 /* ARM v8.1 extension. */
23419 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23420 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23421 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23422 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23424 /* Two address, int/float. Types S8 S16 S32 F32. */
23425 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23426 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23428 /* Data processing with two registers and a shift amount. */
23429 /* Right shifts, and variants with rounding.
23430 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23431 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23432 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23433 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23434 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23435 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23436 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23437 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23438 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23439 /* Shift and insert. Sizes accepted 8 16 32 64. */
23440 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
23441 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
23442 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
23443 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
23444 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23445 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
23446 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
23447 /* Right shift immediate, saturating & narrowing, with rounding variants.
23448 Types accepted S16 S32 S64 U16 U32 U64. */
23449 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23450 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23451 /* As above, unsigned. Types accepted S16 S32 S64. */
23452 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23453 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23454 /* Right shift narrowing. Types accepted I16 I32 I64. */
23455 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23456 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23457 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23458 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
23459 /* CVT with optional immediate for fixed-point variant. */
23460 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
23462 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
23463 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
23465 /* Data processing, three registers of different lengths. */
23466 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23467 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
23468 /* If not scalar, fall back to neon_dyadic_long.
23469 Vector types as above, scalar types S16 S32 U16 U32. */
23470 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23471 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23472 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23473 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23474 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23475 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23476 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23477 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23478 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23479 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23480 /* Saturating doubling multiplies. Types S16 S32. */
23481 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23482 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23483 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23484 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23485 S16 S32 U16 U32. */
23486 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
23488 /* Extract. Size 8. */
23489 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
23490 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
23492 /* Two registers, miscellaneous. */
23493 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23494 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
23495 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
23496 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
23497 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
23498 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
23499 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
23500 /* Vector replicate. Sizes 8 16 32. */
23501 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
23502 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
23503 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23504 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
23505 /* VMOVN. Types I16 I32 I64. */
23506 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
23507 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
23508 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
23509 /* VQMOVUN. Types S16 S32 S64. */
23510 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
23511 /* VZIP / VUZP. Sizes 8 16 32. */
23512 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23513 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23514 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23515 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23516 /* VQABS / VQNEG. Types S8 S16 S32. */
23517 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23518 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23519 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23520 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23521 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
23522 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23523 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
23524 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23525 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
23526 /* Reciprocal estimates. Types U32 F16 F32. */
23527 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23528 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
23529 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23530 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
23531 /* VCLS. Types S8 S16 S32. */
23532 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
23533 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
23534 /* VCLZ. Types I8 I16 I32. */
23535 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
23536 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
23537 /* VCNT. Size 8. */
23538 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
23539 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
23540 /* Two address, untyped. */
23541 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
23542 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
23543 /* VTRN. Sizes 8 16 32. */
23544 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
23545 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
23547 /* Table lookup. Size 8. */
23548 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23549 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23551 #undef THUMB_VARIANT
23552 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
23554 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
23556 /* Neon element/structure load/store. */
23557 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23558 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23559 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23560 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23561 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23562 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23563 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23564 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23566 #undef THUMB_VARIANT
23567 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
23569 #define ARM_VARIANT & fpu_vfp_ext_v3xd
23570 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
23571 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23572 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23573 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23574 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23575 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23576 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23577 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23578 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23580 #undef THUMB_VARIANT
23581 #define THUMB_VARIANT & fpu_vfp_ext_v3
23583 #define ARM_VARIANT & fpu_vfp_ext_v3
23585 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
23586 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23587 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23588 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23589 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23590 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23591 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23592 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23593 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23596 #define ARM_VARIANT & fpu_vfp_ext_fma
23597 #undef THUMB_VARIANT
23598 #define THUMB_VARIANT & fpu_vfp_ext_fma
23599 /* Mnemonics shared by Neon and VFP. These are included in the
23600 VFP FMA variant; NEON and VFP FMA always includes the NEON
23601 FMA instructions. */
23602 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23603 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23604 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
23605 the v form should always be used. */
23606 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23607 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23608 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23609 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23610 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23611 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23613 #undef THUMB_VARIANT
23615 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
23617 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23618 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23619 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23620 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23621 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23622 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23623 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
23624 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
23627 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
23629 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
23630 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
23631 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
23632 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
23633 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
23634 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
23635 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
23636 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
23637 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
23638 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23639 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23640 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23641 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23642 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23643 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23644 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23645 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23646 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23647 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
23648 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
23649 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23650 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23651 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23652 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23653 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23654 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23655 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
23656 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
23657 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
23658 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
23659 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
23660 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
23661 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
23662 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
23663 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23664 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23665 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23666 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23667 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23668 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23669 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23670 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23671 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23672 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23673 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23674 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23675 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
23676 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23677 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23678 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23679 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23680 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23681 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23682 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23683 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23684 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23685 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23686 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23687 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23688 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23689 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23690 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23691 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23692 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23693 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23694 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23695 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23696 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23697 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23698 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23699 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23700 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23701 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23702 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23703 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23704 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23705 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23706 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23707 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23708 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23709 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23710 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23711 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23712 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23713 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23714 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23715 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23716 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23717 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
23718 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23719 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23720 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23721 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23722 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23723 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23724 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23725 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23726 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23727 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23728 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23729 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23730 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23731 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23732 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23733 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23734 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23735 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23736 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23737 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23738 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23739 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
23740 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23741 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23742 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23743 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23744 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23745 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23746 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23747 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23748 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23749 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23750 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23751 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23752 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23753 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23754 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23755 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23756 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23757 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23758 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23759 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23760 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23761 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23762 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23763 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23764 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23765 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23766 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23767 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23768 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23769 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23770 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23771 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23772 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23773 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23774 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23775 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23776 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23777 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23778 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23779 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23780 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23781 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23782 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23783 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23784 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23785 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23786 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23787 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23788 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23789 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23790 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
23793 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
23795 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
23796 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
23797 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
23798 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23799 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23800 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23801 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23802 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23803 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23804 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23805 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23806 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23807 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23808 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23809 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23810 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23811 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23812 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23813 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23814 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23815 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
23816 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23817 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23818 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23819 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23820 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23821 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23822 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23823 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23824 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23825 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23826 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23827 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23828 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23829 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23830 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23831 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23832 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23833 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23834 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23835 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23836 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23837 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23838 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23839 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23840 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23841 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23842 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23843 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23844 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23845 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23846 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23847 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23848 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23849 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23850 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23851 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23854 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
23856 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23857 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23858 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23859 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23860 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23861 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23862 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23863 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23864 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
23865 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
23866 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
23867 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
23868 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
23869 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
23870 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
23871 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
23872 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
23873 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
23874 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
23875 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
23876 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
23877 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
23878 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
23879 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
23880 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
23881 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
23882 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
23883 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
23884 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
23885 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
23886 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
23887 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
23888 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
23889 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
23890 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
23891 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
23892 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
23893 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
23894 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
23895 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
23896 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
23897 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
23898 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
23899 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
23900 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
23901 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
23902 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
23903 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
23904 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
23905 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
23906 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
23907 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
23908 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
23909 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
23910 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23911 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23912 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23913 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23914 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23915 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23916 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
23917 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
23918 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
23919 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
23920 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23921 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23922 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23923 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23924 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23925 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23926 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23927 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23928 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23929 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23930 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23931 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23933 /* ARMv8.5-A instructions. */
23935 #define ARM_VARIANT & arm_ext_sb
23936 #undef THUMB_VARIANT
23937 #define THUMB_VARIANT & arm_ext_sb
23938 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
23941 #define ARM_VARIANT & arm_ext_predres
23942 #undef THUMB_VARIANT
23943 #define THUMB_VARIANT & arm_ext_predres
23944 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
23945 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
23946 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
23948 /* ARMv8-M instructions. */
23950 #define ARM_VARIANT NULL
23951 #undef THUMB_VARIANT
23952 #define THUMB_VARIANT & arm_ext_v8m
23953 ToU("sg", e97fe97f
, 0, (), noargs
),
23954 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
23955 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
23956 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
23957 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
23958 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
23959 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
23961 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
23962 instructions behave as nop if no VFP is present. */
23963 #undef THUMB_VARIANT
23964 #define THUMB_VARIANT & arm_ext_v8m_main
23965 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
23966 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
23968 /* Armv8.1-M Mainline instructions. */
23969 #undef THUMB_VARIANT
23970 #define THUMB_VARIANT & arm_ext_v8_1m_main
23971 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
23972 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
23973 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23974 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
23975 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23977 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
23978 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
23979 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
23981 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
23982 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
23984 #undef THUMB_VARIANT
23985 #define THUMB_VARIANT & mve_ext
23987 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23988 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23989 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23990 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23991 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23992 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23993 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23994 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23995 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23996 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23997 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23998 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23999 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24000 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24001 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24003 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
24004 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
24005 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
24006 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
24007 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
24008 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
24009 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
24010 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
24011 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
24012 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
24013 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
24014 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
24015 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
24016 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
24017 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
24019 /* MVE and MVE FP only. */
24020 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24021 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24022 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24023 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24024 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
24025 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
24026 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24027 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24028 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24029 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24030 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24031 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24032 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24033 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24034 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24035 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24037 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24038 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24039 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24040 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24041 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24042 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24043 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24044 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24045 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24046 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24047 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24048 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24049 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24050 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24051 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24052 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24053 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24054 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24055 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24056 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24058 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
24059 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
24060 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
24061 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24062 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24063 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
24064 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
24067 #define ARM_VARIANT & fpu_vfp_ext_v1
24068 #undef THUMB_VARIANT
24069 #define THUMB_VARIANT & arm_ext_v6t2
24071 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24074 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24076 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
24077 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
24078 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
24079 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24081 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
24082 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24083 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24085 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24086 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24088 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
24089 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
24091 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24092 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24095 #define ARM_VARIANT & fpu_vfp_ext_v2
24097 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
24098 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
24099 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
24100 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
24103 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24104 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
24105 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
24106 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
24107 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
24110 #define ARM_VARIANT & fpu_neon_ext_v1
24111 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24112 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
24113 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24114 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24117 #undef THUMB_VARIANT
24149 /* MD interface: bits in the object file. */
24151 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24152 for use in the a.out file, and stores them in the array pointed to by buf.
24153 This knows about the endian-ness of the target machine and does
24154 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24155 2 (short) and 4 (long) Floating numbers are put out as a series of
24156 LITTLENUMS (shorts, here at least). */
24159 md_number_to_chars (char * buf
, valueT val
, int n
)
24161 if (target_big_endian
)
24162 number_to_chars_bigendian (buf
, val
, n
);
24164 number_to_chars_littleendian (buf
, val
, n
);
24168 md_chars_to_number (char * buf
, int n
)
24171 unsigned char * where
= (unsigned char *) buf
;
24173 if (target_big_endian
)
24178 result
|= (*where
++ & 255);
24186 result
|= (where
[n
] & 255);
24193 /* MD interface: Sections. */
24195 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24196 that an rs_machine_dependent frag may reach. */
24199 arm_frag_max_var (fragS
*fragp
)
24201 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24202 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24204 Note that we generate relaxable instructions even for cases that don't
24205 really need it, like an immediate that's a trivial constant. So we're
24206 overestimating the instruction size for some of those cases. Rather
24207 than putting more intelligence here, it would probably be better to
24208 avoid generating a relaxation frag in the first place when it can be
24209 determined up front that a short instruction will suffice. */
24211 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
24215 /* Estimate the size of a frag before relaxing. Assume everything fits in
24219 md_estimate_size_before_relax (fragS
* fragp
,
24220 segT segtype ATTRIBUTE_UNUSED
)
24226 /* Convert a machine dependent frag. */
24229 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
24231 unsigned long insn
;
24232 unsigned long old_op
;
24240 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24242 old_op
= bfd_get_16(abfd
, buf
);
24243 if (fragp
->fr_symbol
)
24245 exp
.X_op
= O_symbol
;
24246 exp
.X_add_symbol
= fragp
->fr_symbol
;
24250 exp
.X_op
= O_constant
;
24252 exp
.X_add_number
= fragp
->fr_offset
;
24253 opcode
= fragp
->fr_subtype
;
24256 case T_MNEM_ldr_pc
:
24257 case T_MNEM_ldr_pc2
:
24258 case T_MNEM_ldr_sp
:
24259 case T_MNEM_str_sp
:
24266 if (fragp
->fr_var
== 4)
24268 insn
= THUMB_OP32 (opcode
);
24269 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
24271 insn
|= (old_op
& 0x700) << 4;
24275 insn
|= (old_op
& 7) << 12;
24276 insn
|= (old_op
& 0x38) << 13;
24278 insn
|= 0x00000c00;
24279 put_thumb32_insn (buf
, insn
);
24280 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
24284 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
24286 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
24289 if (fragp
->fr_var
== 4)
24291 insn
= THUMB_OP32 (opcode
);
24292 insn
|= (old_op
& 0xf0) << 4;
24293 put_thumb32_insn (buf
, insn
);
24294 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
24298 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24299 exp
.X_add_number
-= 4;
24307 if (fragp
->fr_var
== 4)
24309 int r0off
= (opcode
== T_MNEM_mov
24310 || opcode
== T_MNEM_movs
) ? 0 : 8;
24311 insn
= THUMB_OP32 (opcode
);
24312 insn
= (insn
& 0xe1ffffff) | 0x10000000;
24313 insn
|= (old_op
& 0x700) << r0off
;
24314 put_thumb32_insn (buf
, insn
);
24315 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24319 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
24324 if (fragp
->fr_var
== 4)
24326 insn
= THUMB_OP32(opcode
);
24327 put_thumb32_insn (buf
, insn
);
24328 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
24331 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
24335 if (fragp
->fr_var
== 4)
24337 insn
= THUMB_OP32(opcode
);
24338 insn
|= (old_op
& 0xf00) << 14;
24339 put_thumb32_insn (buf
, insn
);
24340 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
24343 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
24346 case T_MNEM_add_sp
:
24347 case T_MNEM_add_pc
:
24348 case T_MNEM_inc_sp
:
24349 case T_MNEM_dec_sp
:
24350 if (fragp
->fr_var
== 4)
24352 /* ??? Choose between add and addw. */
24353 insn
= THUMB_OP32 (opcode
);
24354 insn
|= (old_op
& 0xf0) << 4;
24355 put_thumb32_insn (buf
, insn
);
24356 if (opcode
== T_MNEM_add_pc
)
24357 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
24359 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24362 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24370 if (fragp
->fr_var
== 4)
24372 insn
= THUMB_OP32 (opcode
);
24373 insn
|= (old_op
& 0xf0) << 4;
24374 insn
|= (old_op
& 0xf) << 16;
24375 put_thumb32_insn (buf
, insn
);
24376 if (insn
& (1 << 20))
24377 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24379 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24382 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24388 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
24389 (enum bfd_reloc_code_real
) reloc_type
);
24390 fixp
->fx_file
= fragp
->fr_file
;
24391 fixp
->fx_line
= fragp
->fr_line
;
24392 fragp
->fr_fix
+= fragp
->fr_var
;
24394 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24395 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
24396 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
24397 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
24400 /* Return the size of a relaxable immediate operand instruction.
24401 SHIFT and SIZE specify the form of the allowable immediate. */
24403 relax_immediate (fragS
*fragp
, int size
, int shift
)
24409 /* ??? Should be able to do better than this. */
24410 if (fragp
->fr_symbol
)
24413 low
= (1 << shift
) - 1;
24414 mask
= (1 << (shift
+ size
)) - (1 << shift
);
24415 offset
= fragp
->fr_offset
;
24416 /* Force misaligned offsets to 32-bit variant. */
24419 if (offset
& ~mask
)
24424 /* Get the address of a symbol during relaxation. */
24426 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
24432 sym
= fragp
->fr_symbol
;
24433 sym_frag
= symbol_get_frag (sym
);
24434 know (S_GET_SEGMENT (sym
) != absolute_section
24435 || sym_frag
== &zero_address_frag
);
24436 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
24438 /* If frag has yet to be reached on this pass, assume it will
24439 move by STRETCH just as we did. If this is not so, it will
24440 be because some frag between grows, and that will force
24444 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
24448 /* Adjust stretch for any alignment frag. Note that if have
24449 been expanding the earlier code, the symbol may be
24450 defined in what appears to be an earlier frag. FIXME:
24451 This doesn't handle the fr_subtype field, which specifies
24452 a maximum number of bytes to skip when doing an
24454 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
24456 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
24459 stretch
= - ((- stretch
)
24460 & ~ ((1 << (int) f
->fr_offset
) - 1));
24462 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
24474 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
24477 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
24482 /* Assume worst case for symbols not known to be in the same section. */
24483 if (fragp
->fr_symbol
== NULL
24484 || !S_IS_DEFINED (fragp
->fr_symbol
)
24485 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24486 || S_IS_WEAK (fragp
->fr_symbol
))
24489 val
= relaxed_symbol_addr (fragp
, stretch
);
24490 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
24491 addr
= (addr
+ 4) & ~3;
24492 /* Force misaligned targets to 32-bit variant. */
24496 if (val
< 0 || val
> 1020)
24501 /* Return the size of a relaxable add/sub immediate instruction. */
24503 relax_addsub (fragS
*fragp
, asection
*sec
)
24508 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24509 op
= bfd_get_16(sec
->owner
, buf
);
24510 if ((op
& 0xf) == ((op
>> 4) & 0xf))
24511 return relax_immediate (fragp
, 8, 0);
24513 return relax_immediate (fragp
, 3, 0);
24516 /* Return TRUE iff the definition of symbol S could be pre-empted
24517 (overridden) at link or load time. */
24519 symbol_preemptible (symbolS
*s
)
24521 /* Weak symbols can always be pre-empted. */
24525 /* Non-global symbols cannot be pre-empted. */
24526 if (! S_IS_EXTERNAL (s
))
24530 /* In ELF, a global symbol can be marked protected, or private. In that
24531 case it can't be pre-empted (other definitions in the same link unit
24532 would violate the ODR). */
24533 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
24537 /* Other global symbols might be pre-empted. */
24541 /* Return the size of a relaxable branch instruction. BITS is the
24542 size of the offset field in the narrow instruction. */
24545 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
24551 /* Assume worst case for symbols not known to be in the same section. */
24552 if (!S_IS_DEFINED (fragp
->fr_symbol
)
24553 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24554 || S_IS_WEAK (fragp
->fr_symbol
))
24558 /* A branch to a function in ARM state will require interworking. */
24559 if (S_IS_DEFINED (fragp
->fr_symbol
)
24560 && ARM_IS_FUNC (fragp
->fr_symbol
))
24564 if (symbol_preemptible (fragp
->fr_symbol
))
24567 val
= relaxed_symbol_addr (fragp
, stretch
);
24568 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
24571 /* Offset is a signed value *2 */
24573 if (val
>= limit
|| val
< -limit
)
24579 /* Relax a machine dependent frag. This returns the amount by which
24580 the current size of the frag should change. */
24583 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
24588 oldsize
= fragp
->fr_var
;
24589 switch (fragp
->fr_subtype
)
24591 case T_MNEM_ldr_pc2
:
24592 newsize
= relax_adr (fragp
, sec
, stretch
);
24594 case T_MNEM_ldr_pc
:
24595 case T_MNEM_ldr_sp
:
24596 case T_MNEM_str_sp
:
24597 newsize
= relax_immediate (fragp
, 8, 2);
24601 newsize
= relax_immediate (fragp
, 5, 2);
24605 newsize
= relax_immediate (fragp
, 5, 1);
24609 newsize
= relax_immediate (fragp
, 5, 0);
24612 newsize
= relax_adr (fragp
, sec
, stretch
);
24618 newsize
= relax_immediate (fragp
, 8, 0);
24621 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
24624 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
24626 case T_MNEM_add_sp
:
24627 case T_MNEM_add_pc
:
24628 newsize
= relax_immediate (fragp
, 8, 2);
24630 case T_MNEM_inc_sp
:
24631 case T_MNEM_dec_sp
:
24632 newsize
= relax_immediate (fragp
, 7, 2);
24638 newsize
= relax_addsub (fragp
, sec
);
24644 fragp
->fr_var
= newsize
;
24645 /* Freeze wide instructions that are at or before the same location as
24646 in the previous pass. This avoids infinite loops.
24647 Don't freeze them unconditionally because targets may be artificially
24648 misaligned by the expansion of preceding frags. */
24649 if (stretch
<= 0 && newsize
> 2)
24651 md_convert_frag (sec
->owner
, sec
, fragp
);
24655 return newsize
- oldsize
;
24658 /* Round up a section size to the appropriate boundary. */
24661 md_section_align (segT segment ATTRIBUTE_UNUSED
,
24667 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
24668 of an rs_align_code fragment. */
24671 arm_handle_align (fragS
* fragP
)
24673 static unsigned char const arm_noop
[2][2][4] =
24676 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
24677 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
24680 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
24681 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
24684 static unsigned char const thumb_noop
[2][2][2] =
24687 {0xc0, 0x46}, /* LE */
24688 {0x46, 0xc0}, /* BE */
24691 {0x00, 0xbf}, /* LE */
24692 {0xbf, 0x00} /* BE */
24695 static unsigned char const wide_thumb_noop
[2][4] =
24696 { /* Wide Thumb-2 */
24697 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
24698 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
24701 unsigned bytes
, fix
, noop_size
;
24703 const unsigned char * noop
;
24704 const unsigned char *narrow_noop
= NULL
;
24709 if (fragP
->fr_type
!= rs_align_code
)
24712 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
24713 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
24716 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24717 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
24719 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
24721 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
24723 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24724 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
24726 narrow_noop
= thumb_noop
[1][target_big_endian
];
24727 noop
= wide_thumb_noop
[target_big_endian
];
24730 noop
= thumb_noop
[0][target_big_endian
];
24738 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24739 ? selected_cpu
: arm_arch_none
,
24741 [target_big_endian
];
24748 fragP
->fr_var
= noop_size
;
24750 if (bytes
& (noop_size
- 1))
24752 fix
= bytes
& (noop_size
- 1);
24754 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
24756 memset (p
, 0, fix
);
24763 if (bytes
& noop_size
)
24765 /* Insert a narrow noop. */
24766 memcpy (p
, narrow_noop
, noop_size
);
24768 bytes
-= noop_size
;
24772 /* Use wide noops for the remainder */
24776 while (bytes
>= noop_size
)
24778 memcpy (p
, noop
, noop_size
);
24780 bytes
-= noop_size
;
24784 fragP
->fr_fix
+= fix
;
24787 /* Called from md_do_align. Used to create an alignment
24788 frag in a code section. */
24791 arm_frag_align_code (int n
, int max
)
24795 /* We assume that there will never be a requirement
24796 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
24797 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24802 _("alignments greater than %d bytes not supported in .text sections."),
24803 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
24804 as_fatal ("%s", err_msg
);
24807 p
= frag_var (rs_align_code
,
24808 MAX_MEM_FOR_RS_ALIGN_CODE
,
24810 (relax_substateT
) max
,
24817 /* Perform target specific initialisation of a frag.
24818 Note - despite the name this initialisation is not done when the frag
24819 is created, but only when its type is assigned. A frag can be created
24820 and used a long time before its type is set, so beware of assuming that
24821 this initialisation is performed first. */
24825 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
24827 /* Record whether this frag is in an ARM or a THUMB area. */
24828 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24831 #else /* OBJ_ELF is defined. */
24833 arm_init_frag (fragS
* fragP
, int max_chars
)
24835 bfd_boolean frag_thumb_mode
;
24837 /* If the current ARM vs THUMB mode has not already
24838 been recorded into this frag then do so now. */
24839 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
24840 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24842 /* PR 21809: Do not set a mapping state for debug sections
24843 - it just confuses other tools. */
24844 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
24847 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
24849 /* Record a mapping symbol for alignment frags. We will delete this
24850 later if the alignment ends up empty. */
24851 switch (fragP
->fr_type
)
24854 case rs_align_test
:
24856 mapping_state_2 (MAP_DATA
, max_chars
);
24858 case rs_align_code
:
24859 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
24866 /* When we change sections we need to issue a new mapping symbol. */
24869 arm_elf_change_section (void)
24871 /* Link an unlinked unwind index table section to the .text section. */
24872 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
24873 && elf_linked_to_section (now_seg
) == NULL
)
24874 elf_linked_to_section (now_seg
) = text_section
;
24878 arm_elf_section_type (const char * str
, size_t len
)
24880 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
24881 return SHT_ARM_EXIDX
;
24886 /* Code to deal with unwinding tables. */
24888 static void add_unwind_adjustsp (offsetT
);
24890 /* Generate any deferred unwind frame offset. */
24893 flush_pending_unwind (void)
24897 offset
= unwind
.pending_offset
;
24898 unwind
.pending_offset
= 0;
24900 add_unwind_adjustsp (offset
);
24903 /* Add an opcode to this list for this function. Two-byte opcodes should
24904 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
24908 add_unwind_opcode (valueT op
, int length
)
24910 /* Add any deferred stack adjustment. */
24911 if (unwind
.pending_offset
)
24912 flush_pending_unwind ();
24914 unwind
.sp_restored
= 0;
24916 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
24918 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
24919 if (unwind
.opcodes
)
24920 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
24921 unwind
.opcode_alloc
);
24923 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
24928 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
24930 unwind
.opcode_count
++;
24934 /* Add unwind opcodes to adjust the stack pointer. */
24937 add_unwind_adjustsp (offsetT offset
)
24941 if (offset
> 0x200)
24943 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
24948 /* Long form: 0xb2, uleb128. */
24949 /* This might not fit in a word so add the individual bytes,
24950 remembering the list is built in reverse order. */
24951 o
= (valueT
) ((offset
- 0x204) >> 2);
24953 add_unwind_opcode (0, 1);
24955 /* Calculate the uleb128 encoding of the offset. */
24959 bytes
[n
] = o
& 0x7f;
24965 /* Add the insn. */
24967 add_unwind_opcode (bytes
[n
- 1], 1);
24968 add_unwind_opcode (0xb2, 1);
24970 else if (offset
> 0x100)
24972 /* Two short opcodes. */
24973 add_unwind_opcode (0x3f, 1);
24974 op
= (offset
- 0x104) >> 2;
24975 add_unwind_opcode (op
, 1);
24977 else if (offset
> 0)
24979 /* Short opcode. */
24980 op
= (offset
- 4) >> 2;
24981 add_unwind_opcode (op
, 1);
24983 else if (offset
< 0)
24986 while (offset
> 0x100)
24988 add_unwind_opcode (0x7f, 1);
24991 op
= ((offset
- 4) >> 2) | 0x40;
24992 add_unwind_opcode (op
, 1);
24996 /* Finish the list of unwind opcodes for this function. */
24999 finish_unwind_opcodes (void)
25003 if (unwind
.fp_used
)
25005 /* Adjust sp as necessary. */
25006 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
25007 flush_pending_unwind ();
25009 /* After restoring sp from the frame pointer. */
25010 op
= 0x90 | unwind
.fp_reg
;
25011 add_unwind_opcode (op
, 1);
25014 flush_pending_unwind ();
25018 /* Start an exception table entry. If idx is nonzero this is an index table
25022 start_unwind_section (const segT text_seg
, int idx
)
25024 const char * text_name
;
25025 const char * prefix
;
25026 const char * prefix_once
;
25027 const char * group_name
;
25035 prefix
= ELF_STRING_ARM_unwind
;
25036 prefix_once
= ELF_STRING_ARM_unwind_once
;
25037 type
= SHT_ARM_EXIDX
;
25041 prefix
= ELF_STRING_ARM_unwind_info
;
25042 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
25043 type
= SHT_PROGBITS
;
25046 text_name
= segment_name (text_seg
);
25047 if (streq (text_name
, ".text"))
25050 if (strncmp (text_name
, ".gnu.linkonce.t.",
25051 strlen (".gnu.linkonce.t.")) == 0)
25053 prefix
= prefix_once
;
25054 text_name
+= strlen (".gnu.linkonce.t.");
25057 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
25063 /* Handle COMDAT group. */
25064 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
25066 group_name
= elf_group_name (text_seg
);
25067 if (group_name
== NULL
)
25069 as_bad (_("Group section `%s' has no group signature"),
25070 segment_name (text_seg
));
25071 ignore_rest_of_line ();
25074 flags
|= SHF_GROUP
;
25078 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
25081 /* Set the section link for index tables. */
25083 elf_linked_to_section (now_seg
) = text_seg
;
25087 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25088 personality routine data. Returns zero, or the index table value for
25089 an inline entry. */
25092 create_unwind_entry (int have_data
)
25097 /* The current word of data. */
25099 /* The number of bytes left in this word. */
25102 finish_unwind_opcodes ();
25104 /* Remember the current text section. */
25105 unwind
.saved_seg
= now_seg
;
25106 unwind
.saved_subseg
= now_subseg
;
25108 start_unwind_section (now_seg
, 0);
25110 if (unwind
.personality_routine
== NULL
)
25112 if (unwind
.personality_index
== -2)
25115 as_bad (_("handlerdata in cantunwind frame"));
25116 return 1; /* EXIDX_CANTUNWIND. */
25119 /* Use a default personality routine if none is specified. */
25120 if (unwind
.personality_index
== -1)
25122 if (unwind
.opcode_count
> 3)
25123 unwind
.personality_index
= 1;
25125 unwind
.personality_index
= 0;
25128 /* Space for the personality routine entry. */
25129 if (unwind
.personality_index
== 0)
25131 if (unwind
.opcode_count
> 3)
25132 as_bad (_("too many unwind opcodes for personality routine 0"));
25136 /* All the data is inline in the index table. */
25139 while (unwind
.opcode_count
> 0)
25141 unwind
.opcode_count
--;
25142 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25146 /* Pad with "finish" opcodes. */
25148 data
= (data
<< 8) | 0xb0;
25155 /* We get two opcodes "free" in the first word. */
25156 size
= unwind
.opcode_count
- 2;
25160 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25161 if (unwind
.personality_index
!= -1)
25163 as_bad (_("attempt to recreate an unwind entry"));
25167 /* An extra byte is required for the opcode count. */
25168 size
= unwind
.opcode_count
+ 1;
25171 size
= (size
+ 3) >> 2;
25173 as_bad (_("too many unwind opcodes"));
25175 frag_align (2, 0, 0);
25176 record_alignment (now_seg
, 2);
25177 unwind
.table_entry
= expr_build_dot ();
25179 /* Allocate the table entry. */
25180 ptr
= frag_more ((size
<< 2) + 4);
25181 /* PR 13449: Zero the table entries in case some of them are not used. */
25182 memset (ptr
, 0, (size
<< 2) + 4);
25183 where
= frag_now_fix () - ((size
<< 2) + 4);
25185 switch (unwind
.personality_index
)
25188 /* ??? Should this be a PLT generating relocation? */
25189 /* Custom personality routine. */
25190 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
25191 BFD_RELOC_ARM_PREL31
);
25196 /* Set the first byte to the number of additional words. */
25197 data
= size
> 0 ? size
- 1 : 0;
25201 /* ABI defined personality routines. */
25203 /* Three opcodes bytes are packed into the first word. */
25210 /* The size and first two opcode bytes go in the first word. */
25211 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
25216 /* Should never happen. */
25220 /* Pack the opcodes into words (MSB first), reversing the list at the same
25222 while (unwind
.opcode_count
> 0)
25226 md_number_to_chars (ptr
, data
, 4);
25231 unwind
.opcode_count
--;
25233 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25236 /* Finish off the last word. */
25239 /* Pad with "finish" opcodes. */
25241 data
= (data
<< 8) | 0xb0;
25243 md_number_to_chars (ptr
, data
, 4);
25248 /* Add an empty descriptor if there is no user-specified data. */
25249 ptr
= frag_more (4);
25250 md_number_to_chars (ptr
, 0, 4);
25257 /* Initialize the DWARF-2 unwind information for this procedure. */
25260 tc_arm_frame_initial_instructions (void)
25262 cfi_add_CFA_def_cfa (REG_SP
, 0);
25264 #endif /* OBJ_ELF */
25266 /* Convert REGNAME to a DWARF-2 register number. */
25269 tc_arm_regname_to_dw2regnum (char *regname
)
25271 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
25275 /* PR 16694: Allow VFP registers as well. */
25276 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
25280 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
25289 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
25293 exp
.X_op
= O_secrel
;
25294 exp
.X_add_symbol
= symbol
;
25295 exp
.X_add_number
= 0;
25296 emit_expr (&exp
, size
);
25300 /* MD interface: Symbol and relocation handling. */
25302 /* Return the address within the segment that a PC-relative fixup is
25303 relative to. For ARM, PC-relative fixups applied to instructions
25304 are generally relative to the location of the fixup plus 8 bytes.
25305 Thumb branches are offset by 4, and Thumb loads relative to PC
25306 require special handling. */
25309 md_pcrel_from_section (fixS
* fixP
, segT seg
)
25311 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25313 /* If this is pc-relative and we are going to emit a relocation
25314 then we just want to put out any pipeline compensation that the linker
25315 will need. Otherwise we want to use the calculated base.
25316 For WinCE we skip the bias for externals as well, since this
25317 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25319 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25320 || (arm_force_relocation (fixP
)
25322 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
25328 switch (fixP
->fx_r_type
)
25330 /* PC relative addressing on the Thumb is slightly odd as the
25331 bottom two bits of the PC are forced to zero for the
25332 calculation. This happens *after* application of the
25333 pipeline offset. However, Thumb adrl already adjusts for
25334 this, so we need not do it again. */
25335 case BFD_RELOC_ARM_THUMB_ADD
:
25338 case BFD_RELOC_ARM_THUMB_OFFSET
:
25339 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25340 case BFD_RELOC_ARM_T32_ADD_PC12
:
25341 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
25342 return (base
+ 4) & ~3;
25344 /* Thumb branches are simply offset by +4. */
25345 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25346 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25347 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25348 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25349 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25350 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25351 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25352 case BFD_RELOC_ARM_THUMB_BF17
:
25353 case BFD_RELOC_ARM_THUMB_BF19
:
25354 case BFD_RELOC_ARM_THUMB_BF13
:
25355 case BFD_RELOC_ARM_THUMB_LOOP12
:
25358 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25360 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25361 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25362 && ARM_IS_FUNC (fixP
->fx_addsy
)
25363 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25364 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25367 /* BLX is like branches above, but forces the low two bits of PC to
25369 case BFD_RELOC_THUMB_PCREL_BLX
:
25371 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25372 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25373 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25374 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25375 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25376 return (base
+ 4) & ~3;
25378 /* ARM mode branches are offset by +8. However, the Windows CE
25379 loader expects the relocation not to take this into account. */
25380 case BFD_RELOC_ARM_PCREL_BLX
:
25382 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25383 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25384 && ARM_IS_FUNC (fixP
->fx_addsy
)
25385 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25386 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25389 case BFD_RELOC_ARM_PCREL_CALL
:
25391 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25392 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25393 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25394 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25395 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25398 case BFD_RELOC_ARM_PCREL_BRANCH
:
25399 case BFD_RELOC_ARM_PCREL_JUMP
:
25400 case BFD_RELOC_ARM_PLT32
:
25402 /* When handling fixups immediately, because we have already
25403 discovered the value of a symbol, or the address of the frag involved
25404 we must account for the offset by +8, as the OS loader will never see the reloc.
25405 see fixup_segment() in write.c
25406 The S_IS_EXTERNAL test handles the case of global symbols.
25407 Those need the calculated base, not just the pipe compensation the linker will need. */
25409 && fixP
->fx_addsy
!= NULL
25410 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25411 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
25419 /* ARM mode loads relative to PC are also offset by +8. Unlike
25420 branches, the Windows CE loader *does* expect the relocation
25421 to take this into account. */
25422 case BFD_RELOC_ARM_OFFSET_IMM
:
25423 case BFD_RELOC_ARM_OFFSET_IMM8
:
25424 case BFD_RELOC_ARM_HWLITERAL
:
25425 case BFD_RELOC_ARM_LITERAL
:
25426 case BFD_RELOC_ARM_CP_OFF_IMM
:
25430 /* Other PC-relative relocations are un-offset. */
25436 static bfd_boolean flag_warn_syms
= TRUE
;
25439 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
25441 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25442 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25443 does mean that the resulting code might be very confusing to the reader.
25444 Also this warning can be triggered if the user omits an operand before
25445 an immediate address, eg:
25449 GAS treats this as an assignment of the value of the symbol foo to a
25450 symbol LDR, and so (without this code) it will not issue any kind of
25451 warning or error message.
25453 Note - ARM instructions are case-insensitive but the strings in the hash
25454 table are all stored in lower case, so we must first ensure that name is
25456 if (flag_warn_syms
&& arm_ops_hsh
)
25458 char * nbuf
= strdup (name
);
25461 for (p
= nbuf
; *p
; p
++)
25463 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
25465 static struct hash_control
* already_warned
= NULL
;
25467 if (already_warned
== NULL
)
25468 already_warned
= hash_new ();
25469 /* Only warn about the symbol once. To keep the code
25470 simple we let hash_insert do the lookup for us. */
25471 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
25472 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
25481 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
25482 Otherwise we have no need to default values of symbols. */
25485 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
25488 if (name
[0] == '_' && name
[1] == 'G'
25489 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
25493 if (symbol_find (name
))
25494 as_bad (_("GOT already in the symbol table"));
25496 GOT_symbol
= symbol_new (name
, undefined_section
,
25497 (valueT
) 0, & zero_address_frag
);
25507 /* Subroutine of md_apply_fix. Check to see if an immediate can be
25508 computed as two separate immediate values, added together. We
25509 already know that this value cannot be computed by just one ARM
25512 static unsigned int
25513 validate_immediate_twopart (unsigned int val
,
25514 unsigned int * highpart
)
25519 for (i
= 0; i
< 32; i
+= 2)
25520 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
25526 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
25528 else if (a
& 0xff0000)
25530 if (a
& 0xff000000)
25532 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
25536 gas_assert (a
& 0xff000000);
25537 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
25540 return (a
& 0xff) | (i
<< 7);
25547 validate_offset_imm (unsigned int val
, int hwse
)
25549 if ((hwse
&& val
> 255) || val
> 4095)
25554 /* Subroutine of md_apply_fix. Do those data_ops which can take a
25555 negative immediate constant by altering the instruction. A bit of
25560 by inverting the second operand, and
25563 by negating the second operand. */
25566 negate_data_op (unsigned long * instruction
,
25567 unsigned long value
)
25570 unsigned long negated
, inverted
;
25572 negated
= encode_arm_immediate (-value
);
25573 inverted
= encode_arm_immediate (~value
);
25575 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
25578 /* First negates. */
25579 case OPCODE_SUB
: /* ADD <-> SUB */
25580 new_inst
= OPCODE_ADD
;
25585 new_inst
= OPCODE_SUB
;
25589 case OPCODE_CMP
: /* CMP <-> CMN */
25590 new_inst
= OPCODE_CMN
;
25595 new_inst
= OPCODE_CMP
;
25599 /* Now Inverted ops. */
25600 case OPCODE_MOV
: /* MOV <-> MVN */
25601 new_inst
= OPCODE_MVN
;
25606 new_inst
= OPCODE_MOV
;
25610 case OPCODE_AND
: /* AND <-> BIC */
25611 new_inst
= OPCODE_BIC
;
25616 new_inst
= OPCODE_AND
;
25620 case OPCODE_ADC
: /* ADC <-> SBC */
25621 new_inst
= OPCODE_SBC
;
25626 new_inst
= OPCODE_ADC
;
25630 /* We cannot do anything. */
25635 if (value
== (unsigned) FAIL
)
25638 *instruction
&= OPCODE_MASK
;
25639 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
25643 /* Like negate_data_op, but for Thumb-2. */
25645 static unsigned int
25646 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
25650 unsigned int negated
, inverted
;
25652 negated
= encode_thumb32_immediate (-value
);
25653 inverted
= encode_thumb32_immediate (~value
);
25655 rd
= (*instruction
>> 8) & 0xf;
25656 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
25659 /* ADD <-> SUB. Includes CMP <-> CMN. */
25660 case T2_OPCODE_SUB
:
25661 new_inst
= T2_OPCODE_ADD
;
25665 case T2_OPCODE_ADD
:
25666 new_inst
= T2_OPCODE_SUB
;
25670 /* ORR <-> ORN. Includes MOV <-> MVN. */
25671 case T2_OPCODE_ORR
:
25672 new_inst
= T2_OPCODE_ORN
;
25676 case T2_OPCODE_ORN
:
25677 new_inst
= T2_OPCODE_ORR
;
25681 /* AND <-> BIC. TST has no inverted equivalent. */
25682 case T2_OPCODE_AND
:
25683 new_inst
= T2_OPCODE_BIC
;
25690 case T2_OPCODE_BIC
:
25691 new_inst
= T2_OPCODE_AND
;
25696 case T2_OPCODE_ADC
:
25697 new_inst
= T2_OPCODE_SBC
;
25701 case T2_OPCODE_SBC
:
25702 new_inst
= T2_OPCODE_ADC
;
25706 /* We cannot do anything. */
25711 if (value
== (unsigned int)FAIL
)
25714 *instruction
&= T2_OPCODE_MASK
;
25715 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
25719 /* Read a 32-bit thumb instruction from buf. */
25721 static unsigned long
25722 get_thumb32_insn (char * buf
)
25724 unsigned long insn
;
25725 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
25726 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25731 /* We usually want to set the low bit on the address of thumb function
25732 symbols. In particular .word foo - . should have the low bit set.
25733 Generic code tries to fold the difference of two symbols to
25734 a constant. Prevent this and force a relocation when the first symbols
25735 is a thumb function. */
25738 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
25740 if (op
== O_subtract
25741 && l
->X_op
== O_symbol
25742 && r
->X_op
== O_symbol
25743 && THUMB_IS_FUNC (l
->X_add_symbol
))
25745 l
->X_op
= O_subtract
;
25746 l
->X_op_symbol
= r
->X_add_symbol
;
25747 l
->X_add_number
-= r
->X_add_number
;
25751 /* Process as normal. */
25755 /* Encode Thumb2 unconditional branches and calls. The encoding
25756 for the 2 are identical for the immediate values. */
25759 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
25761 #define T2I1I2MASK ((1 << 13) | (1 << 11))
25764 addressT S
, I1
, I2
, lo
, hi
;
25766 S
= (value
>> 24) & 0x01;
25767 I1
= (value
>> 23) & 0x01;
25768 I2
= (value
>> 22) & 0x01;
25769 hi
= (value
>> 12) & 0x3ff;
25770 lo
= (value
>> 1) & 0x7ff;
25771 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25772 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25773 newval
|= (S
<< 10) | hi
;
25774 newval2
&= ~T2I1I2MASK
;
25775 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
25776 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25777 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25781 md_apply_fix (fixS
* fixP
,
25785 offsetT value
= * valP
;
25787 unsigned int newimm
;
25788 unsigned long temp
;
25790 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
25792 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
25794 /* Note whether this will delete the relocation. */
25796 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
25799 /* On a 64-bit host, silently truncate 'value' to 32 bits for
25800 consistency with the behaviour on 32-bit hosts. Remember value
25802 value
&= 0xffffffff;
25803 value
^= 0x80000000;
25804 value
-= 0x80000000;
25807 fixP
->fx_addnumber
= value
;
25809 /* Same treatment for fixP->fx_offset. */
25810 fixP
->fx_offset
&= 0xffffffff;
25811 fixP
->fx_offset
^= 0x80000000;
25812 fixP
->fx_offset
-= 0x80000000;
25814 switch (fixP
->fx_r_type
)
25816 case BFD_RELOC_NONE
:
25817 /* This will need to go in the object file. */
25821 case BFD_RELOC_ARM_IMMEDIATE
:
25822 /* We claim that this fixup has been processed here,
25823 even if in fact we generate an error because we do
25824 not have a reloc for it, so tc_gen_reloc will reject it. */
25827 if (fixP
->fx_addsy
)
25829 const char *msg
= 0;
25831 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25832 msg
= _("undefined symbol %s used as an immediate value");
25833 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25834 msg
= _("symbol %s is in a different section");
25835 else if (S_IS_WEAK (fixP
->fx_addsy
))
25836 msg
= _("symbol %s is weak and may be overridden later");
25840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25841 msg
, S_GET_NAME (fixP
->fx_addsy
));
25846 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25848 /* If the offset is negative, we should use encoding A2 for ADR. */
25849 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
25850 newimm
= negate_data_op (&temp
, value
);
25853 newimm
= encode_arm_immediate (value
);
25855 /* If the instruction will fail, see if we can fix things up by
25856 changing the opcode. */
25857 if (newimm
== (unsigned int) FAIL
)
25858 newimm
= negate_data_op (&temp
, value
);
25859 /* MOV accepts both ARM modified immediate (A1 encoding) and
25860 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
25861 When disassembling, MOV is preferred when there is no encoding
25863 if (newimm
== (unsigned int) FAIL
25864 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
25865 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
25866 && !((temp
>> SBIT_SHIFT
) & 0x1)
25867 && value
>= 0 && value
<= 0xffff)
25869 /* Clear bits[23:20] to change encoding from A1 to A2. */
25870 temp
&= 0xff0fffff;
25871 /* Encoding high 4bits imm. Code below will encode the remaining
25873 temp
|= (value
& 0x0000f000) << 4;
25874 newimm
= value
& 0x00000fff;
25878 if (newimm
== (unsigned int) FAIL
)
25880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25881 _("invalid constant (%lx) after fixup"),
25882 (unsigned long) value
);
25886 newimm
|= (temp
& 0xfffff000);
25887 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25890 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25892 unsigned int highpart
= 0;
25893 unsigned int newinsn
= 0xe1a00000; /* nop. */
25895 if (fixP
->fx_addsy
)
25897 const char *msg
= 0;
25899 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25900 msg
= _("undefined symbol %s used as an immediate value");
25901 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25902 msg
= _("symbol %s is in a different section");
25903 else if (S_IS_WEAK (fixP
->fx_addsy
))
25904 msg
= _("symbol %s is weak and may be overridden later");
25908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25909 msg
, S_GET_NAME (fixP
->fx_addsy
));
25914 newimm
= encode_arm_immediate (value
);
25915 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25917 /* If the instruction will fail, see if we can fix things up by
25918 changing the opcode. */
25919 if (newimm
== (unsigned int) FAIL
25920 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
25922 /* No ? OK - try using two ADD instructions to generate
25924 newimm
= validate_immediate_twopart (value
, & highpart
);
25926 /* Yes - then make sure that the second instruction is
25928 if (newimm
!= (unsigned int) FAIL
)
25930 /* Still No ? Try using a negated value. */
25931 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
25932 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
25933 /* Otherwise - give up. */
25936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25937 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
25942 /* Replace the first operand in the 2nd instruction (which
25943 is the PC) with the destination register. We have
25944 already added in the PC in the first instruction and we
25945 do not want to do it again. */
25946 newinsn
&= ~ 0xf0000;
25947 newinsn
|= ((newinsn
& 0x0f000) << 4);
25950 newimm
|= (temp
& 0xfffff000);
25951 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25953 highpart
|= (newinsn
& 0xfffff000);
25954 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
25958 case BFD_RELOC_ARM_OFFSET_IMM
:
25959 if (!fixP
->fx_done
&& seg
->use_rela_p
)
25961 /* Fall through. */
25963 case BFD_RELOC_ARM_LITERAL
:
25969 if (validate_offset_imm (value
, 0) == FAIL
)
25971 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
25972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25973 _("invalid literal constant: pool needs to be closer"));
25975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25976 _("bad immediate value for offset (%ld)"),
25981 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25983 newval
&= 0xfffff000;
25986 newval
&= 0xff7ff000;
25987 newval
|= value
| (sign
? INDEX_UP
: 0);
25989 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25992 case BFD_RELOC_ARM_OFFSET_IMM8
:
25993 case BFD_RELOC_ARM_HWLITERAL
:
25999 if (validate_offset_imm (value
, 1) == FAIL
)
26001 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
26002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26003 _("invalid literal constant: pool needs to be closer"));
26005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26006 _("bad immediate value for 8-bit offset (%ld)"),
26011 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26013 newval
&= 0xfffff0f0;
26016 newval
&= 0xff7ff0f0;
26017 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
26019 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26022 case BFD_RELOC_ARM_T32_OFFSET_U8
:
26023 if (value
< 0 || value
> 1020 || value
% 4 != 0)
26024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26025 _("bad immediate value for offset (%ld)"), (long) value
);
26028 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
26030 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
26033 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26034 /* This is a complicated relocation used for all varieties of Thumb32
26035 load/store instruction with immediate offset:
26037 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26038 *4, optional writeback(W)
26039 (doubleword load/store)
26041 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26042 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26043 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26044 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26045 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26047 Uppercase letters indicate bits that are already encoded at
26048 this point. Lowercase letters are our problem. For the
26049 second block of instructions, the secondary opcode nybble
26050 (bits 8..11) is present, and bit 23 is zero, even if this is
26051 a PC-relative operation. */
26052 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26054 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
26056 if ((newval
& 0xf0000000) == 0xe0000000)
26058 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26060 newval
|= (1 << 23);
26063 if (value
% 4 != 0)
26065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26066 _("offset not a multiple of 4"));
26072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26073 _("offset out of range"));
26078 else if ((newval
& 0x000f0000) == 0x000f0000)
26080 /* PC-relative, 12-bit offset. */
26082 newval
|= (1 << 23);
26087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26088 _("offset out of range"));
26093 else if ((newval
& 0x00000100) == 0x00000100)
26095 /* Writeback: 8-bit, +/- offset. */
26097 newval
|= (1 << 9);
26102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26103 _("offset out of range"));
26108 else if ((newval
& 0x00000f00) == 0x00000e00)
26110 /* T-instruction: positive 8-bit offset. */
26111 if (value
< 0 || value
> 0xff)
26113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26114 _("offset out of range"));
26122 /* Positive 12-bit or negative 8-bit offset. */
26126 newval
|= (1 << 23);
26136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26137 _("offset out of range"));
26144 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
26145 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
26148 case BFD_RELOC_ARM_SHIFT_IMM
:
26149 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26150 if (((unsigned long) value
) > 32
26152 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
26154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26155 _("shift expression is too large"));
26160 /* Shifts of zero must be done as lsl. */
26162 else if (value
== 32)
26164 newval
&= 0xfffff07f;
26165 newval
|= (value
& 0x1f) << 7;
26166 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26169 case BFD_RELOC_ARM_T32_IMMEDIATE
:
26170 case BFD_RELOC_ARM_T32_ADD_IMM
:
26171 case BFD_RELOC_ARM_T32_IMM12
:
26172 case BFD_RELOC_ARM_T32_ADD_PC12
:
26173 /* We claim that this fixup has been processed here,
26174 even if in fact we generate an error because we do
26175 not have a reloc for it, so tc_gen_reloc will reject it. */
26179 && ! S_IS_DEFINED (fixP
->fx_addsy
))
26181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26182 _("undefined symbol %s used as an immediate value"),
26183 S_GET_NAME (fixP
->fx_addsy
));
26187 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26189 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
26192 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26193 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26194 Thumb2 modified immediate encoding (T2). */
26195 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
26196 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26198 newimm
= encode_thumb32_immediate (value
);
26199 if (newimm
== (unsigned int) FAIL
)
26200 newimm
= thumb32_negate_data_op (&newval
, value
);
26202 if (newimm
== (unsigned int) FAIL
)
26204 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
26206 /* Turn add/sum into addw/subw. */
26207 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26208 newval
= (newval
& 0xfeffffff) | 0x02000000;
26209 /* No flat 12-bit imm encoding for addsw/subsw. */
26210 if ((newval
& 0x00100000) == 0)
26212 /* 12 bit immediate for addw/subw. */
26216 newval
^= 0x00a00000;
26219 newimm
= (unsigned int) FAIL
;
26226 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26227 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26228 disassembling, MOV is preferred when there is no encoding
26230 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
26231 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26232 but with the Rn field [19:16] set to 1111. */
26233 && (((newval
>> 16) & 0xf) == 0xf)
26234 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
26235 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
26236 && value
>= 0 && value
<= 0xffff)
26238 /* Toggle bit[25] to change encoding from T2 to T3. */
26240 /* Clear bits[19:16]. */
26241 newval
&= 0xfff0ffff;
26242 /* Encoding high 4bits imm. Code below will encode the
26243 remaining low 12bits. */
26244 newval
|= (value
& 0x0000f000) << 4;
26245 newimm
= value
& 0x00000fff;
26250 if (newimm
== (unsigned int)FAIL
)
26252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26253 _("invalid constant (%lx) after fixup"),
26254 (unsigned long) value
);
26258 newval
|= (newimm
& 0x800) << 15;
26259 newval
|= (newimm
& 0x700) << 4;
26260 newval
|= (newimm
& 0x0ff);
26262 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
26263 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
26266 case BFD_RELOC_ARM_SMC
:
26267 if (((unsigned long) value
) > 0xffff)
26268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26269 _("invalid smc expression"));
26270 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26271 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26272 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26275 case BFD_RELOC_ARM_HVC
:
26276 if (((unsigned long) value
) > 0xffff)
26277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26278 _("invalid hvc expression"));
26279 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26280 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26281 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26284 case BFD_RELOC_ARM_SWI
:
26285 if (fixP
->tc_fix_data
!= 0)
26287 if (((unsigned long) value
) > 0xff)
26288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26289 _("invalid swi expression"));
26290 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26292 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26296 if (((unsigned long) value
) > 0x00ffffff)
26297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26298 _("invalid swi expression"));
26299 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26301 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26305 case BFD_RELOC_ARM_MULTI
:
26306 if (((unsigned long) value
) > 0xffff)
26307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26308 _("invalid expression in load/store multiple"));
26309 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
26310 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26314 case BFD_RELOC_ARM_PCREL_CALL
:
26316 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26318 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26319 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26320 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26321 /* Flip the bl to blx. This is a simple flip
26322 bit here because we generate PCREL_CALL for
26323 unconditional bls. */
26325 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26326 newval
= newval
| 0x10000000;
26327 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26333 goto arm_branch_common
;
26335 case BFD_RELOC_ARM_PCREL_JUMP
:
26336 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26338 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26339 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26340 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26342 /* This would map to a bl<cond>, b<cond>,
26343 b<always> to a Thumb function. We
26344 need to force a relocation for this particular
26346 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26349 /* Fall through. */
26351 case BFD_RELOC_ARM_PLT32
:
26353 case BFD_RELOC_ARM_PCREL_BRANCH
:
26355 goto arm_branch_common
;
26357 case BFD_RELOC_ARM_PCREL_BLX
:
26360 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26362 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26363 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26364 && ARM_IS_FUNC (fixP
->fx_addsy
))
26366 /* Flip the blx to a bl and warn. */
26367 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26368 newval
= 0xeb000000;
26369 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26370 _("blx to '%s' an ARM ISA state function changed to bl"),
26372 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26378 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
26379 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
26383 /* We are going to store value (shifted right by two) in the
26384 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26385 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26389 _("misaligned branch destination"));
26390 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
26391 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
26392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26394 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26396 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26397 newval
|= (value
>> 2) & 0x00ffffff;
26398 /* Set the H bit on BLX instructions. */
26402 newval
|= 0x01000000;
26404 newval
&= ~0x01000000;
26406 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26410 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
26411 /* CBZ can only branch forward. */
26413 /* Attempts to use CBZ to branch to the next instruction
26414 (which, strictly speaking, are prohibited) will be turned into
26417 FIXME: It may be better to remove the instruction completely and
26418 perform relaxation. */
26421 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26422 newval
= 0xbf00; /* NOP encoding T1 */
26423 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26430 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26432 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26433 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
26434 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26439 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
26440 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
26441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26443 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26445 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26446 newval
|= (value
& 0x1ff) >> 1;
26447 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26451 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
26452 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
26453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26455 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26458 newval
|= (value
& 0xfff) >> 1;
26459 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26463 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26465 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26466 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26467 && ARM_IS_FUNC (fixP
->fx_addsy
)
26468 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26470 /* Force a relocation for a branch 20 bits wide. */
26473 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
26474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26475 _("conditional branch out of range"));
26477 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26480 addressT S
, J1
, J2
, lo
, hi
;
26482 S
= (value
& 0x00100000) >> 20;
26483 J2
= (value
& 0x00080000) >> 19;
26484 J1
= (value
& 0x00040000) >> 18;
26485 hi
= (value
& 0x0003f000) >> 12;
26486 lo
= (value
& 0x00000ffe) >> 1;
26488 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26489 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26490 newval
|= (S
<< 10) | hi
;
26491 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
26492 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26493 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26497 case BFD_RELOC_THUMB_PCREL_BLX
:
26498 /* If there is a blx from a thumb state function to
26499 another thumb function flip this to a bl and warn
26503 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26504 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26505 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26507 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26508 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26509 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
26511 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26512 newval
= newval
| 0x1000;
26513 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26514 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26519 goto thumb_bl_common
;
26521 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26522 /* A bl from Thumb state ISA to an internal ARM state function
26523 is converted to a blx. */
26525 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26526 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26527 && ARM_IS_FUNC (fixP
->fx_addsy
)
26528 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26530 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26531 newval
= newval
& ~0x1000;
26532 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26533 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
26539 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26540 /* For a BLX instruction, make sure that the relocation is rounded up
26541 to a word boundary. This follows the semantics of the instruction
26542 which specifies that bit 1 of the target address will come from bit
26543 1 of the base address. */
26544 value
= (value
+ 3) & ~ 3;
26547 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
26548 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26549 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26552 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
26554 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
26555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26556 else if ((value
& ~0x1ffffff)
26557 && ((value
& ~0x1ffffff) != ~0x1ffffff))
26558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26559 _("Thumb2 branch out of range"));
26562 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26563 encode_thumb2_b_bl_offset (buf
, value
);
26567 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26568 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
26569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26571 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26572 encode_thumb2_b_bl_offset (buf
, value
);
26577 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26582 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26583 md_number_to_chars (buf
, value
, 2);
26587 case BFD_RELOC_ARM_TLS_CALL
:
26588 case BFD_RELOC_ARM_THM_TLS_CALL
:
26589 case BFD_RELOC_ARM_TLS_DESCSEQ
:
26590 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
26591 case BFD_RELOC_ARM_TLS_GOTDESC
:
26592 case BFD_RELOC_ARM_TLS_GD32
:
26593 case BFD_RELOC_ARM_TLS_LE32
:
26594 case BFD_RELOC_ARM_TLS_IE32
:
26595 case BFD_RELOC_ARM_TLS_LDM32
:
26596 case BFD_RELOC_ARM_TLS_LDO32
:
26597 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26600 /* Same handling as above, but with the arm_fdpic guard. */
26601 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
26602 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
26603 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
26606 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26611 _("Relocation supported only in FDPIC mode"));
26615 case BFD_RELOC_ARM_GOT32
:
26616 case BFD_RELOC_ARM_GOTOFF
:
26619 case BFD_RELOC_ARM_GOT_PREL
:
26620 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26621 md_number_to_chars (buf
, value
, 4);
26624 case BFD_RELOC_ARM_TARGET2
:
26625 /* TARGET2 is not partial-inplace, so we need to write the
26626 addend here for REL targets, because it won't be written out
26627 during reloc processing later. */
26628 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26629 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
26632 /* Relocations for FDPIC. */
26633 case BFD_RELOC_ARM_GOTFUNCDESC
:
26634 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
26635 case BFD_RELOC_ARM_FUNCDESC
:
26638 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26639 md_number_to_chars (buf
, 0, 4);
26643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26644 _("Relocation supported only in FDPIC mode"));
26649 case BFD_RELOC_RVA
:
26651 case BFD_RELOC_ARM_TARGET1
:
26652 case BFD_RELOC_ARM_ROSEGREL32
:
26653 case BFD_RELOC_ARM_SBREL32
:
26654 case BFD_RELOC_32_PCREL
:
26656 case BFD_RELOC_32_SECREL
:
26658 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26660 /* For WinCE we only do this for pcrel fixups. */
26661 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
26663 md_number_to_chars (buf
, value
, 4);
26667 case BFD_RELOC_ARM_PREL31
:
26668 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26670 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
26671 if ((value
^ (value
>> 1)) & 0x40000000)
26673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26674 _("rel31 relocation overflow"));
26676 newval
|= value
& 0x7fffffff;
26677 md_number_to_chars (buf
, newval
, 4);
26682 case BFD_RELOC_ARM_CP_OFF_IMM
:
26683 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26684 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
26685 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
26686 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26688 newval
= get_thumb32_insn (buf
);
26689 if ((newval
& 0x0f200f00) == 0x0d000900)
26691 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
26692 has permitted values that are multiples of 2, in the range 0
26694 if (value
< -510 || value
> 510 || (value
& 1))
26695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26696 _("co-processor offset out of range"));
26698 else if ((newval
& 0xfe001f80) == 0xec000f80)
26700 if (value
< -511 || value
> 512 || (value
& 3))
26701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26702 _("co-processor offset out of range"));
26704 else if (value
< -1023 || value
> 1023 || (value
& 3))
26705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26706 _("co-processor offset out of range"));
26711 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26712 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26713 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26715 newval
= get_thumb32_insn (buf
);
26718 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26719 newval
&= 0xffffff80;
26721 newval
&= 0xffffff00;
26725 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26726 newval
&= 0xff7fff80;
26728 newval
&= 0xff7fff00;
26729 if ((newval
& 0x0f200f00) == 0x0d000900)
26731 /* This is a fp16 vstr/vldr.
26733 It requires the immediate offset in the instruction is shifted
26734 left by 1 to be a half-word offset.
26736 Here, left shift by 1 first, and later right shift by 2
26737 should get the right offset. */
26740 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
26742 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26743 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26744 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26746 put_thumb32_insn (buf
, newval
);
26749 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
26750 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
26751 if (value
< -255 || value
> 255)
26752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26753 _("co-processor offset out of range"));
26755 goto cp_off_common
;
26757 case BFD_RELOC_ARM_THUMB_OFFSET
:
26758 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26759 /* Exactly what ranges, and where the offset is inserted depends
26760 on the type of instruction, we can establish this from the
26762 switch (newval
>> 12)
26764 case 4: /* PC load. */
26765 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
26766 forced to zero for these loads; md_pcrel_from has already
26767 compensated for this. */
26769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26770 _("invalid offset, target not word aligned (0x%08lX)"),
26771 (((unsigned long) fixP
->fx_frag
->fr_address
26772 + (unsigned long) fixP
->fx_where
) & ~3)
26773 + (unsigned long) value
);
26775 if (value
& ~0x3fc)
26776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26777 _("invalid offset, value too big (0x%08lX)"),
26780 newval
|= value
>> 2;
26783 case 9: /* SP load/store. */
26784 if (value
& ~0x3fc)
26785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26786 _("invalid offset, value too big (0x%08lX)"),
26788 newval
|= value
>> 2;
26791 case 6: /* Word load/store. */
26793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26794 _("invalid offset, value too big (0x%08lX)"),
26796 newval
|= value
<< 4; /* 6 - 2. */
26799 case 7: /* Byte load/store. */
26801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26802 _("invalid offset, value too big (0x%08lX)"),
26804 newval
|= value
<< 6;
26807 case 8: /* Halfword load/store. */
26809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26810 _("invalid offset, value too big (0x%08lX)"),
26812 newval
|= value
<< 5; /* 6 - 1. */
26816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26817 "Unable to process relocation for thumb opcode: %lx",
26818 (unsigned long) newval
);
26821 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26824 case BFD_RELOC_ARM_THUMB_ADD
:
26825 /* This is a complicated relocation, since we use it for all of
26826 the following immediate relocations:
26830 9bit ADD/SUB SP word-aligned
26831 10bit ADD PC/SP word-aligned
26833 The type of instruction being processed is encoded in the
26840 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26842 int rd
= (newval
>> 4) & 0xf;
26843 int rs
= newval
& 0xf;
26844 int subtract
= !!(newval
& 0x8000);
26846 /* Check for HI regs, only very restricted cases allowed:
26847 Adjusting SP, and using PC or SP to get an address. */
26848 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
26849 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
26850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26851 _("invalid Hi register with immediate"));
26853 /* If value is negative, choose the opposite instruction. */
26857 subtract
= !subtract
;
26859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26860 _("immediate value out of range"));
26865 if (value
& ~0x1fc)
26866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26867 _("invalid immediate for stack address calculation"));
26868 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
26869 newval
|= value
>> 2;
26871 else if (rs
== REG_PC
|| rs
== REG_SP
)
26873 /* PR gas/18541. If the addition is for a defined symbol
26874 within range of an ADR instruction then accept it. */
26877 && fixP
->fx_addsy
!= NULL
)
26881 if (! S_IS_DEFINED (fixP
->fx_addsy
)
26882 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
26883 || S_IS_WEAK (fixP
->fx_addsy
))
26885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26886 _("address calculation needs a strongly defined nearby symbol"));
26890 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26892 /* Round up to the next 4-byte boundary. */
26897 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
26901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26902 _("symbol too far away"));
26912 if (subtract
|| value
& ~0x3fc)
26913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26914 _("invalid immediate for address calculation (value = 0x%08lX)"),
26915 (unsigned long) (subtract
? - value
: value
));
26916 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
26918 newval
|= value
>> 2;
26923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26924 _("immediate value out of range"));
26925 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
26926 newval
|= (rd
<< 8) | value
;
26931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26932 _("immediate value out of range"));
26933 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
26934 newval
|= rd
| (rs
<< 3) | (value
<< 6);
26937 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26940 case BFD_RELOC_ARM_THUMB_IMM
:
26941 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26942 if (value
< 0 || value
> 255)
26943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26944 _("invalid immediate: %ld is out of range"),
26947 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26950 case BFD_RELOC_ARM_THUMB_SHIFT
:
26951 /* 5bit shift value (0..32). LSL cannot take 32. */
26952 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
26953 temp
= newval
& 0xf800;
26954 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
26955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26956 _("invalid shift value: %ld"), (long) value
);
26957 /* Shifts of zero must be encoded as LSL. */
26959 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
26960 /* Shifts of 32 are encoded as zero. */
26961 else if (value
== 32)
26963 newval
|= value
<< 6;
26964 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26967 case BFD_RELOC_VTABLE_INHERIT
:
26968 case BFD_RELOC_VTABLE_ENTRY
:
26972 case BFD_RELOC_ARM_MOVW
:
26973 case BFD_RELOC_ARM_MOVT
:
26974 case BFD_RELOC_ARM_THUMB_MOVW
:
26975 case BFD_RELOC_ARM_THUMB_MOVT
:
26976 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26978 /* REL format relocations are limited to a 16-bit addend. */
26979 if (!fixP
->fx_done
)
26981 if (value
< -0x8000 || value
> 0x7fff)
26982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26983 _("offset out of range"));
26985 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
26986 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26991 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
26992 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26994 newval
= get_thumb32_insn (buf
);
26995 newval
&= 0xfbf08f00;
26996 newval
|= (value
& 0xf000) << 4;
26997 newval
|= (value
& 0x0800) << 15;
26998 newval
|= (value
& 0x0700) << 4;
26999 newval
|= (value
& 0x00ff);
27000 put_thumb32_insn (buf
, newval
);
27004 newval
= md_chars_to_number (buf
, 4);
27005 newval
&= 0xfff0f000;
27006 newval
|= value
& 0x0fff;
27007 newval
|= (value
& 0xf000) << 4;
27008 md_number_to_chars (buf
, newval
, 4);
27013 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27014 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27015 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27016 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27017 gas_assert (!fixP
->fx_done
);
27020 bfd_boolean is_mov
;
27021 bfd_vma encoded_addend
= value
;
27023 /* Check that addend can be encoded in instruction. */
27024 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
27025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27026 _("the offset 0x%08lX is not representable"),
27027 (unsigned long) encoded_addend
);
27029 /* Extract the instruction. */
27030 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
27031 is_mov
= (insn
& 0xf800) == 0x2000;
27036 if (!seg
->use_rela_p
)
27037 insn
|= encoded_addend
;
27043 /* Extract the instruction. */
27044 /* Encoding is the following
27049 /* The following conditions must be true :
27054 rd
= (insn
>> 4) & 0xf;
27056 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
27057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27058 _("Unable to process relocation for thumb opcode: %lx"),
27059 (unsigned long) insn
);
27061 /* Encode as ADD immediate8 thumb 1 code. */
27062 insn
= 0x3000 | (rd
<< 8);
27064 /* Place the encoded addend into the first 8 bits of the
27066 if (!seg
->use_rela_p
)
27067 insn
|= encoded_addend
;
27070 /* Update the instruction. */
27071 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
27075 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27076 case BFD_RELOC_ARM_ALU_PC_G0
:
27077 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27078 case BFD_RELOC_ARM_ALU_PC_G1
:
27079 case BFD_RELOC_ARM_ALU_PC_G2
:
27080 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27081 case BFD_RELOC_ARM_ALU_SB_G0
:
27082 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27083 case BFD_RELOC_ARM_ALU_SB_G1
:
27084 case BFD_RELOC_ARM_ALU_SB_G2
:
27085 gas_assert (!fixP
->fx_done
);
27086 if (!seg
->use_rela_p
)
27089 bfd_vma encoded_addend
;
27090 bfd_vma addend_abs
= llabs (value
);
27092 /* Check that the absolute value of the addend can be
27093 expressed as an 8-bit constant plus a rotation. */
27094 encoded_addend
= encode_arm_immediate (addend_abs
);
27095 if (encoded_addend
== (unsigned int) FAIL
)
27096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27097 _("the offset 0x%08lX is not representable"),
27098 (unsigned long) addend_abs
);
27100 /* Extract the instruction. */
27101 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27103 /* If the addend is positive, use an ADD instruction.
27104 Otherwise use a SUB. Take care not to destroy the S bit. */
27105 insn
&= 0xff1fffff;
27111 /* Place the encoded addend into the first 12 bits of the
27113 insn
&= 0xfffff000;
27114 insn
|= encoded_addend
;
27116 /* Update the instruction. */
27117 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27121 case BFD_RELOC_ARM_LDR_PC_G0
:
27122 case BFD_RELOC_ARM_LDR_PC_G1
:
27123 case BFD_RELOC_ARM_LDR_PC_G2
:
27124 case BFD_RELOC_ARM_LDR_SB_G0
:
27125 case BFD_RELOC_ARM_LDR_SB_G1
:
27126 case BFD_RELOC_ARM_LDR_SB_G2
:
27127 gas_assert (!fixP
->fx_done
);
27128 if (!seg
->use_rela_p
)
27131 bfd_vma addend_abs
= llabs (value
);
27133 /* Check that the absolute value of the addend can be
27134 encoded in 12 bits. */
27135 if (addend_abs
>= 0x1000)
27136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27137 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27138 (unsigned long) addend_abs
);
27140 /* Extract the instruction. */
27141 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27143 /* If the addend is negative, clear bit 23 of the instruction.
27144 Otherwise set it. */
27146 insn
&= ~(1 << 23);
27150 /* Place the absolute value of the addend into the first 12 bits
27151 of the instruction. */
27152 insn
&= 0xfffff000;
27153 insn
|= addend_abs
;
27155 /* Update the instruction. */
27156 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27160 case BFD_RELOC_ARM_LDRS_PC_G0
:
27161 case BFD_RELOC_ARM_LDRS_PC_G1
:
27162 case BFD_RELOC_ARM_LDRS_PC_G2
:
27163 case BFD_RELOC_ARM_LDRS_SB_G0
:
27164 case BFD_RELOC_ARM_LDRS_SB_G1
:
27165 case BFD_RELOC_ARM_LDRS_SB_G2
:
27166 gas_assert (!fixP
->fx_done
);
27167 if (!seg
->use_rela_p
)
27170 bfd_vma addend_abs
= llabs (value
);
27172 /* Check that the absolute value of the addend can be
27173 encoded in 8 bits. */
27174 if (addend_abs
>= 0x100)
27175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27176 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27177 (unsigned long) addend_abs
);
27179 /* Extract the instruction. */
27180 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27182 /* If the addend is negative, clear bit 23 of the instruction.
27183 Otherwise set it. */
27185 insn
&= ~(1 << 23);
27189 /* Place the first four bits of the absolute value of the addend
27190 into the first 4 bits of the instruction, and the remaining
27191 four into bits 8 .. 11. */
27192 insn
&= 0xfffff0f0;
27193 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
27195 /* Update the instruction. */
27196 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27200 case BFD_RELOC_ARM_LDC_PC_G0
:
27201 case BFD_RELOC_ARM_LDC_PC_G1
:
27202 case BFD_RELOC_ARM_LDC_PC_G2
:
27203 case BFD_RELOC_ARM_LDC_SB_G0
:
27204 case BFD_RELOC_ARM_LDC_SB_G1
:
27205 case BFD_RELOC_ARM_LDC_SB_G2
:
27206 gas_assert (!fixP
->fx_done
);
27207 if (!seg
->use_rela_p
)
27210 bfd_vma addend_abs
= llabs (value
);
27212 /* Check that the absolute value of the addend is a multiple of
27213 four and, when divided by four, fits in 8 bits. */
27214 if (addend_abs
& 0x3)
27215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27216 _("bad offset 0x%08lX (must be word-aligned)"),
27217 (unsigned long) addend_abs
);
27219 if ((addend_abs
>> 2) > 0xff)
27220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27221 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27222 (unsigned long) addend_abs
);
27224 /* Extract the instruction. */
27225 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27227 /* If the addend is negative, clear bit 23 of the instruction.
27228 Otherwise set it. */
27230 insn
&= ~(1 << 23);
27234 /* Place the addend (divided by four) into the first eight
27235 bits of the instruction. */
27236 insn
&= 0xfffffff0;
27237 insn
|= addend_abs
>> 2;
27239 /* Update the instruction. */
27240 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27244 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27246 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27247 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27248 && ARM_IS_FUNC (fixP
->fx_addsy
)
27249 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27251 /* Force a relocation for a branch 5 bits wide. */
27254 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
27255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27258 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27260 addressT boff
= value
>> 1;
27262 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27263 newval
|= (boff
<< 7);
27264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27268 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27270 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27271 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27272 && ARM_IS_FUNC (fixP
->fx_addsy
)
27273 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27277 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
27278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27279 _("branch out of range"));
27281 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27283 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27285 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
27286 addressT diff
= value
- boff
;
27290 newval
|= 1 << 1; /* T bit. */
27292 else if (diff
!= 2)
27294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27295 _("out of range label-relative fixup value"));
27297 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27301 case BFD_RELOC_ARM_THUMB_BF17
:
27303 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27304 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27305 && ARM_IS_FUNC (fixP
->fx_addsy
)
27306 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27308 /* Force a relocation for a branch 17 bits wide. */
27312 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
27313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27316 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27319 addressT immA
, immB
, immC
;
27321 immA
= (value
& 0x0001f000) >> 12;
27322 immB
= (value
& 0x00000ffc) >> 2;
27323 immC
= (value
& 0x00000002) >> 1;
27325 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27326 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27328 newval2
|= (immC
<< 11) | (immB
<< 1);
27329 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27330 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27334 case BFD_RELOC_ARM_THUMB_BF19
:
27336 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27337 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27338 && ARM_IS_FUNC (fixP
->fx_addsy
)
27339 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27341 /* Force a relocation for a branch 19 bits wide. */
27345 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
27346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27349 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27352 addressT immA
, immB
, immC
;
27354 immA
= (value
& 0x0007f000) >> 12;
27355 immB
= (value
& 0x00000ffc) >> 2;
27356 immC
= (value
& 0x00000002) >> 1;
27358 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27359 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27361 newval2
|= (immC
<< 11) | (immB
<< 1);
27362 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27363 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27367 case BFD_RELOC_ARM_THUMB_BF13
:
27369 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27370 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27371 && ARM_IS_FUNC (fixP
->fx_addsy
)
27372 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27374 /* Force a relocation for a branch 13 bits wide. */
27378 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
27379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27382 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27385 addressT immA
, immB
, immC
;
27387 immA
= (value
& 0x00001000) >> 12;
27388 immB
= (value
& 0x00000ffc) >> 2;
27389 immC
= (value
& 0x00000002) >> 1;
27391 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27392 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27394 newval2
|= (immC
<< 11) | (immB
<< 1);
27395 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27396 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27400 case BFD_RELOC_ARM_THUMB_LOOP12
:
27402 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27403 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27404 && ARM_IS_FUNC (fixP
->fx_addsy
)
27405 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27407 /* Force a relocation for a branch 12 bits wide. */
27411 bfd_vma insn
= get_thumb32_insn (buf
);
27412 /* le lr, <label> or le <label> */
27413 if (((insn
& 0xffffffff) == 0xf00fc001)
27414 || ((insn
& 0xffffffff) == 0xf02fc001))
27417 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
27418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27420 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27422 addressT imml
, immh
;
27424 immh
= (value
& 0x00000ffc) >> 2;
27425 imml
= (value
& 0x00000002) >> 1;
27427 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27428 newval
|= (imml
<< 11) | (immh
<< 1);
27429 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
27433 case BFD_RELOC_ARM_V4BX
:
27434 /* This will need to go in the object file. */
27438 case BFD_RELOC_UNUSED
:
27440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27441 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
27445 /* Translate internal representation of relocation info to BFD target
27449 tc_gen_reloc (asection
*section
, fixS
*fixp
)
27452 bfd_reloc_code_real_type code
;
27454 reloc
= XNEW (arelent
);
27456 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
27457 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
27458 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
27460 if (fixp
->fx_pcrel
)
27462 if (section
->use_rela_p
)
27463 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
27465 fixp
->fx_offset
= reloc
->address
;
27467 reloc
->addend
= fixp
->fx_offset
;
27469 switch (fixp
->fx_r_type
)
27472 if (fixp
->fx_pcrel
)
27474 code
= BFD_RELOC_8_PCREL
;
27477 /* Fall through. */
27480 if (fixp
->fx_pcrel
)
27482 code
= BFD_RELOC_16_PCREL
;
27485 /* Fall through. */
27488 if (fixp
->fx_pcrel
)
27490 code
= BFD_RELOC_32_PCREL
;
27493 /* Fall through. */
27495 case BFD_RELOC_ARM_MOVW
:
27496 if (fixp
->fx_pcrel
)
27498 code
= BFD_RELOC_ARM_MOVW_PCREL
;
27501 /* Fall through. */
27503 case BFD_RELOC_ARM_MOVT
:
27504 if (fixp
->fx_pcrel
)
27506 code
= BFD_RELOC_ARM_MOVT_PCREL
;
27509 /* Fall through. */
27511 case BFD_RELOC_ARM_THUMB_MOVW
:
27512 if (fixp
->fx_pcrel
)
27514 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
27517 /* Fall through. */
27519 case BFD_RELOC_ARM_THUMB_MOVT
:
27520 if (fixp
->fx_pcrel
)
27522 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
27525 /* Fall through. */
27527 case BFD_RELOC_NONE
:
27528 case BFD_RELOC_ARM_PCREL_BRANCH
:
27529 case BFD_RELOC_ARM_PCREL_BLX
:
27530 case BFD_RELOC_RVA
:
27531 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27532 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27533 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27534 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27535 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27536 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27537 case BFD_RELOC_VTABLE_ENTRY
:
27538 case BFD_RELOC_VTABLE_INHERIT
:
27540 case BFD_RELOC_32_SECREL
:
27542 code
= fixp
->fx_r_type
;
27545 case BFD_RELOC_THUMB_PCREL_BLX
:
27547 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27548 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27551 code
= BFD_RELOC_THUMB_PCREL_BLX
;
27554 case BFD_RELOC_ARM_LITERAL
:
27555 case BFD_RELOC_ARM_HWLITERAL
:
27556 /* If this is called then the a literal has
27557 been referenced across a section boundary. */
27558 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27559 _("literal referenced across section boundary"));
27563 case BFD_RELOC_ARM_TLS_CALL
:
27564 case BFD_RELOC_ARM_THM_TLS_CALL
:
27565 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27566 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27567 case BFD_RELOC_ARM_GOT32
:
27568 case BFD_RELOC_ARM_GOTOFF
:
27569 case BFD_RELOC_ARM_GOT_PREL
:
27570 case BFD_RELOC_ARM_PLT32
:
27571 case BFD_RELOC_ARM_TARGET1
:
27572 case BFD_RELOC_ARM_ROSEGREL32
:
27573 case BFD_RELOC_ARM_SBREL32
:
27574 case BFD_RELOC_ARM_PREL31
:
27575 case BFD_RELOC_ARM_TARGET2
:
27576 case BFD_RELOC_ARM_TLS_LDO32
:
27577 case BFD_RELOC_ARM_PCREL_CALL
:
27578 case BFD_RELOC_ARM_PCREL_JUMP
:
27579 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27580 case BFD_RELOC_ARM_ALU_PC_G0
:
27581 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27582 case BFD_RELOC_ARM_ALU_PC_G1
:
27583 case BFD_RELOC_ARM_ALU_PC_G2
:
27584 case BFD_RELOC_ARM_LDR_PC_G0
:
27585 case BFD_RELOC_ARM_LDR_PC_G1
:
27586 case BFD_RELOC_ARM_LDR_PC_G2
:
27587 case BFD_RELOC_ARM_LDRS_PC_G0
:
27588 case BFD_RELOC_ARM_LDRS_PC_G1
:
27589 case BFD_RELOC_ARM_LDRS_PC_G2
:
27590 case BFD_RELOC_ARM_LDC_PC_G0
:
27591 case BFD_RELOC_ARM_LDC_PC_G1
:
27592 case BFD_RELOC_ARM_LDC_PC_G2
:
27593 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27594 case BFD_RELOC_ARM_ALU_SB_G0
:
27595 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27596 case BFD_RELOC_ARM_ALU_SB_G1
:
27597 case BFD_RELOC_ARM_ALU_SB_G2
:
27598 case BFD_RELOC_ARM_LDR_SB_G0
:
27599 case BFD_RELOC_ARM_LDR_SB_G1
:
27600 case BFD_RELOC_ARM_LDR_SB_G2
:
27601 case BFD_RELOC_ARM_LDRS_SB_G0
:
27602 case BFD_RELOC_ARM_LDRS_SB_G1
:
27603 case BFD_RELOC_ARM_LDRS_SB_G2
:
27604 case BFD_RELOC_ARM_LDC_SB_G0
:
27605 case BFD_RELOC_ARM_LDC_SB_G1
:
27606 case BFD_RELOC_ARM_LDC_SB_G2
:
27607 case BFD_RELOC_ARM_V4BX
:
27608 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27609 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27610 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27611 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27612 case BFD_RELOC_ARM_GOTFUNCDESC
:
27613 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27614 case BFD_RELOC_ARM_FUNCDESC
:
27615 case BFD_RELOC_ARM_THUMB_BF17
:
27616 case BFD_RELOC_ARM_THUMB_BF19
:
27617 case BFD_RELOC_ARM_THUMB_BF13
:
27618 code
= fixp
->fx_r_type
;
27621 case BFD_RELOC_ARM_TLS_GOTDESC
:
27622 case BFD_RELOC_ARM_TLS_GD32
:
27623 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27624 case BFD_RELOC_ARM_TLS_LE32
:
27625 case BFD_RELOC_ARM_TLS_IE32
:
27626 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27627 case BFD_RELOC_ARM_TLS_LDM32
:
27628 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27629 /* BFD will include the symbol's address in the addend.
27630 But we don't want that, so subtract it out again here. */
27631 if (!S_IS_COMMON (fixp
->fx_addsy
))
27632 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
27633 code
= fixp
->fx_r_type
;
27637 case BFD_RELOC_ARM_IMMEDIATE
:
27638 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27639 _("internal relocation (type: IMMEDIATE) not fixed up"));
27642 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27643 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27644 _("ADRL used for a symbol not defined in the same file"));
27647 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27648 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27649 case BFD_RELOC_ARM_THUMB_LOOP12
:
27650 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27651 _("%s used for a symbol not defined in the same file"),
27652 bfd_get_reloc_code_name (fixp
->fx_r_type
));
27655 case BFD_RELOC_ARM_OFFSET_IMM
:
27656 if (section
->use_rela_p
)
27658 code
= fixp
->fx_r_type
;
27662 if (fixp
->fx_addsy
!= NULL
27663 && !S_IS_DEFINED (fixp
->fx_addsy
)
27664 && S_IS_LOCAL (fixp
->fx_addsy
))
27666 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27667 _("undefined local label `%s'"),
27668 S_GET_NAME (fixp
->fx_addsy
));
27672 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27673 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
27680 switch (fixp
->fx_r_type
)
27682 case BFD_RELOC_NONE
: type
= "NONE"; break;
27683 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
27684 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
27685 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
27686 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
27687 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
27688 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
27689 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
27690 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
27691 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
27692 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
27693 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
27694 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
27695 default: type
= _("<unknown>"); break;
27697 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27698 _("cannot represent %s relocation in this object file format"),
27705 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
27707 && fixp
->fx_addsy
== GOT_symbol
)
27709 code
= BFD_RELOC_ARM_GOTPC
;
27710 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
27714 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
27716 if (reloc
->howto
== NULL
)
27718 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27719 _("cannot represent %s relocation in this object file format"),
27720 bfd_get_reloc_code_name (code
));
27724 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
27725 vtable entry to be used in the relocation's section offset. */
27726 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27727 reloc
->address
= fixp
->fx_offset
;
27732 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
27735 cons_fix_new_arm (fragS
* frag
,
27739 bfd_reloc_code_real_type reloc
)
27744 FIXME: @@ Should look at CPU word size. */
27748 reloc
= BFD_RELOC_8
;
27751 reloc
= BFD_RELOC_16
;
27755 reloc
= BFD_RELOC_32
;
27758 reloc
= BFD_RELOC_64
;
27763 if (exp
->X_op
== O_secrel
)
27765 exp
->X_op
= O_symbol
;
27766 reloc
= BFD_RELOC_32_SECREL
;
27770 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
27773 #if defined (OBJ_COFF)
27775 arm_validate_fix (fixS
* fixP
)
27777 /* If the destination of the branch is a defined symbol which does not have
27778 the THUMB_FUNC attribute, then we must be calling a function which has
27779 the (interfacearm) attribute. We look for the Thumb entry point to that
27780 function and change the branch to refer to that function instead. */
27781 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
27782 && fixP
->fx_addsy
!= NULL
27783 && S_IS_DEFINED (fixP
->fx_addsy
)
27784 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
27786 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
27793 arm_force_relocation (struct fix
* fixp
)
27795 #if defined (OBJ_COFF) && defined (TE_PE)
27796 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
27800 /* In case we have a call or a branch to a function in ARM ISA mode from
27801 a thumb function or vice-versa force the relocation. These relocations
27802 are cleared off for some cores that might have blx and simple transformations
27806 switch (fixp
->fx_r_type
)
27808 case BFD_RELOC_ARM_PCREL_JUMP
:
27809 case BFD_RELOC_ARM_PCREL_CALL
:
27810 case BFD_RELOC_THUMB_PCREL_BLX
:
27811 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
27815 case BFD_RELOC_ARM_PCREL_BLX
:
27816 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27817 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27818 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27819 if (ARM_IS_FUNC (fixp
->fx_addsy
))
27828 /* Resolve these relocations even if the symbol is extern or weak.
27829 Technically this is probably wrong due to symbol preemption.
27830 In practice these relocations do not have enough range to be useful
27831 at dynamic link time, and some code (e.g. in the Linux kernel)
27832 expects these references to be resolved. */
27833 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
27834 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
27835 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
27836 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
27837 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27838 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
27839 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
27840 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
27841 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27842 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
27843 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
27844 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
27845 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
27846 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
27849 /* Always leave these relocations for the linker. */
27850 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27851 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27852 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27855 /* Always generate relocations against function symbols. */
27856 if (fixp
->fx_r_type
== BFD_RELOC_32
27858 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
27861 return generic_force_reloc (fixp
);
27864 #if defined (OBJ_ELF) || defined (OBJ_COFF)
27865 /* Relocations against function names must be left unadjusted,
27866 so that the linker can use this information to generate interworking
27867 stubs. The MIPS version of this function
27868 also prevents relocations that are mips-16 specific, but I do not
27869 know why it does this.
27872 There is one other problem that ought to be addressed here, but
27873 which currently is not: Taking the address of a label (rather
27874 than a function) and then later jumping to that address. Such
27875 addresses also ought to have their bottom bit set (assuming that
27876 they reside in Thumb code), but at the moment they will not. */
27879 arm_fix_adjustable (fixS
* fixP
)
27881 if (fixP
->fx_addsy
== NULL
)
27884 /* Preserve relocations against symbols with function type. */
27885 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
27888 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
27889 && fixP
->fx_subsy
== NULL
)
27892 /* We need the symbol name for the VTABLE entries. */
27893 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
27894 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27897 /* Don't allow symbols to be discarded on GOT related relocs. */
27898 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
27899 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
27900 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
27901 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
27902 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
27903 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
27904 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
27905 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
27906 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
27907 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
27908 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
27909 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
27910 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
27911 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
27912 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
27913 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
27914 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
27917 /* Similarly for group relocations. */
27918 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27919 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27920 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27923 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
27924 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
27925 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27926 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
27927 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
27928 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27929 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
27930 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
27931 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
27934 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
27935 offsets, so keep these symbols. */
27936 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
27937 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
27942 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
27946 elf32_arm_target_format (void)
27949 return (target_big_endian
27950 ? "elf32-bigarm-symbian"
27951 : "elf32-littlearm-symbian");
27952 #elif defined (TE_VXWORKS)
27953 return (target_big_endian
27954 ? "elf32-bigarm-vxworks"
27955 : "elf32-littlearm-vxworks");
27956 #elif defined (TE_NACL)
27957 return (target_big_endian
27958 ? "elf32-bigarm-nacl"
27959 : "elf32-littlearm-nacl");
27963 if (target_big_endian
)
27964 return "elf32-bigarm-fdpic";
27966 return "elf32-littlearm-fdpic";
27970 if (target_big_endian
)
27971 return "elf32-bigarm";
27973 return "elf32-littlearm";
27979 armelf_frob_symbol (symbolS
* symp
,
27982 elf_frob_symbol (symp
, puntp
);
27986 /* MD interface: Finalization. */
27991 literal_pool
* pool
;
27993 /* Ensure that all the predication blocks are properly closed. */
27994 check_pred_blocks_finished ();
27996 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
27998 /* Put it at the end of the relevant section. */
27999 subseg_set (pool
->section
, pool
->sub_section
);
28001 arm_elf_change_section ();
28008 /* Remove any excess mapping symbols generated for alignment frags in
28009 SEC. We may have created a mapping symbol before a zero byte
28010 alignment; remove it if there's a mapping symbol after the
28013 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
28014 void *dummy ATTRIBUTE_UNUSED
)
28016 segment_info_type
*seginfo
= seg_info (sec
);
28019 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
28022 for (fragp
= seginfo
->frchainP
->frch_root
;
28024 fragp
= fragp
->fr_next
)
28026 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
28027 fragS
*next
= fragp
->fr_next
;
28029 /* Variable-sized frags have been converted to fixed size by
28030 this point. But if this was variable-sized to start with,
28031 there will be a fixed-size frag after it. So don't handle
28033 if (sym
== NULL
|| next
== NULL
)
28036 if (S_GET_VALUE (sym
) < next
->fr_address
)
28037 /* Not at the end of this frag. */
28039 know (S_GET_VALUE (sym
) == next
->fr_address
);
28043 if (next
->tc_frag_data
.first_map
!= NULL
)
28045 /* Next frag starts with a mapping symbol. Discard this
28047 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28051 if (next
->fr_next
== NULL
)
28053 /* This mapping symbol is at the end of the section. Discard
28055 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
28056 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28060 /* As long as we have empty frags without any mapping symbols,
28062 /* If the next frag is non-empty and does not start with a
28063 mapping symbol, then this mapping symbol is required. */
28064 if (next
->fr_address
!= next
->fr_next
->fr_address
)
28067 next
= next
->fr_next
;
28069 while (next
!= NULL
);
28074 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28078 arm_adjust_symtab (void)
28083 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28085 if (ARM_IS_THUMB (sym
))
28087 if (THUMB_IS_FUNC (sym
))
28089 /* Mark the symbol as a Thumb function. */
28090 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
28091 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
28092 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
28094 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
28095 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
28097 as_bad (_("%s: unexpected function type: %d"),
28098 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
28100 else switch (S_GET_STORAGE_CLASS (sym
))
28103 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
28106 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
28109 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
28117 if (ARM_IS_INTERWORK (sym
))
28118 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
28125 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28127 if (ARM_IS_THUMB (sym
))
28129 elf_symbol_type
* elf_sym
;
28131 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
28132 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
28134 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
28135 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
28137 /* If it's a .thumb_func, declare it as so,
28138 otherwise tag label as .code 16. */
28139 if (THUMB_IS_FUNC (sym
))
28140 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
28141 ST_BRANCH_TO_THUMB
);
28142 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28143 elf_sym
->internal_elf_sym
.st_info
=
28144 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
28149 /* Remove any overlapping mapping symbols generated by alignment frags. */
28150 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
28151 /* Now do generic ELF adjustments. */
28152 elf_adjust_symtab ();
28156 /* MD interface: Initialization. */
28159 set_constant_flonums (void)
28163 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
28164 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
28168 /* Auto-select Thumb mode if it's the only available instruction set for the
28169 given architecture. */
28172 autoselect_thumb_from_cpu_variant (void)
28174 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
28175 opcode_select (16);
28184 if ( (arm_ops_hsh
= hash_new ()) == NULL
28185 || (arm_cond_hsh
= hash_new ()) == NULL
28186 || (arm_vcond_hsh
= hash_new ()) == NULL
28187 || (arm_shift_hsh
= hash_new ()) == NULL
28188 || (arm_psr_hsh
= hash_new ()) == NULL
28189 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
28190 || (arm_reg_hsh
= hash_new ()) == NULL
28191 || (arm_reloc_hsh
= hash_new ()) == NULL
28192 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
28193 as_fatal (_("virtual memory exhausted"));
28195 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
28196 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
28197 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
28198 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
28199 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
28200 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
28201 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
28202 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
28203 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
28204 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
28205 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
28206 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
28207 (void *) (v7m_psrs
+ i
));
28208 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
28209 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
28211 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
28213 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
28214 (void *) (barrier_opt_names
+ i
));
28216 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
28218 struct reloc_entry
* entry
= reloc_names
+ i
;
28220 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
28221 /* This makes encode_branch() use the EABI versions of this relocation. */
28222 entry
->reloc
= BFD_RELOC_UNUSED
;
28224 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
28228 set_constant_flonums ();
28230 /* Set the cpu variant based on the command-line options. We prefer
28231 -mcpu= over -march= if both are set (as for GCC); and we prefer
28232 -mfpu= over any other way of setting the floating point unit.
28233 Use of legacy options with new options are faulted. */
28236 if (mcpu_cpu_opt
|| march_cpu_opt
)
28237 as_bad (_("use of old and new-style options to set CPU type"));
28239 selected_arch
= *legacy_cpu
;
28241 else if (mcpu_cpu_opt
)
28243 selected_arch
= *mcpu_cpu_opt
;
28244 selected_ext
= *mcpu_ext_opt
;
28246 else if (march_cpu_opt
)
28248 selected_arch
= *march_cpu_opt
;
28249 selected_ext
= *march_ext_opt
;
28251 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28256 as_bad (_("use of old and new-style options to set FPU type"));
28258 selected_fpu
= *legacy_fpu
;
28261 selected_fpu
= *mfpu_opt
;
28264 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28265 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28266 /* Some environments specify a default FPU. If they don't, infer it
28267 from the processor. */
28269 selected_fpu
= *mcpu_fpu_opt
;
28270 else if (march_fpu_opt
)
28271 selected_fpu
= *march_fpu_opt
;
28273 selected_fpu
= fpu_default
;
28277 if (ARM_FEATURE_ZERO (selected_fpu
))
28279 if (!no_cpu_selected ())
28280 selected_fpu
= fpu_default
;
28282 selected_fpu
= fpu_arch_fpa
;
28286 if (ARM_FEATURE_ZERO (selected_arch
))
28288 selected_arch
= cpu_default
;
28289 selected_cpu
= selected_arch
;
28291 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28293 /* Autodection of feature mode: allow all features in cpu_variant but leave
28294 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28295 after all instruction have been processed and we can decide what CPU
28296 should be selected. */
28297 if (ARM_FEATURE_ZERO (selected_arch
))
28298 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28300 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28303 autoselect_thumb_from_cpu_variant ();
28305 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
28307 #if defined OBJ_COFF || defined OBJ_ELF
28309 unsigned int flags
= 0;
28311 #if defined OBJ_ELF
28312 flags
= meabi_flags
;
28314 switch (meabi_flags
)
28316 case EF_ARM_EABI_UNKNOWN
:
28318 /* Set the flags in the private structure. */
28319 if (uses_apcs_26
) flags
|= F_APCS26
;
28320 if (support_interwork
) flags
|= F_INTERWORK
;
28321 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
28322 if (pic_code
) flags
|= F_PIC
;
28323 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
28324 flags
|= F_SOFT_FLOAT
;
28326 switch (mfloat_abi_opt
)
28328 case ARM_FLOAT_ABI_SOFT
:
28329 case ARM_FLOAT_ABI_SOFTFP
:
28330 flags
|= F_SOFT_FLOAT
;
28333 case ARM_FLOAT_ABI_HARD
:
28334 if (flags
& F_SOFT_FLOAT
)
28335 as_bad (_("hard-float conflicts with specified fpu"));
28339 /* Using pure-endian doubles (even if soft-float). */
28340 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
28341 flags
|= F_VFP_FLOAT
;
28343 #if defined OBJ_ELF
28344 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
28345 flags
|= EF_ARM_MAVERICK_FLOAT
;
28348 case EF_ARM_EABI_VER4
:
28349 case EF_ARM_EABI_VER5
:
28350 /* No additional flags to set. */
28357 bfd_set_private_flags (stdoutput
, flags
);
28359 /* We have run out flags in the COFF header to encode the
28360 status of ATPCS support, so instead we create a dummy,
28361 empty, debug section called .arm.atpcs. */
28366 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
28370 bfd_set_section_flags
28371 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
28372 bfd_set_section_size (stdoutput
, sec
, 0);
28373 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
28379 /* Record the CPU type as well. */
28380 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
28381 mach
= bfd_mach_arm_iWMMXt2
;
28382 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
28383 mach
= bfd_mach_arm_iWMMXt
;
28384 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
28385 mach
= bfd_mach_arm_XScale
;
28386 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
28387 mach
= bfd_mach_arm_ep9312
;
28388 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
28389 mach
= bfd_mach_arm_5TE
;
28390 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
28392 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28393 mach
= bfd_mach_arm_5T
;
28395 mach
= bfd_mach_arm_5
;
28397 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
28399 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28400 mach
= bfd_mach_arm_4T
;
28402 mach
= bfd_mach_arm_4
;
28404 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
28405 mach
= bfd_mach_arm_3M
;
28406 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
28407 mach
= bfd_mach_arm_3
;
28408 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
28409 mach
= bfd_mach_arm_2a
;
28410 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
28411 mach
= bfd_mach_arm_2
;
28413 mach
= bfd_mach_arm_unknown
;
28415 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
28418 /* Command line processing. */
28421 Invocation line includes a switch not recognized by the base assembler.
28422 See if it's a processor-specific option.
28424 This routine is somewhat complicated by the need for backwards
28425 compatibility (since older releases of gcc can't be changed).
28426 The new options try to make the interface as compatible as
28429 New options (supported) are:
28431 -mcpu=<cpu name> Assemble for selected processor
28432 -march=<architecture name> Assemble for selected architecture
28433 -mfpu=<fpu architecture> Assemble for selected FPU.
28434 -EB/-mbig-endian Big-endian
28435 -EL/-mlittle-endian Little-endian
28436 -k Generate PIC code
28437 -mthumb Start in Thumb mode
28438 -mthumb-interwork Code supports ARM/Thumb interworking
28440 -m[no-]warn-deprecated Warn about deprecated features
28441 -m[no-]warn-syms Warn when symbols match instructions
28443 For now we will also provide support for:
28445 -mapcs-32 32-bit Program counter
28446 -mapcs-26 26-bit Program counter
28447 -macps-float Floats passed in FP registers
28448 -mapcs-reentrant Reentrant code
28450 (sometime these will probably be replaced with -mapcs=<list of options>
28451 and -matpcs=<list of options>)
28453 The remaining options are only supported for back-wards compatibility.
28454 Cpu variants, the arm part is optional:
28455 -m[arm]1 Currently not supported.
28456 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
28457 -m[arm]3 Arm 3 processor
28458 -m[arm]6[xx], Arm 6 processors
28459 -m[arm]7[xx][t][[d]m] Arm 7 processors
28460 -m[arm]8[10] Arm 8 processors
28461 -m[arm]9[20][tdmi] Arm 9 processors
28462 -mstrongarm[110[0]] StrongARM processors
28463 -mxscale XScale processors
28464 -m[arm]v[2345[t[e]]] Arm architectures
28465 -mall All (except the ARM1)
28467 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
28468 -mfpe-old (No float load/store multiples)
28469 -mvfpxd VFP Single precision
28471 -mno-fpu Disable all floating point instructions
28473 The following CPU names are recognized:
28474 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
28475 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
28476 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
28477 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
28478 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
28479 arm10t arm10e, arm1020t, arm1020e, arm10200e,
28480 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
28484 const char * md_shortopts
= "m:k";
28486 #ifdef ARM_BI_ENDIAN
28487 #define OPTION_EB (OPTION_MD_BASE + 0)
28488 #define OPTION_EL (OPTION_MD_BASE + 1)
28490 #if TARGET_BYTES_BIG_ENDIAN
28491 #define OPTION_EB (OPTION_MD_BASE + 0)
28493 #define OPTION_EL (OPTION_MD_BASE + 1)
28496 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
28497 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
28499 struct option md_longopts
[] =
28502 {"EB", no_argument
, NULL
, OPTION_EB
},
28505 {"EL", no_argument
, NULL
, OPTION_EL
},
28507 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
28509 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
28511 {NULL
, no_argument
, NULL
, 0}
28514 size_t md_longopts_size
= sizeof (md_longopts
);
28516 struct arm_option_table
28518 const char * option
; /* Option name to match. */
28519 const char * help
; /* Help information. */
28520 int * var
; /* Variable to change. */
28521 int value
; /* What to change it to. */
28522 const char * deprecated
; /* If non-null, print this message. */
28525 struct arm_option_table arm_opts
[] =
28527 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
28528 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
28529 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
28530 &support_interwork
, 1, NULL
},
28531 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
28532 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
28533 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
28535 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
28536 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
28537 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
28538 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
28541 /* These are recognized by the assembler, but have no affect on code. */
28542 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
28543 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
28545 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
28546 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
28547 &warn_on_deprecated
, 0, NULL
},
28548 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
28549 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
28550 {NULL
, NULL
, NULL
, 0, NULL
}
28553 struct arm_legacy_option_table
28555 const char * option
; /* Option name to match. */
28556 const arm_feature_set
** var
; /* Variable to change. */
28557 const arm_feature_set value
; /* What to change it to. */
28558 const char * deprecated
; /* If non-null, print this message. */
28561 const struct arm_legacy_option_table arm_legacy_opts
[] =
28563 /* DON'T add any new processors to this list -- we want the whole list
28564 to go away... Add them to the processors table instead. */
28565 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28566 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28567 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28568 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28569 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28570 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28571 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28572 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28573 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28574 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28575 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28576 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28577 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28578 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28579 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28580 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28581 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28582 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28583 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28584 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28585 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28586 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28587 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28588 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28589 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28590 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28591 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28592 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28593 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28594 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28595 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28596 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28597 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28598 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28599 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28600 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28601 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28602 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28603 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28604 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28605 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28606 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28607 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28608 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28609 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28610 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28611 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28612 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28613 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28614 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28615 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28616 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28617 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28618 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28619 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28620 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28621 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28622 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28623 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28624 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28625 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28626 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28627 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28628 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28629 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28630 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28631 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28632 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28633 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
28634 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
28635 N_("use -mcpu=strongarm110")},
28636 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
28637 N_("use -mcpu=strongarm1100")},
28638 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
28639 N_("use -mcpu=strongarm1110")},
28640 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
28641 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
28642 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
28644 /* Architecture variants -- don't add any more to this list either. */
28645 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28646 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28647 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28648 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28649 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28650 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28651 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28652 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28653 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28654 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28655 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28656 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28657 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28658 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28659 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28660 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28661 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28662 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28664 /* Floating point variants -- don't add any more to this list either. */
28665 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
28666 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
28667 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
28668 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
28669 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
28671 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
28674 struct arm_cpu_option_table
28678 const arm_feature_set value
;
28679 const arm_feature_set ext
;
28680 /* For some CPUs we assume an FPU unless the user explicitly sets
28682 const arm_feature_set default_fpu
;
28683 /* The canonical name of the CPU, or NULL to use NAME converted to upper
28685 const char * canonical_name
;
28688 /* This list should, at a minimum, contain all the cpu names
28689 recognized by GCC. */
28690 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
28692 static const struct arm_cpu_option_table arm_cpus
[] =
28694 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
28697 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
28700 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
28703 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
28706 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
28709 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
28712 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
28715 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
28718 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
28721 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
28724 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
28727 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
28730 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
28733 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
28736 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
28739 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
28742 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
28745 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
28748 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
28751 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
28754 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
28757 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
28760 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
28763 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
28766 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
28769 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
28772 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
28775 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
28778 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
28781 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
28784 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
28787 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
28790 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
28793 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
28796 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
28799 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
28802 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
28805 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
28808 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
28811 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
28814 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
28817 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
28820 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
28823 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
28826 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
28829 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
28833 /* For V5 or later processors we default to using VFP; but the user
28834 should really set the FPU type explicitly. */
28835 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
28838 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
28841 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28844 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28847 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
28850 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
28853 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
28856 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
28859 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
28862 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
28865 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
28868 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
28871 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
28874 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
28877 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
28880 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
28883 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
28886 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
28889 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
28892 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
28895 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
28898 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
28901 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
28904 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
28907 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
28910 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
28913 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
28916 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
28919 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
28922 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
28925 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
28928 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
28931 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
28934 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
28937 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
28940 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
28943 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
28944 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28946 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
28948 FPU_ARCH_NEON_VFP_V4
),
28949 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
28950 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
28951 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28952 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
28953 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28954 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28955 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
28957 FPU_ARCH_NEON_VFP_V4
),
28958 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
28960 FPU_ARCH_NEON_VFP_V4
),
28961 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
28963 FPU_ARCH_NEON_VFP_V4
),
28964 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
28965 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28966 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28967 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
28968 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28969 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28970 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
28971 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28972 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28973 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
28974 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28975 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28976 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
28977 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28978 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28979 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
28980 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28981 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28982 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
28983 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28984 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28985 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
28986 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28987 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28988 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
28989 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28990 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28991 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
28992 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28993 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28994 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
28997 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
28999 FPU_ARCH_VFP_V3D16
),
29000 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
29001 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29003 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
29004 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29005 FPU_ARCH_VFP_V3D16
),
29006 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
29007 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29008 FPU_ARCH_VFP_V3D16
),
29009 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
29010 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29011 FPU_ARCH_NEON_VFP_ARMV8
),
29012 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
29013 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29015 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
29018 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
29021 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
29024 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
29027 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
29030 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
29033 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
29036 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
29037 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29038 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29039 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
29040 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29041 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29042 /* ??? XSCALE is really an architecture. */
29043 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
29047 /* ??? iwmmxt is not a processor. */
29048 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
29051 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
29054 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
29059 ARM_CPU_OPT ("ep9312", "ARM920T",
29060 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
29061 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
29063 /* Marvell processors. */
29064 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
29065 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29066 FPU_ARCH_VFP_V3D16
),
29067 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
29068 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29069 FPU_ARCH_NEON_VFP_V4
),
29071 /* APM X-Gene family. */
29072 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
29074 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29075 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
29076 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29077 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29079 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29083 struct arm_ext_table
29087 const arm_feature_set merge
;
29088 const arm_feature_set clear
;
29091 struct arm_arch_option_table
29095 const arm_feature_set value
;
29096 const arm_feature_set default_fpu
;
29097 const struct arm_ext_table
* ext_table
;
29100 /* Used to add support for +E and +noE extension. */
29101 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29102 /* Used to add support for a +E extension. */
29103 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29104 /* Used to add support for a +noE extension. */
29105 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29107 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29108 ~0 & ~FPU_ENDIAN_PURE)
29110 static const struct arm_ext_table armv5te_ext_table
[] =
29112 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
29113 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29116 static const struct arm_ext_table armv7_ext_table
[] =
29118 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29119 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29122 static const struct arm_ext_table armv7ve_ext_table
[] =
29124 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
29125 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
29126 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29127 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29128 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29129 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
29130 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29132 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
29133 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29135 /* Aliases for +simd. */
29136 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29138 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29139 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29140 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29142 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29145 static const struct arm_ext_table armv7a_ext_table
[] =
29147 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29148 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29149 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29150 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29151 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29152 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
29153 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29155 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
29156 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29158 /* Aliases for +simd. */
29159 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29160 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29162 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29163 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29165 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
29166 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
29167 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29170 static const struct arm_ext_table armv7r_ext_table
[] =
29172 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
29173 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
29174 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29175 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29176 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
29177 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29178 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29179 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
29180 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29183 static const struct arm_ext_table armv7em_ext_table
[] =
29185 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
29186 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29187 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
29188 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
29189 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29190 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
29191 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29194 static const struct arm_ext_table armv8a_ext_table
[] =
29196 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29197 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29198 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29199 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29201 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29202 should use the +simd option to turn on FP. */
29203 ARM_REMOVE ("fp", ALL_FP
),
29204 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29205 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29206 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29210 static const struct arm_ext_table armv81a_ext_table
[] =
29212 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29213 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29214 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29216 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29217 should use the +simd option to turn on FP. */
29218 ARM_REMOVE ("fp", ALL_FP
),
29219 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29220 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29221 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29224 static const struct arm_ext_table armv82a_ext_table
[] =
29226 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29227 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
29228 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
29229 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29230 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29231 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29233 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29234 should use the +simd option to turn on FP. */
29235 ARM_REMOVE ("fp", ALL_FP
),
29236 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29237 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29238 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29241 static const struct arm_ext_table armv84a_ext_table
[] =
29243 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29244 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29245 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29246 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29248 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29249 should use the +simd option to turn on FP. */
29250 ARM_REMOVE ("fp", ALL_FP
),
29251 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29252 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29253 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29256 static const struct arm_ext_table armv85a_ext_table
[] =
29258 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29259 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29260 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29261 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29263 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29264 should use the +simd option to turn on FP. */
29265 ARM_REMOVE ("fp", ALL_FP
),
29266 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29269 static const struct arm_ext_table armv8m_main_ext_table
[] =
29271 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29272 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29273 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
29274 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29275 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29278 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
29280 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29281 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29283 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29284 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
29287 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29288 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29289 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
29290 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
29292 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29293 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
29294 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29295 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29298 static const struct arm_ext_table armv8r_ext_table
[] =
29300 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29301 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29302 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29303 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29304 ARM_REMOVE ("fp", ALL_FP
),
29305 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
29306 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29309 /* This list should, at a minimum, contain all the architecture names
29310 recognized by GCC. */
29311 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29312 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29313 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29315 static const struct arm_arch_option_table arm_archs
[] =
29317 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
29318 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
29319 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
29320 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29321 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29322 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
29323 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
29324 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
29325 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
29326 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
29327 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
29328 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
29329 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
29330 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
29331 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
29332 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
29333 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
29334 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29335 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29336 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
29337 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
29338 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29339 kept to preserve existing behaviour. */
29340 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29341 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29342 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
29343 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
29344 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
29345 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29346 kept to preserve existing behaviour. */
29347 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29348 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29349 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
29350 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
29351 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
29352 /* The official spelling of the ARMv7 profile variants is the dashed form.
29353 Accept the non-dashed form for compatibility with old toolchains. */
29354 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29355 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
29356 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29357 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29358 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29359 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29360 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29361 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
29362 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
29363 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
29365 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
29367 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
29368 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
29369 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
29370 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
29371 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
29372 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
29373 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
29374 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
29375 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
29376 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
29377 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29379 #undef ARM_ARCH_OPT
29381 /* ISA extensions in the co-processor and main instruction set space. */
29383 struct arm_option_extension_value_table
29387 const arm_feature_set merge_value
;
29388 const arm_feature_set clear_value
;
29389 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29390 indicates that an extension is available for all architectures while
29391 ARM_ANY marks an empty entry. */
29392 const arm_feature_set allowed_archs
[2];
29395 /* The following table must be in alphabetical order with a NULL last entry. */
29397 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29398 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29400 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29401 use the context sensitive approach using arm_ext_table's. */
29402 static const struct arm_option_extension_value_table arm_extensions
[] =
29404 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29405 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29406 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29407 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
29408 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29409 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
29410 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
29412 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29413 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29414 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
29415 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
29416 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29417 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29418 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29420 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29421 | ARM_EXT2_FP16_FML
),
29422 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29423 | ARM_EXT2_FP16_FML
),
29425 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29426 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29427 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29428 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29429 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29430 Thumb divide instruction. Due to this having the same name as the
29431 previous entry, this will be ignored when doing command-line parsing and
29432 only considered by build attribute selection code. */
29433 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29434 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29435 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
29436 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
29437 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
29438 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
29439 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
29440 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
29441 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
29442 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29443 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29444 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29445 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29446 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29447 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29448 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
29449 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
29450 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
29451 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29452 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29453 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29455 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
29456 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
29457 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29458 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
29459 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
29460 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29461 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29462 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29464 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29465 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29466 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
29467 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29468 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
29469 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
29470 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29471 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
29473 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
29474 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29475 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
29476 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
29477 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
29481 /* ISA floating-point and Advanced SIMD extensions. */
29482 struct arm_option_fpu_value_table
29485 const arm_feature_set value
;
29488 /* This list should, at a minimum, contain all the fpu names
29489 recognized by GCC. */
29490 static const struct arm_option_fpu_value_table arm_fpus
[] =
29492 {"softfpa", FPU_NONE
},
29493 {"fpe", FPU_ARCH_FPE
},
29494 {"fpe2", FPU_ARCH_FPE
},
29495 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
29496 {"fpa", FPU_ARCH_FPA
},
29497 {"fpa10", FPU_ARCH_FPA
},
29498 {"fpa11", FPU_ARCH_FPA
},
29499 {"arm7500fe", FPU_ARCH_FPA
},
29500 {"softvfp", FPU_ARCH_VFP
},
29501 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
29502 {"vfp", FPU_ARCH_VFP_V2
},
29503 {"vfp9", FPU_ARCH_VFP_V2
},
29504 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
29505 {"vfp10", FPU_ARCH_VFP_V2
},
29506 {"vfp10-r0", FPU_ARCH_VFP_V1
},
29507 {"vfpxd", FPU_ARCH_VFP_V1xD
},
29508 {"vfpv2", FPU_ARCH_VFP_V2
},
29509 {"vfpv3", FPU_ARCH_VFP_V3
},
29510 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
29511 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
29512 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
29513 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
29514 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
29515 {"arm1020t", FPU_ARCH_VFP_V1
},
29516 {"arm1020e", FPU_ARCH_VFP_V2
},
29517 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
29518 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
29519 {"maverick", FPU_ARCH_MAVERICK
},
29520 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29521 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29522 {"neon-fp16", FPU_ARCH_NEON_FP16
},
29523 {"vfpv4", FPU_ARCH_VFP_V4
},
29524 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
29525 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
29526 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
29527 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
29528 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
29529 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
29530 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
29531 {"crypto-neon-fp-armv8",
29532 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
29533 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
29534 {"crypto-neon-fp-armv8.1",
29535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
29536 {NULL
, ARM_ARCH_NONE
}
29539 struct arm_option_value_table
29545 static const struct arm_option_value_table arm_float_abis
[] =
29547 {"hard", ARM_FLOAT_ABI_HARD
},
29548 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
29549 {"soft", ARM_FLOAT_ABI_SOFT
},
29554 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
29555 static const struct arm_option_value_table arm_eabis
[] =
29557 {"gnu", EF_ARM_EABI_UNKNOWN
},
29558 {"4", EF_ARM_EABI_VER4
},
29559 {"5", EF_ARM_EABI_VER5
},
29564 struct arm_long_option_table
29566 const char * option
; /* Substring to match. */
29567 const char * help
; /* Help information. */
29568 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
29569 const char * deprecated
; /* If non-null, print this message. */
29573 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
29574 arm_feature_set
*ext_set
,
29575 const struct arm_ext_table
*ext_table
)
29577 /* We insist on extensions being specified in alphabetical order, and with
29578 extensions being added before being removed. We achieve this by having
29579 the global ARM_EXTENSIONS table in alphabetical order, and using the
29580 ADDING_VALUE variable to indicate whether we are adding an extension (1)
29581 or removing it (0) and only allowing it to change in the order
29583 const struct arm_option_extension_value_table
* opt
= NULL
;
29584 const arm_feature_set arm_any
= ARM_ANY
;
29585 int adding_value
= -1;
29587 while (str
!= NULL
&& *str
!= 0)
29594 as_bad (_("invalid architectural extension"));
29599 ext
= strchr (str
, '+');
29604 len
= strlen (str
);
29606 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
29608 if (adding_value
!= 0)
29611 opt
= arm_extensions
;
29619 if (adding_value
== -1)
29622 opt
= arm_extensions
;
29624 else if (adding_value
!= 1)
29626 as_bad (_("must specify extensions to add before specifying "
29627 "those to remove"));
29634 as_bad (_("missing architectural extension"));
29638 gas_assert (adding_value
!= -1);
29639 gas_assert (opt
!= NULL
);
29641 if (ext_table
!= NULL
)
29643 const struct arm_ext_table
* ext_opt
= ext_table
;
29644 bfd_boolean found
= FALSE
;
29645 for (; ext_opt
->name
!= NULL
; ext_opt
++)
29646 if (ext_opt
->name_len
== len
29647 && strncmp (ext_opt
->name
, str
, len
) == 0)
29651 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
29652 /* TODO: Option not supported. When we remove the
29653 legacy table this case should error out. */
29656 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
29660 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
29661 /* TODO: Option not supported. When we remove the
29662 legacy table this case should error out. */
29664 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
29676 /* Scan over the options table trying to find an exact match. */
29677 for (; opt
->name
!= NULL
; opt
++)
29678 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29680 int i
, nb_allowed_archs
=
29681 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
29682 /* Check we can apply the extension to this architecture. */
29683 for (i
= 0; i
< nb_allowed_archs
; i
++)
29686 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
29688 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
29691 if (i
== nb_allowed_archs
)
29693 as_bad (_("extension does not apply to the base architecture"));
29697 /* Add or remove the extension. */
29699 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
29701 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
29703 /* Allowing Thumb division instructions for ARMv7 in autodetection
29704 rely on this break so that duplicate extensions (extensions
29705 with the same name as a previous extension in the list) are not
29706 considered for command-line parsing. */
29710 if (opt
->name
== NULL
)
29712 /* Did we fail to find an extension because it wasn't specified in
29713 alphabetical order, or because it does not exist? */
29715 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29716 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29719 if (opt
->name
== NULL
)
29720 as_bad (_("unknown architectural extension `%s'"), str
);
29722 as_bad (_("architectural extensions must be specified in "
29723 "alphabetical order"));
29729 /* We should skip the extension we've just matched the next time
29741 arm_parse_cpu (const char *str
)
29743 const struct arm_cpu_option_table
*opt
;
29744 const char *ext
= strchr (str
, '+');
29750 len
= strlen (str
);
29754 as_bad (_("missing cpu name `%s'"), str
);
29758 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
29759 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29761 mcpu_cpu_opt
= &opt
->value
;
29762 if (mcpu_ext_opt
== NULL
)
29763 mcpu_ext_opt
= XNEW (arm_feature_set
);
29764 *mcpu_ext_opt
= opt
->ext
;
29765 mcpu_fpu_opt
= &opt
->default_fpu
;
29766 if (opt
->canonical_name
)
29768 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
29769 strcpy (selected_cpu_name
, opt
->canonical_name
);
29775 if (len
>= sizeof selected_cpu_name
)
29776 len
= (sizeof selected_cpu_name
) - 1;
29778 for (i
= 0; i
< len
; i
++)
29779 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
29780 selected_cpu_name
[i
] = 0;
29784 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
29789 as_bad (_("unknown cpu `%s'"), str
);
29794 arm_parse_arch (const char *str
)
29796 const struct arm_arch_option_table
*opt
;
29797 const char *ext
= strchr (str
, '+');
29803 len
= strlen (str
);
29807 as_bad (_("missing architecture name `%s'"), str
);
29811 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
29812 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29814 march_cpu_opt
= &opt
->value
;
29815 if (march_ext_opt
== NULL
)
29816 march_ext_opt
= XNEW (arm_feature_set
);
29817 *march_ext_opt
= arm_arch_none
;
29818 march_fpu_opt
= &opt
->default_fpu
;
29819 strcpy (selected_cpu_name
, opt
->name
);
29822 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
29828 as_bad (_("unknown architecture `%s'\n"), str
);
29833 arm_parse_fpu (const char * str
)
29835 const struct arm_option_fpu_value_table
* opt
;
29837 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
29838 if (streq (opt
->name
, str
))
29840 mfpu_opt
= &opt
->value
;
29844 as_bad (_("unknown floating point format `%s'\n"), str
);
29849 arm_parse_float_abi (const char * str
)
29851 const struct arm_option_value_table
* opt
;
29853 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
29854 if (streq (opt
->name
, str
))
29856 mfloat_abi_opt
= opt
->value
;
29860 as_bad (_("unknown floating point abi `%s'\n"), str
);
29866 arm_parse_eabi (const char * str
)
29868 const struct arm_option_value_table
*opt
;
29870 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
29871 if (streq (opt
->name
, str
))
29873 meabi_flags
= opt
->value
;
29876 as_bad (_("unknown EABI `%s'\n"), str
);
29882 arm_parse_it_mode (const char * str
)
29884 bfd_boolean ret
= TRUE
;
29886 if (streq ("arm", str
))
29887 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
29888 else if (streq ("thumb", str
))
29889 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
29890 else if (streq ("always", str
))
29891 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
29892 else if (streq ("never", str
))
29893 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
29896 as_bad (_("unknown implicit IT mode `%s', should be "\
29897 "arm, thumb, always, or never."), str
);
29905 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
29907 codecomposer_syntax
= TRUE
;
29908 arm_comment_chars
[0] = ';';
29909 arm_line_separator_chars
[0] = 0;
29913 struct arm_long_option_table arm_long_opts
[] =
29915 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
29916 arm_parse_cpu
, NULL
},
29917 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
29918 arm_parse_arch
, NULL
},
29919 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
29920 arm_parse_fpu
, NULL
},
29921 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
29922 arm_parse_float_abi
, NULL
},
29924 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
29925 arm_parse_eabi
, NULL
},
29927 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
29928 arm_parse_it_mode
, NULL
},
29929 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
29930 arm_ccs_mode
, NULL
},
29931 {NULL
, NULL
, 0, NULL
}
29935 md_parse_option (int c
, const char * arg
)
29937 struct arm_option_table
*opt
;
29938 const struct arm_legacy_option_table
*fopt
;
29939 struct arm_long_option_table
*lopt
;
29945 target_big_endian
= 1;
29951 target_big_endian
= 0;
29955 case OPTION_FIX_V4BX
:
29963 #endif /* OBJ_ELF */
29966 /* Listing option. Just ignore these, we don't support additional
29971 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
29973 if (c
== opt
->option
[0]
29974 && ((arg
== NULL
&& opt
->option
[1] == 0)
29975 || streq (arg
, opt
->option
+ 1)))
29977 /* If the option is deprecated, tell the user. */
29978 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
29979 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29980 arg
? arg
: "", _(opt
->deprecated
));
29982 if (opt
->var
!= NULL
)
29983 *opt
->var
= opt
->value
;
29989 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
29991 if (c
== fopt
->option
[0]
29992 && ((arg
== NULL
&& fopt
->option
[1] == 0)
29993 || streq (arg
, fopt
->option
+ 1)))
29995 /* If the option is deprecated, tell the user. */
29996 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
29997 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29998 arg
? arg
: "", _(fopt
->deprecated
));
30000 if (fopt
->var
!= NULL
)
30001 *fopt
->var
= &fopt
->value
;
30007 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30009 /* These options are expected to have an argument. */
30010 if (c
== lopt
->option
[0]
30012 && strncmp (arg
, lopt
->option
+ 1,
30013 strlen (lopt
->option
+ 1)) == 0)
30015 /* If the option is deprecated, tell the user. */
30016 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
30017 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
30018 _(lopt
->deprecated
));
30020 /* Call the sup-option parser. */
30021 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
30032 md_show_usage (FILE * fp
)
30034 struct arm_option_table
*opt
;
30035 struct arm_long_option_table
*lopt
;
30037 fprintf (fp
, _(" ARM-specific assembler options:\n"));
30039 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30040 if (opt
->help
!= NULL
)
30041 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
30043 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30044 if (lopt
->help
!= NULL
)
30045 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
30049 -EB assemble code for a big-endian cpu\n"));
30054 -EL assemble code for a little-endian cpu\n"));
30058 --fix-v4bx Allow BX in ARMv4 code\n"));
30062 --fdpic generate an FDPIC object file\n"));
30063 #endif /* OBJ_ELF */
30071 arm_feature_set flags
;
30072 } cpu_arch_ver_table
;
30074 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30075 chronologically for architectures, with an exception for ARMv6-M and
30076 ARMv6S-M due to legacy reasons. No new architecture should have a
30077 special case. This allows for build attribute selection results to be
30078 stable when new architectures are added. */
30079 static const cpu_arch_ver_table cpu_arch_ver
[] =
30081 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
30082 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
30083 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
30084 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
30085 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
30086 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
30087 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
30088 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
30089 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
30090 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
30091 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
30092 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
30093 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
30094 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
30095 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
30096 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
30097 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
30098 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
30099 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
30100 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
30101 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
30102 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
30103 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
30104 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
30106 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30107 always selected build attributes to match those of ARMv6-M
30108 (resp. ARMv6S-M). However, due to these architectures being a strict
30109 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30110 would be selected when fully respecting chronology of architectures.
30111 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30112 move them before ARMv7 architectures. */
30113 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
30114 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
30116 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
30117 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
30118 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
30119 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
30120 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
30121 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
30122 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
30123 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
30124 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
30125 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
30126 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
30127 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
30128 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
30129 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
30130 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
30131 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
30132 {-1, ARM_ARCH_NONE
}
30135 /* Set an attribute if it has not already been set by the user. */
30138 aeabi_set_attribute_int (int tag
, int value
)
30141 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30142 || !attributes_set_explicitly
[tag
])
30143 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
30147 aeabi_set_attribute_string (int tag
, const char *value
)
30150 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30151 || !attributes_set_explicitly
[tag
])
30152 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
30155 /* Return whether features in the *NEEDED feature set are available via
30156 extensions for the architecture whose feature set is *ARCH_FSET. */
30159 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
30160 const arm_feature_set
*needed
)
30162 int i
, nb_allowed_archs
;
30163 arm_feature_set ext_fset
;
30164 const struct arm_option_extension_value_table
*opt
;
30166 ext_fset
= arm_arch_none
;
30167 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30169 /* Extension does not provide any feature we need. */
30170 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
30174 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30175 for (i
= 0; i
< nb_allowed_archs
; i
++)
30178 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
30181 /* Extension is available, add it. */
30182 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
30183 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
30187 /* Can we enable all features in *needed? */
30188 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
30191 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30192 a given architecture feature set *ARCH_EXT_FSET including extension feature
30193 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30194 - if true, check for an exact match of the architecture modulo extensions;
30195 - otherwise, select build attribute value of the first superset
30196 architecture released so that results remains stable when new architectures
30198 For -march/-mcpu=all the build attribute value of the most featureful
30199 architecture is returned. Tag_CPU_arch_profile result is returned in
30203 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
30204 const arm_feature_set
*ext_fset
,
30205 char *profile
, int exact_match
)
30207 arm_feature_set arch_fset
;
30208 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
30210 /* Select most featureful architecture with all its extensions if building
30211 for -march=all as the feature sets used to set build attributes. */
30212 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
30214 /* Force revisiting of decision for each new architecture. */
30215 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30217 return TAG_CPU_ARCH_V8
;
30220 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
30222 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
30224 arm_feature_set known_arch_fset
;
30226 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
30229 /* Base architecture match user-specified architecture and
30230 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30231 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
30236 /* Base architecture match user-specified architecture only
30237 (eg. ARMv6-M in the same case as above). Record it in case we
30238 find a match with above condition. */
30239 else if (p_ver_ret
== NULL
30240 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
30246 /* Architecture has all features wanted. */
30247 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
30249 arm_feature_set added_fset
;
30251 /* Compute features added by this architecture over the one
30252 recorded in p_ver_ret. */
30253 if (p_ver_ret
!= NULL
)
30254 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
30256 /* First architecture that match incl. with extensions, or the
30257 only difference in features over the recorded match is
30258 features that were optional and are now mandatory. */
30259 if (p_ver_ret
== NULL
30260 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
30266 else if (p_ver_ret
== NULL
)
30268 arm_feature_set needed_ext_fset
;
30270 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
30272 /* Architecture has all features needed when using some
30273 extensions. Record it and continue searching in case there
30274 exist an architecture providing all needed features without
30275 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30277 if (have_ext_for_needed_feat_p (&known_arch_fset
,
30284 if (p_ver_ret
== NULL
)
30288 /* Tag_CPU_arch_profile. */
30289 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
30290 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
30291 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
30292 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
30294 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
30296 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
30300 return p_ver_ret
->val
;
30303 /* Set the public EABI object attributes. */
30306 aeabi_set_public_attributes (void)
30308 char profile
= '\0';
30311 int fp16_optional
= 0;
30312 int skip_exact_match
= 0;
30313 arm_feature_set flags
, flags_arch
, flags_ext
;
30315 /* Autodetection mode, choose the architecture based the instructions
30317 if (no_cpu_selected ())
30319 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
30321 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
30322 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
30324 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
30325 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
30327 /* Code run during relaxation relies on selected_cpu being set. */
30328 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30329 flags_ext
= arm_arch_none
;
30330 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
30331 selected_ext
= flags_ext
;
30332 selected_cpu
= flags
;
30334 /* Otherwise, choose the architecture based on the capabilities of the
30338 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
30339 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
30340 flags_ext
= selected_ext
;
30341 flags
= selected_cpu
;
30343 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
30345 /* Allow the user to override the reported architecture. */
30346 if (!ARM_FEATURE_ZERO (selected_object_arch
))
30348 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
30349 flags_ext
= arm_arch_none
;
30352 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
30354 /* When this function is run again after relaxation has happened there is no
30355 way to determine whether an architecture or CPU was specified by the user:
30356 - selected_cpu is set above for relaxation to work;
30357 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30358 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30359 Therefore, if not in -march=all case we first try an exact match and fall
30360 back to autodetection. */
30361 if (!skip_exact_match
)
30362 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
30364 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
30366 as_bad (_("no architecture contains all the instructions used\n"));
30368 /* Tag_CPU_name. */
30369 if (selected_cpu_name
[0])
30373 q
= selected_cpu_name
;
30374 if (strncmp (q
, "armv", 4) == 0)
30379 for (i
= 0; q
[i
]; i
++)
30380 q
[i
] = TOUPPER (q
[i
]);
30382 aeabi_set_attribute_string (Tag_CPU_name
, q
);
30385 /* Tag_CPU_arch. */
30386 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
30388 /* Tag_CPU_arch_profile. */
30389 if (profile
!= '\0')
30390 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
30392 /* Tag_DSP_extension. */
30393 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
30394 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
30396 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30397 /* Tag_ARM_ISA_use. */
30398 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
30399 || ARM_FEATURE_ZERO (flags_arch
))
30400 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
30402 /* Tag_THUMB_ISA_use. */
30403 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
30404 || ARM_FEATURE_ZERO (flags_arch
))
30408 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30409 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
30411 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
30415 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
30418 /* Tag_VFP_arch. */
30419 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
30420 aeabi_set_attribute_int (Tag_VFP_arch
,
30421 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30423 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
30424 aeabi_set_attribute_int (Tag_VFP_arch
,
30425 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30427 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
30430 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
30432 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
30434 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
30437 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
30438 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
30439 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
30440 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
30441 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
30443 /* Tag_ABI_HardFP_use. */
30444 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
30445 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
30446 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
30448 /* Tag_WMMX_arch. */
30449 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
30450 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
30451 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
30452 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
30454 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
30455 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
30456 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
30457 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
30458 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
30459 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
30461 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
30463 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
30467 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
30472 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
30473 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
30474 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
30475 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
30477 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
30478 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
30479 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
30483 We set Tag_DIV_use to two when integer divide instructions have been used
30484 in ARM state, or when Thumb integer divide instructions have been used,
30485 but we have no architecture profile set, nor have we any ARM instructions.
30487 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
30488 by the base architecture.
30490 For new architectures we will have to check these tests. */
30491 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30492 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30493 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
30494 aeabi_set_attribute_int (Tag_DIV_use
, 0);
30495 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
30496 || (profile
== '\0'
30497 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
30498 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
30499 aeabi_set_attribute_int (Tag_DIV_use
, 2);
30501 /* Tag_MP_extension_use. */
30502 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
30503 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
30505 /* Tag Virtualization_use. */
30506 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
30508 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
30511 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
30514 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
30515 finished and free extension feature bits which will not be used anymore. */
30518 arm_md_post_relax (void)
30520 aeabi_set_public_attributes ();
30521 XDELETE (mcpu_ext_opt
);
30522 mcpu_ext_opt
= NULL
;
30523 XDELETE (march_ext_opt
);
30524 march_ext_opt
= NULL
;
30527 /* Add the default contents for the .ARM.attributes section. */
30532 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30535 aeabi_set_public_attributes ();
30537 #endif /* OBJ_ELF */
30539 /* Parse a .cpu directive. */
30542 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
30544 const struct arm_cpu_option_table
*opt
;
30548 name
= input_line_pointer
;
30549 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30550 input_line_pointer
++;
30551 saved_char
= *input_line_pointer
;
30552 *input_line_pointer
= 0;
30554 /* Skip the first "all" entry. */
30555 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
30556 if (streq (opt
->name
, name
))
30558 selected_arch
= opt
->value
;
30559 selected_ext
= opt
->ext
;
30560 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30561 if (opt
->canonical_name
)
30562 strcpy (selected_cpu_name
, opt
->canonical_name
);
30566 for (i
= 0; opt
->name
[i
]; i
++)
30567 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30569 selected_cpu_name
[i
] = 0;
30571 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30573 *input_line_pointer
= saved_char
;
30574 demand_empty_rest_of_line ();
30577 as_bad (_("unknown cpu `%s'"), name
);
30578 *input_line_pointer
= saved_char
;
30579 ignore_rest_of_line ();
30582 /* Parse a .arch directive. */
30585 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
30587 const struct arm_arch_option_table
*opt
;
30591 name
= input_line_pointer
;
30592 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30593 input_line_pointer
++;
30594 saved_char
= *input_line_pointer
;
30595 *input_line_pointer
= 0;
30597 /* Skip the first "all" entry. */
30598 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30599 if (streq (opt
->name
, name
))
30601 selected_arch
= opt
->value
;
30602 selected_ext
= arm_arch_none
;
30603 selected_cpu
= selected_arch
;
30604 strcpy (selected_cpu_name
, opt
->name
);
30605 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30606 *input_line_pointer
= saved_char
;
30607 demand_empty_rest_of_line ();
30611 as_bad (_("unknown architecture `%s'\n"), name
);
30612 *input_line_pointer
= saved_char
;
30613 ignore_rest_of_line ();
30616 /* Parse a .object_arch directive. */
30619 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
30621 const struct arm_arch_option_table
*opt
;
30625 name
= input_line_pointer
;
30626 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30627 input_line_pointer
++;
30628 saved_char
= *input_line_pointer
;
30629 *input_line_pointer
= 0;
30631 /* Skip the first "all" entry. */
30632 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30633 if (streq (opt
->name
, name
))
30635 selected_object_arch
= opt
->value
;
30636 *input_line_pointer
= saved_char
;
30637 demand_empty_rest_of_line ();
30641 as_bad (_("unknown architecture `%s'\n"), name
);
30642 *input_line_pointer
= saved_char
;
30643 ignore_rest_of_line ();
30646 /* Parse a .arch_extension directive. */
30649 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
30651 const struct arm_option_extension_value_table
*opt
;
30654 int adding_value
= 1;
30656 name
= input_line_pointer
;
30657 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30658 input_line_pointer
++;
30659 saved_char
= *input_line_pointer
;
30660 *input_line_pointer
= 0;
30662 if (strlen (name
) >= 2
30663 && strncmp (name
, "no", 2) == 0)
30669 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30670 if (streq (opt
->name
, name
))
30672 int i
, nb_allowed_archs
=
30673 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
30674 for (i
= 0; i
< nb_allowed_archs
; i
++)
30677 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
30679 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
30683 if (i
== nb_allowed_archs
)
30685 as_bad (_("architectural extension `%s' is not allowed for the "
30686 "current base architecture"), name
);
30691 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
30694 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
30696 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30697 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30698 *input_line_pointer
= saved_char
;
30699 demand_empty_rest_of_line ();
30700 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
30701 on this return so that duplicate extensions (extensions with the
30702 same name as a previous extension in the list) are not considered
30703 for command-line parsing. */
30707 if (opt
->name
== NULL
)
30708 as_bad (_("unknown architecture extension `%s'\n"), name
);
30710 *input_line_pointer
= saved_char
;
30711 ignore_rest_of_line ();
30714 /* Parse a .fpu directive. */
30717 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
30719 const struct arm_option_fpu_value_table
*opt
;
30723 name
= input_line_pointer
;
30724 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30725 input_line_pointer
++;
30726 saved_char
= *input_line_pointer
;
30727 *input_line_pointer
= 0;
30729 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30730 if (streq (opt
->name
, name
))
30732 selected_fpu
= opt
->value
;
30733 #ifndef CPU_DEFAULT
30734 if (no_cpu_selected ())
30735 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30738 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30739 *input_line_pointer
= saved_char
;
30740 demand_empty_rest_of_line ();
30744 as_bad (_("unknown floating point format `%s'\n"), name
);
30745 *input_line_pointer
= saved_char
;
30746 ignore_rest_of_line ();
30749 /* Copy symbol information. */
30752 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
30754 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
30758 /* Given a symbolic attribute NAME, return the proper integer value.
30759 Returns -1 if the attribute is not known. */
30762 arm_convert_symbolic_attribute (const char *name
)
30764 static const struct
30769 attribute_table
[] =
30771 /* When you modify this table you should
30772 also modify the list in doc/c-arm.texi. */
30773 #define T(tag) {#tag, tag}
30774 T (Tag_CPU_raw_name
),
30777 T (Tag_CPU_arch_profile
),
30778 T (Tag_ARM_ISA_use
),
30779 T (Tag_THUMB_ISA_use
),
30783 T (Tag_Advanced_SIMD_arch
),
30784 T (Tag_PCS_config
),
30785 T (Tag_ABI_PCS_R9_use
),
30786 T (Tag_ABI_PCS_RW_data
),
30787 T (Tag_ABI_PCS_RO_data
),
30788 T (Tag_ABI_PCS_GOT_use
),
30789 T (Tag_ABI_PCS_wchar_t
),
30790 T (Tag_ABI_FP_rounding
),
30791 T (Tag_ABI_FP_denormal
),
30792 T (Tag_ABI_FP_exceptions
),
30793 T (Tag_ABI_FP_user_exceptions
),
30794 T (Tag_ABI_FP_number_model
),
30795 T (Tag_ABI_align_needed
),
30796 T (Tag_ABI_align8_needed
),
30797 T (Tag_ABI_align_preserved
),
30798 T (Tag_ABI_align8_preserved
),
30799 T (Tag_ABI_enum_size
),
30800 T (Tag_ABI_HardFP_use
),
30801 T (Tag_ABI_VFP_args
),
30802 T (Tag_ABI_WMMX_args
),
30803 T (Tag_ABI_optimization_goals
),
30804 T (Tag_ABI_FP_optimization_goals
),
30805 T (Tag_compatibility
),
30806 T (Tag_CPU_unaligned_access
),
30807 T (Tag_FP_HP_extension
),
30808 T (Tag_VFP_HP_extension
),
30809 T (Tag_ABI_FP_16bit_format
),
30810 T (Tag_MPextension_use
),
30812 T (Tag_nodefaults
),
30813 T (Tag_also_compatible_with
),
30814 T (Tag_conformance
),
30816 T (Tag_Virtualization_use
),
30817 T (Tag_DSP_extension
),
30819 /* We deliberately do not include Tag_MPextension_use_legacy. */
30827 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
30828 if (streq (name
, attribute_table
[i
].name
))
30829 return attribute_table
[i
].tag
;
30834 /* Apply sym value for relocations only in the case that they are for
30835 local symbols in the same segment as the fixup and you have the
30836 respective architectural feature for blx and simple switches. */
30839 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
30842 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
30843 /* PR 17444: If the local symbol is in a different section then a reloc
30844 will always be generated for it, so applying the symbol value now
30845 will result in a double offset being stored in the relocation. */
30846 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
30847 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
30849 switch (fixP
->fx_r_type
)
30851 case BFD_RELOC_ARM_PCREL_BLX
:
30852 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30853 if (ARM_IS_FUNC (fixP
->fx_addsy
))
30857 case BFD_RELOC_ARM_PCREL_CALL
:
30858 case BFD_RELOC_THUMB_PCREL_BLX
:
30859 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
30870 #endif /* OBJ_ELF */