projects / deliverable / binutils-gdb.git / blob
? search:


1cb36116e476a378f4d122f459a680a5a7b8bdff
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #include <string.h>
25 #define NO_RELOC 0
26 #include "as.h"
27 #include "safe-ctype.h"
28
29 /* Need TARGET_CPU. */
30 #include "config.h"
31 #include "subsegs.h"
32 #include "obstack.h"
33 #include "symbols.h"
34 #include "listing.h"
35
36 #ifdef OBJ_ELF
37 #include "elf/arm.h"
38 #include "dwarf2dbg.h"
39 #endif
40
41 /* Types of processor to assemble for. */
42 #define ARM_1 0x00000001
43 #define ARM_2 0x00000002
44 #define ARM_3 0x00000004
45 #define ARM_250 ARM_3
46 #define ARM_6 0x00000008
47 #define ARM_7 ARM_6 /* Same core instruction set. */
48 #define ARM_8 ARM_6 /* Same core instruction set. */
49 #define ARM_9 ARM_6 /* Same core instruction set. */
50 #define ARM_CPU_MASK 0x0000000f
51
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
54 #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
55 #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
56 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
58 #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
59
60 /* Architectures are the sum of the base and extensions. */
61 #define ARM_ARCH_V3M ARM_EXT_LONGMUL
62 #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
63 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
64 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
65 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
66 #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
67 #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
68
69 /* Some useful combinations: */
70 #define ARM_ANY 0x00ffffff
71 #define ARM_2UP (ARM_ANY - ARM_1)
72 #define ARM_ALL ARM_2UP /* Not arm1 only. */
73 #define ARM_3UP 0x00fffffc
74 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
75
76 #define FPU_CORE 0x80000000
77 #define FPU_FPA10 0x40000000
78 #define FPU_FPA11 0x40000000
79 #define FPU_NONE 0
80
81 /* Some useful combinations. */
82 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
83 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
84
85 #ifndef CPU_DEFAULT
86 #if defined __XSCALE__
87 #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
88 #else
89 #if defined __thumb__
90 #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
91 #else
92 #define CPU_DEFAULT ARM_ALL
93 #endif
94 #endif
95 #endif
96
97 #ifndef FPU_DEFAULT
98 #define FPU_DEFAULT FPU_ALL
99 #endif
100
101 #define streq(a, b) (strcmp (a, b) == 0)
102 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
103
104 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
105 static int target_oabi = 0;
106
107 #if defined OBJ_COFF || defined OBJ_ELF
108 /* Flags stored in private area of BFD structure. */
109 static boolean uses_apcs_26 = false;
110 static boolean atpcs = false;
111 static boolean support_interwork = false;
112 static boolean uses_apcs_float = false;
113 static boolean pic_code = false;
114 #endif
115
116 /* This array holds the chars that always start a comment. If the
117 pre-processor is disabled, these aren't very useful. */
118 CONST char comment_chars[] = "@";
119
120 /* This array holds the chars that only start a comment at the beginning of
121 a line. If the line seems to have the form '# 123 filename'
122 .line and .file directives will appear in the pre-processed output. */
123 /* Note that input_file.c hand checks for '#' at the beginning of the
124 first line of the input file. This is because the compiler outputs
125 #NO_APP at the beginning of its output. */
126 /* Also note that comments like this one will always work. */
127 CONST char line_comment_chars[] = "#";
128
129 CONST char line_separator_chars[] = ";";
130
131 /* Chars that can be used to separate mant
132 from exp in floating point numbers. */
133 CONST char EXP_CHARS[] = "eE";
134
135 /* Chars that mean this number is a floating point constant. */
136 /* As in 0f12.456 */
137 /* or 0d1.2345e12 */
138
139 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
140
141 /* Prefix characters that indicate the start of an immediate
142 value. */
143 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
144
145 #ifdef OBJ_ELF
146 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
147 symbolS * GOT_symbol;
148 #endif
149
150 /* Size of relocation record. */
151 CONST int md_reloc_size = 8;
152
153 /* 0: assemble for ARM,
154 1: assemble for Thumb,
155 2: assemble for Thumb even though target CPU does not support thumb
156 instructions. */
157 static int thumb_mode = 0;
158
159 typedef struct arm_fix
160 {
161 int thumb_mode;
162 } arm_fix_data;
163
164 struct arm_it
165 {
166 CONST char * error;
167 unsigned long instruction;
168 int suffix;
169 int size;
170 struct
171 {
172 bfd_reloc_code_real_type type;
173 expressionS exp;
174 int pc_rel;
175 } reloc;
176 };
177
178 struct arm_it inst;
179
180 enum asm_shift_index
181 {
182 SHIFT_LSL = 0,
183 SHIFT_LSR,
184 SHIFT_ASR,
185 SHIFT_ROR,
186 SHIFT_RRX
187 };
188
189 struct asm_shift_properties
190 {
191 enum asm_shift_index index;
192 unsigned long bit_field;
193 unsigned int allows_0 : 1;
194 unsigned int allows_32 : 1;
195 };
196
197 static const struct asm_shift_properties shift_properties [] =
198 {
199 { SHIFT_LSL, 0, 1, 0},
200 { SHIFT_LSR, 0x20, 0, 1},
201 { SHIFT_ASR, 0x40, 0, 1},
202 { SHIFT_ROR, 0x60, 0, 0},
203 { SHIFT_RRX, 0x60, 0, 0}
204 };
205
206 struct asm_shift_name
207 {
208 const char * name;
209 const struct asm_shift_properties * properties;
210 };
211
212 static const struct asm_shift_name shift_names [] =
213 {
214 { "asl", shift_properties + SHIFT_LSL },
215 { "lsl", shift_properties + SHIFT_LSL },
216 { "lsr", shift_properties + SHIFT_LSR },
217 { "asr", shift_properties + SHIFT_ASR },
218 { "ror", shift_properties + SHIFT_ROR },
219 { "rrx", shift_properties + SHIFT_RRX },
220 { "ASL", shift_properties + SHIFT_LSL },
221 { "LSL", shift_properties + SHIFT_LSL },
222 { "LSR", shift_properties + SHIFT_LSR },
223 { "ASR", shift_properties + SHIFT_ASR },
224 { "ROR", shift_properties + SHIFT_ROR },
225 { "RRX", shift_properties + SHIFT_RRX }
226 };
227
228 #define NO_SHIFT_RESTRICT 1
229 #define SHIFT_RESTRICT 0
230
231 #define NUM_FLOAT_VALS 8
232
233 CONST char * fp_const[] =
234 {
235 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
236 };
237
238 /* Number of littlenums required to hold an extended precision number. */
239 #define MAX_LITTLENUMS 6
240
241 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
242
243 #define FAIL (-1)
244 #define SUCCESS (0)
245
246 #define SUFF_S 1
247 #define SUFF_D 2
248 #define SUFF_E 3
249 #define SUFF_P 4
250
251 #define CP_T_X 0x00008000
252 #define CP_T_Y 0x00400000
253 #define CP_T_Pre 0x01000000
254 #define CP_T_UD 0x00800000
255 #define CP_T_WB 0x00200000
256
257 #define CONDS_BIT 0x00100000
258 #define LOAD_BIT 0x00100000
259 #define TRANS_BIT 0x00200000
260
261 #define DOUBLE_LOAD_FLAG 0x00000001
262
263 struct asm_cond
264 {
265 CONST char * template;
266 unsigned long value;
267 };
268
269 /* This is to save a hash look-up in the common case. */
270 #define COND_ALWAYS 0xe0000000
271
272 static CONST struct asm_cond conds[] =
273 {
274 {"eq", 0x00000000},
275 {"ne", 0x10000000},
276 {"cs", 0x20000000}, {"hs", 0x20000000},
277 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
278 {"mi", 0x40000000},
279 {"pl", 0x50000000},
280 {"vs", 0x60000000},
281 {"vc", 0x70000000},
282 {"hi", 0x80000000},
283 {"ls", 0x90000000},
284 {"ge", 0xa0000000},
285 {"lt", 0xb0000000},
286 {"gt", 0xc0000000},
287 {"le", 0xd0000000},
288 {"al", 0xe0000000},
289 {"nv", 0xf0000000}
290 };
291
292 /* Warning: If the top bit of the set_bits is set, then the standard
293 instruction bitmask is ignored, and the new bitmask is taken from
294 the set_bits: */
295 struct asm_flg
296 {
297 CONST char * template; /* Basic flag string. */
298 unsigned long set_bits; /* Bits to set. */
299 };
300
301 static CONST struct asm_flg s_flag[] =
302 {
303 {"s", CONDS_BIT},
304 {NULL, 0}
305 };
306
307 static CONST struct asm_flg ldr_flags[] =
308 {
309 {"d", DOUBLE_LOAD_FLAG},
310 {"b", 0x00400000},
311 {"t", TRANS_BIT},
312 {"bt", 0x00400000 | TRANS_BIT},
313 {"h", 0x801000b0},
314 {"sh", 0x801000f0},
315 {"sb", 0x801000d0},
316 {NULL, 0}
317 };
318
319 static CONST struct asm_flg str_flags[] =
320 {
321 {"d", DOUBLE_LOAD_FLAG},
322 {"b", 0x00400000},
323 {"t", TRANS_BIT},
324 {"bt", 0x00400000 | TRANS_BIT},
325 {"h", 0x800000b0},
326 {NULL, 0}
327 };
328
329 static CONST struct asm_flg byte_flag[] =
330 {
331 {"b", 0x00400000},
332 {NULL, 0}
333 };
334
335 static CONST struct asm_flg cmp_flags[] =
336 {
337 {"s", CONDS_BIT},
338 {"p", 0x0010f000},
339 {NULL, 0}
340 };
341
342 static CONST struct asm_flg ldm_flags[] =
343 {
344 {"ed", 0x01800000},
345 {"fd", 0x00800000},
346 {"ea", 0x01000000},
347 {"fa", 0x00000000},
348 {"ib", 0x01800000},
349 {"ia", 0x00800000},
350 {"db", 0x01000000},
351 {"da", 0x00000000},
352 {NULL, 0}
353 };
354
355 static CONST struct asm_flg stm_flags[] =
356 {
357 {"ed", 0x00000000},
358 {"fd", 0x01000000},
359 {"ea", 0x00800000},
360 {"fa", 0x01800000},
361 {"ib", 0x01800000},
362 {"ia", 0x00800000},
363 {"db", 0x01000000},
364 {"da", 0x00000000},
365 {NULL, 0}
366 };
367
368 static CONST struct asm_flg lfm_flags[] =
369 {
370 {"fd", 0x00800000},
371 {"ea", 0x01000000},
372 {NULL, 0}
373 };
374
375 static CONST struct asm_flg sfm_flags[] =
376 {
377 {"fd", 0x01000000},
378 {"ea", 0x00800000},
379 {NULL, 0}
380 };
381
382 static CONST struct asm_flg round_flags[] =
383 {
384 {"p", 0x00000020},
385 {"m", 0x00000040},
386 {"z", 0x00000060},
387 {NULL, 0}
388 };
389
390 /* The implementation of the FIX instruction is broken on some assemblers,
391 in that it accepts a precision specifier as well as a rounding specifier,
392 despite the fact that this is meaningless. To be more compatible, we
393 accept it as well, though of course it does not set any bits. */
394 static CONST struct asm_flg fix_flags[] =
395 {
396 {"p", 0x00000020},
397 {"m", 0x00000040},
398 {"z", 0x00000060},
399 {"sp", 0x00000020},
400 {"sm", 0x00000040},
401 {"sz", 0x00000060},
402 {"dp", 0x00000020},
403 {"dm", 0x00000040},
404 {"dz", 0x00000060},
405 {"ep", 0x00000020},
406 {"em", 0x00000040},
407 {"ez", 0x00000060},
408 {NULL, 0}
409 };
410
411 static CONST struct asm_flg except_flag[] =
412 {
413 {"e", 0x00400000},
414 {NULL, 0}
415 };
416
417 static CONST struct asm_flg long_flag[] =
418 {
419 {"l", 0x00400000},
420 {NULL, 0}
421 };
422
423 struct asm_psr
424 {
425 CONST char * template;
426 boolean cpsr;
427 unsigned long field;
428 };
429
430 /* The bit that distnguishes CPSR and SPSR. */
431 #define SPSR_BIT (1 << 22)
432
433 /* How many bits to shift the PSR_xxx bits up by. */
434 #define PSR_SHIFT 16
435
436 #define PSR_c (1 << 0)
437 #define PSR_x (1 << 1)
438 #define PSR_s (1 << 2)
439 #define PSR_f (1 << 3)
440
441 static CONST struct asm_psr psrs[] =
442 {
443 {"CPSR", true, PSR_c | PSR_f},
444 {"CPSR_all", true, PSR_c | PSR_f},
445 {"SPSR", false, PSR_c | PSR_f},
446 {"SPSR_all", false, PSR_c | PSR_f},
447 {"CPSR_flg", true, PSR_f},
448 {"CPSR_f", true, PSR_f},
449 {"SPSR_flg", false, PSR_f},
450 {"SPSR_f", false, PSR_f},
451 {"CPSR_c", true, PSR_c},
452 {"CPSR_ctl", true, PSR_c},
453 {"SPSR_c", false, PSR_c},
454 {"SPSR_ctl", false, PSR_c},
455 {"CPSR_x", true, PSR_x},
456 {"CPSR_s", true, PSR_s},
457 {"SPSR_x", false, PSR_x},
458 {"SPSR_s", false, PSR_s},
459 /* Combinations of flags. */
460 {"CPSR_fs", true, PSR_f | PSR_s},
461 {"CPSR_fx", true, PSR_f | PSR_x},
462 {"CPSR_fc", true, PSR_f | PSR_c},
463 {"CPSR_sf", true, PSR_s | PSR_f},
464 {"CPSR_sx", true, PSR_s | PSR_x},
465 {"CPSR_sc", true, PSR_s | PSR_c},
466 {"CPSR_xf", true, PSR_x | PSR_f},
467 {"CPSR_xs", true, PSR_x | PSR_s},
468 {"CPSR_xc", true, PSR_x | PSR_c},
469 {"CPSR_cf", true, PSR_c | PSR_f},
470 {"CPSR_cs", true, PSR_c | PSR_s},
471 {"CPSR_cx", true, PSR_c | PSR_x},
472 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
473 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
474 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
475 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
476 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
477 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
478 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
479 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
480 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
481 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
482 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
483 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
484 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
485 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
486 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
487 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
488 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
489 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
490 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
491 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
492 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
493 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
494 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
495 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
496 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
497 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
498 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
499 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
500 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
501 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
502 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
503 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
504 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
505 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
506 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
507 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
508 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
509 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
510 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
511 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
512 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
513 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
514 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
515 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
516 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
517 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
518 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
519 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
520 {"SPSR_fs", false, PSR_f | PSR_s},
521 {"SPSR_fx", false, PSR_f | PSR_x},
522 {"SPSR_fc", false, PSR_f | PSR_c},
523 {"SPSR_sf", false, PSR_s | PSR_f},
524 {"SPSR_sx", false, PSR_s | PSR_x},
525 {"SPSR_sc", false, PSR_s | PSR_c},
526 {"SPSR_xf", false, PSR_x | PSR_f},
527 {"SPSR_xs", false, PSR_x | PSR_s},
528 {"SPSR_xc", false, PSR_x | PSR_c},
529 {"SPSR_cf", false, PSR_c | PSR_f},
530 {"SPSR_cs", false, PSR_c | PSR_s},
531 {"SPSR_cx", false, PSR_c | PSR_x},
532 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
533 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
534 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
535 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
536 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
537 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
538 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
539 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
540 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
541 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
542 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
543 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
544 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
545 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
546 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
547 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
548 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
549 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
550 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
551 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
552 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
553 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
554 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
555 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
556 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
557 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
558 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
559 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
560 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
561 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
562 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
563 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
564 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
565 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
566 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
567 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
568 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
569 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
570 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
571 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
572 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
573 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
574 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
575 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
576 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
577 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
578 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
579 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
580 };
581
582 /* Functions called by parser. */
583 /* ARM instructions. */
584 static void do_arit PARAMS ((char *, unsigned long));
585 static void do_cmp PARAMS ((char *, unsigned long));
586 static void do_mov PARAMS ((char *, unsigned long));
587 static void do_ldst PARAMS ((char *, unsigned long));
588 static void do_ldmstm PARAMS ((char *, unsigned long));
589 static void do_branch PARAMS ((char *, unsigned long));
590 static void do_swi PARAMS ((char *, unsigned long));
591 /* Pseudo Op codes. */
592 static void do_adr PARAMS ((char *, unsigned long));
593 static void do_nop PARAMS ((char *, unsigned long));
594 /* ARM 2. */
595 static void do_mul PARAMS ((char *, unsigned long));
596 static void do_mla PARAMS ((char *, unsigned long));
597 /* ARM 3. */
598 static void do_swap PARAMS ((char *, unsigned long));
599 /* ARM 6. */
600 static void do_msr PARAMS ((char *, unsigned long));
601 static void do_mrs PARAMS ((char *, unsigned long));
602 /* ARM 7M. */
603 static void do_mull PARAMS ((char *, unsigned long));
604 /* ARM THUMB. */
605 static void do_bx PARAMS ((char *, unsigned long));
606
607 /* ARM_EXT_XScale. */
608 static void do_mia PARAMS ((char *, unsigned long));
609 static void do_mar PARAMS ((char *, unsigned long));
610 static void do_mra PARAMS ((char *, unsigned long));
611 static void do_pld PARAMS ((char *, unsigned long));
612 static void do_ldrd PARAMS ((char *, unsigned long));
613
614 /* ARM_EXT_V5. */
615 static void do_blx PARAMS ((char *, unsigned long));
616 static void do_bkpt PARAMS ((char *, unsigned long));
617 static void do_clz PARAMS ((char *, unsigned long));
618 static void do_lstc2 PARAMS ((char *, unsigned long));
619 static void do_cdp2 PARAMS ((char *, unsigned long));
620 static void do_co_reg2 PARAMS ((char *, unsigned long));
621
622 static void do_t_blx PARAMS ((char *));
623 static void do_t_bkpt PARAMS ((char *));
624
625 /* ARM_EXT_V5E. */
626 static void do_smla PARAMS ((char *, unsigned long));
627 static void do_smlal PARAMS ((char *, unsigned long));
628 static void do_smul PARAMS ((char *, unsigned long));
629 static void do_qadd PARAMS ((char *, unsigned long));
630 static void do_co_reg2c PARAMS ((char *, unsigned long));
631
632 /* Coprocessor Instructions. */
633 static void do_cdp PARAMS ((char *, unsigned long));
634 static void do_lstc PARAMS ((char *, unsigned long));
635 static void do_co_reg PARAMS ((char *, unsigned long));
636 static void do_fp_ctrl PARAMS ((char *, unsigned long));
637 static void do_fp_ldst PARAMS ((char *, unsigned long));
638 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
639 static void do_fp_dyadic PARAMS ((char *, unsigned long));
640 static void do_fp_monadic PARAMS ((char *, unsigned long));
641 static void do_fp_cmp PARAMS ((char *, unsigned long));
642 static void do_fp_from_reg PARAMS ((char *, unsigned long));
643 static void do_fp_to_reg PARAMS ((char *, unsigned long));
644
645 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
646 static int arm_reg_parse PARAMS ((char **));
647 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
648 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
649 static int add_to_lit_pool PARAMS ((void));
650 static unsigned validate_immediate PARAMS ((unsigned));
651 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
652 static int validate_offset_imm PARAMS ((unsigned int, int));
653 static void opcode_select PARAMS ((int));
654 static void end_of_line PARAMS ((char *));
655 static int reg_required_here PARAMS ((char **, int));
656 static int psr_required_here PARAMS ((char **));
657 static int co_proc_number PARAMS ((char **));
658 static int cp_opc_expr PARAMS ((char **, int, int));
659 static int cp_reg_required_here PARAMS ((char **, int));
660 static int fp_reg_required_here PARAMS ((char **, int));
661 static int cp_address_offset PARAMS ((char **));
662 static int cp_address_required_here PARAMS ((char **));
663 static int my_get_float_expression PARAMS ((char **));
664 static int skip_past_comma PARAMS ((char **));
665 static int walk_no_bignums PARAMS ((symbolS *));
666 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
667 static int data_op2 PARAMS ((char **));
668 static int fp_op2 PARAMS ((char **));
669 static long reg_list PARAMS ((char **));
670 static void thumb_load_store PARAMS ((char *, int, int));
671 static int decode_shift PARAMS ((char **, int));
672 static int ldst_extend PARAMS ((char **, int));
673 static void thumb_add_sub PARAMS ((char *, int));
674 static void insert_reg PARAMS ((int));
675 static void thumb_shift PARAMS ((char *, int));
676 static void thumb_mov_compare PARAMS ((char *, int));
677 static void set_constant_flonums PARAMS ((void));
678 static valueT md_chars_to_number PARAMS ((char *, int));
679 static void insert_reg_alias PARAMS ((char *, int));
680 static void output_inst PARAMS ((void));
681 static int accum0_required_here PARAMS ((char **));
682 static int ld_mode_required_here PARAMS ((char **));
683 static void do_branch25 PARAMS ((char *, unsigned long));
684 static symbolS * find_real_start PARAMS ((symbolS *));
685 #ifdef OBJ_ELF
686 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
687 #endif
688
689 /* ARM instructions take 4bytes in the object file, Thumb instructions
690 take 2: */
691 #define INSN_SIZE 4
692
693 /* LONGEST_INST is the longest basic instruction name without
694 conditions or flags. ARM7M has 4 of length 5. El Segundo
695 has one basic instruction name of length 7 (SMLALxy). */
696 #define LONGEST_INST 7
697
698 struct asm_opcode
699 {
700 /* Basic string to match. */
701 CONST char * template;
702
703 /* Basic instruction code. */
704 unsigned long value;
705
706 /* Compulsory suffix that must follow conds. If "", then the
707 instruction is not conditional and must have no suffix. */
708 CONST char * comp_suffix;
709
710 /* Bits to toggle if flag 'n' set. */
711 CONST struct asm_flg * flags;
712
713 /* Which CPU variants this exists for. */
714 unsigned long variants;
715
716 /* Function to call to parse args. */
717 void (* parms) PARAMS ((char *, unsigned long));
718 };
719
720 static CONST struct asm_opcode insns[] =
721 {
722 /* Intel XScale extensions to ARM V5 ISA. */
723 {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
724 {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
725 {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
726 {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
727 {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
728 {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
729 {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar},
730 {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra},
731 {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld},
732 {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd},
733 {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},
734
735 /* ARM Instructions. */
736 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
737 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
738 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
739 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
740 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
741 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
742 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
743 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
744 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
745 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
746 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
747 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
748 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
749 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
750 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
751 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
752 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
753 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
754 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
755 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
756 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
757 #ifdef TE_WINCE
758 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
759 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
760 #else
761 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
762 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
763 #endif
764
765 /* Pseudo ops. */
766 {"adr", 0x028f0000, NULL, long_flag, ARM_ANY, do_adr},
767 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
768
769 /* ARM 2 multiplies. */
770 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
771 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
772
773 /* ARM 3 - swp instructions. */
774 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
775
776 /* ARM 6 Coprocessor instructions. */
777 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
778 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
779 /* ScottB: our code uses 0x0128f000 for msr.
780 NickC: but this is wrong because the bits 16 through 19 are
781 handled by the PSR_xxx defines above. */
782
783 /* ARM 7M long multiplies - need signed/unsigned flags! */
784 {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
785 {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
786 {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
787 {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
788
789 /* ARM THUMB interworking. */
790 {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},
791
792 /* Floating point instructions. */
793 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
794 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
795 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
796 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
797 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
798 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
799 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
800 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
801 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
802 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
803 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
804 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
805 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
806 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
807 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
808 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
809 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
810 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
811 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
812 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
813 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
814 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
815 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
816 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
817 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
818 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
819 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
820 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
821 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
822 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
823 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
824 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
825 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
826 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
827 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
828 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
829 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
830 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
831 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
832 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
833 be an optional suffix, but part of the instruction. To be compatible,
834 we accept either. */
835 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
836 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
837 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
838 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
839
840 /* Generic copressor instructions. */
841 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
842 {"ldc", 0x0c100000, NULL, long_flag, ARM_2UP, do_lstc},
843 {"stc", 0x0c000000, NULL, long_flag, ARM_2UP, do_lstc},
844 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
845 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
846
847 /* ARM ISA extension 5. */
848 /* Note: blx is actually 2 opcodes, so the .value is set dynamically.
849 And it's sometimes conditional and sometimes not. */
850 {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx},
851 {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz},
852 {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt},
853 {"ldc2", 0xfc100000, "", long_flag, ARM_EXT_V5, do_lstc2},
854 {"stc2", 0xfc000000, "", long_flag, ARM_EXT_V5, do_lstc2},
855 {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2},
856 {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2},
857 {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},
858
859 /* ARM ISA extension 5E, El Segundo. */
860 {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla},
861 {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla},
862 {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
863 {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla},
864
865 {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla},
866 {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
867
868 {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal},
869 {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal},
870 {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal},
871 {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal},
872
873 {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul},
874 {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
875 {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul},
876 {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
877
878 {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
879 {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
880
881 {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd},
882 {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd},
883 {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd},
884 {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd},
885
886 {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
887 {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
888 };
889
890 /* Defines for various bits that we will want to toggle. */
891 #define INST_IMMEDIATE 0x02000000
892 #define OFFSET_REG 0x02000000
893 #define HWOFFSET_IMM 0x00400000
894 #define SHIFT_BY_REG 0x00000010
895 #define PRE_INDEX 0x01000000
896 #define INDEX_UP 0x00800000
897 #define WRITE_BACK 0x00200000
898 #define LDM_TYPE_2_OR_3 0x00400000
899
900 #define LITERAL_MASK 0xf000f000
901 #define COND_MASK 0xf0000000
902 #define OPCODE_MASK 0xfe1fffff
903 #define DATA_OP_SHIFT 21
904
905 /* Codes to distinguish the arithmetic instructions. */
906 #define OPCODE_AND 0
907 #define OPCODE_EOR 1
908 #define OPCODE_SUB 2
909 #define OPCODE_RSB 3
910 #define OPCODE_ADD 4
911 #define OPCODE_ADC 5
912 #define OPCODE_SBC 6
913 #define OPCODE_RSC 7
914 #define OPCODE_TST 8
915 #define OPCODE_TEQ 9
916 #define OPCODE_CMP 10
917 #define OPCODE_CMN 11
918 #define OPCODE_ORR 12
919 #define OPCODE_MOV 13
920 #define OPCODE_BIC 14
921 #define OPCODE_MVN 15
922
923 static void do_t_nop PARAMS ((char *));
924 static void do_t_arit PARAMS ((char *));
925 static void do_t_add PARAMS ((char *));
926 static void do_t_asr PARAMS ((char *));
927 static void do_t_branch9 PARAMS ((char *));
928 static void do_t_branch12 PARAMS ((char *));
929 static void do_t_branch23 PARAMS ((char *));
930 static void do_t_bx PARAMS ((char *));
931 static void do_t_compare PARAMS ((char *));
932 static void do_t_ldmstm PARAMS ((char *));
933 static void do_t_ldr PARAMS ((char *));
934 static void do_t_ldrb PARAMS ((char *));
935 static void do_t_ldrh PARAMS ((char *));
936 static void do_t_lds PARAMS ((char *));
937 static void do_t_lsl PARAMS ((char *));
938 static void do_t_lsr PARAMS ((char *));
939 static void do_t_mov PARAMS ((char *));
940 static void do_t_push_pop PARAMS ((char *));
941 static void do_t_str PARAMS ((char *));
942 static void do_t_strb PARAMS ((char *));
943 static void do_t_strh PARAMS ((char *));
944 static void do_t_sub PARAMS ((char *));
945 static void do_t_swi PARAMS ((char *));
946 static void do_t_adr PARAMS ((char *));
947
948 #define T_OPCODE_MUL 0x4340
949 #define T_OPCODE_TST 0x4200
950 #define T_OPCODE_CMN 0x42c0
951 #define T_OPCODE_NEG 0x4240
952 #define T_OPCODE_MVN 0x43c0
953
954 #define T_OPCODE_ADD_R3 0x1800
955 #define T_OPCODE_SUB_R3 0x1a00
956 #define T_OPCODE_ADD_HI 0x4400
957 #define T_OPCODE_ADD_ST 0xb000
958 #define T_OPCODE_SUB_ST 0xb080
959 #define T_OPCODE_ADD_SP 0xa800
960 #define T_OPCODE_ADD_PC 0xa000
961 #define T_OPCODE_ADD_I8 0x3000
962 #define T_OPCODE_SUB_I8 0x3800
963 #define T_OPCODE_ADD_I3 0x1c00
964 #define T_OPCODE_SUB_I3 0x1e00
965
966 #define T_OPCODE_ASR_R 0x4100
967 #define T_OPCODE_LSL_R 0x4080
968 #define T_OPCODE_LSR_R 0x40c0
969 #define T_OPCODE_ASR_I 0x1000
970 #define T_OPCODE_LSL_I 0x0000
971 #define T_OPCODE_LSR_I 0x0800
972
973 #define T_OPCODE_MOV_I8 0x2000
974 #define T_OPCODE_CMP_I8 0x2800
975 #define T_OPCODE_CMP_LR 0x4280
976 #define T_OPCODE_MOV_HR 0x4600
977 #define T_OPCODE_CMP_HR 0x4500
978
979 #define T_OPCODE_LDR_PC 0x4800
980 #define T_OPCODE_LDR_SP 0x9800
981 #define T_OPCODE_STR_SP 0x9000
982 #define T_OPCODE_LDR_IW 0x6800
983 #define T_OPCODE_STR_IW 0x6000
984 #define T_OPCODE_LDR_IH 0x8800
985 #define T_OPCODE_STR_IH 0x8000
986 #define T_OPCODE_LDR_IB 0x7800
987 #define T_OPCODE_STR_IB 0x7000
988 #define T_OPCODE_LDR_RW 0x5800
989 #define T_OPCODE_STR_RW 0x5000
990 #define T_OPCODE_LDR_RH 0x5a00
991 #define T_OPCODE_STR_RH 0x5200
992 #define T_OPCODE_LDR_RB 0x5c00
993 #define T_OPCODE_STR_RB 0x5400
994
995 #define T_OPCODE_PUSH 0xb400
996 #define T_OPCODE_POP 0xbc00
997
998 #define T_OPCODE_BRANCH 0xe7fe
999
1000 static int thumb_reg PARAMS ((char ** str, int hi_lo));
1001
1002 #define THUMB_SIZE 2 /* Size of thumb instruction. */
1003 #define THUMB_REG_LO 0x1
1004 #define THUMB_REG_HI 0x2
1005 #define THUMB_REG_ANY 0x3
1006
1007 #define THUMB_H1 0x0080
1008 #define THUMB_H2 0x0040
1009
1010 #define THUMB_ASR 0
1011 #define THUMB_LSL 1
1012 #define THUMB_LSR 2
1013
1014 #define THUMB_MOVE 0
1015 #define THUMB_COMPARE 1
1016
1017 #define THUMB_LOAD 0
1018 #define THUMB_STORE 1
1019
1020 #define THUMB_PP_PC_LR 0x0100
1021
1022 /* These three are used for immediate shifts, do not alter. */
1023 #define THUMB_WORD 2
1024 #define THUMB_HALFWORD 1
1025 #define THUMB_BYTE 0
1026
1027 struct thumb_opcode
1028 {
1029 /* Basic string to match. */
1030 CONST char * template;
1031
1032 /* Basic instruction code. */
1033 unsigned long value;
1034
1035 int size;
1036
1037 /* Which CPU variants this exists for. */
1038 unsigned long variants;
1039
1040 /* Function to call to parse args. */
1041 void (* parms) PARAMS ((char *));
1042 };
1043
1044 static CONST struct thumb_opcode tinsns[] =
1045 {
1046 {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit},
1047 {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add},
1048 {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit},
1049 {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr},
1050 {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12},
1051 {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9},
1052 {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9},
1053 {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1054 {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1055 {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1056 {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1057 {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1058 {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9},
1059 {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9},
1060 {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9},
1061 {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9},
1062 {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9},
1063 {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9},
1064 {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9},
1065 {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9},
1066 {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9},
1067 {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9},
1068 {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9},
1069 {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit},
1070 {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23},
1071 {"blx", 0, 0, ARM_EXT_V5, do_t_blx},
1072 {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt},
1073 {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx},
1074 {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit},
1075 {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare},
1076 {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit},
1077 {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm},
1078 {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr},
1079 {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb},
1080 {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh},
1081 {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1082 {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1083 {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1084 {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1085 {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl},
1086 {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr},
1087 {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov},
1088 {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit},
1089 {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit},
1090 {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit},
1091 {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit},
1092 {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop},
1093 {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop},
1094 {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit},
1095 {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit},
1096 {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm},
1097 {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str},
1098 {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb},
1099 {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh},
1100 {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi},
1101 {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub},
1102 {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit},
1103 /* Pseudo ops: */
1104 {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr},
1105 {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */
1106 };
1107
1108 struct reg_entry
1109 {
1110 CONST char * name;
1111 int number;
1112 };
1113
1114 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1115 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1116 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1117
1118 #define REG_PC 15
1119 #define REG_LR 14
1120 #define REG_SP 13
1121
1122 /* These are the standard names. Users can add aliases with .req. */
1123 static CONST struct reg_entry reg_table[] =
1124 {
1125 /* Processor Register Numbers. */
1126 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1127 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1128 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1129 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1130 /* APCS conventions. */
1131 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1132 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1133 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1134 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1135 /* ATPCS additions to APCS conventions. */
1136 {"wr", 7}, {"v8", 11},
1137 /* FP Registers. */
1138 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1139 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1140 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1141 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1142 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1143 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1144 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1145 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1146 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1147 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1148 /* ATPCS additions to float register names. */
1149 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1150 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1151 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1152 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1153 /* FIXME: At some point we need to add VFP register names. */
1154 /* Array terminator. */
1155 {NULL, 0}
1156 };
1157
1158 #define BAD_ARGS _("Bad arguments to instruction")
1159 #define BAD_PC _("r15 not allowed here")
1160 #define BAD_FLAGS _("Instruction should not have flags")
1161 #define BAD_COND _("Instruction is not conditional")
1162 #define ERR_NO_ACCUM _("acc0 expected")
1163
1164 static struct hash_control * arm_ops_hsh = NULL;
1165 static struct hash_control * arm_tops_hsh = NULL;
1166 static struct hash_control * arm_cond_hsh = NULL;
1167 static struct hash_control * arm_shift_hsh = NULL;
1168 static struct hash_control * arm_reg_hsh = NULL;
1169 static struct hash_control * arm_psr_hsh = NULL;
1170
1171 /* This table describes all the machine specific pseudo-ops the assembler
1172 has to support. The fields are:
1173 pseudo-op name without dot
1174 function to call to execute this pseudo-op
1175 Integer arg to pass to the function. */
1176
1177 static void s_req PARAMS ((int));
1178 static void s_align PARAMS ((int));
1179 static void s_bss PARAMS ((int));
1180 static void s_even PARAMS ((int));
1181 static void s_ltorg PARAMS ((int));
1182 static void s_arm PARAMS ((int));
1183 static void s_thumb PARAMS ((int));
1184 static void s_code PARAMS ((int));
1185 static void s_force_thumb PARAMS ((int));
1186 static void s_thumb_func PARAMS ((int));
1187 static void s_thumb_set PARAMS ((int));
1188 static void arm_s_text PARAMS ((int));
1189 static void arm_s_data PARAMS ((int));
1190 #ifdef OBJ_ELF
1191 static void arm_s_section PARAMS ((int));
1192 static void s_arm_elf_cons PARAMS ((int));
1193 #endif
1194
1195 static int my_get_expression PARAMS ((expressionS *, char **));
1196
1197 CONST pseudo_typeS md_pseudo_table[] =
1198 {
1199 /* Never called becasue '.req' does not start line. */
1200 { "req", s_req, 0 },
1201 { "bss", s_bss, 0 },
1202 { "align", s_align, 0 },
1203 { "arm", s_arm, 0 },
1204 { "thumb", s_thumb, 0 },
1205 { "code", s_code, 0 },
1206 { "force_thumb", s_force_thumb, 0 },
1207 { "thumb_func", s_thumb_func, 0 },
1208 { "thumb_set", s_thumb_set, 0 },
1209 { "even", s_even, 0 },
1210 { "ltorg", s_ltorg, 0 },
1211 { "pool", s_ltorg, 0 },
1212 /* Allow for the effect of section changes. */
1213 { "text", arm_s_text, 0 },
1214 { "data", arm_s_data, 0 },
1215 #ifdef OBJ_ELF
1216 { "section", arm_s_section, 0 },
1217 { "section.s", arm_s_section, 0 },
1218 { "sect", arm_s_section, 0 },
1219 { "sect.s", arm_s_section, 0 },
1220 { "word", s_arm_elf_cons, 4 },
1221 { "long", s_arm_elf_cons, 4 },
1222 { "file", dwarf2_directive_file, 0 },
1223 { "loc", dwarf2_directive_loc, 0 },
1224 #else
1225 { "word", cons, 4},
1226 #endif
1227 { "extend", float_cons, 'x' },
1228 { "ldouble", float_cons, 'x' },
1229 { "packed", float_cons, 'p' },
1230 { 0, 0, 0 }
1231 };
1232
1233 /* Stuff needed to resolve the label ambiguity
1234 As:
1235 ...
1236 label: <insn>
1237 may differ from:
1238 ...
1239 label:
1240 <insn>
1241 */
1242
1243 symbolS * last_label_seen;
1244 static int label_is_thumb_function_name = false;
1245
1246 /* Literal stuff. */
1247
1248 #define MAX_LITERAL_POOL_SIZE 1024
1249
1250 typedef struct literalS
1251 {
1252 struct expressionS exp;
1253 struct arm_it * inst;
1254 } literalT;
1255
1256 literalT literals[MAX_LITERAL_POOL_SIZE];
1257
1258 /* Next free entry in the pool. */
1259 int next_literal_pool_place = 0;
1260
1261 /* Next literal pool number. */
1262 int lit_pool_num = 1;
1263
1264 symbolS * current_poolP = NULL;
1265
1266 static int
1267 add_to_lit_pool ()
1268 {
1269 int lit_count = 0;
1270
1271 if (current_poolP == NULL)
1272 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1273 (valueT) 0, &zero_address_frag);
1274
1275 /* Check if this literal value is already in the pool: */
1276 while (lit_count < next_literal_pool_place)
1277 {
1278 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1279 && inst.reloc.exp.X_op == O_constant
1280 && (literals[lit_count].exp.X_add_number
1281 == inst.reloc.exp.X_add_number)
1282 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1283 break;
1284
1285 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1286 && inst.reloc.exp.X_op == O_symbol
1287 && (literals[lit_count].exp.X_add_number
1288 == inst.reloc.exp.X_add_number)
1289 && (literals[lit_count].exp.X_add_symbol
1290 == inst.reloc.exp.X_add_symbol)
1291 && (literals[lit_count].exp.X_op_symbol
1292 == inst.reloc.exp.X_op_symbol))
1293 break;
1294
1295 lit_count++;
1296 }
1297
1298 if (lit_count == next_literal_pool_place) /* New entry. */
1299 {
1300 if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
1301 {
1302 inst.error = _("Literal Pool Overflow");
1303 return FAIL;
1304 }
1305
1306 literals[next_literal_pool_place].exp = inst.reloc.exp;
1307 lit_count = next_literal_pool_place++;
1308 }
1309
1310 inst.reloc.exp.X_op = O_symbol;
1311 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1312 inst.reloc.exp.X_add_symbol = current_poolP;
1313
1314 return SUCCESS;
1315 }
1316
1317 /* Can't use symbol_new here, so have to create a symbol and then at
1318 a later date assign it a value. Thats what these functions do. */
1319
1320 static void
1321 symbol_locate (symbolP, name, segment, valu, frag)
1322 symbolS * symbolP;
1323 CONST char * name; /* It is copied, the caller can modify. */
1324 segT segment; /* Segment identifier (SEG_<something>). */
1325 valueT valu; /* Symbol value. */
1326 fragS * frag; /* Associated fragment. */
1327 {
1328 unsigned int name_length;
1329 char * preserved_copy_of_name;
1330
1331 name_length = strlen (name) + 1; /* +1 for \0. */
1332 obstack_grow (&notes, name, name_length);
1333 preserved_copy_of_name = obstack_finish (&notes);
1334 #ifdef STRIP_UNDERSCORE
1335 if (preserved_copy_of_name[0] == '_')
1336 preserved_copy_of_name++;
1337 #endif
1338
1339 #ifdef tc_canonicalize_symbol_name
1340 preserved_copy_of_name =
1341 tc_canonicalize_symbol_name (preserved_copy_of_name);
1342 #endif
1343
1344 S_SET_NAME (symbolP, preserved_copy_of_name);
1345
1346 S_SET_SEGMENT (symbolP, segment);
1347 S_SET_VALUE (symbolP, valu);
1348 symbol_clear_list_pointers(symbolP);
1349
1350 symbol_set_frag (symbolP, frag);
1351
1352 /* Link to end of symbol chain. */
1353 {
1354 extern int symbol_table_frozen;
1355 if (symbol_table_frozen)
1356 abort ();
1357 }
1358
1359 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1360
1361 obj_symbol_new_hook (symbolP);
1362
1363 #ifdef tc_symbol_new_hook
1364 tc_symbol_new_hook (symbolP);
1365 #endif
1366
1367 #ifdef DEBUG_SYMS
1368 verify_symbol_chain (symbol_rootP, symbol_lastP);
1369 #endif /* DEBUG_SYMS */
1370 }
1371
1372 /* Check that an immediate is valid.
1373 If so, convert it to the right format. */
1374
1375 static unsigned int
1376 validate_immediate (val)
1377 unsigned int val;
1378 {
1379 unsigned int a;
1380 unsigned int i;
1381
1382 #define rotate_left(v, n) (v << n | v >> (32 - n))
1383
1384 for (i = 0; i < 32; i += 2)
1385 if ((a = rotate_left (val, i)) <= 0xff)
1386 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1387
1388 return FAIL;
1389 }
1390
1391 /* Check to see if an immediate can be computed as two seperate immediate
1392 values, added together. We already know that this value cannot be
1393 computed by just one ARM instruction. */
1394
1395 static unsigned int
1396 validate_immediate_twopart (val, highpart)
1397 unsigned int val;
1398 unsigned int * highpart;
1399 {
1400 unsigned int a;
1401 unsigned int i;
1402
1403 for (i = 0; i < 32; i += 2)
1404 if (((a = rotate_left (val, i)) & 0xff) != 0)
1405 {
1406 if (a & 0xff00)
1407 {
1408 if (a & ~ 0xffff)
1409 continue;
1410 * highpart = (a >> 8) | ((i + 24) << 7);
1411 }
1412 else if (a & 0xff0000)
1413 {
1414 if (a & 0xff000000)
1415 continue;
1416 * highpart = (a >> 16) | ((i + 16) << 7);
1417 }
1418 else
1419 {
1420 assert (a & 0xff000000);
1421 * highpart = (a >> 24) | ((i + 8) << 7);
1422 }
1423
1424 return (a & 0xff) | (i << 7);
1425 }
1426
1427 return FAIL;
1428 }
1429
1430 static int
1431 validate_offset_imm (val, hwse)
1432 unsigned int val;
1433 int hwse;
1434 {
1435 if ((hwse && val > 255) || val > 4095)
1436 return FAIL;
1437 return val;
1438 }
1439
1440 static void
1441 s_req (a)
1442 int a ATTRIBUTE_UNUSED;
1443 {
1444 as_bad (_("Invalid syntax for .req directive."));
1445 }
1446
1447 static void
1448 s_bss (ignore)
1449 int ignore ATTRIBUTE_UNUSED;
1450 {
1451 /* We don't support putting frags in the BSS segment, we fake it by
1452 marking in_bss, then looking at s_skip for clues. */
1453 subseg_set (bss_section, 0);
1454 demand_empty_rest_of_line ();
1455 }
1456
1457 static void
1458 s_even (ignore)
1459 int ignore ATTRIBUTE_UNUSED;
1460 {
1461 /* Never make frag if expect extra pass. */
1462 if (!need_pass_2)
1463 frag_align (1, 0, 0);
1464
1465 record_alignment (now_seg, 1);
1466
1467 demand_empty_rest_of_line ();
1468 }
1469
1470 static void
1471 s_ltorg (ignored)
1472 int ignored ATTRIBUTE_UNUSED;
1473 {
1474 int lit_count = 0;
1475 char sym_name[20];
1476
1477 if (current_poolP == NULL)
1478 return;
1479
1480 /* Align pool as you have word accesses.
1481 Only make a frag if we have to. */
1482 if (!need_pass_2)
1483 frag_align (2, 0, 0);
1484
1485 record_alignment (now_seg, 2);
1486
1487 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1488
1489 symbol_locate (current_poolP, sym_name, now_seg,
1490 (valueT) frag_now_fix (), frag_now);
1491 symbol_table_insert (current_poolP);
1492
1493 ARM_SET_THUMB (current_poolP, thumb_mode);
1494
1495 #if defined OBJ_COFF || defined OBJ_ELF
1496 ARM_SET_INTERWORK (current_poolP, support_interwork);
1497 #endif
1498
1499 while (lit_count < next_literal_pool_place)
1500 /* First output the expression in the instruction to the pool. */
1501 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1502
1503 next_literal_pool_place = 0;
1504 current_poolP = NULL;
1505 }
1506
1507 /* Same as s_align_ptwo but align 0 => align 2. */
1508
1509 static void
1510 s_align (unused)
1511 int unused ATTRIBUTE_UNUSED;
1512 {
1513 register int temp;
1514 register long temp_fill;
1515 long max_alignment = 15;
1516
1517 temp = get_absolute_expression ();
1518 if (temp > max_alignment)
1519 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1520 else if (temp < 0)
1521 {
1522 as_bad (_("Alignment negative. 0 assumed."));
1523 temp = 0;
1524 }
1525
1526 if (*input_line_pointer == ',')
1527 {
1528 input_line_pointer++;
1529 temp_fill = get_absolute_expression ();
1530 }
1531 else
1532 temp_fill = 0;
1533
1534 if (!temp)
1535 temp = 2;
1536
1537 /* Only make a frag if we HAVE to. */
1538 if (temp && !need_pass_2)
1539 frag_align (temp, (int) temp_fill, 0);
1540 demand_empty_rest_of_line ();
1541
1542 record_alignment (now_seg, temp);
1543 }
1544
1545 static void
1546 s_force_thumb (ignore)
1547 int ignore ATTRIBUTE_UNUSED;
1548 {
1549 /* If we are not already in thumb mode go into it, EVEN if
1550 the target processor does not support thumb instructions.
1551 This is used by gcc/config/arm/lib1funcs.asm for example
1552 to compile interworking support functions even if the
1553 target processor should not support interworking. */
1554 if (! thumb_mode)
1555 {
1556 thumb_mode = 2;
1557
1558 record_alignment (now_seg, 1);
1559 }
1560
1561 demand_empty_rest_of_line ();
1562 }
1563
1564 static void
1565 s_thumb_func (ignore)
1566 int ignore ATTRIBUTE_UNUSED;
1567 {
1568 if (! thumb_mode)
1569 opcode_select (16);
1570
1571 /* The following label is the name/address of the start of a Thumb function.
1572 We need to know this for the interworking support. */
1573 label_is_thumb_function_name = true;
1574
1575 demand_empty_rest_of_line ();
1576 }
1577
1578 /* Perform a .set directive, but also mark the alias as
1579 being a thumb function. */
1580
1581 static void
1582 s_thumb_set (equiv)
1583 int equiv;
1584 {
1585 /* XXX the following is a duplicate of the code for s_set() in read.c
1586 We cannot just call that code as we need to get at the symbol that
1587 is created. */
1588 register char * name;
1589 register char delim;
1590 register char * end_name;
1591 register symbolS * symbolP;
1592
1593 /* Especial apologies for the random logic:
1594 This just grew, and could be parsed much more simply!
1595 Dean - in haste. */
1596 name = input_line_pointer;
1597 delim = get_symbol_end ();
1598 end_name = input_line_pointer;
1599 *end_name = delim;
1600
1601 SKIP_WHITESPACE ();
1602
1603 if (*input_line_pointer != ',')
1604 {
1605 *end_name = 0;
1606 as_bad (_("Expected comma after name \"%s\""), name);
1607 *end_name = delim;
1608 ignore_rest_of_line ();
1609 return;
1610 }
1611
1612 input_line_pointer++;
1613 *end_name = 0;
1614
1615 if (name[0] == '.' && name[1] == '\0')
1616 {
1617 /* XXX - this should not happen to .thumb_set. */
1618 abort ();
1619 }
1620
1621 if ((symbolP = symbol_find (name)) == NULL
1622 && (symbolP = md_undefined_symbol (name)) == NULL)
1623 {
1624 #ifndef NO_LISTING
1625 /* When doing symbol listings, play games with dummy fragments living
1626 outside the normal fragment chain to record the file and line info
1627 for this symbol. */
1628 if (listing & LISTING_SYMBOLS)
1629 {
1630 extern struct list_info_struct * listing_tail;
1631 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1632
1633 memset (dummy_frag, 0, sizeof (fragS));
1634 dummy_frag->fr_type = rs_fill;
1635 dummy_frag->line = listing_tail;
1636 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1637 dummy_frag->fr_symbol = symbolP;
1638 }
1639 else
1640 #endif
1641 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1642
1643 #ifdef OBJ_COFF
1644 /* "set" symbols are local unless otherwise specified. */
1645 SF_SET_LOCAL (symbolP);
1646 #endif /* OBJ_COFF */
1647 } /* Make a new symbol. */
1648
1649 symbol_table_insert (symbolP);
1650
1651 * end_name = delim;
1652
1653 if (equiv
1654 && S_IS_DEFINED (symbolP)
1655 && S_GET_SEGMENT (symbolP) != reg_section)
1656 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1657
1658 pseudo_set (symbolP);
1659
1660 demand_empty_rest_of_line ();
1661
1662 /* XXX Now we come to the Thumb specific bit of code. */
1663
1664 THUMB_SET_FUNC (symbolP, 1);
1665 ARM_SET_THUMB (symbolP, 1);
1666 #if defined OBJ_ELF || defined OBJ_COFF
1667 ARM_SET_INTERWORK (symbolP, support_interwork);
1668 #endif
1669 }
1670
1671 /* If we change section we must dump the literal pool first. */
1672
1673 static void
1674 arm_s_text (ignore)
1675 int ignore;
1676 {
1677 if (now_seg != text_section)
1678 s_ltorg (0);
1679
1680 #ifdef OBJ_ELF
1681 obj_elf_text (ignore);
1682 #else
1683 s_text (ignore);
1684 #endif
1685 }
1686
1687 static void
1688 arm_s_data (ignore)
1689 int ignore;
1690 {
1691 if (flag_readonly_data_in_text)
1692 {
1693 if (now_seg != text_section)
1694 s_ltorg (0);
1695 }
1696 else if (now_seg != data_section)
1697 s_ltorg (0);
1698
1699 #ifdef OBJ_ELF
1700 obj_elf_data (ignore);
1701 #else
1702 s_data (ignore);
1703 #endif
1704 }
1705
1706 #ifdef OBJ_ELF
1707 static void
1708 arm_s_section (ignore)
1709 int ignore;
1710 {
1711 s_ltorg (0);
1712
1713 obj_elf_section (ignore);
1714 }
1715 #endif
1716
1717 static void
1718 opcode_select (width)
1719 int width;
1720 {
1721 switch (width)
1722 {
1723 case 16:
1724 if (! thumb_mode)
1725 {
1726 if (! (cpu_variant & ARM_EXT_THUMB))
1727 as_bad (_("selected processor does not support THUMB opcodes"));
1728
1729 thumb_mode = 1;
1730 /* No need to force the alignment, since we will have been
1731 coming from ARM mode, which is word-aligned. */
1732 record_alignment (now_seg, 1);
1733 }
1734 break;
1735
1736 case 32:
1737 if (thumb_mode)
1738 {
1739 if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB)
1740 as_bad (_("selected processor does not support ARM opcodes"));
1741
1742 thumb_mode = 0;
1743
1744 if (!need_pass_2)
1745 frag_align (2, 0, 0);
1746
1747 record_alignment (now_seg, 1);
1748 }
1749 break;
1750
1751 default:
1752 as_bad (_("invalid instruction size selected (%d)"), width);
1753 }
1754 }
1755
1756 static void
1757 s_arm (ignore)
1758 int ignore ATTRIBUTE_UNUSED;
1759 {
1760 opcode_select (32);
1761 demand_empty_rest_of_line ();
1762 }
1763
1764 static void
1765 s_thumb (ignore)
1766 int ignore ATTRIBUTE_UNUSED;
1767 {
1768 opcode_select (16);
1769 demand_empty_rest_of_line ();
1770 }
1771
1772 static void
1773 s_code (unused)
1774 int unused ATTRIBUTE_UNUSED;
1775 {
1776 register int temp;
1777
1778 temp = get_absolute_expression ();
1779 switch (temp)
1780 {
1781 case 16:
1782 case 32:
1783 opcode_select (temp);
1784 break;
1785
1786 default:
1787 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1788 }
1789 }
1790
1791 static void
1792 end_of_line (str)
1793 char * str;
1794 {
1795 skip_whitespace (str);
1796
1797 if (* str != '\0')
1798 inst.error = _("Garbage following instruction");
1799 }
1800
1801 static int
1802 skip_past_comma (str)
1803 char ** str;
1804 {
1805 char * p = * str, c;
1806 int comma = 0;
1807
1808 while ((c = *p) == ' ' || c == ',')
1809 {
1810 p++;
1811 if (c == ',' && comma++)
1812 return FAIL;
1813 }
1814
1815 if (c == '\0')
1816 return FAIL;
1817
1818 *str = p;
1819 return comma ? SUCCESS : FAIL;
1820 }
1821
1822 /* A standard register must be given at this point.
1823 SHIFT is the place to put it in inst.instruction.
1824 Restores input start point on error.
1825 Returns the reg#, or FAIL. */
1826
1827 static int
1828 reg_required_here (str, shift)
1829 char ** str;
1830 int shift;
1831 {
1832 static char buff [128]; /* XXX */
1833 int reg;
1834 char * start = * str;
1835
1836 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1837 {
1838 if (shift >= 0)
1839 inst.instruction |= reg << shift;
1840 return reg;
1841 }
1842
1843 /* Restore the start point, we may have got a reg of the wrong class. */
1844 *str = start;
1845
1846 /* In the few cases where we might be able to accept something else
1847 this error can be overridden. */
1848 sprintf (buff, _("Register expected, not '%.100s'"), start);
1849 inst.error = buff;
1850
1851 return FAIL;
1852 }
1853
1854 static CONST struct asm_psr *
1855 arm_psr_parse (ccp)
1856 register char ** ccp;
1857 {
1858 char * start = * ccp;
1859 char c;
1860 char * p;
1861 CONST struct asm_psr * psr;
1862
1863 p = start;
1864
1865 /* Skip to the end of the next word in the input stream. */
1866 do
1867 {
1868 c = *p++;
1869 }
1870 while (ISALPHA (c) || c == '_');
1871
1872 /* Terminate the word. */
1873 *--p = 0;
1874
1875 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1876 feature for ease of use and backwards compatibility. */
1877 if (!strncmp (start, "cpsr", 4))
1878 strncpy (start, "CPSR", 4);
1879 else if (!strncmp (start, "spsr", 4))
1880 strncpy (start, "SPSR", 4);
1881
1882 /* Now locate the word in the psr hash table. */
1883 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1884
1885 /* Restore the input stream. */
1886 *p = c;
1887
1888 /* If we found a valid match, advance the
1889 stream pointer past the end of the word. */
1890 *ccp = p;
1891
1892 return psr;
1893 }
1894
1895 /* Parse the input looking for a PSR flag. */
1896
1897 static int
1898 psr_required_here (str)
1899 char ** str;
1900 {
1901 char * start = * str;
1902 CONST struct asm_psr * psr;
1903
1904 psr = arm_psr_parse (str);
1905
1906 if (psr)
1907 {
1908 /* If this is the SPSR that is being modified, set the R bit. */
1909 if (! psr->cpsr)
1910 inst.instruction |= SPSR_BIT;
1911
1912 /* Set the psr flags in the MSR instruction. */
1913 inst.instruction |= psr->field << PSR_SHIFT;
1914
1915 return SUCCESS;
1916 }
1917
1918 /* In the few cases where we might be able to accept
1919 something else this error can be overridden. */
1920 inst.error = _("flag for {c}psr instruction expected");
1921
1922 /* Restore the start point. */
1923 *str = start;
1924 return FAIL;
1925 }
1926
1927 static int
1928 co_proc_number (str)
1929 char ** str;
1930 {
1931 int processor, pchar;
1932
1933 skip_whitespace (* str);
1934
1935 /* The data sheet seems to imply that just a number on its own is valid
1936 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1937 accept either. */
1938 if (**str == 'p' || **str == 'P')
1939 (*str)++;
1940
1941 pchar = *(*str)++;
1942 if (pchar >= '0' && pchar <= '9')
1943 {
1944 processor = pchar - '0';
1945 if (**str >= '0' && **str <= '9')
1946 {
1947 processor = processor * 10 + *(*str)++ - '0';
1948 if (processor > 15)
1949 {
1950 inst.error = _("Illegal co-processor number");
1951 return FAIL;
1952 }
1953 }
1954 }
1955 else
1956 {
1957 inst.error = _("Bad or missing co-processor number");
1958 return FAIL;
1959 }
1960
1961 inst.instruction |= processor << 8;
1962 return SUCCESS;
1963 }
1964
1965 static int
1966 cp_opc_expr (str, where, length)
1967 char ** str;
1968 int where;
1969 int length;
1970 {
1971 expressionS expr;
1972
1973 skip_whitespace (* str);
1974
1975 memset (&expr, '\0', sizeof (expr));
1976
1977 if (my_get_expression (&expr, str))
1978 return FAIL;
1979 if (expr.X_op != O_constant)
1980 {
1981 inst.error = _("bad or missing expression");
1982 return FAIL;
1983 }
1984
1985 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1986 {
1987 inst.error = _("immediate co-processor expression too large");
1988 return FAIL;
1989 }
1990
1991 inst.instruction |= expr.X_add_number << where;
1992 return SUCCESS;
1993 }
1994
1995 static int
1996 cp_reg_required_here (str, where)
1997 char ** str;
1998 int where;
1999 {
2000 int reg;
2001 char * start = *str;
2002
2003 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
2004 {
2005 reg &= 15;
2006 inst.instruction |= reg << where;
2007 return reg;
2008 }
2009
2010 /* In the few cases where we might be able to accept something else
2011 this error can be overridden. */
2012 inst.error = _("Co-processor register expected");
2013
2014 /* Restore the start point. */
2015 *str = start;
2016 return FAIL;
2017 }
2018
2019 static int
2020 fp_reg_required_here (str, where)
2021 char ** str;
2022 int where;
2023 {
2024 int reg;
2025 char * start = * str;
2026
2027 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
2028 {
2029 reg &= 7;
2030 inst.instruction |= reg << where;
2031 return reg;
2032 }
2033
2034 /* In the few cases where we might be able to accept something else
2035 this error can be overridden. */
2036 inst.error = _("Floating point register expected");
2037
2038 /* Restore the start point. */
2039 *str = start;
2040 return FAIL;
2041 }
2042
2043 static int
2044 cp_address_offset (str)
2045 char ** str;
2046 {
2047 int offset;
2048
2049 skip_whitespace (* str);
2050
2051 if (! is_immediate_prefix (**str))
2052 {
2053 inst.error = _("immediate expression expected");
2054 return FAIL;
2055 }
2056
2057 (*str)++;
2058
2059 if (my_get_expression (& inst.reloc.exp, str))
2060 return FAIL;
2061
2062 if (inst.reloc.exp.X_op == O_constant)
2063 {
2064 offset = inst.reloc.exp.X_add_number;
2065
2066 if (offset & 3)
2067 {
2068 inst.error = _("co-processor address must be word aligned");
2069 return FAIL;
2070 }
2071
2072 if (offset > 1023 || offset < -1023)
2073 {
2074 inst.error = _("offset too large");
2075 return FAIL;
2076 }
2077
2078 if (offset >= 0)
2079 inst.instruction |= INDEX_UP;
2080 else
2081 offset = -offset;
2082
2083 inst.instruction |= offset >> 2;
2084 }
2085 else
2086 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2087
2088 return SUCCESS;
2089 }
2090
2091 static int
2092 cp_address_required_here (str)
2093 char ** str;
2094 {
2095 char * p = * str;
2096 int pre_inc = 0;
2097 int write_back = 0;
2098
2099 if (*p == '[')
2100 {
2101 int reg;
2102
2103 p++;
2104 skip_whitespace (p);
2105
2106 if ((reg = reg_required_here (& p, 16)) == FAIL)
2107 return FAIL;
2108
2109 skip_whitespace (p);
2110
2111 if (*p == ']')
2112 {
2113 p++;
2114
2115 if (skip_past_comma (& p) == SUCCESS)
2116 {
2117 /* [Rn], #expr */
2118 write_back = WRITE_BACK;
2119
2120 if (reg == REG_PC)
2121 {
2122 inst.error = _("pc may not be used in post-increment");
2123 return FAIL;
2124 }
2125
2126 if (cp_address_offset (& p) == FAIL)
2127 return FAIL;
2128 }
2129 else
2130 pre_inc = PRE_INDEX | INDEX_UP;
2131 }
2132 else
2133 {
2134 /* '['Rn, #expr']'[!] */
2135
2136 if (skip_past_comma (& p) == FAIL)
2137 {
2138 inst.error = _("pre-indexed expression expected");
2139 return FAIL;
2140 }
2141
2142 pre_inc = PRE_INDEX;
2143
2144 if (cp_address_offset (& p) == FAIL)
2145 return FAIL;
2146
2147 skip_whitespace (p);
2148
2149 if (*p++ != ']')
2150 {
2151 inst.error = _("missing ]");
2152 return FAIL;
2153 }
2154
2155 skip_whitespace (p);
2156
2157 if (*p == '!')
2158 {
2159 if (reg == REG_PC)
2160 {
2161 inst.error = _("pc may not be used with write-back");
2162 return FAIL;
2163 }
2164
2165 p++;
2166 write_back = WRITE_BACK;
2167 }
2168 }
2169 }
2170 else
2171 {
2172 if (my_get_expression (&inst.reloc.exp, &p))
2173 return FAIL;
2174
2175 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2176 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2177 inst.reloc.pc_rel = 1;
2178 inst.instruction |= (REG_PC << 16);
2179 pre_inc = PRE_INDEX;
2180 }
2181
2182 inst.instruction |= write_back | pre_inc;
2183 *str = p;
2184 return SUCCESS;
2185 }
2186
2187 static void
2188 do_nop (str, flags)
2189 char * str;
2190 unsigned long flags;
2191 {
2192 /* Do nothing really. */
2193 inst.instruction |= flags; /* This is pointless. */
2194 end_of_line (str);
2195 return;
2196 }
2197
2198 static void
2199 do_mrs (str, flags)
2200 char *str;
2201 unsigned long flags;
2202 {
2203 int skip = 0;
2204
2205 /* Only one syntax. */
2206 skip_whitespace (str);
2207
2208 if (reg_required_here (&str, 12) == FAIL)
2209 {
2210 inst.error = BAD_ARGS;
2211 return;
2212 }
2213
2214 if (skip_past_comma (&str) == FAIL)
2215 {
2216 inst.error = _("comma expected after register name");
2217 return;
2218 }
2219
2220 skip_whitespace (str);
2221
2222 if ( strcmp (str, "CPSR") == 0
2223 || strcmp (str, "SPSR") == 0
2224 /* Lower case versions for backwards compatability. */
2225 || strcmp (str, "cpsr") == 0
2226 || strcmp (str, "spsr") == 0)
2227 skip = 4;
2228
2229 /* This is for backwards compatability with older toolchains. */
2230 else if ( strcmp (str, "cpsr_all") == 0
2231 || strcmp (str, "spsr_all") == 0)
2232 skip = 8;
2233 else
2234 {
2235 inst.error = _("{C|S}PSR expected");
2236 return;
2237 }
2238
2239 if (* str == 's' || * str == 'S')
2240 inst.instruction |= SPSR_BIT;
2241 str += skip;
2242
2243 inst.instruction |= flags;
2244 end_of_line (str);
2245 }
2246
2247 /* Two possible forms:
2248 "{C|S}PSR_<field>, Rm",
2249 "{C|S}PSR_f, #expression". */
2250
2251 static void
2252 do_msr (str, flags)
2253 char * str;
2254 unsigned long flags;
2255 {
2256 skip_whitespace (str);
2257
2258 if (psr_required_here (& str) == FAIL)
2259 return;
2260
2261 if (skip_past_comma (& str) == FAIL)
2262 {
2263 inst.error = _("comma missing after psr flags");
2264 return;
2265 }
2266
2267 skip_whitespace (str);
2268
2269 if (reg_required_here (& str, 0) != FAIL)
2270 {
2271 inst.error = NULL;
2272 inst.instruction |= flags;
2273 end_of_line (str);
2274 return;
2275 }
2276
2277 if (! is_immediate_prefix (* str))
2278 {
2279 inst.error =
2280 _("only a register or immediate value can follow a psr flag");
2281 return;
2282 }
2283
2284 str ++;
2285 inst.error = NULL;
2286
2287 if (my_get_expression (& inst.reloc.exp, & str))
2288 {
2289 inst.error =
2290 _("only a register or immediate value can follow a psr flag");
2291 return;
2292 }
2293
2294 #if 0 /* The first edition of the ARM architecture manual stated that
2295 writing anything other than the flags with an immediate operation
2296 had UNPREDICTABLE effects. This constraint was removed in the
2297 second edition of the specification. */
2298 if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
2299 && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2300 {
2301 inst.error = _("immediate value cannot be used to set this field");
2302 return;
2303 }
2304 #endif
2305
2306 flags |= INST_IMMEDIATE;
2307
2308 if (inst.reloc.exp.X_add_symbol)
2309 {
2310 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2311 inst.reloc.pc_rel = 0;
2312 }
2313 else
2314 {
2315 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2316
2317 if (value == (unsigned) FAIL)
2318 {
2319 inst.error = _("Invalid constant");
2320 return;
2321 }
2322
2323 inst.instruction |= value;
2324 }
2325
2326 inst.error = NULL;
2327 inst.instruction |= flags;
2328 end_of_line (str);
2329 }
2330
2331 /* Long Multiply Parser
2332 UMULL RdLo, RdHi, Rm, Rs
2333 SMULL RdLo, RdHi, Rm, Rs
2334 UMLAL RdLo, RdHi, Rm, Rs
2335 SMLAL RdLo, RdHi, Rm, Rs. */
2336
2337 static void
2338 do_mull (str, flags)
2339 char * str;
2340 unsigned long flags;
2341 {
2342 int rdlo, rdhi, rm, rs;
2343
2344 /* Only one format "rdlo, rdhi, rm, rs". */
2345 skip_whitespace (str);
2346
2347 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2348 {
2349 inst.error = BAD_ARGS;
2350 return;
2351 }
2352
2353 if (skip_past_comma (&str) == FAIL
2354 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2355 {
2356 inst.error = BAD_ARGS;
2357 return;
2358 }
2359
2360 if (skip_past_comma (&str) == FAIL
2361 || (rm = reg_required_here (&str, 0)) == FAIL)
2362 {
2363 inst.error = BAD_ARGS;
2364 return;
2365 }
2366
2367 /* rdhi, rdlo and rm must all be different. */
2368 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2369 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2370
2371 if (skip_past_comma (&str) == FAIL
2372 || (rs = reg_required_here (&str, 8)) == FAIL)
2373 {
2374 inst.error = BAD_ARGS;
2375 return;
2376 }
2377
2378 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2379 {
2380 inst.error = BAD_PC;
2381 return;
2382 }
2383
2384 inst.instruction |= flags;
2385 end_of_line (str);
2386 return;
2387 }
2388
2389 static void
2390 do_mul (str, flags)
2391 char * str;
2392 unsigned long flags;
2393 {
2394 int rd, rm;
2395
2396 /* Only one format "rd, rm, rs". */
2397 skip_whitespace (str);
2398
2399 if ((rd = reg_required_here (&str, 16)) == FAIL)
2400 {
2401 inst.error = BAD_ARGS;
2402 return;
2403 }
2404
2405 if (rd == REG_PC)
2406 {
2407 inst.error = BAD_PC;
2408 return;
2409 }
2410
2411 if (skip_past_comma (&str) == FAIL
2412 || (rm = reg_required_here (&str, 0)) == FAIL)
2413 {
2414 inst.error = BAD_ARGS;
2415 return;
2416 }
2417
2418 if (rm == REG_PC)
2419 {
2420 inst.error = BAD_PC;
2421 return;
2422 }
2423
2424 if (rm == rd)
2425 as_tsktsk (_("rd and rm should be different in mul"));
2426
2427 if (skip_past_comma (&str) == FAIL
2428 || (rm = reg_required_here (&str, 8)) == FAIL)
2429 {
2430 inst.error = BAD_ARGS;
2431 return;
2432 }
2433
2434 if (rm == REG_PC)
2435 {
2436 inst.error = BAD_PC;
2437 return;
2438 }
2439
2440 inst.instruction |= flags;
2441 end_of_line (str);
2442 return;
2443 }
2444
2445 static void
2446 do_mla (str, flags)
2447 char * str;
2448 unsigned long flags;
2449 {
2450 int rd, rm;
2451
2452 /* Only one format "rd, rm, rs, rn". */
2453 skip_whitespace (str);
2454
2455 if ((rd = reg_required_here (&str, 16)) == FAIL)
2456 {
2457 inst.error = BAD_ARGS;
2458 return;
2459 }
2460
2461 if (rd == REG_PC)
2462 {
2463 inst.error = BAD_PC;
2464 return;
2465 }
2466
2467 if (skip_past_comma (&str) == FAIL
2468 || (rm = reg_required_here (&str, 0)) == FAIL)
2469 {
2470 inst.error = BAD_ARGS;
2471 return;
2472 }
2473
2474 if (rm == REG_PC)
2475 {
2476 inst.error = BAD_PC;
2477 return;
2478 }
2479
2480 if (rm == rd)
2481 as_tsktsk (_("rd and rm should be different in mla"));
2482
2483 if (skip_past_comma (&str) == FAIL
2484 || (rd = reg_required_here (&str, 8)) == FAIL
2485 || skip_past_comma (&str) == FAIL
2486 || (rm = reg_required_here (&str, 12)) == FAIL)
2487 {
2488 inst.error = BAD_ARGS;
2489 return;
2490 }
2491
2492 if (rd == REG_PC || rm == REG_PC)
2493 {
2494 inst.error = BAD_PC;
2495 return;
2496 }
2497
2498 inst.instruction |= flags;
2499 end_of_line (str);
2500 return;
2501 }
2502
2503 /* Expects *str -> the characters "acc0", possibly with leading blanks.
2504 Advances *str to the next non-alphanumeric.
2505 Returns 0, or else FAIL (in which case sets inst.error).
2506
2507 (In a future XScale, there may be accumulators other than zero.
2508 At that time this routine and its callers can be upgraded to suit.) */
2509
2510 static int
2511 accum0_required_here (str)
2512 char ** str;
2513 {
2514 static char buff [128]; /* Note the address is taken. Hence, static. */
2515 char * p = * str;
2516 char c;
2517 int result = 0; /* The accum number. */
2518
2519 skip_whitespace (p);
2520
2521 *str = p; /* Advance caller's string pointer too. */
2522 c = *p++;
2523 while (ISALNUM (c))
2524 c = *p++;
2525
2526 *--p = 0; /* Aap nul into input buffer at non-alnum. */
2527
2528 if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
2529 {
2530 sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
2531 inst.error = buff;
2532 result = FAIL;
2533 }
2534
2535 *p = c; /* Unzap. */
2536 *str = p; /* Caller's string pointer to after match. */
2537 return result;
2538 }
2539
2540 /* Expects **str -> after a comma. May be leading blanks.
2541 Advances *str, recognizing a load mode, and setting inst.instruction.
2542 Returns rn, or else FAIL (in which case may set inst.error
2543 and not advance str)
2544
2545 Note: doesn't know Rd, so no err checks that require such knowledge. */
2546
2547 static int
2548 ld_mode_required_here (string)
2549 char ** string;
2550 {
2551 char * str = * string;
2552 int rn;
2553 int pre_inc = 0;
2554
2555 skip_whitespace (str);
2556
2557 if (* str == '[')
2558 {
2559 str++;
2560
2561 skip_whitespace (str);
2562
2563 if ((rn = reg_required_here (& str, 16)) == FAIL)
2564 return FAIL;
2565
2566 skip_whitespace (str);
2567
2568 if (* str == ']')
2569 {
2570 str ++;
2571
2572 if (skip_past_comma (& str) == SUCCESS)
2573 {
2574 /* [Rn],... (post inc) */
2575 if (ldst_extend (& str, 1) == FAIL)
2576 return FAIL;
2577 }
2578 else /* [Rn] */
2579 {
2580 skip_whitespace (str);
2581
2582 if (* str == '!')
2583 {
2584 str ++;
2585 inst.instruction |= WRITE_BACK;
2586 }
2587
2588 inst.instruction |= INDEX_UP | HWOFFSET_IMM;
2589 pre_inc = 1;
2590 }
2591 }
2592 else /* [Rn,...] */
2593 {
2594 if (skip_past_comma (& str) == FAIL)
2595 {
2596 inst.error = _("pre-indexed expression expected");
2597 return FAIL;
2598 }
2599
2600 pre_inc = 1;
2601
2602 if (ldst_extend (& str, 1) == FAIL)
2603 return FAIL;
2604
2605 skip_whitespace (str);
2606
2607 if (* str ++ != ']')
2608 {
2609 inst.error = _("missing ]");
2610 return FAIL;
2611 }
2612
2613 skip_whitespace (str);
2614
2615 if (* str == '!')
2616 {
2617 str ++;
2618 inst.instruction |= WRITE_BACK;
2619 }
2620 }
2621 }
2622 else if (* str == '=') /* ldr's "r,=label" syntax */
2623 /* We should never reach here, because <text> = <expression> is
2624 caught gas/read.c read_a_source_file() as a .set operation. */
2625 return FAIL;
2626 else /* PC +- 8 bit immediate offset. */
2627 {
2628 if (my_get_expression (& inst.reloc.exp, & str))
2629 return FAIL;
2630
2631 inst.instruction |= HWOFFSET_IMM; /* The I bit. */
2632 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2633 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2634 inst.reloc.pc_rel = 1;
2635 inst.instruction |= (REG_PC << 16);
2636
2637 rn = REG_PC;
2638 pre_inc = 1;
2639 }
2640
2641 inst.instruction |= (pre_inc ? PRE_INDEX : 0);
2642 * string = str;
2643
2644 return rn;
2645 }
2646
2647 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
2648 SMLAxy{cond} Rd,Rm,Rs,Rn
2649 SMLAWy{cond} Rd,Rm,Rs,Rn
2650 Error if any register is R15. */
2651
2652 static void
2653 do_smla (str, flags)
2654 char * str;
2655 unsigned long flags;
2656 {
2657 int rd, rm, rs, rn;
2658
2659 skip_whitespace (str);
2660
2661 if ((rd = reg_required_here (& str, 16)) == FAIL
2662 || skip_past_comma (& str) == FAIL
2663 || (rm = reg_required_here (& str, 0)) == FAIL
2664 || skip_past_comma (& str) == FAIL
2665 || (rs = reg_required_here (& str, 8)) == FAIL
2666 || skip_past_comma (& str) == FAIL
2667 || (rn = reg_required_here (& str, 12)) == FAIL)
2668 inst.error = BAD_ARGS;
2669
2670 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
2671 inst.error = BAD_PC;
2672
2673 else if (flags)
2674 inst.error = BAD_FLAGS;
2675
2676 else
2677 end_of_line (str);
2678 }
2679
2680 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
2681 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
2682 Error if any register is R15.
2683 Warning if Rdlo == Rdhi. */
2684
2685 static void
2686 do_smlal (str, flags)
2687 char * str;
2688 unsigned long flags;
2689 {
2690 int rdlo, rdhi, rm, rs;
2691
2692 skip_whitespace (str);
2693
2694 if ((rdlo = reg_required_here (& str, 12)) == FAIL
2695 || skip_past_comma (& str) == FAIL
2696 || (rdhi = reg_required_here (& str, 16)) == FAIL
2697 || skip_past_comma (& str) == FAIL
2698 || (rm = reg_required_here (& str, 0)) == FAIL
2699 || skip_past_comma (& str) == FAIL
2700 || (rs = reg_required_here (& str, 8)) == FAIL)
2701 {
2702 inst.error = BAD_ARGS;
2703 return;
2704 }
2705
2706 if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
2707 {
2708 inst.error = BAD_PC;
2709 return;
2710 }
2711
2712 if (rdlo == rdhi)
2713 as_tsktsk (_("rdhi and rdlo must be different"));
2714
2715 if (flags)
2716 inst.error = BAD_FLAGS;
2717 else
2718 end_of_line (str);
2719 }
2720
2721 /* ARM V5E (El Segundo) signed-multiply (argument parse)
2722 SMULxy{cond} Rd,Rm,Rs
2723 Error if any register is R15. */
2724
2725 static void
2726 do_smul (str, flags)
2727 char * str;
2728 unsigned long flags;
2729 {
2730 int rd, rm, rs;
2731
2732 skip_whitespace (str);
2733
2734 if ((rd = reg_required_here (& str, 16)) == FAIL
2735 || skip_past_comma (& str) == FAIL
2736 || (rm = reg_required_here (& str, 0)) == FAIL
2737 || skip_past_comma (& str) == FAIL
2738 || (rs = reg_required_here (& str, 8)) == FAIL)
2739 inst.error = BAD_ARGS;
2740
2741 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
2742 inst.error = BAD_PC;
2743
2744 else if (flags)
2745 inst.error = BAD_FLAGS;
2746
2747 else
2748 end_of_line (str);
2749 }
2750
2751 /* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
2752 Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
2753 Error if any register is R15. */
2754
2755 static void
2756 do_qadd (str, flags)
2757 char * str;
2758 unsigned long flags;
2759 {
2760 int rd, rm, rn;
2761
2762 skip_whitespace (str);
2763
2764 if ((rd = reg_required_here (& str, 12)) == FAIL
2765 || skip_past_comma (& str) == FAIL
2766 || (rm = reg_required_here (& str, 0)) == FAIL
2767 || skip_past_comma (& str) == FAIL
2768 || (rn = reg_required_here (& str, 16)) == FAIL)
2769 inst.error = BAD_ARGS;
2770
2771 else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
2772 inst.error = BAD_PC;
2773
2774 else if (flags)
2775 inst.error = BAD_FLAGS;
2776
2777 else
2778 end_of_line (str);
2779 }
2780
2781 /* ARM V5E (el Segundo)
2782 MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2783 MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2784
2785 These are equivalent to the XScale instructions MAR and MRA,
2786 respectively, when coproc == 0, opcode == 0, and CRm == 0.
2787
2788 Result unpredicatable if Rd or Rn is R15. */
2789
2790 static void
2791 do_co_reg2c (str, flags)
2792 char * str;
2793 unsigned long flags;
2794 {
2795 int rd, rn;
2796
2797 skip_whitespace (str);
2798
2799 if (co_proc_number (& str) == FAIL)
2800 {
2801 if (!inst.error)
2802 inst.error = BAD_ARGS;
2803 return;
2804 }
2805
2806 if (skip_past_comma (& str) == FAIL
2807 || cp_opc_expr (& str, 4, 4) == FAIL)
2808 {
2809 if (!inst.error)
2810 inst.error = BAD_ARGS;
2811 return;
2812 }
2813
2814 if (skip_past_comma (& str) == FAIL
2815 || (rd = reg_required_here (& str, 12)) == FAIL)
2816 {
2817 if (!inst.error)
2818 inst.error = BAD_ARGS;
2819 return;
2820 }
2821
2822 if (skip_past_comma (& str) == FAIL
2823 || (rn = reg_required_here (& str, 16)) == FAIL)
2824 {
2825 if (!inst.error)
2826 inst.error = BAD_ARGS;
2827 return;
2828 }
2829
2830 /* Unpredictable result if rd or rn is R15. */
2831 if (rd == REG_PC || rn == REG_PC)
2832 as_tsktsk
2833 (_("Warning: Instruction unpredictable when using r15"));
2834
2835 if (skip_past_comma (& str) == FAIL
2836 || cp_reg_required_here (& str, 0) == FAIL)
2837 {
2838 if (!inst.error)
2839 inst.error = BAD_ARGS;
2840 return;
2841 }
2842
2843 if (flags)
2844 inst.error = BAD_COND;
2845
2846 end_of_line (str);
2847 }
2848
2849 /* ARM V5 count-leading-zeroes instruction (argument parse)
2850 CLZ{<cond>} <Rd>, <Rm>
2851 Condition defaults to COND_ALWAYS.
2852 Error if Rd or Rm are R15. */
2853
2854 static void
2855 do_clz (str, flags)
2856 char * str;
2857 unsigned long flags;
2858 {
2859 int rd, rm;
2860
2861 if (flags)
2862 {
2863 as_bad (BAD_FLAGS);
2864 return;
2865 }
2866
2867 skip_whitespace (str);
2868
2869 if (((rd = reg_required_here (& str, 12)) == FAIL)
2870 || (skip_past_comma (& str) == FAIL)
2871 || ((rm = reg_required_here (& str, 0)) == FAIL))
2872 inst.error = BAD_ARGS;
2873
2874 else if (rd == REG_PC || rm == REG_PC )
2875 inst.error = BAD_PC;
2876
2877 else
2878 end_of_line (str);
2879 }
2880
2881 /* ARM V5 (argument parse)
2882 LDC2{L} <coproc>, <CRd>, <addressing mode>
2883 STC2{L} <coproc>, <CRd>, <addressing mode>
2884 Instruction is not conditional, and has 0xf in the codition field.
2885 Otherwise, it's the same as LDC/STC. */
2886
2887 static void
2888 do_lstc2 (str, flags)
2889 char * str;
2890 unsigned long flags;
2891 {
2892 if (flags)
2893 inst.error = BAD_COND;
2894
2895 skip_whitespace (str);
2896
2897 if (co_proc_number (& str) == FAIL)
2898 {
2899 if (!inst.error)
2900 inst.error = BAD_ARGS;
2901 }
2902 else if (skip_past_comma (& str) == FAIL
2903 || cp_reg_required_here (& str, 12) == FAIL)
2904 {
2905 if (!inst.error)
2906 inst.error = BAD_ARGS;
2907 }
2908 else if (skip_past_comma (& str) == FAIL
2909 || cp_address_required_here (& str) == FAIL)
2910 {
2911 if (! inst.error)
2912 inst.error = BAD_ARGS;
2913 }
2914 else
2915 end_of_line (str);
2916 }
2917
2918 /* ARM V5 (argument parse)
2919 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
2920 Instruction is not conditional, and has 0xf in the condition field.
2921 Otherwise, it's the same as CDP. */
2922
2923 static void
2924 do_cdp2 (str, flags)
2925 char * str;
2926 unsigned long flags;
2927 {
2928 skip_whitespace (str);
2929
2930 if (co_proc_number (& str) == FAIL)
2931 {
2932 if (!inst.error)
2933 inst.error = BAD_ARGS;
2934 return;
2935 }
2936
2937 if (skip_past_comma (& str) == FAIL
2938 || cp_opc_expr (& str, 20,4) == FAIL)
2939 {
2940 if (!inst.error)
2941 inst.error = BAD_ARGS;
2942 return;
2943 }
2944
2945 if (skip_past_comma (& str) == FAIL
2946 || cp_reg_required_here (& str, 12) == FAIL)
2947 {
2948 if (!inst.error)
2949 inst.error = BAD_ARGS;
2950 return;
2951 }
2952
2953 if (skip_past_comma (& str) == FAIL
2954 || cp_reg_required_here (& str, 16) == FAIL)
2955 {
2956 if (!inst.error)
2957 inst.error = BAD_ARGS;
2958 return;
2959 }
2960
2961 if (skip_past_comma (& str) == FAIL
2962 || cp_reg_required_here (& str, 0) == FAIL)
2963 {
2964 if (!inst.error)
2965 inst.error = BAD_ARGS;
2966 return;
2967 }
2968
2969 if (skip_past_comma (& str) == SUCCESS)
2970 {
2971 if (cp_opc_expr (& str, 5, 3) == FAIL)
2972 {
2973 if (!inst.error)
2974 inst.error = BAD_ARGS;
2975 return;
2976 }
2977 }
2978
2979 if (flags)
2980 inst.error = BAD_FLAGS;
2981
2982 end_of_line (str);
2983 }
2984
2985 /* ARM V5 (argument parse)
2986 MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2987 MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2988 Instruction is not conditional, and has 0xf in the condition field.
2989 Otherwise, it's the same as MCR/MRC. */
2990
2991 static void
2992 do_co_reg2 (str, flags)
2993 char * str;
2994 unsigned long flags;
2995 {
2996 skip_whitespace (str);
2997
2998 if (co_proc_number (& str) == FAIL)
2999 {
3000 if (!inst.error)
3001 inst.error = BAD_ARGS;
3002 return;
3003 }
3004
3005 if (skip_past_comma (& str) == FAIL
3006 || cp_opc_expr (& str, 21, 3) == FAIL)
3007 {
3008 if (!inst.error)
3009 inst.error = BAD_ARGS;
3010 return;
3011 }
3012
3013 if (skip_past_comma (& str) == FAIL
3014 || reg_required_here (& str, 12) == FAIL)
3015 {
3016 if (!inst.error)
3017 inst.error = BAD_ARGS;
3018 return;
3019 }
3020
3021 if (skip_past_comma (& str) == FAIL
3022 || cp_reg_required_here (& str, 16) == FAIL)
3023 {
3024 if (!inst.error)
3025 inst.error = BAD_ARGS;
3026 return;
3027 }
3028
3029 if (skip_past_comma (& str) == FAIL
3030 || cp_reg_required_here (& str, 0) == FAIL)
3031 {
3032 if (!inst.error)
3033 inst.error = BAD_ARGS;
3034 return;
3035 }
3036
3037 if (skip_past_comma (& str) == SUCCESS)
3038 {
3039 if (cp_opc_expr (& str, 5, 3) == FAIL)
3040 {
3041 if (!inst.error)
3042 inst.error = BAD_ARGS;
3043 return;
3044 }
3045 }
3046
3047 if (flags)
3048 inst.error = BAD_COND;
3049
3050 end_of_line (str);
3051 }
3052
3053 /* THUMB V5 breakpoint instruction (argument parse)
3054 BKPT <immed_8>. */
3055
3056 static void
3057 do_t_bkpt (str)
3058 char * str;
3059 {
3060 expressionS expr;
3061 unsigned long number;
3062
3063 skip_whitespace (str);
3064
3065 /* Allow optional leading '#'. */
3066 if (is_immediate_prefix (*str))
3067 str ++;
3068
3069 memset (& expr, '\0', sizeof (expr));
3070 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3071 {
3072 inst.error = _("bad or missing expression");
3073 return;
3074 }
3075
3076 number = expr.X_add_number;
3077
3078 /* Check it fits an 8 bit unsigned. */
3079 if (number != (number & 0xff))
3080 {
3081 inst.error = _("immediate value out of range");
3082 return;
3083 }
3084
3085 inst.instruction |= number;
3086
3087 end_of_line (str);
3088 }
3089
3090 /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
3091 Expects inst.instruction is set for BLX(1).
3092 Note: this is cloned from do_branch, and the reloc changed to be a
3093 new one that can cope with setting one extra bit (the H bit). */
3094
3095 static void
3096 do_branch25 (str, flags)
3097 char * str;
3098 unsigned long flags ATTRIBUTE_UNUSED;
3099 {
3100 if (my_get_expression (& inst.reloc.exp, & str))
3101 return;
3102
3103 #ifdef OBJ_ELF
3104 {
3105 char * save_in;
3106
3107 /* ScottB: February 5, 1998 */
3108 /* Check to see of PLT32 reloc required for the instruction. */
3109
3110 /* arm_parse_reloc() works on input_line_pointer.
3111 We actually want to parse the operands to the branch instruction
3112 passed in 'str'. Save the input pointer and restore it later. */
3113 save_in = input_line_pointer;
3114 input_line_pointer = str;
3115
3116 if (inst.reloc.exp.X_op == O_symbol
3117 && *str == '('
3118 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3119 {
3120 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3121 inst.reloc.pc_rel = 0;
3122 /* Modify str to point to after parsed operands, otherwise
3123 end_of_line() will complain about the (PLT) left in str. */
3124 str = input_line_pointer;
3125 }
3126 else
3127 {
3128 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3129 inst.reloc.pc_rel = 1;
3130 }
3131
3132 input_line_pointer = save_in;
3133 }
3134 #else
3135 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3136 inst.reloc.pc_rel = 1;
3137 #endif /* OBJ_ELF */
3138
3139 end_of_line (str);
3140 }
3141
3142 /* ARM V5 branch-link-exchange instruction (argument parse)
3143 BLX <target_addr> ie BLX(1)
3144 BLX{<condition>} <Rm> ie BLX(2)
3145 Unfortunately, there are two different opcodes for this mnemonic.
3146 So, the insns[].value is not used, and the code here zaps values
3147 into inst.instruction.
3148 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
3149
3150 static void
3151 do_blx (str, flags)
3152 char * str;
3153 unsigned long flags;
3154 {
3155 char * mystr = str;
3156 int rm;
3157
3158 if (flags)
3159 {
3160 as_bad (BAD_FLAGS);
3161 return;
3162 }
3163
3164 skip_whitespace (mystr);
3165 rm = reg_required_here (& mystr, 0);
3166
3167 /* The above may set inst.error. Ignore his opinion. */
3168 inst.error = 0;
3169
3170 if (rm != FAIL)
3171 {
3172 /* Arg is a register.
3173 Use the condition code our caller put in inst.instruction.
3174 Pass ourselves off as a BX with a funny opcode. */
3175 inst.instruction |= 0x012fff30;
3176 do_bx (str, flags);
3177 }
3178 else
3179 {
3180 /* This must be is BLX <target address>, no condition allowed. */
3181 if (inst.instruction != COND_ALWAYS)
3182 {
3183 inst.error = BAD_COND;
3184 return;
3185 }
3186
3187 inst.instruction = 0xfafffffe;
3188
3189 /* Process like a B/BL, but with a different reloc.
3190 Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
3191 do_branch25 (str, flags);
3192 }
3193 }
3194
3195 /* ARM V5 Thumb BLX (argument parse)
3196 BLX <target_addr> which is BLX(1)
3197 BLX <Rm> which is BLX(2)
3198 Unfortunately, there are two different opcodes for this mnemonic.
3199 So, the tinsns[].value is not used, and the code here zaps values
3200 into inst.instruction. */
3201
3202 static void
3203 do_t_blx (str)
3204 char * str;
3205 {
3206 char * mystr = str;
3207 int rm;
3208
3209 skip_whitespace (mystr);
3210 inst.instruction = 0x4780;
3211
3212 /* Note that this call is to the ARM register recognizer. BLX(2)
3213 uses the ARM register space, not the Thumb one, so a call to
3214 thumb_reg() would be wrong. */
3215 rm = reg_required_here (& mystr, 3);
3216 inst.error = 0;
3217
3218 if (rm != FAIL)
3219 {
3220 /* It's BLX(2). The .instruction was zapped with rm & is final. */
3221 inst.size = 2;
3222 }
3223 else
3224 {
3225 /* No ARM register. This must be BLX(1). Change the .instruction. */
3226 inst.instruction = 0xf7ffeffe;
3227 inst.size = 4;
3228
3229 if (my_get_expression (& inst.reloc.exp, & mystr))
3230 return;
3231
3232 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
3233 inst.reloc.pc_rel = 1;
3234 }
3235
3236 end_of_line (mystr);
3237 }
3238
3239 /* ARM V5 breakpoint instruction (argument parse)
3240 BKPT <16 bit unsigned immediate>
3241 Instruction is not conditional.
3242 The bit pattern given in insns[] has the COND_ALWAYS condition,
3243 and it is an error if the caller tried to override that.
3244 Note "flags" is nonzero if a flag was supplied (which is an error). */
3245
3246 static void
3247 do_bkpt (str, flags)
3248 char * str;
3249 unsigned long flags;
3250 {
3251 expressionS expr;
3252 unsigned long number;
3253
3254 skip_whitespace (str);
3255
3256 /* Allow optional leading '#'. */
3257 if (is_immediate_prefix (* str))
3258 str++;
3259
3260 memset (& expr, '\0', sizeof (expr));
3261
3262 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3263 {
3264 inst.error = _("bad or missing expression");
3265 return;
3266 }
3267
3268 number = expr.X_add_number;
3269
3270 /* Check it fits a 16 bit unsigned. */
3271 if (number != (number & 0xffff))
3272 {
3273 inst.error = _("immediate value out of range");
3274 return;
3275 }
3276
3277 /* Top 12 of 16 bits to bits 19:8. */
3278 inst.instruction |= (number & 0xfff0) << 4;
3279
3280 /* Bottom 4 of 16 bits to bits 3:0. */
3281 inst.instruction |= number & 0xf;
3282
3283 end_of_line (str);
3284
3285 if (flags)
3286 inst.error = BAD_FLAGS;
3287 }
3288
3289 /* Xscale multiply-accumulate (argument parse)
3290 MIAcc acc0,Rm,Rs
3291 MIAPHcc acc0,Rm,Rs
3292 MIAxycc acc0,Rm,Rs. */
3293
3294 static void
3295 do_mia (str, flags)
3296 char * str;
3297 unsigned long flags;
3298 {
3299 int rs;
3300 int rm;
3301
3302 if (flags)
3303 as_bad (BAD_FLAGS);
3304
3305 else if (accum0_required_here (& str) == FAIL)
3306 inst.error = ERR_NO_ACCUM;
3307
3308 else if (skip_past_comma (& str) == FAIL
3309 || (rm = reg_required_here (& str, 0)) == FAIL)
3310 inst.error = BAD_ARGS;
3311
3312 else if (skip_past_comma (& str) == FAIL
3313 || (rs = reg_required_here (& str, 12)) == FAIL)
3314 inst.error = BAD_ARGS;
3315
3316 /* inst.instruction has now been zapped with both rm and rs. */
3317 else if (rm == REG_PC || rs == REG_PC)
3318 inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
3319
3320 else
3321 end_of_line (str);
3322 }
3323
3324 /* Xscale move-accumulator-register (argument parse)
3325
3326 MARcc acc0,RdLo,RdHi. */
3327
3328 static void
3329 do_mar (str, flags)
3330 char * str;
3331 unsigned long flags;
3332 {
3333 int rdlo, rdhi;
3334
3335 if (flags)
3336 as_bad (BAD_FLAGS);
3337
3338 else if (accum0_required_here (& str) == FAIL)
3339 inst.error = ERR_NO_ACCUM;
3340
3341 else if (skip_past_comma (& str) == FAIL
3342 || (rdlo = reg_required_here (& str, 12)) == FAIL)
3343 inst.error = BAD_ARGS;
3344
3345 else if (skip_past_comma (& str) == FAIL
3346 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3347 inst.error = BAD_ARGS;
3348
3349 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3350 else if (rdlo == REG_PC || rdhi == REG_PC)
3351 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3352
3353 else
3354 end_of_line (str);
3355 }
3356
3357 /* Xscale move-register-accumulator (argument parse)
3358
3359 MRAcc RdLo,RdHi,acc0. */
3360
3361 static void
3362 do_mra (str, flags)
3363 char * str;
3364 unsigned long flags;
3365 {
3366 int rdlo;
3367 int rdhi;
3368
3369 if (flags)
3370 {
3371 as_bad (BAD_FLAGS);
3372 return;
3373 }
3374
3375 skip_whitespace (str);
3376
3377 if ((rdlo = reg_required_here (& str, 12)) == FAIL)
3378 inst.error = BAD_ARGS;
3379
3380 else if (skip_past_comma (& str) == FAIL
3381 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3382 inst.error = BAD_ARGS;
3383
3384 else if (skip_past_comma (& str) == FAIL
3385 || accum0_required_here (& str) == FAIL)
3386 inst.error = ERR_NO_ACCUM;
3387
3388 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3389 else if (rdlo == rdhi)
3390 inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
3391
3392 else if (rdlo == REG_PC || rdhi == REG_PC)
3393 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3394 else
3395 end_of_line (str);
3396 }
3397
3398 /* Xscale: Preload-Cache
3399
3400 PLD <addr_mode>
3401
3402 Syntactically, like LDR with B=1, W=0, L=1. */
3403
3404 static void
3405 do_pld (str, flags)
3406 char * str;
3407 unsigned long flags;
3408 {
3409 int rd;
3410
3411 if (flags)
3412 {
3413 as_bad (BAD_FLAGS);
3414 return;
3415 }
3416
3417 skip_whitespace (str);
3418
3419 if (* str != '[')
3420 {
3421 inst.error = _("'[' expected after PLD mnemonic");
3422 return;
3423 }
3424
3425 ++ str;
3426 skip_whitespace (str);
3427
3428 if ((rd = reg_required_here (& str, 16)) == FAIL)
3429 return;
3430
3431 skip_whitespace (str);
3432
3433 if (* str == ']')
3434 {
3435 /* [Rn], ... ? */
3436 ++ str;
3437 skip_whitespace (str);
3438
3439 if (skip_past_comma (& str) == SUCCESS)
3440 {
3441 if (ldst_extend (& str, 0) == FAIL)
3442 return;
3443 }
3444 else if (* str == '!') /* [Rn]! */
3445 {
3446 inst.error = _("writeback used in preload instruction");
3447 ++ str;
3448 }
3449 else /* [Rn] */
3450 inst.instruction |= INDEX_UP | PRE_INDEX;
3451 }
3452 else /* [Rn, ...] */
3453 {
3454 if (skip_past_comma (& str) == FAIL)
3455 {
3456 inst.error = _("pre-indexed expression expected");
3457 return;
3458 }
3459
3460 if (ldst_extend (& str, 0) == FAIL)
3461 return;
3462
3463 skip_whitespace (str);
3464
3465 if (* str != ']')
3466 {
3467 inst.error = _("missing ]");
3468 return;
3469 }
3470
3471 ++ str;
3472 skip_whitespace (str);
3473
3474 if (* str == '!') /* [Rn]! */
3475 {
3476 inst.error = _("writeback used in preload instruction");
3477 ++ str;
3478 }
3479
3480 inst.instruction |= PRE_INDEX;
3481 }
3482
3483 end_of_line (str);
3484 }
3485
3486 /* Xscale load-consecutive (argument parse)
3487 Mode is like LDRH.
3488
3489 LDRccD R, mode
3490 STRccD R, mode. */
3491
3492 static void
3493 do_ldrd (str, flags)
3494 char * str;
3495 unsigned long flags;
3496 {
3497 int rd;
3498 int rn;
3499
3500 if (flags != DOUBLE_LOAD_FLAG)
3501 {
3502 /* Change instruction pattern to normal ldr/str. */
3503 if (inst.instruction & 0x20)
3504 inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */
3505 else
3506 inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */
3507
3508 /* Perform a normal load/store instruction parse. */
3509 do_ldst (str, flags);
3510
3511 return;
3512 }
3513
3514 if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE)
3515 {
3516 static char buff[128];
3517
3518 --str;
3519 while (ISSPACE (*str))
3520 --str;
3521 str -= 4;
3522
3523 /* Deny all knowledge. */
3524 sprintf (buff, _("bad instruction '%.100s'"), str);
3525 inst.error = buff;
3526 return;
3527 }
3528
3529 skip_whitespace (str);
3530
3531 if ((rd = reg_required_here (& str, 12)) == FAIL)
3532 {
3533 inst.error = BAD_ARGS;
3534 return;
3535 }
3536
3537 if (skip_past_comma (& str) == FAIL
3538 || (rn = ld_mode_required_here (& str)) == FAIL)
3539 {
3540 if (!inst.error)
3541 inst.error = BAD_ARGS;
3542 return;
3543 }
3544
3545 /* inst.instruction has now been zapped with Rd and the addressing mode. */
3546 if (rd & 1) /* Unpredictable result if Rd is odd. */
3547 {
3548 inst.error = _("Destination register must be even");
3549 return;
3550 }
3551
3552 if (rd == REG_LR || rd == 12)
3553 {
3554 inst.error = _("r12 or r14 not allowed here");
3555 return;
3556 }
3557
3558 if (((rd == rn) || (rd + 1 == rn))
3559 &&
3560 ((inst.instruction & WRITE_BACK)
3561 || (!(inst.instruction & PRE_INDEX))))
3562 as_warn (_("pre/post-indexing used when modified address register is destination"));
3563
3564 end_of_line (str);
3565 }
3566
3567 /* Returns the index into fp_values of a floating point number,
3568 or -1 if not in the table. */
3569
3570 static int
3571 my_get_float_expression (str)
3572 char ** str;
3573 {
3574 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3575 char * save_in;
3576 expressionS exp;
3577 int i;
3578 int j;
3579
3580 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3581
3582 /* Look for a raw floating point number. */
3583 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3584 && is_end_of_line[(unsigned char) *save_in])
3585 {
3586 for (i = 0; i < NUM_FLOAT_VALS; i++)
3587 {
3588 for (j = 0; j < MAX_LITTLENUMS; j++)
3589 {
3590 if (words[j] != fp_values[i][j])
3591 break;
3592 }
3593
3594 if (j == MAX_LITTLENUMS)
3595 {
3596 *str = save_in;
3597 return i;
3598 }
3599 }
3600 }
3601
3602 /* Try and parse a more complex expression, this will probably fail
3603 unless the code uses a floating point prefix (eg "0f"). */
3604 save_in = input_line_pointer;
3605 input_line_pointer = *str;
3606 if (expression (&exp) == absolute_section
3607 && exp.X_op == O_big
3608 && exp.X_add_number < 0)
3609 {
3610 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3611 Ditto for 15. */
3612 if (gen_to_words (words, 5, (long) 15) == 0)
3613 {
3614 for (i = 0; i < NUM_FLOAT_VALS; i++)
3615 {
3616 for (j = 0; j < MAX_LITTLENUMS; j++)
3617 {
3618 if (words[j] != fp_values[i][j])
3619 break;
3620 }
3621
3622 if (j == MAX_LITTLENUMS)
3623 {
3624 *str = input_line_pointer;
3625 input_line_pointer = save_in;
3626 return i;
3627 }
3628 }
3629 }
3630 }
3631
3632 *str = input_line_pointer;
3633 input_line_pointer = save_in;
3634 return -1;
3635 }
3636
3637 /* Return true if anything in the expression is a bignum. */
3638
3639 static int
3640 walk_no_bignums (sp)
3641 symbolS * sp;
3642 {
3643 if (symbol_get_value_expression (sp)->X_op == O_big)
3644 return 1;
3645
3646 if (symbol_get_value_expression (sp)->X_add_symbol)
3647 {
3648 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
3649 || (symbol_get_value_expression (sp)->X_op_symbol
3650 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3651 }
3652
3653 return 0;
3654 }
3655
3656 static int
3657 my_get_expression (ep, str)
3658 expressionS * ep;
3659 char ** str;
3660 {
3661 char * save_in;
3662 segT seg;
3663
3664 save_in = input_line_pointer;
3665 input_line_pointer = *str;
3666 seg = expression (ep);
3667
3668 #ifdef OBJ_AOUT
3669 if (seg != absolute_section
3670 && seg != text_section
3671 && seg != data_section
3672 && seg != bss_section
3673 && seg != undefined_section)
3674 {
3675 inst.error = _("bad_segment");
3676 *str = input_line_pointer;
3677 input_line_pointer = save_in;
3678 return 1;
3679 }
3680 #endif
3681
3682 /* Get rid of any bignums now, so that we don't generate an error for which
3683 we can't establish a line number later on. Big numbers are never valid
3684 in instructions, which is where this routine is always called. */
3685 if (ep->X_op == O_big
3686 || (ep->X_add_symbol
3687 && (walk_no_bignums (ep->X_add_symbol)
3688 || (ep->X_op_symbol
3689 && walk_no_bignums (ep->X_op_symbol)))))
3690 {
3691 inst.error = _("Invalid constant");
3692 *str = input_line_pointer;
3693 input_line_pointer = save_in;
3694 return 1;
3695 }
3696
3697 *str = input_line_pointer;
3698 input_line_pointer = save_in;
3699 return 0;
3700 }
3701
3702 /* UNRESTRICT should be one if <shift> <register> is permitted for this
3703 instruction. */
3704
3705 static int
3706 decode_shift (str, unrestrict)
3707 char ** str;
3708 int unrestrict;
3709 {
3710 const struct asm_shift_name * shift;
3711 char * p;
3712 char c;
3713
3714 skip_whitespace (* str);
3715
3716 for (p = * str; ISALPHA (* p); p ++)
3717 ;
3718
3719 if (p == * str)
3720 {
3721 inst.error = _("Shift expression expected");
3722 return FAIL;
3723 }
3724
3725 c = * p;
3726 * p = '\0';
3727 shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
3728 * p = c;
3729
3730 if (shift == NULL)
3731 {
3732 inst.error = _("Shift expression expected");
3733 return FAIL;
3734 }
3735
3736 assert (shift->properties->index == shift_properties[shift->properties->index].index);
3737
3738 if (shift->properties->index == SHIFT_RRX)
3739 {
3740 * str = p;
3741 inst.instruction |= shift->properties->bit_field;
3742 return SUCCESS;
3743 }
3744
3745 skip_whitespace (p);
3746
3747 if (unrestrict && reg_required_here (& p, 8) != FAIL)
3748 {
3749 inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
3750 * str = p;
3751 return SUCCESS;
3752 }
3753 else if (! is_immediate_prefix (* p))
3754 {
3755 inst.error = (unrestrict
3756 ? _("shift requires register or #expression")
3757 : _("shift requires #expression"));
3758 * str = p;
3759 return FAIL;
3760 }
3761
3762 inst.error = NULL;
3763 p ++;
3764
3765 if (my_get_expression (& inst.reloc.exp, & p))
3766 return FAIL;
3767
3768 /* Validate some simple #expressions. */
3769 if (inst.reloc.exp.X_op == O_constant)
3770 {
3771 unsigned num = inst.reloc.exp.X_add_number;
3772
3773 /* Reject operations greater than 32. */
3774 if (num > 32
3775 /* Reject a shift of 0 unless the mode allows it. */
3776 || (num == 0 && shift->properties->allows_0 == 0)
3777 /* Reject a shift of 32 unless the mode allows it. */
3778 || (num == 32 && shift->properties->allows_32 == 0)
3779 )
3780 {
3781 /* As a special case we allow a shift of zero for
3782 modes that do not support it to be recoded as an
3783 logical shift left of zero (ie nothing). We warn
3784 about this though. */
3785 if (num == 0)
3786 {
3787 as_warn (_("Shift of 0 ignored."));
3788 shift = & shift_names[0];
3789 assert (shift->properties->index == SHIFT_LSL);
3790 }
3791 else
3792 {
3793 inst.error = _("Invalid immediate shift");
3794 return FAIL;
3795 }
3796 }
3797
3798 /* Shifts of 32 are encoded as 0, for those shifts that
3799 support it. */
3800 if (num == 32)
3801 num = 0;
3802
3803 inst.instruction |= (num << 7) | shift->properties->bit_field;
3804 }
3805 else
3806 {
3807 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
3808 inst.reloc.pc_rel = 0;
3809 inst.instruction |= shift->properties->bit_field;
3810 }
3811
3812 * str = p;
3813 return SUCCESS;
3814 }
3815
3816 /* Do those data_ops which can take a negative immediate constant
3817 by altering the instuction. A bit of a hack really.
3818 MOV <-> MVN
3819 AND <-> BIC
3820 ADC <-> SBC
3821 by inverting the second operand, and
3822 ADD <-> SUB
3823 CMP <-> CMN
3824 by negating the second operand. */
3825
3826 static int
3827 negate_data_op (instruction, value)
3828 unsigned long * instruction;
3829 unsigned long value;
3830 {
3831 int op, new_inst;
3832 unsigned long negated, inverted;
3833
3834 negated = validate_immediate (-value);
3835 inverted = validate_immediate (~value);
3836
3837 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
3838 switch (op)
3839 {
3840 /* First negates. */
3841 case OPCODE_SUB: /* ADD <-> SUB */
3842 new_inst = OPCODE_ADD;
3843 value = negated;
3844 break;
3845
3846 case OPCODE_ADD:
3847 new_inst = OPCODE_SUB;
3848 value = negated;
3849 break;
3850
3851 case OPCODE_CMP: /* CMP <-> CMN */
3852 new_inst = OPCODE_CMN;
3853 value = negated;
3854 break;
3855
3856 case OPCODE_CMN:
3857 new_inst = OPCODE_CMP;
3858 value = negated;
3859 break;
3860
3861 /* Now Inverted ops. */
3862 case OPCODE_MOV: /* MOV <-> MVN */
3863 new_inst = OPCODE_MVN;
3864 value = inverted;
3865 break;
3866
3867 case OPCODE_MVN:
3868 new_inst = OPCODE_MOV;
3869 value = inverted;
3870 break;
3871
3872 case OPCODE_AND: /* AND <-> BIC */
3873 new_inst = OPCODE_BIC;
3874 value = inverted;
3875 break;
3876
3877 case OPCODE_BIC:
3878 new_inst = OPCODE_AND;
3879 value = inverted;
3880 break;
3881
3882 case OPCODE_ADC: /* ADC <-> SBC */
3883 new_inst = OPCODE_SBC;
3884 value = inverted;
3885 break;
3886
3887 case OPCODE_SBC:
3888 new_inst = OPCODE_ADC;
3889 value = inverted;
3890 break;
3891
3892 /* We cannot do anything. */
3893 default:
3894 return FAIL;
3895 }
3896
3897 if (value == (unsigned) FAIL)
3898 return FAIL;
3899
3900 *instruction &= OPCODE_MASK;
3901 *instruction |= new_inst << DATA_OP_SHIFT;
3902 return value;
3903 }
3904
3905 static int
3906 data_op2 (str)
3907 char ** str;
3908 {
3909 int value;
3910 expressionS expr;
3911
3912 skip_whitespace (* str);
3913
3914 if (reg_required_here (str, 0) != FAIL)
3915 {
3916 if (skip_past_comma (str) == SUCCESS)
3917 /* Shift operation on register. */
3918 return decode_shift (str, NO_SHIFT_RESTRICT);
3919
3920 return SUCCESS;
3921 }
3922 else
3923 {
3924 /* Immediate expression. */
3925 if (is_immediate_prefix (**str))
3926 {
3927 (*str)++;
3928 inst.error = NULL;
3929
3930 if (my_get_expression (&inst.reloc.exp, str))
3931 return FAIL;
3932
3933 if (inst.reloc.exp.X_add_symbol)
3934 {
3935 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3936 inst.reloc.pc_rel = 0;
3937 }
3938 else
3939 {
3940 if (skip_past_comma (str) == SUCCESS)
3941 {
3942 /* #x, y -- ie explicit rotation by Y. */
3943 if (my_get_expression (&expr, str))
3944 return FAIL;
3945
3946 if (expr.X_op != O_constant)
3947 {
3948 inst.error = _("Constant expression expected");
3949 return FAIL;
3950 }
3951
3952 /* Rotate must be a multiple of 2. */
3953 if (((unsigned) expr.X_add_number) > 30
3954 || (expr.X_add_number & 1) != 0
3955 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
3956 {
3957 inst.error = _("Invalid constant");
3958 return FAIL;
3959 }
3960 inst.instruction |= INST_IMMEDIATE;
3961 inst.instruction |= inst.reloc.exp.X_add_number;
3962 inst.instruction |= expr.X_add_number << 7;
3963 return SUCCESS;
3964 }
3965
3966 /* Implicit rotation, select a suitable one. */
3967 value = validate_immediate (inst.reloc.exp.X_add_number);
3968
3969 if (value == FAIL)
3970 {
3971 /* Can't be done. Perhaps the code reads something like
3972 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
3973 if ((value = negate_data_op (&inst.instruction,
3974 inst.reloc.exp.X_add_number))
3975 == FAIL)
3976 {
3977 inst.error = _("Invalid constant");
3978 return FAIL;
3979 }
3980 }
3981
3982 inst.instruction |= value;
3983 }
3984
3985 inst.instruction |= INST_IMMEDIATE;
3986 return SUCCESS;
3987 }
3988
3989 (*str)++;
3990 inst.error = _("Register or shift expression expected");
3991 return FAIL;
3992 }
3993 }
3994
3995 static int
3996 fp_op2 (str)
3997 char ** str;
3998 {
3999 skip_whitespace (* str);
4000
4001 if (fp_reg_required_here (str, 0) != FAIL)
4002 return SUCCESS;
4003 else
4004 {
4005 /* Immediate expression. */
4006 if (*((*str)++) == '#')
4007 {
4008 int i;
4009
4010 inst.error = NULL;
4011
4012 skip_whitespace (* str);
4013
4014 /* First try and match exact strings, this is to guarantee
4015 that some formats will work even for cross assembly. */
4016
4017 for (i = 0; fp_const[i]; i++)
4018 {
4019 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4020 {
4021 char *start = *str;
4022
4023 *str += strlen (fp_const[i]);
4024 if (is_end_of_line[(unsigned char) **str])
4025 {
4026 inst.instruction |= i + 8;
4027 return SUCCESS;
4028 }
4029 *str = start;
4030 }
4031 }
4032
4033 /* Just because we didn't get a match doesn't mean that the
4034 constant isn't valid, just that it is in a format that we
4035 don't automatically recognize. Try parsing it with
4036 the standard expression routines. */
4037 if ((i = my_get_float_expression (str)) >= 0)
4038 {
4039 inst.instruction |= i + 8;
4040 return SUCCESS;
4041 }
4042
4043 inst.error = _("Invalid floating point immediate expression");
4044 return FAIL;
4045 }
4046 inst.error =
4047 _("Floating point register or immediate expression expected");
4048 return FAIL;
4049 }
4050 }
4051
4052 static void
4053 do_arit (str, flags)
4054 char * str;
4055 unsigned long flags;
4056 {
4057 skip_whitespace (str);
4058
4059 if (reg_required_here (&str, 12) == FAIL
4060 || skip_past_comma (&str) == FAIL
4061 || reg_required_here (&str, 16) == FAIL
4062 || skip_past_comma (&str) == FAIL
4063 || data_op2 (&str) == FAIL)
4064 {
4065 if (!inst.error)
4066 inst.error = BAD_ARGS;
4067 return;
4068 }
4069
4070 inst.instruction |= flags;
4071 end_of_line (str);
4072 return;
4073 }
4074
4075 static void
4076 do_adr (str, flags)
4077 char * str;
4078 unsigned long flags;
4079 {
4080 skip_whitespace (str);
4081
4082 if (reg_required_here (&str, 12) == FAIL
4083 || skip_past_comma (&str) == FAIL
4084 || my_get_expression (&inst.reloc.exp, &str))
4085 {
4086 if (!inst.error)
4087 inst.error = BAD_ARGS;
4088 return;
4089 }
4090
4091 if (flags & 0x00400000)
4092 {
4093 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4094 into a relative address of the form:
4095 add rd, pc, #low(label-.-8)"
4096 add rd, rd, #high(label-.-8)" */
4097 /* Frag hacking will turn this into a sub instruction if the offset turns
4098 out to be negative. */
4099 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4100 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
4101 inst.reloc.pc_rel = 1;
4102 inst.instruction |= flags & ~0x00400000;
4103 inst.size = INSN_SIZE * 2;
4104 }
4105 else
4106 {
4107 /* This is a pseudo-op of the form "adr rd, label" to be converted
4108 into a relative address of the form "add rd, pc, #label-.-8". */
4109 /* Frag hacking will turn this into a sub instruction if the offset turns
4110 out to be negative. */
4111 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4112 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
4113 inst.reloc.pc_rel = 1;
4114 inst.instruction |= flags;
4115 }
4116
4117 end_of_line (str);
4118 }
4119
4120 static void
4121 do_cmp (str, flags)
4122 char * str;
4123 unsigned long flags;
4124 {
4125 skip_whitespace (str);
4126
4127 if (reg_required_here (&str, 16) == FAIL)
4128 {
4129 if (!inst.error)
4130 inst.error = BAD_ARGS;
4131 return;
4132 }
4133
4134 if (skip_past_comma (&str) == FAIL
4135 || data_op2 (&str) == FAIL)
4136 {
4137 if (!inst.error)
4138 inst.error = BAD_ARGS;
4139 return;
4140 }
4141
4142 inst.instruction |= flags;
4143 if ((flags & 0x0000f000) == 0)
4144 inst.instruction |= CONDS_BIT;
4145
4146 end_of_line (str);
4147 return;
4148 }
4149
4150 static void
4151 do_mov (str, flags)
4152 char * str;
4153 unsigned long flags;
4154 {
4155 skip_whitespace (str);
4156
4157 if (reg_required_here (&str, 12) == FAIL)
4158 {
4159 if (!inst.error)
4160 inst.error = BAD_ARGS;
4161 return;
4162 }
4163
4164 if (skip_past_comma (&str) == FAIL
4165 || data_op2 (&str) == FAIL)
4166 {
4167 if (!inst.error)
4168 inst.error = BAD_ARGS;
4169 return;
4170 }
4171
4172 inst.instruction |= flags;
4173 end_of_line (str);
4174 return;
4175 }
4176
4177 static int
4178 ldst_extend (str, hwse)
4179 char ** str;
4180 int hwse;
4181 {
4182 int add = INDEX_UP;
4183
4184 switch (**str)
4185 {
4186 case '#':
4187 case '$':
4188 (*str)++;
4189 if (my_get_expression (& inst.reloc.exp, str))
4190 return FAIL;
4191
4192 if (inst.reloc.exp.X_op == O_constant)
4193 {
4194 int value = inst.reloc.exp.X_add_number;
4195
4196 if ((hwse && (value < -255 || value > 255))
4197 || (value < -4095 || value > 4095))
4198 {
4199 inst.error = _("address offset too large");
4200 return FAIL;
4201 }
4202
4203 if (value < 0)
4204 {
4205 value = -value;
4206 add = 0;
4207 }
4208
4209 /* Halfword and signextension instructions have the
4210 immediate value split across bits 11..8 and bits 3..0. */
4211 if (hwse)
4212 inst.instruction |= (add | HWOFFSET_IMM
4213 | ((value >> 4) << 8) | (value & 0xF));
4214 else
4215 inst.instruction |= add | value;
4216 }
4217 else
4218 {
4219 if (hwse)
4220 {
4221 inst.instruction |= HWOFFSET_IMM;
4222 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4223 }
4224 else
4225 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4226 inst.reloc.pc_rel = 0;
4227 }
4228 return SUCCESS;
4229
4230 case '-':
4231 add = 0;
4232 /* Fall through. */
4233
4234 case '+':
4235 (*str)++;
4236 /* Fall through. */
4237
4238 default:
4239 if (reg_required_here (str, 0) == FAIL)
4240 return FAIL;
4241
4242 if (hwse)
4243 inst.instruction |= add;
4244 else
4245 {
4246 inst.instruction |= add | OFFSET_REG;
4247 if (skip_past_comma (str) == SUCCESS)
4248 return decode_shift (str, SHIFT_RESTRICT);
4249 }
4250
4251 return SUCCESS;
4252 }
4253 }
4254
4255 static void
4256 do_ldst (str, flags)
4257 char * str;
4258 unsigned long flags;
4259 {
4260 int halfword = 0;
4261 int pre_inc = 0;
4262 int conflict_reg;
4263 int value;
4264
4265 /* This is not ideal, but it is the simplest way of dealing with the
4266 ARM7T halfword instructions (since they use a different
4267 encoding, but the same mnemonic): */
4268 halfword = (flags & 0x80000000) != 0;
4269 if (halfword)
4270 {
4271 /* This is actually a load/store of a halfword, or a
4272 signed-extension load. */
4273 if ((cpu_variant & ARM_EXT_HALFWORD) == 0)
4274 {
4275 inst.error
4276 = _("Processor does not support halfwords or signed bytes");
4277 return;
4278 }
4279
4280 inst.instruction = ((inst.instruction & COND_MASK)
4281 | (flags & ~COND_MASK));
4282
4283 flags = 0;
4284 }
4285
4286 skip_whitespace (str);
4287
4288 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
4289 {
4290 if (!inst.error)
4291 inst.error = BAD_ARGS;
4292 return;
4293 }
4294
4295 if (skip_past_comma (& str) == FAIL)
4296 {
4297 inst.error = _("Address expected");
4298 return;
4299 }
4300
4301 if (*str == '[')
4302 {
4303 int reg;
4304
4305 str++;
4306
4307 skip_whitespace (str);
4308
4309 if ((reg = reg_required_here (&str, 16)) == FAIL)
4310 return;
4311
4312 /* Conflicts can occur on stores as well as loads. */
4313 conflict_reg = (conflict_reg == reg);
4314
4315 skip_whitespace (str);
4316
4317 if (*str == ']')
4318 {
4319 str ++;
4320
4321 if (skip_past_comma (&str) == SUCCESS)
4322 {
4323 /* [Rn],... (post inc) */
4324 if (ldst_extend (&str, halfword) == FAIL)
4325 return;
4326 if (conflict_reg)
4327 {
4328 if (flags & TRANS_BIT)
4329 as_warn (_("Rn and Rd must be different in %s"),
4330 ((inst.instruction & LOAD_BIT)
4331 ? "LDRT" : "STRT"));
4332 else
4333 as_warn (_("%s register same as write-back base"),
4334 ((inst.instruction & LOAD_BIT)
4335 ? _("destination") : _("source")));
4336 }
4337 }
4338 else
4339 {
4340 /* [Rn] */
4341 if (halfword)
4342 inst.instruction |= HWOFFSET_IMM;
4343
4344 skip_whitespace (str);
4345
4346 if (*str == '!')
4347 {
4348 if (conflict_reg)
4349 as_warn (_("%s register same as write-back base"),
4350 ((inst.instruction & LOAD_BIT)
4351 ? _("destination") : _("source")));
4352 str++;
4353 inst.instruction |= WRITE_BACK;
4354 }
4355
4356 flags |= INDEX_UP;
4357 if (flags & TRANS_BIT)
4358 {
4359 if (conflict_reg)
4360 as_warn (_("Rn and Rd must be different in %s"),
4361 ((inst.instruction & LOAD_BIT)
4362 ? "LDRT" : "STRT"));
4363 }
4364 else
4365 pre_inc = 1;
4366 }
4367 }
4368 else
4369 {
4370 /* [Rn,...] */
4371 if (skip_past_comma (&str) == FAIL)
4372 {
4373 inst.error = _("pre-indexed expression expected");
4374 return;
4375 }
4376
4377 pre_inc = 1;
4378 if (ldst_extend (&str, halfword) == FAIL)
4379 return;
4380
4381 skip_whitespace (str);
4382
4383 if (*str++ != ']')
4384 {
4385 inst.error = _("missing ]");
4386 return;
4387 }
4388
4389 skip_whitespace (str);
4390
4391 if (*str == '!')
4392 {
4393 if (conflict_reg)
4394 as_warn (_("%s register same as write-back base"),
4395 ((inst.instruction & LOAD_BIT)
4396 ? _("destination") : _("source")));
4397 str++;
4398 inst.instruction |= WRITE_BACK;
4399 }
4400 }
4401 }
4402 else if (*str == '=')
4403 {
4404 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4405 str++;
4406
4407 skip_whitespace (str);
4408
4409 if (my_get_expression (&inst.reloc.exp, &str))
4410 return;
4411
4412 if (inst.reloc.exp.X_op != O_constant
4413 && inst.reloc.exp.X_op != O_symbol)
4414 {
4415 inst.error = _("Constant expression expected");
4416 return;
4417 }
4418
4419 if (inst.reloc.exp.X_op == O_constant)
4420 {
4421 value = validate_immediate (inst.reloc.exp.X_add_number);
4422
4423 if (value != FAIL)
4424 {
4425 /* This can be done with a mov instruction. */
4426 inst.instruction &= LITERAL_MASK;
4427 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4428 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
4429 end_of_line (str);
4430 return;
4431 }
4432
4433 value = validate_immediate (~ inst.reloc.exp.X_add_number);
4434
4435 if (value != FAIL)
4436 {
4437 /* This can be done with a mvn instruction. */
4438 inst.instruction &= LITERAL_MASK;
4439 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4440 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
4441 end_of_line (str);
4442 return;
4443 }
4444 }
4445
4446 /* Insert into literal pool. */
4447 if (add_to_lit_pool () == FAIL)
4448 {
4449 if (!inst.error)
4450 inst.error = _("literal pool insertion failed");
4451 return;
4452 }
4453
4454 /* Change the instruction exp to point to the pool. */
4455 if (halfword)
4456 {
4457 inst.instruction |= HWOFFSET_IMM;
4458 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
4459 }
4460 else
4461 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
4462
4463 inst.reloc.pc_rel = 1;
4464 inst.instruction |= (REG_PC << 16);
4465 pre_inc = 1;
4466 }
4467 else
4468 {
4469 if (my_get_expression (&inst.reloc.exp, &str))
4470 return;
4471
4472 if (halfword)
4473 {
4474 inst.instruction |= HWOFFSET_IMM;
4475 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4476 }
4477 else
4478 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4479 #ifndef TE_WINCE
4480 /* PC rel adjust. */
4481 inst.reloc.exp.X_add_number -= 8;
4482 #endif
4483 inst.reloc.pc_rel = 1;
4484 inst.instruction |= (REG_PC << 16);
4485 pre_inc = 1;
4486 }
4487
4488 if (pre_inc && (flags & TRANS_BIT))
4489 inst.error = _("Pre-increment instruction with translate");
4490
4491 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
4492 end_of_line (str);
4493 return;
4494 }
4495
4496 static long
4497 reg_list (strp)
4498 char ** strp;
4499 {
4500 char * str = * strp;
4501 long range = 0;
4502 int another_range;
4503
4504 /* We come back here if we get ranges concatenated by '+' or '|'. */
4505 do
4506 {
4507 another_range = 0;
4508
4509 if (*str == '{')
4510 {
4511 int in_range = 0;
4512 int cur_reg = -1;
4513
4514 str++;
4515 do
4516 {
4517 int reg;
4518
4519 skip_whitespace (str);
4520
4521 if ((reg = reg_required_here (& str, -1)) == FAIL)
4522 return FAIL;
4523
4524 if (in_range)
4525 {
4526 int i;
4527
4528 if (reg <= cur_reg)
4529 {
4530 inst.error = _("Bad range in register list");
4531 return FAIL;
4532 }
4533
4534 for (i = cur_reg + 1; i < reg; i++)
4535 {
4536 if (range & (1 << i))
4537 as_tsktsk
4538 (_("Warning: Duplicated register (r%d) in register list"),
4539 i);
4540 else
4541 range |= 1 << i;
4542 }
4543 in_range = 0;
4544 }
4545
4546 if (range & (1 << reg))
4547 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
4548 reg);
4549 else if (reg <= cur_reg)
4550 as_tsktsk (_("Warning: Register range not in ascending order"));
4551
4552 range |= 1 << reg;
4553 cur_reg = reg;
4554 }
4555 while (skip_past_comma (&str) != FAIL
4556 || (in_range = 1, *str++ == '-'));
4557 str--;
4558 skip_whitespace (str);
4559
4560 if (*str++ != '}')
4561 {
4562 inst.error = _("Missing `}'");
4563 return FAIL;
4564 }
4565 }
4566 else
4567 {
4568 expressionS expr;
4569
4570 if (my_get_expression (&expr, &str))
4571 return FAIL;
4572
4573 if (expr.X_op == O_constant)
4574 {
4575 if (expr.X_add_number
4576 != (expr.X_add_number & 0x0000ffff))
4577 {
4578 inst.error = _("invalid register mask");
4579 return FAIL;
4580 }
4581
4582 if ((range & expr.X_add_number) != 0)
4583 {
4584 int regno = range & expr.X_add_number;
4585
4586 regno &= -regno;
4587 regno = (1 << regno) - 1;
4588 as_tsktsk
4589 (_("Warning: Duplicated register (r%d) in register list"),
4590 regno);
4591 }
4592
4593 range |= expr.X_add_number;
4594 }
4595 else
4596 {
4597 if (inst.reloc.type != 0)
4598 {
4599 inst.error = _("expression too complex");
4600 return FAIL;
4601 }
4602
4603 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
4604 inst.reloc.type = BFD_RELOC_ARM_MULTI;
4605 inst.reloc.pc_rel = 0;
4606 }
4607 }
4608
4609 skip_whitespace (str);
4610
4611 if (*str == '|' || *str == '+')
4612 {
4613 str++;
4614 another_range = 1;
4615 }
4616 }
4617 while (another_range);
4618
4619 *strp = str;
4620 return range;
4621 }
4622
4623 static void
4624 do_ldmstm (str, flags)
4625 char * str;
4626 unsigned long flags;
4627 {
4628 int base_reg;
4629 long range;
4630
4631 skip_whitespace (str);
4632
4633 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
4634 return;
4635
4636 if (base_reg == REG_PC)
4637 {
4638 inst.error = _("r15 not allowed as base register");
4639 return;
4640 }
4641
4642 skip_whitespace (str);
4643
4644 if (*str == '!')
4645 {
4646 flags |= WRITE_BACK;
4647 str++;
4648 }
4649
4650 if (skip_past_comma (&str) == FAIL
4651 || (range = reg_list (&str)) == FAIL)
4652 {
4653 if (! inst.error)
4654 inst.error = BAD_ARGS;
4655 return;
4656 }
4657
4658 if (*str == '^')
4659 {
4660 str++;
4661 flags |= LDM_TYPE_2_OR_3;
4662 }
4663
4664 inst.instruction |= flags | range;
4665 end_of_line (str);
4666 return;
4667 }
4668
4669 static void
4670 do_swi (str, flags)
4671 char * str;
4672 unsigned long flags;
4673 {
4674 skip_whitespace (str);
4675
4676 /* Allow optional leading '#'. */
4677 if (is_immediate_prefix (*str))
4678 str++;
4679
4680 if (my_get_expression (& inst.reloc.exp, & str))
4681 return;
4682
4683 inst.reloc.type = BFD_RELOC_ARM_SWI;
4684 inst.reloc.pc_rel = 0;
4685 inst.instruction |= flags;
4686
4687 end_of_line (str);
4688
4689 return;
4690 }
4691
4692 static void
4693 do_swap (str, flags)
4694 char * str;
4695 unsigned long flags;
4696 {
4697 int reg;
4698
4699 skip_whitespace (str);
4700
4701 if ((reg = reg_required_here (&str, 12)) == FAIL)
4702 return;
4703
4704 if (reg == REG_PC)
4705 {
4706 inst.error = _("r15 not allowed in swap");
4707 return;
4708 }
4709
4710 if (skip_past_comma (&str) == FAIL
4711 || (reg = reg_required_here (&str, 0)) == FAIL)
4712 {
4713 if (!inst.error)
4714 inst.error = BAD_ARGS;
4715 return;
4716 }
4717
4718 if (reg == REG_PC)
4719 {
4720 inst.error = _("r15 not allowed in swap");
4721 return;
4722 }
4723
4724 if (skip_past_comma (&str) == FAIL
4725 || *str++ != '[')
4726 {
4727 inst.error = BAD_ARGS;
4728 return;
4729 }
4730
4731 skip_whitespace (str);
4732
4733 if ((reg = reg_required_here (&str, 16)) == FAIL)
4734 return;
4735
4736 if (reg == REG_PC)
4737 {
4738 inst.error = BAD_PC;
4739 return;
4740 }
4741
4742 skip_whitespace (str);
4743
4744 if (*str++ != ']')
4745 {
4746 inst.error = _("missing ]");
4747 return;
4748 }
4749
4750 inst.instruction |= flags;
4751 end_of_line (str);
4752 return;
4753 }
4754
4755 static void
4756 do_branch (str, flags)
4757 char * str;
4758 unsigned long flags ATTRIBUTE_UNUSED;
4759 {
4760 if (my_get_expression (&inst.reloc.exp, &str))
4761 return;
4762
4763 #ifdef OBJ_ELF
4764 {
4765 char * save_in;
4766
4767 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
4768 required for the instruction. */
4769
4770 /* arm_parse_reloc () works on input_line_pointer.
4771 We actually want to parse the operands to the branch instruction
4772 passed in 'str'. Save the input pointer and restore it later. */
4773 save_in = input_line_pointer;
4774 input_line_pointer = str;
4775 if (inst.reloc.exp.X_op == O_symbol
4776 && *str == '('
4777 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
4778 {
4779 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4780 inst.reloc.pc_rel = 0;
4781 /* Modify str to point to after parsed operands, otherwise
4782 end_of_line() will complain about the (PLT) left in str. */
4783 str = input_line_pointer;
4784 }
4785 else
4786 {
4787 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4788 inst.reloc.pc_rel = 1;
4789 }
4790 input_line_pointer = save_in;
4791 }
4792 #else
4793 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4794 inst.reloc.pc_rel = 1;
4795 #endif /* OBJ_ELF */
4796
4797 end_of_line (str);
4798 return;
4799 }
4800
4801 static void
4802 do_bx (str, flags)
4803 char * str;
4804 unsigned long flags ATTRIBUTE_UNUSED;
4805 {
4806 int reg;
4807
4808 skip_whitespace (str);
4809
4810 if ((reg = reg_required_here (&str, 0)) == FAIL)
4811 {
4812 inst.error = BAD_ARGS;
4813 return;
4814 }
4815
4816 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
4817 if (reg == REG_PC)
4818 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
4819
4820 end_of_line (str);
4821 }
4822
4823 static void
4824 do_cdp (str, flags)
4825 char * str;
4826 unsigned long flags ATTRIBUTE_UNUSED;
4827 {
4828 /* Co-processor data operation.
4829 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
4830 skip_whitespace (str);
4831
4832 if (co_proc_number (&str) == FAIL)
4833 {
4834 if (!inst.error)
4835 inst.error = BAD_ARGS;
4836 return;
4837 }
4838
4839 if (skip_past_comma (&str) == FAIL
4840 || cp_opc_expr (&str, 20,4) == FAIL)
4841 {
4842 if (!inst.error)
4843 inst.error = BAD_ARGS;
4844 return;
4845 }
4846
4847 if (skip_past_comma (&str) == FAIL
4848 || cp_reg_required_here (&str, 12) == FAIL)
4849 {
4850 if (!inst.error)
4851 inst.error = BAD_ARGS;
4852 return;
4853 }
4854
4855 if (skip_past_comma (&str) == FAIL
4856 || cp_reg_required_here (&str, 16) == FAIL)
4857 {
4858 if (!inst.error)
4859 inst.error = BAD_ARGS;
4860 return;
4861 }
4862
4863 if (skip_past_comma (&str) == FAIL
4864 || cp_reg_required_here (&str, 0) == FAIL)
4865 {
4866 if (!inst.error)
4867 inst.error = BAD_ARGS;
4868 return;
4869 }
4870
4871 if (skip_past_comma (&str) == SUCCESS)
4872 {
4873 if (cp_opc_expr (&str, 5, 3) == FAIL)
4874 {
4875 if (!inst.error)
4876 inst.error = BAD_ARGS;
4877 return;
4878 }
4879 }
4880
4881 end_of_line (str);
4882 return;
4883 }
4884
4885 static void
4886 do_lstc (str, flags)
4887 char * str;
4888 unsigned long flags;
4889 {
4890 /* Co-processor register load/store.
4891 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
4892
4893 skip_whitespace (str);
4894
4895 if (co_proc_number (&str) == FAIL)
4896 {
4897 if (!inst.error)
4898 inst.error = BAD_ARGS;
4899 return;
4900 }
4901
4902 if (skip_past_comma (&str) == FAIL
4903 || cp_reg_required_here (&str, 12) == FAIL)
4904 {
4905 if (!inst.error)
4906 inst.error = BAD_ARGS;
4907 return;
4908 }
4909
4910 if (skip_past_comma (&str) == FAIL
4911 || cp_address_required_here (&str) == FAIL)
4912 {
4913 if (! inst.error)
4914 inst.error = BAD_ARGS;
4915 return;
4916 }
4917
4918 inst.instruction |= flags;
4919 end_of_line (str);
4920 return;
4921 }
4922
4923 static void
4924 do_co_reg (str, flags)
4925 char * str;
4926 unsigned long flags;
4927 {
4928 /* Co-processor register transfer.
4929 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
4930
4931 skip_whitespace (str);
4932
4933 if (co_proc_number (&str) == FAIL)
4934 {
4935 if (!inst.error)
4936 inst.error = BAD_ARGS;
4937 return;
4938 }
4939
4940 if (skip_past_comma (&str) == FAIL
4941 || cp_opc_expr (&str, 21, 3) == FAIL)
4942 {
4943 if (!inst.error)
4944 inst.error = BAD_ARGS;
4945 return;
4946 }
4947
4948 if (skip_past_comma (&str) == FAIL
4949 || reg_required_here (&str, 12) == FAIL)
4950 {
4951 if (!inst.error)
4952 inst.error = BAD_ARGS;
4953 return;
4954 }
4955
4956 if (skip_past_comma (&str) == FAIL
4957 || cp_reg_required_here (&str, 16) == FAIL)
4958 {
4959 if (!inst.error)
4960 inst.error = BAD_ARGS;
4961 return;
4962 }
4963
4964 if (skip_past_comma (&str) == FAIL
4965 || cp_reg_required_here (&str, 0) == FAIL)
4966 {
4967 if (!inst.error)
4968 inst.error = BAD_ARGS;
4969 return;
4970 }
4971
4972 if (skip_past_comma (&str) == SUCCESS)
4973 {
4974 if (cp_opc_expr (&str, 5, 3) == FAIL)
4975 {
4976 if (!inst.error)
4977 inst.error = BAD_ARGS;
4978 return;
4979 }
4980 }
4981 if (flags)
4982 {
4983 inst.error = BAD_COND;
4984 }
4985
4986 end_of_line (str);
4987 return;
4988 }
4989
4990 static void
4991 do_fp_ctrl (str, flags)
4992 char * str;
4993 unsigned long flags ATTRIBUTE_UNUSED;
4994 {
4995 /* FP control registers.
4996 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
4997
4998 skip_whitespace (str);
4999
5000 if (reg_required_here (&str, 12) == FAIL)
5001 {
5002 if (!inst.error)
5003 inst.error = BAD_ARGS;
5004 return;
5005 }
5006
5007 end_of_line (str);
5008 return;
5009 }
5010
5011 static void
5012 do_fp_ldst (str, flags)
5013 char * str;
5014 unsigned long flags ATTRIBUTE_UNUSED;
5015 {
5016 skip_whitespace (str);
5017
5018 switch (inst.suffix)
5019 {
5020 case SUFF_S:
5021 break;
5022 case SUFF_D:
5023 inst.instruction |= CP_T_X;
5024 break;
5025 case SUFF_E:
5026 inst.instruction |= CP_T_Y;
5027 break;
5028 case SUFF_P:
5029 inst.instruction |= CP_T_X | CP_T_Y;
5030 break;
5031 default:
5032 abort ();
5033 }
5034
5035 if (fp_reg_required_here (&str, 12) == FAIL)
5036 {
5037 if (!inst.error)
5038 inst.error = BAD_ARGS;
5039 return;
5040 }
5041
5042 if (skip_past_comma (&str) == FAIL
5043 || cp_address_required_here (&str) == FAIL)
5044 {
5045 if (!inst.error)
5046 inst.error = BAD_ARGS;
5047 return;
5048 }
5049
5050 end_of_line (str);
5051 }
5052
5053 static void
5054 do_fp_ldmstm (str, flags)
5055 char * str;
5056 unsigned long flags;
5057 {
5058 int num_regs;
5059
5060 skip_whitespace (str);
5061
5062 if (fp_reg_required_here (&str, 12) == FAIL)
5063 {
5064 if (! inst.error)
5065 inst.error = BAD_ARGS;
5066 return;
5067 }
5068
5069 /* Get Number of registers to transfer. */
5070 if (skip_past_comma (&str) == FAIL
5071 || my_get_expression (&inst.reloc.exp, &str))
5072 {
5073 if (! inst.error)
5074 inst.error = _("constant expression expected");
5075 return;
5076 }
5077
5078 if (inst.reloc.exp.X_op != O_constant)
5079 {
5080 inst.error = _("Constant value required for number of registers");
5081 return;
5082 }
5083
5084 num_regs = inst.reloc.exp.X_add_number;
5085
5086 if (num_regs < 1 || num_regs > 4)
5087 {
5088 inst.error = _("number of registers must be in the range [1:4]");
5089 return;
5090 }
5091
5092 switch (num_regs)
5093 {
5094 case 1:
5095 inst.instruction |= CP_T_X;
5096 break;
5097 case 2:
5098 inst.instruction |= CP_T_Y;
5099 break;
5100 case 3:
5101 inst.instruction |= CP_T_Y | CP_T_X;
5102 break;
5103 case 4:
5104 break;
5105 default:
5106 abort ();
5107 }
5108
5109 if (flags)
5110 {
5111 int reg;
5112 int write_back;
5113 int offset;
5114
5115 /* The instruction specified "ea" or "fd", so we can only accept
5116 [Rn]{!}. The instruction does not really support stacking or
5117 unstacking, so we have to emulate these by setting appropriate
5118 bits and offsets. */
5119 if (skip_past_comma (&str) == FAIL
5120 || *str != '[')
5121 {
5122 if (! inst.error)
5123 inst.error = BAD_ARGS;
5124 return;
5125 }
5126
5127 str++;
5128 skip_whitespace (str);
5129
5130 if ((reg = reg_required_here (&str, 16)) == FAIL)
5131 return;
5132
5133 skip_whitespace (str);
5134
5135 if (*str != ']')
5136 {
5137 inst.error = BAD_ARGS;
5138 return;
5139 }
5140
5141 str++;
5142 if (*str == '!')
5143 {
5144 write_back = 1;
5145 str++;
5146 if (reg == REG_PC)
5147 {
5148 inst.error =
5149 _("R15 not allowed as base register with write-back");
5150 return;
5151 }
5152 }
5153 else
5154 write_back = 0;
5155
5156 if (flags & CP_T_Pre)
5157 {
5158 /* Pre-decrement. */
5159 offset = 3 * num_regs;
5160 if (write_back)
5161 flags |= CP_T_WB;
5162 }
5163 else
5164 {
5165 /* Post-increment. */
5166 if (write_back)
5167 {
5168 flags |= CP_T_WB;
5169 offset = 3 * num_regs;
5170 }
5171 else
5172 {
5173 /* No write-back, so convert this into a standard pre-increment
5174 instruction -- aesthetically more pleasing. */
5175 flags = CP_T_Pre | CP_T_UD;
5176 offset = 0;
5177 }
5178 }
5179
5180 inst.instruction |= flags | offset;
5181 }
5182 else if (skip_past_comma (&str) == FAIL
5183 || cp_address_required_here (&str) == FAIL)
5184 {
5185 if (! inst.error)
5186 inst.error = BAD_ARGS;
5187 return;
5188 }
5189
5190 end_of_line (str);
5191 }
5192
5193 static void
5194 do_fp_dyadic (str, flags)
5195 char * str;
5196 unsigned long flags;
5197 {
5198 skip_whitespace (str);
5199
5200 switch (inst.suffix)
5201 {
5202 case SUFF_S:
5203 break;
5204 case SUFF_D:
5205 inst.instruction |= 0x00000080;
5206 break;
5207 case SUFF_E:
5208 inst.instruction |= 0x00080000;
5209 break;
5210 default:
5211 abort ();
5212 }
5213
5214 if (fp_reg_required_here (&str, 12) == FAIL)
5215 {
5216 if (! inst.error)
5217 inst.error = BAD_ARGS;
5218 return;
5219 }
5220
5221 if (skip_past_comma (&str) == FAIL
5222 || fp_reg_required_here (&str, 16) == FAIL)
5223 {
5224 if (! inst.error)
5225 inst.error = BAD_ARGS;
5226 return;
5227 }
5228
5229 if (skip_past_comma (&str) == FAIL
5230 || fp_op2 (&str) == FAIL)
5231 {
5232 if (! inst.error)
5233 inst.error = BAD_ARGS;
5234 return;
5235 }
5236
5237 inst.instruction |= flags;
5238 end_of_line (str);
5239 return;
5240 }
5241
5242 static void
5243 do_fp_monadic (str, flags)
5244 char * str;
5245 unsigned long flags;
5246 {
5247 skip_whitespace (str);
5248
5249 switch (inst.suffix)
5250 {
5251 case SUFF_S:
5252 break;
5253 case SUFF_D:
5254 inst.instruction |= 0x00000080;
5255 break;
5256 case SUFF_E:
5257 inst.instruction |= 0x00080000;
5258 break;
5259 default:
5260 abort ();
5261 }
5262
5263 if (fp_reg_required_here (&str, 12) == FAIL)
5264 {
5265 if (! inst.error)
5266 inst.error = BAD_ARGS;
5267 return;
5268 }
5269
5270 if (skip_past_comma (&str) == FAIL
5271 || fp_op2 (&str) == FAIL)
5272 {
5273 if (! inst.error)
5274 inst.error = BAD_ARGS;
5275 return;
5276 }
5277
5278 inst.instruction |= flags;
5279 end_of_line (str);
5280 return;
5281 }
5282
5283 static void
5284 do_fp_cmp (str, flags)
5285 char * str;
5286 unsigned long flags;
5287 {
5288 skip_whitespace (str);
5289
5290 if (fp_reg_required_here (&str, 16) == FAIL)
5291 {
5292 if (! inst.error)
5293 inst.error = BAD_ARGS;
5294 return;
5295 }
5296
5297 if (skip_past_comma (&str) == FAIL
5298 || fp_op2 (&str) == FAIL)
5299 {
5300 if (! inst.error)
5301 inst.error = BAD_ARGS;
5302 return;
5303 }
5304
5305 inst.instruction |= flags;
5306 end_of_line (str);
5307 return;
5308 }
5309
5310 static void
5311 do_fp_from_reg (str, flags)
5312 char * str;
5313 unsigned long flags;
5314 {
5315 skip_whitespace (str);
5316
5317 switch (inst.suffix)
5318 {
5319 case SUFF_S:
5320 break;
5321 case SUFF_D:
5322 inst.instruction |= 0x00000080;
5323 break;
5324 case SUFF_E:
5325 inst.instruction |= 0x00080000;
5326 break;
5327 default:
5328 abort ();
5329 }
5330
5331 if (fp_reg_required_here (&str, 16) == FAIL)
5332 {
5333 if (! inst.error)
5334 inst.error = BAD_ARGS;
5335 return;
5336 }
5337
5338 if (skip_past_comma (&str) == FAIL
5339 || reg_required_here (&str, 12) == FAIL)
5340 {
5341 if (! inst.error)
5342 inst.error = BAD_ARGS;
5343 return;
5344 }
5345
5346 inst.instruction |= flags;
5347 end_of_line (str);
5348 return;
5349 }
5350
5351 static void
5352 do_fp_to_reg (str, flags)
5353 char * str;
5354 unsigned long flags;
5355 {
5356 skip_whitespace (str);
5357
5358 if (reg_required_here (&str, 12) == FAIL)
5359 return;
5360
5361 if (skip_past_comma (&str) == FAIL
5362 || fp_reg_required_here (&str, 0) == FAIL)
5363 {
5364 if (! inst.error)
5365 inst.error = BAD_ARGS;
5366 return;
5367 }
5368
5369 inst.instruction |= flags;
5370 end_of_line (str);
5371 return;
5372 }
5373
5374 /* Thumb specific routines. */
5375
5376 /* Parse and validate that a register is of the right form, this saves
5377 repeated checking of this information in many similar cases.
5378 Unlike the 32-bit case we do not insert the register into the opcode
5379 here, since the position is often unknown until the full instruction
5380 has been parsed. */
5381
5382 static int
5383 thumb_reg (strp, hi_lo)
5384 char ** strp;
5385 int hi_lo;
5386 {
5387 int reg;
5388
5389 if ((reg = reg_required_here (strp, -1)) == FAIL)
5390 return FAIL;
5391
5392 switch (hi_lo)
5393 {
5394 case THUMB_REG_LO:
5395 if (reg > 7)
5396 {
5397 inst.error = _("lo register required");
5398 return FAIL;
5399 }
5400 break;
5401
5402 case THUMB_REG_HI:
5403 if (reg < 8)
5404 {
5405 inst.error = _("hi register required");
5406 return FAIL;
5407 }
5408 break;
5409
5410 default:
5411 break;
5412 }
5413
5414 return reg;
5415 }
5416
5417 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
5418 was SUB. */
5419
5420 static void
5421 thumb_add_sub (str, subtract)
5422 char * str;
5423 int subtract;
5424 {
5425 int Rd, Rs, Rn = FAIL;
5426
5427 skip_whitespace (str);
5428
5429 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5430 || skip_past_comma (&str) == FAIL)
5431 {
5432 if (! inst.error)
5433 inst.error = BAD_ARGS;
5434 return;
5435 }
5436
5437 if (is_immediate_prefix (*str))
5438 {
5439 Rs = Rd;
5440 str++;
5441 if (my_get_expression (&inst.reloc.exp, &str))
5442 return;
5443 }
5444 else
5445 {
5446 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5447 return;
5448
5449 if (skip_past_comma (&str) == FAIL)
5450 {
5451 /* Two operand format, shuffle the registers
5452 and pretend there are 3. */
5453 Rn = Rs;
5454 Rs = Rd;
5455 }
5456 else if (is_immediate_prefix (*str))
5457 {
5458 str++;
5459 if (my_get_expression (&inst.reloc.exp, &str))
5460 return;
5461 }
5462 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5463 return;
5464 }
5465
5466 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5467 for the latter case, EXPR contains the immediate that was found. */
5468 if (Rn != FAIL)
5469 {
5470 /* All register format. */
5471 if (Rd > 7 || Rs > 7 || Rn > 7)
5472 {
5473 if (Rs != Rd)
5474 {
5475 inst.error = _("dest and source1 must be the same register");
5476 return;
5477 }
5478
5479 /* Can't do this for SUB. */
5480 if (subtract)
5481 {
5482 inst.error = _("subtract valid only on lo regs");
5483 return;
5484 }
5485
5486 inst.instruction = (T_OPCODE_ADD_HI
5487 | (Rd > 7 ? THUMB_H1 : 0)
5488 | (Rn > 7 ? THUMB_H2 : 0));
5489 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
5490 }
5491 else
5492 {
5493 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
5494 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5495 }
5496 }
5497 else
5498 {
5499 /* Immediate expression, now things start to get nasty. */
5500
5501 /* First deal with HI regs, only very restricted cases allowed:
5502 Adjusting SP, and using PC or SP to get an address. */
5503 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5504 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
5505 {
5506 inst.error = _("invalid Hi register with immediate");
5507 return;
5508 }
5509
5510 if (inst.reloc.exp.X_op != O_constant)
5511 {
5512 /* Value isn't known yet, all we can do is store all the fragments
5513 we know about in the instruction and let the reloc hacking
5514 work it all out. */
5515 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
5516 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5517 }
5518 else
5519 {
5520 int offset = inst.reloc.exp.X_add_number;
5521
5522 if (subtract)
5523 offset = -offset;
5524
5525 if (offset < 0)
5526 {
5527 offset = -offset;
5528 subtract = 1;
5529
5530 /* Quick check, in case offset is MIN_INT. */
5531 if (offset < 0)
5532 {
5533 inst.error = _("immediate value out of range");
5534 return;
5535 }
5536 }
5537 else
5538 subtract = 0;
5539
5540 if (Rd == REG_SP)
5541 {
5542 if (offset & ~0x1fc)
5543 {
5544 inst.error = _("invalid immediate value for stack adjust");
5545 return;
5546 }
5547 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5548 inst.instruction |= offset >> 2;
5549 }
5550 else if (Rs == REG_PC || Rs == REG_SP)
5551 {
5552 if (subtract
5553 || (offset & ~0x3fc))
5554 {
5555 inst.error = _("invalid immediate for address calculation");
5556 return;
5557 }
5558 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
5559 : T_OPCODE_ADD_SP);
5560 inst.instruction |= (Rd << 8) | (offset >> 2);
5561 }
5562 else if (Rs == Rd)
5563 {
5564 if (offset & ~0xff)
5565 {
5566 inst.error = _("immediate value out of range");
5567 return;
5568 }
5569 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5570 inst.instruction |= (Rd << 8) | offset;
5571 }
5572 else
5573 {
5574 if (offset & ~0x7)
5575 {
5576 inst.error = _("immediate value out of range");
5577 return;
5578 }
5579 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5580 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
5581 }
5582 }
5583 }
5584
5585 end_of_line (str);
5586 }
5587
5588 static void
5589 thumb_shift (str, shift)
5590 char * str;
5591 int shift;
5592 {
5593 int Rd, Rs, Rn = FAIL;
5594
5595 skip_whitespace (str);
5596
5597 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5598 || skip_past_comma (&str) == FAIL)
5599 {
5600 if (! inst.error)
5601 inst.error = BAD_ARGS;
5602 return;
5603 }
5604
5605 if (is_immediate_prefix (*str))
5606 {
5607 /* Two operand immediate format, set Rs to Rd. */
5608 Rs = Rd;
5609 str ++;
5610 if (my_get_expression (&inst.reloc.exp, &str))
5611 return;
5612 }
5613 else
5614 {
5615 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5616 return;
5617
5618 if (skip_past_comma (&str) == FAIL)
5619 {
5620 /* Two operand format, shuffle the registers
5621 and pretend there are 3. */
5622 Rn = Rs;
5623 Rs = Rd;
5624 }
5625 else if (is_immediate_prefix (*str))
5626 {
5627 str++;
5628 if (my_get_expression (&inst.reloc.exp, &str))
5629 return;
5630 }
5631 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5632 return;
5633 }
5634
5635 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5636 for the latter case, EXPR contains the immediate that was found. */
5637
5638 if (Rn != FAIL)
5639 {
5640 if (Rs != Rd)
5641 {
5642 inst.error = _("source1 and dest must be same register");
5643 return;
5644 }
5645
5646 switch (shift)
5647 {
5648 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
5649 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
5650 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
5651 }
5652
5653 inst.instruction |= Rd | (Rn << 3);
5654 }
5655 else
5656 {
5657 switch (shift)
5658 {
5659 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
5660 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
5661 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
5662 }
5663
5664 if (inst.reloc.exp.X_op != O_constant)
5665 {
5666 /* Value isn't known yet, create a dummy reloc and let reloc
5667 hacking fix it up. */
5668 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
5669 }
5670 else
5671 {
5672 unsigned shift_value = inst.reloc.exp.X_add_number;
5673
5674 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
5675 {
5676 inst.error = _("Invalid immediate for shift");
5677 return;
5678 }
5679
5680 /* Shifts of zero are handled by converting to LSL. */
5681 if (shift_value == 0)
5682 inst.instruction = T_OPCODE_LSL_I;
5683
5684 /* Shifts of 32 are encoded as a shift of zero. */
5685 if (shift_value == 32)
5686 shift_value = 0;
5687
5688 inst.instruction |= shift_value << 6;
5689 }
5690
5691 inst.instruction |= Rd | (Rs << 3);
5692 }
5693
5694 end_of_line (str);
5695 }
5696
5697 static void
5698 thumb_mov_compare (str, move)
5699 char * str;
5700 int move;
5701 {
5702 int Rd, Rs = FAIL;
5703
5704 skip_whitespace (str);
5705
5706 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5707 || skip_past_comma (&str) == FAIL)
5708 {
5709 if (! inst.error)
5710 inst.error = BAD_ARGS;
5711 return;
5712 }
5713
5714 if (is_immediate_prefix (*str))
5715 {
5716 str++;
5717 if (my_get_expression (&inst.reloc.exp, &str))
5718 return;
5719 }
5720 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5721 return;
5722
5723 if (Rs != FAIL)
5724 {
5725 if (Rs < 8 && Rd < 8)
5726 {
5727 if (move == THUMB_MOVE)
5728 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
5729 since a MOV instruction produces unpredictable results. */
5730 inst.instruction = T_OPCODE_ADD_I3;
5731 else
5732 inst.instruction = T_OPCODE_CMP_LR;
5733 inst.instruction |= Rd | (Rs << 3);
5734 }
5735 else
5736 {
5737 if (move == THUMB_MOVE)
5738 inst.instruction = T_OPCODE_MOV_HR;
5739 else
5740 inst.instruction = T_OPCODE_CMP_HR;
5741
5742 if (Rd > 7)
5743 inst.instruction |= THUMB_H1;
5744
5745 if (Rs > 7)
5746 inst.instruction |= THUMB_H2;
5747
5748 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
5749 }
5750 }
5751 else
5752 {
5753 if (Rd > 7)
5754 {
5755 inst.error = _("only lo regs allowed with immediate");
5756 return;
5757 }
5758
5759 if (move == THUMB_MOVE)
5760 inst.instruction = T_OPCODE_MOV_I8;
5761 else
5762 inst.instruction = T_OPCODE_CMP_I8;
5763
5764 inst.instruction |= Rd << 8;
5765
5766 if (inst.reloc.exp.X_op != O_constant)
5767 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
5768 else
5769 {
5770 unsigned value = inst.reloc.exp.X_add_number;
5771
5772 if (value > 255)
5773 {
5774 inst.error = _("invalid immediate");
5775 return;
5776 }
5777
5778 inst.instruction |= value;
5779 }
5780 }
5781
5782 end_of_line (str);
5783 }
5784
5785 static void
5786 thumb_load_store (str, load_store, size)
5787 char * str;
5788 int load_store;
5789 int size;
5790 {
5791 int Rd, Rb, Ro = FAIL;
5792
5793 skip_whitespace (str);
5794
5795 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5796 || skip_past_comma (&str) == FAIL)
5797 {
5798 if (! inst.error)
5799 inst.error = BAD_ARGS;
5800 return;
5801 }
5802
5803 if (*str == '[')
5804 {
5805 str++;
5806 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5807 return;
5808
5809 if (skip_past_comma (&str) != FAIL)
5810 {
5811 if (is_immediate_prefix (*str))
5812 {
5813 str++;
5814 if (my_get_expression (&inst.reloc.exp, &str))
5815 return;
5816 }
5817 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5818 return;
5819 }
5820 else
5821 {
5822 inst.reloc.exp.X_op = O_constant;
5823 inst.reloc.exp.X_add_number = 0;
5824 }
5825
5826 if (*str != ']')
5827 {
5828 inst.error = _("expected ']'");
5829 return;
5830 }
5831 str++;
5832 }
5833 else if (*str == '=')
5834 {
5835 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
5836 str++;
5837
5838 skip_whitespace (str);
5839
5840 if (my_get_expression (& inst.reloc.exp, & str))
5841 return;
5842
5843 end_of_line (str);
5844
5845 if ( inst.reloc.exp.X_op != O_constant
5846 && inst.reloc.exp.X_op != O_symbol)
5847 {
5848 inst.error = "Constant expression expected";
5849 return;
5850 }
5851
5852 if (inst.reloc.exp.X_op == O_constant
5853 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
5854 {
5855 /* This can be done with a mov instruction. */
5856
5857 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
5858 inst.instruction |= inst.reloc.exp.X_add_number;
5859 return;
5860 }
5861
5862 /* Insert into literal pool. */
5863 if (add_to_lit_pool () == FAIL)
5864 {
5865 if (!inst.error)
5866 inst.error = "literal pool insertion failed";
5867 return;
5868 }
5869
5870 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5871 inst.reloc.pc_rel = 1;
5872 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5873 /* Adjust ARM pipeline offset to Thumb. */
5874 inst.reloc.exp.X_add_number += 4;
5875
5876 return;
5877 }
5878 else
5879 {
5880 if (my_get_expression (&inst.reloc.exp, &str))
5881 return;
5882
5883 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5884 inst.reloc.pc_rel = 1;
5885 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
5886 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5887 end_of_line (str);
5888 return;
5889 }
5890
5891 if (Rb == REG_PC || Rb == REG_SP)
5892 {
5893 if (size != THUMB_WORD)
5894 {
5895 inst.error = _("byte or halfword not valid for base register");
5896 return;
5897 }
5898 else if (Rb == REG_PC && load_store != THUMB_LOAD)
5899 {
5900 inst.error = _("R15 based store not allowed");
5901 return;
5902 }
5903 else if (Ro != FAIL)
5904 {
5905 inst.error = _("Invalid base register for register offset");
5906 return;
5907 }
5908
5909 if (Rb == REG_PC)
5910 inst.instruction = T_OPCODE_LDR_PC;
5911 else if (load_store == THUMB_LOAD)
5912 inst.instruction = T_OPCODE_LDR_SP;
5913 else
5914 inst.instruction = T_OPCODE_STR_SP;
5915
5916 inst.instruction |= Rd << 8;
5917 if (inst.reloc.exp.X_op == O_constant)
5918 {
5919 unsigned offset = inst.reloc.exp.X_add_number;
5920
5921 if (offset & ~0x3fc)
5922 {
5923 inst.error = _("invalid offset");
5924 return;
5925 }
5926
5927 inst.instruction |= offset >> 2;
5928 }
5929 else
5930 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5931 }
5932 else if (Rb > 7)
5933 {
5934 inst.error = _("invalid base register in load/store");
5935 return;
5936 }
5937 else if (Ro == FAIL)
5938 {
5939 /* Immediate offset. */
5940 if (size == THUMB_WORD)
5941 inst.instruction = (load_store == THUMB_LOAD
5942 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
5943 else if (size == THUMB_HALFWORD)
5944 inst.instruction = (load_store == THUMB_LOAD
5945 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
5946 else
5947 inst.instruction = (load_store == THUMB_LOAD
5948 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
5949
5950 inst.instruction |= Rd | (Rb << 3);
5951
5952 if (inst.reloc.exp.X_op == O_constant)
5953 {
5954 unsigned offset = inst.reloc.exp.X_add_number;
5955
5956 if (offset & ~(0x1f << size))
5957 {
5958 inst.error = _("Invalid offset");
5959 return;
5960 }
5961 inst.instruction |= (offset >> size) << 6;
5962 }
5963 else
5964 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5965 }
5966 else
5967 {
5968 /* Register offset. */
5969 if (size == THUMB_WORD)
5970 inst.instruction = (load_store == THUMB_LOAD
5971 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
5972 else if (size == THUMB_HALFWORD)
5973 inst.instruction = (load_store == THUMB_LOAD
5974 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
5975 else
5976 inst.instruction = (load_store == THUMB_LOAD
5977 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
5978
5979 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5980 }
5981
5982 end_of_line (str);
5983 }
5984
5985 static void
5986 do_t_nop (str)
5987 char * str;
5988 {
5989 /* Do nothing. */
5990 end_of_line (str);
5991 return;
5992 }
5993
5994 /* Handle the Format 4 instructions that do not have equivalents in other
5995 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
5996 BIC and MVN. */
5997
5998 static void
5999 do_t_arit (str)
6000 char * str;
6001 {
6002 int Rd, Rs, Rn;
6003
6004 skip_whitespace (str);
6005
6006 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6007 || skip_past_comma (&str) == FAIL
6008 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6009 {
6010 inst.error = BAD_ARGS;
6011 return;
6012 }
6013
6014 if (skip_past_comma (&str) != FAIL)
6015 {
6016 /* Three operand format not allowed for TST, CMN, NEG and MVN.
6017 (It isn't allowed for CMP either, but that isn't handled by this
6018 function.) */
6019 if (inst.instruction == T_OPCODE_TST
6020 || inst.instruction == T_OPCODE_CMN
6021 || inst.instruction == T_OPCODE_NEG
6022 || inst.instruction == T_OPCODE_MVN)
6023 {
6024 inst.error = BAD_ARGS;
6025 return;
6026 }
6027
6028 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6029 return;
6030
6031 if (Rs != Rd)
6032 {
6033 inst.error = _("dest and source1 must be the same register");
6034 return;
6035 }
6036 Rs = Rn;
6037 }
6038
6039 if (inst.instruction == T_OPCODE_MUL
6040 && Rs == Rd)
6041 as_tsktsk (_("Rs and Rd must be different in MUL"));
6042
6043 inst.instruction |= Rd | (Rs << 3);
6044 end_of_line (str);
6045 }
6046
6047 static void
6048 do_t_add (str)
6049 char * str;
6050 {
6051 thumb_add_sub (str, 0);
6052 }
6053
6054 static void
6055 do_t_asr (str)
6056 char * str;
6057 {
6058 thumb_shift (str, THUMB_ASR);
6059 }
6060
6061 static void
6062 do_t_branch9 (str)
6063 char * str;
6064 {
6065 if (my_get_expression (&inst.reloc.exp, &str))
6066 return;
6067 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6068 inst.reloc.pc_rel = 1;
6069 end_of_line (str);
6070 }
6071
6072 static void
6073 do_t_branch12 (str)
6074 char * str;
6075 {
6076 if (my_get_expression (&inst.reloc.exp, &str))
6077 return;
6078 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6079 inst.reloc.pc_rel = 1;
6080 end_of_line (str);
6081 }
6082
6083 /* Find the real, Thumb encoded start of a Thumb function. */
6084
6085 static symbolS *
6086 find_real_start (symbolP)
6087 symbolS * symbolP;
6088 {
6089 char * real_start;
6090 const char * name = S_GET_NAME (symbolP);
6091 symbolS * new_target;
6092
6093 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
6094 #define STUB_NAME ".real_start_of"
6095
6096 if (name == NULL)
6097 abort ();
6098
6099 /* Names that start with '.' are local labels, not function entry points.
6100 The compiler may generate BL instructions to these labels because it
6101 needs to perform a branch to a far away location. */
6102 if (name[0] == '.')
6103 return symbolP;
6104
6105 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
6106 sprintf (real_start, "%s%s", STUB_NAME, name);
6107
6108 new_target = symbol_find (real_start);
6109
6110 if (new_target == NULL)
6111 {
6112 as_warn ("Failed to find real start of function: %s\n", name);
6113 new_target = symbolP;
6114 }
6115
6116 free (real_start);
6117
6118 return new_target;
6119 }
6120
6121 static void
6122 do_t_branch23 (str)
6123 char * str;
6124 {
6125 if (my_get_expression (& inst.reloc.exp, & str))
6126 return;
6127
6128 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6129 inst.reloc.pc_rel = 1;
6130 end_of_line (str);
6131
6132 /* If the destination of the branch is a defined symbol which does not have
6133 the THUMB_FUNC attribute, then we must be calling a function which has
6134 the (interfacearm) attribute. We look for the Thumb entry point to that
6135 function and change the branch to refer to that function instead. */
6136 if ( inst.reloc.exp.X_op == O_symbol
6137 && inst.reloc.exp.X_add_symbol != NULL
6138 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6139 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6140 inst.reloc.exp.X_add_symbol =
6141 find_real_start (inst.reloc.exp.X_add_symbol);
6142 }
6143
6144 static void
6145 do_t_bx (str)
6146 char * str;
6147 {
6148 int reg;
6149
6150 skip_whitespace (str);
6151
6152 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
6153 return;
6154
6155 /* This sets THUMB_H2 from the top bit of reg. */
6156 inst.instruction |= reg << 3;
6157
6158 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6159 should cause the alignment to be checked once it is known. This is
6160 because BX PC only works if the instruction is word aligned. */
6161
6162 end_of_line (str);
6163 }
6164
6165 static void
6166 do_t_compare (str)
6167 char * str;
6168 {
6169 thumb_mov_compare (str, THUMB_COMPARE);
6170 }
6171
6172 static void
6173 do_t_ldmstm (str)
6174 char * str;
6175 {
6176 int Rb;
6177 long range;
6178
6179 skip_whitespace (str);
6180
6181 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6182 return;
6183
6184 if (*str != '!')
6185 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
6186 else
6187 str++;
6188
6189 if (skip_past_comma (&str) == FAIL
6190 || (range = reg_list (&str)) == FAIL)
6191 {
6192 if (! inst.error)
6193 inst.error = BAD_ARGS;
6194 return;
6195 }
6196
6197 if (inst.reloc.type != BFD_RELOC_NONE)
6198 {
6199 /* This really doesn't seem worth it. */
6200 inst.reloc.type = BFD_RELOC_NONE;
6201 inst.error = _("Expression too complex");
6202 return;
6203 }
6204
6205 if (range & ~0xff)
6206 {
6207 inst.error = _("only lo-regs valid in load/store multiple");
6208 return;
6209 }
6210
6211 inst.instruction |= (Rb << 8) | range;
6212 end_of_line (str);
6213 }
6214
6215 static void
6216 do_t_ldr (str)
6217 char * str;
6218 {
6219 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
6220 }
6221
6222 static void
6223 do_t_ldrb (str)
6224 char * str;
6225 {
6226 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
6227 }
6228
6229 static void
6230 do_t_ldrh (str)
6231 char * str;
6232 {
6233 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
6234 }
6235
6236 static void
6237 do_t_lds (str)
6238 char * str;
6239 {
6240 int Rd, Rb, Ro;
6241
6242 skip_whitespace (str);
6243
6244 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6245 || skip_past_comma (&str) == FAIL
6246 || *str++ != '['
6247 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6248 || skip_past_comma (&str) == FAIL
6249 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6250 || *str++ != ']')
6251 {
6252 if (! inst.error)
6253 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
6254 return;
6255 }
6256
6257 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
6258 end_of_line (str);
6259 }
6260
6261 static void
6262 do_t_lsl (str)
6263 char * str;
6264 {
6265 thumb_shift (str, THUMB_LSL);
6266 }
6267
6268 static void
6269 do_t_lsr (str)
6270 char * str;
6271 {
6272 thumb_shift (str, THUMB_LSR);
6273 }
6274
6275 static void
6276 do_t_mov (str)
6277 char * str;
6278 {
6279 thumb_mov_compare (str, THUMB_MOVE);
6280 }
6281
6282 static void
6283 do_t_push_pop (str)
6284 char * str;
6285 {
6286 long range;
6287
6288 skip_whitespace (str);
6289
6290 if ((range = reg_list (&str)) == FAIL)
6291 {
6292 if (! inst.error)
6293 inst.error = BAD_ARGS;
6294 return;
6295 }
6296
6297 if (inst.reloc.type != BFD_RELOC_NONE)
6298 {
6299 /* This really doesn't seem worth it. */
6300 inst.reloc.type = BFD_RELOC_NONE;
6301 inst.error = _("Expression too complex");
6302 return;
6303 }
6304
6305 if (range & ~0xff)
6306 {
6307 if ((inst.instruction == T_OPCODE_PUSH
6308 && (range & ~0xff) == 1 << REG_LR)
6309 || (inst.instruction == T_OPCODE_POP
6310 && (range & ~0xff) == 1 << REG_PC))
6311 {
6312 inst.instruction |= THUMB_PP_PC_LR;
6313 range &= 0xff;
6314 }
6315 else
6316 {
6317 inst.error = _("invalid register list to push/pop instruction");
6318 return;
6319 }
6320 }
6321
6322 inst.instruction |= range;
6323 end_of_line (str);
6324 }
6325
6326 static void
6327 do_t_str (str)
6328 char * str;
6329 {
6330 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
6331 }
6332
6333 static void
6334 do_t_strb (str)
6335 char * str;
6336 {
6337 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
6338 }
6339
6340 static void
6341 do_t_strh (str)
6342 char * str;
6343 {
6344 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
6345 }
6346
6347 static void
6348 do_t_sub (str)
6349 char * str;
6350 {
6351 thumb_add_sub (str, 1);
6352 }
6353
6354 static void
6355 do_t_swi (str)
6356 char * str;
6357 {
6358 skip_whitespace (str);
6359
6360 if (my_get_expression (&inst.reloc.exp, &str))
6361 return;
6362
6363 inst.reloc.type = BFD_RELOC_ARM_SWI;
6364 end_of_line (str);
6365 return;
6366 }
6367
6368 static void
6369 do_t_adr (str)
6370 char * str;
6371 {
6372 int reg;
6373
6374 /* This is a pseudo-op of the form "adr rd, label" to be converted
6375 into a relative address of the form "add rd, pc, #label-.-4". */
6376 skip_whitespace (str);
6377
6378 /* Store Rd in temporary location inside instruction. */
6379 if ((reg = reg_required_here (&str, 4)) == FAIL
6380 || (reg > 7) /* For Thumb reg must be r0..r7. */
6381 || skip_past_comma (&str) == FAIL
6382 || my_get_expression (&inst.reloc.exp, &str))
6383 {
6384 if (!inst.error)
6385 inst.error = BAD_ARGS;
6386 return;
6387 }
6388
6389 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6390 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6391 inst.reloc.pc_rel = 1;
6392 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
6393
6394 end_of_line (str);
6395 }
6396
6397 static void
6398 insert_reg (entry)
6399 int entry;
6400 {
6401 int len = strlen (reg_table[entry].name) + 2;
6402 char * buf = (char *) xmalloc (len);
6403 char * buf2 = (char *) xmalloc (len);
6404 int i = 0;
6405
6406 #ifdef REGISTER_PREFIX
6407 buf[i++] = REGISTER_PREFIX;
6408 #endif
6409
6410 strcpy (buf + i, reg_table[entry].name);
6411
6412 for (i = 0; buf[i]; i++)
6413 buf2[i] = TOUPPER (buf[i]);
6414
6415 buf2[i] = '\0';
6416
6417 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
6418 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
6419 }
6420
6421 static void
6422 insert_reg_alias (str, regnum)
6423 char *str;
6424 int regnum;
6425 {
6426 struct reg_entry *new =
6427 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
6428 char *name = xmalloc (strlen (str) + 1);
6429 strcpy (name, str);
6430
6431 new->name = name;
6432 new->number = regnum;
6433
6434 hash_insert (arm_reg_hsh, name, (PTR) new);
6435 }
6436
6437 static void
6438 set_constant_flonums ()
6439 {
6440 int i;
6441
6442 for (i = 0; i < NUM_FLOAT_VALS; i++)
6443 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
6444 abort ();
6445 }
6446
6447 void
6448 md_begin ()
6449 {
6450 unsigned mach;
6451 unsigned int i;
6452
6453 if ( (arm_ops_hsh = hash_new ()) == NULL
6454 || (arm_tops_hsh = hash_new ()) == NULL
6455 || (arm_cond_hsh = hash_new ()) == NULL
6456 || (arm_shift_hsh = hash_new ()) == NULL
6457 || (arm_reg_hsh = hash_new ()) == NULL
6458 || (arm_psr_hsh = hash_new ()) == NULL)
6459 as_fatal (_("Virtual memory exhausted"));
6460
6461 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
6462 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
6463 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
6464 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
6465 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
6466 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
6467 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
6468 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
6469 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
6470 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
6471
6472 for (i = 0; reg_table[i].name; i++)
6473 insert_reg (i);
6474
6475 set_constant_flonums ();
6476
6477 #if defined OBJ_COFF || defined OBJ_ELF
6478 {
6479 unsigned int flags = 0;
6480
6481 /* Set the flags in the private structure. */
6482 if (uses_apcs_26) flags |= F_APCS26;
6483 if (support_interwork) flags |= F_INTERWORK;
6484 if (uses_apcs_float) flags |= F_APCS_FLOAT;
6485 if (pic_code) flags |= F_PIC;
6486 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
6487
6488 bfd_set_private_flags (stdoutput, flags);
6489
6490 /* We have run out flags in the COFF header to encode the
6491 status of ATPCS support, so instead we create a dummy,
6492 empty, debug section called .arm.atpcs. */
6493 if (atpcs)
6494 {
6495 asection * sec;
6496
6497 sec = bfd_make_section (stdoutput, ".arm.atpcs");
6498
6499 if (sec != NULL)
6500 {
6501 bfd_set_section_flags
6502 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
6503 bfd_set_section_size (stdoutput, sec, 0);
6504 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
6505 }
6506 }
6507 }
6508 #endif
6509
6510 /* Record the CPU type as well. */
6511 switch (cpu_variant & ARM_CPU_MASK)
6512 {
6513 case ARM_2:
6514 mach = bfd_mach_arm_2;
6515 break;
6516
6517 case ARM_3: /* Also ARM_250. */
6518 mach = bfd_mach_arm_2a;
6519 break;
6520
6521 default:
6522 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
6523 mach = bfd_mach_arm_4;
6524 break;
6525
6526 case ARM_7: /* Also ARM_6. */
6527 mach = bfd_mach_arm_3;
6528 break;
6529 }
6530
6531 /* Catch special cases. */
6532 if (cpu_variant & ARM_EXT_XSCALE)
6533 mach = bfd_mach_arm_XScale;
6534 else if (cpu_variant & ARM_EXT_V5E)
6535 mach = bfd_mach_arm_5TE;
6536 else if (cpu_variant & ARM_EXT_V5)
6537 {
6538 if (cpu_variant & ARM_EXT_THUMB)
6539 mach = bfd_mach_arm_5T;
6540 else
6541 mach = bfd_mach_arm_5;
6542 }
6543 else if (cpu_variant & ARM_EXT_HALFWORD)
6544 {
6545 if (cpu_variant & ARM_EXT_THUMB)
6546 mach = bfd_mach_arm_4T;
6547 else
6548 mach = bfd_mach_arm_4;
6549 }
6550 else if (cpu_variant & ARM_EXT_LONGMUL)
6551 mach = bfd_mach_arm_3M;
6552
6553 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
6554 }
6555
6556 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6557 for use in the a.out file, and stores them in the array pointed to by buf.
6558 This knows about the endian-ness of the target machine and does
6559 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6560 2 (short) and 4 (long) Floating numbers are put out as a series of
6561 LITTLENUMS (shorts, here at least). */
6562
6563 void
6564 md_number_to_chars (buf, val, n)
6565 char * buf;
6566 valueT val;
6567 int n;
6568 {
6569 if (target_big_endian)
6570 number_to_chars_bigendian (buf, val, n);
6571 else
6572 number_to_chars_littleendian (buf, val, n);
6573 }
6574
6575 static valueT
6576 md_chars_to_number (buf, n)
6577 char * buf;
6578 int n;
6579 {
6580 valueT result = 0;
6581 unsigned char * where = (unsigned char *) buf;
6582
6583 if (target_big_endian)
6584 {
6585 while (n--)
6586 {
6587 result <<= 8;
6588 result |= (*where++ & 255);
6589 }
6590 }
6591 else
6592 {
6593 while (n--)
6594 {
6595 result <<= 8;
6596 result |= (where[n] & 255);
6597 }
6598 }
6599
6600 return result;
6601 }
6602
6603 /* Turn a string in input_line_pointer into a floating point constant
6604 of type TYPE, and store the appropriate bytes in *LITP. The number
6605 of LITTLENUMS emitted is stored in *SIZEP. An error message is
6606 returned, or NULL on OK.
6607
6608 Note that fp constants aren't represent in the normal way on the ARM.
6609 In big endian mode, things are as expected. However, in little endian
6610 mode fp constants are big-endian word-wise, and little-endian byte-wise
6611 within the words. For example, (double) 1.1 in big endian mode is
6612 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
6613 the byte sequence 99 99 f1 3f 9a 99 99 99.
6614
6615 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
6616
6617 char *
6618 md_atof (type, litP, sizeP)
6619 char type;
6620 char * litP;
6621 int * sizeP;
6622 {
6623 int prec;
6624 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6625 char *t;
6626 int i;
6627
6628 switch (type)
6629 {
6630 case 'f':
6631 case 'F':
6632 case 's':
6633 case 'S':
6634 prec = 2;
6635 break;
6636
6637 case 'd':
6638 case 'D':
6639 case 'r':
6640 case 'R':
6641 prec = 4;
6642 break;
6643
6644 case 'x':
6645 case 'X':
6646 prec = 6;
6647 break;
6648
6649 case 'p':
6650 case 'P':
6651 prec = 6;
6652 break;
6653
6654 default:
6655 *sizeP = 0;
6656 return _("Bad call to MD_ATOF()");
6657 }
6658
6659 t = atof_ieee (input_line_pointer, type, words);
6660 if (t)
6661 input_line_pointer = t;
6662 *sizeP = prec * 2;
6663
6664 if (target_big_endian)
6665 {
6666 for (i = 0; i < prec; i++)
6667 {
6668 md_number_to_chars (litP, (valueT) words[i], 2);
6669 litP += 2;
6670 }
6671 }
6672 else
6673 {
6674 /* For a 4 byte float the order of elements in `words' is 1 0. For an
6675 8 byte float the order is 1 0 3 2. */
6676 for (i = 0; i < prec; i += 2)
6677 {
6678 md_number_to_chars (litP, (valueT) words[i + 1], 2);
6679 md_number_to_chars (litP + 2, (valueT) words[i], 2);
6680 litP += 4;
6681 }
6682 }
6683
6684 return 0;
6685 }
6686
6687 /* The knowledge of the PC's pipeline offset is built into the insns
6688 themselves. */
6689
6690 long
6691 md_pcrel_from (fixP)
6692 fixS * fixP;
6693 {
6694 if (fixP->fx_addsy
6695 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
6696 && fixP->fx_subsy == NULL)
6697 return 0;
6698
6699 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
6700 {
6701 /* PC relative addressing on the Thumb is slightly odd
6702 as the bottom two bits of the PC are forced to zero
6703 for the calculation. */
6704 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
6705 }
6706
6707 #ifdef TE_WINCE
6708 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
6709 so we un-adjust here to compensate for the accomodation. */
6710 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
6711 #else
6712 return fixP->fx_where + fixP->fx_frag->fr_address;
6713 #endif
6714 }
6715
6716 /* Round up a section size to the appropriate boundary. */
6717
6718 valueT
6719 md_section_align (segment, size)
6720 segT segment ATTRIBUTE_UNUSED;
6721 valueT size;
6722 {
6723 #ifdef OBJ_ELF
6724 return size;
6725 #else
6726 /* Round all sects to multiple of 4. */
6727 return (size + 3) & ~3;
6728 #endif
6729 }
6730
6731 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6732 Otherwise we have no need to default values of symbols. */
6733
6734 symbolS *
6735 md_undefined_symbol (name)
6736 char * name ATTRIBUTE_UNUSED;
6737 {
6738 #ifdef OBJ_ELF
6739 if (name[0] == '_' && name[1] == 'G'
6740 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6741 {
6742 if (!GOT_symbol)
6743 {
6744 if (symbol_find (name))
6745 as_bad ("GOT already in the symbol table");
6746
6747 GOT_symbol = symbol_new (name, undefined_section,
6748 (valueT) 0, & zero_address_frag);
6749 }
6750
6751 return GOT_symbol;
6752 }
6753 #endif
6754
6755 return 0;
6756 }
6757
6758 /* arm_reg_parse () := if it looks like a register, return its token and
6759 advance the pointer. */
6760
6761 static int
6762 arm_reg_parse (ccp)
6763 register char ** ccp;
6764 {
6765 char * start = * ccp;
6766 char c;
6767 char * p;
6768 struct reg_entry * reg;
6769
6770 #ifdef REGISTER_PREFIX
6771 if (*start != REGISTER_PREFIX)
6772 return FAIL;
6773 p = start + 1;
6774 #else
6775 p = start;
6776 #ifdef OPTIONAL_REGISTER_PREFIX
6777 if (*p == OPTIONAL_REGISTER_PREFIX)
6778 p++, start++;
6779 #endif
6780 #endif
6781 if (!ISALPHA (*p) || !is_name_beginner (*p))
6782 return FAIL;
6783
6784 c = *p++;
6785 while (ISALPHA (c) || ISDIGIT (c) || c == '_')
6786 c = *p++;
6787
6788 *--p = 0;
6789 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
6790 *p = c;
6791
6792 if (reg)
6793 {
6794 *ccp = p;
6795 return reg->number;
6796 }
6797
6798 return FAIL;
6799 }
6800
6801 int
6802 md_apply_fix3 (fixP, val, seg)
6803 fixS * fixP;
6804 valueT * val;
6805 segT seg;
6806 {
6807 offsetT value = * val;
6808 offsetT newval;
6809 unsigned int newimm;
6810 unsigned long temp;
6811 int sign;
6812 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6813 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
6814
6815 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
6816
6817 /* Note whether this will delete the relocation. */
6818 #if 0
6819 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
6820 doesn't work fully.) */
6821 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
6822 && !fixP->fx_pcrel)
6823 #else
6824 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6825 #endif
6826 fixP->fx_done = 1;
6827
6828 /* If this symbol is in a different section then we need to leave it for
6829 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
6830 so we have to undo it's effects here. */
6831 if (fixP->fx_pcrel)
6832 {
6833 if (fixP->fx_addsy != NULL
6834 && S_IS_DEFINED (fixP->fx_addsy)
6835 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6836 {
6837 if (target_oabi
6838 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
6839 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
6840 ))
6841 value = 0;
6842 else
6843 value += md_pcrel_from (fixP);
6844 }
6845 }
6846
6847 /* Remember value for emit_reloc. */
6848 fixP->fx_addnumber = value;
6849
6850 switch (fixP->fx_r_type)
6851 {
6852 case BFD_RELOC_ARM_IMMEDIATE:
6853 newimm = validate_immediate (value);
6854 temp = md_chars_to_number (buf, INSN_SIZE);
6855
6856 /* If the instruction will fail, see if we can fix things up by
6857 changing the opcode. */
6858 if (newimm == (unsigned int) FAIL
6859 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
6860 {
6861 as_bad_where (fixP->fx_file, fixP->fx_line,
6862 _("invalid constant (%lx) after fixup"),
6863 (unsigned long) value);
6864 break;
6865 }
6866
6867 newimm |= (temp & 0xfffff000);
6868 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6869 break;
6870
6871 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6872 {
6873 unsigned int highpart = 0;
6874 unsigned int newinsn = 0xe1a00000; /* nop. */
6875 newimm = validate_immediate (value);
6876 temp = md_chars_to_number (buf, INSN_SIZE);
6877
6878 /* If the instruction will fail, see if we can fix things up by
6879 changing the opcode. */
6880 if (newimm == (unsigned int) FAIL
6881 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
6882 {
6883 /* No ? OK - try using two ADD instructions to generate
6884 the value. */
6885 newimm = validate_immediate_twopart (value, & highpart);
6886
6887 /* Yes - then make sure that the second instruction is
6888 also an add. */
6889 if (newimm != (unsigned int) FAIL)
6890 newinsn = temp;
6891 /* Still No ? Try using a negated value. */
6892 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
6893 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
6894 /* Otherwise - give up. */
6895 else
6896 {
6897 as_bad_where (fixP->fx_file, fixP->fx_line,
6898 _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
6899 value);
6900 break;
6901 }
6902
6903 /* Replace the first operand in the 2nd instruction (which
6904 is the PC) with the destination register. We have
6905 already added in the PC in the first instruction and we
6906 do not want to do it again. */
6907 newinsn &= ~ 0xf0000;
6908 newinsn |= ((newinsn & 0x0f000) << 4);
6909 }
6910
6911 newimm |= (temp & 0xfffff000);
6912 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6913
6914 highpart |= (newinsn & 0xfffff000);
6915 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
6916 }
6917 break;
6918
6919 case BFD_RELOC_ARM_OFFSET_IMM:
6920 sign = value >= 0;
6921
6922 if (value < 0)
6923 value = - value;
6924
6925 if (validate_offset_imm (value, 0) == FAIL)
6926 {
6927 as_bad_where (fixP->fx_file, fixP->fx_line,
6928 _("bad immediate value for offset (%ld)"),
6929 (long) value);
6930 break;
6931 }
6932
6933 newval = md_chars_to_number (buf, INSN_SIZE);
6934 newval &= 0xff7ff000;
6935 newval |= value | (sign ? INDEX_UP : 0);
6936 md_number_to_chars (buf, newval, INSN_SIZE);
6937 break;
6938
6939 case BFD_RELOC_ARM_OFFSET_IMM8:
6940 case BFD_RELOC_ARM_HWLITERAL:
6941 sign = value >= 0;
6942
6943 if (value < 0)
6944 value = - value;
6945
6946 if (validate_offset_imm (value, 1) == FAIL)
6947 {
6948 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
6949 as_bad_where (fixP->fx_file, fixP->fx_line,
6950 _("invalid literal constant: pool needs to be closer"));
6951 else
6952 as_bad (_("bad immediate value for half-word offset (%ld)"),
6953 (long) value);
6954 break;
6955 }
6956
6957 newval = md_chars_to_number (buf, INSN_SIZE);
6958 newval &= 0xff7ff0f0;
6959 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
6960 md_number_to_chars (buf, newval, INSN_SIZE);
6961 break;
6962
6963 case BFD_RELOC_ARM_LITERAL:
6964 sign = value >= 0;
6965
6966 if (value < 0)
6967 value = - value;
6968
6969 if (validate_offset_imm (value, 0) == FAIL)
6970 {
6971 as_bad_where (fixP->fx_file, fixP->fx_line,
6972 _("invalid literal constant: pool needs to be closer"));
6973 break;
6974 }
6975
6976 newval = md_chars_to_number (buf, INSN_SIZE);
6977 newval &= 0xff7ff000;
6978 newval |= value | (sign ? INDEX_UP : 0);
6979 md_number_to_chars (buf, newval, INSN_SIZE);
6980 break;
6981
6982 case BFD_RELOC_ARM_SHIFT_IMM:
6983 newval = md_chars_to_number (buf, INSN_SIZE);
6984 if (((unsigned long) value) > 32
6985 || (value == 32
6986 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
6987 {
6988 as_bad_where (fixP->fx_file, fixP->fx_line,
6989 _("shift expression is too large"));
6990 break;
6991 }
6992
6993 if (value == 0)
6994 /* Shifts of zero must be done as lsl. */
6995 newval &= ~0x60;
6996 else if (value == 32)
6997 value = 0;
6998 newval &= 0xfffff07f;
6999 newval |= (value & 0x1f) << 7;
7000 md_number_to_chars (buf, newval, INSN_SIZE);
7001 break;
7002
7003 case BFD_RELOC_ARM_SWI:
7004 if (arm_data->thumb_mode)
7005 {
7006 if (((unsigned long) value) > 0xff)
7007 as_bad_where (fixP->fx_file, fixP->fx_line,
7008 _("Invalid swi expression"));
7009 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
7010 newval |= value;
7011 md_number_to_chars (buf, newval, THUMB_SIZE);
7012 }
7013 else
7014 {
7015 if (((unsigned long) value) > 0x00ffffff)
7016 as_bad_where (fixP->fx_file, fixP->fx_line,
7017 _("Invalid swi expression"));
7018 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
7019 newval |= value;
7020 md_number_to_chars (buf, newval, INSN_SIZE);
7021 }
7022 break;
7023
7024 case BFD_RELOC_ARM_MULTI:
7025 if (((unsigned long) value) > 0xffff)
7026 as_bad_where (fixP->fx_file, fixP->fx_line,
7027 _("Invalid expression in load/store multiple"));
7028 newval = value | md_chars_to_number (buf, INSN_SIZE);
7029 md_number_to_chars (buf, newval, INSN_SIZE);
7030 break;
7031
7032 case BFD_RELOC_ARM_PCREL_BRANCH:
7033 newval = md_chars_to_number (buf, INSN_SIZE);
7034
7035 /* Sign-extend a 24-bit number. */
7036 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
7037
7038 #ifdef OBJ_ELF
7039 if (! target_oabi)
7040 value = fixP->fx_offset;
7041 #endif
7042
7043 /* We are going to store value (shifted right by two) in the
7044 instruction, in a 24 bit, signed field. Thus we need to check
7045 that none of the top 8 bits of the shifted value (top 7 bits of
7046 the unshifted, unsigned value) are set, or that they are all set. */
7047 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
7048 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
7049 {
7050 #ifdef OBJ_ELF
7051 /* Normally we would be stuck at this point, since we cannot store
7052 the absolute address that is the destination of the branch in the
7053 24 bits of the branch instruction. If however, we happen to know
7054 that the destination of the branch is in the same section as the
7055 branch instruciton itself, then we can compute the relocation for
7056 ourselves and not have to bother the linker with it.
7057
7058 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
7059 because I have not worked out how to do this for OBJ_COFF or
7060 target_oabi. */
7061 if (! target_oabi
7062 && fixP->fx_addsy != NULL
7063 && S_IS_DEFINED (fixP->fx_addsy)
7064 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
7065 {
7066 /* Get pc relative value to go into the branch. */
7067 value = * val;
7068
7069 /* Permit a backward branch provided that enough bits
7070 are set. Allow a forwards branch, provided that
7071 enough bits are clear. */
7072 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
7073 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
7074 fixP->fx_done = 1;
7075 }
7076
7077 if (! fixP->fx_done)
7078 #endif
7079 as_bad_where (fixP->fx_file, fixP->fx_line,
7080 _("gas can't handle same-section branch dest >= 0x04000000"));
7081 }
7082
7083 value >>= 2;
7084 value += SEXT24 (newval);
7085
7086 if ( (value & ~ ((offsetT) 0xffffff)) != 0
7087 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
7088 as_bad_where (fixP->fx_file, fixP->fx_line,
7089 _("out of range branch"));
7090
7091 newval = (value & 0x00ffffff) | (newval & 0xff000000);
7092 md_number_to_chars (buf, newval, INSN_SIZE);
7093 break;
7094
7095 case BFD_RELOC_ARM_PCREL_BLX:
7096 {
7097 offsetT hbit;
7098 newval = md_chars_to_number (buf, INSN_SIZE);
7099
7100 #ifdef OBJ_ELF
7101 if (! target_oabi)
7102 value = fixP->fx_offset;
7103 #endif
7104 hbit = (value >> 1) & 1;
7105 value = (value >> 2) & 0x00ffffff;
7106 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
7107 newval = value | (newval & 0xfe000000) | (hbit << 24);
7108 md_number_to_chars (buf, newval, INSN_SIZE);
7109 }
7110 break;
7111
7112 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
7113 newval = md_chars_to_number (buf, THUMB_SIZE);
7114 {
7115 addressT diff = (newval & 0xff) << 1;
7116 if (diff & 0x100)
7117 diff |= ~0xff;
7118
7119 value += diff;
7120 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
7121 as_bad_where (fixP->fx_file, fixP->fx_line,
7122 _("Branch out of range"));
7123 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
7124 }
7125 md_number_to_chars (buf, newval, THUMB_SIZE);
7126 break;
7127
7128 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
7129 newval = md_chars_to_number (buf, THUMB_SIZE);
7130 {
7131 addressT diff = (newval & 0x7ff) << 1;
7132 if (diff & 0x800)
7133 diff |= ~0x7ff;
7134
7135 value += diff;
7136 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
7137 as_bad_where (fixP->fx_file, fixP->fx_line,
7138 _("Branch out of range"));
7139 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
7140 }
7141 md_number_to_chars (buf, newval, THUMB_SIZE);
7142 break;
7143
7144 case BFD_RELOC_THUMB_PCREL_BLX:
7145 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7146 {
7147 offsetT newval2;
7148 addressT diff;
7149
7150 newval = md_chars_to_number (buf, THUMB_SIZE);
7151 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
7152 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
7153 if (diff & 0x400000)
7154 diff |= ~0x3fffff;
7155 #ifdef OBJ_ELF
7156 value = fixP->fx_offset;
7157 #endif
7158 value += diff;
7159 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
7160 as_bad_where (fixP->fx_file, fixP->fx_line,
7161 _("Branch with link out of range"));
7162
7163 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
7164 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
7165 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
7166 /* Remove bit zero of the adjusted offset. Bit zero can only be
7167 set if the upper insn is at a half-word boundary, since the
7168 destination address, an ARM instruction, must always be on a
7169 word boundary. The semantics of the BLX (1) instruction, however,
7170 are that bit zero in the offset must always be zero, and the
7171 corresponding bit one in the target address will be set from bit
7172 one of the source address. */
7173 newval2 &= ~1;
7174 md_number_to_chars (buf, newval, THUMB_SIZE);
7175 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
7176 }
7177 break;
7178
7179 case BFD_RELOC_8:
7180 if (fixP->fx_done || fixP->fx_pcrel)
7181 md_number_to_chars (buf, value, 1);
7182 #ifdef OBJ_ELF
7183 else if (!target_oabi)
7184 {
7185 value = fixP->fx_offset;
7186 md_number_to_chars (buf, value, 1);
7187 }
7188 #endif
7189 break;
7190
7191 case BFD_RELOC_16:
7192 if (fixP->fx_done || fixP->fx_pcrel)
7193 md_number_to_chars (buf, value, 2);
7194 #ifdef OBJ_ELF
7195 else if (!target_oabi)
7196 {
7197 value = fixP->fx_offset;
7198 md_number_to_chars (buf, value, 2);
7199 }
7200 #endif
7201 break;
7202
7203 #ifdef OBJ_ELF
7204 case BFD_RELOC_ARM_GOT32:
7205 case BFD_RELOC_ARM_GOTOFF:
7206 md_number_to_chars (buf, 0, 4);
7207 break;
7208 #endif
7209
7210 case BFD_RELOC_RVA:
7211 case BFD_RELOC_32:
7212 if (fixP->fx_done || fixP->fx_pcrel)
7213 md_number_to_chars (buf, value, 4);
7214 #ifdef OBJ_ELF
7215 else if (!target_oabi)
7216 {
7217 value = fixP->fx_offset;
7218 md_number_to_chars (buf, value, 4);
7219 }
7220 #endif
7221 break;
7222
7223 #ifdef OBJ_ELF
7224 case BFD_RELOC_ARM_PLT32:
7225 /* It appears the instruction is fully prepared at this point. */
7226 break;
7227 #endif
7228
7229 case BFD_RELOC_ARM_GOTPC:
7230 md_number_to_chars (buf, value, 4);
7231 break;
7232
7233 case BFD_RELOC_ARM_CP_OFF_IMM:
7234 sign = value >= 0;
7235 if (value < -1023 || value > 1023 || (value & 3))
7236 as_bad_where (fixP->fx_file, fixP->fx_line,
7237 _("Illegal value for co-processor offset"));
7238 if (value < 0)
7239 value = -value;
7240 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
7241 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
7242 md_number_to_chars (buf, newval, INSN_SIZE);
7243 break;
7244
7245 case BFD_RELOC_ARM_THUMB_OFFSET:
7246 newval = md_chars_to_number (buf, THUMB_SIZE);
7247 /* Exactly what ranges, and where the offset is inserted depends
7248 on the type of instruction, we can establish this from the
7249 top 4 bits. */
7250 switch (newval >> 12)
7251 {
7252 case 4: /* PC load. */
7253 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
7254 forced to zero for these loads, so we will need to round
7255 up the offset if the instruction address is not word
7256 aligned (since the final address produced must be, and
7257 we can only describe word-aligned immediate offsets). */
7258
7259 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
7260 as_bad_where (fixP->fx_file, fixP->fx_line,
7261 _("Invalid offset, target not word aligned (0x%08X)"),
7262 (unsigned int) (fixP->fx_frag->fr_address
7263 + fixP->fx_where + value));
7264
7265 if ((value + 2) & ~0x3fe)
7266 as_bad_where (fixP->fx_file, fixP->fx_line,
7267 _("Invalid offset, value too big (0x%08lX)"), value);
7268
7269 /* Round up, since pc will be rounded down. */
7270 newval |= (value + 2) >> 2;
7271 break;
7272
7273 case 9: /* SP load/store. */
7274 if (value & ~0x3fc)
7275 as_bad_where (fixP->fx_file, fixP->fx_line,
7276 _("Invalid offset, value too big (0x%08lX)"), value);
7277 newval |= value >> 2;
7278 break;
7279
7280 case 6: /* Word load/store. */
7281 if (value & ~0x7c)
7282 as_bad_where (fixP->fx_file, fixP->fx_line,
7283 _("Invalid offset, value too big (0x%08lX)"), value);
7284 newval |= value << 4; /* 6 - 2. */
7285 break;
7286
7287 case 7: /* Byte load/store. */
7288 if (value & ~0x1f)
7289 as_bad_where (fixP->fx_file, fixP->fx_line,
7290 _("Invalid offset, value too big (0x%08lX)"), value);
7291 newval |= value << 6;
7292 break;
7293
7294 case 8: /* Halfword load/store. */
7295 if (value & ~0x3e)
7296 as_bad_where (fixP->fx_file, fixP->fx_line,
7297 _("Invalid offset, value too big (0x%08lX)"), value);
7298 newval |= value << 5; /* 6 - 1. */
7299 break;
7300
7301 default:
7302 as_bad_where (fixP->fx_file, fixP->fx_line,
7303 "Unable to process relocation for thumb opcode: %lx",
7304 (unsigned long) newval);
7305 break;
7306 }
7307 md_number_to_chars (buf, newval, THUMB_SIZE);
7308 break;
7309
7310 case BFD_RELOC_ARM_THUMB_ADD:
7311 /* This is a complicated relocation, since we use it for all of
7312 the following immediate relocations:
7313
7314 3bit ADD/SUB
7315 8bit ADD/SUB
7316 9bit ADD/SUB SP word-aligned
7317 10bit ADD PC/SP word-aligned
7318
7319 The type of instruction being processed is encoded in the
7320 instruction field:
7321
7322 0x8000 SUB
7323 0x00F0 Rd
7324 0x000F Rs
7325 */
7326 newval = md_chars_to_number (buf, THUMB_SIZE);
7327 {
7328 int rd = (newval >> 4) & 0xf;
7329 int rs = newval & 0xf;
7330 int subtract = newval & 0x8000;
7331
7332 if (rd == REG_SP)
7333 {
7334 if (value & ~0x1fc)
7335 as_bad_where (fixP->fx_file, fixP->fx_line,
7336 _("Invalid immediate for stack address calculation"));
7337 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
7338 newval |= value >> 2;
7339 }
7340 else if (rs == REG_PC || rs == REG_SP)
7341 {
7342 if (subtract ||
7343 value & ~0x3fc)
7344 as_bad_where (fixP->fx_file, fixP->fx_line,
7345 _("Invalid immediate for address calculation (value = 0x%08lX)"),
7346 (unsigned long) value);
7347 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
7348 newval |= rd << 8;
7349 newval |= value >> 2;
7350 }
7351 else if (rs == rd)
7352 {
7353 if (value & ~0xff)
7354 as_bad_where (fixP->fx_file, fixP->fx_line,
7355 _("Invalid 8bit immediate"));
7356 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
7357 newval |= (rd << 8) | value;
7358 }
7359 else
7360 {
7361 if (value & ~0x7)
7362 as_bad_where (fixP->fx_file, fixP->fx_line,
7363 _("Invalid 3bit immediate"));
7364 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
7365 newval |= rd | (rs << 3) | (value << 6);
7366 }
7367 }
7368 md_number_to_chars (buf, newval, THUMB_SIZE);
7369 break;
7370
7371 case BFD_RELOC_ARM_THUMB_IMM:
7372 newval = md_chars_to_number (buf, THUMB_SIZE);
7373 switch (newval >> 11)
7374 {
7375 case 0x04: /* 8bit immediate MOV. */
7376 case 0x05: /* 8bit immediate CMP. */
7377 if (value < 0 || value > 255)
7378 as_bad_where (fixP->fx_file, fixP->fx_line,
7379 _("Invalid immediate: %ld is too large"),
7380 (long) value);
7381 newval |= value;
7382 break;
7383
7384 default:
7385 abort ();
7386 }
7387 md_number_to_chars (buf, newval, THUMB_SIZE);
7388 break;
7389
7390 case BFD_RELOC_ARM_THUMB_SHIFT:
7391 /* 5bit shift value (0..31). */
7392 if (value < 0 || value > 31)
7393 as_bad_where (fixP->fx_file, fixP->fx_line,
7394 _("Illegal Thumb shift value: %ld"), (long) value);
7395 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
7396 newval |= value << 6;
7397 md_number_to_chars (buf, newval, THUMB_SIZE);
7398 break;
7399
7400 case BFD_RELOC_VTABLE_INHERIT:
7401 case BFD_RELOC_VTABLE_ENTRY:
7402 fixP->fx_done = 0;
7403 return 1;
7404
7405 case BFD_RELOC_NONE:
7406 default:
7407 as_bad_where (fixP->fx_file, fixP->fx_line,
7408 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
7409 }
7410
7411 return 1;
7412 }
7413
7414 /* Translate internal representation of relocation info to BFD target
7415 format. */
7416
7417 arelent *
7418 tc_gen_reloc (section, fixp)
7419 asection * section ATTRIBUTE_UNUSED;
7420 fixS * fixp;
7421 {
7422 arelent * reloc;
7423 bfd_reloc_code_real_type code;
7424
7425 reloc = (arelent *) xmalloc (sizeof (arelent));
7426
7427 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7428 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7429 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7430
7431 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
7432 #ifndef OBJ_ELF
7433 if (fixp->fx_pcrel == 0)
7434 reloc->addend = fixp->fx_offset;
7435 else
7436 reloc->addend = fixp->fx_offset = reloc->address;
7437 #else /* OBJ_ELF */
7438 reloc->addend = fixp->fx_offset;
7439 #endif
7440
7441 switch (fixp->fx_r_type)
7442 {
7443 case BFD_RELOC_8:
7444 if (fixp->fx_pcrel)
7445 {
7446 code = BFD_RELOC_8_PCREL;
7447 break;
7448 }
7449
7450 case BFD_RELOC_16:
7451 if (fixp->fx_pcrel)
7452 {
7453 code = BFD_RELOC_16_PCREL;
7454 break;
7455 }
7456
7457 case BFD_RELOC_32:
7458 if (fixp->fx_pcrel)
7459 {
7460 code = BFD_RELOC_32_PCREL;
7461 break;
7462 }
7463
7464 case BFD_RELOC_ARM_PCREL_BRANCH:
7465 case BFD_RELOC_ARM_PCREL_BLX:
7466 case BFD_RELOC_RVA:
7467 case BFD_RELOC_THUMB_PCREL_BRANCH9:
7468 case BFD_RELOC_THUMB_PCREL_BRANCH12:
7469 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7470 case BFD_RELOC_THUMB_PCREL_BLX:
7471 case BFD_RELOC_VTABLE_ENTRY:
7472 case BFD_RELOC_VTABLE_INHERIT:
7473 code = fixp->fx_r_type;
7474 break;
7475
7476 case BFD_RELOC_ARM_LITERAL:
7477 case BFD_RELOC_ARM_HWLITERAL:
7478 /* If this is called then the a literal has been referenced across
7479 a section boundary - possibly due to an implicit dump. */
7480 as_bad_where (fixp->fx_file, fixp->fx_line,
7481 _("Literal referenced across section boundary (Implicit dump?)"));
7482 return NULL;
7483
7484 #ifdef OBJ_ELF
7485 case BFD_RELOC_ARM_GOT32:
7486 case BFD_RELOC_ARM_GOTOFF:
7487 case BFD_RELOC_ARM_PLT32:
7488 code = fixp->fx_r_type;
7489 break;
7490 #endif
7491
7492 case BFD_RELOC_ARM_IMMEDIATE:
7493 as_bad_where (fixp->fx_file, fixp->fx_line,
7494 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
7495 fixp->fx_r_type);
7496 return NULL;
7497
7498 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
7499 as_bad_where (fixp->fx_file, fixp->fx_line,
7500 _("ADRL used for a symbol not defined in the same file"));
7501 return NULL;
7502
7503 case BFD_RELOC_ARM_OFFSET_IMM:
7504 as_bad_where (fixp->fx_file, fixp->fx_line,
7505 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
7506 fixp->fx_r_type);
7507 return NULL;
7508
7509 default:
7510 {
7511 char * type;
7512
7513 switch (fixp->fx_r_type)
7514 {
7515 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
7516 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
7517 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
7518 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
7519 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
7520 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
7521 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
7522 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
7523 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
7524 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
7525 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
7526 default: type = _("<unknown>"); break;
7527 }
7528 as_bad_where (fixp->fx_file, fixp->fx_line,
7529 _("Cannot represent %s relocation in this object file format"),
7530 type);
7531 return NULL;
7532 }
7533 }
7534
7535 #ifdef OBJ_ELF
7536 if (code == BFD_RELOC_32_PCREL
7537 && GOT_symbol
7538 && fixp->fx_addsy == GOT_symbol)
7539 {
7540 code = BFD_RELOC_ARM_GOTPC;
7541 reloc->addend = fixp->fx_offset = reloc->address;
7542 }
7543 #endif
7544
7545 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7546
7547 if (reloc->howto == NULL)
7548 {
7549 as_bad_where (fixp->fx_file, fixp->fx_line,
7550 _("Can not represent %s relocation in this object file format"),
7551 bfd_get_reloc_code_name (code));
7552 return NULL;
7553 }
7554
7555 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
7556 vtable entry to be used in the relocation's section offset. */
7557 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7558 reloc->address = fixp->fx_offset;
7559
7560 return reloc;
7561 }
7562
7563 int
7564 md_estimate_size_before_relax (fragP, segtype)
7565 fragS * fragP ATTRIBUTE_UNUSED;
7566 segT segtype ATTRIBUTE_UNUSED;
7567 {
7568 as_fatal (_("md_estimate_size_before_relax\n"));
7569 return 1;
7570 }
7571
7572 static void
7573 output_inst PARAMS ((void))
7574 {
7575 char * to = NULL;
7576
7577 if (inst.error)
7578 {
7579 as_bad (inst.error);
7580 return;
7581 }
7582
7583 to = frag_more (inst.size);
7584
7585 if (thumb_mode && (inst.size > THUMB_SIZE))
7586 {
7587 assert (inst.size == (2 * THUMB_SIZE));
7588 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7589 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7590 }
7591 else if (inst.size > INSN_SIZE)
7592 {
7593 assert (inst.size == (2 * INSN_SIZE));
7594 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7595 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7596 }
7597 else
7598 md_number_to_chars (to, inst.instruction, inst.size);
7599
7600 if (inst.reloc.type != BFD_RELOC_NONE)
7601 fix_new_arm (frag_now, to - frag_now->fr_literal,
7602 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7603 inst.reloc.type);
7604
7605 #ifdef OBJ_ELF
7606 dwarf2_emit_insn (inst.size);
7607 #endif
7608 }
7609
7610 void
7611 md_assemble (str)
7612 char * str;
7613 {
7614 char c;
7615 char * p;
7616 char * q;
7617 char * start;
7618
7619 /* Align the instruction.
7620 This may not be the right thing to do but ... */
7621 #if 0
7622 arm_align (2, 0);
7623 #endif
7624 listing_prev_line (); /* Defined in listing.h. */
7625
7626 /* Align the previous label if needed. */
7627 if (last_label_seen != NULL)
7628 {
7629 symbol_set_frag (last_label_seen, frag_now);
7630 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7631 S_SET_SEGMENT (last_label_seen, now_seg);
7632 }
7633
7634 memset (&inst, '\0', sizeof (inst));
7635 inst.reloc.type = BFD_RELOC_NONE;
7636
7637 skip_whitespace (str);
7638
7639 /* Scan up to the end of the op-code, which must end in white space or
7640 end of string. */
7641 for (start = p = str; *p != '\0'; p++)
7642 if (*p == ' ')
7643 break;
7644
7645 if (p == str)
7646 {
7647 as_bad (_("No operator -- statement `%s'\n"), str);
7648 return;
7649 }
7650
7651 if (thumb_mode)
7652 {
7653 CONST struct thumb_opcode * opcode;
7654
7655 c = *p;
7656 *p = '\0';
7657 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
7658 *p = c;
7659
7660 if (opcode)
7661 {
7662 /* Check that this instruction is supported for this CPU. */
7663 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
7664 {
7665 as_bad (_("selected processor does not support this opcode"));
7666 return;
7667 }
7668
7669 inst.instruction = opcode->value;
7670 inst.size = opcode->size;
7671 (*opcode->parms) (p);
7672 output_inst ();
7673 return;
7674 }
7675 }
7676 else
7677 {
7678 CONST struct asm_opcode * opcode;
7679 unsigned long cond_code;
7680
7681 inst.size = INSN_SIZE;
7682 /* P now points to the end of the opcode, probably white space, but we
7683 have to break the opcode up in case it contains condionals and flags;
7684 keep trying with progressively smaller basic instructions until one
7685 matches, or we run out of opcode. */
7686 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
7687
7688 for (; q != str; q--)
7689 {
7690 c = *q;
7691 *q = '\0';
7692
7693 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
7694 *q = c;
7695
7696 if (opcode && opcode->template)
7697 {
7698 unsigned long flag_bits = 0;
7699 char * r;
7700
7701 /* Check that this instruction is supported for this CPU. */
7702 if ((opcode->variants & cpu_variant) == 0)
7703 goto try_shorter;
7704
7705 inst.instruction = opcode->value;
7706 if (q == p) /* Just a simple opcode. */
7707 {
7708 if (opcode->comp_suffix)
7709 {
7710 if (*opcode->comp_suffix != '\0')
7711 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
7712 str, opcode->comp_suffix);
7713 else
7714 /* Not a conditional instruction. */
7715 (*opcode->parms) (q, 0);
7716 }
7717 else
7718 {
7719 /* A conditional instruction with default condition. */
7720 inst.instruction |= COND_ALWAYS;
7721 (*opcode->parms) (q, 0);
7722 }
7723 output_inst ();
7724 return;
7725 }
7726
7727 /* Not just a simple opcode. Check if extra is a
7728 conditional. */
7729 r = q;
7730 if (p - r >= 2)
7731 {
7732 CONST struct asm_cond *cond;
7733 char d = *(r + 2);
7734
7735 *(r + 2) = '\0';
7736 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
7737 *(r + 2) = d;
7738 if (cond)
7739 {
7740 if (cond->value == 0xf0000000)
7741 as_tsktsk (
7742 _("Warning: Use of the 'nv' conditional is deprecated\n"));
7743
7744 cond_code = cond->value;
7745 r += 2;
7746 }
7747 else
7748 cond_code = COND_ALWAYS;
7749 }
7750 else
7751 cond_code = COND_ALWAYS;
7752
7753 /* Apply the conditional, or complain it's not allowed. */
7754 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
7755 {
7756 /* Instruction isn't conditional. */
7757 if (cond_code != COND_ALWAYS)
7758 {
7759 as_bad (_("Opcode `%s' is unconditional\n"), str);
7760 return;
7761 }
7762 }
7763 else
7764 /* Instruction is conditional: set the condition into it. */
7765 inst.instruction |= cond_code;
7766
7767 /* If there is a compulsory suffix, it should come here
7768 before any optional flags. */
7769 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
7770 {
7771 CONST char *s = opcode->comp_suffix;
7772
7773 while (*s)
7774 {
7775 inst.suffix++;
7776 if (*r == *s)
7777 break;
7778 s++;
7779 }
7780
7781 if (*s == '\0')
7782 {
7783 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
7784 str, opcode->comp_suffix);
7785 return;
7786 }
7787
7788 r++;
7789 }
7790
7791 /* The remainder, if any should now be flags for the instruction;
7792 Scan these checking each one found with the opcode. */
7793 if (r != p)
7794 {
7795 char d;
7796 CONST struct asm_flg *flag = opcode->flags;
7797
7798 if (flag)
7799 {
7800 int flagno;
7801
7802 d = *p;
7803 *p = '\0';
7804
7805 for (flagno = 0; flag[flagno].template; flagno++)
7806 {
7807 if (streq (r, flag[flagno].template))
7808 {
7809 flag_bits |= flag[flagno].set_bits;
7810 break;
7811 }
7812 }
7813
7814 *p = d;
7815 if (! flag[flagno].template)
7816 goto try_shorter;
7817 }
7818 else
7819 goto try_shorter;
7820 }
7821
7822 (*opcode->parms) (p, flag_bits);
7823 output_inst ();
7824 return;
7825 }
7826
7827 try_shorter:
7828 ;
7829 }
7830 }
7831
7832 /* It wasn't an instruction, but it might be a register alias of the form
7833 alias .req reg. */
7834 q = p;
7835 skip_whitespace (q);
7836
7837 c = *p;
7838 *p = '\0';
7839
7840 if (*q && !strncmp (q, ".req ", 4))
7841 {
7842 int reg;
7843 char * copy_of_str;
7844 char * r;
7845
7846 #ifdef IGNORE_OPCODE_CASE
7847 str = original_case_string;
7848 #endif
7849 copy_of_str = str;
7850
7851 q += 4;
7852 skip_whitespace (q);
7853
7854 for (r = q; *r != '\0'; r++)
7855 if (*r == ' ')
7856 break;
7857
7858 if (r != q)
7859 {
7860 int regnum;
7861 char d = *r;
7862
7863 *r = '\0';
7864 regnum = arm_reg_parse (& q);
7865 *r = d;
7866
7867 reg = arm_reg_parse (& str);
7868
7869 if (reg == FAIL)
7870 {
7871 if (regnum != FAIL)
7872 insert_reg_alias (str, regnum);
7873 else
7874 as_warn (_("register '%s' does not exist\n"), q);
7875 }
7876 else if (regnum != FAIL)
7877 {
7878 if (reg != regnum)
7879 as_warn (_("ignoring redefinition of register alias '%s'"),
7880 copy_of_str);
7881
7882 /* Do not warn about redefinitions to the same alias. */
7883 }
7884 else
7885 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
7886 copy_of_str, q);
7887 }
7888 else
7889 as_warn (_("ignoring incomplete .req pseuso op"));
7890
7891 *p = c;
7892 return;
7893 }
7894
7895 *p = c;
7896 as_bad (_("bad instruction `%s'"), start);
7897 }
7898
7899 /* md_parse_option
7900 Invocation line includes a switch not recognized by the base assembler.
7901 See if it's a processor-specific option. These are:
7902 Cpu variants, the arm part is optional:
7903 -m[arm]1 Currently not supported.
7904 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
7905 -m[arm]3 Arm 3 processor
7906 -m[arm]6[xx], Arm 6 processors
7907 -m[arm]7[xx][t][[d]m] Arm 7 processors
7908 -m[arm]8[10] Arm 8 processors
7909 -m[arm]9[20][tdmi] Arm 9 processors
7910 -mstrongarm[110[0]] StrongARM processors
7911 -mxscale XScale processors
7912 -m[arm]v[2345[t[e]]] Arm architectures
7913 -mall All (except the ARM1)
7914 FP variants:
7915 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
7916 -mfpe-old (No float load/store multiples)
7917 -mno-fpu Disable all floating point instructions
7918 Run-time endian selection:
7919 -EB big endian cpu
7920 -EL little endian cpu
7921 ARM Procedure Calling Standard:
7922 -mapcs-32 32 bit APCS
7923 -mapcs-26 26 bit APCS
7924 -mapcs-float Pass floats in float regs
7925 -mapcs-reentrant Position independent code
7926 -mthumb-interwork Code supports Arm/Thumb interworking
7927 -matpcs ARM/Thumb Procedure Call Standard
7928 -moabi Old ELF ABI */
7929
7930 CONST char * md_shortopts = "m:k";
7931
7932 struct option md_longopts[] =
7933 {
7934 #ifdef ARM_BI_ENDIAN
7935 #define OPTION_EB (OPTION_MD_BASE + 0)
7936 {"EB", no_argument, NULL, OPTION_EB},
7937 #define OPTION_EL (OPTION_MD_BASE + 1)
7938 {"EL", no_argument, NULL, OPTION_EL},
7939 #ifdef OBJ_ELF
7940 #define OPTION_OABI (OPTION_MD_BASE +2)
7941 {"oabi", no_argument, NULL, OPTION_OABI},
7942 #endif
7943 #endif
7944 {NULL, no_argument, NULL, 0}
7945 };
7946
7947 size_t md_longopts_size = sizeof (md_longopts);
7948
7949 int
7950 md_parse_option (c, arg)
7951 int c;
7952 char * arg;
7953 {
7954 char * str = arg;
7955
7956 switch (c)
7957 {
7958 #ifdef ARM_BI_ENDIAN
7959 case OPTION_EB:
7960 target_big_endian = 1;
7961 break;
7962 case OPTION_EL:
7963 target_big_endian = 0;
7964 break;
7965 #endif
7966
7967 case 'm':
7968 switch (*str)
7969 {
7970 case 'f':
7971 if (streq (str, "fpa10"))
7972 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
7973 else if (streq (str, "fpa11"))
7974 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
7975 else if (streq (str, "fpe-old"))
7976 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
7977 else
7978 goto bad;
7979 break;
7980
7981 case 'n':
7982 if (streq (str, "no-fpu"))
7983 cpu_variant &= ~FPU_ALL;
7984 break;
7985
7986 #ifdef OBJ_ELF
7987 case 'o':
7988 if (streq (str, "oabi"))
7989 target_oabi = true;
7990 break;
7991 #endif
7992
7993 case 't':
7994 /* Limit assembler to generating only Thumb instructions: */
7995 if (streq (str, "thumb"))
7996 {
7997 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB;
7998 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
7999 thumb_mode = 1;
8000 }
8001 else if (streq (str, "thumb-interwork"))
8002 {
8003 if ((cpu_variant & ARM_EXT_THUMB) == 0)
8004 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
8005 #if defined OBJ_COFF || defined OBJ_ELF
8006 support_interwork = true;
8007 #endif
8008 }
8009 else
8010 goto bad;
8011 break;
8012
8013 default:
8014 if (streq (str, "all"))
8015 {
8016 cpu_variant = ARM_ALL | FPU_ALL;
8017 return 1;
8018 }
8019 #if defined OBJ_COFF || defined OBJ_ELF
8020 if (! strncmp (str, "apcs-", 5))
8021 {
8022 /* GCC passes on all command line options starting "-mapcs-..."
8023 to us, so we must parse them here. */
8024
8025 str += 5;
8026
8027 if (streq (str, "32"))
8028 {
8029 uses_apcs_26 = false;
8030 return 1;
8031 }
8032 else if (streq (str, "26"))
8033 {
8034 uses_apcs_26 = true;
8035 return 1;
8036 }
8037 else if (streq (str, "frame"))
8038 {
8039 /* Stack frames are being generated - does not affect
8040 linkage of code. */
8041 return 1;
8042 }
8043 else if (streq (str, "stack-check"))
8044 {
8045 /* Stack checking is being performed - does not affect
8046 linkage, but does require that the functions
8047 __rt_stkovf_split_small and __rt_stkovf_split_big be
8048 present in the final link. */
8049
8050 return 1;
8051 }
8052 else if (streq (str, "float"))
8053 {
8054 /* Floating point arguments are being passed in the floating
8055 point registers. This does affect linking, since this
8056 version of the APCS is incompatible with the version that
8057 passes floating points in the integer registers. */
8058
8059 uses_apcs_float = true;
8060 return 1;
8061 }
8062 else if (streq (str, "reentrant"))
8063 {
8064 /* Reentrant code has been generated. This does affect
8065 linking, since there is no point in linking reentrant/
8066 position independent code with absolute position code. */
8067 pic_code = true;
8068 return 1;
8069 }
8070
8071 as_bad (_("Unrecognised APCS switch -m%s"), arg);
8072 return 0;
8073 }
8074
8075 if (! strcmp (str, "atpcs"))
8076 {
8077 atpcs = true;
8078 return 1;
8079 }
8080 #endif
8081 /* Strip off optional "arm". */
8082 if (! strncmp (str, "arm", 3))
8083 str += 3;
8084
8085 switch (*str)
8086 {
8087 case '1':
8088 if (streq (str, "1"))
8089 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
8090 else
8091 goto bad;
8092 break;
8093
8094 case '2':
8095 if (streq (str, "2"))
8096 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8097 else if (streq (str, "250"))
8098 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
8099 else
8100 goto bad;
8101 break;
8102
8103 case '3':
8104 if (streq (str, "3"))
8105 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8106 else
8107 goto bad;
8108 break;
8109
8110 case '6':
8111 switch (strtol (str, NULL, 10))
8112 {
8113 case 6:
8114 case 60:
8115 case 600:
8116 case 610:
8117 case 620:
8118 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
8119 break;
8120 default:
8121 goto bad;
8122 }
8123 break;
8124
8125 case '7':
8126 /* Eat the processor name. */
8127 switch (strtol (str, & str, 10))
8128 {
8129 case 7:
8130 case 70:
8131 case 700:
8132 case 710:
8133 case 720:
8134 case 7100:
8135 case 7500:
8136 break;
8137 default:
8138 goto bad;
8139 }
8140 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8141 for (; *str; str++)
8142 {
8143 switch (*str)
8144 {
8145 case 't':
8146 cpu_variant |= ARM_ARCH_V4T;
8147 break;
8148
8149 case 'm':
8150 cpu_variant |= ARM_EXT_LONGMUL;
8151 break;
8152
8153 case 'f': /* fe => fp enabled cpu. */
8154 if (str[1] == 'e')
8155 ++ str;
8156 else
8157 goto bad;
8158
8159 case 'c': /* Left over from 710c processor name. */
8160 case 'd': /* Debug. */
8161 case 'i': /* Embedded ICE. */
8162 /* Included for completeness in ARM processor naming. */
8163 break;
8164
8165 default:
8166 goto bad;
8167 }
8168 }
8169 break;
8170
8171 case '8':
8172 if (streq (str, "8") || streq (str, "810"))
8173 cpu_variant = (cpu_variant & ~ARM_ANY)
8174 | ARM_8 | ARM_ARCH_V4;
8175 else
8176 goto bad;
8177 break;
8178
8179 case '9':
8180 if (streq (str, "9"))
8181 cpu_variant = (cpu_variant & ~ARM_ANY)
8182 | ARM_9 | ARM_ARCH_V4T;
8183 else if (streq (str, "920"))
8184 cpu_variant = (cpu_variant & ~ARM_ANY)
8185 | ARM_9 | ARM_ARCH_V4;
8186 else if (streq (str, "920t"))
8187 cpu_variant = (cpu_variant & ~ARM_ANY)
8188 | ARM_9 | ARM_ARCH_V4T;
8189 else if (streq (str, "9tdmi"))
8190 cpu_variant = (cpu_variant & ~ARM_ANY)
8191 | ARM_9 | ARM_ARCH_V4T;
8192 else
8193 goto bad;
8194 break;
8195
8196 case 's':
8197 if (streq (str, "strongarm")
8198 || streq (str, "strongarm110")
8199 || streq (str, "strongarm1100"))
8200 cpu_variant = (cpu_variant & ~ARM_ANY)
8201 | ARM_8 | ARM_ARCH_V4;
8202 else
8203 goto bad;
8204 break;
8205
8206 case 'x':
8207 if (streq (str, "xscale"))
8208 cpu_variant = ARM_9 | ARM_ARCH_XSCALE;
8209 else
8210 goto bad;
8211 break;
8212
8213 case 'v':
8214 /* Select variant based on architecture rather than
8215 processor. */
8216 switch (*++str)
8217 {
8218 case '2':
8219 switch (*++str)
8220 {
8221 case 'a':
8222 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8223 break;
8224 case 0:
8225 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8226 break;
8227 default:
8228 as_bad (_("Invalid architecture variant -m%s"), arg);
8229 break;
8230 }
8231 break;
8232
8233 case '3':
8234 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8235
8236 switch (*++str)
8237 {
8238 case 'm': cpu_variant |= ARM_EXT_LONGMUL; break;
8239 case 0: break;
8240 default:
8241 as_bad (_("Invalid architecture variant -m%s"), arg);
8242 break;
8243 }
8244 break;
8245
8246 case '4':
8247 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
8248
8249 switch (*++str)
8250 {
8251 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8252 case 0: break;
8253 default:
8254 as_bad (_("Invalid architecture variant -m%s"), arg);
8255 break;
8256 }
8257 break;
8258
8259 case '5':
8260 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
8261 switch (*++str)
8262 {
8263 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8264 case 'e': cpu_variant |= ARM_EXT_V5E; break;
8265 case 0: break;
8266 default:
8267 as_bad (_("Invalid architecture variant -m%s"), arg);
8268 break;
8269 }
8270 break;
8271
8272 default:
8273 as_bad (_("Invalid architecture variant -m%s"), arg);
8274 break;
8275 }
8276 break;
8277
8278 default:
8279 bad:
8280 as_bad (_("Invalid processor variant -m%s"), arg);
8281 return 0;
8282 }
8283 }
8284 break;
8285
8286 #if defined OBJ_ELF || defined OBJ_COFF
8287 case 'k':
8288 pic_code = 1;
8289 break;
8290 #endif
8291
8292 default:
8293 return 0;
8294 }
8295
8296 return 1;
8297 }
8298
8299 void
8300 md_show_usage (fp)
8301 FILE * fp;
8302 {
8303 fprintf (fp, _("\
8304 ARM Specific Assembler Options:\n\
8305 -m[arm][<processor name>] select processor variant\n\
8306 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
8307 -mthumb only allow Thumb instructions\n\
8308 -mthumb-interwork mark the assembled code as supporting interworking\n\
8309 -mall allow any instruction\n\
8310 -mfpa10, -mfpa11 select floating point architecture\n\
8311 -mfpe-old don't allow floating-point multiple instructions\n\
8312 -mno-fpu don't allow any floating-point instructions.\n\
8313 -k generate PIC code.\n"));
8314 #if defined OBJ_COFF || defined OBJ_ELF
8315 fprintf (fp, _("\
8316 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
8317 -matpcs use ARM/Thumb Procedure Calling Standard\n\
8318 -mapcs-float floating point args are passed in FP regs\n\
8319 -mapcs-reentrant the code is position independent/reentrant\n"));
8320 #endif
8321 #ifdef OBJ_ELF
8322 fprintf (fp, _("\
8323 -moabi support the old ELF ABI\n"));
8324 #endif
8325 #ifdef ARM_BI_ENDIAN
8326 fprintf (fp, _("\
8327 -EB assemble code for a big endian cpu\n\
8328 -EL assemble code for a little endian cpu\n"));
8329 #endif
8330 }
8331
8332 /* We need to be able to fix up arbitrary expressions in some statements.
8333 This is so that we can handle symbols that are an arbitrary distance from
8334 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8335 which returns part of an address in a form which will be valid for
8336 a data instruction. We do this by pushing the expression into a symbol
8337 in the expr_section, and creating a fix for that. */
8338
8339 static void
8340 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
8341 fragS * frag;
8342 int where;
8343 short int size;
8344 expressionS * exp;
8345 int pc_rel;
8346 int reloc;
8347 {
8348 fixS * new_fix;
8349 arm_fix_data * arm_data;
8350
8351 switch (exp->X_op)
8352 {
8353 case O_constant:
8354 case O_symbol:
8355 case O_add:
8356 case O_subtract:
8357 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
8358 break;
8359
8360 default:
8361 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
8362 pc_rel, reloc);
8363 break;
8364 }
8365
8366 /* Mark whether the fix is to a THUMB instruction, or an ARM
8367 instruction. */
8368 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
8369 new_fix->tc_fix_data = (PTR) arm_data;
8370 arm_data->thumb_mode = thumb_mode;
8371
8372 return;
8373 }
8374
8375 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8376
8377 void
8378 cons_fix_new_arm (frag, where, size, exp)
8379 fragS * frag;
8380 int where;
8381 int size;
8382 expressionS * exp;
8383 {
8384 bfd_reloc_code_real_type type;
8385 int pcrel = 0;
8386
8387 /* Pick a reloc.
8388 FIXME: @@ Should look at CPU word size. */
8389 switch (size)
8390 {
8391 case 1:
8392 type = BFD_RELOC_8;
8393 break;
8394 case 2:
8395 type = BFD_RELOC_16;
8396 break;
8397 case 4:
8398 default:
8399 type = BFD_RELOC_32;
8400 break;
8401 case 8:
8402 type = BFD_RELOC_64;
8403 break;
8404 }
8405
8406 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
8407 }
8408
8409 /* A good place to do this, although this was probably not intended
8410 for this kind of use. We need to dump the literal pool before
8411 references are made to a null symbol pointer. */
8412
8413 void
8414 arm_cleanup ()
8415 {
8416 if (current_poolP == NULL)
8417 return;
8418
8419 /* Put it at the end of text section. */
8420 subseg_set (text_section, 0);
8421 s_ltorg (0);
8422 listing_prev_line ();
8423 }
8424
8425 void
8426 arm_start_line_hook ()
8427 {
8428 last_label_seen = NULL;
8429 }
8430
8431 void
8432 arm_frob_label (sym)
8433 symbolS * sym;
8434 {
8435 last_label_seen = sym;
8436
8437 ARM_SET_THUMB (sym, thumb_mode);
8438
8439 #if defined OBJ_COFF || defined OBJ_ELF
8440 ARM_SET_INTERWORK (sym, support_interwork);
8441 #endif
8442
8443 /* Note - do not allow local symbols (.Lxxx) to be labeled
8444 as Thumb functions. This is because these labels, whilst
8445 they exist inside Thumb code, are not the entry points for
8446 possible ARM->Thumb calls. Also, these labels can be used
8447 as part of a computed goto or switch statement. eg gcc
8448 can generate code that looks like this:
8449
8450 ldr r2, [pc, .Laaa]
8451 lsl r3, r3, #2
8452 ldr r2, [r3, r2]
8453 mov pc, r2
8454
8455 .Lbbb: .word .Lxxx
8456 .Lccc: .word .Lyyy
8457 ..etc...
8458 .Laaa: .word Lbbb
8459
8460 The first instruction loads the address of the jump table.
8461 The second instruction converts a table index into a byte offset.
8462 The third instruction gets the jump address out of the table.
8463 The fourth instruction performs the jump.
8464
8465 If the address stored at .Laaa is that of a symbol which has the
8466 Thumb_Func bit set, then the linker will arrange for this address
8467 to have the bottom bit set, which in turn would mean that the
8468 address computation performed by the third instruction would end
8469 up with the bottom bit set. Since the ARM is capable of unaligned
8470 word loads, the instruction would then load the incorrect address
8471 out of the jump table, and chaos would ensue. */
8472 if (label_is_thumb_function_name
8473 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8474 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8475 {
8476 /* When the address of a Thumb function is taken the bottom
8477 bit of that address should be set. This will allow
8478 interworking between Arm and Thumb functions to work
8479 correctly. */
8480
8481 THUMB_SET_FUNC (sym, 1);
8482
8483 label_is_thumb_function_name = false;
8484 }
8485 }
8486
8487 /* Adjust the symbol table. This marks Thumb symbols as distinct from
8488 ARM ones. */
8489
8490 void
8491 arm_adjust_symtab ()
8492 {
8493 #ifdef OBJ_COFF
8494 symbolS * sym;
8495
8496 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8497 {
8498 if (ARM_IS_THUMB (sym))
8499 {
8500 if (THUMB_IS_FUNC (sym))
8501 {
8502 /* Mark the symbol as a Thumb function. */
8503 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
8504 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
8505 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
8506
8507 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
8508 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
8509 else
8510 as_bad (_("%s: unexpected function type: %d"),
8511 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
8512 }
8513 else switch (S_GET_STORAGE_CLASS (sym))
8514 {
8515 case C_EXT:
8516 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
8517 break;
8518 case C_STAT:
8519 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
8520 break;
8521 case C_LABEL:
8522 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
8523 break;
8524 default:
8525 /* Do nothing. */
8526 break;
8527 }
8528 }
8529
8530 if (ARM_IS_INTERWORK (sym))
8531 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
8532 }
8533 #endif
8534 #ifdef OBJ_ELF
8535 symbolS * sym;
8536 char bind;
8537
8538 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8539 {
8540 if (ARM_IS_THUMB (sym))
8541 {
8542 elf_symbol_type * elf_sym;
8543
8544 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
8545 bind = ELF_ST_BIND (elf_sym);
8546
8547 /* If it's a .thumb_func, declare it as so,
8548 otherwise tag label as .code 16. */
8549 if (THUMB_IS_FUNC (sym))
8550 elf_sym->internal_elf_sym.st_info =
8551 ELF_ST_INFO (bind, STT_ARM_TFUNC);
8552 else
8553 elf_sym->internal_elf_sym.st_info =
8554 ELF_ST_INFO (bind, STT_ARM_16BIT);
8555 }
8556 }
8557 #endif
8558 }
8559
8560 int
8561 arm_data_in_code ()
8562 {
8563 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8564 {
8565 *input_line_pointer = '/';
8566 input_line_pointer += 5;
8567 *input_line_pointer = 0;
8568 return 1;
8569 }
8570
8571 return 0;
8572 }
8573
8574 char *
8575 arm_canonicalize_symbol_name (name)
8576 char * name;
8577 {
8578 int len;
8579
8580 if (thumb_mode && (len = strlen (name)) > 5
8581 && streq (name + len - 5, "/data"))
8582 *(name + len - 5) = 0;
8583
8584 return name;
8585 }
8586
8587 boolean
8588 arm_validate_fix (fixP)
8589 fixS * fixP;
8590 {
8591 /* If the destination of the branch is a defined symbol which does not have
8592 the THUMB_FUNC attribute, then we must be calling a function which has
8593 the (interfacearm) attribute. We look for the Thumb entry point to that
8594 function and change the branch to refer to that function instead. */
8595 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
8596 && fixP->fx_addsy != NULL
8597 && S_IS_DEFINED (fixP->fx_addsy)
8598 && ! THUMB_IS_FUNC (fixP->fx_addsy))
8599 {
8600 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
8601 return true;
8602 }
8603
8604 return false;
8605 }
8606
8607 #ifdef OBJ_COFF
8608 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
8609 local labels from being added to the output symbol table when they
8610 are used with the ADRL pseudo op. The ADRL relocation should always
8611 be resolved before the binbary is emitted, so it is safe to say that
8612 it is adjustable. */
8613
8614 boolean
8615 arm_fix_adjustable (fixP)
8616 fixS * fixP;
8617 {
8618 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
8619 return 1;
8620 return 0;
8621 }
8622 #endif
8623 #ifdef OBJ_ELF
8624 /* Relocations against Thumb function names must be left unadjusted,
8625 so that the linker can use this information to correctly set the
8626 bottom bit of their addresses. The MIPS version of this function
8627 also prevents relocations that are mips-16 specific, but I do not
8628 know why it does this.
8629
8630 FIXME:
8631 There is one other problem that ought to be addressed here, but
8632 which currently is not: Taking the address of a label (rather
8633 than a function) and then later jumping to that address. Such
8634 addresses also ought to have their bottom bit set (assuming that
8635 they reside in Thumb code), but at the moment they will not. */
8636
8637 boolean
8638 arm_fix_adjustable (fixP)
8639 fixS * fixP;
8640 {
8641 if (fixP->fx_addsy == NULL)
8642 return 1;
8643
8644 /* Prevent all adjustments to global symbols. */
8645 if (S_IS_EXTERN (fixP->fx_addsy))
8646 return 0;
8647
8648 if (S_IS_WEAK (fixP->fx_addsy))
8649 return 0;
8650
8651 if (THUMB_IS_FUNC (fixP->fx_addsy)
8652 && fixP->fx_subsy == NULL)
8653 return 0;
8654
8655 /* We need the symbol name for the VTABLE entries. */
8656 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8657 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8658 return 0;
8659
8660 return 1;
8661 }
8662
8663 const char *
8664 elf32_arm_target_format ()
8665 {
8666 if (target_big_endian)
8667 {
8668 if (target_oabi)
8669 return "elf32-bigarm-oabi";
8670 else
8671 return "elf32-bigarm";
8672 }
8673 else
8674 {
8675 if (target_oabi)
8676 return "elf32-littlearm-oabi";
8677 else
8678 return "elf32-littlearm";
8679 }
8680 }
8681
8682 void
8683 armelf_frob_symbol (symp, puntp)
8684 symbolS * symp;
8685 int * puntp;
8686 {
8687 elf_frob_symbol (symp, puntp);
8688 }
8689
8690 int
8691 arm_force_relocation (fixp)
8692 struct fix * fixp;
8693 {
8694 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8695 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
8696 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
8697 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
8698 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
8699 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
8700 return 1;
8701
8702 return 0;
8703 }
8704
8705 static bfd_reloc_code_real_type
8706 arm_parse_reloc ()
8707 {
8708 char id [16];
8709 char * ip;
8710 unsigned int i;
8711 static struct
8712 {
8713 char * str;
8714 int len;
8715 bfd_reloc_code_real_type reloc;
8716 }
8717 reloc_map[] =
8718 {
8719 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
8720 MAP ("(got)", BFD_RELOC_ARM_GOT32),
8721 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
8722 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
8723 branch instructions generated by GCC for PLT relocs. */
8724 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
8725 { NULL, 0, BFD_RELOC_UNUSED }
8726 #undef MAP
8727 };
8728
8729 for (i = 0, ip = input_line_pointer;
8730 i < sizeof (id) && (ISALNUM (*ip) || ISPUNCT (*ip));
8731 i++, ip++)
8732 id[i] = TOLOWER (*ip);
8733
8734 for (i = 0; reloc_map[i].str; i++)
8735 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
8736 break;
8737
8738 input_line_pointer += reloc_map[i].len;
8739
8740 return reloc_map[i].reloc;
8741 }
8742
8743 static void
8744 s_arm_elf_cons (nbytes)
8745 int nbytes;
8746 {
8747 expressionS exp;
8748
8749 #ifdef md_flush_pending_output
8750 md_flush_pending_output ();
8751 #endif
8752
8753 if (is_it_end_of_statement ())
8754 {
8755 demand_empty_rest_of_line ();
8756 return;
8757 }
8758
8759 #ifdef md_cons_align
8760 md_cons_align (nbytes);
8761 #endif
8762
8763 do
8764 {
8765 bfd_reloc_code_real_type reloc;
8766
8767 expression (& exp);
8768
8769 if (exp.X_op == O_symbol
8770 && * input_line_pointer == '('
8771 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
8772 {
8773 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
8774 int size = bfd_get_reloc_size (howto);
8775
8776 if (size > nbytes)
8777 as_bad ("%s relocations do not fit in %d bytes",
8778 howto->name, nbytes);
8779 else
8780 {
8781 register char *p = frag_more ((int) nbytes);
8782 int offset = nbytes - size;
8783
8784 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8785 &exp, 0, reloc);
8786 }
8787 }
8788 else
8789 emit_expr (&exp, (unsigned int) nbytes);
8790 }
8791 while (*input_line_pointer++ == ',');
8792
8793 /* Put terminator back into stream. */
8794 input_line_pointer --;
8795 demand_empty_rest_of_line ();
8796 }
8797
8798 #endif /* OBJ_ELF */
8799
8800 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8801 of an rs_align_code fragment. */
8802
8803 void
8804 arm_handle_align (fragP)
8805 fragS *fragP;
8806 {
8807 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
8808 static char const thumb_noop[2] = { 0xc0, 0x46 };
8809 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
8810 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
8811
8812 int bytes, fix, noop_size;
8813 char * p;
8814 const char * noop;
8815
8816 if (fragP->fr_type != rs_align_code)
8817 return;
8818
8819 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
8820 p = fragP->fr_literal + fragP->fr_fix;
8821 fix = 0;
8822
8823 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
8824 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
8825
8826 if (fragP->tc_frag_data)
8827 {
8828 if (target_big_endian)
8829 noop = thumb_bigend_noop;
8830 else
8831 noop = thumb_noop;
8832 noop_size = sizeof (thumb_noop);
8833 }
8834 else
8835 {
8836 if (target_big_endian)
8837 noop = arm_bigend_noop;
8838 else
8839 noop = arm_noop;
8840 noop_size = sizeof (arm_noop);
8841 }
8842
8843 if (bytes & (noop_size - 1))
8844 {
8845 fix = bytes & (noop_size - 1);
8846 memset (p, 0, fix);
8847 p += fix;
8848 bytes -= fix;
8849 }
8850
8851 while (bytes >= noop_size)
8852 {
8853 memcpy (p, noop, noop_size);
8854 p += noop_size;
8855 bytes -= noop_size;
8856 fix += noop_size;
8857 }
8858
8859 fragP->fr_fix += fix;
8860 fragP->fr_var = noop_size;
8861 }
8862
8863 /* Called from md_do_align. Used to create an alignment
8864 frag in a code section. */
8865
8866 void
8867 arm_frag_align_code (n, max)
8868 int n;
8869 int max;
8870 {
8871 char * p;
8872
8873 /* We assume that there will never be a requirment
8874 to support alignments greater than 32 bytes. */
8875 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
8876 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
8877
8878 p = frag_var (rs_align_code,
8879 MAX_MEM_FOR_RS_ALIGN_CODE,
8880 1,
8881 (relax_substateT) max,
8882 (symbolS *) NULL,
8883 (offsetT) n,
8884 (char *) NULL);
8885 *p = 0;
8886
8887 }
8888
8889 /* Perform target specific initialisation of a frag. */
8890
8891 void
8892 arm_init_frag (fragP)
8893 fragS *fragP;
8894 {
8895 /* Record whether this frag is in an ARM or a THUMB area. */
8896 fragP->tc_frag_data = thumb_mode;
8897 }
GDB Binutils - Deliverables
This page took 0.199697 seconds and 3 git commands to generate.