1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 namelen
= nameend
- newname
;
2307 namebuf
= (char *) alloca (namelen
+ 1);
2308 strncpy (namebuf
, newname
, namelen
);
2309 namebuf
[namelen
] = '\0';
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all uppercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Insert name in all lowercase. */
2323 for (p
= namebuf
; *p
; p
++)
2326 if (strncmp (namebuf
, newname
, namelen
))
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2333 /* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
2337 s_req (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .req directive"));
2343 s_dn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .dn directive"));
2349 s_qn (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .qn directive"));
2354 /* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
2361 s_unreq (int a ATTRIBUTE_UNUSED
)
2366 name
= input_line_pointer
;
2368 while (*input_line_pointer
!= 0
2369 && *input_line_pointer
!= ' '
2370 && *input_line_pointer
!= '\n')
2371 ++input_line_pointer
;
2373 saved_char
= *input_line_pointer
;
2374 *input_line_pointer
= 0;
2377 as_bad (_("invalid syntax for .unreq directive"));
2380 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2384 as_bad (_("unknown register alias '%s'"), name
);
2385 else if (reg
->builtin
)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2393 hash_delete (arm_reg_hsh
, name
, FALSE
);
2394 free ((char *) reg
->name
);
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
2403 nbuf
= strdup (name
);
2404 for (p
= nbuf
; *p
; p
++)
2406 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2409 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2410 free ((char *) reg
->name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2432 *input_line_pointer
= saved_char
;
2433 demand_empty_rest_of_line ();
2436 /* Directives: Instruction set selection. */
2439 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2444 /* Create a new mapping symbol for the transition to STATE. */
2447 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2450 const char * symname
;
2457 type
= BSF_NO_FLAGS
;
2461 type
= BSF_NO_FLAGS
;
2465 type
= BSF_NO_FLAGS
;
2471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2477 THUMB_SET_FUNC (symbolP
, 0);
2478 ARM_SET_THUMB (symbolP
, 0);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2483 THUMB_SET_FUNC (symbolP
, 1);
2484 ARM_SET_THUMB (symbolP
, 1);
2485 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2496 check_mapping_symbols.
2498 If .fill or other data filling directive generates zero sized data,
2499 the mapping symbol for the following code will have the same value
2500 as the one generated for the data filling directive. In this case,
2501 we replace the old symbol with the new one at the same address. */
2504 if (frag
->tc_frag_data
.first_map
!= NULL
)
2506 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2507 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2509 frag
->tc_frag_data
.first_map
= symbolP
;
2511 if (frag
->tc_frag_data
.last_map
!= NULL
)
2513 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2514 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2515 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2517 frag
->tc_frag_data
.last_map
= symbolP
;
2520 /* We must sometimes convert a region marked as code to data during
2521 code alignment, if an odd number of bytes have to be padded. The
2522 code mapping symbol is pushed to an aligned address. */
2525 insert_data_mapping_symbol (enum mstate state
,
2526 valueT value
, fragS
*frag
, offsetT bytes
)
2528 /* If there was already a mapping symbol, remove it. */
2529 if (frag
->tc_frag_data
.last_map
!= NULL
2530 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2532 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2536 know (frag
->tc_frag_data
.first_map
== symp
);
2537 frag
->tc_frag_data
.first_map
= NULL
;
2539 frag
->tc_frag_data
.last_map
= NULL
;
2540 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2543 make_mapping_symbol (MAP_DATA
, value
, frag
);
2544 make_mapping_symbol (state
, value
+ bytes
, frag
);
2547 static void mapping_state_2 (enum mstate state
, int max_chars
);
2549 /* Set the mapping state to STATE. Only call this when about to
2550 emit some STATE bytes to the file. */
2553 mapping_state (enum mstate state
)
2555 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2557 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2559 if (mapstate
== state
)
2560 /* The mapping symbol has already been emitted.
2561 There is nothing else to do. */
2563 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2564 /* This case will be evaluated later in the next else. */
2566 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2567 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2569 /* Only add the symbol if the offset is > 0:
2570 if we're at the first frag, check it's size > 0;
2571 if we're not at the first frag, then for sure
2572 the offset is > 0. */
2573 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2574 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2577 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2580 mapping_state_2 (state
, 0);
2584 /* Same as mapping_state, but MAX_CHARS bytes have already been
2585 allocated. Put the mapping symbol that far back. */
2588 mapping_state_2 (enum mstate state
, int max_chars
)
2590 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2592 if (!SEG_NORMAL (now_seg
))
2595 if (mapstate
== state
)
2596 /* The mapping symbol has already been emitted.
2597 There is nothing else to do. */
2600 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2601 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2604 #define mapping_state(x) ((void)0)
2605 #define mapping_state_2(x, y) ((void)0)
2608 /* Find the real, Thumb encoded start of a Thumb function. */
2612 find_real_start (symbolS
* symbolP
)
2615 const char * name
= S_GET_NAME (symbolP
);
2616 symbolS
* new_target
;
2618 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2619 #define STUB_NAME ".real_start_of"
2624 /* The compiler may generate BL instructions to local labels because
2625 it needs to perform a branch to a far away location. These labels
2626 do not have a corresponding ".real_start_of" label. We check
2627 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2628 the ".real_start_of" convention for nonlocal branches. */
2629 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2632 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2633 new_target
= symbol_find (real_start
);
2635 if (new_target
== NULL
)
2637 as_warn (_("Failed to find real start of function: %s\n"), name
);
2638 new_target
= symbolP
;
2646 opcode_select (int width
)
2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2654 as_bad (_("selected processor does not support THUMB opcodes"));
2657 /* No need to force the alignment, since we will have been
2658 coming from ARM mode, which is word-aligned. */
2659 record_alignment (now_seg
, 1);
2666 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2667 as_bad (_("selected processor does not support ARM opcodes"));
2672 frag_align (2, 0, 0);
2674 record_alignment (now_seg
, 1);
2679 as_bad (_("invalid instruction size selected (%d)"), width
);
2684 s_arm (int ignore ATTRIBUTE_UNUSED
)
2687 demand_empty_rest_of_line ();
2691 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2694 demand_empty_rest_of_line ();
2698 s_code (int unused ATTRIBUTE_UNUSED
)
2702 temp
= get_absolute_expression ();
2707 opcode_select (temp
);
2711 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2716 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2718 /* If we are not already in thumb mode go into it, EVEN if
2719 the target processor does not support thumb instructions.
2720 This is used by gcc/config/arm/lib1funcs.asm for example
2721 to compile interworking support functions even if the
2722 target processor should not support interworking. */
2726 record_alignment (now_seg
, 1);
2729 demand_empty_rest_of_line ();
2733 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2737 /* The following label is the name/address of the start of a Thumb function.
2738 We need to know this for the interworking support. */
2739 label_is_thumb_function_name
= TRUE
;
2742 /* Perform a .set directive, but also mark the alias as
2743 being a thumb function. */
2746 s_thumb_set (int equiv
)
2748 /* XXX the following is a duplicate of the code for s_set() in read.c
2749 We cannot just call that code as we need to get at the symbol that
2756 /* Especial apologies for the random logic:
2757 This just grew, and could be parsed much more simply!
2759 name
= input_line_pointer
;
2760 delim
= get_symbol_end ();
2761 end_name
= input_line_pointer
;
2764 if (*input_line_pointer
!= ',')
2767 as_bad (_("expected comma after name \"%s\""), name
);
2769 ignore_rest_of_line ();
2773 input_line_pointer
++;
2776 if (name
[0] == '.' && name
[1] == '\0')
2778 /* XXX - this should not happen to .thumb_set. */
2782 if ((symbolP
= symbol_find (name
)) == NULL
2783 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2786 /* When doing symbol listings, play games with dummy fragments living
2787 outside the normal fragment chain to record the file and line info
2789 if (listing
& LISTING_SYMBOLS
)
2791 extern struct list_info_struct
* listing_tail
;
2792 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2794 memset (dummy_frag
, 0, sizeof (fragS
));
2795 dummy_frag
->fr_type
= rs_fill
;
2796 dummy_frag
->line
= listing_tail
;
2797 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2798 dummy_frag
->fr_symbol
= symbolP
;
2802 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2805 /* "set" symbols are local unless otherwise specified. */
2806 SF_SET_LOCAL (symbolP
);
2807 #endif /* OBJ_COFF */
2808 } /* Make a new symbol. */
2810 symbol_table_insert (symbolP
);
2815 && S_IS_DEFINED (symbolP
)
2816 && S_GET_SEGMENT (symbolP
) != reg_section
)
2817 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2819 pseudo_set (symbolP
);
2821 demand_empty_rest_of_line ();
2823 /* XXX Now we come to the Thumb specific bit of code. */
2825 THUMB_SET_FUNC (symbolP
, 1);
2826 ARM_SET_THUMB (symbolP
, 1);
2827 #if defined OBJ_ELF || defined OBJ_COFF
2828 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2832 /* Directives: Mode selection. */
2834 /* .syntax [unified|divided] - choose the new unified syntax
2835 (same for Arm and Thumb encoding, modulo slight differences in what
2836 can be represented) or the old divergent syntax for each mode. */
2838 s_syntax (int unused ATTRIBUTE_UNUSED
)
2842 name
= input_line_pointer
;
2843 delim
= get_symbol_end ();
2845 if (!strcasecmp (name
, "unified"))
2846 unified_syntax
= TRUE
;
2847 else if (!strcasecmp (name
, "divided"))
2848 unified_syntax
= FALSE
;
2851 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2854 *input_line_pointer
= delim
;
2855 demand_empty_rest_of_line ();
2858 /* Directives: sectioning and alignment. */
2860 /* Same as s_align_ptwo but align 0 => align 2. */
2863 s_align (int unused ATTRIBUTE_UNUSED
)
2868 long max_alignment
= 15;
2870 temp
= get_absolute_expression ();
2871 if (temp
> max_alignment
)
2872 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2875 as_bad (_("alignment negative. 0 assumed."));
2879 if (*input_line_pointer
== ',')
2881 input_line_pointer
++;
2882 temp_fill
= get_absolute_expression ();
2894 /* Only make a frag if we HAVE to. */
2895 if (temp
&& !need_pass_2
)
2897 if (!fill_p
&& subseg_text_p (now_seg
))
2898 frag_align_code (temp
, 0);
2900 frag_align (temp
, (int) temp_fill
, 0);
2902 demand_empty_rest_of_line ();
2904 record_alignment (now_seg
, temp
);
2908 s_bss (int ignore ATTRIBUTE_UNUSED
)
2910 /* We don't support putting frags in the BSS segment, we fake it by
2911 marking in_bss, then looking at s_skip for clues. */
2912 subseg_set (bss_section
, 0);
2913 demand_empty_rest_of_line ();
2915 #ifdef md_elf_section_change_hook
2916 md_elf_section_change_hook ();
2921 s_even (int ignore ATTRIBUTE_UNUSED
)
2923 /* Never make frag if expect extra pass. */
2925 frag_align (1, 0, 0);
2927 record_alignment (now_seg
, 1);
2929 demand_empty_rest_of_line ();
2932 /* Directives: Literal pools. */
2934 static literal_pool
*
2935 find_literal_pool (void)
2937 literal_pool
* pool
;
2939 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2941 if (pool
->section
== now_seg
2942 && pool
->sub_section
== now_subseg
)
2949 static literal_pool
*
2950 find_or_make_literal_pool (void)
2952 /* Next literal pool ID number. */
2953 static unsigned int latest_pool_num
= 1;
2954 literal_pool
* pool
;
2956 pool
= find_literal_pool ();
2960 /* Create a new pool. */
2961 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2965 pool
->next_free_entry
= 0;
2966 pool
->section
= now_seg
;
2967 pool
->sub_section
= now_subseg
;
2968 pool
->next
= list_of_pools
;
2969 pool
->symbol
= NULL
;
2971 /* Add it to the list. */
2972 list_of_pools
= pool
;
2975 /* New pools, and emptied pools, will have a NULL symbol. */
2976 if (pool
->symbol
== NULL
)
2978 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2979 (valueT
) 0, &zero_address_frag
);
2980 pool
->id
= latest_pool_num
++;
2987 /* Add the literal in the global 'inst'
2988 structure to the relevant literal pool. */
2991 add_to_lit_pool (void)
2993 literal_pool
* pool
;
2996 pool
= find_or_make_literal_pool ();
2998 /* Check if this literal value is already in the pool. */
2999 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3001 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3002 && (inst
.reloc
.exp
.X_op
== O_constant
)
3003 && (pool
->literals
[entry
].X_add_number
3004 == inst
.reloc
.exp
.X_add_number
)
3005 && (pool
->literals
[entry
].X_unsigned
3006 == inst
.reloc
.exp
.X_unsigned
))
3009 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3010 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3011 && (pool
->literals
[entry
].X_add_number
3012 == inst
.reloc
.exp
.X_add_number
)
3013 && (pool
->literals
[entry
].X_add_symbol
3014 == inst
.reloc
.exp
.X_add_symbol
)
3015 && (pool
->literals
[entry
].X_op_symbol
3016 == inst
.reloc
.exp
.X_op_symbol
))
3020 /* Do we need to create a new entry? */
3021 if (entry
== pool
->next_free_entry
)
3023 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3025 inst
.error
= _("literal pool overflow");
3029 pool
->literals
[entry
] = inst
.reloc
.exp
;
3030 pool
->next_free_entry
+= 1;
3033 inst
.reloc
.exp
.X_op
= O_symbol
;
3034 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3035 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3040 /* Can't use symbol_new here, so have to create a symbol and then at
3041 a later date assign it a value. Thats what these functions do. */
3044 symbol_locate (symbolS
* symbolP
,
3045 const char * name
, /* It is copied, the caller can modify. */
3046 segT segment
, /* Segment identifier (SEG_<something>). */
3047 valueT valu
, /* Symbol value. */
3048 fragS
* frag
) /* Associated fragment. */
3050 unsigned int name_length
;
3051 char * preserved_copy_of_name
;
3053 name_length
= strlen (name
) + 1; /* +1 for \0. */
3054 obstack_grow (¬es
, name
, name_length
);
3055 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3057 #ifdef tc_canonicalize_symbol_name
3058 preserved_copy_of_name
=
3059 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3062 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3064 S_SET_SEGMENT (symbolP
, segment
);
3065 S_SET_VALUE (symbolP
, valu
);
3066 symbol_clear_list_pointers (symbolP
);
3068 symbol_set_frag (symbolP
, frag
);
3070 /* Link to end of symbol chain. */
3072 extern int symbol_table_frozen
;
3074 if (symbol_table_frozen
)
3078 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3080 obj_symbol_new_hook (symbolP
);
3082 #ifdef tc_symbol_new_hook
3083 tc_symbol_new_hook (symbolP
);
3087 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3088 #endif /* DEBUG_SYMS */
3093 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3096 literal_pool
* pool
;
3099 pool
= find_literal_pool ();
3101 || pool
->symbol
== NULL
3102 || pool
->next_free_entry
== 0)
3105 mapping_state (MAP_DATA
);
3107 /* Align pool as you have word accesses.
3108 Only make a frag if we have to. */
3110 frag_align (2, 0, 0);
3112 record_alignment (now_seg
, 2);
3114 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3116 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3117 (valueT
) frag_now_fix (), frag_now
);
3118 symbol_table_insert (pool
->symbol
);
3120 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3122 #if defined OBJ_COFF || defined OBJ_ELF
3123 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3126 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3127 /* First output the expression in the instruction to the pool. */
3128 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3130 /* Mark the pool as empty. */
3131 pool
->next_free_entry
= 0;
3132 pool
->symbol
= NULL
;
3136 /* Forward declarations for functions below, in the MD interface
3138 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3139 static valueT
create_unwind_entry (int);
3140 static void start_unwind_section (const segT
, int);
3141 static void add_unwind_opcode (valueT
, int);
3142 static void flush_pending_unwind (void);
3144 /* Directives: Data. */
3147 s_arm_elf_cons (int nbytes
)
3151 #ifdef md_flush_pending_output
3152 md_flush_pending_output ();
3155 if (is_it_end_of_statement ())
3157 demand_empty_rest_of_line ();
3161 #ifdef md_cons_align
3162 md_cons_align (nbytes
);
3165 mapping_state (MAP_DATA
);
3169 char *base
= input_line_pointer
;
3173 if (exp
.X_op
!= O_symbol
)
3174 emit_expr (&exp
, (unsigned int) nbytes
);
3177 char *before_reloc
= input_line_pointer
;
3178 reloc
= parse_reloc (&input_line_pointer
);
3181 as_bad (_("unrecognized relocation suffix"));
3182 ignore_rest_of_line ();
3185 else if (reloc
== BFD_RELOC_UNUSED
)
3186 emit_expr (&exp
, (unsigned int) nbytes
);
3189 reloc_howto_type
*howto
= (reloc_howto_type
*)
3190 bfd_reloc_type_lookup (stdoutput
,
3191 (bfd_reloc_code_real_type
) reloc
);
3192 int size
= bfd_get_reloc_size (howto
);
3194 if (reloc
== BFD_RELOC_ARM_PLT32
)
3196 as_bad (_("(plt) is only valid on branch targets"));
3197 reloc
= BFD_RELOC_UNUSED
;
3202 as_bad (_("%s relocations do not fit in %d bytes"),
3203 howto
->name
, nbytes
);
3206 /* We've parsed an expression stopping at O_symbol.
3207 But there may be more expression left now that we
3208 have parsed the relocation marker. Parse it again.
3209 XXX Surely there is a cleaner way to do this. */
3210 char *p
= input_line_pointer
;
3212 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3213 memcpy (save_buf
, base
, input_line_pointer
- base
);
3214 memmove (base
+ (input_line_pointer
- before_reloc
),
3215 base
, before_reloc
- base
);
3217 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3219 memcpy (base
, save_buf
, p
- base
);
3221 offset
= nbytes
- size
;
3222 p
= frag_more ((int) nbytes
);
3223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3224 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3229 while (*input_line_pointer
++ == ',');
3231 /* Put terminator back into stream. */
3232 input_line_pointer
--;
3233 demand_empty_rest_of_line ();
3236 /* Emit an expression containing a 32-bit thumb instruction.
3237 Implementation based on put_thumb32_insn. */
3240 emit_thumb32_expr (expressionS
* exp
)
3242 expressionS exp_high
= *exp
;
3244 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3245 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3246 exp
->X_add_number
&= 0xffff;
3247 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3250 /* Guess the instruction size based on the opcode. */
3253 thumb_insn_size (int opcode
)
3255 if ((unsigned int) opcode
< 0xe800u
)
3257 else if ((unsigned int) opcode
>= 0xe8000000u
)
3264 emit_insn (expressionS
*exp
, int nbytes
)
3268 if (exp
->X_op
== O_constant
)
3273 size
= thumb_insn_size (exp
->X_add_number
);
3277 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3279 as_bad (_(".inst.n operand too big. "\
3280 "Use .inst.w instead"));
3285 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3286 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3288 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3290 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3291 emit_thumb32_expr (exp
);
3293 emit_expr (exp
, (unsigned int) size
);
3295 it_fsm_post_encode ();
3299 as_bad (_("cannot determine Thumb instruction size. " \
3300 "Use .inst.n/.inst.w instead"));
3303 as_bad (_("constant expression required"));
3308 /* Like s_arm_elf_cons but do not use md_cons_align and
3309 set the mapping state to MAP_ARM/MAP_THUMB. */
3312 s_arm_elf_inst (int nbytes
)
3314 if (is_it_end_of_statement ())
3316 demand_empty_rest_of_line ();
3320 /* Calling mapping_state () here will not change ARM/THUMB,
3321 but will ensure not to be in DATA state. */
3324 mapping_state (MAP_THUMB
);
3329 as_bad (_("width suffixes are invalid in ARM mode"));
3330 ignore_rest_of_line ();
3336 mapping_state (MAP_ARM
);
3345 if (! emit_insn (& exp
, nbytes
))
3347 ignore_rest_of_line ();
3351 while (*input_line_pointer
++ == ',');
3353 /* Put terminator back into stream. */
3354 input_line_pointer
--;
3355 demand_empty_rest_of_line ();
3358 /* Parse a .rel31 directive. */
3361 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3368 if (*input_line_pointer
== '1')
3369 highbit
= 0x80000000;
3370 else if (*input_line_pointer
!= '0')
3371 as_bad (_("expected 0 or 1"));
3373 input_line_pointer
++;
3374 if (*input_line_pointer
!= ',')
3375 as_bad (_("missing comma"));
3376 input_line_pointer
++;
3378 #ifdef md_flush_pending_output
3379 md_flush_pending_output ();
3382 #ifdef md_cons_align
3386 mapping_state (MAP_DATA
);
3391 md_number_to_chars (p
, highbit
, 4);
3392 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3393 BFD_RELOC_ARM_PREL31
);
3395 demand_empty_rest_of_line ();
3398 /* Directives: AEABI stack-unwind tables. */
3400 /* Parse an unwind_fnstart directive. Simply records the current location. */
3403 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3405 demand_empty_rest_of_line ();
3406 if (unwind
.proc_start
)
3408 as_bad (_("duplicate .fnstart directive"));
3412 /* Mark the start of the function. */
3413 unwind
.proc_start
= expr_build_dot ();
3415 /* Reset the rest of the unwind info. */
3416 unwind
.opcode_count
= 0;
3417 unwind
.table_entry
= NULL
;
3418 unwind
.personality_routine
= NULL
;
3419 unwind
.personality_index
= -1;
3420 unwind
.frame_size
= 0;
3421 unwind
.fp_offset
= 0;
3422 unwind
.fp_reg
= REG_SP
;
3424 unwind
.sp_restored
= 0;
3428 /* Parse a handlerdata directive. Creates the exception handling table entry
3429 for the function. */
3432 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3436 as_bad (MISSING_FNSTART
);
3438 if (unwind
.table_entry
)
3439 as_bad (_("duplicate .handlerdata directive"));
3441 create_unwind_entry (1);
3444 /* Parse an unwind_fnend directive. Generates the index table entry. */
3447 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3452 unsigned int marked_pr_dependency
;
3454 demand_empty_rest_of_line ();
3456 if (!unwind
.proc_start
)
3458 as_bad (_(".fnend directive without .fnstart"));
3462 /* Add eh table entry. */
3463 if (unwind
.table_entry
== NULL
)
3464 val
= create_unwind_entry (0);
3468 /* Add index table entry. This is two words. */
3469 start_unwind_section (unwind
.saved_seg
, 1);
3470 frag_align (2, 0, 0);
3471 record_alignment (now_seg
, 2);
3473 ptr
= frag_more (8);
3474 where
= frag_now_fix () - 8;
3476 /* Self relative offset of the function start. */
3477 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3478 BFD_RELOC_ARM_PREL31
);
3480 /* Indicate dependency on EHABI-defined personality routines to the
3481 linker, if it hasn't been done already. */
3482 marked_pr_dependency
3483 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3484 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3485 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3487 static const char *const name
[] =
3489 "__aeabi_unwind_cpp_pr0",
3490 "__aeabi_unwind_cpp_pr1",
3491 "__aeabi_unwind_cpp_pr2"
3493 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3494 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3495 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3496 |= 1 << unwind
.personality_index
;
3500 /* Inline exception table entry. */
3501 md_number_to_chars (ptr
+ 4, val
, 4);
3503 /* Self relative offset of the table entry. */
3504 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3505 BFD_RELOC_ARM_PREL31
);
3507 /* Restore the original section. */
3508 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3510 unwind
.proc_start
= NULL
;
3514 /* Parse an unwind_cantunwind directive. */
3517 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3519 demand_empty_rest_of_line ();
3520 if (!unwind
.proc_start
)
3521 as_bad (MISSING_FNSTART
);
3523 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3524 as_bad (_("personality routine specified for cantunwind frame"));
3526 unwind
.personality_index
= -2;
3530 /* Parse a personalityindex directive. */
3533 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3537 if (!unwind
.proc_start
)
3538 as_bad (MISSING_FNSTART
);
3540 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3541 as_bad (_("duplicate .personalityindex directive"));
3545 if (exp
.X_op
!= O_constant
3546 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3548 as_bad (_("bad personality routine number"));
3549 ignore_rest_of_line ();
3553 unwind
.personality_index
= exp
.X_add_number
;
3555 demand_empty_rest_of_line ();
3559 /* Parse a personality directive. */
3562 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personality directive"));
3572 name
= input_line_pointer
;
3573 c
= get_symbol_end ();
3574 p
= input_line_pointer
;
3575 unwind
.personality_routine
= symbol_find_or_make (name
);
3577 demand_empty_rest_of_line ();
3581 /* Parse a directive saving core registers. */
3584 s_arm_unwind_save_core (void)
3590 range
= parse_reg_list (&input_line_pointer
);
3593 as_bad (_("expected register list"));
3594 ignore_rest_of_line ();
3598 demand_empty_rest_of_line ();
3600 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3601 into .unwind_save {..., sp...}. We aren't bothered about the value of
3602 ip because it is clobbered by calls. */
3603 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3604 && (range
& 0x3000) == 0x1000)
3606 unwind
.opcode_count
--;
3607 unwind
.sp_restored
= 0;
3608 range
= (range
| 0x2000) & ~0x1000;
3609 unwind
.pending_offset
= 0;
3615 /* See if we can use the short opcodes. These pop a block of up to 8
3616 registers starting with r4, plus maybe r14. */
3617 for (n
= 0; n
< 8; n
++)
3619 /* Break at the first non-saved register. */
3620 if ((range
& (1 << (n
+ 4))) == 0)
3623 /* See if there are any other bits set. */
3624 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3626 /* Use the long form. */
3627 op
= 0x8000 | ((range
>> 4) & 0xfff);
3628 add_unwind_opcode (op
, 2);
3632 /* Use the short form. */
3634 op
= 0xa8; /* Pop r14. */
3636 op
= 0xa0; /* Do not pop r14. */
3638 add_unwind_opcode (op
, 1);
3645 op
= 0xb100 | (range
& 0xf);
3646 add_unwind_opcode (op
, 2);
3649 /* Record the number of bytes pushed. */
3650 for (n
= 0; n
< 16; n
++)
3652 if (range
& (1 << n
))
3653 unwind
.frame_size
+= 4;
3658 /* Parse a directive saving FPA registers. */
3661 s_arm_unwind_save_fpa (int reg
)
3667 /* Get Number of registers to transfer. */
3668 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3671 exp
.X_op
= O_illegal
;
3673 if (exp
.X_op
!= O_constant
)
3675 as_bad (_("expected , <constant>"));
3676 ignore_rest_of_line ();
3680 num_regs
= exp
.X_add_number
;
3682 if (num_regs
< 1 || num_regs
> 4)
3684 as_bad (_("number of registers must be in the range [1:4]"));
3685 ignore_rest_of_line ();
3689 demand_empty_rest_of_line ();
3694 op
= 0xb4 | (num_regs
- 1);
3695 add_unwind_opcode (op
, 1);
3700 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3701 add_unwind_opcode (op
, 2);
3703 unwind
.frame_size
+= num_regs
* 12;
3707 /* Parse a directive saving VFP registers for ARMv6 and above. */
3710 s_arm_unwind_save_vfp_armv6 (void)
3715 int num_vfpv3_regs
= 0;
3716 int num_regs_below_16
;
3718 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3721 as_bad (_("expected register list"));
3722 ignore_rest_of_line ();
3726 demand_empty_rest_of_line ();
3728 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3729 than FSTMX/FLDMX-style ones). */
3731 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3733 num_vfpv3_regs
= count
;
3734 else if (start
+ count
> 16)
3735 num_vfpv3_regs
= start
+ count
- 16;
3737 if (num_vfpv3_regs
> 0)
3739 int start_offset
= start
> 16 ? start
- 16 : 0;
3740 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3741 add_unwind_opcode (op
, 2);
3744 /* Generate opcode for registers numbered in the range 0 .. 15. */
3745 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3746 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3747 if (num_regs_below_16
> 0)
3749 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3750 add_unwind_opcode (op
, 2);
3753 unwind
.frame_size
+= count
* 8;
3757 /* Parse a directive saving VFP registers for pre-ARMv6. */
3760 s_arm_unwind_save_vfp (void)
3766 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3769 as_bad (_("expected register list"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op
= 0xb8 | (count
- 1);
3780 add_unwind_opcode (op
, 1);
3785 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3786 add_unwind_opcode (op
, 2);
3788 unwind
.frame_size
+= count
* 8 + 4;
3792 /* Parse a directive saving iWMMXt data registers. */
3795 s_arm_unwind_save_mmxwr (void)
3803 if (*input_line_pointer
== '{')
3804 input_line_pointer
++;
3808 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3812 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3817 as_tsktsk (_("register list not in ascending order"));
3820 if (*input_line_pointer
== '-')
3822 input_line_pointer
++;
3823 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3826 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3829 else if (reg
>= hi_reg
)
3831 as_bad (_("bad register range"));
3834 for (; reg
< hi_reg
; reg
++)
3838 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3840 if (*input_line_pointer
== '}')
3841 input_line_pointer
++;
3843 demand_empty_rest_of_line ();
3845 /* Generate any deferred opcodes because we're going to be looking at
3847 flush_pending_unwind ();
3849 for (i
= 0; i
< 16; i
++)
3851 if (mask
& (1 << i
))
3852 unwind
.frame_size
+= 8;
3855 /* Attempt to combine with a previous opcode. We do this because gcc
3856 likes to output separate unwind directives for a single block of
3858 if (unwind
.opcode_count
> 0)
3860 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3861 if ((i
& 0xf8) == 0xc0)
3864 /* Only merge if the blocks are contiguous. */
3867 if ((mask
& 0xfe00) == (1 << 9))
3869 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3870 unwind
.opcode_count
--;
3873 else if (i
== 6 && unwind
.opcode_count
>= 2)
3875 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3879 op
= 0xffff << (reg
- 1);
3881 && ((mask
& op
) == (1u << (reg
- 1))))
3883 op
= (1 << (reg
+ i
+ 1)) - 1;
3884 op
&= ~((1 << reg
) - 1);
3886 unwind
.opcode_count
-= 2;
3893 /* We want to generate opcodes in the order the registers have been
3894 saved, ie. descending order. */
3895 for (reg
= 15; reg
>= -1; reg
--)
3897 /* Save registers in blocks. */
3899 || !(mask
& (1 << reg
)))
3901 /* We found an unsaved reg. Generate opcodes to save the
3908 op
= 0xc0 | (hi_reg
- 10);
3909 add_unwind_opcode (op
, 1);
3914 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3915 add_unwind_opcode (op
, 2);
3924 ignore_rest_of_line ();
3928 s_arm_unwind_save_mmxwcg (void)
3935 if (*input_line_pointer
== '{')
3936 input_line_pointer
++;
3940 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3944 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3950 as_tsktsk (_("register list not in ascending order"));
3953 if (*input_line_pointer
== '-')
3955 input_line_pointer
++;
3956 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3959 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3962 else if (reg
>= hi_reg
)
3964 as_bad (_("bad register range"));
3967 for (; reg
< hi_reg
; reg
++)
3971 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3973 if (*input_line_pointer
== '}')
3974 input_line_pointer
++;
3976 demand_empty_rest_of_line ();
3978 /* Generate any deferred opcodes because we're going to be looking at
3980 flush_pending_unwind ();
3982 for (reg
= 0; reg
< 16; reg
++)
3984 if (mask
& (1 << reg
))
3985 unwind
.frame_size
+= 4;
3988 add_unwind_opcode (op
, 2);
3991 ignore_rest_of_line ();
3995 /* Parse an unwind_save directive.
3996 If the argument is non-zero, this is a .vsave directive. */
3999 s_arm_unwind_save (int arch_v6
)
4002 struct reg_entry
*reg
;
4003 bfd_boolean had_brace
= FALSE
;
4005 if (!unwind
.proc_start
)
4006 as_bad (MISSING_FNSTART
);
4008 /* Figure out what sort of save we have. */
4009 peek
= input_line_pointer
;
4017 reg
= arm_reg_parse_multi (&peek
);
4021 as_bad (_("register expected"));
4022 ignore_rest_of_line ();
4031 as_bad (_("FPA .unwind_save does not take a register list"));
4032 ignore_rest_of_line ();
4035 input_line_pointer
= peek
;
4036 s_arm_unwind_save_fpa (reg
->number
);
4039 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4042 s_arm_unwind_save_vfp_armv6 ();
4044 s_arm_unwind_save_vfp ();
4046 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4047 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4050 as_bad (_(".unwind_save does not support this kind of register"));
4051 ignore_rest_of_line ();
4056 /* Parse an unwind_movsp directive. */
4059 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4065 if (!unwind
.proc_start
)
4066 as_bad (MISSING_FNSTART
);
4068 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4071 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4072 ignore_rest_of_line ();
4076 /* Optional constant. */
4077 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4079 if (immediate_for_directive (&offset
) == FAIL
)
4085 demand_empty_rest_of_line ();
4087 if (reg
== REG_SP
|| reg
== REG_PC
)
4089 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4093 if (unwind
.fp_reg
!= REG_SP
)
4094 as_bad (_("unexpected .unwind_movsp directive"));
4096 /* Generate opcode to restore the value. */
4098 add_unwind_opcode (op
, 1);
4100 /* Record the information for later. */
4101 unwind
.fp_reg
= reg
;
4102 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4103 unwind
.sp_restored
= 1;
4106 /* Parse an unwind_pad directive. */
4109 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4113 if (!unwind
.proc_start
)
4114 as_bad (MISSING_FNSTART
);
4116 if (immediate_for_directive (&offset
) == FAIL
)
4121 as_bad (_("stack increment must be multiple of 4"));
4122 ignore_rest_of_line ();
4126 /* Don't generate any opcodes, just record the details for later. */
4127 unwind
.frame_size
+= offset
;
4128 unwind
.pending_offset
+= offset
;
4130 demand_empty_rest_of_line ();
4133 /* Parse an unwind_setfp directive. */
4136 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4146 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4149 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4151 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4153 as_bad (_("expected <reg>, <reg>"));
4154 ignore_rest_of_line ();
4158 /* Optional constant. */
4159 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4161 if (immediate_for_directive (&offset
) == FAIL
)
4167 demand_empty_rest_of_line ();
4169 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4171 as_bad (_("register must be either sp or set by a previous"
4172 "unwind_movsp directive"));
4176 /* Don't generate any opcodes, just record the information for later. */
4177 unwind
.fp_reg
= fp_reg
;
4179 if (sp_reg
== REG_SP
)
4180 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4182 unwind
.fp_offset
-= offset
;
4185 /* Parse an unwind_raw directive. */
4188 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4191 /* This is an arbitrary limit. */
4192 unsigned char op
[16];
4195 if (!unwind
.proc_start
)
4196 as_bad (MISSING_FNSTART
);
4199 if (exp
.X_op
== O_constant
4200 && skip_past_comma (&input_line_pointer
) != FAIL
)
4202 unwind
.frame_size
+= exp
.X_add_number
;
4206 exp
.X_op
= O_illegal
;
4208 if (exp
.X_op
!= O_constant
)
4210 as_bad (_("expected <offset>, <opcode>"));
4211 ignore_rest_of_line ();
4217 /* Parse the opcode. */
4222 as_bad (_("unwind opcode too long"));
4223 ignore_rest_of_line ();
4225 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4227 as_bad (_("invalid unwind opcode"));
4228 ignore_rest_of_line ();
4231 op
[count
++] = exp
.X_add_number
;
4233 /* Parse the next byte. */
4234 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4240 /* Add the opcode bytes in reverse order. */
4242 add_unwind_opcode (op
[count
], 1);
4244 demand_empty_rest_of_line ();
4248 /* Parse a .eabi_attribute directive. */
4251 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4253 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4255 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4256 attributes_set_explicitly
[tag
] = 1;
4258 #endif /* OBJ_ELF */
4260 static void s_arm_arch (int);
4261 static void s_arm_object_arch (int);
4262 static void s_arm_cpu (int);
4263 static void s_arm_fpu (int);
4268 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4275 if (exp
.X_op
== O_symbol
)
4276 exp
.X_op
= O_secrel
;
4278 emit_expr (&exp
, 4);
4280 while (*input_line_pointer
++ == ',');
4282 input_line_pointer
--;
4283 demand_empty_rest_of_line ();
4287 /* This table describes all the machine specific pseudo-ops the assembler
4288 has to support. The fields are:
4289 pseudo-op name without dot
4290 function to call to execute this pseudo-op
4291 Integer arg to pass to the function. */
4293 const pseudo_typeS md_pseudo_table
[] =
4295 /* Never called because '.req' does not start a line. */
4296 { "req", s_req
, 0 },
4297 /* Following two are likewise never called. */
4300 { "unreq", s_unreq
, 0 },
4301 { "bss", s_bss
, 0 },
4302 { "align", s_align
, 0 },
4303 { "arm", s_arm
, 0 },
4304 { "thumb", s_thumb
, 0 },
4305 { "code", s_code
, 0 },
4306 { "force_thumb", s_force_thumb
, 0 },
4307 { "thumb_func", s_thumb_func
, 0 },
4308 { "thumb_set", s_thumb_set
, 0 },
4309 { "even", s_even
, 0 },
4310 { "ltorg", s_ltorg
, 0 },
4311 { "pool", s_ltorg
, 0 },
4312 { "syntax", s_syntax
, 0 },
4313 { "cpu", s_arm_cpu
, 0 },
4314 { "arch", s_arm_arch
, 0 },
4315 { "object_arch", s_arm_object_arch
, 0 },
4316 { "fpu", s_arm_fpu
, 0 },
4318 { "word", s_arm_elf_cons
, 4 },
4319 { "long", s_arm_elf_cons
, 4 },
4320 { "inst.n", s_arm_elf_inst
, 2 },
4321 { "inst.w", s_arm_elf_inst
, 4 },
4322 { "inst", s_arm_elf_inst
, 0 },
4323 { "rel31", s_arm_rel31
, 0 },
4324 { "fnstart", s_arm_unwind_fnstart
, 0 },
4325 { "fnend", s_arm_unwind_fnend
, 0 },
4326 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4327 { "personality", s_arm_unwind_personality
, 0 },
4328 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4329 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4330 { "save", s_arm_unwind_save
, 0 },
4331 { "vsave", s_arm_unwind_save
, 1 },
4332 { "movsp", s_arm_unwind_movsp
, 0 },
4333 { "pad", s_arm_unwind_pad
, 0 },
4334 { "setfp", s_arm_unwind_setfp
, 0 },
4335 { "unwind_raw", s_arm_unwind_raw
, 0 },
4336 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4340 /* These are used for dwarf. */
4344 /* These are used for dwarf2. */
4345 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4346 { "loc", dwarf2_directive_loc
, 0 },
4347 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4349 { "extend", float_cons
, 'x' },
4350 { "ldouble", float_cons
, 'x' },
4351 { "packed", float_cons
, 'p' },
4353 {"secrel32", pe_directive_secrel
, 0},
4358 /* Parser functions used exclusively in instruction operands. */
4360 /* Generic immediate-value read function for use in insn parsing.
4361 STR points to the beginning of the immediate (the leading #);
4362 VAL receives the value; if the value is outside [MIN, MAX]
4363 issue an error. PREFIX_OPT is true if the immediate prefix is
4367 parse_immediate (char **str
, int *val
, int min
, int max
,
4368 bfd_boolean prefix_opt
)
4371 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4372 if (exp
.X_op
!= O_constant
)
4374 inst
.error
= _("constant expression required");
4378 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4380 inst
.error
= _("immediate value out of range");
4384 *val
= exp
.X_add_number
;
4388 /* Less-generic immediate-value read function with the possibility of loading a
4389 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4390 instructions. Puts the result directly in inst.operands[i]. */
4393 parse_big_immediate (char **str
, int i
)
4398 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4400 if (exp
.X_op
== O_constant
)
4402 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4403 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4404 O_constant. We have to be careful not to break compilation for
4405 32-bit X_add_number, though. */
4406 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4408 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4409 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4410 inst
.operands
[i
].regisimm
= 1;
4413 else if (exp
.X_op
== O_big
4414 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4415 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4417 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4418 /* Bignums have their least significant bits in
4419 generic_bignum[0]. Make sure we put 32 bits in imm and
4420 32 bits in reg, in a (hopefully) portable way. */
4421 gas_assert (parts
!= 0);
4422 inst
.operands
[i
].imm
= 0;
4423 for (j
= 0; j
< parts
; j
++, idx
++)
4424 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4425 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4426 inst
.operands
[i
].reg
= 0;
4427 for (j
= 0; j
< parts
; j
++, idx
++)
4428 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4429 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4430 inst
.operands
[i
].regisimm
= 1;
4440 /* Returns the pseudo-register number of an FPA immediate constant,
4441 or FAIL if there isn't a valid constant here. */
4444 parse_fpa_immediate (char ** str
)
4446 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4452 /* First try and match exact strings, this is to guarantee
4453 that some formats will work even for cross assembly. */
4455 for (i
= 0; fp_const
[i
]; i
++)
4457 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4461 *str
+= strlen (fp_const
[i
]);
4462 if (is_end_of_line
[(unsigned char) **str
])
4468 /* Just because we didn't get a match doesn't mean that the constant
4469 isn't valid, just that it is in a format that we don't
4470 automatically recognize. Try parsing it with the standard
4471 expression routines. */
4473 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4475 /* Look for a raw floating point number. */
4476 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4477 && is_end_of_line
[(unsigned char) *save_in
])
4479 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4481 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4483 if (words
[j
] != fp_values
[i
][j
])
4487 if (j
== MAX_LITTLENUMS
)
4495 /* Try and parse a more complex expression, this will probably fail
4496 unless the code uses a floating point prefix (eg "0f"). */
4497 save_in
= input_line_pointer
;
4498 input_line_pointer
= *str
;
4499 if (expression (&exp
) == absolute_section
4500 && exp
.X_op
== O_big
4501 && exp
.X_add_number
< 0)
4503 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4505 if (gen_to_words (words
, 5, (long) 15) == 0)
4507 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4509 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4511 if (words
[j
] != fp_values
[i
][j
])
4515 if (j
== MAX_LITTLENUMS
)
4517 *str
= input_line_pointer
;
4518 input_line_pointer
= save_in
;
4525 *str
= input_line_pointer
;
4526 input_line_pointer
= save_in
;
4527 inst
.error
= _("invalid FPA immediate expression");
4531 /* Returns 1 if a number has "quarter-precision" float format
4532 0baBbbbbbc defgh000 00000000 00000000. */
4535 is_quarter_float (unsigned imm
)
4537 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4538 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4541 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4542 0baBbbbbbc defgh000 00000000 00000000.
4543 The zero and minus-zero cases need special handling, since they can't be
4544 encoded in the "quarter-precision" float format, but can nonetheless be
4545 loaded as integer constants. */
4548 parse_qfloat_immediate (char **ccp
, int *immed
)
4552 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4553 int found_fpchar
= 0;
4555 skip_past_char (&str
, '#');
4557 /* We must not accidentally parse an integer as a floating-point number. Make
4558 sure that the value we parse is not an integer by checking for special
4559 characters '.' or 'e'.
4560 FIXME: This is a horrible hack, but doing better is tricky because type
4561 information isn't in a very usable state at parse time. */
4563 skip_whitespace (fpnum
);
4565 if (strncmp (fpnum
, "0x", 2) == 0)
4569 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4570 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4580 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4582 unsigned fpword
= 0;
4585 /* Our FP word must be 32 bits (single-precision FP). */
4586 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4588 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4592 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4605 /* Shift operands. */
4608 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4611 struct asm_shift_name
4614 enum shift_kind kind
;
4617 /* Third argument to parse_shift. */
4618 enum parse_shift_mode
4620 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4621 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4622 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4623 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4624 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4627 /* Parse a <shift> specifier on an ARM data processing instruction.
4628 This has three forms:
4630 (LSL|LSR|ASL|ASR|ROR) Rs
4631 (LSL|LSR|ASL|ASR|ROR) #imm
4634 Note that ASL is assimilated to LSL in the instruction encoding, and
4635 RRX to ROR #0 (which cannot be written as such). */
4638 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4640 const struct asm_shift_name
*shift_name
;
4641 enum shift_kind shift
;
4646 for (p
= *str
; ISALPHA (*p
); p
++)
4651 inst
.error
= _("shift expression expected");
4655 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4658 if (shift_name
== NULL
)
4660 inst
.error
= _("shift expression expected");
4664 shift
= shift_name
->kind
;
4668 case NO_SHIFT_RESTRICT
:
4669 case SHIFT_IMMEDIATE
: break;
4671 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4672 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4674 inst
.error
= _("'LSL' or 'ASR' required");
4679 case SHIFT_LSL_IMMEDIATE
:
4680 if (shift
!= SHIFT_LSL
)
4682 inst
.error
= _("'LSL' required");
4687 case SHIFT_ASR_IMMEDIATE
:
4688 if (shift
!= SHIFT_ASR
)
4690 inst
.error
= _("'ASR' required");
4698 if (shift
!= SHIFT_RRX
)
4700 /* Whitespace can appear here if the next thing is a bare digit. */
4701 skip_whitespace (p
);
4703 if (mode
== NO_SHIFT_RESTRICT
4704 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4706 inst
.operands
[i
].imm
= reg
;
4707 inst
.operands
[i
].immisreg
= 1;
4709 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4712 inst
.operands
[i
].shift_kind
= shift
;
4713 inst
.operands
[i
].shifted
= 1;
4718 /* Parse a <shifter_operand> for an ARM data processing instruction:
4721 #<immediate>, <rotate>
4725 where <shift> is defined by parse_shift above, and <rotate> is a
4726 multiple of 2 between 0 and 30. Validation of immediate operands
4727 is deferred to md_apply_fix. */
4730 parse_shifter_operand (char **str
, int i
)
4735 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4737 inst
.operands
[i
].reg
= value
;
4738 inst
.operands
[i
].isreg
= 1;
4740 /* parse_shift will override this if appropriate */
4741 inst
.reloc
.exp
.X_op
= O_constant
;
4742 inst
.reloc
.exp
.X_add_number
= 0;
4744 if (skip_past_comma (str
) == FAIL
)
4747 /* Shift operation on register. */
4748 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4751 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4754 if (skip_past_comma (str
) == SUCCESS
)
4756 /* #x, y -- ie explicit rotation by Y. */
4757 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4760 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4762 inst
.error
= _("constant expression expected");
4766 value
= exp
.X_add_number
;
4767 if (value
< 0 || value
> 30 || value
% 2 != 0)
4769 inst
.error
= _("invalid rotation");
4772 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4774 inst
.error
= _("invalid constant");
4778 /* Convert to decoded value. md_apply_fix will put it back. */
4779 inst
.reloc
.exp
.X_add_number
4780 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4781 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4784 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4785 inst
.reloc
.pc_rel
= 0;
4789 /* Group relocation information. Each entry in the table contains the
4790 textual name of the relocation as may appear in assembler source
4791 and must end with a colon.
4792 Along with this textual name are the relocation codes to be used if
4793 the corresponding instruction is an ALU instruction (ADD or SUB only),
4794 an LDR, an LDRS, or an LDC. */
4796 struct group_reloc_table_entry
4807 /* Varieties of non-ALU group relocation. */
4814 static struct group_reloc_table_entry group_reloc_table
[] =
4815 { /* Program counter relative: */
4817 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4822 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4823 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4824 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4825 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4827 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4832 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4833 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4837 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4838 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4841 /* Section base relative */
4843 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4848 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4849 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4850 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4851 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4853 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4858 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4859 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4860 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4861 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4863 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4864 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4865 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4866 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4868 /* Given the address of a pointer pointing to the textual name of a group
4869 relocation as may appear in assembler source, attempt to find its details
4870 in group_reloc_table. The pointer will be updated to the character after
4871 the trailing colon. On failure, FAIL will be returned; SUCCESS
4872 otherwise. On success, *entry will be updated to point at the relevant
4873 group_reloc_table entry. */
4876 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4879 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4881 int length
= strlen (group_reloc_table
[i
].name
);
4883 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4884 && (*str
)[length
] == ':')
4886 *out
= &group_reloc_table
[i
];
4887 *str
+= (length
+ 1);
4895 /* Parse a <shifter_operand> for an ARM data processing instruction
4896 (as for parse_shifter_operand) where group relocations are allowed:
4899 #<immediate>, <rotate>
4900 #:<group_reloc>:<expression>
4904 where <group_reloc> is one of the strings defined in group_reloc_table.
4905 The hashes are optional.
4907 Everything else is as for parse_shifter_operand. */
4909 static parse_operand_result
4910 parse_shifter_operand_group_reloc (char **str
, int i
)
4912 /* Determine if we have the sequence of characters #: or just :
4913 coming next. If we do, then we check for a group relocation.
4914 If we don't, punt the whole lot to parse_shifter_operand. */
4916 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4917 || (*str
)[0] == ':')
4919 struct group_reloc_table_entry
*entry
;
4921 if ((*str
)[0] == '#')
4926 /* Try to parse a group relocation. Anything else is an error. */
4927 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4929 inst
.error
= _("unknown group relocation");
4930 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4933 /* We now have the group relocation table entry corresponding to
4934 the name in the assembler source. Next, we parse the expression. */
4935 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4936 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4938 /* Record the relocation type (always the ALU variant here). */
4939 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4940 gas_assert (inst
.reloc
.type
!= 0);
4942 return PARSE_OPERAND_SUCCESS
;
4945 return parse_shifter_operand (str
, i
) == SUCCESS
4946 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4948 /* Never reached. */
4951 /* Parse a Neon alignment expression. Information is written to
4952 inst.operands[i]. We assume the initial ':' has been skipped.
4954 align .imm = align << 8, .immisalign=1, .preind=0 */
4955 static parse_operand_result
4956 parse_neon_alignment (char **str
, int i
)
4961 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4963 if (exp
.X_op
!= O_constant
)
4965 inst
.error
= _("alignment must be constant");
4966 return PARSE_OPERAND_FAIL
;
4969 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4970 inst
.operands
[i
].immisalign
= 1;
4971 /* Alignments are not pre-indexes. */
4972 inst
.operands
[i
].preind
= 0;
4975 return PARSE_OPERAND_SUCCESS
;
4978 /* Parse all forms of an ARM address expression. Information is written
4979 to inst.operands[i] and/or inst.reloc.
4981 Preindexed addressing (.preind=1):
4983 [Rn, #offset] .reg=Rn .reloc.exp=offset
4984 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4985 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4986 .shift_kind=shift .reloc.exp=shift_imm
4988 These three may have a trailing ! which causes .writeback to be set also.
4990 Postindexed addressing (.postind=1, .writeback=1):
4992 [Rn], #offset .reg=Rn .reloc.exp=offset
4993 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4994 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4995 .shift_kind=shift .reloc.exp=shift_imm
4997 Unindexed addressing (.preind=0, .postind=0):
4999 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5003 [Rn]{!} shorthand for [Rn,#0]{!}
5004 =immediate .isreg=0 .reloc.exp=immediate
5005 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5007 It is the caller's responsibility to check for addressing modes not
5008 supported by the instruction, and to set inst.reloc.type. */
5010 static parse_operand_result
5011 parse_address_main (char **str
, int i
, int group_relocations
,
5012 group_reloc_type group_type
)
5017 if (skip_past_char (&p
, '[') == FAIL
)
5019 if (skip_past_char (&p
, '=') == FAIL
)
5021 /* Bare address - translate to PC-relative offset. */
5022 inst
.reloc
.pc_rel
= 1;
5023 inst
.operands
[i
].reg
= REG_PC
;
5024 inst
.operands
[i
].isreg
= 1;
5025 inst
.operands
[i
].preind
= 1;
5027 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5029 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5030 return PARSE_OPERAND_FAIL
;
5033 return PARSE_OPERAND_SUCCESS
;
5036 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5038 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5039 return PARSE_OPERAND_FAIL
;
5041 inst
.operands
[i
].reg
= reg
;
5042 inst
.operands
[i
].isreg
= 1;
5044 if (skip_past_comma (&p
) == SUCCESS
)
5046 inst
.operands
[i
].preind
= 1;
5049 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5051 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5053 inst
.operands
[i
].imm
= reg
;
5054 inst
.operands
[i
].immisreg
= 1;
5056 if (skip_past_comma (&p
) == SUCCESS
)
5057 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5058 return PARSE_OPERAND_FAIL
;
5060 else if (skip_past_char (&p
, ':') == SUCCESS
)
5062 /* FIXME: '@' should be used here, but it's filtered out by generic
5063 code before we get to see it here. This may be subject to
5065 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5067 if (result
!= PARSE_OPERAND_SUCCESS
)
5072 if (inst
.operands
[i
].negative
)
5074 inst
.operands
[i
].negative
= 0;
5078 if (group_relocations
5079 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5081 struct group_reloc_table_entry
*entry
;
5083 /* Skip over the #: or : sequence. */
5089 /* Try to parse a group relocation. Anything else is an
5091 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5093 inst
.error
= _("unknown group relocation");
5094 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5097 /* We now have the group relocation table entry corresponding to
5098 the name in the assembler source. Next, we parse the
5100 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5101 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5103 /* Record the relocation type. */
5107 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5111 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5115 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5122 if (inst
.reloc
.type
== 0)
5124 inst
.error
= _("this group relocation is not allowed on this instruction");
5125 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5129 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5130 return PARSE_OPERAND_FAIL
;
5133 else if (skip_past_char (&p
, ':') == SUCCESS
)
5135 /* FIXME: '@' should be used here, but it's filtered out by generic code
5136 before we get to see it here. This may be subject to change. */
5137 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5139 if (result
!= PARSE_OPERAND_SUCCESS
)
5143 if (skip_past_char (&p
, ']') == FAIL
)
5145 inst
.error
= _("']' expected");
5146 return PARSE_OPERAND_FAIL
;
5149 if (skip_past_char (&p
, '!') == SUCCESS
)
5150 inst
.operands
[i
].writeback
= 1;
5152 else if (skip_past_comma (&p
) == SUCCESS
)
5154 if (skip_past_char (&p
, '{') == SUCCESS
)
5156 /* [Rn], {expr} - unindexed, with option */
5157 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5158 0, 255, TRUE
) == FAIL
)
5159 return PARSE_OPERAND_FAIL
;
5161 if (skip_past_char (&p
, '}') == FAIL
)
5163 inst
.error
= _("'}' expected at end of 'option' field");
5164 return PARSE_OPERAND_FAIL
;
5166 if (inst
.operands
[i
].preind
)
5168 inst
.error
= _("cannot combine index with option");
5169 return PARSE_OPERAND_FAIL
;
5172 return PARSE_OPERAND_SUCCESS
;
5176 inst
.operands
[i
].postind
= 1;
5177 inst
.operands
[i
].writeback
= 1;
5179 if (inst
.operands
[i
].preind
)
5181 inst
.error
= _("cannot combine pre- and post-indexing");
5182 return PARSE_OPERAND_FAIL
;
5186 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5188 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5190 /* We might be using the immediate for alignment already. If we
5191 are, OR the register number into the low-order bits. */
5192 if (inst
.operands
[i
].immisalign
)
5193 inst
.operands
[i
].imm
|= reg
;
5195 inst
.operands
[i
].imm
= reg
;
5196 inst
.operands
[i
].immisreg
= 1;
5198 if (skip_past_comma (&p
) == SUCCESS
)
5199 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5200 return PARSE_OPERAND_FAIL
;
5204 if (inst
.operands
[i
].negative
)
5206 inst
.operands
[i
].negative
= 0;
5209 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5210 return PARSE_OPERAND_FAIL
;
5215 /* If at this point neither .preind nor .postind is set, we have a
5216 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5217 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5219 inst
.operands
[i
].preind
= 1;
5220 inst
.reloc
.exp
.X_op
= O_constant
;
5221 inst
.reloc
.exp
.X_add_number
= 0;
5224 return PARSE_OPERAND_SUCCESS
;
5228 parse_address (char **str
, int i
)
5230 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5234 static parse_operand_result
5235 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5237 return parse_address_main (str
, i
, 1, type
);
5240 /* Parse an operand for a MOVW or MOVT instruction. */
5242 parse_half (char **str
)
5247 skip_past_char (&p
, '#');
5248 if (strncasecmp (p
, ":lower16:", 9) == 0)
5249 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5250 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5251 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5253 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5256 skip_whitespace (p
);
5259 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5262 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5264 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5266 inst
.error
= _("constant expression expected");
5269 if (inst
.reloc
.exp
.X_add_number
< 0
5270 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5272 inst
.error
= _("immediate value out of range");
5280 /* Miscellaneous. */
5282 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5283 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5285 parse_psr (char **str
)
5288 unsigned long psr_field
;
5289 const struct asm_psr
*psr
;
5292 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5293 feature for ease of use and backwards compatibility. */
5295 if (strncasecmp (p
, "SPSR", 4) == 0)
5296 psr_field
= SPSR_BIT
;
5297 else if (strncasecmp (p
, "CPSR", 4) == 0)
5304 while (ISALNUM (*p
) || *p
== '_');
5306 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5318 /* A suffix follows. */
5324 while (ISALNUM (*p
) || *p
== '_');
5326 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5331 psr_field
|= psr
->field
;
5336 goto error
; /* Garbage after "[CS]PSR". */
5338 psr_field
|= (PSR_c
| PSR_f
);
5344 inst
.error
= _("flag for {c}psr instruction expected");
5348 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5349 value suitable for splatting into the AIF field of the instruction. */
5352 parse_cps_flags (char **str
)
5361 case '\0': case ',':
5364 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5365 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5366 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5369 inst
.error
= _("unrecognized CPS flag");
5374 if (saw_a_flag
== 0)
5376 inst
.error
= _("missing CPS flags");
5384 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5385 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5388 parse_endian_specifier (char **str
)
5393 if (strncasecmp (s
, "BE", 2))
5395 else if (strncasecmp (s
, "LE", 2))
5399 inst
.error
= _("valid endian specifiers are be or le");
5403 if (ISALNUM (s
[2]) || s
[2] == '_')
5405 inst
.error
= _("valid endian specifiers are be or le");
5410 return little_endian
;
5413 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5414 value suitable for poking into the rotate field of an sxt or sxta
5415 instruction, or FAIL on error. */
5418 parse_ror (char **str
)
5423 if (strncasecmp (s
, "ROR", 3) == 0)
5427 inst
.error
= _("missing rotation field after comma");
5431 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5436 case 0: *str
= s
; return 0x0;
5437 case 8: *str
= s
; return 0x1;
5438 case 16: *str
= s
; return 0x2;
5439 case 24: *str
= s
; return 0x3;
5442 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5447 /* Parse a conditional code (from conds[] below). The value returned is in the
5448 range 0 .. 14, or FAIL. */
5450 parse_cond (char **str
)
5453 const struct asm_cond
*c
;
5455 /* Condition codes are always 2 characters, so matching up to
5456 3 characters is sufficient. */
5461 while (ISALPHA (*q
) && n
< 3)
5463 cond
[n
] = TOLOWER (*q
);
5468 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5471 inst
.error
= _("condition required");
5479 /* Parse an option for a barrier instruction. Returns the encoding for the
5482 parse_barrier (char **str
)
5485 const struct asm_barrier_opt
*o
;
5488 while (ISALPHA (*q
))
5491 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5500 /* Parse the operands of a table branch instruction. Similar to a memory
5503 parse_tb (char **str
)
5508 if (skip_past_char (&p
, '[') == FAIL
)
5510 inst
.error
= _("'[' expected");
5514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5516 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5519 inst
.operands
[0].reg
= reg
;
5521 if (skip_past_comma (&p
) == FAIL
)
5523 inst
.error
= _("',' expected");
5527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5529 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5532 inst
.operands
[0].imm
= reg
;
5534 if (skip_past_comma (&p
) == SUCCESS
)
5536 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5538 if (inst
.reloc
.exp
.X_add_number
!= 1)
5540 inst
.error
= _("invalid shift");
5543 inst
.operands
[0].shifted
= 1;
5546 if (skip_past_char (&p
, ']') == FAIL
)
5548 inst
.error
= _("']' expected");
5555 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5556 information on the types the operands can take and how they are encoded.
5557 Up to four operands may be read; this function handles setting the
5558 ".present" field for each read operand itself.
5559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5560 else returns FAIL. */
5563 parse_neon_mov (char **str
, int *which_operand
)
5565 int i
= *which_operand
, val
;
5566 enum arm_reg_type rtype
;
5568 struct neon_type_el optype
;
5570 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5572 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isscalar
= 1;
5575 inst
.operands
[i
].vectype
= optype
;
5576 inst
.operands
[i
++].present
= 1;
5578 if (skip_past_comma (&ptr
) == FAIL
)
5581 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5584 inst
.operands
[i
].reg
= val
;
5585 inst
.operands
[i
].isreg
= 1;
5586 inst
.operands
[i
].present
= 1;
5588 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5591 /* Cases 0, 1, 2, 3, 5 (D only). */
5592 if (skip_past_comma (&ptr
) == FAIL
)
5595 inst
.operands
[i
].reg
= val
;
5596 inst
.operands
[i
].isreg
= 1;
5597 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5598 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5599 inst
.operands
[i
].isvec
= 1;
5600 inst
.operands
[i
].vectype
= optype
;
5601 inst
.operands
[i
++].present
= 1;
5603 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5605 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5606 Case 13: VMOV <Sd>, <Rm> */
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isreg
= 1;
5609 inst
.operands
[i
].present
= 1;
5611 if (rtype
== REG_TYPE_NQ
)
5613 first_error (_("can't use Neon quad register here"));
5616 else if (rtype
!= REG_TYPE_VFS
)
5619 if (skip_past_comma (&ptr
) == FAIL
)
5621 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5623 inst
.operands
[i
].reg
= val
;
5624 inst
.operands
[i
].isreg
= 1;
5625 inst
.operands
[i
].present
= 1;
5628 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5631 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5632 Case 1: VMOV<c><q> <Dd>, <Dm>
5633 Case 8: VMOV.F32 <Sd>, <Sm>
5634 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5639 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5640 inst
.operands
[i
].isvec
= 1;
5641 inst
.operands
[i
].vectype
= optype
;
5642 inst
.operands
[i
].present
= 1;
5644 if (skip_past_comma (&ptr
) == SUCCESS
)
5649 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5652 inst
.operands
[i
].reg
= val
;
5653 inst
.operands
[i
].isreg
= 1;
5654 inst
.operands
[i
++].present
= 1;
5656 if (skip_past_comma (&ptr
) == FAIL
)
5659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5662 inst
.operands
[i
].reg
= val
;
5663 inst
.operands
[i
].isreg
= 1;
5664 inst
.operands
[i
++].present
= 1;
5667 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5668 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5669 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5670 Case 10: VMOV.F32 <Sd>, #<imm>
5671 Case 11: VMOV.F64 <Dd>, #<imm> */
5672 inst
.operands
[i
].immisfloat
= 1;
5673 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5674 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5675 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5679 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5683 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5688 inst
.operands
[i
++].present
= 1;
5690 if (skip_past_comma (&ptr
) == FAIL
)
5693 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5695 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5696 inst
.operands
[i
].reg
= val
;
5697 inst
.operands
[i
].isscalar
= 1;
5698 inst
.operands
[i
].present
= 1;
5699 inst
.operands
[i
].vectype
= optype
;
5701 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5703 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5704 inst
.operands
[i
].reg
= val
;
5705 inst
.operands
[i
].isreg
= 1;
5706 inst
.operands
[i
++].present
= 1;
5708 if (skip_past_comma (&ptr
) == FAIL
)
5711 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5714 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5718 inst
.operands
[i
].reg
= val
;
5719 inst
.operands
[i
].isreg
= 1;
5720 inst
.operands
[i
].isvec
= 1;
5721 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5722 inst
.operands
[i
].vectype
= optype
;
5723 inst
.operands
[i
].present
= 1;
5725 if (rtype
== REG_TYPE_VFS
)
5729 if (skip_past_comma (&ptr
) == FAIL
)
5731 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5734 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5737 inst
.operands
[i
].reg
= val
;
5738 inst
.operands
[i
].isreg
= 1;
5739 inst
.operands
[i
].isvec
= 1;
5740 inst
.operands
[i
].issingle
= 1;
5741 inst
.operands
[i
].vectype
= optype
;
5742 inst
.operands
[i
].present
= 1;
5745 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5749 inst
.operands
[i
].reg
= val
;
5750 inst
.operands
[i
].isreg
= 1;
5751 inst
.operands
[i
].isvec
= 1;
5752 inst
.operands
[i
].issingle
= 1;
5753 inst
.operands
[i
].vectype
= optype
;
5754 inst
.operands
[i
++].present
= 1;
5759 first_error (_("parse error"));
5763 /* Successfully parsed the operands. Update args. */
5769 first_error (_("expected comma"));
5773 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5777 /* Use this macro when the operand constraints are different
5778 for ARM and THUMB (e.g. ldrd). */
5779 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5780 ((arm_operand) | ((thumb_operand) << 16))
5782 /* Matcher codes for parse_operands. */
5783 enum operand_parse_code
5785 OP_stop
, /* end of line */
5787 OP_RR
, /* ARM register */
5788 OP_RRnpc
, /* ARM register, not r15 */
5789 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5790 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5791 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5792 optional trailing ! */
5793 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5794 OP_RCP
, /* Coprocessor number */
5795 OP_RCN
, /* Coprocessor register */
5796 OP_RF
, /* FPA register */
5797 OP_RVS
, /* VFP single precision register */
5798 OP_RVD
, /* VFP double precision register (0..15) */
5799 OP_RND
, /* Neon double precision register (0..31) */
5800 OP_RNQ
, /* Neon quad precision register */
5801 OP_RVSD
, /* VFP single or double precision register */
5802 OP_RNDQ
, /* Neon double or quad precision register */
5803 OP_RNSDQ
, /* Neon single, double or quad precision register */
5804 OP_RNSC
, /* Neon scalar D[X] */
5805 OP_RVC
, /* VFP control register */
5806 OP_RMF
, /* Maverick F register */
5807 OP_RMD
, /* Maverick D register */
5808 OP_RMFX
, /* Maverick FX register */
5809 OP_RMDX
, /* Maverick DX register */
5810 OP_RMAX
, /* Maverick AX register */
5811 OP_RMDS
, /* Maverick DSPSC register */
5812 OP_RIWR
, /* iWMMXt wR register */
5813 OP_RIWC
, /* iWMMXt wC register */
5814 OP_RIWG
, /* iWMMXt wCG register */
5815 OP_RXA
, /* XScale accumulator register */
5817 OP_REGLST
, /* ARM register list */
5818 OP_VRSLST
, /* VFP single-precision register list */
5819 OP_VRDLST
, /* VFP double-precision register list */
5820 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5821 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5822 OP_NSTRLST
, /* Neon element/structure list */
5824 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5825 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5826 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5827 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5828 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5829 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5830 OP_VMOV
, /* Neon VMOV operands. */
5831 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5832 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5833 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5835 OP_I0
, /* immediate zero */
5836 OP_I7
, /* immediate value 0 .. 7 */
5837 OP_I15
, /* 0 .. 15 */
5838 OP_I16
, /* 1 .. 16 */
5839 OP_I16z
, /* 0 .. 16 */
5840 OP_I31
, /* 0 .. 31 */
5841 OP_I31w
, /* 0 .. 31, optional trailing ! */
5842 OP_I32
, /* 1 .. 32 */
5843 OP_I32z
, /* 0 .. 32 */
5844 OP_I63
, /* 0 .. 63 */
5845 OP_I63s
, /* -64 .. 63 */
5846 OP_I64
, /* 1 .. 64 */
5847 OP_I64z
, /* 0 .. 64 */
5848 OP_I255
, /* 0 .. 255 */
5850 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5851 OP_I7b
, /* 0 .. 7 */
5852 OP_I15b
, /* 0 .. 15 */
5853 OP_I31b
, /* 0 .. 31 */
5855 OP_SH
, /* shifter operand */
5856 OP_SHG
, /* shifter operand with possible group relocation */
5857 OP_ADDR
, /* Memory address expression (any mode) */
5858 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5859 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5860 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5861 OP_EXP
, /* arbitrary expression */
5862 OP_EXPi
, /* same, with optional immediate prefix */
5863 OP_EXPr
, /* same, with optional relocation suffix */
5864 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5866 OP_CPSF
, /* CPS flags */
5867 OP_ENDI
, /* Endianness specifier */
5868 OP_PSR
, /* CPSR/SPSR mask for msr */
5869 OP_COND
, /* conditional code */
5870 OP_TB
, /* Table branch. */
5872 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5873 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5875 OP_RRnpc_I0
, /* ARM register or literal 0 */
5876 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5877 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5878 OP_RF_IF
, /* FPA register or immediate */
5879 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5880 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5882 /* Optional operands. */
5883 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5884 OP_oI31b
, /* 0 .. 31 */
5885 OP_oI32b
, /* 1 .. 32 */
5886 OP_oIffffb
, /* 0 .. 65535 */
5887 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5889 OP_oRR
, /* ARM register */
5890 OP_oRRnpc
, /* ARM register, not the PC */
5891 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5892 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5893 OP_oRND
, /* Optional Neon double precision register */
5894 OP_oRNQ
, /* Optional Neon quad precision register */
5895 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5896 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5897 OP_oSHll
, /* LSL immediate */
5898 OP_oSHar
, /* ASR immediate */
5899 OP_oSHllar
, /* LSL or ASR immediate */
5900 OP_oROR
, /* ROR 0/8/16/24 */
5901 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5903 /* Some pre-defined mixed (ARM/THUMB) operands. */
5904 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5905 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5906 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5908 OP_FIRST_OPTIONAL
= OP_oI7b
5911 /* Generic instruction operand parser. This does no encoding and no
5912 semantic validation; it merely squirrels values away in the inst
5913 structure. Returns SUCCESS or FAIL depending on whether the
5914 specified grammar matched. */
5916 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5918 unsigned const int *upat
= pattern
;
5919 char *backtrack_pos
= 0;
5920 const char *backtrack_error
= 0;
5921 int i
, val
, backtrack_index
= 0;
5922 enum arm_reg_type rtype
;
5923 parse_operand_result result
;
5924 unsigned int op_parse_code
;
5926 #define po_char_or_fail(chr) \
5929 if (skip_past_char (&str, chr) == FAIL) \
5934 #define po_reg_or_fail(regtype) \
5937 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5938 & inst.operands[i].vectype); \
5941 first_error (_(reg_expected_msgs[regtype])); \
5944 inst.operands[i].reg = val; \
5945 inst.operands[i].isreg = 1; \
5946 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5947 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5948 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5949 || rtype == REG_TYPE_VFD \
5950 || rtype == REG_TYPE_NQ); \
5954 #define po_reg_or_goto(regtype, label) \
5957 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5958 & inst.operands[i].vectype); \
5962 inst.operands[i].reg = val; \
5963 inst.operands[i].isreg = 1; \
5964 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5965 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5966 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5967 || rtype == REG_TYPE_VFD \
5968 || rtype == REG_TYPE_NQ); \
5972 #define po_imm_or_fail(min, max, popt) \
5975 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5977 inst.operands[i].imm = val; \
5981 #define po_scalar_or_goto(elsz, label) \
5984 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5987 inst.operands[i].reg = val; \
5988 inst.operands[i].isscalar = 1; \
5992 #define po_misc_or_fail(expr) \
6000 #define po_misc_or_fail_no_backtrack(expr) \
6004 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6005 backtrack_pos = 0; \
6006 if (result != PARSE_OPERAND_SUCCESS) \
6011 skip_whitespace (str
);
6013 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6015 op_parse_code
= upat
[i
];
6016 if (op_parse_code
>= 1<<16)
6017 op_parse_code
= thumb
? (op_parse_code
>> 16)
6018 : (op_parse_code
& ((1<<16)-1));
6020 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6022 /* Remember where we are in case we need to backtrack. */
6023 gas_assert (!backtrack_pos
);
6024 backtrack_pos
= str
;
6025 backtrack_error
= inst
.error
;
6026 backtrack_index
= i
;
6029 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6030 po_char_or_fail (',');
6032 switch (op_parse_code
)
6040 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6041 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6042 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6043 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6044 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6045 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6047 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6049 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6051 /* Also accept generic coprocessor regs for unknown registers. */
6053 po_reg_or_fail (REG_TYPE_CN
);
6055 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6056 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6057 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6058 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6059 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6060 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6061 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6062 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6063 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6064 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6066 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6068 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6069 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6071 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6073 /* Neon scalar. Using an element size of 8 means that some invalid
6074 scalars are accepted here, so deal with those in later code. */
6075 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6079 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6082 po_imm_or_fail (0, 0, TRUE
);
6087 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6092 po_scalar_or_goto (8, try_rr
);
6095 po_reg_or_fail (REG_TYPE_RN
);
6101 po_scalar_or_goto (8, try_nsdq
);
6104 po_reg_or_fail (REG_TYPE_NSDQ
);
6110 po_scalar_or_goto (8, try_ndq
);
6113 po_reg_or_fail (REG_TYPE_NDQ
);
6119 po_scalar_or_goto (8, try_vfd
);
6122 po_reg_or_fail (REG_TYPE_VFD
);
6127 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6128 not careful then bad things might happen. */
6129 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6134 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6137 /* There's a possibility of getting a 64-bit immediate here, so
6138 we need special handling. */
6139 if (parse_big_immediate (&str
, i
) == FAIL
)
6141 inst
.error
= _("immediate value is out of range");
6149 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6152 po_imm_or_fail (0, 63, TRUE
);
6157 po_char_or_fail ('[');
6158 po_reg_or_fail (REG_TYPE_RN
);
6159 po_char_or_fail (']');
6165 po_reg_or_fail (REG_TYPE_RN
);
6166 if (skip_past_char (&str
, '!') == SUCCESS
)
6167 inst
.operands
[i
].writeback
= 1;
6171 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6172 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6173 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6174 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6175 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6176 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6177 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6178 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6179 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6180 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6181 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6182 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6184 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6186 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6187 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6189 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6190 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6191 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6193 /* Immediate variants */
6195 po_char_or_fail ('{');
6196 po_imm_or_fail (0, 255, TRUE
);
6197 po_char_or_fail ('}');
6201 /* The expression parser chokes on a trailing !, so we have
6202 to find it first and zap it. */
6205 while (*s
&& *s
!= ',')
6210 inst
.operands
[i
].writeback
= 1;
6212 po_imm_or_fail (0, 31, TRUE
);
6220 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6225 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6230 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6232 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6234 val
= parse_reloc (&str
);
6237 inst
.error
= _("unrecognized relocation suffix");
6240 else if (val
!= BFD_RELOC_UNUSED
)
6242 inst
.operands
[i
].imm
= val
;
6243 inst
.operands
[i
].hasreloc
= 1;
6248 /* Operand for MOVW or MOVT. */
6250 po_misc_or_fail (parse_half (&str
));
6253 /* Register or expression. */
6254 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6255 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6257 /* Register or immediate. */
6258 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6259 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6261 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6263 if (!is_immediate_prefix (*str
))
6266 val
= parse_fpa_immediate (&str
);
6269 /* FPA immediates are encoded as registers 8-15.
6270 parse_fpa_immediate has already applied the offset. */
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isreg
= 1;
6275 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6276 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6278 /* Two kinds of register. */
6281 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6283 || (rege
->type
!= REG_TYPE_MMXWR
6284 && rege
->type
!= REG_TYPE_MMXWC
6285 && rege
->type
!= REG_TYPE_MMXWCG
))
6287 inst
.error
= _("iWMMXt data or control register expected");
6290 inst
.operands
[i
].reg
= rege
->number
;
6291 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6297 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6299 || (rege
->type
!= REG_TYPE_MMXWC
6300 && rege
->type
!= REG_TYPE_MMXWCG
))
6302 inst
.error
= _("iWMMXt control register expected");
6305 inst
.operands
[i
].reg
= rege
->number
;
6306 inst
.operands
[i
].isreg
= 1;
6311 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6312 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6313 case OP_oROR
: val
= parse_ror (&str
); break;
6314 case OP_PSR
: val
= parse_psr (&str
); break;
6315 case OP_COND
: val
= parse_cond (&str
); break;
6316 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6319 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6320 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6323 val
= parse_psr (&str
);
6327 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6330 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6332 if (strncasecmp (str
, "APSR_", 5) == 0)
6339 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6340 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6341 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6342 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6343 default: found
= 16;
6347 inst
.operands
[i
].isvec
= 1;
6348 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6349 inst
.operands
[i
].reg
= REG_PC
;
6356 po_misc_or_fail (parse_tb (&str
));
6359 /* Register lists. */
6361 val
= parse_reg_list (&str
);
6364 inst
.operands
[1].writeback
= 1;
6370 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6374 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6378 /* Allow Q registers too. */
6379 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6384 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6386 inst
.operands
[i
].issingle
= 1;
6391 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6396 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6397 &inst
.operands
[i
].vectype
);
6400 /* Addressing modes */
6402 po_misc_or_fail (parse_address (&str
, i
));
6406 po_misc_or_fail_no_backtrack (
6407 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6411 po_misc_or_fail_no_backtrack (
6412 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6416 po_misc_or_fail_no_backtrack (
6417 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6421 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6425 po_misc_or_fail_no_backtrack (
6426 parse_shifter_operand_group_reloc (&str
, i
));
6430 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6434 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6438 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6442 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6445 /* Various value-based sanity checks and shared operations. We
6446 do not signal immediate failures for the register constraints;
6447 this allows a syntax error to take precedence. */
6448 switch (op_parse_code
)
6456 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6457 inst
.error
= BAD_PC
;
6462 if (inst
.operands
[i
].isreg
)
6464 if (inst
.operands
[i
].reg
== REG_PC
)
6465 inst
.error
= BAD_PC
;
6466 else if (inst
.operands
[i
].reg
== REG_SP
)
6467 inst
.error
= BAD_SP
;
6472 if (inst
.operands
[i
].isreg
6473 && inst
.operands
[i
].reg
== REG_PC
6474 && (inst
.operands
[i
].writeback
|| thumb
))
6475 inst
.error
= BAD_PC
;
6493 inst
.operands
[i
].imm
= val
;
6500 /* If we get here, this operand was successfully parsed. */
6501 inst
.operands
[i
].present
= 1;
6505 inst
.error
= BAD_ARGS
;
6510 /* The parse routine should already have set inst.error, but set a
6511 default here just in case. */
6513 inst
.error
= _("syntax error");
6517 /* Do not backtrack over a trailing optional argument that
6518 absorbed some text. We will only fail again, with the
6519 'garbage following instruction' error message, which is
6520 probably less helpful than the current one. */
6521 if (backtrack_index
== i
&& backtrack_pos
!= str
6522 && upat
[i
+1] == OP_stop
)
6525 inst
.error
= _("syntax error");
6529 /* Try again, skipping the optional argument at backtrack_pos. */
6530 str
= backtrack_pos
;
6531 inst
.error
= backtrack_error
;
6532 inst
.operands
[backtrack_index
].present
= 0;
6533 i
= backtrack_index
;
6537 /* Check that we have parsed all the arguments. */
6538 if (*str
!= '\0' && !inst
.error
)
6539 inst
.error
= _("garbage following instruction");
6541 return inst
.error
? FAIL
: SUCCESS
;
6544 #undef po_char_or_fail
6545 #undef po_reg_or_fail
6546 #undef po_reg_or_goto
6547 #undef po_imm_or_fail
6548 #undef po_scalar_or_fail
6550 /* Shorthand macro for instruction encoding functions issuing errors. */
6551 #define constraint(expr, err) \
6562 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6563 instructions are unpredictable if these registers are used. This
6564 is the BadReg predicate in ARM's Thumb-2 documentation. */
6565 #define reject_bad_reg(reg) \
6567 if (reg == REG_SP || reg == REG_PC) \
6569 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6574 /* If REG is R13 (the stack pointer), warn that its use is
6576 #define warn_deprecated_sp(reg) \
6578 if (warn_on_deprecated && reg == REG_SP) \
6579 as_warn (_("use of r13 is deprecated")); \
6582 /* Functions for operand encoding. ARM, then Thumb. */
6584 #define rotate_left(v, n) (v << n | v >> (32 - n))
6586 /* If VAL can be encoded in the immediate field of an ARM instruction,
6587 return the encoded form. Otherwise, return FAIL. */
6590 encode_arm_immediate (unsigned int val
)
6594 for (i
= 0; i
< 32; i
+= 2)
6595 if ((a
= rotate_left (val
, i
)) <= 0xff)
6596 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6601 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6602 return the encoded form. Otherwise, return FAIL. */
6604 encode_thumb32_immediate (unsigned int val
)
6611 for (i
= 1; i
<= 24; i
++)
6614 if ((val
& ~(0xff << i
)) == 0)
6615 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6619 if (val
== ((a
<< 16) | a
))
6621 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6625 if (val
== ((a
<< 16) | a
))
6626 return 0x200 | (a
>> 8);
6630 /* Encode a VFP SP or DP register number into inst.instruction. */
6633 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6635 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6638 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6641 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6644 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6649 first_error (_("D register out of range for selected VFP version"));
6657 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6661 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6665 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6669 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6673 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6677 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6685 /* Encode a <shift> in an ARM-format instruction. The immediate,
6686 if any, is handled by md_apply_fix. */
6688 encode_arm_shift (int i
)
6690 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6691 inst
.instruction
|= SHIFT_ROR
<< 5;
6694 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6695 if (inst
.operands
[i
].immisreg
)
6697 inst
.instruction
|= SHIFT_BY_REG
;
6698 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6701 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6706 encode_arm_shifter_operand (int i
)
6708 if (inst
.operands
[i
].isreg
)
6710 inst
.instruction
|= inst
.operands
[i
].reg
;
6711 encode_arm_shift (i
);
6714 inst
.instruction
|= INST_IMMEDIATE
;
6717 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6719 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6721 gas_assert (inst
.operands
[i
].isreg
);
6722 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6724 if (inst
.operands
[i
].preind
)
6728 inst
.error
= _("instruction does not accept preindexed addressing");
6731 inst
.instruction
|= PRE_INDEX
;
6732 if (inst
.operands
[i
].writeback
)
6733 inst
.instruction
|= WRITE_BACK
;
6736 else if (inst
.operands
[i
].postind
)
6738 gas_assert (inst
.operands
[i
].writeback
);
6740 inst
.instruction
|= WRITE_BACK
;
6742 else /* unindexed - only for coprocessor */
6744 inst
.error
= _("instruction does not accept unindexed addressing");
6748 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6749 && (((inst
.instruction
& 0x000f0000) >> 16)
6750 == ((inst
.instruction
& 0x0000f000) >> 12)))
6751 as_warn ((inst
.instruction
& LOAD_BIT
)
6752 ? _("destination register same as write-back base")
6753 : _("source register same as write-back base"));
6756 /* inst.operands[i] was set up by parse_address. Encode it into an
6757 ARM-format mode 2 load or store instruction. If is_t is true,
6758 reject forms that cannot be used with a T instruction (i.e. not
6761 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6763 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6765 encode_arm_addr_mode_common (i
, is_t
);
6767 if (inst
.operands
[i
].immisreg
)
6769 constraint ((inst
.operands
[i
].imm
== REG_PC
6770 || (is_pc
&& inst
.operands
[i
].writeback
)),
6772 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6773 inst
.instruction
|= inst
.operands
[i
].imm
;
6774 if (!inst
.operands
[i
].negative
)
6775 inst
.instruction
|= INDEX_UP
;
6776 if (inst
.operands
[i
].shifted
)
6778 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6779 inst
.instruction
|= SHIFT_ROR
<< 5;
6782 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6783 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6787 else /* immediate offset in inst.reloc */
6789 if (is_pc
&& !inst
.reloc
.pc_rel
)
6791 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6792 /* BAD_PC_ADDRESSING Condition =
6794 which becomes !is_load || is_t. */
6795 constraint ((!is_load
|| is_t
),
6799 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6800 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6804 /* inst.operands[i] was set up by parse_address. Encode it into an
6805 ARM-format mode 3 load or store instruction. Reject forms that
6806 cannot be used with such instructions. If is_t is true, reject
6807 forms that cannot be used with a T instruction (i.e. not
6810 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6812 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6814 inst
.error
= _("instruction does not accept scaled register index");
6818 encode_arm_addr_mode_common (i
, is_t
);
6820 if (inst
.operands
[i
].immisreg
)
6822 constraint ((inst
.operands
[i
].imm
== REG_PC
6823 || inst
.operands
[i
].reg
== REG_PC
),
6825 inst
.instruction
|= inst
.operands
[i
].imm
;
6826 if (!inst
.operands
[i
].negative
)
6827 inst
.instruction
|= INDEX_UP
;
6829 else /* immediate offset in inst.reloc */
6831 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6832 && inst
.operands
[i
].writeback
),
6834 inst
.instruction
|= HWOFFSET_IMM
;
6835 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6836 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6840 /* inst.operands[i] was set up by parse_address. Encode it into an
6841 ARM-format instruction. Reject all forms which cannot be encoded
6842 into a coprocessor load/store instruction. If wb_ok is false,
6843 reject use of writeback; if unind_ok is false, reject use of
6844 unindexed addressing. If reloc_override is not 0, use it instead
6845 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6846 (in which case it is preserved). */
6849 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6851 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6853 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6855 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6857 gas_assert (!inst
.operands
[i
].writeback
);
6860 inst
.error
= _("instruction does not support unindexed addressing");
6863 inst
.instruction
|= inst
.operands
[i
].imm
;
6864 inst
.instruction
|= INDEX_UP
;
6868 if (inst
.operands
[i
].preind
)
6869 inst
.instruction
|= PRE_INDEX
;
6871 if (inst
.operands
[i
].writeback
)
6873 if (inst
.operands
[i
].reg
== REG_PC
)
6875 inst
.error
= _("pc may not be used with write-back");
6880 inst
.error
= _("instruction does not support writeback");
6883 inst
.instruction
|= WRITE_BACK
;
6887 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6888 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6889 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6890 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6893 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6895 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6901 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6902 Determine whether it can be performed with a move instruction; if
6903 it can, convert inst.instruction to that move instruction and
6904 return TRUE; if it can't, convert inst.instruction to a literal-pool
6905 load and return FALSE. If this is not a valid thing to do in the
6906 current context, set inst.error and return TRUE.
6908 inst.operands[i] describes the destination register. */
6911 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6916 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6920 if ((inst
.instruction
& tbit
) == 0)
6922 inst
.error
= _("invalid pseudo operation");
6925 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6927 inst
.error
= _("constant expression expected");
6930 if (inst
.reloc
.exp
.X_op
== O_constant
)
6934 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6936 /* This can be done with a mov(1) instruction. */
6937 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6938 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6944 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6947 /* This can be done with a mov instruction. */
6948 inst
.instruction
&= LITERAL_MASK
;
6949 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6950 inst
.instruction
|= value
& 0xfff;
6954 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6957 /* This can be done with a mvn instruction. */
6958 inst
.instruction
&= LITERAL_MASK
;
6959 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6960 inst
.instruction
|= value
& 0xfff;
6966 if (add_to_lit_pool () == FAIL
)
6968 inst
.error
= _("literal pool insertion failed");
6971 inst
.operands
[1].reg
= REG_PC
;
6972 inst
.operands
[1].isreg
= 1;
6973 inst
.operands
[1].preind
= 1;
6974 inst
.reloc
.pc_rel
= 1;
6975 inst
.reloc
.type
= (thumb_p
6976 ? BFD_RELOC_ARM_THUMB_OFFSET
6978 ? BFD_RELOC_ARM_HWLITERAL
6979 : BFD_RELOC_ARM_LITERAL
));
6983 /* Functions for instruction encoding, sorted by sub-architecture.
6984 First some generics; their names are taken from the conventional
6985 bit positions for register arguments in ARM format instructions. */
6995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7002 inst
.instruction
|= inst
.operands
[1].reg
;
7008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7009 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7015 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7016 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7022 unsigned Rn
= inst
.operands
[2].reg
;
7023 /* Enforce restrictions on SWP instruction. */
7024 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7026 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7027 _("Rn must not overlap other operands"));
7029 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7030 if (warn_on_deprecated
7031 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7032 as_warn (_("swp{b} use is deprecated for this architecture"));
7035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7036 inst
.instruction
|= inst
.operands
[1].reg
;
7037 inst
.instruction
|= Rn
<< 16;
7043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7045 inst
.instruction
|= inst
.operands
[2].reg
;
7051 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7052 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7053 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7054 || inst
.reloc
.exp
.X_add_number
!= 0),
7056 inst
.instruction
|= inst
.operands
[0].reg
;
7057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7058 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7064 inst
.instruction
|= inst
.operands
[0].imm
;
7070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7071 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7074 /* ARM instructions, in alphabetical order by function name (except
7075 that wrapper functions appear immediately after the function they
7078 /* This is a pseudo-op of the form "adr rd, label" to be converted
7079 into a relative address of the form "add rd, pc, #label-.-8". */
7084 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7086 /* Frag hacking will turn this into a sub instruction if the offset turns
7087 out to be negative. */
7088 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7089 inst
.reloc
.pc_rel
= 1;
7090 inst
.reloc
.exp
.X_add_number
-= 8;
7093 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7094 into a relative address of the form:
7095 add rd, pc, #low(label-.-8)"
7096 add rd, rd, #high(label-.-8)" */
7101 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7103 /* Frag hacking will turn this into a sub instruction if the offset turns
7104 out to be negative. */
7105 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7106 inst
.reloc
.pc_rel
= 1;
7107 inst
.size
= INSN_SIZE
* 2;
7108 inst
.reloc
.exp
.X_add_number
-= 8;
7114 if (!inst
.operands
[1].present
)
7115 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7118 encode_arm_shifter_operand (2);
7124 if (inst
.operands
[0].present
)
7126 constraint ((inst
.instruction
& 0xf0) != 0x40
7127 && inst
.operands
[0].imm
!= 0xf,
7128 _("bad barrier type"));
7129 inst
.instruction
|= inst
.operands
[0].imm
;
7132 inst
.instruction
|= 0xf;
7138 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7139 constraint (msb
> 32, _("bit-field extends past end of register"));
7140 /* The instruction encoding stores the LSB and MSB,
7141 not the LSB and width. */
7142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7143 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7144 inst
.instruction
|= (msb
- 1) << 16;
7152 /* #0 in second position is alternative syntax for bfc, which is
7153 the same instruction but with REG_PC in the Rm field. */
7154 if (!inst
.operands
[1].isreg
)
7155 inst
.operands
[1].reg
= REG_PC
;
7157 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7158 constraint (msb
> 32, _("bit-field extends past end of register"));
7159 /* The instruction encoding stores the LSB and MSB,
7160 not the LSB and width. */
7161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7162 inst
.instruction
|= inst
.operands
[1].reg
;
7163 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7164 inst
.instruction
|= (msb
- 1) << 16;
7170 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7171 _("bit-field extends past end of register"));
7172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7173 inst
.instruction
|= inst
.operands
[1].reg
;
7174 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7175 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7178 /* ARM V5 breakpoint instruction (argument parse)
7179 BKPT <16 bit unsigned immediate>
7180 Instruction is not conditional.
7181 The bit pattern given in insns[] has the COND_ALWAYS condition,
7182 and it is an error if the caller tried to override that. */
7187 /* Top 12 of 16 bits to bits 19:8. */
7188 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7190 /* Bottom 4 of 16 bits to bits 3:0. */
7191 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7195 encode_branch (int default_reloc
)
7197 if (inst
.operands
[0].hasreloc
)
7199 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7200 _("the only suffix valid here is '(plt)'"));
7201 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7205 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7207 inst
.reloc
.pc_rel
= 1;
7214 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7215 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7218 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7225 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7227 if (inst
.cond
== COND_ALWAYS
)
7228 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7230 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7234 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7237 /* ARM V5 branch-link-exchange instruction (argument parse)
7238 BLX <target_addr> ie BLX(1)
7239 BLX{<condition>} <Rm> ie BLX(2)
7240 Unfortunately, there are two different opcodes for this mnemonic.
7241 So, the insns[].value is not used, and the code here zaps values
7242 into inst.instruction.
7243 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7248 if (inst
.operands
[0].isreg
)
7250 /* Arg is a register; the opcode provided by insns[] is correct.
7251 It is not illegal to do "blx pc", just useless. */
7252 if (inst
.operands
[0].reg
== REG_PC
)
7253 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7255 inst
.instruction
|= inst
.operands
[0].reg
;
7259 /* Arg is an address; this instruction cannot be executed
7260 conditionally, and the opcode must be adjusted.
7261 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7262 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7263 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7264 inst
.instruction
= 0xfa000000;
7265 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7272 bfd_boolean want_reloc
;
7274 if (inst
.operands
[0].reg
== REG_PC
)
7275 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7277 inst
.instruction
|= inst
.operands
[0].reg
;
7278 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7279 it is for ARMv4t or earlier. */
7280 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7281 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7285 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7290 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7294 /* ARM v5TEJ. Jump to Jazelle code. */
7299 if (inst
.operands
[0].reg
== REG_PC
)
7300 as_tsktsk (_("use of r15 in bxj is not really useful"));
7302 inst
.instruction
|= inst
.operands
[0].reg
;
7305 /* Co-processor data operation:
7306 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7307 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7311 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7312 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7313 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7314 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7315 inst
.instruction
|= inst
.operands
[4].reg
;
7316 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7322 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7323 encode_arm_shifter_operand (1);
7326 /* Transfer between coprocessor and ARM registers.
7327 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7332 No special properties. */
7339 Rd
= inst
.operands
[2].reg
;
7342 if (inst
.instruction
== 0xee000010
7343 || inst
.instruction
== 0xfe000010)
7345 reject_bad_reg (Rd
);
7348 constraint (Rd
== REG_SP
, BAD_SP
);
7353 if (inst
.instruction
== 0xe000010)
7354 constraint (Rd
== REG_PC
, BAD_PC
);
7358 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7359 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7360 inst
.instruction
|= Rd
<< 12;
7361 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7362 inst
.instruction
|= inst
.operands
[4].reg
;
7363 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7366 /* Transfer between coprocessor register and pair of ARM registers.
7367 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7372 Two XScale instructions are special cases of these:
7374 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7375 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7377 Result unpredictable if Rd or Rn is R15. */
7384 Rd
= inst
.operands
[2].reg
;
7385 Rn
= inst
.operands
[3].reg
;
7389 reject_bad_reg (Rd
);
7390 reject_bad_reg (Rn
);
7394 constraint (Rd
== REG_PC
, BAD_PC
);
7395 constraint (Rn
== REG_PC
, BAD_PC
);
7398 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7399 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7400 inst
.instruction
|= Rd
<< 12;
7401 inst
.instruction
|= Rn
<< 16;
7402 inst
.instruction
|= inst
.operands
[4].reg
;
7408 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7409 if (inst
.operands
[1].present
)
7411 inst
.instruction
|= CPSI_MMOD
;
7412 inst
.instruction
|= inst
.operands
[1].imm
;
7419 inst
.instruction
|= inst
.operands
[0].imm
;
7425 /* There is no IT instruction in ARM mode. We
7426 process it to do the validation as if in
7427 thumb mode, just in case the code gets
7428 assembled for thumb using the unified syntax. */
7433 set_it_insn_type (IT_INSN
);
7434 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7435 now_it
.cc
= inst
.operands
[0].imm
;
7442 int base_reg
= inst
.operands
[0].reg
;
7443 int range
= inst
.operands
[1].imm
;
7445 inst
.instruction
|= base_reg
<< 16;
7446 inst
.instruction
|= range
;
7448 if (inst
.operands
[1].writeback
)
7449 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7451 if (inst
.operands
[0].writeback
)
7453 inst
.instruction
|= WRITE_BACK
;
7454 /* Check for unpredictable uses of writeback. */
7455 if (inst
.instruction
& LOAD_BIT
)
7457 /* Not allowed in LDM type 2. */
7458 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7459 && ((range
& (1 << REG_PC
)) == 0))
7460 as_warn (_("writeback of base register is UNPREDICTABLE"));
7461 /* Only allowed if base reg not in list for other types. */
7462 else if (range
& (1 << base_reg
))
7463 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7467 /* Not allowed for type 2. */
7468 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7469 as_warn (_("writeback of base register is UNPREDICTABLE"));
7470 /* Only allowed if base reg not in list, or first in list. */
7471 else if ((range
& (1 << base_reg
))
7472 && (range
& ((1 << base_reg
) - 1)))
7473 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7478 /* ARMv5TE load-consecutive (argument parse)
7487 constraint (inst
.operands
[0].reg
% 2 != 0,
7488 _("first destination register must be even"));
7489 constraint (inst
.operands
[1].present
7490 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7491 _("can only load two consecutive registers"));
7492 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7493 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7495 if (!inst
.operands
[1].present
)
7496 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7498 if (inst
.instruction
& LOAD_BIT
)
7500 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7501 register and the first register written; we have to diagnose
7502 overlap between the base and the second register written here. */
7504 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7505 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7506 as_warn (_("base register written back, and overlaps "
7507 "second destination register"));
7509 /* For an index-register load, the index register must not overlap the
7510 destination (even if not write-back). */
7511 else if (inst
.operands
[2].immisreg
7512 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7513 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7514 as_warn (_("index register overlaps destination register"));
7517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7518 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7524 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7525 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7526 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7527 || inst
.operands
[1].negative
7528 /* This can arise if the programmer has written
7530 or if they have mistakenly used a register name as the last
7533 It is very difficult to distinguish between these two cases
7534 because "rX" might actually be a label. ie the register
7535 name has been occluded by a symbol of the same name. So we
7536 just generate a general 'bad addressing mode' type error
7537 message and leave it up to the programmer to discover the
7538 true cause and fix their mistake. */
7539 || (inst
.operands
[1].reg
== REG_PC
),
7542 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7543 || inst
.reloc
.exp
.X_add_number
!= 0,
7544 _("offset must be zero in ARM encoding"));
7546 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7548 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7550 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7556 constraint (inst
.operands
[0].reg
% 2 != 0,
7557 _("even register required"));
7558 constraint (inst
.operands
[1].present
7559 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7560 _("can only load two consecutive registers"));
7561 /* If op 1 were present and equal to PC, this function wouldn't
7562 have been called in the first place. */
7563 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7566 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7573 if (!inst
.operands
[1].isreg
)
7574 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7576 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7582 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7584 if (inst
.operands
[1].preind
)
7586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7587 || inst
.reloc
.exp
.X_add_number
!= 0,
7588 _("this instruction requires a post-indexed address"));
7590 inst
.operands
[1].preind
= 0;
7591 inst
.operands
[1].postind
= 1;
7592 inst
.operands
[1].writeback
= 1;
7594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7595 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7598 /* Halfword and signed-byte load/store operations. */
7603 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7605 if (!inst
.operands
[1].isreg
)
7606 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7608 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7614 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7616 if (inst
.operands
[1].preind
)
7618 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7619 || inst
.reloc
.exp
.X_add_number
!= 0,
7620 _("this instruction requires a post-indexed address"));
7622 inst
.operands
[1].preind
= 0;
7623 inst
.operands
[1].postind
= 1;
7624 inst
.operands
[1].writeback
= 1;
7626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7627 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7630 /* Co-processor register load/store.
7631 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7635 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7636 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7637 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7643 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7644 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7645 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7646 && !(inst
.instruction
& 0x00400000))
7647 as_tsktsk (_("Rd and Rm should be different in mla"));
7649 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7650 inst
.instruction
|= inst
.operands
[1].reg
;
7651 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7652 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7659 encode_arm_shifter_operand (1);
7662 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7669 top
= (inst
.instruction
& 0x00400000) != 0;
7670 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7671 _(":lower16: not allowed this instruction"));
7672 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7673 _(":upper16: not allowed instruction"));
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7675 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7677 imm
= inst
.reloc
.exp
.X_add_number
;
7678 /* The value is in two pieces: 0:11, 16:19. */
7679 inst
.instruction
|= (imm
& 0x00000fff);
7680 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7684 static void do_vfp_nsyn_opcode (const char *);
7687 do_vfp_nsyn_mrs (void)
7689 if (inst
.operands
[0].isvec
)
7691 if (inst
.operands
[1].reg
!= 1)
7692 first_error (_("operand 1 must be FPSCR"));
7693 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7694 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7695 do_vfp_nsyn_opcode ("fmstat");
7697 else if (inst
.operands
[1].isvec
)
7698 do_vfp_nsyn_opcode ("fmrx");
7706 do_vfp_nsyn_msr (void)
7708 if (inst
.operands
[0].isvec
)
7709 do_vfp_nsyn_opcode ("fmxr");
7719 unsigned Rt
= inst
.operands
[0].reg
;
7721 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7723 inst
.error
= BAD_SP
;
7727 /* APSR_ sets isvec. All other refs to PC are illegal. */
7728 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7730 inst
.error
= BAD_PC
;
7734 if (inst
.operands
[1].reg
!= 1)
7735 first_error (_("operand 1 must be FPSCR"));
7737 inst
.instruction
|= (Rt
<< 12);
7743 unsigned Rt
= inst
.operands
[1].reg
;
7746 reject_bad_reg (Rt
);
7747 else if (Rt
== REG_PC
)
7749 inst
.error
= BAD_PC
;
7753 if (inst
.operands
[0].reg
!= 1)
7754 first_error (_("operand 0 must be FPSCR"));
7756 inst
.instruction
|= (Rt
<< 12);
7762 if (do_vfp_nsyn_mrs () == SUCCESS
)
7765 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7766 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7768 _("'CPSR' or 'SPSR' expected"));
7769 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7771 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7774 /* Two possible forms:
7775 "{C|S}PSR_<field>, Rm",
7776 "{C|S}PSR_f, #expression". */
7781 if (do_vfp_nsyn_msr () == SUCCESS
)
7784 inst
.instruction
|= inst
.operands
[0].imm
;
7785 if (inst
.operands
[1].isreg
)
7786 inst
.instruction
|= inst
.operands
[1].reg
;
7789 inst
.instruction
|= INST_IMMEDIATE
;
7790 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7791 inst
.reloc
.pc_rel
= 0;
7798 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7800 if (!inst
.operands
[2].present
)
7801 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7802 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7803 inst
.instruction
|= inst
.operands
[1].reg
;
7804 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7806 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7807 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7808 as_tsktsk (_("Rd and Rm should be different in mul"));
7811 /* Long Multiply Parser
7812 UMULL RdLo, RdHi, Rm, Rs
7813 SMULL RdLo, RdHi, Rm, Rs
7814 UMLAL RdLo, RdHi, Rm, Rs
7815 SMLAL RdLo, RdHi, Rm, Rs. */
7820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7821 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7822 inst
.instruction
|= inst
.operands
[2].reg
;
7823 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7825 /* rdhi and rdlo must be different. */
7826 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7827 as_tsktsk (_("rdhi and rdlo must be different"));
7829 /* rdhi, rdlo and rm must all be different before armv6. */
7830 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7831 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7832 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7833 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7839 if (inst
.operands
[0].present
7840 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7842 /* Architectural NOP hints are CPSR sets with no bits selected. */
7843 inst
.instruction
&= 0xf0000000;
7844 inst
.instruction
|= 0x0320f000;
7845 if (inst
.operands
[0].present
)
7846 inst
.instruction
|= inst
.operands
[0].imm
;
7850 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7851 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7852 Condition defaults to COND_ALWAYS.
7853 Error if Rd, Rn or Rm are R15. */
7858 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7859 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7860 inst
.instruction
|= inst
.operands
[2].reg
;
7861 if (inst
.operands
[3].present
)
7862 encode_arm_shift (3);
7865 /* ARM V6 PKHTB (Argument Parse). */
7870 if (!inst
.operands
[3].present
)
7872 /* If the shift specifier is omitted, turn the instruction
7873 into pkhbt rd, rm, rn. */
7874 inst
.instruction
&= 0xfff00010;
7875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7876 inst
.instruction
|= inst
.operands
[1].reg
;
7877 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7883 inst
.instruction
|= inst
.operands
[2].reg
;
7884 encode_arm_shift (3);
7888 /* ARMv5TE: Preload-Cache
7892 Syntactically, like LDR with B=1, W=0, L=1. */
7897 constraint (!inst
.operands
[0].isreg
,
7898 _("'[' expected after PLD mnemonic"));
7899 constraint (inst
.operands
[0].postind
,
7900 _("post-indexed expression used in preload instruction"));
7901 constraint (inst
.operands
[0].writeback
,
7902 _("writeback used in preload instruction"));
7903 constraint (!inst
.operands
[0].preind
,
7904 _("unindexed addressing used in preload instruction"));
7905 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7908 /* ARMv7: PLI <addr_mode> */
7912 constraint (!inst
.operands
[0].isreg
,
7913 _("'[' expected after PLI mnemonic"));
7914 constraint (inst
.operands
[0].postind
,
7915 _("post-indexed expression used in preload instruction"));
7916 constraint (inst
.operands
[0].writeback
,
7917 _("writeback used in preload instruction"));
7918 constraint (!inst
.operands
[0].preind
,
7919 _("unindexed addressing used in preload instruction"));
7920 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7921 inst
.instruction
&= ~PRE_INDEX
;
7927 inst
.operands
[1] = inst
.operands
[0];
7928 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7929 inst
.operands
[0].isreg
= 1;
7930 inst
.operands
[0].writeback
= 1;
7931 inst
.operands
[0].reg
= REG_SP
;
7935 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7936 word at the specified address and the following word
7938 Unconditionally executed.
7939 Error if Rn is R15. */
7944 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7945 if (inst
.operands
[0].writeback
)
7946 inst
.instruction
|= WRITE_BACK
;
7949 /* ARM V6 ssat (argument parse). */
7954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7955 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7956 inst
.instruction
|= inst
.operands
[2].reg
;
7958 if (inst
.operands
[3].present
)
7959 encode_arm_shift (3);
7962 /* ARM V6 usat (argument parse). */
7967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7968 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7969 inst
.instruction
|= inst
.operands
[2].reg
;
7971 if (inst
.operands
[3].present
)
7972 encode_arm_shift (3);
7975 /* ARM V6 ssat16 (argument parse). */
7980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7981 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7982 inst
.instruction
|= inst
.operands
[2].reg
;
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7989 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7990 inst
.instruction
|= inst
.operands
[2].reg
;
7993 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7994 preserving the other bits.
7996 setend <endian_specifier>, where <endian_specifier> is either
8002 if (inst
.operands
[0].imm
)
8003 inst
.instruction
|= 0x200;
8009 unsigned int Rm
= (inst
.operands
[1].present
8010 ? inst
.operands
[1].reg
8011 : inst
.operands
[0].reg
);
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8014 inst
.instruction
|= Rm
;
8015 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8017 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8018 inst
.instruction
|= SHIFT_BY_REG
;
8021 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8027 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8028 inst
.reloc
.pc_rel
= 0;
8034 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8035 inst
.reloc
.pc_rel
= 0;
8038 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8039 SMLAxy{cond} Rd,Rm,Rs,Rn
8040 SMLAWy{cond} Rd,Rm,Rs,Rn
8041 Error if any register is R15. */
8046 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8047 inst
.instruction
|= inst
.operands
[1].reg
;
8048 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8049 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8052 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8053 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8054 Error if any register is R15.
8055 Warning if Rdlo == Rdhi. */
8060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8062 inst
.instruction
|= inst
.operands
[2].reg
;
8063 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8065 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8066 as_tsktsk (_("rdhi and rdlo must be different"));
8069 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8070 SMULxy{cond} Rd,Rm,Rs
8071 Error if any register is R15. */
8076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8077 inst
.instruction
|= inst
.operands
[1].reg
;
8078 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8081 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8082 the same for both ARM and Thumb-2. */
8089 if (inst
.operands
[0].present
)
8091 reg
= inst
.operands
[0].reg
;
8092 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8097 inst
.instruction
|= reg
<< 16;
8098 inst
.instruction
|= inst
.operands
[1].imm
;
8099 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8100 inst
.instruction
|= WRITE_BACK
;
8103 /* ARM V6 strex (argument parse). */
8108 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8109 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8110 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8111 || inst
.operands
[2].negative
8112 /* See comment in do_ldrex(). */
8113 || (inst
.operands
[2].reg
== REG_PC
),
8116 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8117 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8119 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8120 || inst
.reloc
.exp
.X_add_number
!= 0,
8121 _("offset must be zero in ARM encoding"));
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8124 inst
.instruction
|= inst
.operands
[1].reg
;
8125 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8126 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8132 constraint (inst
.operands
[1].reg
% 2 != 0,
8133 _("even register required"));
8134 constraint (inst
.operands
[2].present
8135 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8136 _("can only store two consecutive registers"));
8137 /* If op 2 were present and equal to PC, this function wouldn't
8138 have been called in the first place. */
8139 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8141 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8142 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8143 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8147 inst
.instruction
|= inst
.operands
[1].reg
;
8148 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8151 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8152 extends it to 32-bits, and adds the result to a value in another
8153 register. You can specify a rotation by 0, 8, 16, or 24 bits
8154 before extracting the 16-bit value.
8155 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8156 Condition defaults to COND_ALWAYS.
8157 Error if any register uses R15. */
8162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8164 inst
.instruction
|= inst
.operands
[2].reg
;
8165 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8170 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8171 Condition defaults to COND_ALWAYS.
8172 Error if any register uses R15. */
8177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8178 inst
.instruction
|= inst
.operands
[1].reg
;
8179 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8182 /* VFP instructions. In a logical order: SP variant first, monad
8183 before dyad, arithmetic then move then load/store. */
8186 do_vfp_sp_monadic (void)
8188 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8189 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8193 do_vfp_sp_dyadic (void)
8195 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8196 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8197 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8201 do_vfp_sp_compare_z (void)
8203 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8207 do_vfp_dp_sp_cvt (void)
8209 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8210 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8214 do_vfp_sp_dp_cvt (void)
8216 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8217 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8221 do_vfp_reg_from_sp (void)
8223 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8224 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8228 do_vfp_reg2_from_sp2 (void)
8230 constraint (inst
.operands
[2].imm
!= 2,
8231 _("only two consecutive VFP SP registers allowed here"));
8232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8234 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8238 do_vfp_sp_from_reg (void)
8240 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8245 do_vfp_sp2_from_reg2 (void)
8247 constraint (inst
.operands
[0].imm
!= 2,
8248 _("only two consecutive VFP SP registers allowed here"));
8249 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8250 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8251 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8255 do_vfp_sp_ldst (void)
8257 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8258 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8262 do_vfp_dp_ldst (void)
8264 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8265 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8270 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8272 if (inst
.operands
[0].writeback
)
8273 inst
.instruction
|= WRITE_BACK
;
8275 constraint (ldstm_type
!= VFP_LDSTMIA
,
8276 _("this addressing mode requires base-register writeback"));
8277 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8278 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8279 inst
.instruction
|= inst
.operands
[1].imm
;
8283 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8287 if (inst
.operands
[0].writeback
)
8288 inst
.instruction
|= WRITE_BACK
;
8290 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8291 _("this addressing mode requires base-register writeback"));
8293 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8294 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8296 count
= inst
.operands
[1].imm
<< 1;
8297 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8300 inst
.instruction
|= count
;
8304 do_vfp_sp_ldstmia (void)
8306 vfp_sp_ldstm (VFP_LDSTMIA
);
8310 do_vfp_sp_ldstmdb (void)
8312 vfp_sp_ldstm (VFP_LDSTMDB
);
8316 do_vfp_dp_ldstmia (void)
8318 vfp_dp_ldstm (VFP_LDSTMIA
);
8322 do_vfp_dp_ldstmdb (void)
8324 vfp_dp_ldstm (VFP_LDSTMDB
);
8328 do_vfp_xp_ldstmia (void)
8330 vfp_dp_ldstm (VFP_LDSTMIAX
);
8334 do_vfp_xp_ldstmdb (void)
8336 vfp_dp_ldstm (VFP_LDSTMDBX
);
8340 do_vfp_dp_rd_rm (void)
8342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8347 do_vfp_dp_rn_rd (void)
8349 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8350 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8354 do_vfp_dp_rd_rn (void)
8356 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8357 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8361 do_vfp_dp_rd_rn_rm (void)
8363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8364 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8365 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8371 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8375 do_vfp_dp_rm_rd_rn (void)
8377 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8378 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8379 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8382 /* VFPv3 instructions. */
8384 do_vfp_sp_const (void)
8386 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8387 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8388 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8392 do_vfp_dp_const (void)
8394 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8395 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8396 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8400 vfp_conv (int srcsize
)
8402 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8403 inst
.instruction
|= (immbits
& 1) << 5;
8404 inst
.instruction
|= (immbits
>> 1);
8408 do_vfp_sp_conv_16 (void)
8410 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8415 do_vfp_dp_conv_16 (void)
8417 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8422 do_vfp_sp_conv_32 (void)
8424 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8429 do_vfp_dp_conv_32 (void)
8431 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8435 /* FPA instructions. Also in a logical order. */
8440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8441 inst
.instruction
|= inst
.operands
[1].reg
;
8445 do_fpa_ldmstm (void)
8447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8448 switch (inst
.operands
[1].imm
)
8450 case 1: inst
.instruction
|= CP_T_X
; break;
8451 case 2: inst
.instruction
|= CP_T_Y
; break;
8452 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8457 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8459 /* The instruction specified "ea" or "fd", so we can only accept
8460 [Rn]{!}. The instruction does not really support stacking or
8461 unstacking, so we have to emulate these by setting appropriate
8462 bits and offsets. */
8463 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8464 || inst
.reloc
.exp
.X_add_number
!= 0,
8465 _("this instruction does not support indexing"));
8467 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8468 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8470 if (!(inst
.instruction
& INDEX_UP
))
8471 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8473 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8475 inst
.operands
[2].preind
= 0;
8476 inst
.operands
[2].postind
= 1;
8480 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8483 /* iWMMXt instructions: strictly in alphabetical order. */
8486 do_iwmmxt_tandorc (void)
8488 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8492 do_iwmmxt_textrc (void)
8494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8495 inst
.instruction
|= inst
.operands
[1].imm
;
8499 do_iwmmxt_textrm (void)
8501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8503 inst
.instruction
|= inst
.operands
[2].imm
;
8507 do_iwmmxt_tinsr (void)
8509 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8510 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8511 inst
.instruction
|= inst
.operands
[2].imm
;
8515 do_iwmmxt_tmia (void)
8517 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8518 inst
.instruction
|= inst
.operands
[1].reg
;
8519 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8523 do_iwmmxt_waligni (void)
8525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8527 inst
.instruction
|= inst
.operands
[2].reg
;
8528 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8532 do_iwmmxt_wmerge (void)
8534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8536 inst
.instruction
|= inst
.operands
[2].reg
;
8537 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8541 do_iwmmxt_wmov (void)
8543 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8545 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8546 inst
.instruction
|= inst
.operands
[1].reg
;
8550 do_iwmmxt_wldstbh (void)
8553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8555 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8557 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8558 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8562 do_iwmmxt_wldstw (void)
8564 /* RIWR_RIWC clears .isreg for a control register. */
8565 if (!inst
.operands
[0].isreg
)
8567 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8568 inst
.instruction
|= 0xf0000000;
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8576 do_iwmmxt_wldstd (void)
8578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8579 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8580 && inst
.operands
[1].immisreg
)
8582 inst
.instruction
&= ~0x1a000ff;
8583 inst
.instruction
|= (0xf << 28);
8584 if (inst
.operands
[1].preind
)
8585 inst
.instruction
|= PRE_INDEX
;
8586 if (!inst
.operands
[1].negative
)
8587 inst
.instruction
|= INDEX_UP
;
8588 if (inst
.operands
[1].writeback
)
8589 inst
.instruction
|= WRITE_BACK
;
8590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8591 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8592 inst
.instruction
|= inst
.operands
[1].imm
;
8595 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8599 do_iwmmxt_wshufh (void)
8601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8603 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8604 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8608 do_iwmmxt_wzero (void)
8610 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8611 inst
.instruction
|= inst
.operands
[0].reg
;
8612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8617 do_iwmmxt_wrwrwr_or_imm5 (void)
8619 if (inst
.operands
[2].isreg
)
8622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8623 _("immediate operand requires iWMMXt2"));
8625 if (inst
.operands
[2].imm
== 0)
8627 switch ((inst
.instruction
>> 20) & 0xf)
8633 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8634 inst
.operands
[2].imm
= 16;
8635 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8641 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8642 inst
.operands
[2].imm
= 32;
8643 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8650 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8652 wrn
= (inst
.instruction
>> 16) & 0xf;
8653 inst
.instruction
&= 0xff0fff0f;
8654 inst
.instruction
|= wrn
;
8655 /* Bail out here; the instruction is now assembled. */
8660 /* Map 32 -> 0, etc. */
8661 inst
.operands
[2].imm
&= 0x1f;
8662 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8666 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8667 operations first, then control, shift, and load/store. */
8669 /* Insns like "foo X,Y,Z". */
8672 do_mav_triple (void)
8674 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8675 inst
.instruction
|= inst
.operands
[1].reg
;
8676 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8679 /* Insns like "foo W,X,Y,Z".
8680 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8686 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8687 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8688 inst
.instruction
|= inst
.operands
[3].reg
;
8691 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8695 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8698 /* Maverick shift immediate instructions.
8699 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8700 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8705 int imm
= inst
.operands
[2].imm
;
8707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8708 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8710 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8711 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8712 Bit 4 should be 0. */
8713 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8715 inst
.instruction
|= imm
;
8718 /* XScale instructions. Also sorted arithmetic before move. */
8720 /* Xscale multiply-accumulate (argument parse)
8723 MIAxycc acc0,Rm,Rs. */
8728 inst
.instruction
|= inst
.operands
[1].reg
;
8729 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8732 /* Xscale move-accumulator-register (argument parse)
8734 MARcc acc0,RdLo,RdHi. */
8739 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8740 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8743 /* Xscale move-register-accumulator (argument parse)
8745 MRAcc RdLo,RdHi,acc0. */
8750 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8751 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8752 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8755 /* Encoding functions relevant only to Thumb. */
8757 /* inst.operands[i] is a shifted-register operand; encode
8758 it into inst.instruction in the format used by Thumb32. */
8761 encode_thumb32_shifted_operand (int i
)
8763 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8764 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8766 constraint (inst
.operands
[i
].immisreg
,
8767 _("shift by register not allowed in thumb mode"));
8768 inst
.instruction
|= inst
.operands
[i
].reg
;
8769 if (shift
== SHIFT_RRX
)
8770 inst
.instruction
|= SHIFT_ROR
<< 4;
8773 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8774 _("expression too complex"));
8776 constraint (value
> 32
8777 || (value
== 32 && (shift
== SHIFT_LSL
8778 || shift
== SHIFT_ROR
)),
8779 _("shift expression is too large"));
8783 else if (value
== 32)
8786 inst
.instruction
|= shift
<< 4;
8787 inst
.instruction
|= (value
& 0x1c) << 10;
8788 inst
.instruction
|= (value
& 0x03) << 6;
8793 /* inst.operands[i] was set up by parse_address. Encode it into a
8794 Thumb32 format load or store instruction. Reject forms that cannot
8795 be used with such instructions. If is_t is true, reject forms that
8796 cannot be used with a T instruction; if is_d is true, reject forms
8797 that cannot be used with a D instruction. If it is a store insn,
8801 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8803 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8805 constraint (!inst
.operands
[i
].isreg
,
8806 _("Instruction does not support =N addresses"));
8808 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8809 if (inst
.operands
[i
].immisreg
)
8811 constraint (is_pc
, BAD_PC_ADDRESSING
);
8812 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8813 constraint (inst
.operands
[i
].negative
,
8814 _("Thumb does not support negative register indexing"));
8815 constraint (inst
.operands
[i
].postind
,
8816 _("Thumb does not support register post-indexing"));
8817 constraint (inst
.operands
[i
].writeback
,
8818 _("Thumb does not support register indexing with writeback"));
8819 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8820 _("Thumb supports only LSL in shifted register indexing"));
8822 inst
.instruction
|= inst
.operands
[i
].imm
;
8823 if (inst
.operands
[i
].shifted
)
8825 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8826 _("expression too complex"));
8827 constraint (inst
.reloc
.exp
.X_add_number
< 0
8828 || inst
.reloc
.exp
.X_add_number
> 3,
8829 _("shift out of range"));
8830 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8832 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8834 else if (inst
.operands
[i
].preind
)
8836 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8837 constraint (is_t
&& inst
.operands
[i
].writeback
,
8838 _("cannot use writeback with this instruction"));
8839 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8840 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8844 inst
.instruction
|= 0x01000000;
8845 if (inst
.operands
[i
].writeback
)
8846 inst
.instruction
|= 0x00200000;
8850 inst
.instruction
|= 0x00000c00;
8851 if (inst
.operands
[i
].writeback
)
8852 inst
.instruction
|= 0x00000100;
8854 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8856 else if (inst
.operands
[i
].postind
)
8858 gas_assert (inst
.operands
[i
].writeback
);
8859 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8860 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8863 inst
.instruction
|= 0x00200000;
8865 inst
.instruction
|= 0x00000900;
8866 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8868 else /* unindexed - only for coprocessor */
8869 inst
.error
= _("instruction does not accept unindexed addressing");
8872 /* Table of Thumb instructions which exist in both 16- and 32-bit
8873 encodings (the latter only in post-V6T2 cores). The index is the
8874 value used in the insns table below. When there is more than one
8875 possible 16-bit encoding for the instruction, this table always
8877 Also contains several pseudo-instructions used during relaxation. */
8878 #define T16_32_TAB \
8879 X(_adc, 4140, eb400000), \
8880 X(_adcs, 4140, eb500000), \
8881 X(_add, 1c00, eb000000), \
8882 X(_adds, 1c00, eb100000), \
8883 X(_addi, 0000, f1000000), \
8884 X(_addis, 0000, f1100000), \
8885 X(_add_pc,000f, f20f0000), \
8886 X(_add_sp,000d, f10d0000), \
8887 X(_adr, 000f, f20f0000), \
8888 X(_and, 4000, ea000000), \
8889 X(_ands, 4000, ea100000), \
8890 X(_asr, 1000, fa40f000), \
8891 X(_asrs, 1000, fa50f000), \
8892 X(_b, e000, f000b000), \
8893 X(_bcond, d000, f0008000), \
8894 X(_bic, 4380, ea200000), \
8895 X(_bics, 4380, ea300000), \
8896 X(_cmn, 42c0, eb100f00), \
8897 X(_cmp, 2800, ebb00f00), \
8898 X(_cpsie, b660, f3af8400), \
8899 X(_cpsid, b670, f3af8600), \
8900 X(_cpy, 4600, ea4f0000), \
8901 X(_dec_sp,80dd, f1ad0d00), \
8902 X(_eor, 4040, ea800000), \
8903 X(_eors, 4040, ea900000), \
8904 X(_inc_sp,00dd, f10d0d00), \
8905 X(_ldmia, c800, e8900000), \
8906 X(_ldr, 6800, f8500000), \
8907 X(_ldrb, 7800, f8100000), \
8908 X(_ldrh, 8800, f8300000), \
8909 X(_ldrsb, 5600, f9100000), \
8910 X(_ldrsh, 5e00, f9300000), \
8911 X(_ldr_pc,4800, f85f0000), \
8912 X(_ldr_pc2,4800, f85f0000), \
8913 X(_ldr_sp,9800, f85d0000), \
8914 X(_lsl, 0000, fa00f000), \
8915 X(_lsls, 0000, fa10f000), \
8916 X(_lsr, 0800, fa20f000), \
8917 X(_lsrs, 0800, fa30f000), \
8918 X(_mov, 2000, ea4f0000), \
8919 X(_movs, 2000, ea5f0000), \
8920 X(_mul, 4340, fb00f000), \
8921 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8922 X(_mvn, 43c0, ea6f0000), \
8923 X(_mvns, 43c0, ea7f0000), \
8924 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8925 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8926 X(_orr, 4300, ea400000), \
8927 X(_orrs, 4300, ea500000), \
8928 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8929 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8930 X(_rev, ba00, fa90f080), \
8931 X(_rev16, ba40, fa90f090), \
8932 X(_revsh, bac0, fa90f0b0), \
8933 X(_ror, 41c0, fa60f000), \
8934 X(_rors, 41c0, fa70f000), \
8935 X(_sbc, 4180, eb600000), \
8936 X(_sbcs, 4180, eb700000), \
8937 X(_stmia, c000, e8800000), \
8938 X(_str, 6000, f8400000), \
8939 X(_strb, 7000, f8000000), \
8940 X(_strh, 8000, f8200000), \
8941 X(_str_sp,9000, f84d0000), \
8942 X(_sub, 1e00, eba00000), \
8943 X(_subs, 1e00, ebb00000), \
8944 X(_subi, 8000, f1a00000), \
8945 X(_subis, 8000, f1b00000), \
8946 X(_sxtb, b240, fa4ff080), \
8947 X(_sxth, b200, fa0ff080), \
8948 X(_tst, 4200, ea100f00), \
8949 X(_uxtb, b2c0, fa5ff080), \
8950 X(_uxth, b280, fa1ff080), \
8951 X(_nop, bf00, f3af8000), \
8952 X(_yield, bf10, f3af8001), \
8953 X(_wfe, bf20, f3af8002), \
8954 X(_wfi, bf30, f3af8003), \
8955 X(_sev, bf40, f3af8004),
8957 /* To catch errors in encoding functions, the codes are all offset by
8958 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8959 as 16-bit instructions. */
8960 #define X(a,b,c) T_MNEM##a
8961 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8964 #define X(a,b,c) 0x##b
8965 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8966 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8969 #define X(a,b,c) 0x##c
8970 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8971 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8972 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8976 /* Thumb instruction encoders, in alphabetical order. */
8981 do_t_add_sub_w (void)
8985 Rd
= inst
.operands
[0].reg
;
8986 Rn
= inst
.operands
[1].reg
;
8988 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8989 is the SP-{plus,minus}-immediate form of the instruction. */
8991 constraint (Rd
== REG_PC
, BAD_PC
);
8993 reject_bad_reg (Rd
);
8995 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8996 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8999 /* Parse an add or subtract instruction. We get here with inst.instruction
9000 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9007 Rd
= inst
.operands
[0].reg
;
9008 Rs
= (inst
.operands
[1].present
9009 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9010 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9013 set_it_insn_type_last ();
9021 flags
= (inst
.instruction
== T_MNEM_adds
9022 || inst
.instruction
== T_MNEM_subs
);
9024 narrow
= !in_it_block ();
9026 narrow
= in_it_block ();
9027 if (!inst
.operands
[2].isreg
)
9031 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9033 add
= (inst
.instruction
== T_MNEM_add
9034 || inst
.instruction
== T_MNEM_adds
);
9036 if (inst
.size_req
!= 4)
9038 /* Attempt to use a narrow opcode, with relaxation if
9040 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9041 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9042 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9043 opcode
= T_MNEM_add_sp
;
9044 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9045 opcode
= T_MNEM_add_pc
;
9046 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9049 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9051 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9055 inst
.instruction
= THUMB_OP16(opcode
);
9056 inst
.instruction
|= (Rd
<< 4) | Rs
;
9057 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9058 if (inst
.size_req
!= 2)
9059 inst
.relax
= opcode
;
9062 constraint (inst
.size_req
== 2, BAD_HIREG
);
9064 if (inst
.size_req
== 4
9065 || (inst
.size_req
!= 2 && !opcode
))
9069 constraint (add
, BAD_PC
);
9070 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9071 _("only SUBS PC, LR, #const allowed"));
9072 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9073 _("expression too complex"));
9074 constraint (inst
.reloc
.exp
.X_add_number
< 0
9075 || inst
.reloc
.exp
.X_add_number
> 0xff,
9076 _("immediate value out of range"));
9077 inst
.instruction
= T2_SUBS_PC_LR
9078 | inst
.reloc
.exp
.X_add_number
;
9079 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9082 else if (Rs
== REG_PC
)
9084 /* Always use addw/subw. */
9085 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9086 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9090 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9091 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9094 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9096 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9098 inst
.instruction
|= Rd
<< 8;
9099 inst
.instruction
|= Rs
<< 16;
9104 Rn
= inst
.operands
[2].reg
;
9105 /* See if we can do this with a 16-bit instruction. */
9106 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9108 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9113 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9114 || inst
.instruction
== T_MNEM_add
)
9117 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9121 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9123 /* Thumb-1 cores (except v6-M) require at least one high
9124 register in a narrow non flag setting add. */
9125 if (Rd
> 7 || Rn
> 7
9126 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9127 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9134 inst
.instruction
= T_OPCODE_ADD_HI
;
9135 inst
.instruction
|= (Rd
& 8) << 4;
9136 inst
.instruction
|= (Rd
& 7);
9137 inst
.instruction
|= Rn
<< 3;
9143 constraint (Rd
== REG_PC
, BAD_PC
);
9144 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9145 constraint (Rs
== REG_PC
, BAD_PC
);
9146 reject_bad_reg (Rn
);
9148 /* If we get here, it can't be done in 16 bits. */
9149 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9150 _("shift must be constant"));
9151 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9152 inst
.instruction
|= Rd
<< 8;
9153 inst
.instruction
|= Rs
<< 16;
9154 encode_thumb32_shifted_operand (2);
9159 constraint (inst
.instruction
== T_MNEM_adds
9160 || inst
.instruction
== T_MNEM_subs
,
9163 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9165 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9166 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9169 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9171 inst
.instruction
|= (Rd
<< 4) | Rs
;
9172 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9176 Rn
= inst
.operands
[2].reg
;
9177 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9179 /* We now have Rd, Rs, and Rn set to registers. */
9180 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9182 /* Can't do this for SUB. */
9183 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9184 inst
.instruction
= T_OPCODE_ADD_HI
;
9185 inst
.instruction
|= (Rd
& 8) << 4;
9186 inst
.instruction
|= (Rd
& 7);
9188 inst
.instruction
|= Rn
<< 3;
9190 inst
.instruction
|= Rs
<< 3;
9192 constraint (1, _("dest must overlap one source register"));
9196 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9197 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9198 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9208 Rd
= inst
.operands
[0].reg
;
9209 reject_bad_reg (Rd
);
9211 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9213 /* Defer to section relaxation. */
9214 inst
.relax
= inst
.instruction
;
9215 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9216 inst
.instruction
|= Rd
<< 4;
9218 else if (unified_syntax
&& inst
.size_req
!= 2)
9220 /* Generate a 32-bit opcode. */
9221 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9222 inst
.instruction
|= Rd
<< 8;
9223 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9224 inst
.reloc
.pc_rel
= 1;
9228 /* Generate a 16-bit opcode. */
9229 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9230 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9231 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9232 inst
.reloc
.pc_rel
= 1;
9234 inst
.instruction
|= Rd
<< 4;
9238 /* Arithmetic instructions for which there is just one 16-bit
9239 instruction encoding, and it allows only two low registers.
9240 For maximal compatibility with ARM syntax, we allow three register
9241 operands even when Thumb-32 instructions are not available, as long
9242 as the first two are identical. For instance, both "sbc r0,r1" and
9243 "sbc r0,r0,r1" are allowed. */
9249 Rd
= inst
.operands
[0].reg
;
9250 Rs
= (inst
.operands
[1].present
9251 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9252 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9253 Rn
= inst
.operands
[2].reg
;
9255 reject_bad_reg (Rd
);
9256 reject_bad_reg (Rs
);
9257 if (inst
.operands
[2].isreg
)
9258 reject_bad_reg (Rn
);
9262 if (!inst
.operands
[2].isreg
)
9264 /* For an immediate, we always generate a 32-bit opcode;
9265 section relaxation will shrink it later if possible. */
9266 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9267 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9268 inst
.instruction
|= Rd
<< 8;
9269 inst
.instruction
|= Rs
<< 16;
9270 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9276 /* See if we can do this with a 16-bit instruction. */
9277 if (THUMB_SETS_FLAGS (inst
.instruction
))
9278 narrow
= !in_it_block ();
9280 narrow
= in_it_block ();
9282 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9284 if (inst
.operands
[2].shifted
)
9286 if (inst
.size_req
== 4)
9292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9293 inst
.instruction
|= Rd
;
9294 inst
.instruction
|= Rn
<< 3;
9298 /* If we get here, it can't be done in 16 bits. */
9299 constraint (inst
.operands
[2].shifted
9300 && inst
.operands
[2].immisreg
,
9301 _("shift must be constant"));
9302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9303 inst
.instruction
|= Rd
<< 8;
9304 inst
.instruction
|= Rs
<< 16;
9305 encode_thumb32_shifted_operand (2);
9310 /* On its face this is a lie - the instruction does set the
9311 flags. However, the only supported mnemonic in this mode
9313 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9315 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9316 _("unshifted register required"));
9317 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9318 constraint (Rd
!= Rs
,
9319 _("dest and source1 must be the same register"));
9321 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9322 inst
.instruction
|= Rd
;
9323 inst
.instruction
|= Rn
<< 3;
9327 /* Similarly, but for instructions where the arithmetic operation is
9328 commutative, so we can allow either of them to be different from
9329 the destination operand in a 16-bit instruction. For instance, all
9330 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9337 Rd
= inst
.operands
[0].reg
;
9338 Rs
= (inst
.operands
[1].present
9339 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9340 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9341 Rn
= inst
.operands
[2].reg
;
9343 reject_bad_reg (Rd
);
9344 reject_bad_reg (Rs
);
9345 if (inst
.operands
[2].isreg
)
9346 reject_bad_reg (Rn
);
9350 if (!inst
.operands
[2].isreg
)
9352 /* For an immediate, we always generate a 32-bit opcode;
9353 section relaxation will shrink it later if possible. */
9354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9355 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9356 inst
.instruction
|= Rd
<< 8;
9357 inst
.instruction
|= Rs
<< 16;
9358 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9364 /* See if we can do this with a 16-bit instruction. */
9365 if (THUMB_SETS_FLAGS (inst
.instruction
))
9366 narrow
= !in_it_block ();
9368 narrow
= in_it_block ();
9370 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9372 if (inst
.operands
[2].shifted
)
9374 if (inst
.size_req
== 4)
9381 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9382 inst
.instruction
|= Rd
;
9383 inst
.instruction
|= Rn
<< 3;
9388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9389 inst
.instruction
|= Rd
;
9390 inst
.instruction
|= Rs
<< 3;
9395 /* If we get here, it can't be done in 16 bits. */
9396 constraint (inst
.operands
[2].shifted
9397 && inst
.operands
[2].immisreg
,
9398 _("shift must be constant"));
9399 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9400 inst
.instruction
|= Rd
<< 8;
9401 inst
.instruction
|= Rs
<< 16;
9402 encode_thumb32_shifted_operand (2);
9407 /* On its face this is a lie - the instruction does set the
9408 flags. However, the only supported mnemonic in this mode
9410 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9412 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9413 _("unshifted register required"));
9414 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9417 inst
.instruction
|= Rd
;
9420 inst
.instruction
|= Rn
<< 3;
9422 inst
.instruction
|= Rs
<< 3;
9424 constraint (1, _("dest must overlap one source register"));
9431 if (inst
.operands
[0].present
)
9433 constraint ((inst
.instruction
& 0xf0) != 0x40
9434 && inst
.operands
[0].imm
!= 0xf,
9435 _("bad barrier type"));
9436 inst
.instruction
|= inst
.operands
[0].imm
;
9439 inst
.instruction
|= 0xf;
9446 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9447 constraint (msb
> 32, _("bit-field extends past end of register"));
9448 /* The instruction encoding stores the LSB and MSB,
9449 not the LSB and width. */
9450 Rd
= inst
.operands
[0].reg
;
9451 reject_bad_reg (Rd
);
9452 inst
.instruction
|= Rd
<< 8;
9453 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9454 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9455 inst
.instruction
|= msb
- 1;
9464 Rd
= inst
.operands
[0].reg
;
9465 reject_bad_reg (Rd
);
9467 /* #0 in second position is alternative syntax for bfc, which is
9468 the same instruction but with REG_PC in the Rm field. */
9469 if (!inst
.operands
[1].isreg
)
9473 Rn
= inst
.operands
[1].reg
;
9474 reject_bad_reg (Rn
);
9477 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9478 constraint (msb
> 32, _("bit-field extends past end of register"));
9479 /* The instruction encoding stores the LSB and MSB,
9480 not the LSB and width. */
9481 inst
.instruction
|= Rd
<< 8;
9482 inst
.instruction
|= Rn
<< 16;
9483 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9484 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9485 inst
.instruction
|= msb
- 1;
9493 Rd
= inst
.operands
[0].reg
;
9494 Rn
= inst
.operands
[1].reg
;
9496 reject_bad_reg (Rd
);
9497 reject_bad_reg (Rn
);
9499 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9500 _("bit-field extends past end of register"));
9501 inst
.instruction
|= Rd
<< 8;
9502 inst
.instruction
|= Rn
<< 16;
9503 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9504 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9505 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9508 /* ARM V5 Thumb BLX (argument parse)
9509 BLX <target_addr> which is BLX(1)
9510 BLX <Rm> which is BLX(2)
9511 Unfortunately, there are two different opcodes for this mnemonic.
9512 So, the insns[].value is not used, and the code here zaps values
9513 into inst.instruction.
9515 ??? How to take advantage of the additional two bits of displacement
9516 available in Thumb32 mode? Need new relocation? */
9521 set_it_insn_type_last ();
9523 if (inst
.operands
[0].isreg
)
9525 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9526 /* We have a register, so this is BLX(2). */
9527 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9531 /* No register. This must be BLX(1). */
9532 inst
.instruction
= 0xf000e800;
9533 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9534 inst
.reloc
.pc_rel
= 1;
9545 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9549 /* Conditional branches inside IT blocks are encoded as unconditional
9556 if (cond
!= COND_ALWAYS
)
9557 opcode
= T_MNEM_bcond
;
9559 opcode
= inst
.instruction
;
9561 if (unified_syntax
&& inst
.size_req
== 4)
9563 inst
.instruction
= THUMB_OP32(opcode
);
9564 if (cond
== COND_ALWAYS
)
9565 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9568 gas_assert (cond
!= 0xF);
9569 inst
.instruction
|= cond
<< 22;
9570 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9575 inst
.instruction
= THUMB_OP16(opcode
);
9576 if (cond
== COND_ALWAYS
)
9577 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9580 inst
.instruction
|= cond
<< 8;
9581 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9583 /* Allow section relaxation. */
9584 if (unified_syntax
&& inst
.size_req
!= 2)
9585 inst
.relax
= opcode
;
9588 inst
.reloc
.pc_rel
= 1;
9594 constraint (inst
.cond
!= COND_ALWAYS
,
9595 _("instruction is always unconditional"));
9596 if (inst
.operands
[0].present
)
9598 constraint (inst
.operands
[0].imm
> 255,
9599 _("immediate value out of range"));
9600 inst
.instruction
|= inst
.operands
[0].imm
;
9601 set_it_insn_type (NEUTRAL_IT_INSN
);
9606 do_t_branch23 (void)
9608 set_it_insn_type_last ();
9609 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9610 inst
.reloc
.pc_rel
= 1;
9612 #if defined(OBJ_COFF)
9613 /* If the destination of the branch is a defined symbol which does not have
9614 the THUMB_FUNC attribute, then we must be calling a function which has
9615 the (interfacearm) attribute. We look for the Thumb entry point to that
9616 function and change the branch to refer to that function instead. */
9617 if ( inst
.reloc
.exp
.X_op
== O_symbol
9618 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9619 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9620 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9621 inst
.reloc
.exp
.X_add_symbol
=
9622 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9629 set_it_insn_type_last ();
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9631 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9632 should cause the alignment to be checked once it is known. This is
9633 because BX PC only works if the instruction is word aligned. */
9641 set_it_insn_type_last ();
9642 Rm
= inst
.operands
[0].reg
;
9643 reject_bad_reg (Rm
);
9644 inst
.instruction
|= Rm
<< 16;
9653 Rd
= inst
.operands
[0].reg
;
9654 Rm
= inst
.operands
[1].reg
;
9656 reject_bad_reg (Rd
);
9657 reject_bad_reg (Rm
);
9659 inst
.instruction
|= Rd
<< 8;
9660 inst
.instruction
|= Rm
<< 16;
9661 inst
.instruction
|= Rm
;
9667 set_it_insn_type (OUTSIDE_IT_INSN
);
9668 inst
.instruction
|= inst
.operands
[0].imm
;
9674 set_it_insn_type (OUTSIDE_IT_INSN
);
9676 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9677 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9679 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9680 inst
.instruction
= 0xf3af8000;
9681 inst
.instruction
|= imod
<< 9;
9682 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9683 if (inst
.operands
[1].present
)
9684 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9689 && (inst
.operands
[0].imm
& 4),
9690 _("selected processor does not support 'A' form "
9691 "of this instruction"));
9692 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9693 _("Thumb does not support the 2-argument "
9694 "form of this instruction"));
9695 inst
.instruction
|= inst
.operands
[0].imm
;
9699 /* THUMB CPY instruction (argument parse). */
9704 if (inst
.size_req
== 4)
9706 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9707 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9708 inst
.instruction
|= inst
.operands
[1].reg
;
9712 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9713 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9714 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9721 set_it_insn_type (OUTSIDE_IT_INSN
);
9722 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9723 inst
.instruction
|= inst
.operands
[0].reg
;
9724 inst
.reloc
.pc_rel
= 1;
9725 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9731 inst
.instruction
|= inst
.operands
[0].imm
;
9737 unsigned Rd
, Rn
, Rm
;
9739 Rd
= inst
.operands
[0].reg
;
9740 Rn
= (inst
.operands
[1].present
9741 ? inst
.operands
[1].reg
: Rd
);
9742 Rm
= inst
.operands
[2].reg
;
9744 reject_bad_reg (Rd
);
9745 reject_bad_reg (Rn
);
9746 reject_bad_reg (Rm
);
9748 inst
.instruction
|= Rd
<< 8;
9749 inst
.instruction
|= Rn
<< 16;
9750 inst
.instruction
|= Rm
;
9756 if (unified_syntax
&& inst
.size_req
== 4)
9757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9759 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9765 unsigned int cond
= inst
.operands
[0].imm
;
9767 set_it_insn_type (IT_INSN
);
9768 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9771 /* If the condition is a negative condition, invert the mask. */
9772 if ((cond
& 0x1) == 0x0)
9774 unsigned int mask
= inst
.instruction
& 0x000f;
9776 if ((mask
& 0x7) == 0)
9777 /* no conversion needed */;
9778 else if ((mask
& 0x3) == 0)
9780 else if ((mask
& 0x1) == 0)
9785 inst
.instruction
&= 0xfff0;
9786 inst
.instruction
|= mask
;
9789 inst
.instruction
|= cond
<< 4;
9792 /* Helper function used for both push/pop and ldm/stm. */
9794 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9798 load
= (inst
.instruction
& (1 << 20)) != 0;
9800 if (mask
& (1 << 13))
9801 inst
.error
= _("SP not allowed in register list");
9803 if ((mask
& (1 << base
)) != 0
9805 inst
.error
= _("having the base register in the register list when "
9806 "using write back is UNPREDICTABLE");
9810 if (mask
& (1 << 15))
9812 if (mask
& (1 << 14))
9813 inst
.error
= _("LR and PC should not both be in register list");
9815 set_it_insn_type_last ();
9820 if (mask
& (1 << 15))
9821 inst
.error
= _("PC not allowed in register list");
9824 if ((mask
& (mask
- 1)) == 0)
9826 /* Single register transfers implemented as str/ldr. */
9829 if (inst
.instruction
& (1 << 23))
9830 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9832 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9836 if (inst
.instruction
& (1 << 23))
9837 inst
.instruction
= 0x00800000; /* ia -> [base] */
9839 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9842 inst
.instruction
|= 0xf8400000;
9844 inst
.instruction
|= 0x00100000;
9846 mask
= ffs (mask
) - 1;
9850 inst
.instruction
|= WRITE_BACK
;
9852 inst
.instruction
|= mask
;
9853 inst
.instruction
|= base
<< 16;
9859 /* This really doesn't seem worth it. */
9860 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9861 _("expression too complex"));
9862 constraint (inst
.operands
[1].writeback
,
9863 _("Thumb load/store multiple does not support {reglist}^"));
9871 /* See if we can use a 16-bit instruction. */
9872 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9873 && inst
.size_req
!= 4
9874 && !(inst
.operands
[1].imm
& ~0xff))
9876 mask
= 1 << inst
.operands
[0].reg
;
9878 if (inst
.operands
[0].reg
<= 7
9879 && (inst
.instruction
== T_MNEM_stmia
9880 ? inst
.operands
[0].writeback
9881 : (inst
.operands
[0].writeback
9882 == !(inst
.operands
[1].imm
& mask
))))
9884 if (inst
.instruction
== T_MNEM_stmia
9885 && (inst
.operands
[1].imm
& mask
)
9886 && (inst
.operands
[1].imm
& (mask
- 1)))
9887 as_warn (_("value stored for r%d is UNKNOWN"),
9888 inst
.operands
[0].reg
);
9890 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9892 inst
.instruction
|= inst
.operands
[1].imm
;
9895 else if (inst
.operands
[0] .reg
== REG_SP
9896 && inst
.operands
[0].writeback
)
9898 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9899 ? T_MNEM_push
: T_MNEM_pop
);
9900 inst
.instruction
|= inst
.operands
[1].imm
;
9907 if (inst
.instruction
< 0xffff)
9908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9910 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9911 inst
.operands
[0].writeback
);
9916 constraint (inst
.operands
[0].reg
> 7
9917 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9918 constraint (inst
.instruction
!= T_MNEM_ldmia
9919 && inst
.instruction
!= T_MNEM_stmia
,
9920 _("Thumb-2 instruction only valid in unified syntax"));
9921 if (inst
.instruction
== T_MNEM_stmia
)
9923 if (!inst
.operands
[0].writeback
)
9924 as_warn (_("this instruction will write back the base register"));
9925 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9926 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9927 as_warn (_("value stored for r%d is UNKNOWN"),
9928 inst
.operands
[0].reg
);
9932 if (!inst
.operands
[0].writeback
9933 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9934 as_warn (_("this instruction will write back the base register"));
9935 else if (inst
.operands
[0].writeback
9936 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9937 as_warn (_("this instruction will not write back the base register"));
9940 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9942 inst
.instruction
|= inst
.operands
[1].imm
;
9949 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9950 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9951 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9952 || inst
.operands
[1].negative
,
9955 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9958 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9959 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9965 if (!inst
.operands
[1].present
)
9967 constraint (inst
.operands
[0].reg
== REG_LR
,
9968 _("r14 not allowed as first register "
9969 "when second register is omitted"));
9970 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9972 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9976 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9977 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9983 unsigned long opcode
;
9986 if (inst
.operands
[0].isreg
9987 && !inst
.operands
[0].preind
9988 && inst
.operands
[0].reg
== REG_PC
)
9989 set_it_insn_type_last ();
9991 opcode
= inst
.instruction
;
9994 if (!inst
.operands
[1].isreg
)
9996 if (opcode
<= 0xffff)
9997 inst
.instruction
= THUMB_OP32 (opcode
);
9998 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10001 if (inst
.operands
[1].isreg
10002 && !inst
.operands
[1].writeback
10003 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10004 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10005 && opcode
<= 0xffff
10006 && inst
.size_req
!= 4)
10008 /* Insn may have a 16-bit form. */
10009 Rn
= inst
.operands
[1].reg
;
10010 if (inst
.operands
[1].immisreg
)
10012 inst
.instruction
= THUMB_OP16 (opcode
);
10014 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10016 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10017 reject_bad_reg (inst
.operands
[1].imm
);
10019 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10020 && opcode
!= T_MNEM_ldrsb
)
10021 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10022 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10029 if (inst
.reloc
.pc_rel
)
10030 opcode
= T_MNEM_ldr_pc2
;
10032 opcode
= T_MNEM_ldr_pc
;
10036 if (opcode
== T_MNEM_ldr
)
10037 opcode
= T_MNEM_ldr_sp
;
10039 opcode
= T_MNEM_str_sp
;
10041 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10045 inst
.instruction
= inst
.operands
[0].reg
;
10046 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10048 inst
.instruction
|= THUMB_OP16 (opcode
);
10049 if (inst
.size_req
== 2)
10050 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10052 inst
.relax
= opcode
;
10056 /* Definitely a 32-bit variant. */
10058 /* Do some validations regarding addressing modes. */
10059 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10060 && opcode
!= T_MNEM_str
)
10061 reject_bad_reg (inst
.operands
[1].imm
);
10063 inst
.instruction
= THUMB_OP32 (opcode
);
10064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10065 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10069 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10071 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10073 /* Only [Rn,Rm] is acceptable. */
10074 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10075 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10076 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10077 || inst
.operands
[1].negative
,
10078 _("Thumb does not support this addressing mode"));
10079 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10083 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10084 if (!inst
.operands
[1].isreg
)
10085 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10088 constraint (!inst
.operands
[1].preind
10089 || inst
.operands
[1].shifted
10090 || inst
.operands
[1].writeback
,
10091 _("Thumb does not support this addressing mode"));
10092 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10094 constraint (inst
.instruction
& 0x0600,
10095 _("byte or halfword not valid for base register"));
10096 constraint (inst
.operands
[1].reg
== REG_PC
10097 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10098 _("r15 based store not allowed"));
10099 constraint (inst
.operands
[1].immisreg
,
10100 _("invalid base register for register offset"));
10102 if (inst
.operands
[1].reg
== REG_PC
)
10103 inst
.instruction
= T_OPCODE_LDR_PC
;
10104 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10105 inst
.instruction
= T_OPCODE_LDR_SP
;
10107 inst
.instruction
= T_OPCODE_STR_SP
;
10109 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10110 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10114 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10115 if (!inst
.operands
[1].immisreg
)
10117 /* Immediate offset. */
10118 inst
.instruction
|= inst
.operands
[0].reg
;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10120 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10124 /* Register offset. */
10125 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10126 constraint (inst
.operands
[1].negative
,
10127 _("Thumb does not support this addressing mode"));
10130 switch (inst
.instruction
)
10132 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10133 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10134 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10135 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10136 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10137 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10138 case 0x5600 /* ldrsb */:
10139 case 0x5e00 /* ldrsh */: break;
10143 inst
.instruction
|= inst
.operands
[0].reg
;
10144 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10145 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10151 if (!inst
.operands
[1].present
)
10153 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10154 constraint (inst
.operands
[0].reg
== REG_LR
,
10155 _("r14 not allowed here"));
10157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10159 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10166 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10172 unsigned Rd
, Rn
, Rm
, Ra
;
10174 Rd
= inst
.operands
[0].reg
;
10175 Rn
= inst
.operands
[1].reg
;
10176 Rm
= inst
.operands
[2].reg
;
10177 Ra
= inst
.operands
[3].reg
;
10179 reject_bad_reg (Rd
);
10180 reject_bad_reg (Rn
);
10181 reject_bad_reg (Rm
);
10182 reject_bad_reg (Ra
);
10184 inst
.instruction
|= Rd
<< 8;
10185 inst
.instruction
|= Rn
<< 16;
10186 inst
.instruction
|= Rm
;
10187 inst
.instruction
|= Ra
<< 12;
10193 unsigned RdLo
, RdHi
, Rn
, Rm
;
10195 RdLo
= inst
.operands
[0].reg
;
10196 RdHi
= inst
.operands
[1].reg
;
10197 Rn
= inst
.operands
[2].reg
;
10198 Rm
= inst
.operands
[3].reg
;
10200 reject_bad_reg (RdLo
);
10201 reject_bad_reg (RdHi
);
10202 reject_bad_reg (Rn
);
10203 reject_bad_reg (Rm
);
10205 inst
.instruction
|= RdLo
<< 12;
10206 inst
.instruction
|= RdHi
<< 8;
10207 inst
.instruction
|= Rn
<< 16;
10208 inst
.instruction
|= Rm
;
10212 do_t_mov_cmp (void)
10216 Rn
= inst
.operands
[0].reg
;
10217 Rm
= inst
.operands
[1].reg
;
10220 set_it_insn_type_last ();
10222 if (unified_syntax
)
10224 int r0off
= (inst
.instruction
== T_MNEM_mov
10225 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10226 unsigned long opcode
;
10227 bfd_boolean narrow
;
10228 bfd_boolean low_regs
;
10230 low_regs
= (Rn
<= 7 && Rm
<= 7);
10231 opcode
= inst
.instruction
;
10232 if (in_it_block ())
10233 narrow
= opcode
!= T_MNEM_movs
;
10235 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10236 if (inst
.size_req
== 4
10237 || inst
.operands
[1].shifted
)
10240 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10241 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10242 && !inst
.operands
[1].shifted
10246 inst
.instruction
= T2_SUBS_PC_LR
;
10250 if (opcode
== T_MNEM_cmp
)
10252 constraint (Rn
== REG_PC
, BAD_PC
);
10255 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10257 warn_deprecated_sp (Rm
);
10258 /* R15 was documented as a valid choice for Rm in ARMv6,
10259 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10260 tools reject R15, so we do too. */
10261 constraint (Rm
== REG_PC
, BAD_PC
);
10264 reject_bad_reg (Rm
);
10266 else if (opcode
== T_MNEM_mov
10267 || opcode
== T_MNEM_movs
)
10269 if (inst
.operands
[1].isreg
)
10271 if (opcode
== T_MNEM_movs
)
10273 reject_bad_reg (Rn
);
10274 reject_bad_reg (Rm
);
10278 /* This is mov.n. */
10279 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10280 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10282 as_warn (_("Use of r%u as a source register is "
10283 "deprecated when r%u is the destination "
10284 "register."), Rm
, Rn
);
10289 /* This is mov.w. */
10290 constraint (Rn
== REG_PC
, BAD_PC
);
10291 constraint (Rm
== REG_PC
, BAD_PC
);
10292 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10296 reject_bad_reg (Rn
);
10299 if (!inst
.operands
[1].isreg
)
10301 /* Immediate operand. */
10302 if (!in_it_block () && opcode
== T_MNEM_mov
)
10304 if (low_regs
&& narrow
)
10306 inst
.instruction
= THUMB_OP16 (opcode
);
10307 inst
.instruction
|= Rn
<< 8;
10308 if (inst
.size_req
== 2)
10309 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10311 inst
.relax
= opcode
;
10315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10316 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10317 inst
.instruction
|= Rn
<< r0off
;
10318 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10321 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10322 && (inst
.instruction
== T_MNEM_mov
10323 || inst
.instruction
== T_MNEM_movs
))
10325 /* Register shifts are encoded as separate shift instructions. */
10326 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10328 if (in_it_block ())
10333 if (inst
.size_req
== 4)
10336 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10342 switch (inst
.operands
[1].shift_kind
)
10345 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10348 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10351 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10354 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10360 inst
.instruction
= opcode
;
10363 inst
.instruction
|= Rn
;
10364 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10369 inst
.instruction
|= CONDS_BIT
;
10371 inst
.instruction
|= Rn
<< 8;
10372 inst
.instruction
|= Rm
<< 16;
10373 inst
.instruction
|= inst
.operands
[1].imm
;
10378 /* Some mov with immediate shift have narrow variants.
10379 Register shifts are handled above. */
10380 if (low_regs
&& inst
.operands
[1].shifted
10381 && (inst
.instruction
== T_MNEM_mov
10382 || inst
.instruction
== T_MNEM_movs
))
10384 if (in_it_block ())
10385 narrow
= (inst
.instruction
== T_MNEM_mov
);
10387 narrow
= (inst
.instruction
== T_MNEM_movs
);
10392 switch (inst
.operands
[1].shift_kind
)
10394 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10395 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10396 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10397 default: narrow
= FALSE
; break;
10403 inst
.instruction
|= Rn
;
10404 inst
.instruction
|= Rm
<< 3;
10405 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10409 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10410 inst
.instruction
|= Rn
<< r0off
;
10411 encode_thumb32_shifted_operand (1);
10415 switch (inst
.instruction
)
10418 inst
.instruction
= T_OPCODE_MOV_HR
;
10419 inst
.instruction
|= (Rn
& 0x8) << 4;
10420 inst
.instruction
|= (Rn
& 0x7);
10421 inst
.instruction
|= Rm
<< 3;
10425 /* We know we have low registers at this point.
10426 Generate LSLS Rd, Rs, #0. */
10427 inst
.instruction
= T_OPCODE_LSL_I
;
10428 inst
.instruction
|= Rn
;
10429 inst
.instruction
|= Rm
<< 3;
10435 inst
.instruction
= T_OPCODE_CMP_LR
;
10436 inst
.instruction
|= Rn
;
10437 inst
.instruction
|= Rm
<< 3;
10441 inst
.instruction
= T_OPCODE_CMP_HR
;
10442 inst
.instruction
|= (Rn
& 0x8) << 4;
10443 inst
.instruction
|= (Rn
& 0x7);
10444 inst
.instruction
|= Rm
<< 3;
10451 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10453 /* PR 10443: Do not silently ignore shifted operands. */
10454 constraint (inst
.operands
[1].shifted
,
10455 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10457 if (inst
.operands
[1].isreg
)
10459 if (Rn
< 8 && Rm
< 8)
10461 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10462 since a MOV instruction produces unpredictable results. */
10463 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10464 inst
.instruction
= T_OPCODE_ADD_I3
;
10466 inst
.instruction
= T_OPCODE_CMP_LR
;
10468 inst
.instruction
|= Rn
;
10469 inst
.instruction
|= Rm
<< 3;
10473 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10474 inst
.instruction
= T_OPCODE_MOV_HR
;
10476 inst
.instruction
= T_OPCODE_CMP_HR
;
10482 constraint (Rn
> 7,
10483 _("only lo regs allowed with immediate"));
10484 inst
.instruction
|= Rn
<< 8;
10485 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10496 top
= (inst
.instruction
& 0x00800000) != 0;
10497 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10499 constraint (top
, _(":lower16: not allowed this instruction"));
10500 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10502 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10504 constraint (!top
, _(":upper16: not allowed this instruction"));
10505 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10508 Rd
= inst
.operands
[0].reg
;
10509 reject_bad_reg (Rd
);
10511 inst
.instruction
|= Rd
<< 8;
10512 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10514 imm
= inst
.reloc
.exp
.X_add_number
;
10515 inst
.instruction
|= (imm
& 0xf000) << 4;
10516 inst
.instruction
|= (imm
& 0x0800) << 15;
10517 inst
.instruction
|= (imm
& 0x0700) << 4;
10518 inst
.instruction
|= (imm
& 0x00ff);
10523 do_t_mvn_tst (void)
10527 Rn
= inst
.operands
[0].reg
;
10528 Rm
= inst
.operands
[1].reg
;
10530 if (inst
.instruction
== T_MNEM_cmp
10531 || inst
.instruction
== T_MNEM_cmn
)
10532 constraint (Rn
== REG_PC
, BAD_PC
);
10534 reject_bad_reg (Rn
);
10535 reject_bad_reg (Rm
);
10537 if (unified_syntax
)
10539 int r0off
= (inst
.instruction
== T_MNEM_mvn
10540 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10541 bfd_boolean narrow
;
10543 if (inst
.size_req
== 4
10544 || inst
.instruction
> 0xffff
10545 || inst
.operands
[1].shifted
10546 || Rn
> 7 || Rm
> 7)
10548 else if (inst
.instruction
== T_MNEM_cmn
)
10550 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10551 narrow
= !in_it_block ();
10553 narrow
= in_it_block ();
10555 if (!inst
.operands
[1].isreg
)
10557 /* For an immediate, we always generate a 32-bit opcode;
10558 section relaxation will shrink it later if possible. */
10559 if (inst
.instruction
< 0xffff)
10560 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10561 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10562 inst
.instruction
|= Rn
<< r0off
;
10563 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10567 /* See if we can do this with a 16-bit instruction. */
10570 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10571 inst
.instruction
|= Rn
;
10572 inst
.instruction
|= Rm
<< 3;
10576 constraint (inst
.operands
[1].shifted
10577 && inst
.operands
[1].immisreg
,
10578 _("shift must be constant"));
10579 if (inst
.instruction
< 0xffff)
10580 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10581 inst
.instruction
|= Rn
<< r0off
;
10582 encode_thumb32_shifted_operand (1);
10588 constraint (inst
.instruction
> 0xffff
10589 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10590 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10591 _("unshifted register required"));
10592 constraint (Rn
> 7 || Rm
> 7,
10595 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10596 inst
.instruction
|= Rn
;
10597 inst
.instruction
|= Rm
<< 3;
10607 if (do_vfp_nsyn_mrs () == SUCCESS
)
10610 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10613 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10614 _("selected processor does not support "
10615 "requested special purpose register"));
10619 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10620 _("selected processor does not support "
10621 "requested special purpose register"));
10622 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10623 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10624 _("'CPSR' or 'SPSR' expected"));
10627 Rd
= inst
.operands
[0].reg
;
10628 reject_bad_reg (Rd
);
10630 inst
.instruction
|= Rd
<< 8;
10631 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10632 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10641 if (do_vfp_nsyn_msr () == SUCCESS
)
10644 constraint (!inst
.operands
[1].isreg
,
10645 _("Thumb encoding does not support an immediate here"));
10646 flags
= inst
.operands
[0].imm
;
10649 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10650 _("selected processor does not support "
10651 "requested special purpose register"));
10655 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10656 _("selected processor does not support "
10657 "requested special purpose register"));
10661 Rn
= inst
.operands
[1].reg
;
10662 reject_bad_reg (Rn
);
10664 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10665 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10666 inst
.instruction
|= (flags
& 0xff);
10667 inst
.instruction
|= Rn
<< 16;
10673 bfd_boolean narrow
;
10674 unsigned Rd
, Rn
, Rm
;
10676 if (!inst
.operands
[2].present
)
10677 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10679 Rd
= inst
.operands
[0].reg
;
10680 Rn
= inst
.operands
[1].reg
;
10681 Rm
= inst
.operands
[2].reg
;
10683 if (unified_syntax
)
10685 if (inst
.size_req
== 4
10691 else if (inst
.instruction
== T_MNEM_muls
)
10692 narrow
= !in_it_block ();
10694 narrow
= in_it_block ();
10698 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10699 constraint (Rn
> 7 || Rm
> 7,
10706 /* 16-bit MULS/Conditional MUL. */
10707 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10708 inst
.instruction
|= Rd
;
10711 inst
.instruction
|= Rm
<< 3;
10713 inst
.instruction
|= Rn
<< 3;
10715 constraint (1, _("dest must overlap one source register"));
10719 constraint (inst
.instruction
!= T_MNEM_mul
,
10720 _("Thumb-2 MUL must not set flags"));
10722 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10723 inst
.instruction
|= Rd
<< 8;
10724 inst
.instruction
|= Rn
<< 16;
10725 inst
.instruction
|= Rm
<< 0;
10727 reject_bad_reg (Rd
);
10728 reject_bad_reg (Rn
);
10729 reject_bad_reg (Rm
);
10736 unsigned RdLo
, RdHi
, Rn
, Rm
;
10738 RdLo
= inst
.operands
[0].reg
;
10739 RdHi
= inst
.operands
[1].reg
;
10740 Rn
= inst
.operands
[2].reg
;
10741 Rm
= inst
.operands
[3].reg
;
10743 reject_bad_reg (RdLo
);
10744 reject_bad_reg (RdHi
);
10745 reject_bad_reg (Rn
);
10746 reject_bad_reg (Rm
);
10748 inst
.instruction
|= RdLo
<< 12;
10749 inst
.instruction
|= RdHi
<< 8;
10750 inst
.instruction
|= Rn
<< 16;
10751 inst
.instruction
|= Rm
;
10754 as_tsktsk (_("rdhi and rdlo must be different"));
10760 set_it_insn_type (NEUTRAL_IT_INSN
);
10762 if (unified_syntax
)
10764 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10766 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10767 inst
.instruction
|= inst
.operands
[0].imm
;
10771 /* PR9722: Check for Thumb2 availability before
10772 generating a thumb2 nop instruction. */
10773 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10775 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10776 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10779 inst
.instruction
= 0x46c0;
10784 constraint (inst
.operands
[0].present
,
10785 _("Thumb does not support NOP with hints"));
10786 inst
.instruction
= 0x46c0;
10793 if (unified_syntax
)
10795 bfd_boolean narrow
;
10797 if (THUMB_SETS_FLAGS (inst
.instruction
))
10798 narrow
= !in_it_block ();
10800 narrow
= in_it_block ();
10801 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10803 if (inst
.size_req
== 4)
10808 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10809 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10814 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10815 inst
.instruction
|= inst
.operands
[0].reg
;
10816 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10821 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10823 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10825 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10826 inst
.instruction
|= inst
.operands
[0].reg
;
10827 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10836 Rd
= inst
.operands
[0].reg
;
10837 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10839 reject_bad_reg (Rd
);
10840 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10841 reject_bad_reg (Rn
);
10843 inst
.instruction
|= Rd
<< 8;
10844 inst
.instruction
|= Rn
<< 16;
10846 if (!inst
.operands
[2].isreg
)
10848 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10849 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10855 Rm
= inst
.operands
[2].reg
;
10856 reject_bad_reg (Rm
);
10858 constraint (inst
.operands
[2].shifted
10859 && inst
.operands
[2].immisreg
,
10860 _("shift must be constant"));
10861 encode_thumb32_shifted_operand (2);
10868 unsigned Rd
, Rn
, Rm
;
10870 Rd
= inst
.operands
[0].reg
;
10871 Rn
= inst
.operands
[1].reg
;
10872 Rm
= inst
.operands
[2].reg
;
10874 reject_bad_reg (Rd
);
10875 reject_bad_reg (Rn
);
10876 reject_bad_reg (Rm
);
10878 inst
.instruction
|= Rd
<< 8;
10879 inst
.instruction
|= Rn
<< 16;
10880 inst
.instruction
|= Rm
;
10881 if (inst
.operands
[3].present
)
10883 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10884 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10885 _("expression too complex"));
10886 inst
.instruction
|= (val
& 0x1c) << 10;
10887 inst
.instruction
|= (val
& 0x03) << 6;
10894 if (!inst
.operands
[3].present
)
10898 inst
.instruction
&= ~0x00000020;
10900 /* PR 10168. Swap the Rm and Rn registers. */
10901 Rtmp
= inst
.operands
[1].reg
;
10902 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10903 inst
.operands
[2].reg
= Rtmp
;
10911 if (inst
.operands
[0].immisreg
)
10912 reject_bad_reg (inst
.operands
[0].imm
);
10914 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10918 do_t_push_pop (void)
10922 constraint (inst
.operands
[0].writeback
,
10923 _("push/pop do not support {reglist}^"));
10924 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10925 _("expression too complex"));
10927 mask
= inst
.operands
[0].imm
;
10928 if ((mask
& ~0xff) == 0)
10929 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10930 else if ((inst
.instruction
== T_MNEM_push
10931 && (mask
& ~0xff) == 1 << REG_LR
)
10932 || (inst
.instruction
== T_MNEM_pop
10933 && (mask
& ~0xff) == 1 << REG_PC
))
10935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10936 inst
.instruction
|= THUMB_PP_PC_LR
;
10937 inst
.instruction
|= mask
& 0xff;
10939 else if (unified_syntax
)
10941 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10942 encode_thumb2_ldmstm (13, mask
, TRUE
);
10946 inst
.error
= _("invalid register list to push/pop instruction");
10956 Rd
= inst
.operands
[0].reg
;
10957 Rm
= inst
.operands
[1].reg
;
10959 reject_bad_reg (Rd
);
10960 reject_bad_reg (Rm
);
10962 inst
.instruction
|= Rd
<< 8;
10963 inst
.instruction
|= Rm
<< 16;
10964 inst
.instruction
|= Rm
;
10972 Rd
= inst
.operands
[0].reg
;
10973 Rm
= inst
.operands
[1].reg
;
10975 reject_bad_reg (Rd
);
10976 reject_bad_reg (Rm
);
10978 if (Rd
<= 7 && Rm
<= 7
10979 && inst
.size_req
!= 4)
10981 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10982 inst
.instruction
|= Rd
;
10983 inst
.instruction
|= Rm
<< 3;
10985 else if (unified_syntax
)
10987 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10988 inst
.instruction
|= Rd
<< 8;
10989 inst
.instruction
|= Rm
<< 16;
10990 inst
.instruction
|= Rm
;
10993 inst
.error
= BAD_HIREG
;
11001 Rd
= inst
.operands
[0].reg
;
11002 Rm
= inst
.operands
[1].reg
;
11004 reject_bad_reg (Rd
);
11005 reject_bad_reg (Rm
);
11007 inst
.instruction
|= Rd
<< 8;
11008 inst
.instruction
|= Rm
;
11016 Rd
= inst
.operands
[0].reg
;
11017 Rs
= (inst
.operands
[1].present
11018 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11019 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11021 reject_bad_reg (Rd
);
11022 reject_bad_reg (Rs
);
11023 if (inst
.operands
[2].isreg
)
11024 reject_bad_reg (inst
.operands
[2].reg
);
11026 inst
.instruction
|= Rd
<< 8;
11027 inst
.instruction
|= Rs
<< 16;
11028 if (!inst
.operands
[2].isreg
)
11030 bfd_boolean narrow
;
11032 if ((inst
.instruction
& 0x00100000) != 0)
11033 narrow
= !in_it_block ();
11035 narrow
= in_it_block ();
11037 if (Rd
> 7 || Rs
> 7)
11040 if (inst
.size_req
== 4 || !unified_syntax
)
11043 if (inst
.reloc
.exp
.X_op
!= O_constant
11044 || inst
.reloc
.exp
.X_add_number
!= 0)
11047 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11048 relaxation, but it doesn't seem worth the hassle. */
11051 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11052 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11053 inst
.instruction
|= Rs
<< 3;
11054 inst
.instruction
|= Rd
;
11058 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11059 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11063 encode_thumb32_shifted_operand (2);
11069 set_it_insn_type (OUTSIDE_IT_INSN
);
11070 if (inst
.operands
[0].imm
)
11071 inst
.instruction
|= 0x8;
11077 if (!inst
.operands
[1].present
)
11078 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11080 if (unified_syntax
)
11082 bfd_boolean narrow
;
11085 switch (inst
.instruction
)
11088 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11090 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11092 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11094 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11098 if (THUMB_SETS_FLAGS (inst
.instruction
))
11099 narrow
= !in_it_block ();
11101 narrow
= in_it_block ();
11102 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11104 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11106 if (inst
.operands
[2].isreg
11107 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11108 || inst
.operands
[2].reg
> 7))
11110 if (inst
.size_req
== 4)
11113 reject_bad_reg (inst
.operands
[0].reg
);
11114 reject_bad_reg (inst
.operands
[1].reg
);
11118 if (inst
.operands
[2].isreg
)
11120 reject_bad_reg (inst
.operands
[2].reg
);
11121 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11122 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11124 inst
.instruction
|= inst
.operands
[2].reg
;
11128 inst
.operands
[1].shifted
= 1;
11129 inst
.operands
[1].shift_kind
= shift_kind
;
11130 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11131 ? T_MNEM_movs
: T_MNEM_mov
);
11132 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11133 encode_thumb32_shifted_operand (1);
11134 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11135 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11140 if (inst
.operands
[2].isreg
)
11142 switch (shift_kind
)
11144 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11145 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11146 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11147 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11151 inst
.instruction
|= inst
.operands
[0].reg
;
11152 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11156 switch (shift_kind
)
11158 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11159 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11160 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11163 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11164 inst
.instruction
|= inst
.operands
[0].reg
;
11165 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11171 constraint (inst
.operands
[0].reg
> 7
11172 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11173 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11175 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11177 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11178 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11179 _("source1 and dest must be same register"));
11181 switch (inst
.instruction
)
11183 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11184 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11185 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11186 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11190 inst
.instruction
|= inst
.operands
[0].reg
;
11191 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11195 switch (inst
.instruction
)
11197 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11198 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11199 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11200 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11203 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11204 inst
.instruction
|= inst
.operands
[0].reg
;
11205 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11213 unsigned Rd
, Rn
, Rm
;
11215 Rd
= inst
.operands
[0].reg
;
11216 Rn
= inst
.operands
[1].reg
;
11217 Rm
= inst
.operands
[2].reg
;
11219 reject_bad_reg (Rd
);
11220 reject_bad_reg (Rn
);
11221 reject_bad_reg (Rm
);
11223 inst
.instruction
|= Rd
<< 8;
11224 inst
.instruction
|= Rn
<< 16;
11225 inst
.instruction
|= Rm
;
11231 unsigned Rd
, Rn
, Rm
;
11233 Rd
= inst
.operands
[0].reg
;
11234 Rm
= inst
.operands
[1].reg
;
11235 Rn
= inst
.operands
[2].reg
;
11237 reject_bad_reg (Rd
);
11238 reject_bad_reg (Rn
);
11239 reject_bad_reg (Rm
);
11241 inst
.instruction
|= Rd
<< 8;
11242 inst
.instruction
|= Rn
<< 16;
11243 inst
.instruction
|= Rm
;
11249 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11250 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11251 _("expression too complex"));
11252 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11253 inst
.instruction
|= (value
& 0xf000) >> 12;
11254 inst
.instruction
|= (value
& 0x0ff0);
11255 inst
.instruction
|= (value
& 0x000f) << 16;
11259 do_t_ssat_usat (int bias
)
11263 Rd
= inst
.operands
[0].reg
;
11264 Rn
= inst
.operands
[2].reg
;
11266 reject_bad_reg (Rd
);
11267 reject_bad_reg (Rn
);
11269 inst
.instruction
|= Rd
<< 8;
11270 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11271 inst
.instruction
|= Rn
<< 16;
11273 if (inst
.operands
[3].present
)
11275 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11277 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11279 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11280 _("expression too complex"));
11282 if (shift_amount
!= 0)
11284 constraint (shift_amount
> 31,
11285 _("shift expression is too large"));
11287 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11288 inst
.instruction
|= 0x00200000; /* sh bit. */
11290 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11291 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11299 do_t_ssat_usat (1);
11307 Rd
= inst
.operands
[0].reg
;
11308 Rn
= inst
.operands
[2].reg
;
11310 reject_bad_reg (Rd
);
11311 reject_bad_reg (Rn
);
11313 inst
.instruction
|= Rd
<< 8;
11314 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11315 inst
.instruction
|= Rn
<< 16;
11321 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11322 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11323 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11324 || inst
.operands
[2].negative
,
11327 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11329 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11330 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11331 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11332 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11338 if (!inst
.operands
[2].present
)
11339 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11341 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11342 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11343 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11346 inst
.instruction
|= inst
.operands
[0].reg
;
11347 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11348 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11349 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11355 unsigned Rd
, Rn
, Rm
;
11357 Rd
= inst
.operands
[0].reg
;
11358 Rn
= inst
.operands
[1].reg
;
11359 Rm
= inst
.operands
[2].reg
;
11361 reject_bad_reg (Rd
);
11362 reject_bad_reg (Rn
);
11363 reject_bad_reg (Rm
);
11365 inst
.instruction
|= Rd
<< 8;
11366 inst
.instruction
|= Rn
<< 16;
11367 inst
.instruction
|= Rm
;
11368 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11376 Rd
= inst
.operands
[0].reg
;
11377 Rm
= inst
.operands
[1].reg
;
11379 reject_bad_reg (Rd
);
11380 reject_bad_reg (Rm
);
11382 if (inst
.instruction
<= 0xffff
11383 && inst
.size_req
!= 4
11384 && Rd
<= 7 && Rm
<= 7
11385 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11387 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11388 inst
.instruction
|= Rd
;
11389 inst
.instruction
|= Rm
<< 3;
11391 else if (unified_syntax
)
11393 if (inst
.instruction
<= 0xffff)
11394 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11395 inst
.instruction
|= Rd
<< 8;
11396 inst
.instruction
|= Rm
;
11397 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11401 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11402 _("Thumb encoding does not support rotation"));
11403 constraint (1, BAD_HIREG
);
11410 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11419 half
= (inst
.instruction
& 0x10) != 0;
11420 set_it_insn_type_last ();
11421 constraint (inst
.operands
[0].immisreg
,
11422 _("instruction requires register index"));
11424 Rn
= inst
.operands
[0].reg
;
11425 Rm
= inst
.operands
[0].imm
;
11427 constraint (Rn
== REG_SP
, BAD_SP
);
11428 reject_bad_reg (Rm
);
11430 constraint (!half
&& inst
.operands
[0].shifted
,
11431 _("instruction does not allow shifted index"));
11432 inst
.instruction
|= (Rn
<< 16) | Rm
;
11438 do_t_ssat_usat (0);
11446 Rd
= inst
.operands
[0].reg
;
11447 Rn
= inst
.operands
[2].reg
;
11449 reject_bad_reg (Rd
);
11450 reject_bad_reg (Rn
);
11452 inst
.instruction
|= Rd
<< 8;
11453 inst
.instruction
|= inst
.operands
[1].imm
;
11454 inst
.instruction
|= Rn
<< 16;
11457 /* Neon instruction encoder helpers. */
11459 /* Encodings for the different types for various Neon opcodes. */
11461 /* An "invalid" code for the following tables. */
11464 struct neon_tab_entry
11467 unsigned float_or_poly
;
11468 unsigned scalar_or_imm
;
11471 /* Map overloaded Neon opcodes to their respective encodings. */
11472 #define NEON_ENC_TAB \
11473 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11474 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11475 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11476 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11477 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11478 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11479 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11480 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11481 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11482 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11483 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11484 /* Register variants of the following two instructions are encoded as
11485 vcge / vcgt with the operands reversed. */ \
11486 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11487 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11488 X(vfma, N_INV, 0x0000c10, N_INV), \
11489 X(vfms, N_INV, 0x0200c10, N_INV), \
11490 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11491 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11492 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11493 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11494 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11495 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11496 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11497 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11498 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11499 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11500 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11501 X(vshl, 0x0000400, N_INV, 0x0800510), \
11502 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11503 X(vand, 0x0000110, N_INV, 0x0800030), \
11504 X(vbic, 0x0100110, N_INV, 0x0800030), \
11505 X(veor, 0x1000110, N_INV, N_INV), \
11506 X(vorn, 0x0300110, N_INV, 0x0800010), \
11507 X(vorr, 0x0200110, N_INV, 0x0800010), \
11508 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11509 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11510 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11511 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11512 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11513 X(vst1, 0x0000000, 0x0800000, N_INV), \
11514 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11515 X(vst2, 0x0000100, 0x0800100, N_INV), \
11516 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11517 X(vst3, 0x0000200, 0x0800200, N_INV), \
11518 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11519 X(vst4, 0x0000300, 0x0800300, N_INV), \
11520 X(vmovn, 0x1b20200, N_INV, N_INV), \
11521 X(vtrn, 0x1b20080, N_INV, N_INV), \
11522 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11523 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11524 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11525 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11526 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11527 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11528 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11529 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11530 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11531 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11532 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11536 #define X(OPC,I,F,S) N_MNEM_##OPC
11541 static const struct neon_tab_entry neon_enc_tab
[] =
11543 #define X(OPC,I,F,S) { (I), (F), (S) }
11548 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11549 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11550 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11551 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11552 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11553 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11554 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11555 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11556 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11557 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11558 #define NEON_ENC_SINGLE_(X) \
11559 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11560 #define NEON_ENC_DOUBLE_(X) \
11561 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11563 #define NEON_ENCODE(type, inst) \
11566 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11567 inst.is_neon = 1; \
11571 #define check_neon_suffixes \
11574 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11576 as_bad (_("invalid neon suffix for non neon instruction")); \
11582 /* Define shapes for instruction operands. The following mnemonic characters
11583 are used in this table:
11585 F - VFP S<n> register
11586 D - Neon D<n> register
11587 Q - Neon Q<n> register
11591 L - D<n> register list
11593 This table is used to generate various data:
11594 - enumerations of the form NS_DDR to be used as arguments to
11596 - a table classifying shapes into single, double, quad, mixed.
11597 - a table used to drive neon_select_shape. */
11599 #define NEON_SHAPE_DEF \
11600 X(3, (D, D, D), DOUBLE), \
11601 X(3, (Q, Q, Q), QUAD), \
11602 X(3, (D, D, I), DOUBLE), \
11603 X(3, (Q, Q, I), QUAD), \
11604 X(3, (D, D, S), DOUBLE), \
11605 X(3, (Q, Q, S), QUAD), \
11606 X(2, (D, D), DOUBLE), \
11607 X(2, (Q, Q), QUAD), \
11608 X(2, (D, S), DOUBLE), \
11609 X(2, (Q, S), QUAD), \
11610 X(2, (D, R), DOUBLE), \
11611 X(2, (Q, R), QUAD), \
11612 X(2, (D, I), DOUBLE), \
11613 X(2, (Q, I), QUAD), \
11614 X(3, (D, L, D), DOUBLE), \
11615 X(2, (D, Q), MIXED), \
11616 X(2, (Q, D), MIXED), \
11617 X(3, (D, Q, I), MIXED), \
11618 X(3, (Q, D, I), MIXED), \
11619 X(3, (Q, D, D), MIXED), \
11620 X(3, (D, Q, Q), MIXED), \
11621 X(3, (Q, Q, D), MIXED), \
11622 X(3, (Q, D, S), MIXED), \
11623 X(3, (D, Q, S), MIXED), \
11624 X(4, (D, D, D, I), DOUBLE), \
11625 X(4, (Q, Q, Q, I), QUAD), \
11626 X(2, (F, F), SINGLE), \
11627 X(3, (F, F, F), SINGLE), \
11628 X(2, (F, I), SINGLE), \
11629 X(2, (F, D), MIXED), \
11630 X(2, (D, F), MIXED), \
11631 X(3, (F, F, I), MIXED), \
11632 X(4, (R, R, F, F), SINGLE), \
11633 X(4, (F, F, R, R), SINGLE), \
11634 X(3, (D, R, R), DOUBLE), \
11635 X(3, (R, R, D), DOUBLE), \
11636 X(2, (S, R), SINGLE), \
11637 X(2, (R, S), SINGLE), \
11638 X(2, (F, R), SINGLE), \
11639 X(2, (R, F), SINGLE)
11641 #define S2(A,B) NS_##A##B
11642 #define S3(A,B,C) NS_##A##B##C
11643 #define S4(A,B,C,D) NS_##A##B##C##D
11645 #define X(N, L, C) S##N L
11658 enum neon_shape_class
11666 #define X(N, L, C) SC_##C
11668 static enum neon_shape_class neon_shape_class
[] =
11686 /* Register widths of above. */
11687 static unsigned neon_shape_el_size
[] =
11698 struct neon_shape_info
11701 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11704 #define S2(A,B) { SE_##A, SE_##B }
11705 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11706 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11708 #define X(N, L, C) { N, S##N L }
11710 static struct neon_shape_info neon_shape_tab
[] =
11720 /* Bit masks used in type checking given instructions.
11721 'N_EQK' means the type must be the same as (or based on in some way) the key
11722 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11723 set, various other bits can be set as well in order to modify the meaning of
11724 the type constraint. */
11726 enum neon_type_mask
11749 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11750 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11751 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11752 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11753 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11754 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11755 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11756 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11757 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11758 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11760 N_MAX_NONSPECIAL
= N_F64
11763 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11765 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11766 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11767 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11768 #define N_SUF_32 (N_SU_32 | N_F32)
11769 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11770 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11772 /* Pass this as the first type argument to neon_check_type to ignore types
11774 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11776 /* Select a "shape" for the current instruction (describing register types or
11777 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11778 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11779 function of operand parsing, so this function doesn't need to be called.
11780 Shapes should be listed in order of decreasing length. */
11782 static enum neon_shape
11783 neon_select_shape (enum neon_shape shape
, ...)
11786 enum neon_shape first_shape
= shape
;
11788 /* Fix missing optional operands. FIXME: we don't know at this point how
11789 many arguments we should have, so this makes the assumption that we have
11790 > 1. This is true of all current Neon opcodes, I think, but may not be
11791 true in the future. */
11792 if (!inst
.operands
[1].present
)
11793 inst
.operands
[1] = inst
.operands
[0];
11795 va_start (ap
, shape
);
11797 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11802 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11804 if (!inst
.operands
[j
].present
)
11810 switch (neon_shape_tab
[shape
].el
[j
])
11813 if (!(inst
.operands
[j
].isreg
11814 && inst
.operands
[j
].isvec
11815 && inst
.operands
[j
].issingle
11816 && !inst
.operands
[j
].isquad
))
11821 if (!(inst
.operands
[j
].isreg
11822 && inst
.operands
[j
].isvec
11823 && !inst
.operands
[j
].isquad
11824 && !inst
.operands
[j
].issingle
))
11829 if (!(inst
.operands
[j
].isreg
11830 && !inst
.operands
[j
].isvec
))
11835 if (!(inst
.operands
[j
].isreg
11836 && inst
.operands
[j
].isvec
11837 && inst
.operands
[j
].isquad
11838 && !inst
.operands
[j
].issingle
))
11843 if (!(!inst
.operands
[j
].isreg
11844 && !inst
.operands
[j
].isscalar
))
11849 if (!(!inst
.operands
[j
].isreg
11850 && inst
.operands
[j
].isscalar
))
11866 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11867 first_error (_("invalid instruction shape"));
11872 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11873 means the Q bit should be set). */
11876 neon_quad (enum neon_shape shape
)
11878 return neon_shape_class
[shape
] == SC_QUAD
;
11882 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11885 /* Allow modification to be made to types which are constrained to be
11886 based on the key element, based on bits set alongside N_EQK. */
11887 if ((typebits
& N_EQK
) != 0)
11889 if ((typebits
& N_HLF
) != 0)
11891 else if ((typebits
& N_DBL
) != 0)
11893 if ((typebits
& N_SGN
) != 0)
11894 *g_type
= NT_signed
;
11895 else if ((typebits
& N_UNS
) != 0)
11896 *g_type
= NT_unsigned
;
11897 else if ((typebits
& N_INT
) != 0)
11898 *g_type
= NT_integer
;
11899 else if ((typebits
& N_FLT
) != 0)
11900 *g_type
= NT_float
;
11901 else if ((typebits
& N_SIZ
) != 0)
11902 *g_type
= NT_untyped
;
11906 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11907 operand type, i.e. the single type specified in a Neon instruction when it
11908 is the only one given. */
11910 static struct neon_type_el
11911 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11913 struct neon_type_el dest
= *key
;
11915 gas_assert ((thisarg
& N_EQK
) != 0);
11917 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11922 /* Convert Neon type and size into compact bitmask representation. */
11924 static enum neon_type_mask
11925 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11932 case 8: return N_8
;
11933 case 16: return N_16
;
11934 case 32: return N_32
;
11935 case 64: return N_64
;
11943 case 8: return N_I8
;
11944 case 16: return N_I16
;
11945 case 32: return N_I32
;
11946 case 64: return N_I64
;
11954 case 16: return N_F16
;
11955 case 32: return N_F32
;
11956 case 64: return N_F64
;
11964 case 8: return N_P8
;
11965 case 16: return N_P16
;
11973 case 8: return N_S8
;
11974 case 16: return N_S16
;
11975 case 32: return N_S32
;
11976 case 64: return N_S64
;
11984 case 8: return N_U8
;
11985 case 16: return N_U16
;
11986 case 32: return N_U32
;
11987 case 64: return N_U64
;
11998 /* Convert compact Neon bitmask type representation to a type and size. Only
11999 handles the case where a single bit is set in the mask. */
12002 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12003 enum neon_type_mask mask
)
12005 if ((mask
& N_EQK
) != 0)
12008 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12010 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12012 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12014 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12019 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12021 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12022 *type
= NT_unsigned
;
12023 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12024 *type
= NT_integer
;
12025 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12026 *type
= NT_untyped
;
12027 else if ((mask
& (N_P8
| N_P16
)) != 0)
12029 else if ((mask
& (N_F32
| N_F64
)) != 0)
12037 /* Modify a bitmask of allowed types. This is only needed for type
12041 modify_types_allowed (unsigned allowed
, unsigned mods
)
12044 enum neon_el_type type
;
12050 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12052 if (el_type_of_type_chk (&type
, &size
,
12053 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12055 neon_modify_type_size (mods
, &type
, &size
);
12056 destmask
|= type_chk_of_el_type (type
, size
);
12063 /* Check type and return type classification.
12064 The manual states (paraphrase): If one datatype is given, it indicates the
12066 - the second operand, if there is one
12067 - the operand, if there is no second operand
12068 - the result, if there are no operands.
12069 This isn't quite good enough though, so we use a concept of a "key" datatype
12070 which is set on a per-instruction basis, which is the one which matters when
12071 only one data type is written.
12072 Note: this function has side-effects (e.g. filling in missing operands). All
12073 Neon instructions should call it before performing bit encoding. */
12075 static struct neon_type_el
12076 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12079 unsigned i
, pass
, key_el
= 0;
12080 unsigned types
[NEON_MAX_TYPE_ELS
];
12081 enum neon_el_type k_type
= NT_invtype
;
12082 unsigned k_size
= -1u;
12083 struct neon_type_el badtype
= {NT_invtype
, -1};
12084 unsigned key_allowed
= 0;
12086 /* Optional registers in Neon instructions are always (not) in operand 1.
12087 Fill in the missing operand here, if it was omitted. */
12088 if (els
> 1 && !inst
.operands
[1].present
)
12089 inst
.operands
[1] = inst
.operands
[0];
12091 /* Suck up all the varargs. */
12093 for (i
= 0; i
< els
; i
++)
12095 unsigned thisarg
= va_arg (ap
, unsigned);
12096 if (thisarg
== N_IGNORE_TYPE
)
12101 types
[i
] = thisarg
;
12102 if ((thisarg
& N_KEY
) != 0)
12107 if (inst
.vectype
.elems
> 0)
12108 for (i
= 0; i
< els
; i
++)
12109 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12111 first_error (_("types specified in both the mnemonic and operands"));
12115 /* Duplicate inst.vectype elements here as necessary.
12116 FIXME: No idea if this is exactly the same as the ARM assembler,
12117 particularly when an insn takes one register and one non-register
12119 if (inst
.vectype
.elems
== 1 && els
> 1)
12122 inst
.vectype
.elems
= els
;
12123 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12124 for (j
= 0; j
< els
; j
++)
12126 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12129 else if (inst
.vectype
.elems
== 0 && els
> 0)
12132 /* No types were given after the mnemonic, so look for types specified
12133 after each operand. We allow some flexibility here; as long as the
12134 "key" operand has a type, we can infer the others. */
12135 for (j
= 0; j
< els
; j
++)
12136 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12137 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12139 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12141 for (j
= 0; j
< els
; j
++)
12142 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12143 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12148 first_error (_("operand types can't be inferred"));
12152 else if (inst
.vectype
.elems
!= els
)
12154 first_error (_("type specifier has the wrong number of parts"));
12158 for (pass
= 0; pass
< 2; pass
++)
12160 for (i
= 0; i
< els
; i
++)
12162 unsigned thisarg
= types
[i
];
12163 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12164 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12165 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12166 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12168 /* Decay more-specific signed & unsigned types to sign-insensitive
12169 integer types if sign-specific variants are unavailable. */
12170 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12171 && (types_allowed
& N_SU_ALL
) == 0)
12172 g_type
= NT_integer
;
12174 /* If only untyped args are allowed, decay any more specific types to
12175 them. Some instructions only care about signs for some element
12176 sizes, so handle that properly. */
12177 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12178 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12179 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12180 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12181 g_type
= NT_untyped
;
12185 if ((thisarg
& N_KEY
) != 0)
12189 key_allowed
= thisarg
& ~N_KEY
;
12194 if ((thisarg
& N_VFP
) != 0)
12196 enum neon_shape_el regshape
;
12197 unsigned regwidth
, match
;
12199 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12202 first_error (_("invalid instruction shape"));
12205 regshape
= neon_shape_tab
[ns
].el
[i
];
12206 regwidth
= neon_shape_el_size
[regshape
];
12208 /* In VFP mode, operands must match register widths. If we
12209 have a key operand, use its width, else use the width of
12210 the current operand. */
12216 if (regwidth
!= match
)
12218 first_error (_("operand size must match register width"));
12223 if ((thisarg
& N_EQK
) == 0)
12225 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12227 if ((given_type
& types_allowed
) == 0)
12229 first_error (_("bad type in Neon instruction"));
12235 enum neon_el_type mod_k_type
= k_type
;
12236 unsigned mod_k_size
= k_size
;
12237 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12238 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12240 first_error (_("inconsistent types in Neon instruction"));
12248 return inst
.vectype
.el
[key_el
];
12251 /* Neon-style VFP instruction forwarding. */
12253 /* Thumb VFP instructions have 0xE in the condition field. */
12256 do_vfp_cond_or_thumb (void)
12261 inst
.instruction
|= 0xe0000000;
12263 inst
.instruction
|= inst
.cond
<< 28;
12266 /* Look up and encode a simple mnemonic, for use as a helper function for the
12267 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12268 etc. It is assumed that operand parsing has already been done, and that the
12269 operands are in the form expected by the given opcode (this isn't necessarily
12270 the same as the form in which they were parsed, hence some massaging must
12271 take place before this function is called).
12272 Checks current arch version against that in the looked-up opcode. */
12275 do_vfp_nsyn_opcode (const char *opname
)
12277 const struct asm_opcode
*opcode
;
12279 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12284 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12285 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12292 inst
.instruction
= opcode
->tvalue
;
12293 opcode
->tencode ();
12297 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12298 opcode
->aencode ();
12303 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12305 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12310 do_vfp_nsyn_opcode ("fadds");
12312 do_vfp_nsyn_opcode ("fsubs");
12317 do_vfp_nsyn_opcode ("faddd");
12319 do_vfp_nsyn_opcode ("fsubd");
12323 /* Check operand types to see if this is a VFP instruction, and if so call
12327 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12329 enum neon_shape rs
;
12330 struct neon_type_el et
;
12335 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12336 et
= neon_check_type (2, rs
,
12337 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12341 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12342 et
= neon_check_type (3, rs
,
12343 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12350 if (et
.type
!= NT_invtype
)
12361 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12363 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12368 do_vfp_nsyn_opcode ("fmacs");
12370 do_vfp_nsyn_opcode ("fnmacs");
12375 do_vfp_nsyn_opcode ("fmacd");
12377 do_vfp_nsyn_opcode ("fnmacd");
12382 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12384 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12389 do_vfp_nsyn_opcode ("ffmas");
12391 do_vfp_nsyn_opcode ("ffnmas");
12396 do_vfp_nsyn_opcode ("ffmad");
12398 do_vfp_nsyn_opcode ("ffnmad");
12403 do_vfp_nsyn_mul (enum neon_shape rs
)
12406 do_vfp_nsyn_opcode ("fmuls");
12408 do_vfp_nsyn_opcode ("fmuld");
12412 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12414 int is_neg
= (inst
.instruction
& 0x80) != 0;
12415 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12420 do_vfp_nsyn_opcode ("fnegs");
12422 do_vfp_nsyn_opcode ("fabss");
12427 do_vfp_nsyn_opcode ("fnegd");
12429 do_vfp_nsyn_opcode ("fabsd");
12433 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12434 insns belong to Neon, and are handled elsewhere. */
12437 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12439 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12443 do_vfp_nsyn_opcode ("fldmdbs");
12445 do_vfp_nsyn_opcode ("fldmias");
12450 do_vfp_nsyn_opcode ("fstmdbs");
12452 do_vfp_nsyn_opcode ("fstmias");
12457 do_vfp_nsyn_sqrt (void)
12459 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12460 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12463 do_vfp_nsyn_opcode ("fsqrts");
12465 do_vfp_nsyn_opcode ("fsqrtd");
12469 do_vfp_nsyn_div (void)
12471 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12472 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12473 N_F32
| N_F64
| N_KEY
| N_VFP
);
12476 do_vfp_nsyn_opcode ("fdivs");
12478 do_vfp_nsyn_opcode ("fdivd");
12482 do_vfp_nsyn_nmul (void)
12484 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12485 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12486 N_F32
| N_F64
| N_KEY
| N_VFP
);
12490 NEON_ENCODE (SINGLE
, inst
);
12491 do_vfp_sp_dyadic ();
12495 NEON_ENCODE (DOUBLE
, inst
);
12496 do_vfp_dp_rd_rn_rm ();
12498 do_vfp_cond_or_thumb ();
12502 do_vfp_nsyn_cmp (void)
12504 if (inst
.operands
[1].isreg
)
12506 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12507 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12511 NEON_ENCODE (SINGLE
, inst
);
12512 do_vfp_sp_monadic ();
12516 NEON_ENCODE (DOUBLE
, inst
);
12517 do_vfp_dp_rd_rm ();
12522 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12523 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12525 switch (inst
.instruction
& 0x0fffffff)
12528 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12531 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12539 NEON_ENCODE (SINGLE
, inst
);
12540 do_vfp_sp_compare_z ();
12544 NEON_ENCODE (DOUBLE
, inst
);
12548 do_vfp_cond_or_thumb ();
12552 nsyn_insert_sp (void)
12554 inst
.operands
[1] = inst
.operands
[0];
12555 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12556 inst
.operands
[0].reg
= REG_SP
;
12557 inst
.operands
[0].isreg
= 1;
12558 inst
.operands
[0].writeback
= 1;
12559 inst
.operands
[0].present
= 1;
12563 do_vfp_nsyn_push (void)
12566 if (inst
.operands
[1].issingle
)
12567 do_vfp_nsyn_opcode ("fstmdbs");
12569 do_vfp_nsyn_opcode ("fstmdbd");
12573 do_vfp_nsyn_pop (void)
12576 if (inst
.operands
[1].issingle
)
12577 do_vfp_nsyn_opcode ("fldmias");
12579 do_vfp_nsyn_opcode ("fldmiad");
12582 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12583 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12586 neon_dp_fixup (struct arm_it
* insn
)
12588 unsigned int i
= insn
->instruction
;
12593 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12604 insn
->instruction
= i
;
12607 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12611 neon_logbits (unsigned x
)
12613 return ffs (x
) - 4;
12616 #define LOW4(R) ((R) & 0xf)
12617 #define HI1(R) (((R) >> 4) & 1)
12619 /* Encode insns with bit pattern:
12621 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12622 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12624 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12625 different meaning for some instruction. */
12628 neon_three_same (int isquad
, int ubit
, int size
)
12630 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12631 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12632 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12633 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12634 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12635 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12636 inst
.instruction
|= (isquad
!= 0) << 6;
12637 inst
.instruction
|= (ubit
!= 0) << 24;
12639 inst
.instruction
|= neon_logbits (size
) << 20;
12641 neon_dp_fixup (&inst
);
12644 /* Encode instructions of the form:
12646 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12647 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12649 Don't write size if SIZE == -1. */
12652 neon_two_same (int qbit
, int ubit
, int size
)
12654 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12655 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12656 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12657 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12658 inst
.instruction
|= (qbit
!= 0) << 6;
12659 inst
.instruction
|= (ubit
!= 0) << 24;
12662 inst
.instruction
|= neon_logbits (size
) << 18;
12664 neon_dp_fixup (&inst
);
12667 /* Neon instruction encoders, in approximate order of appearance. */
12670 do_neon_dyadic_i_su (void)
12672 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12673 struct neon_type_el et
= neon_check_type (3, rs
,
12674 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12675 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12679 do_neon_dyadic_i64_su (void)
12681 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12682 struct neon_type_el et
= neon_check_type (3, rs
,
12683 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12684 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12688 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12691 unsigned size
= et
.size
>> 3;
12692 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12693 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12695 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12696 inst
.instruction
|= (isquad
!= 0) << 6;
12697 inst
.instruction
|= immbits
<< 16;
12698 inst
.instruction
|= (size
>> 3) << 7;
12699 inst
.instruction
|= (size
& 0x7) << 19;
12701 inst
.instruction
|= (uval
!= 0) << 24;
12703 neon_dp_fixup (&inst
);
12707 do_neon_shl_imm (void)
12709 if (!inst
.operands
[2].isreg
)
12711 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12712 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12713 NEON_ENCODE (IMMED
, inst
);
12714 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12718 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12719 struct neon_type_el et
= neon_check_type (3, rs
,
12720 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12723 /* VSHL/VQSHL 3-register variants have syntax such as:
12725 whereas other 3-register operations encoded by neon_three_same have
12728 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12730 tmp
= inst
.operands
[2].reg
;
12731 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12732 inst
.operands
[1].reg
= tmp
;
12733 NEON_ENCODE (INTEGER
, inst
);
12734 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12739 do_neon_qshl_imm (void)
12741 if (!inst
.operands
[2].isreg
)
12743 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12744 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12746 NEON_ENCODE (IMMED
, inst
);
12747 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12748 inst
.operands
[2].imm
);
12752 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12753 struct neon_type_el et
= neon_check_type (3, rs
,
12754 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12757 /* See note in do_neon_shl_imm. */
12758 tmp
= inst
.operands
[2].reg
;
12759 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12760 inst
.operands
[1].reg
= tmp
;
12761 NEON_ENCODE (INTEGER
, inst
);
12762 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12767 do_neon_rshl (void)
12769 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12770 struct neon_type_el et
= neon_check_type (3, rs
,
12771 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12774 tmp
= inst
.operands
[2].reg
;
12775 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12776 inst
.operands
[1].reg
= tmp
;
12777 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12781 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12783 /* Handle .I8 pseudo-instructions. */
12786 /* Unfortunately, this will make everything apart from zero out-of-range.
12787 FIXME is this the intended semantics? There doesn't seem much point in
12788 accepting .I8 if so. */
12789 immediate
|= immediate
<< 8;
12795 if (immediate
== (immediate
& 0x000000ff))
12797 *immbits
= immediate
;
12800 else if (immediate
== (immediate
& 0x0000ff00))
12802 *immbits
= immediate
>> 8;
12805 else if (immediate
== (immediate
& 0x00ff0000))
12807 *immbits
= immediate
>> 16;
12810 else if (immediate
== (immediate
& 0xff000000))
12812 *immbits
= immediate
>> 24;
12815 if ((immediate
& 0xffff) != (immediate
>> 16))
12816 goto bad_immediate
;
12817 immediate
&= 0xffff;
12820 if (immediate
== (immediate
& 0x000000ff))
12822 *immbits
= immediate
;
12825 else if (immediate
== (immediate
& 0x0000ff00))
12827 *immbits
= immediate
>> 8;
12832 first_error (_("immediate value out of range"));
12836 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12840 neon_bits_same_in_bytes (unsigned imm
)
12842 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12843 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12844 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12845 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12848 /* For immediate of above form, return 0bABCD. */
12851 neon_squash_bits (unsigned imm
)
12853 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12854 | ((imm
& 0x01000000) >> 21);
12857 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12860 neon_qfloat_bits (unsigned imm
)
12862 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12865 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12866 the instruction. *OP is passed as the initial value of the op field, and
12867 may be set to a different value depending on the constant (i.e.
12868 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12869 MVN). If the immediate looks like a repeated pattern then also
12870 try smaller element sizes. */
12873 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12874 unsigned *immbits
, int *op
, int size
,
12875 enum neon_el_type type
)
12877 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12879 if (type
== NT_float
&& !float_p
)
12882 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12884 if (size
!= 32 || *op
== 1)
12886 *immbits
= neon_qfloat_bits (immlo
);
12892 if (neon_bits_same_in_bytes (immhi
)
12893 && neon_bits_same_in_bytes (immlo
))
12897 *immbits
= (neon_squash_bits (immhi
) << 4)
12898 | neon_squash_bits (immlo
);
12903 if (immhi
!= immlo
)
12909 if (immlo
== (immlo
& 0x000000ff))
12914 else if (immlo
== (immlo
& 0x0000ff00))
12916 *immbits
= immlo
>> 8;
12919 else if (immlo
== (immlo
& 0x00ff0000))
12921 *immbits
= immlo
>> 16;
12924 else if (immlo
== (immlo
& 0xff000000))
12926 *immbits
= immlo
>> 24;
12929 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12931 *immbits
= (immlo
>> 8) & 0xff;
12934 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12936 *immbits
= (immlo
>> 16) & 0xff;
12940 if ((immlo
& 0xffff) != (immlo
>> 16))
12947 if (immlo
== (immlo
& 0x000000ff))
12952 else if (immlo
== (immlo
& 0x0000ff00))
12954 *immbits
= immlo
>> 8;
12958 if ((immlo
& 0xff) != (immlo
>> 8))
12963 if (immlo
== (immlo
& 0x000000ff))
12965 /* Don't allow MVN with 8-bit immediate. */
12975 /* Write immediate bits [7:0] to the following locations:
12977 |28/24|23 19|18 16|15 4|3 0|
12978 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12980 This function is used by VMOV/VMVN/VORR/VBIC. */
12983 neon_write_immbits (unsigned immbits
)
12985 inst
.instruction
|= immbits
& 0xf;
12986 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12987 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12990 /* Invert low-order SIZE bits of XHI:XLO. */
12993 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12995 unsigned immlo
= xlo
? *xlo
: 0;
12996 unsigned immhi
= xhi
? *xhi
: 0;
13001 immlo
= (~immlo
) & 0xff;
13005 immlo
= (~immlo
) & 0xffff;
13009 immhi
= (~immhi
) & 0xffffffff;
13010 /* fall through. */
13013 immlo
= (~immlo
) & 0xffffffff;
13028 do_neon_logic (void)
13030 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13032 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13033 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13034 /* U bit and size field were set as part of the bitmask. */
13035 NEON_ENCODE (INTEGER
, inst
);
13036 neon_three_same (neon_quad (rs
), 0, -1);
13040 const int three_ops_form
= (inst
.operands
[2].present
13041 && !inst
.operands
[2].isreg
);
13042 const int immoperand
= (three_ops_form
? 2 : 1);
13043 enum neon_shape rs
= (three_ops_form
13044 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13045 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13046 struct neon_type_el et
= neon_check_type (2, rs
,
13047 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13048 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13052 if (et
.type
== NT_invtype
)
13055 if (three_ops_form
)
13056 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13057 _("first and second operands shall be the same register"));
13059 NEON_ENCODE (IMMED
, inst
);
13061 immbits
= inst
.operands
[immoperand
].imm
;
13064 /* .i64 is a pseudo-op, so the immediate must be a repeating
13066 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13067 inst
.operands
[immoperand
].reg
: 0))
13069 /* Set immbits to an invalid constant. */
13070 immbits
= 0xdeadbeef;
13077 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13081 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13085 /* Pseudo-instruction for VBIC. */
13086 neon_invert_size (&immbits
, 0, et
.size
);
13087 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13091 /* Pseudo-instruction for VORR. */
13092 neon_invert_size (&immbits
, 0, et
.size
);
13093 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13103 inst
.instruction
|= neon_quad (rs
) << 6;
13104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13105 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13106 inst
.instruction
|= cmode
<< 8;
13107 neon_write_immbits (immbits
);
13109 neon_dp_fixup (&inst
);
13114 do_neon_bitfield (void)
13116 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13117 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13118 neon_three_same (neon_quad (rs
), 0, -1);
13122 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13125 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13126 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13128 if (et
.type
== NT_float
)
13130 NEON_ENCODE (FLOAT
, inst
);
13131 neon_three_same (neon_quad (rs
), 0, -1);
13135 NEON_ENCODE (INTEGER
, inst
);
13136 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13141 do_neon_dyadic_if_su (void)
13143 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13147 do_neon_dyadic_if_su_d (void)
13149 /* This version only allow D registers, but that constraint is enforced during
13150 operand parsing so we don't need to do anything extra here. */
13151 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13155 do_neon_dyadic_if_i_d (void)
13157 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13158 affected if we specify unsigned args. */
13159 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13162 enum vfp_or_neon_is_neon_bits
13165 NEON_CHECK_ARCH
= 2
13168 /* Call this function if an instruction which may have belonged to the VFP or
13169 Neon instruction sets, but turned out to be a Neon instruction (due to the
13170 operand types involved, etc.). We have to check and/or fix-up a couple of
13173 - Make sure the user hasn't attempted to make a Neon instruction
13175 - Alter the value in the condition code field if necessary.
13176 - Make sure that the arch supports Neon instructions.
13178 Which of these operations take place depends on bits from enum
13179 vfp_or_neon_is_neon_bits.
13181 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13182 current instruction's condition is COND_ALWAYS, the condition field is
13183 changed to inst.uncond_value. This is necessary because instructions shared
13184 between VFP and Neon may be conditional for the VFP variants only, and the
13185 unconditional Neon version must have, e.g., 0xF in the condition field. */
13188 vfp_or_neon_is_neon (unsigned check
)
13190 /* Conditions are always legal in Thumb mode (IT blocks). */
13191 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13193 if (inst
.cond
!= COND_ALWAYS
)
13195 first_error (_(BAD_COND
));
13198 if (inst
.uncond_value
!= -1)
13199 inst
.instruction
|= inst
.uncond_value
<< 28;
13202 if ((check
& NEON_CHECK_ARCH
)
13203 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13205 first_error (_(BAD_FPU
));
13213 do_neon_addsub_if_i (void)
13215 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13218 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13221 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13222 affected if we specify unsigned args. */
13223 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13226 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13228 V<op> A,B (A is operand 0, B is operand 2)
13233 so handle that case specially. */
13236 neon_exchange_operands (void)
13238 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13239 if (inst
.operands
[1].present
)
13241 /* Swap operands[1] and operands[2]. */
13242 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13243 inst
.operands
[1] = inst
.operands
[2];
13244 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13248 inst
.operands
[1] = inst
.operands
[2];
13249 inst
.operands
[2] = inst
.operands
[0];
13254 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13256 if (inst
.operands
[2].isreg
)
13259 neon_exchange_operands ();
13260 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13264 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13265 struct neon_type_el et
= neon_check_type (2, rs
,
13266 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13268 NEON_ENCODE (IMMED
, inst
);
13269 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13270 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13271 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13272 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13273 inst
.instruction
|= neon_quad (rs
) << 6;
13274 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13275 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13277 neon_dp_fixup (&inst
);
13284 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13288 do_neon_cmp_inv (void)
13290 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13296 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13299 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13300 scalars, which are encoded in 5 bits, M : Rm.
13301 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13302 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13306 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13308 unsigned regno
= NEON_SCALAR_REG (scalar
);
13309 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13314 if (regno
> 7 || elno
> 3)
13316 return regno
| (elno
<< 3);
13319 if (regno
> 15 || elno
> 1)
13321 return regno
| (elno
<< 4);
13325 first_error (_("scalar out of range for multiply instruction"));
13331 /* Encode multiply / multiply-accumulate scalar instructions. */
13334 neon_mul_mac (struct neon_type_el et
, int ubit
)
13338 /* Give a more helpful error message if we have an invalid type. */
13339 if (et
.type
== NT_invtype
)
13342 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13343 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13344 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13345 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13346 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13347 inst
.instruction
|= LOW4 (scalar
);
13348 inst
.instruction
|= HI1 (scalar
) << 5;
13349 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13350 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13351 inst
.instruction
|= (ubit
!= 0) << 24;
13353 neon_dp_fixup (&inst
);
13357 do_neon_mac_maybe_scalar (void)
13359 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13362 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13365 if (inst
.operands
[2].isscalar
)
13367 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13368 struct neon_type_el et
= neon_check_type (3, rs
,
13369 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13370 NEON_ENCODE (SCALAR
, inst
);
13371 neon_mul_mac (et
, neon_quad (rs
));
13375 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13376 affected if we specify unsigned args. */
13377 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13382 do_neon_fmac (void)
13384 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13387 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13390 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13396 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13397 struct neon_type_el et
= neon_check_type (3, rs
,
13398 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13399 neon_three_same (neon_quad (rs
), 0, et
.size
);
13402 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13403 same types as the MAC equivalents. The polynomial type for this instruction
13404 is encoded the same as the integer type. */
13409 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13412 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13415 if (inst
.operands
[2].isscalar
)
13416 do_neon_mac_maybe_scalar ();
13418 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13422 do_neon_qdmulh (void)
13424 if (inst
.operands
[2].isscalar
)
13426 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13427 struct neon_type_el et
= neon_check_type (3, rs
,
13428 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13429 NEON_ENCODE (SCALAR
, inst
);
13430 neon_mul_mac (et
, neon_quad (rs
));
13434 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13435 struct neon_type_el et
= neon_check_type (3, rs
,
13436 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13437 NEON_ENCODE (INTEGER
, inst
);
13438 /* The U bit (rounding) comes from bit mask. */
13439 neon_three_same (neon_quad (rs
), 0, et
.size
);
13444 do_neon_fcmp_absolute (void)
13446 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13447 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13448 /* Size field comes from bit mask. */
13449 neon_three_same (neon_quad (rs
), 1, -1);
13453 do_neon_fcmp_absolute_inv (void)
13455 neon_exchange_operands ();
13456 do_neon_fcmp_absolute ();
13460 do_neon_step (void)
13462 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13463 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13464 neon_three_same (neon_quad (rs
), 0, -1);
13468 do_neon_abs_neg (void)
13470 enum neon_shape rs
;
13471 struct neon_type_el et
;
13473 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13476 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13479 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13480 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13482 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13483 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13484 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13485 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13486 inst
.instruction
|= neon_quad (rs
) << 6;
13487 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13488 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13490 neon_dp_fixup (&inst
);
13496 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13497 struct neon_type_el et
= neon_check_type (2, rs
,
13498 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13499 int imm
= inst
.operands
[2].imm
;
13500 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13501 _("immediate out of range for insert"));
13502 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13508 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13509 struct neon_type_el et
= neon_check_type (2, rs
,
13510 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13511 int imm
= inst
.operands
[2].imm
;
13512 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13513 _("immediate out of range for insert"));
13514 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13518 do_neon_qshlu_imm (void)
13520 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13521 struct neon_type_el et
= neon_check_type (2, rs
,
13522 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13523 int imm
= inst
.operands
[2].imm
;
13524 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13525 _("immediate out of range for shift"));
13526 /* Only encodes the 'U present' variant of the instruction.
13527 In this case, signed types have OP (bit 8) set to 0.
13528 Unsigned types have OP set to 1. */
13529 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13530 /* The rest of the bits are the same as other immediate shifts. */
13531 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13535 do_neon_qmovn (void)
13537 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13538 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13539 /* Saturating move where operands can be signed or unsigned, and the
13540 destination has the same signedness. */
13541 NEON_ENCODE (INTEGER
, inst
);
13542 if (et
.type
== NT_unsigned
)
13543 inst
.instruction
|= 0xc0;
13545 inst
.instruction
|= 0x80;
13546 neon_two_same (0, 1, et
.size
/ 2);
13550 do_neon_qmovun (void)
13552 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13553 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13554 /* Saturating move with unsigned results. Operands must be signed. */
13555 NEON_ENCODE (INTEGER
, inst
);
13556 neon_two_same (0, 1, et
.size
/ 2);
13560 do_neon_rshift_sat_narrow (void)
13562 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13563 or unsigned. If operands are unsigned, results must also be unsigned. */
13564 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13565 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13566 int imm
= inst
.operands
[2].imm
;
13567 /* This gets the bounds check, size encoding and immediate bits calculation
13571 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13572 VQMOVN.I<size> <Dd>, <Qm>. */
13575 inst
.operands
[2].present
= 0;
13576 inst
.instruction
= N_MNEM_vqmovn
;
13581 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13582 _("immediate out of range"));
13583 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13587 do_neon_rshift_sat_narrow_u (void)
13589 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13590 or unsigned. If operands are unsigned, results must also be unsigned. */
13591 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13592 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13593 int imm
= inst
.operands
[2].imm
;
13594 /* This gets the bounds check, size encoding and immediate bits calculation
13598 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13599 VQMOVUN.I<size> <Dd>, <Qm>. */
13602 inst
.operands
[2].present
= 0;
13603 inst
.instruction
= N_MNEM_vqmovun
;
13608 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13609 _("immediate out of range"));
13610 /* FIXME: The manual is kind of unclear about what value U should have in
13611 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13613 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13617 do_neon_movn (void)
13619 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13620 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13621 NEON_ENCODE (INTEGER
, inst
);
13622 neon_two_same (0, 1, et
.size
/ 2);
13626 do_neon_rshift_narrow (void)
13628 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13629 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13630 int imm
= inst
.operands
[2].imm
;
13631 /* This gets the bounds check, size encoding and immediate bits calculation
13635 /* If immediate is zero then we are a pseudo-instruction for
13636 VMOVN.I<size> <Dd>, <Qm> */
13639 inst
.operands
[2].present
= 0;
13640 inst
.instruction
= N_MNEM_vmovn
;
13645 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13646 _("immediate out of range for narrowing operation"));
13647 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13651 do_neon_shll (void)
13653 /* FIXME: Type checking when lengthening. */
13654 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13655 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13656 unsigned imm
= inst
.operands
[2].imm
;
13658 if (imm
== et
.size
)
13660 /* Maximum shift variant. */
13661 NEON_ENCODE (INTEGER
, inst
);
13662 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13663 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13664 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13665 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13666 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13668 neon_dp_fixup (&inst
);
13672 /* A more-specific type check for non-max versions. */
13673 et
= neon_check_type (2, NS_QDI
,
13674 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13675 NEON_ENCODE (IMMED
, inst
);
13676 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13680 /* Check the various types for the VCVT instruction, and return which version
13681 the current instruction is. */
13684 neon_cvt_flavour (enum neon_shape rs
)
13686 #define CVT_VAR(C,X,Y) \
13687 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13688 if (et.type != NT_invtype) \
13690 inst.error = NULL; \
13693 struct neon_type_el et
;
13694 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13695 || rs
== NS_FF
) ? N_VFP
: 0;
13696 /* The instruction versions which take an immediate take one register
13697 argument, which is extended to the width of the full register. Thus the
13698 "source" and "destination" registers must have the same width. Hack that
13699 here by making the size equal to the key (wider, in this case) operand. */
13700 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13702 CVT_VAR (0, N_S32
, N_F32
);
13703 CVT_VAR (1, N_U32
, N_F32
);
13704 CVT_VAR (2, N_F32
, N_S32
);
13705 CVT_VAR (3, N_F32
, N_U32
);
13706 /* Half-precision conversions. */
13707 CVT_VAR (4, N_F32
, N_F16
);
13708 CVT_VAR (5, N_F16
, N_F32
);
13712 /* VFP instructions. */
13713 CVT_VAR (6, N_F32
, N_F64
);
13714 CVT_VAR (7, N_F64
, N_F32
);
13715 CVT_VAR (8, N_S32
, N_F64
| key
);
13716 CVT_VAR (9, N_U32
, N_F64
| key
);
13717 CVT_VAR (10, N_F64
| key
, N_S32
);
13718 CVT_VAR (11, N_F64
| key
, N_U32
);
13719 /* VFP instructions with bitshift. */
13720 CVT_VAR (12, N_F32
| key
, N_S16
);
13721 CVT_VAR (13, N_F32
| key
, N_U16
);
13722 CVT_VAR (14, N_F64
| key
, N_S16
);
13723 CVT_VAR (15, N_F64
| key
, N_U16
);
13724 CVT_VAR (16, N_S16
, N_F32
| key
);
13725 CVT_VAR (17, N_U16
, N_F32
| key
);
13726 CVT_VAR (18, N_S16
, N_F64
| key
);
13727 CVT_VAR (19, N_U16
, N_F64
| key
);
13733 /* Neon-syntax VFP conversions. */
13736 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13738 const char *opname
= 0;
13740 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13742 /* Conversions with immediate bitshift. */
13743 const char *enc
[] =
13767 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13769 opname
= enc
[flavour
];
13770 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13771 _("operands 0 and 1 must be the same register"));
13772 inst
.operands
[1] = inst
.operands
[2];
13773 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13778 /* Conversions without bitshift. */
13779 const char *enc
[] =
13795 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13796 opname
= enc
[flavour
];
13800 do_vfp_nsyn_opcode (opname
);
13804 do_vfp_nsyn_cvtz (void)
13806 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13807 int flavour
= neon_cvt_flavour (rs
);
13808 const char *enc
[] =
13822 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13823 do_vfp_nsyn_opcode (enc
[flavour
]);
13827 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13829 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13830 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13831 int flavour
= neon_cvt_flavour (rs
);
13833 /* PR11109: Handle round-to-zero for VCVT conversions. */
13835 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13836 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13837 && (rs
== NS_FD
|| rs
== NS_FF
))
13839 do_vfp_nsyn_cvtz ();
13843 /* VFP rather than Neon conversions. */
13846 do_vfp_nsyn_cvt (rs
, flavour
);
13856 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13858 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13861 /* Fixed-point conversion with #0 immediate is encoded as an
13862 integer conversion. */
13863 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13865 immbits
= 32 - inst
.operands
[2].imm
;
13866 NEON_ENCODE (IMMED
, inst
);
13868 inst
.instruction
|= enctab
[flavour
];
13869 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13870 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13871 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13872 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13873 inst
.instruction
|= neon_quad (rs
) << 6;
13874 inst
.instruction
|= 1 << 21;
13875 inst
.instruction
|= immbits
<< 16;
13877 neon_dp_fixup (&inst
);
13885 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13887 NEON_ENCODE (INTEGER
, inst
);
13889 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13893 inst
.instruction
|= enctab
[flavour
];
13895 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13896 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13897 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13898 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13899 inst
.instruction
|= neon_quad (rs
) << 6;
13900 inst
.instruction
|= 2 << 18;
13902 neon_dp_fixup (&inst
);
13906 /* Half-precision conversions for Advanced SIMD -- neon. */
13911 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13913 as_bad (_("operand size must match register width"));
13918 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13920 as_bad (_("operand size must match register width"));
13925 inst
.instruction
= 0x3b60600;
13927 inst
.instruction
= 0x3b60700;
13929 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13930 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13931 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13932 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13933 neon_dp_fixup (&inst
);
13937 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13938 do_vfp_nsyn_cvt (rs
, flavour
);
13943 do_neon_cvtr (void)
13945 do_neon_cvt_1 (FALSE
);
13951 do_neon_cvt_1 (TRUE
);
13955 do_neon_cvtb (void)
13957 inst
.instruction
= 0xeb20a40;
13959 /* The sizes are attached to the mnemonic. */
13960 if (inst
.vectype
.el
[0].type
!= NT_invtype
13961 && inst
.vectype
.el
[0].size
== 16)
13962 inst
.instruction
|= 0x00010000;
13964 /* Programmer's syntax: the sizes are attached to the operands. */
13965 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13966 && inst
.operands
[0].vectype
.size
== 16)
13967 inst
.instruction
|= 0x00010000;
13969 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13970 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13971 do_vfp_cond_or_thumb ();
13976 do_neon_cvtt (void)
13979 inst
.instruction
|= 0x80;
13983 neon_move_immediate (void)
13985 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13986 struct neon_type_el et
= neon_check_type (2, rs
,
13987 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13988 unsigned immlo
, immhi
= 0, immbits
;
13989 int op
, cmode
, float_p
;
13991 constraint (et
.type
== NT_invtype
,
13992 _("operand size must be specified for immediate VMOV"));
13994 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13995 op
= (inst
.instruction
& (1 << 5)) != 0;
13997 immlo
= inst
.operands
[1].imm
;
13998 if (inst
.operands
[1].regisimm
)
13999 immhi
= inst
.operands
[1].reg
;
14001 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14002 _("immediate has bits set outside the operand size"));
14004 float_p
= inst
.operands
[1].immisfloat
;
14006 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14007 et
.size
, et
.type
)) == FAIL
)
14009 /* Invert relevant bits only. */
14010 neon_invert_size (&immlo
, &immhi
, et
.size
);
14011 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14012 with one or the other; those cases are caught by
14013 neon_cmode_for_move_imm. */
14015 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14016 &op
, et
.size
, et
.type
)) == FAIL
)
14018 first_error (_("immediate out of range"));
14023 inst
.instruction
&= ~(1 << 5);
14024 inst
.instruction
|= op
<< 5;
14026 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14027 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14028 inst
.instruction
|= neon_quad (rs
) << 6;
14029 inst
.instruction
|= cmode
<< 8;
14031 neon_write_immbits (immbits
);
14037 if (inst
.operands
[1].isreg
)
14039 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14041 NEON_ENCODE (INTEGER
, inst
);
14042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14043 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14045 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14046 inst
.instruction
|= neon_quad (rs
) << 6;
14050 NEON_ENCODE (IMMED
, inst
);
14051 neon_move_immediate ();
14054 neon_dp_fixup (&inst
);
14057 /* Encode instructions of form:
14059 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14060 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14063 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14067 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14069 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14070 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14071 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14072 inst
.instruction
|= neon_logbits (size
) << 20;
14074 neon_dp_fixup (&inst
);
14078 do_neon_dyadic_long (void)
14080 /* FIXME: Type checking for lengthening op. */
14081 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14082 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14083 neon_mixed_length (et
, et
.size
);
14087 do_neon_abal (void)
14089 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14090 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14091 neon_mixed_length (et
, et
.size
);
14095 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14097 if (inst
.operands
[2].isscalar
)
14099 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14100 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14101 NEON_ENCODE (SCALAR
, inst
);
14102 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14106 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14107 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14108 NEON_ENCODE (INTEGER
, inst
);
14109 neon_mixed_length (et
, et
.size
);
14114 do_neon_mac_maybe_scalar_long (void)
14116 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14120 do_neon_dyadic_wide (void)
14122 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14123 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14124 neon_mixed_length (et
, et
.size
);
14128 do_neon_dyadic_narrow (void)
14130 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14131 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14132 /* Operand sign is unimportant, and the U bit is part of the opcode,
14133 so force the operand type to integer. */
14134 et
.type
= NT_integer
;
14135 neon_mixed_length (et
, et
.size
/ 2);
14139 do_neon_mul_sat_scalar_long (void)
14141 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14145 do_neon_vmull (void)
14147 if (inst
.operands
[2].isscalar
)
14148 do_neon_mac_maybe_scalar_long ();
14151 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14152 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14153 if (et
.type
== NT_poly
)
14154 NEON_ENCODE (POLY
, inst
);
14156 NEON_ENCODE (INTEGER
, inst
);
14157 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14158 zero. Should be OK as-is. */
14159 neon_mixed_length (et
, et
.size
);
14166 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14167 struct neon_type_el et
= neon_check_type (3, rs
,
14168 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14169 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14171 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14172 _("shift out of range"));
14173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14177 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14178 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14179 inst
.instruction
|= neon_quad (rs
) << 6;
14180 inst
.instruction
|= imm
<< 8;
14182 neon_dp_fixup (&inst
);
14188 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14189 struct neon_type_el et
= neon_check_type (2, rs
,
14190 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14191 unsigned op
= (inst
.instruction
>> 7) & 3;
14192 /* N (width of reversed regions) is encoded as part of the bitmask. We
14193 extract it here to check the elements to be reversed are smaller.
14194 Otherwise we'd get a reserved instruction. */
14195 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14196 gas_assert (elsize
!= 0);
14197 constraint (et
.size
>= elsize
,
14198 _("elements must be smaller than reversal region"));
14199 neon_two_same (neon_quad (rs
), 1, et
.size
);
14205 if (inst
.operands
[1].isscalar
)
14207 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14208 struct neon_type_el et
= neon_check_type (2, rs
,
14209 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14210 unsigned sizebits
= et
.size
>> 3;
14211 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14212 int logsize
= neon_logbits (et
.size
);
14213 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14215 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14218 NEON_ENCODE (SCALAR
, inst
);
14219 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14221 inst
.instruction
|= LOW4 (dm
);
14222 inst
.instruction
|= HI1 (dm
) << 5;
14223 inst
.instruction
|= neon_quad (rs
) << 6;
14224 inst
.instruction
|= x
<< 17;
14225 inst
.instruction
|= sizebits
<< 16;
14227 neon_dp_fixup (&inst
);
14231 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14232 struct neon_type_el et
= neon_check_type (2, rs
,
14233 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14234 /* Duplicate ARM register to lanes of vector. */
14235 NEON_ENCODE (ARMREG
, inst
);
14238 case 8: inst
.instruction
|= 0x400000; break;
14239 case 16: inst
.instruction
|= 0x000020; break;
14240 case 32: inst
.instruction
|= 0x000000; break;
14243 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14246 inst
.instruction
|= neon_quad (rs
) << 21;
14247 /* The encoding for this instruction is identical for the ARM and Thumb
14248 variants, except for the condition field. */
14249 do_vfp_cond_or_thumb ();
14253 /* VMOV has particularly many variations. It can be one of:
14254 0. VMOV<c><q> <Qd>, <Qm>
14255 1. VMOV<c><q> <Dd>, <Dm>
14256 (Register operations, which are VORR with Rm = Rn.)
14257 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14258 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14260 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14261 (ARM register to scalar.)
14262 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14263 (Two ARM registers to vector.)
14264 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14265 (Scalar to ARM register.)
14266 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14267 (Vector to two ARM registers.)
14268 8. VMOV.F32 <Sd>, <Sm>
14269 9. VMOV.F64 <Dd>, <Dm>
14270 (VFP register moves.)
14271 10. VMOV.F32 <Sd>, #imm
14272 11. VMOV.F64 <Dd>, #imm
14273 (VFP float immediate load.)
14274 12. VMOV <Rd>, <Sm>
14275 (VFP single to ARM reg.)
14276 13. VMOV <Sd>, <Rm>
14277 (ARM reg to VFP single.)
14278 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14279 (Two ARM regs to two VFP singles.)
14280 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14281 (Two VFP singles to two ARM regs.)
14283 These cases can be disambiguated using neon_select_shape, except cases 1/9
14284 and 3/11 which depend on the operand type too.
14286 All the encoded bits are hardcoded by this function.
14288 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14289 Cases 5, 7 may be used with VFPv2 and above.
14291 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14292 can specify a type where it doesn't make sense to, and is ignored). */
14297 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14298 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14300 struct neon_type_el et
;
14301 const char *ldconst
= 0;
14305 case NS_DD
: /* case 1/9. */
14306 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14307 /* It is not an error here if no type is given. */
14309 if (et
.type
== NT_float
&& et
.size
== 64)
14311 do_vfp_nsyn_opcode ("fcpyd");
14314 /* fall through. */
14316 case NS_QQ
: /* case 0/1. */
14318 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14320 /* The architecture manual I have doesn't explicitly state which
14321 value the U bit should have for register->register moves, but
14322 the equivalent VORR instruction has U = 0, so do that. */
14323 inst
.instruction
= 0x0200110;
14324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14326 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14327 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14328 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14329 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14330 inst
.instruction
|= neon_quad (rs
) << 6;
14332 neon_dp_fixup (&inst
);
14336 case NS_DI
: /* case 3/11. */
14337 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14339 if (et
.type
== NT_float
&& et
.size
== 64)
14341 /* case 11 (fconstd). */
14342 ldconst
= "fconstd";
14343 goto encode_fconstd
;
14345 /* fall through. */
14347 case NS_QI
: /* case 2/3. */
14348 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14350 inst
.instruction
= 0x0800010;
14351 neon_move_immediate ();
14352 neon_dp_fixup (&inst
);
14355 case NS_SR
: /* case 4. */
14357 unsigned bcdebits
= 0;
14359 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14360 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14362 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14363 logsize
= neon_logbits (et
.size
);
14365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14367 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14368 && et
.size
!= 32, _(BAD_FPU
));
14369 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14370 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14374 case 8: bcdebits
= 0x8; break;
14375 case 16: bcdebits
= 0x1; break;
14376 case 32: bcdebits
= 0x0; break;
14380 bcdebits
|= x
<< logsize
;
14382 inst
.instruction
= 0xe000b10;
14383 do_vfp_cond_or_thumb ();
14384 inst
.instruction
|= LOW4 (dn
) << 16;
14385 inst
.instruction
|= HI1 (dn
) << 7;
14386 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14387 inst
.instruction
|= (bcdebits
& 3) << 5;
14388 inst
.instruction
|= (bcdebits
>> 2) << 21;
14392 case NS_DRR
: /* case 5 (fmdrr). */
14393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14396 inst
.instruction
= 0xc400b10;
14397 do_vfp_cond_or_thumb ();
14398 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14399 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14400 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14401 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14404 case NS_RS
: /* case 6. */
14407 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14408 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14409 unsigned abcdebits
= 0;
14411 et
= neon_check_type (2, NS_NULL
,
14412 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14413 logsize
= neon_logbits (et
.size
);
14415 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14418 && et
.size
!= 32, _(BAD_FPU
));
14419 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14420 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14424 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14425 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14426 case 32: abcdebits
= 0x00; break;
14430 abcdebits
|= x
<< logsize
;
14431 inst
.instruction
= 0xe100b10;
14432 do_vfp_cond_or_thumb ();
14433 inst
.instruction
|= LOW4 (dn
) << 16;
14434 inst
.instruction
|= HI1 (dn
) << 7;
14435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14436 inst
.instruction
|= (abcdebits
& 3) << 5;
14437 inst
.instruction
|= (abcdebits
>> 2) << 21;
14441 case NS_RRD
: /* case 7 (fmrrd). */
14442 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14445 inst
.instruction
= 0xc500b10;
14446 do_vfp_cond_or_thumb ();
14447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14449 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14450 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14453 case NS_FF
: /* case 8 (fcpys). */
14454 do_vfp_nsyn_opcode ("fcpys");
14457 case NS_FI
: /* case 10 (fconsts). */
14458 ldconst
= "fconsts";
14460 if (is_quarter_float (inst
.operands
[1].imm
))
14462 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14463 do_vfp_nsyn_opcode (ldconst
);
14466 first_error (_("immediate out of range"));
14469 case NS_RF
: /* case 12 (fmrs). */
14470 do_vfp_nsyn_opcode ("fmrs");
14473 case NS_FR
: /* case 13 (fmsr). */
14474 do_vfp_nsyn_opcode ("fmsr");
14477 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14478 (one of which is a list), but we have parsed four. Do some fiddling to
14479 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14481 case NS_RRFF
: /* case 14 (fmrrs). */
14482 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14483 _("VFP registers must be adjacent"));
14484 inst
.operands
[2].imm
= 2;
14485 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14486 do_vfp_nsyn_opcode ("fmrrs");
14489 case NS_FFRR
: /* case 15 (fmsrr). */
14490 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14491 _("VFP registers must be adjacent"));
14492 inst
.operands
[1] = inst
.operands
[2];
14493 inst
.operands
[2] = inst
.operands
[3];
14494 inst
.operands
[0].imm
= 2;
14495 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14496 do_vfp_nsyn_opcode ("fmsrr");
14505 do_neon_rshift_round_imm (void)
14507 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14508 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14509 int imm
= inst
.operands
[2].imm
;
14511 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14514 inst
.operands
[2].present
= 0;
14519 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14520 _("immediate out of range for shift"));
14521 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14526 do_neon_movl (void)
14528 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14529 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14530 unsigned sizebits
= et
.size
>> 3;
14531 inst
.instruction
|= sizebits
<< 19;
14532 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14538 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14539 struct neon_type_el et
= neon_check_type (2, rs
,
14540 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14541 NEON_ENCODE (INTEGER
, inst
);
14542 neon_two_same (neon_quad (rs
), 1, et
.size
);
14546 do_neon_zip_uzp (void)
14548 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14549 struct neon_type_el et
= neon_check_type (2, rs
,
14550 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14551 if (rs
== NS_DD
&& et
.size
== 32)
14553 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14554 inst
.instruction
= N_MNEM_vtrn
;
14558 neon_two_same (neon_quad (rs
), 1, et
.size
);
14562 do_neon_sat_abs_neg (void)
14564 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14565 struct neon_type_el et
= neon_check_type (2, rs
,
14566 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14567 neon_two_same (neon_quad (rs
), 1, et
.size
);
14571 do_neon_pair_long (void)
14573 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14574 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14575 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14576 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14577 neon_two_same (neon_quad (rs
), 1, et
.size
);
14581 do_neon_recip_est (void)
14583 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14584 struct neon_type_el et
= neon_check_type (2, rs
,
14585 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14586 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14587 neon_two_same (neon_quad (rs
), 1, et
.size
);
14593 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14594 struct neon_type_el et
= neon_check_type (2, rs
,
14595 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14596 neon_two_same (neon_quad (rs
), 1, et
.size
);
14602 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14603 struct neon_type_el et
= neon_check_type (2, rs
,
14604 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14605 neon_two_same (neon_quad (rs
), 1, et
.size
);
14611 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14612 struct neon_type_el et
= neon_check_type (2, rs
,
14613 N_EQK
| N_INT
, N_8
| N_KEY
);
14614 neon_two_same (neon_quad (rs
), 1, et
.size
);
14620 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14621 neon_two_same (neon_quad (rs
), 1, -1);
14625 do_neon_tbl_tbx (void)
14627 unsigned listlenbits
;
14628 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14630 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14632 first_error (_("bad list length for table lookup"));
14636 listlenbits
= inst
.operands
[1].imm
- 1;
14637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14641 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14642 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14643 inst
.instruction
|= listlenbits
<< 8;
14645 neon_dp_fixup (&inst
);
14649 do_neon_ldm_stm (void)
14651 /* P, U and L bits are part of bitmask. */
14652 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14653 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14655 if (inst
.operands
[1].issingle
)
14657 do_vfp_nsyn_ldm_stm (is_dbmode
);
14661 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14662 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14664 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14665 _("register list must contain at least 1 and at most 16 "
14668 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14669 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14670 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14671 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14673 inst
.instruction
|= offsetbits
;
14675 do_vfp_cond_or_thumb ();
14679 do_neon_ldr_str (void)
14681 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14683 if (inst
.operands
[0].issingle
)
14686 do_vfp_nsyn_opcode ("flds");
14688 do_vfp_nsyn_opcode ("fsts");
14693 do_vfp_nsyn_opcode ("fldd");
14695 do_vfp_nsyn_opcode ("fstd");
14699 /* "interleave" version also handles non-interleaving register VLD1/VST1
14703 do_neon_ld_st_interleave (void)
14705 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14706 N_8
| N_16
| N_32
| N_64
);
14707 unsigned alignbits
= 0;
14709 /* The bits in this table go:
14710 0: register stride of one (0) or two (1)
14711 1,2: register list length, minus one (1, 2, 3, 4).
14712 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14713 We use -1 for invalid entries. */
14714 const int typetable
[] =
14716 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14717 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14718 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14719 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14723 if (et
.type
== NT_invtype
)
14726 if (inst
.operands
[1].immisalign
)
14727 switch (inst
.operands
[1].imm
>> 8)
14729 case 64: alignbits
= 1; break;
14731 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14732 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14733 goto bad_alignment
;
14737 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14738 goto bad_alignment
;
14743 first_error (_("bad alignment"));
14747 inst
.instruction
|= alignbits
<< 4;
14748 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14750 /* Bits [4:6] of the immediate in a list specifier encode register stride
14751 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14752 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14753 up the right value for "type" in a table based on this value and the given
14754 list style, then stick it back. */
14755 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14756 | (((inst
.instruction
>> 8) & 3) << 3);
14758 typebits
= typetable
[idx
];
14760 constraint (typebits
== -1, _("bad list type for instruction"));
14762 inst
.instruction
&= ~0xf00;
14763 inst
.instruction
|= typebits
<< 8;
14766 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14767 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14768 otherwise. The variable arguments are a list of pairs of legal (size, align)
14769 values, terminated with -1. */
14772 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14775 int result
= FAIL
, thissize
, thisalign
;
14777 if (!inst
.operands
[1].immisalign
)
14783 va_start (ap
, do_align
);
14787 thissize
= va_arg (ap
, int);
14788 if (thissize
== -1)
14790 thisalign
= va_arg (ap
, int);
14792 if (size
== thissize
&& align
== thisalign
)
14795 while (result
!= SUCCESS
);
14799 if (result
== SUCCESS
)
14802 first_error (_("unsupported alignment for instruction"));
14808 do_neon_ld_st_lane (void)
14810 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14811 int align_good
, do_align
= 0;
14812 int logsize
= neon_logbits (et
.size
);
14813 int align
= inst
.operands
[1].imm
>> 8;
14814 int n
= (inst
.instruction
>> 8) & 3;
14815 int max_el
= 64 / et
.size
;
14817 if (et
.type
== NT_invtype
)
14820 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14821 _("bad list length"));
14822 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14823 _("scalar index out of range"));
14824 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14826 _("stride of 2 unavailable when element size is 8"));
14830 case 0: /* VLD1 / VST1. */
14831 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14833 if (align_good
== FAIL
)
14837 unsigned alignbits
= 0;
14840 case 16: alignbits
= 0x1; break;
14841 case 32: alignbits
= 0x3; break;
14844 inst
.instruction
|= alignbits
<< 4;
14848 case 1: /* VLD2 / VST2. */
14849 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14851 if (align_good
== FAIL
)
14854 inst
.instruction
|= 1 << 4;
14857 case 2: /* VLD3 / VST3. */
14858 constraint (inst
.operands
[1].immisalign
,
14859 _("can't use alignment with this instruction"));
14862 case 3: /* VLD4 / VST4. */
14863 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14864 16, 64, 32, 64, 32, 128, -1);
14865 if (align_good
== FAIL
)
14869 unsigned alignbits
= 0;
14872 case 8: alignbits
= 0x1; break;
14873 case 16: alignbits
= 0x1; break;
14874 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14877 inst
.instruction
|= alignbits
<< 4;
14884 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14885 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14886 inst
.instruction
|= 1 << (4 + logsize
);
14888 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14889 inst
.instruction
|= logsize
<< 10;
14892 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14895 do_neon_ld_dup (void)
14897 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14898 int align_good
, do_align
= 0;
14900 if (et
.type
== NT_invtype
)
14903 switch ((inst
.instruction
>> 8) & 3)
14905 case 0: /* VLD1. */
14906 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14907 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14908 &do_align
, 16, 16, 32, 32, -1);
14909 if (align_good
== FAIL
)
14911 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14914 case 2: inst
.instruction
|= 1 << 5; break;
14915 default: first_error (_("bad list length")); return;
14917 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14920 case 1: /* VLD2. */
14921 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14922 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14923 if (align_good
== FAIL
)
14925 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14926 _("bad list length"));
14927 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14928 inst
.instruction
|= 1 << 5;
14929 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14932 case 2: /* VLD3. */
14933 constraint (inst
.operands
[1].immisalign
,
14934 _("can't use alignment with this instruction"));
14935 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14936 _("bad list length"));
14937 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14938 inst
.instruction
|= 1 << 5;
14939 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14942 case 3: /* VLD4. */
14944 int align
= inst
.operands
[1].imm
>> 8;
14945 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14946 16, 64, 32, 64, 32, 128, -1);
14947 if (align_good
== FAIL
)
14949 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14950 _("bad list length"));
14951 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14952 inst
.instruction
|= 1 << 5;
14953 if (et
.size
== 32 && align
== 128)
14954 inst
.instruction
|= 0x3 << 6;
14956 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14963 inst
.instruction
|= do_align
<< 4;
14966 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14967 apart from bits [11:4]. */
14970 do_neon_ldx_stx (void)
14972 if (inst
.operands
[1].isreg
)
14973 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
14975 switch (NEON_LANE (inst
.operands
[0].imm
))
14977 case NEON_INTERLEAVE_LANES
:
14978 NEON_ENCODE (INTERLV
, inst
);
14979 do_neon_ld_st_interleave ();
14982 case NEON_ALL_LANES
:
14983 NEON_ENCODE (DUP
, inst
);
14988 NEON_ENCODE (LANE
, inst
);
14989 do_neon_ld_st_lane ();
14992 /* L bit comes from bit mask. */
14993 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14994 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14997 if (inst
.operands
[1].postind
)
14999 int postreg
= inst
.operands
[1].imm
& 0xf;
15000 constraint (!inst
.operands
[1].immisreg
,
15001 _("post-index must be a register"));
15002 constraint (postreg
== 0xd || postreg
== 0xf,
15003 _("bad register for post-index"));
15004 inst
.instruction
|= postreg
;
15006 else if (inst
.operands
[1].writeback
)
15008 inst
.instruction
|= 0xd;
15011 inst
.instruction
|= 0xf;
15014 inst
.instruction
|= 0xf9000000;
15016 inst
.instruction
|= 0xf4000000;
15019 /* Overall per-instruction processing. */
15021 /* We need to be able to fix up arbitrary expressions in some statements.
15022 This is so that we can handle symbols that are an arbitrary distance from
15023 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15024 which returns part of an address in a form which will be valid for
15025 a data instruction. We do this by pushing the expression into a symbol
15026 in the expr_section, and creating a fix for that. */
15029 fix_new_arm (fragS
* frag
,
15044 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15045 (enum bfd_reloc_code_real
) reloc
);
15049 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15050 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15054 /* Mark whether the fix is to a THUMB instruction, or an ARM
15056 new_fix
->tc_fix_data
= thumb_mode
;
15059 /* Create a frg for an instruction requiring relaxation. */
15061 output_relax_insn (void)
15067 /* The size of the instruction is unknown, so tie the debug info to the
15068 start of the instruction. */
15069 dwarf2_emit_insn (0);
15071 switch (inst
.reloc
.exp
.X_op
)
15074 sym
= inst
.reloc
.exp
.X_add_symbol
;
15075 offset
= inst
.reloc
.exp
.X_add_number
;
15079 offset
= inst
.reloc
.exp
.X_add_number
;
15082 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15086 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15087 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15088 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15091 /* Write a 32-bit thumb instruction to buf. */
15093 put_thumb32_insn (char * buf
, unsigned long insn
)
15095 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15096 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15100 output_inst (const char * str
)
15106 as_bad ("%s -- `%s'", inst
.error
, str
);
15111 output_relax_insn ();
15114 if (inst
.size
== 0)
15117 to
= frag_more (inst
.size
);
15118 /* PR 9814: Record the thumb mode into the current frag so that we know
15119 what type of NOP padding to use, if necessary. We override any previous
15120 setting so that if the mode has changed then the NOPS that we use will
15121 match the encoding of the last instruction in the frag. */
15122 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15124 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15126 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15127 put_thumb32_insn (to
, inst
.instruction
);
15129 else if (inst
.size
> INSN_SIZE
)
15131 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15132 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15133 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15136 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15138 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15139 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15140 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15143 dwarf2_emit_insn (inst
.size
);
15147 output_it_inst (int cond
, int mask
, char * to
)
15149 unsigned long instruction
= 0xbf00;
15152 instruction
|= mask
;
15153 instruction
|= cond
<< 4;
15157 to
= frag_more (2);
15159 dwarf2_emit_insn (2);
15163 md_number_to_chars (to
, instruction
, 2);
15168 /* Tag values used in struct asm_opcode's tag field. */
15171 OT_unconditional
, /* Instruction cannot be conditionalized.
15172 The ARM condition field is still 0xE. */
15173 OT_unconditionalF
, /* Instruction cannot be conditionalized
15174 and carries 0xF in its ARM condition field. */
15175 OT_csuffix
, /* Instruction takes a conditional suffix. */
15176 OT_csuffixF
, /* Some forms of the instruction take a conditional
15177 suffix, others place 0xF where the condition field
15179 OT_cinfix3
, /* Instruction takes a conditional infix,
15180 beginning at character index 3. (In
15181 unified mode, it becomes a suffix.) */
15182 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15183 tsts, cmps, cmns, and teqs. */
15184 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15185 character index 3, even in unified mode. Used for
15186 legacy instructions where suffix and infix forms
15187 may be ambiguous. */
15188 OT_csuf_or_in3
, /* Instruction takes either a conditional
15189 suffix or an infix at character index 3. */
15190 OT_odd_infix_unc
, /* This is the unconditional variant of an
15191 instruction that takes a conditional infix
15192 at an unusual position. In unified mode,
15193 this variant will accept a suffix. */
15194 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15195 are the conditional variants of instructions that
15196 take conditional infixes in unusual positions.
15197 The infix appears at character index
15198 (tag - OT_odd_infix_0). These are not accepted
15199 in unified mode. */
15202 /* Subroutine of md_assemble, responsible for looking up the primary
15203 opcode from the mnemonic the user wrote. STR points to the
15204 beginning of the mnemonic.
15206 This is not simply a hash table lookup, because of conditional
15207 variants. Most instructions have conditional variants, which are
15208 expressed with a _conditional affix_ to the mnemonic. If we were
15209 to encode each conditional variant as a literal string in the opcode
15210 table, it would have approximately 20,000 entries.
15212 Most mnemonics take this affix as a suffix, and in unified syntax,
15213 'most' is upgraded to 'all'. However, in the divided syntax, some
15214 instructions take the affix as an infix, notably the s-variants of
15215 the arithmetic instructions. Of those instructions, all but six
15216 have the infix appear after the third character of the mnemonic.
15218 Accordingly, the algorithm for looking up primary opcodes given
15221 1. Look up the identifier in the opcode table.
15222 If we find a match, go to step U.
15224 2. Look up the last two characters of the identifier in the
15225 conditions table. If we find a match, look up the first N-2
15226 characters of the identifier in the opcode table. If we
15227 find a match, go to step CE.
15229 3. Look up the fourth and fifth characters of the identifier in
15230 the conditions table. If we find a match, extract those
15231 characters from the identifier, and look up the remaining
15232 characters in the opcode table. If we find a match, go
15237 U. Examine the tag field of the opcode structure, in case this is
15238 one of the six instructions with its conditional infix in an
15239 unusual place. If it is, the tag tells us where to find the
15240 infix; look it up in the conditions table and set inst.cond
15241 accordingly. Otherwise, this is an unconditional instruction.
15242 Again set inst.cond accordingly. Return the opcode structure.
15244 CE. Examine the tag field to make sure this is an instruction that
15245 should receive a conditional suffix. If it is not, fail.
15246 Otherwise, set inst.cond from the suffix we already looked up,
15247 and return the opcode structure.
15249 CM. Examine the tag field to make sure this is an instruction that
15250 should receive a conditional infix after the third character.
15251 If it is not, fail. Otherwise, undo the edits to the current
15252 line of input and proceed as for case CE. */
15254 static const struct asm_opcode
*
15255 opcode_lookup (char **str
)
15259 const struct asm_opcode
*opcode
;
15260 const struct asm_cond
*cond
;
15263 /* Scan up to the end of the mnemonic, which must end in white space,
15264 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15265 for (base
= end
= *str
; *end
!= '\0'; end
++)
15266 if (*end
== ' ' || *end
== '.')
15272 /* Handle a possible width suffix and/or Neon type suffix. */
15277 /* The .w and .n suffixes are only valid if the unified syntax is in
15279 if (unified_syntax
&& end
[1] == 'w')
15281 else if (unified_syntax
&& end
[1] == 'n')
15286 inst
.vectype
.elems
= 0;
15288 *str
= end
+ offset
;
15290 if (end
[offset
] == '.')
15292 /* See if we have a Neon type suffix (possible in either unified or
15293 non-unified ARM syntax mode). */
15294 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15297 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15303 /* Look for unaffixed or special-case affixed mnemonic. */
15304 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15309 if (opcode
->tag
< OT_odd_infix_0
)
15311 inst
.cond
= COND_ALWAYS
;
15315 if (warn_on_deprecated
&& unified_syntax
)
15316 as_warn (_("conditional infixes are deprecated in unified syntax"));
15317 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15318 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15321 inst
.cond
= cond
->value
;
15325 /* Cannot have a conditional suffix on a mnemonic of less than two
15327 if (end
- base
< 3)
15330 /* Look for suffixed mnemonic. */
15332 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15333 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15335 if (opcode
&& cond
)
15338 switch (opcode
->tag
)
15340 case OT_cinfix3_legacy
:
15341 /* Ignore conditional suffixes matched on infix only mnemonics. */
15345 case OT_cinfix3_deprecated
:
15346 case OT_odd_infix_unc
:
15347 if (!unified_syntax
)
15349 /* else fall through */
15353 case OT_csuf_or_in3
:
15354 inst
.cond
= cond
->value
;
15357 case OT_unconditional
:
15358 case OT_unconditionalF
:
15360 inst
.cond
= cond
->value
;
15363 /* Delayed diagnostic. */
15364 inst
.error
= BAD_COND
;
15365 inst
.cond
= COND_ALWAYS
;
15374 /* Cannot have a usual-position infix on a mnemonic of less than
15375 six characters (five would be a suffix). */
15376 if (end
- base
< 6)
15379 /* Look for infixed mnemonic in the usual position. */
15381 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15385 memcpy (save
, affix
, 2);
15386 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15387 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15389 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15390 memcpy (affix
, save
, 2);
15393 && (opcode
->tag
== OT_cinfix3
15394 || opcode
->tag
== OT_cinfix3_deprecated
15395 || opcode
->tag
== OT_csuf_or_in3
15396 || opcode
->tag
== OT_cinfix3_legacy
))
15399 if (warn_on_deprecated
&& unified_syntax
15400 && (opcode
->tag
== OT_cinfix3
15401 || opcode
->tag
== OT_cinfix3_deprecated
))
15402 as_warn (_("conditional infixes are deprecated in unified syntax"));
15404 inst
.cond
= cond
->value
;
15411 /* This function generates an initial IT instruction, leaving its block
15412 virtually open for the new instructions. Eventually,
15413 the mask will be updated by now_it_add_mask () each time
15414 a new instruction needs to be included in the IT block.
15415 Finally, the block is closed with close_automatic_it_block ().
15416 The block closure can be requested either from md_assemble (),
15417 a tencode (), or due to a label hook. */
15420 new_automatic_it_block (int cond
)
15422 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15423 now_it
.mask
= 0x18;
15425 now_it
.block_length
= 1;
15426 mapping_state (MAP_THUMB
);
15427 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15430 /* Close an automatic IT block.
15431 See comments in new_automatic_it_block (). */
15434 close_automatic_it_block (void)
15436 now_it
.mask
= 0x10;
15437 now_it
.block_length
= 0;
15440 /* Update the mask of the current automatically-generated IT
15441 instruction. See comments in new_automatic_it_block (). */
15444 now_it_add_mask (int cond
)
15446 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15447 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15448 | ((bitvalue) << (nbit)))
15449 const int resulting_bit
= (cond
& 1);
15451 now_it
.mask
&= 0xf;
15452 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15454 (5 - now_it
.block_length
));
15455 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15457 ((5 - now_it
.block_length
) - 1) );
15458 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15461 #undef SET_BIT_VALUE
15464 /* The IT blocks handling machinery is accessed through the these functions:
15465 it_fsm_pre_encode () from md_assemble ()
15466 set_it_insn_type () optional, from the tencode functions
15467 set_it_insn_type_last () ditto
15468 in_it_block () ditto
15469 it_fsm_post_encode () from md_assemble ()
15470 force_automatic_it_block_close () from label habdling functions
15473 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15474 initializing the IT insn type with a generic initial value depending
15475 on the inst.condition.
15476 2) During the tencode function, two things may happen:
15477 a) The tencode function overrides the IT insn type by
15478 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15479 b) The tencode function queries the IT block state by
15480 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15482 Both set_it_insn_type and in_it_block run the internal FSM state
15483 handling function (handle_it_state), because: a) setting the IT insn
15484 type may incur in an invalid state (exiting the function),
15485 and b) querying the state requires the FSM to be updated.
15486 Specifically we want to avoid creating an IT block for conditional
15487 branches, so it_fsm_pre_encode is actually a guess and we can't
15488 determine whether an IT block is required until the tencode () routine
15489 has decided what type of instruction this actually it.
15490 Because of this, if set_it_insn_type and in_it_block have to be used,
15491 set_it_insn_type has to be called first.
15493 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15494 determines the insn IT type depending on the inst.cond code.
15495 When a tencode () routine encodes an instruction that can be
15496 either outside an IT block, or, in the case of being inside, has to be
15497 the last one, set_it_insn_type_last () will determine the proper
15498 IT instruction type based on the inst.cond code. Otherwise,
15499 set_it_insn_type can be called for overriding that logic or
15500 for covering other cases.
15502 Calling handle_it_state () may not transition the IT block state to
15503 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15504 still queried. Instead, if the FSM determines that the state should
15505 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15506 after the tencode () function: that's what it_fsm_post_encode () does.
15508 Since in_it_block () calls the state handling function to get an
15509 updated state, an error may occur (due to invalid insns combination).
15510 In that case, inst.error is set.
15511 Therefore, inst.error has to be checked after the execution of
15512 the tencode () routine.
15514 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15515 any pending state change (if any) that didn't take place in
15516 handle_it_state () as explained above. */
15519 it_fsm_pre_encode (void)
15521 if (inst
.cond
!= COND_ALWAYS
)
15522 inst
.it_insn_type
= INSIDE_IT_INSN
;
15524 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15526 now_it
.state_handled
= 0;
15529 /* IT state FSM handling function. */
15532 handle_it_state (void)
15534 now_it
.state_handled
= 1;
15536 switch (now_it
.state
)
15538 case OUTSIDE_IT_BLOCK
:
15539 switch (inst
.it_insn_type
)
15541 case OUTSIDE_IT_INSN
:
15544 case INSIDE_IT_INSN
:
15545 case INSIDE_IT_LAST_INSN
:
15546 if (thumb_mode
== 0)
15549 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15550 as_tsktsk (_("Warning: conditional outside an IT block"\
15555 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15556 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15558 /* Automatically generate the IT instruction. */
15559 new_automatic_it_block (inst
.cond
);
15560 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15561 close_automatic_it_block ();
15565 inst
.error
= BAD_OUT_IT
;
15571 case IF_INSIDE_IT_LAST_INSN
:
15572 case NEUTRAL_IT_INSN
:
15576 now_it
.state
= MANUAL_IT_BLOCK
;
15577 now_it
.block_length
= 0;
15582 case AUTOMATIC_IT_BLOCK
:
15583 /* Three things may happen now:
15584 a) We should increment current it block size;
15585 b) We should close current it block (closing insn or 4 insns);
15586 c) We should close current it block and start a new one (due
15587 to incompatible conditions or
15588 4 insns-length block reached). */
15590 switch (inst
.it_insn_type
)
15592 case OUTSIDE_IT_INSN
:
15593 /* The closure of the block shall happen immediatelly,
15594 so any in_it_block () call reports the block as closed. */
15595 force_automatic_it_block_close ();
15598 case INSIDE_IT_INSN
:
15599 case INSIDE_IT_LAST_INSN
:
15600 case IF_INSIDE_IT_LAST_INSN
:
15601 now_it
.block_length
++;
15603 if (now_it
.block_length
> 4
15604 || !now_it_compatible (inst
.cond
))
15606 force_automatic_it_block_close ();
15607 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15608 new_automatic_it_block (inst
.cond
);
15612 now_it_add_mask (inst
.cond
);
15615 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15616 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15617 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15618 close_automatic_it_block ();
15621 case NEUTRAL_IT_INSN
:
15622 now_it
.block_length
++;
15624 if (now_it
.block_length
> 4)
15625 force_automatic_it_block_close ();
15627 now_it_add_mask (now_it
.cc
& 1);
15631 close_automatic_it_block ();
15632 now_it
.state
= MANUAL_IT_BLOCK
;
15637 case MANUAL_IT_BLOCK
:
15639 /* Check conditional suffixes. */
15640 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15643 now_it
.mask
&= 0x1f;
15644 is_last
= (now_it
.mask
== 0x10);
15646 switch (inst
.it_insn_type
)
15648 case OUTSIDE_IT_INSN
:
15649 inst
.error
= BAD_NOT_IT
;
15652 case INSIDE_IT_INSN
:
15653 if (cond
!= inst
.cond
)
15655 inst
.error
= BAD_IT_COND
;
15660 case INSIDE_IT_LAST_INSN
:
15661 case IF_INSIDE_IT_LAST_INSN
:
15662 if (cond
!= inst
.cond
)
15664 inst
.error
= BAD_IT_COND
;
15669 inst
.error
= BAD_BRANCH
;
15674 case NEUTRAL_IT_INSN
:
15675 /* The BKPT instruction is unconditional even in an IT block. */
15679 inst
.error
= BAD_IT_IT
;
15690 it_fsm_post_encode (void)
15694 if (!now_it
.state_handled
)
15695 handle_it_state ();
15697 is_last
= (now_it
.mask
== 0x10);
15700 now_it
.state
= OUTSIDE_IT_BLOCK
;
15706 force_automatic_it_block_close (void)
15708 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15710 close_automatic_it_block ();
15711 now_it
.state
= OUTSIDE_IT_BLOCK
;
15719 if (!now_it
.state_handled
)
15720 handle_it_state ();
15722 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15726 md_assemble (char *str
)
15729 const struct asm_opcode
* opcode
;
15731 /* Align the previous label if needed. */
15732 if (last_label_seen
!= NULL
)
15734 symbol_set_frag (last_label_seen
, frag_now
);
15735 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15736 S_SET_SEGMENT (last_label_seen
, now_seg
);
15739 memset (&inst
, '\0', sizeof (inst
));
15740 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15742 opcode
= opcode_lookup (&p
);
15745 /* It wasn't an instruction, but it might be a register alias of
15746 the form alias .req reg, or a Neon .dn/.qn directive. */
15747 if (! create_register_alias (str
, p
)
15748 && ! create_neon_reg_alias (str
, p
))
15749 as_bad (_("bad instruction `%s'"), str
);
15754 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15755 as_warn (_("s suffix on comparison instruction is deprecated"));
15757 /* The value which unconditional instructions should have in place of the
15758 condition field. */
15759 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15763 arm_feature_set variant
;
15765 variant
= cpu_variant
;
15766 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15767 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15768 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15769 /* Check that this instruction is supported for this CPU. */
15770 if (!opcode
->tvariant
15771 || (thumb_mode
== 1
15772 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15774 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15777 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15778 && opcode
->tencode
!= do_t_branch
)
15780 as_bad (_("Thumb does not support conditional execution"));
15784 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15786 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15787 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15788 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15790 /* Two things are addressed here.
15791 1) Implicit require narrow instructions on Thumb-1.
15792 This avoids relaxation accidentally introducing Thumb-2
15794 2) Reject wide instructions in non Thumb-2 cores. */
15795 if (inst
.size_req
== 0)
15797 else if (inst
.size_req
== 4)
15799 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15805 inst
.instruction
= opcode
->tvalue
;
15807 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15809 /* Prepare the it_insn_type for those encodings that don't set
15811 it_fsm_pre_encode ();
15813 opcode
->tencode ();
15815 it_fsm_post_encode ();
15818 if (!(inst
.error
|| inst
.relax
))
15820 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15821 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15822 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15824 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15829 /* Something has gone badly wrong if we try to relax a fixed size
15831 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15833 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15834 *opcode
->tvariant
);
15835 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15836 set those bits when Thumb-2 32-bit instructions are seen. ie.
15837 anything other than bl/blx and v6-M instructions.
15838 This is overly pessimistic for relaxable instructions. */
15839 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15841 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15842 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15843 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15846 check_neon_suffixes
;
15850 mapping_state (MAP_THUMB
);
15853 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15857 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15858 is_bx
= (opcode
->aencode
== do_bx
);
15860 /* Check that this instruction is supported for this CPU. */
15861 if (!(is_bx
&& fix_v4bx
)
15862 && !(opcode
->avariant
&&
15863 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15865 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15870 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15874 inst
.instruction
= opcode
->avalue
;
15875 if (opcode
->tag
== OT_unconditionalF
)
15876 inst
.instruction
|= 0xF << 28;
15878 inst
.instruction
|= inst
.cond
<< 28;
15879 inst
.size
= INSN_SIZE
;
15880 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15882 it_fsm_pre_encode ();
15883 opcode
->aencode ();
15884 it_fsm_post_encode ();
15886 /* Arm mode bx is marked as both v4T and v5 because it's still required
15887 on a hypothetical non-thumb v5 core. */
15889 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15891 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15892 *opcode
->avariant
);
15894 check_neon_suffixes
;
15898 mapping_state (MAP_ARM
);
15903 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15911 check_it_blocks_finished (void)
15916 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15917 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15918 == MANUAL_IT_BLOCK
)
15920 as_warn (_("section '%s' finished with an open IT block."),
15924 if (now_it
.state
== MANUAL_IT_BLOCK
)
15925 as_warn (_("file finished with an open IT block."));
15929 /* Various frobbings of labels and their addresses. */
15932 arm_start_line_hook (void)
15934 last_label_seen
= NULL
;
15938 arm_frob_label (symbolS
* sym
)
15940 last_label_seen
= sym
;
15942 ARM_SET_THUMB (sym
, thumb_mode
);
15944 #if defined OBJ_COFF || defined OBJ_ELF
15945 ARM_SET_INTERWORK (sym
, support_interwork
);
15948 force_automatic_it_block_close ();
15950 /* Note - do not allow local symbols (.Lxxx) to be labelled
15951 as Thumb functions. This is because these labels, whilst
15952 they exist inside Thumb code, are not the entry points for
15953 possible ARM->Thumb calls. Also, these labels can be used
15954 as part of a computed goto or switch statement. eg gcc
15955 can generate code that looks like this:
15957 ldr r2, [pc, .Laaa]
15967 The first instruction loads the address of the jump table.
15968 The second instruction converts a table index into a byte offset.
15969 The third instruction gets the jump address out of the table.
15970 The fourth instruction performs the jump.
15972 If the address stored at .Laaa is that of a symbol which has the
15973 Thumb_Func bit set, then the linker will arrange for this address
15974 to have the bottom bit set, which in turn would mean that the
15975 address computation performed by the third instruction would end
15976 up with the bottom bit set. Since the ARM is capable of unaligned
15977 word loads, the instruction would then load the incorrect address
15978 out of the jump table, and chaos would ensue. */
15979 if (label_is_thumb_function_name
15980 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15981 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15983 /* When the address of a Thumb function is taken the bottom
15984 bit of that address should be set. This will allow
15985 interworking between Arm and Thumb functions to work
15988 THUMB_SET_FUNC (sym
, 1);
15990 label_is_thumb_function_name
= FALSE
;
15993 dwarf2_emit_label (sym
);
15997 arm_data_in_code (void)
15999 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16001 *input_line_pointer
= '/';
16002 input_line_pointer
+= 5;
16003 *input_line_pointer
= 0;
16011 arm_canonicalize_symbol_name (char * name
)
16015 if (thumb_mode
&& (len
= strlen (name
)) > 5
16016 && streq (name
+ len
- 5, "/data"))
16017 *(name
+ len
- 5) = 0;
16022 /* Table of all register names defined by default. The user can
16023 define additional names with .req. Note that all register names
16024 should appear in both upper and lowercase variants. Some registers
16025 also have mixed-case names. */
16027 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16028 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16029 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16030 #define REGSET(p,t) \
16031 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16032 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16033 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16034 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16035 #define REGSETH(p,t) \
16036 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16037 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16038 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16039 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16040 #define REGSET2(p,t) \
16041 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16042 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16043 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16044 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16046 static const struct reg_entry reg_names
[] =
16048 /* ARM integer registers. */
16049 REGSET(r
, RN
), REGSET(R
, RN
),
16051 /* ATPCS synonyms. */
16052 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16053 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16054 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16056 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16057 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16058 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16060 /* Well-known aliases. */
16061 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16062 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16064 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16065 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16067 /* Coprocessor numbers. */
16068 REGSET(p
, CP
), REGSET(P
, CP
),
16070 /* Coprocessor register numbers. The "cr" variants are for backward
16072 REGSET(c
, CN
), REGSET(C
, CN
),
16073 REGSET(cr
, CN
), REGSET(CR
, CN
),
16075 /* FPA registers. */
16076 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16077 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16079 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16080 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16082 /* VFP SP registers. */
16083 REGSET(s
,VFS
), REGSET(S
,VFS
),
16084 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16086 /* VFP DP Registers. */
16087 REGSET(d
,VFD
), REGSET(D
,VFD
),
16088 /* Extra Neon DP registers. */
16089 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16091 /* Neon QP registers. */
16092 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16094 /* VFP control registers. */
16095 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16096 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16097 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16098 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16099 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16100 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16102 /* Maverick DSP coprocessor registers. */
16103 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16104 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16106 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16107 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16108 REGDEF(dspsc
,0,DSPSC
),
16110 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16111 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16112 REGDEF(DSPSC
,0,DSPSC
),
16114 /* iWMMXt data registers - p0, c0-15. */
16115 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16117 /* iWMMXt control registers - p1, c0-3. */
16118 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16119 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16120 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16121 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16123 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16124 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16125 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16126 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16127 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16129 /* XScale accumulator registers. */
16130 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16136 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16137 within psr_required_here. */
16138 static const struct asm_psr psrs
[] =
16140 /* Backward compatibility notation. Note that "all" is no longer
16141 truly all possible PSR bits. */
16142 {"all", PSR_c
| PSR_f
},
16146 /* Individual flags. */
16151 /* Combinations of flags. */
16152 {"fs", PSR_f
| PSR_s
},
16153 {"fx", PSR_f
| PSR_x
},
16154 {"fc", PSR_f
| PSR_c
},
16155 {"sf", PSR_s
| PSR_f
},
16156 {"sx", PSR_s
| PSR_x
},
16157 {"sc", PSR_s
| PSR_c
},
16158 {"xf", PSR_x
| PSR_f
},
16159 {"xs", PSR_x
| PSR_s
},
16160 {"xc", PSR_x
| PSR_c
},
16161 {"cf", PSR_c
| PSR_f
},
16162 {"cs", PSR_c
| PSR_s
},
16163 {"cx", PSR_c
| PSR_x
},
16164 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16165 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16166 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16167 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16168 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16169 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16170 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16171 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16172 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16173 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16174 {"scf", PSR_s
| PSR_c
| PSR_f
},
16175 {"scx", PSR_s
| PSR_c
| PSR_x
},
16176 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16177 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16178 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16179 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16180 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16181 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16182 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16183 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16184 {"csf", PSR_c
| PSR_s
| PSR_f
},
16185 {"csx", PSR_c
| PSR_s
| PSR_x
},
16186 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16187 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16188 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16189 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16190 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16191 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16192 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16193 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16194 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16195 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16196 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16197 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16198 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16199 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16200 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16201 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16202 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16203 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16204 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16205 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16206 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16207 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16208 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16209 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16210 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16211 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16214 /* Table of V7M psr names. */
16215 static const struct asm_psr v7m_psrs
[] =
16217 {"apsr", 0 }, {"APSR", 0 },
16218 {"iapsr", 1 }, {"IAPSR", 1 },
16219 {"eapsr", 2 }, {"EAPSR", 2 },
16220 {"psr", 3 }, {"PSR", 3 },
16221 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16222 {"ipsr", 5 }, {"IPSR", 5 },
16223 {"epsr", 6 }, {"EPSR", 6 },
16224 {"iepsr", 7 }, {"IEPSR", 7 },
16225 {"msp", 8 }, {"MSP", 8 },
16226 {"psp", 9 }, {"PSP", 9 },
16227 {"primask", 16}, {"PRIMASK", 16},
16228 {"basepri", 17}, {"BASEPRI", 17},
16229 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16230 {"faultmask", 19}, {"FAULTMASK", 19},
16231 {"control", 20}, {"CONTROL", 20}
16234 /* Table of all shift-in-operand names. */
16235 static const struct asm_shift_name shift_names
[] =
16237 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16238 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16239 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16240 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16241 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16242 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16245 /* Table of all explicit relocation names. */
16247 static struct reloc_entry reloc_names
[] =
16249 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16250 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16251 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16252 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16253 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16254 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16255 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16256 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16257 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16258 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16259 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16260 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16264 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16265 static const struct asm_cond conds
[] =
16269 {"cs", 0x2}, {"hs", 0x2},
16270 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16284 static struct asm_barrier_opt barrier_opt_names
[] =
16292 /* Table of ARM-format instructions. */
16294 /* Macros for gluing together operand strings. N.B. In all cases
16295 other than OPS0, the trailing OP_stop comes from default
16296 zero-initialization of the unspecified elements of the array. */
16297 #define OPS0() { OP_stop, }
16298 #define OPS1(a) { OP_##a, }
16299 #define OPS2(a,b) { OP_##a,OP_##b, }
16300 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16301 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16302 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16303 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16305 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16306 This is useful when mixing operands for ARM and THUMB, i.e. using the
16307 MIX_ARM_THUMB_OPERANDS macro.
16308 In order to use these macros, prefix the number of operands with _
16310 #define OPS_1(a) { a, }
16311 #define OPS_2(a,b) { a,b, }
16312 #define OPS_3(a,b,c) { a,b,c, }
16313 #define OPS_4(a,b,c,d) { a,b,c,d, }
16314 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16315 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16317 /* These macros abstract out the exact format of the mnemonic table and
16318 save some repeated characters. */
16320 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16321 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16322 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16323 THUMB_VARIANT, do_##ae, do_##te }
16325 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16326 a T_MNEM_xyz enumerator. */
16327 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16328 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16329 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16330 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16332 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16333 infix after the third character. */
16334 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16335 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16336 THUMB_VARIANT, do_##ae, do_##te }
16337 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16338 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16339 THUMB_VARIANT, do_##ae, do_##te }
16340 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16341 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16342 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16343 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16344 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16345 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16346 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16347 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16349 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16350 appear in the condition table. */
16351 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16352 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16353 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16355 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16356 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16357 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16358 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16359 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16360 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16361 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16362 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16363 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16364 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16365 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16366 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16367 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16368 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16369 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16370 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16371 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16372 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16373 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16374 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16376 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16377 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16378 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16379 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16381 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16382 field is still 0xE. Many of the Thumb variants can be executed
16383 conditionally, so this is checked separately. */
16384 #define TUE(mnem, op, top, nops, ops, ae, te) \
16385 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16386 THUMB_VARIANT, do_##ae, do_##te }
16388 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16389 condition code field. */
16390 #define TUF(mnem, op, top, nops, ops, ae, te) \
16391 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16392 THUMB_VARIANT, do_##ae, do_##te }
16394 /* ARM-only variants of all the above. */
16395 #define CE(mnem, op, nops, ops, ae) \
16396 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16398 #define C3(mnem, op, nops, ops, ae) \
16399 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16401 /* Legacy mnemonics that always have conditional infix after the third
16403 #define CL(mnem, op, nops, ops, ae) \
16404 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16405 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16407 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16408 #define cCE(mnem, op, nops, ops, ae) \
16409 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16411 /* Legacy coprocessor instructions where conditional infix and conditional
16412 suffix are ambiguous. For consistency this includes all FPA instructions,
16413 not just the potentially ambiguous ones. */
16414 #define cCL(mnem, op, nops, ops, ae) \
16415 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16416 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16418 /* Coprocessor, takes either a suffix or a position-3 infix
16419 (for an FPA corner case). */
16420 #define C3E(mnem, op, nops, ops, ae) \
16421 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16422 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16424 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16425 { m1 #m2 m3, OPS##nops ops, \
16426 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16427 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16429 #define CM(m1, m2, op, nops, ops, ae) \
16430 xCM_ (m1, , m2, op, nops, ops, ae), \
16431 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16432 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16433 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16434 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16435 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16436 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16437 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16438 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16439 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16440 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16441 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16442 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16443 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16444 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16445 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16446 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16447 xCM_ (m1, le, m2, op, nops, ops, ae), \
16448 xCM_ (m1, al, m2, op, nops, ops, ae)
16450 #define UE(mnem, op, nops, ops, ae) \
16451 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16453 #define UF(mnem, op, nops, ops, ae) \
16454 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16456 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16457 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16458 use the same encoding function for each. */
16459 #define NUF(mnem, op, nops, ops, enc) \
16460 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16461 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16463 /* Neon data processing, version which indirects through neon_enc_tab for
16464 the various overloaded versions of opcodes. */
16465 #define nUF(mnem, op, nops, ops, enc) \
16466 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16467 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16469 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16471 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16472 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16473 THUMB_VARIANT, do_##enc, do_##enc }
16475 #define NCE(mnem, op, nops, ops, enc) \
16476 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16478 #define NCEF(mnem, op, nops, ops, enc) \
16479 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16481 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16482 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16483 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16484 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16486 #define nCE(mnem, op, nops, ops, enc) \
16487 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16489 #define nCEF(mnem, op, nops, ops, enc) \
16490 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16494 static const struct asm_opcode insns
[] =
16496 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16497 #define THUMB_VARIANT &arm_ext_v4t
16498 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16499 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16500 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16501 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16502 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16503 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16504 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16505 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16506 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16507 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16508 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16509 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16510 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16511 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16512 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16513 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16515 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16516 for setting PSR flag bits. They are obsolete in V6 and do not
16517 have Thumb equivalents. */
16518 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16519 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16520 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16521 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16522 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16523 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16524 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16525 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16526 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16528 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16529 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16530 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16531 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16533 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16534 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16535 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16537 OP_ADDRGLDR
),ldst
, t_ldst
),
16538 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16540 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16541 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16542 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16543 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16544 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16545 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16547 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16548 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16549 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16550 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16553 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16554 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16555 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16557 /* Thumb-compatibility pseudo ops. */
16558 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16559 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16560 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16561 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16562 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16563 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16564 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16565 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16566 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16567 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16568 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16569 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16571 /* These may simplify to neg. */
16572 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16573 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16575 #undef THUMB_VARIANT
16576 #define THUMB_VARIANT & arm_ext_v6
16578 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16580 /* V1 instructions with no Thumb analogue prior to V6T2. */
16581 #undef THUMB_VARIANT
16582 #define THUMB_VARIANT & arm_ext_v6t2
16584 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16585 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16586 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16588 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16589 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16590 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16591 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16593 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16594 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16596 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16597 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16599 /* V1 instructions with no Thumb analogue at all. */
16600 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16601 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16603 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16604 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16605 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16606 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16607 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16608 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16609 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16610 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16613 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16614 #undef THUMB_VARIANT
16615 #define THUMB_VARIANT & arm_ext_v4t
16617 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16618 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16620 #undef THUMB_VARIANT
16621 #define THUMB_VARIANT & arm_ext_v6t2
16623 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16624 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16626 /* Generic coprocessor instructions. */
16627 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16628 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16629 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16630 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16631 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16632 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16633 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16636 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16638 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16639 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16642 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16643 #undef THUMB_VARIANT
16644 #define THUMB_VARIANT & arm_ext_msr
16646 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16647 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16650 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16651 #undef THUMB_VARIANT
16652 #define THUMB_VARIANT & arm_ext_v6t2
16654 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16655 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16656 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16657 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16658 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16659 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16660 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16661 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16664 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16665 #undef THUMB_VARIANT
16666 #define THUMB_VARIANT & arm_ext_v4t
16668 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16669 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16670 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16671 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16672 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16673 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16676 #define ARM_VARIANT & arm_ext_v4t_5
16678 /* ARM Architecture 4T. */
16679 /* Note: bx (and blx) are required on V5, even if the processor does
16680 not support Thumb. */
16681 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16684 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16685 #undef THUMB_VARIANT
16686 #define THUMB_VARIANT & arm_ext_v5t
16688 /* Note: blx has 2 variants; the .value coded here is for
16689 BLX(2). Only this variant has conditional execution. */
16690 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16691 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16693 #undef THUMB_VARIANT
16694 #define THUMB_VARIANT & arm_ext_v6t2
16696 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16697 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16698 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16699 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16700 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16701 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16702 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16703 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16706 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16707 #undef THUMB_VARIANT
16708 #define THUMB_VARIANT &arm_ext_v5exp
16710 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16711 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16712 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16713 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16715 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16716 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16718 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16719 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16720 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16721 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16723 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16724 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16725 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16726 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16728 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16729 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16731 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16732 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16733 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16734 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16737 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16738 #undef THUMB_VARIANT
16739 #define THUMB_VARIANT &arm_ext_v6t2
16741 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16742 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16744 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16745 ADDRGLDRS
), ldrd
, t_ldstd
),
16747 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16748 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16751 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16753 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16756 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16757 #undef THUMB_VARIANT
16758 #define THUMB_VARIANT & arm_ext_v6
16760 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16761 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16762 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16763 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16764 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16765 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16766 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16767 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16768 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16769 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16771 #undef THUMB_VARIANT
16772 #define THUMB_VARIANT & arm_ext_v6t2
16774 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16775 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16777 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16778 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16780 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16781 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16783 /* ARM V6 not included in V7M. */
16784 #undef THUMB_VARIANT
16785 #define THUMB_VARIANT & arm_ext_v6_notm
16786 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16787 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16788 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16789 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16790 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16791 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16792 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16793 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16794 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16795 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16796 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16797 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16799 /* ARM V6 not included in V7M (eg. integer SIMD). */
16800 #undef THUMB_VARIANT
16801 #define THUMB_VARIANT & arm_ext_v6_dsp
16802 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16803 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16804 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16805 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16806 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16807 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16808 /* Old name for QASX. */
16809 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16810 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16811 /* Old name for QSAX. */
16812 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16813 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16814 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16815 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16816 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16817 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16818 /* Old name for SASX. */
16819 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16820 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16821 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16822 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16823 /* Old name for SHASX. */
16824 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16825 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16826 /* Old name for SHSAX. */
16827 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16828 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16829 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16830 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16831 /* Old name for SSAX. */
16832 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16833 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16834 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16835 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16836 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16837 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16838 /* Old name for UASX. */
16839 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16840 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16841 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16842 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16843 /* Old name for UHASX. */
16844 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16845 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16846 /* Old name for UHSAX. */
16847 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16848 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16849 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16850 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16851 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16852 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16853 /* Old name for UQASX. */
16854 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16855 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16856 /* Old name for UQSAX. */
16857 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16858 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16859 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16860 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16861 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16862 /* Old name for USAX. */
16863 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16864 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16865 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16866 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16867 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16868 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16869 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16870 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16871 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16872 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16873 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16874 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16875 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16876 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16877 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16878 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16879 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16880 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16881 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16882 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16883 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16884 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16885 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16886 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16887 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16888 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16889 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16890 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16891 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16892 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16893 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16894 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16895 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16896 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16899 #define ARM_VARIANT & arm_ext_v6k
16900 #undef THUMB_VARIANT
16901 #define THUMB_VARIANT & arm_ext_v6k
16903 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16904 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16905 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16906 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16908 #undef THUMB_VARIANT
16909 #define THUMB_VARIANT & arm_ext_v6_notm
16910 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16912 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16913 RRnpcb
), strexd
, t_strexd
),
16915 #undef THUMB_VARIANT
16916 #define THUMB_VARIANT & arm_ext_v6t2
16917 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16919 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16921 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16923 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16925 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16928 #define ARM_VARIANT & arm_ext_v6z
16930 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16933 #define ARM_VARIANT & arm_ext_v6t2
16935 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16936 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16937 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16938 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16940 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16941 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16942 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16943 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16945 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16946 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16947 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16948 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16950 /* Thumb-only instructions. */
16952 #define ARM_VARIANT NULL
16953 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
16954 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
16956 /* ARM does not really have an IT instruction, so always allow it.
16957 The opcode is copied from Thumb in order to allow warnings in
16958 -mimplicit-it=[never | arm] modes. */
16960 #define ARM_VARIANT & arm_ext_v1
16962 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16963 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16964 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16965 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16966 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16967 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16968 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16969 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16970 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16971 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16972 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16973 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16974 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16975 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16976 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16977 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16978 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16979 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16981 /* Thumb2 only instructions. */
16983 #define ARM_VARIANT NULL
16985 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16986 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16987 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16988 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16989 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16990 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16992 /* Thumb-2 hardware division instructions (R and M profiles only). */
16993 #undef THUMB_VARIANT
16994 #define THUMB_VARIANT & arm_ext_div
16996 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16997 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16999 /* ARM V6M/V7 instructions. */
17001 #define ARM_VARIANT & arm_ext_barrier
17002 #undef THUMB_VARIANT
17003 #define THUMB_VARIANT & arm_ext_barrier
17005 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
17006 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
17007 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
17009 /* ARM V7 instructions. */
17011 #define ARM_VARIANT & arm_ext_v7
17012 #undef THUMB_VARIANT
17013 #define THUMB_VARIANT & arm_ext_v7
17015 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17016 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17019 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17021 cCE("wfs", e200110
, 1, (RR
), rd
),
17022 cCE("rfs", e300110
, 1, (RR
), rd
),
17023 cCE("wfc", e400110
, 1, (RR
), rd
),
17024 cCE("rfc", e500110
, 1, (RR
), rd
),
17026 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17027 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17028 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17029 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17031 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17032 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17033 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17034 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17036 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17037 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17038 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17039 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17040 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17041 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17042 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17043 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17044 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17045 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17046 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17047 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17049 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17050 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17051 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17052 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17053 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17054 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17055 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17056 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17057 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17058 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17059 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17060 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17062 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17063 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17064 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17065 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17066 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17067 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17068 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17069 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17070 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17071 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17072 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17073 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17075 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17076 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17077 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17078 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17079 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17080 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17081 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17082 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17083 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17084 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17085 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17086 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17088 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17089 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17090 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17091 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17092 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17095 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17098 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17102 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17104 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17108 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17121 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17134 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17147 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17245 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17246 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17247 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17248 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17249 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17250 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17251 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17252 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17253 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17254 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17255 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17257 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17258 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17259 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17260 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17261 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17262 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17263 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17264 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17265 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17266 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17267 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17268 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17270 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17271 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17272 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17273 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17274 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17275 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17276 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17277 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17278 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17279 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17280 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17281 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17283 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17284 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17285 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17286 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17287 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17288 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17289 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17290 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17291 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17292 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17293 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17294 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17296 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17297 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17298 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17299 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17300 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17303 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17306 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17310 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17312 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17316 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17329 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17338 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17342 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17343 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17345 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17351 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17355 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17356 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17358 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17364 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17414 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17415 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17416 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17418 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17419 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17420 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17421 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17422 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17423 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17424 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17425 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17426 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17427 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17428 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17429 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17431 /* The implementation of the FIX instruction is broken on some
17432 assemblers, in that it accepts a precision specifier as well as a
17433 rounding specifier, despite the fact that this is meaningless.
17434 To be more compatible, we accept it as well, though of course it
17435 does not set any bits. */
17436 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17437 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17438 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17439 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17440 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17441 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17442 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17443 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17444 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17445 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17446 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17447 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17448 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17450 /* Instructions that were new with the real FPA, call them V2. */
17452 #define ARM_VARIANT & fpu_fpa_ext_v2
17454 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17455 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17456 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17457 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17458 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17459 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17462 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17464 /* Moves and type conversions. */
17465 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17466 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17467 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17468 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17469 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17470 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17471 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17472 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17473 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17474 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17475 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17476 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17477 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17478 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17480 /* Memory operations. */
17481 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17482 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17483 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17484 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17485 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17486 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17487 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17488 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17489 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17490 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17491 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17492 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17493 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17494 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17495 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17496 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17497 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17498 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17500 /* Monadic operations. */
17501 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17502 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17503 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17505 /* Dyadic operations. */
17506 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17507 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17508 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17509 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17510 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17511 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17512 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17513 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17514 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17517 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17518 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17519 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17520 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17522 /* Double precision load/store are still present on single precision
17523 implementations. */
17524 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17525 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17526 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17527 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17528 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17529 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17530 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17531 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17532 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17533 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17536 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17538 /* Moves and type conversions. */
17539 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17540 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17541 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17542 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17543 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17544 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17545 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17546 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17547 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17548 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17549 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17550 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17551 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17553 /* Monadic operations. */
17554 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17555 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17556 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17558 /* Dyadic operations. */
17559 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17560 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17561 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17562 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17563 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17564 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17565 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17566 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17567 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17570 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17571 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17572 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17573 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17576 #define ARM_VARIANT & fpu_vfp_ext_v2
17578 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17579 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17580 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17581 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17583 /* Instructions which may belong to either the Neon or VFP instruction sets.
17584 Individual encoder functions perform additional architecture checks. */
17586 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17587 #undef THUMB_VARIANT
17588 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17590 /* These mnemonics are unique to VFP. */
17591 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17592 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17593 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17594 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17595 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17596 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17597 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17598 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17599 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17600 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17602 /* Mnemonics shared by Neon and VFP. */
17603 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17604 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17605 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17607 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17608 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17610 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17611 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17613 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17614 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17615 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17616 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17617 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17618 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17619 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17620 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17622 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17623 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17624 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17625 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17628 /* NOTE: All VMOV encoding is special-cased! */
17629 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17630 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17632 #undef THUMB_VARIANT
17633 #define THUMB_VARIANT & fpu_neon_ext_v1
17635 #define ARM_VARIANT & fpu_neon_ext_v1
17637 /* Data processing with three registers of the same length. */
17638 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17639 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17640 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17641 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17642 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17643 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17644 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17645 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17646 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17647 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17648 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17649 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17650 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17651 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17652 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17653 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17654 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17655 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17656 /* If not immediate, fall back to neon_dyadic_i64_su.
17657 shl_imm should accept I8 I16 I32 I64,
17658 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17659 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17660 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17661 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17662 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17663 /* Logic ops, types optional & ignored. */
17664 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17665 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17666 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17667 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17668 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17669 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17670 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17671 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17672 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17673 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17674 /* Bitfield ops, untyped. */
17675 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17676 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17677 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17678 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17679 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17680 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17681 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17682 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17683 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17684 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17685 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17686 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17687 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17688 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17689 back to neon_dyadic_if_su. */
17690 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17691 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17692 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17693 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17694 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17695 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17696 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17697 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17698 /* Comparison. Type I8 I16 I32 F32. */
17699 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17700 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17701 /* As above, D registers only. */
17702 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17703 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17704 /* Int and float variants, signedness unimportant. */
17705 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17706 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17707 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17708 /* Add/sub take types I8 I16 I32 I64 F32. */
17709 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17710 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17711 /* vtst takes sizes 8, 16, 32. */
17712 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17713 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17714 /* VMUL takes I8 I16 I32 F32 P8. */
17715 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17716 /* VQD{R}MULH takes S16 S32. */
17717 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17718 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17719 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17720 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17721 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17722 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17723 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17724 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17725 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17726 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17727 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17728 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17729 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17730 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17731 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17732 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17734 /* Two address, int/float. Types S8 S16 S32 F32. */
17735 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17736 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17738 /* Data processing with two registers and a shift amount. */
17739 /* Right shifts, and variants with rounding.
17740 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17741 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17742 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17743 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17744 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17745 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17746 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17747 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17748 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17749 /* Shift and insert. Sizes accepted 8 16 32 64. */
17750 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17751 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17752 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17753 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17754 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17755 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17756 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17757 /* Right shift immediate, saturating & narrowing, with rounding variants.
17758 Types accepted S16 S32 S64 U16 U32 U64. */
17759 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17760 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17761 /* As above, unsigned. Types accepted S16 S32 S64. */
17762 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17763 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17764 /* Right shift narrowing. Types accepted I16 I32 I64. */
17765 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17766 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17767 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17768 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17769 /* CVT with optional immediate for fixed-point variant. */
17770 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17772 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17773 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17775 /* Data processing, three registers of different lengths. */
17776 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17777 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17778 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17779 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17780 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17781 /* If not scalar, fall back to neon_dyadic_long.
17782 Vector types as above, scalar types S16 S32 U16 U32. */
17783 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17784 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17785 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17786 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17787 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17788 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17789 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17790 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17791 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17792 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17793 /* Saturating doubling multiplies. Types S16 S32. */
17794 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17795 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17796 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17797 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17798 S16 S32 U16 U32. */
17799 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17801 /* Extract. Size 8. */
17802 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17803 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17805 /* Two registers, miscellaneous. */
17806 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17807 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17808 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17809 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17810 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17811 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17812 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17813 /* Vector replicate. Sizes 8 16 32. */
17814 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17815 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17816 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17817 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17818 /* VMOVN. Types I16 I32 I64. */
17819 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17820 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17821 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17822 /* VQMOVUN. Types S16 S32 S64. */
17823 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17824 /* VZIP / VUZP. Sizes 8 16 32. */
17825 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17826 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17827 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17828 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17829 /* VQABS / VQNEG. Types S8 S16 S32. */
17830 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17831 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17832 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17833 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17834 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17835 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17836 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17837 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17838 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17839 /* Reciprocal estimates. Types U32 F32. */
17840 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17841 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17842 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17843 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17844 /* VCLS. Types S8 S16 S32. */
17845 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17846 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17847 /* VCLZ. Types I8 I16 I32. */
17848 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17849 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17850 /* VCNT. Size 8. */
17851 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17852 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17853 /* Two address, untyped. */
17854 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17855 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17856 /* VTRN. Sizes 8 16 32. */
17857 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17858 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17860 /* Table lookup. Size 8. */
17861 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17862 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17864 #undef THUMB_VARIANT
17865 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17867 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17869 /* Neon element/structure load/store. */
17870 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17871 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17872 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17873 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17874 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17875 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17876 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17877 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17879 #undef THUMB_VARIANT
17880 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17882 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17883 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17884 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17885 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17886 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17887 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17888 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17889 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17890 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17891 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17893 #undef THUMB_VARIANT
17894 #define THUMB_VARIANT & fpu_vfp_ext_v3
17896 #define ARM_VARIANT & fpu_vfp_ext_v3
17898 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17899 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17900 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17901 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17902 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17903 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17904 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17905 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17906 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17909 #define ARM_VARIANT &fpu_vfp_ext_fma
17910 #undef THUMB_VARIANT
17911 #define THUMB_VARIANT &fpu_vfp_ext_fma
17912 /* Mnemonics shared by Neon and VFP. These are included in the
17913 VFP FMA variant; NEON and VFP FMA always includes the NEON
17914 FMA instructions. */
17915 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17916 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17917 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17918 the v form should always be used. */
17919 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17920 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17921 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17922 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17923 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17924 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17926 #undef THUMB_VARIANT
17928 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17930 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17931 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17932 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17933 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17934 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17935 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17936 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17937 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17940 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17942 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17943 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17944 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17945 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17946 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17947 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17948 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17949 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17950 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17951 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17952 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17953 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17954 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17955 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17956 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17957 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17958 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17959 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17960 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17961 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17962 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17963 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17964 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17965 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17966 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17967 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17968 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17969 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17970 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17971 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17972 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17973 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17974 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17975 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17976 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17977 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17978 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17979 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17980 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17981 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17982 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17983 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17984 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17985 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17986 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17987 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17988 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17989 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17990 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17991 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17992 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17993 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17994 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17995 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17996 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17997 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17998 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17999 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18000 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18001 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18002 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18003 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18004 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18005 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18006 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18007 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18008 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18009 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18010 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18011 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18012 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18013 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18014 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18015 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18016 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18017 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18018 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18019 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18020 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18021 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18022 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18023 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18024 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18025 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18026 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18027 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18028 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18029 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18030 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18031 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18032 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18033 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18034 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18035 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18036 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18037 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18038 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18039 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18040 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18041 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18042 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18043 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18044 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18045 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18046 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18047 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18048 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18049 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18050 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18051 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18052 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18053 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18054 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18055 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18056 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18057 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18058 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18059 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18060 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18061 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18062 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18063 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18064 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18065 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18066 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18067 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18068 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18069 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18070 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18071 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18072 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18073 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18074 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18075 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18083 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18084 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18085 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18086 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18087 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18088 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18089 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18090 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18091 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18092 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18093 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18094 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18095 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18096 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18097 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18098 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18099 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18100 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18101 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18106 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18108 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18109 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18110 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18111 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18112 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18113 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18114 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18121 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18122 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18129 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18131 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18132 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18146 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18151 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18153 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18159 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18160 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18161 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18163 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18164 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18167 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18169 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18170 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18171 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18172 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18173 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18174 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18175 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18176 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18177 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18178 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18179 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18180 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18181 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18182 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18183 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18184 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18185 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18186 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18187 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18188 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18189 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18190 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18191 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18192 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18193 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18194 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18195 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18196 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18197 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18198 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18199 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18200 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18201 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18202 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18203 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18204 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18205 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18206 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18207 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18208 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18209 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18210 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18211 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18212 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18213 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18214 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18215 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18216 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18217 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18218 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18219 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18220 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18221 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18222 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18223 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18224 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18225 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18226 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18227 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18228 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18229 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18230 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18231 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18232 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18233 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18234 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18235 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18236 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18237 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18238 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18239 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18240 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18241 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18242 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18243 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18244 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18247 #undef THUMB_VARIANT
18274 /* MD interface: bits in the object file. */
18276 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18277 for use in the a.out file, and stores them in the array pointed to by buf.
18278 This knows about the endian-ness of the target machine and does
18279 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18280 2 (short) and 4 (long) Floating numbers are put out as a series of
18281 LITTLENUMS (shorts, here at least). */
18284 md_number_to_chars (char * buf
, valueT val
, int n
)
18286 if (target_big_endian
)
18287 number_to_chars_bigendian (buf
, val
, n
);
18289 number_to_chars_littleendian (buf
, val
, n
);
18293 md_chars_to_number (char * buf
, int n
)
18296 unsigned char * where
= (unsigned char *) buf
;
18298 if (target_big_endian
)
18303 result
|= (*where
++ & 255);
18311 result
|= (where
[n
] & 255);
18318 /* MD interface: Sections. */
18320 /* Estimate the size of a frag before relaxing. Assume everything fits in
18324 md_estimate_size_before_relax (fragS
* fragp
,
18325 segT segtype ATTRIBUTE_UNUSED
)
18331 /* Convert a machine dependent frag. */
18334 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18336 unsigned long insn
;
18337 unsigned long old_op
;
18345 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18347 old_op
= bfd_get_16(abfd
, buf
);
18348 if (fragp
->fr_symbol
)
18350 exp
.X_op
= O_symbol
;
18351 exp
.X_add_symbol
= fragp
->fr_symbol
;
18355 exp
.X_op
= O_constant
;
18357 exp
.X_add_number
= fragp
->fr_offset
;
18358 opcode
= fragp
->fr_subtype
;
18361 case T_MNEM_ldr_pc
:
18362 case T_MNEM_ldr_pc2
:
18363 case T_MNEM_ldr_sp
:
18364 case T_MNEM_str_sp
:
18371 if (fragp
->fr_var
== 4)
18373 insn
= THUMB_OP32 (opcode
);
18374 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18376 insn
|= (old_op
& 0x700) << 4;
18380 insn
|= (old_op
& 7) << 12;
18381 insn
|= (old_op
& 0x38) << 13;
18383 insn
|= 0x00000c00;
18384 put_thumb32_insn (buf
, insn
);
18385 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18389 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18391 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18394 if (fragp
->fr_var
== 4)
18396 insn
= THUMB_OP32 (opcode
);
18397 insn
|= (old_op
& 0xf0) << 4;
18398 put_thumb32_insn (buf
, insn
);
18399 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18403 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18404 exp
.X_add_number
-= 4;
18412 if (fragp
->fr_var
== 4)
18414 int r0off
= (opcode
== T_MNEM_mov
18415 || opcode
== T_MNEM_movs
) ? 0 : 8;
18416 insn
= THUMB_OP32 (opcode
);
18417 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18418 insn
|= (old_op
& 0x700) << r0off
;
18419 put_thumb32_insn (buf
, insn
);
18420 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18424 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18429 if (fragp
->fr_var
== 4)
18431 insn
= THUMB_OP32(opcode
);
18432 put_thumb32_insn (buf
, insn
);
18433 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18436 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18440 if (fragp
->fr_var
== 4)
18442 insn
= THUMB_OP32(opcode
);
18443 insn
|= (old_op
& 0xf00) << 14;
18444 put_thumb32_insn (buf
, insn
);
18445 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18448 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18451 case T_MNEM_add_sp
:
18452 case T_MNEM_add_pc
:
18453 case T_MNEM_inc_sp
:
18454 case T_MNEM_dec_sp
:
18455 if (fragp
->fr_var
== 4)
18457 /* ??? Choose between add and addw. */
18458 insn
= THUMB_OP32 (opcode
);
18459 insn
|= (old_op
& 0xf0) << 4;
18460 put_thumb32_insn (buf
, insn
);
18461 if (opcode
== T_MNEM_add_pc
)
18462 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18464 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18467 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18475 if (fragp
->fr_var
== 4)
18477 insn
= THUMB_OP32 (opcode
);
18478 insn
|= (old_op
& 0xf0) << 4;
18479 insn
|= (old_op
& 0xf) << 16;
18480 put_thumb32_insn (buf
, insn
);
18481 if (insn
& (1 << 20))
18482 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18484 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18487 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18493 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18494 (enum bfd_reloc_code_real
) reloc_type
);
18495 fixp
->fx_file
= fragp
->fr_file
;
18496 fixp
->fx_line
= fragp
->fr_line
;
18497 fragp
->fr_fix
+= fragp
->fr_var
;
18500 /* Return the size of a relaxable immediate operand instruction.
18501 SHIFT and SIZE specify the form of the allowable immediate. */
18503 relax_immediate (fragS
*fragp
, int size
, int shift
)
18509 /* ??? Should be able to do better than this. */
18510 if (fragp
->fr_symbol
)
18513 low
= (1 << shift
) - 1;
18514 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18515 offset
= fragp
->fr_offset
;
18516 /* Force misaligned offsets to 32-bit variant. */
18519 if (offset
& ~mask
)
18524 /* Get the address of a symbol during relaxation. */
18526 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18532 sym
= fragp
->fr_symbol
;
18533 sym_frag
= symbol_get_frag (sym
);
18534 know (S_GET_SEGMENT (sym
) != absolute_section
18535 || sym_frag
== &zero_address_frag
);
18536 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18538 /* If frag has yet to be reached on this pass, assume it will
18539 move by STRETCH just as we did. If this is not so, it will
18540 be because some frag between grows, and that will force
18544 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18548 /* Adjust stretch for any alignment frag. Note that if have
18549 been expanding the earlier code, the symbol may be
18550 defined in what appears to be an earlier frag. FIXME:
18551 This doesn't handle the fr_subtype field, which specifies
18552 a maximum number of bytes to skip when doing an
18554 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18556 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18559 stretch
= - ((- stretch
)
18560 & ~ ((1 << (int) f
->fr_offset
) - 1));
18562 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18574 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18577 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18582 /* Assume worst case for symbols not known to be in the same section. */
18583 if (fragp
->fr_symbol
== NULL
18584 || !S_IS_DEFINED (fragp
->fr_symbol
)
18585 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18586 || S_IS_WEAK (fragp
->fr_symbol
))
18589 val
= relaxed_symbol_addr (fragp
, stretch
);
18590 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18591 addr
= (addr
+ 4) & ~3;
18592 /* Force misaligned targets to 32-bit variant. */
18596 if (val
< 0 || val
> 1020)
18601 /* Return the size of a relaxable add/sub immediate instruction. */
18603 relax_addsub (fragS
*fragp
, asection
*sec
)
18608 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18609 op
= bfd_get_16(sec
->owner
, buf
);
18610 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18611 return relax_immediate (fragp
, 8, 0);
18613 return relax_immediate (fragp
, 3, 0);
18617 /* Return the size of a relaxable branch instruction. BITS is the
18618 size of the offset field in the narrow instruction. */
18621 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18627 /* Assume worst case for symbols not known to be in the same section. */
18628 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18629 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18630 || S_IS_WEAK (fragp
->fr_symbol
))
18634 if (S_IS_DEFINED (fragp
->fr_symbol
)
18635 && ARM_IS_FUNC (fragp
->fr_symbol
))
18639 val
= relaxed_symbol_addr (fragp
, stretch
);
18640 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18643 /* Offset is a signed value *2 */
18645 if (val
>= limit
|| val
< -limit
)
18651 /* Relax a machine dependent frag. This returns the amount by which
18652 the current size of the frag should change. */
18655 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18660 oldsize
= fragp
->fr_var
;
18661 switch (fragp
->fr_subtype
)
18663 case T_MNEM_ldr_pc2
:
18664 newsize
= relax_adr (fragp
, sec
, stretch
);
18666 case T_MNEM_ldr_pc
:
18667 case T_MNEM_ldr_sp
:
18668 case T_MNEM_str_sp
:
18669 newsize
= relax_immediate (fragp
, 8, 2);
18673 newsize
= relax_immediate (fragp
, 5, 2);
18677 newsize
= relax_immediate (fragp
, 5, 1);
18681 newsize
= relax_immediate (fragp
, 5, 0);
18684 newsize
= relax_adr (fragp
, sec
, stretch
);
18690 newsize
= relax_immediate (fragp
, 8, 0);
18693 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18696 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18698 case T_MNEM_add_sp
:
18699 case T_MNEM_add_pc
:
18700 newsize
= relax_immediate (fragp
, 8, 2);
18702 case T_MNEM_inc_sp
:
18703 case T_MNEM_dec_sp
:
18704 newsize
= relax_immediate (fragp
, 7, 2);
18710 newsize
= relax_addsub (fragp
, sec
);
18716 fragp
->fr_var
= newsize
;
18717 /* Freeze wide instructions that are at or before the same location as
18718 in the previous pass. This avoids infinite loops.
18719 Don't freeze them unconditionally because targets may be artificially
18720 misaligned by the expansion of preceding frags. */
18721 if (stretch
<= 0 && newsize
> 2)
18723 md_convert_frag (sec
->owner
, sec
, fragp
);
18727 return newsize
- oldsize
;
18730 /* Round up a section size to the appropriate boundary. */
18733 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18736 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18737 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18739 /* For a.out, force the section size to be aligned. If we don't do
18740 this, BFD will align it for us, but it will not write out the
18741 final bytes of the section. This may be a bug in BFD, but it is
18742 easier to fix it here since that is how the other a.out targets
18746 align
= bfd_get_section_alignment (stdoutput
, segment
);
18747 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18754 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18755 of an rs_align_code fragment. */
18758 arm_handle_align (fragS
* fragP
)
18760 static char const arm_noop
[2][2][4] =
18763 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18764 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18767 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18768 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18771 static char const thumb_noop
[2][2][2] =
18774 {0xc0, 0x46}, /* LE */
18775 {0x46, 0xc0}, /* BE */
18778 {0x00, 0xbf}, /* LE */
18779 {0xbf, 0x00} /* BE */
18782 static char const wide_thumb_noop
[2][4] =
18783 { /* Wide Thumb-2 */
18784 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18785 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18788 unsigned bytes
, fix
, noop_size
;
18791 const char *narrow_noop
= NULL
;
18796 if (fragP
->fr_type
!= rs_align_code
)
18799 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18800 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18803 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18804 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18806 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18808 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18810 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18812 narrow_noop
= thumb_noop
[1][target_big_endian
];
18813 noop
= wide_thumb_noop
[target_big_endian
];
18816 noop
= thumb_noop
[0][target_big_endian
];
18824 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18825 [target_big_endian
];
18832 fragP
->fr_var
= noop_size
;
18834 if (bytes
& (noop_size
- 1))
18836 fix
= bytes
& (noop_size
- 1);
18838 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18840 memset (p
, 0, fix
);
18847 if (bytes
& noop_size
)
18849 /* Insert a narrow noop. */
18850 memcpy (p
, narrow_noop
, noop_size
);
18852 bytes
-= noop_size
;
18856 /* Use wide noops for the remainder */
18860 while (bytes
>= noop_size
)
18862 memcpy (p
, noop
, noop_size
);
18864 bytes
-= noop_size
;
18868 fragP
->fr_fix
+= fix
;
18871 /* Called from md_do_align. Used to create an alignment
18872 frag in a code section. */
18875 arm_frag_align_code (int n
, int max
)
18879 /* We assume that there will never be a requirement
18880 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18881 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18886 _("alignments greater than %d bytes not supported in .text sections."),
18887 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18888 as_fatal ("%s", err_msg
);
18891 p
= frag_var (rs_align_code
,
18892 MAX_MEM_FOR_RS_ALIGN_CODE
,
18894 (relax_substateT
) max
,
18901 /* Perform target specific initialisation of a frag.
18902 Note - despite the name this initialisation is not done when the frag
18903 is created, but only when its type is assigned. A frag can be created
18904 and used a long time before its type is set, so beware of assuming that
18905 this initialisationis performed first. */
18909 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18911 /* Record whether this frag is in an ARM or a THUMB area. */
18912 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18915 #else /* OBJ_ELF is defined. */
18917 arm_init_frag (fragS
* fragP
, int max_chars
)
18919 /* If the current ARM vs THUMB mode has not already
18920 been recorded into this frag then do so now. */
18921 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18923 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18925 /* Record a mapping symbol for alignment frags. We will delete this
18926 later if the alignment ends up empty. */
18927 switch (fragP
->fr_type
)
18930 case rs_align_test
:
18932 mapping_state_2 (MAP_DATA
, max_chars
);
18934 case rs_align_code
:
18935 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18943 /* When we change sections we need to issue a new mapping symbol. */
18946 arm_elf_change_section (void)
18948 /* Link an unlinked unwind index table section to the .text section. */
18949 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18950 && elf_linked_to_section (now_seg
) == NULL
)
18951 elf_linked_to_section (now_seg
) = text_section
;
18955 arm_elf_section_type (const char * str
, size_t len
)
18957 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18958 return SHT_ARM_EXIDX
;
18963 /* Code to deal with unwinding tables. */
18965 static void add_unwind_adjustsp (offsetT
);
18967 /* Generate any deferred unwind frame offset. */
18970 flush_pending_unwind (void)
18974 offset
= unwind
.pending_offset
;
18975 unwind
.pending_offset
= 0;
18977 add_unwind_adjustsp (offset
);
18980 /* Add an opcode to this list for this function. Two-byte opcodes should
18981 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18985 add_unwind_opcode (valueT op
, int length
)
18987 /* Add any deferred stack adjustment. */
18988 if (unwind
.pending_offset
)
18989 flush_pending_unwind ();
18991 unwind
.sp_restored
= 0;
18993 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18995 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18996 if (unwind
.opcodes
)
18997 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18998 unwind
.opcode_alloc
);
19000 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19005 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19007 unwind
.opcode_count
++;
19011 /* Add unwind opcodes to adjust the stack pointer. */
19014 add_unwind_adjustsp (offsetT offset
)
19018 if (offset
> 0x200)
19020 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19025 /* Long form: 0xb2, uleb128. */
19026 /* This might not fit in a word so add the individual bytes,
19027 remembering the list is built in reverse order. */
19028 o
= (valueT
) ((offset
- 0x204) >> 2);
19030 add_unwind_opcode (0, 1);
19032 /* Calculate the uleb128 encoding of the offset. */
19036 bytes
[n
] = o
& 0x7f;
19042 /* Add the insn. */
19044 add_unwind_opcode (bytes
[n
- 1], 1);
19045 add_unwind_opcode (0xb2, 1);
19047 else if (offset
> 0x100)
19049 /* Two short opcodes. */
19050 add_unwind_opcode (0x3f, 1);
19051 op
= (offset
- 0x104) >> 2;
19052 add_unwind_opcode (op
, 1);
19054 else if (offset
> 0)
19056 /* Short opcode. */
19057 op
= (offset
- 4) >> 2;
19058 add_unwind_opcode (op
, 1);
19060 else if (offset
< 0)
19063 while (offset
> 0x100)
19065 add_unwind_opcode (0x7f, 1);
19068 op
= ((offset
- 4) >> 2) | 0x40;
19069 add_unwind_opcode (op
, 1);
19073 /* Finish the list of unwind opcodes for this function. */
19075 finish_unwind_opcodes (void)
19079 if (unwind
.fp_used
)
19081 /* Adjust sp as necessary. */
19082 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19083 flush_pending_unwind ();
19085 /* After restoring sp from the frame pointer. */
19086 op
= 0x90 | unwind
.fp_reg
;
19087 add_unwind_opcode (op
, 1);
19090 flush_pending_unwind ();
19094 /* Start an exception table entry. If idx is nonzero this is an index table
19098 start_unwind_section (const segT text_seg
, int idx
)
19100 const char * text_name
;
19101 const char * prefix
;
19102 const char * prefix_once
;
19103 const char * group_name
;
19107 size_t sec_name_len
;
19114 prefix
= ELF_STRING_ARM_unwind
;
19115 prefix_once
= ELF_STRING_ARM_unwind_once
;
19116 type
= SHT_ARM_EXIDX
;
19120 prefix
= ELF_STRING_ARM_unwind_info
;
19121 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19122 type
= SHT_PROGBITS
;
19125 text_name
= segment_name (text_seg
);
19126 if (streq (text_name
, ".text"))
19129 if (strncmp (text_name
, ".gnu.linkonce.t.",
19130 strlen (".gnu.linkonce.t.")) == 0)
19132 prefix
= prefix_once
;
19133 text_name
+= strlen (".gnu.linkonce.t.");
19136 prefix_len
= strlen (prefix
);
19137 text_len
= strlen (text_name
);
19138 sec_name_len
= prefix_len
+ text_len
;
19139 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19140 memcpy (sec_name
, prefix
, prefix_len
);
19141 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19142 sec_name
[prefix_len
+ text_len
] = '\0';
19148 /* Handle COMDAT group. */
19149 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19151 group_name
= elf_group_name (text_seg
);
19152 if (group_name
== NULL
)
19154 as_bad (_("Group section `%s' has no group signature"),
19155 segment_name (text_seg
));
19156 ignore_rest_of_line ();
19159 flags
|= SHF_GROUP
;
19163 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19165 /* Set the section link for index tables. */
19167 elf_linked_to_section (now_seg
) = text_seg
;
19171 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19172 personality routine data. Returns zero, or the index table value for
19173 and inline entry. */
19176 create_unwind_entry (int have_data
)
19181 /* The current word of data. */
19183 /* The number of bytes left in this word. */
19186 finish_unwind_opcodes ();
19188 /* Remember the current text section. */
19189 unwind
.saved_seg
= now_seg
;
19190 unwind
.saved_subseg
= now_subseg
;
19192 start_unwind_section (now_seg
, 0);
19194 if (unwind
.personality_routine
== NULL
)
19196 if (unwind
.personality_index
== -2)
19199 as_bad (_("handlerdata in cantunwind frame"));
19200 return 1; /* EXIDX_CANTUNWIND. */
19203 /* Use a default personality routine if none is specified. */
19204 if (unwind
.personality_index
== -1)
19206 if (unwind
.opcode_count
> 3)
19207 unwind
.personality_index
= 1;
19209 unwind
.personality_index
= 0;
19212 /* Space for the personality routine entry. */
19213 if (unwind
.personality_index
== 0)
19215 if (unwind
.opcode_count
> 3)
19216 as_bad (_("too many unwind opcodes for personality routine 0"));
19220 /* All the data is inline in the index table. */
19223 while (unwind
.opcode_count
> 0)
19225 unwind
.opcode_count
--;
19226 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19230 /* Pad with "finish" opcodes. */
19232 data
= (data
<< 8) | 0xb0;
19239 /* We get two opcodes "free" in the first word. */
19240 size
= unwind
.opcode_count
- 2;
19243 /* An extra byte is required for the opcode count. */
19244 size
= unwind
.opcode_count
+ 1;
19246 size
= (size
+ 3) >> 2;
19248 as_bad (_("too many unwind opcodes"));
19250 frag_align (2, 0, 0);
19251 record_alignment (now_seg
, 2);
19252 unwind
.table_entry
= expr_build_dot ();
19254 /* Allocate the table entry. */
19255 ptr
= frag_more ((size
<< 2) + 4);
19256 where
= frag_now_fix () - ((size
<< 2) + 4);
19258 switch (unwind
.personality_index
)
19261 /* ??? Should this be a PLT generating relocation? */
19262 /* Custom personality routine. */
19263 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19264 BFD_RELOC_ARM_PREL31
);
19269 /* Set the first byte to the number of additional words. */
19274 /* ABI defined personality routines. */
19276 /* Three opcodes bytes are packed into the first word. */
19283 /* The size and first two opcode bytes go in the first word. */
19284 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19289 /* Should never happen. */
19293 /* Pack the opcodes into words (MSB first), reversing the list at the same
19295 while (unwind
.opcode_count
> 0)
19299 md_number_to_chars (ptr
, data
, 4);
19304 unwind
.opcode_count
--;
19306 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19309 /* Finish off the last word. */
19312 /* Pad with "finish" opcodes. */
19314 data
= (data
<< 8) | 0xb0;
19316 md_number_to_chars (ptr
, data
, 4);
19321 /* Add an empty descriptor if there is no user-specified data. */
19322 ptr
= frag_more (4);
19323 md_number_to_chars (ptr
, 0, 4);
19330 /* Initialize the DWARF-2 unwind information for this procedure. */
19333 tc_arm_frame_initial_instructions (void)
19335 cfi_add_CFA_def_cfa (REG_SP
, 0);
19337 #endif /* OBJ_ELF */
19339 /* Convert REGNAME to a DWARF-2 register number. */
19342 tc_arm_regname_to_dw2regnum (char *regname
)
19344 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19354 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19358 exp
.X_op
= O_secrel
;
19359 exp
.X_add_symbol
= symbol
;
19360 exp
.X_add_number
= 0;
19361 emit_expr (&exp
, size
);
19365 /* MD interface: Symbol and relocation handling. */
19367 /* Return the address within the segment that a PC-relative fixup is
19368 relative to. For ARM, PC-relative fixups applied to instructions
19369 are generally relative to the location of the fixup plus 8 bytes.
19370 Thumb branches are offset by 4, and Thumb loads relative to PC
19371 require special handling. */
19374 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19376 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19378 /* If this is pc-relative and we are going to emit a relocation
19379 then we just want to put out any pipeline compensation that the linker
19380 will need. Otherwise we want to use the calculated base.
19381 For WinCE we skip the bias for externals as well, since this
19382 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19384 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19385 || (arm_force_relocation (fixP
)
19387 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19393 switch (fixP
->fx_r_type
)
19395 /* PC relative addressing on the Thumb is slightly odd as the
19396 bottom two bits of the PC are forced to zero for the
19397 calculation. This happens *after* application of the
19398 pipeline offset. However, Thumb adrl already adjusts for
19399 this, so we need not do it again. */
19400 case BFD_RELOC_ARM_THUMB_ADD
:
19403 case BFD_RELOC_ARM_THUMB_OFFSET
:
19404 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19405 case BFD_RELOC_ARM_T32_ADD_PC12
:
19406 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19407 return (base
+ 4) & ~3;
19409 /* Thumb branches are simply offset by +4. */
19410 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19411 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19412 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19413 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19414 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19417 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19419 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19420 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19421 && ARM_IS_FUNC (fixP
->fx_addsy
)
19422 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19423 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19426 /* BLX is like branches above, but forces the low two bits of PC to
19428 case BFD_RELOC_THUMB_PCREL_BLX
:
19430 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19431 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19432 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19433 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19434 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19435 return (base
+ 4) & ~3;
19437 /* ARM mode branches are offset by +8. However, the Windows CE
19438 loader expects the relocation not to take this into account. */
19439 case BFD_RELOC_ARM_PCREL_BLX
:
19441 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19442 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19443 && ARM_IS_FUNC (fixP
->fx_addsy
)
19444 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19445 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19448 case BFD_RELOC_ARM_PCREL_CALL
:
19450 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19451 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19452 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19453 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19454 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19457 case BFD_RELOC_ARM_PCREL_BRANCH
:
19458 case BFD_RELOC_ARM_PCREL_JUMP
:
19459 case BFD_RELOC_ARM_PLT32
:
19461 /* When handling fixups immediately, because we have already
19462 discovered the value of a symbol, or the address of the frag involved
19463 we must account for the offset by +8, as the OS loader will never see the reloc.
19464 see fixup_segment() in write.c
19465 The S_IS_EXTERNAL test handles the case of global symbols.
19466 Those need the calculated base, not just the pipe compensation the linker will need. */
19468 && fixP
->fx_addsy
!= NULL
19469 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19470 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19478 /* ARM mode loads relative to PC are also offset by +8. Unlike
19479 branches, the Windows CE loader *does* expect the relocation
19480 to take this into account. */
19481 case BFD_RELOC_ARM_OFFSET_IMM
:
19482 case BFD_RELOC_ARM_OFFSET_IMM8
:
19483 case BFD_RELOC_ARM_HWLITERAL
:
19484 case BFD_RELOC_ARM_LITERAL
:
19485 case BFD_RELOC_ARM_CP_OFF_IMM
:
19489 /* Other PC-relative relocations are un-offset. */
19495 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19496 Otherwise we have no need to default values of symbols. */
19499 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19502 if (name
[0] == '_' && name
[1] == 'G'
19503 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19507 if (symbol_find (name
))
19508 as_bad (_("GOT already in the symbol table"));
19510 GOT_symbol
= symbol_new (name
, undefined_section
,
19511 (valueT
) 0, & zero_address_frag
);
19521 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19522 computed as two separate immediate values, added together. We
19523 already know that this value cannot be computed by just one ARM
19526 static unsigned int
19527 validate_immediate_twopart (unsigned int val
,
19528 unsigned int * highpart
)
19533 for (i
= 0; i
< 32; i
+= 2)
19534 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19540 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19542 else if (a
& 0xff0000)
19544 if (a
& 0xff000000)
19546 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19550 gas_assert (a
& 0xff000000);
19551 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19554 return (a
& 0xff) | (i
<< 7);
19561 validate_offset_imm (unsigned int val
, int hwse
)
19563 if ((hwse
&& val
> 255) || val
> 4095)
19568 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19569 negative immediate constant by altering the instruction. A bit of
19574 by inverting the second operand, and
19577 by negating the second operand. */
19580 negate_data_op (unsigned long * instruction
,
19581 unsigned long value
)
19584 unsigned long negated
, inverted
;
19586 negated
= encode_arm_immediate (-value
);
19587 inverted
= encode_arm_immediate (~value
);
19589 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19592 /* First negates. */
19593 case OPCODE_SUB
: /* ADD <-> SUB */
19594 new_inst
= OPCODE_ADD
;
19599 new_inst
= OPCODE_SUB
;
19603 case OPCODE_CMP
: /* CMP <-> CMN */
19604 new_inst
= OPCODE_CMN
;
19609 new_inst
= OPCODE_CMP
;
19613 /* Now Inverted ops. */
19614 case OPCODE_MOV
: /* MOV <-> MVN */
19615 new_inst
= OPCODE_MVN
;
19620 new_inst
= OPCODE_MOV
;
19624 case OPCODE_AND
: /* AND <-> BIC */
19625 new_inst
= OPCODE_BIC
;
19630 new_inst
= OPCODE_AND
;
19634 case OPCODE_ADC
: /* ADC <-> SBC */
19635 new_inst
= OPCODE_SBC
;
19640 new_inst
= OPCODE_ADC
;
19644 /* We cannot do anything. */
19649 if (value
== (unsigned) FAIL
)
19652 *instruction
&= OPCODE_MASK
;
19653 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19657 /* Like negate_data_op, but for Thumb-2. */
19659 static unsigned int
19660 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19664 unsigned int negated
, inverted
;
19666 negated
= encode_thumb32_immediate (-value
);
19667 inverted
= encode_thumb32_immediate (~value
);
19669 rd
= (*instruction
>> 8) & 0xf;
19670 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19673 /* ADD <-> SUB. Includes CMP <-> CMN. */
19674 case T2_OPCODE_SUB
:
19675 new_inst
= T2_OPCODE_ADD
;
19679 case T2_OPCODE_ADD
:
19680 new_inst
= T2_OPCODE_SUB
;
19684 /* ORR <-> ORN. Includes MOV <-> MVN. */
19685 case T2_OPCODE_ORR
:
19686 new_inst
= T2_OPCODE_ORN
;
19690 case T2_OPCODE_ORN
:
19691 new_inst
= T2_OPCODE_ORR
;
19695 /* AND <-> BIC. TST has no inverted equivalent. */
19696 case T2_OPCODE_AND
:
19697 new_inst
= T2_OPCODE_BIC
;
19704 case T2_OPCODE_BIC
:
19705 new_inst
= T2_OPCODE_AND
;
19710 case T2_OPCODE_ADC
:
19711 new_inst
= T2_OPCODE_SBC
;
19715 case T2_OPCODE_SBC
:
19716 new_inst
= T2_OPCODE_ADC
;
19720 /* We cannot do anything. */
19725 if (value
== (unsigned int)FAIL
)
19728 *instruction
&= T2_OPCODE_MASK
;
19729 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19733 /* Read a 32-bit thumb instruction from buf. */
19734 static unsigned long
19735 get_thumb32_insn (char * buf
)
19737 unsigned long insn
;
19738 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19739 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19745 /* We usually want to set the low bit on the address of thumb function
19746 symbols. In particular .word foo - . should have the low bit set.
19747 Generic code tries to fold the difference of two symbols to
19748 a constant. Prevent this and force a relocation when the first symbols
19749 is a thumb function. */
19752 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19754 if (op
== O_subtract
19755 && l
->X_op
== O_symbol
19756 && r
->X_op
== O_symbol
19757 && THUMB_IS_FUNC (l
->X_add_symbol
))
19759 l
->X_op
= O_subtract
;
19760 l
->X_op_symbol
= r
->X_add_symbol
;
19761 l
->X_add_number
-= r
->X_add_number
;
19765 /* Process as normal. */
19769 /* Encode Thumb2 unconditional branches and calls. The encoding
19770 for the 2 are identical for the immediate values. */
19773 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19775 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19778 addressT S
, I1
, I2
, lo
, hi
;
19780 S
= (value
>> 24) & 0x01;
19781 I1
= (value
>> 23) & 0x01;
19782 I2
= (value
>> 22) & 0x01;
19783 hi
= (value
>> 12) & 0x3ff;
19784 lo
= (value
>> 1) & 0x7ff;
19785 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19786 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19787 newval
|= (S
<< 10) | hi
;
19788 newval2
&= ~T2I1I2MASK
;
19789 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19790 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19791 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19795 md_apply_fix (fixS
* fixP
,
19799 offsetT value
= * valP
;
19801 unsigned int newimm
;
19802 unsigned long temp
;
19804 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19806 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19808 /* Note whether this will delete the relocation. */
19810 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19813 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19814 consistency with the behaviour on 32-bit hosts. Remember value
19816 value
&= 0xffffffff;
19817 value
^= 0x80000000;
19818 value
-= 0x80000000;
19821 fixP
->fx_addnumber
= value
;
19823 /* Same treatment for fixP->fx_offset. */
19824 fixP
->fx_offset
&= 0xffffffff;
19825 fixP
->fx_offset
^= 0x80000000;
19826 fixP
->fx_offset
-= 0x80000000;
19828 switch (fixP
->fx_r_type
)
19830 case BFD_RELOC_NONE
:
19831 /* This will need to go in the object file. */
19835 case BFD_RELOC_ARM_IMMEDIATE
:
19836 /* We claim that this fixup has been processed here,
19837 even if in fact we generate an error because we do
19838 not have a reloc for it, so tc_gen_reloc will reject it. */
19841 if (fixP
->fx_addsy
)
19843 const char *msg
= 0;
19845 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19846 msg
= _("undefined symbol %s used as an immediate value");
19847 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19848 msg
= _("symbol %s is in a different section");
19849 else if (S_IS_WEAK (fixP
->fx_addsy
))
19850 msg
= _("symbol %s is weak and may be overridden later");
19854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19855 msg
, S_GET_NAME (fixP
->fx_addsy
));
19860 newimm
= encode_arm_immediate (value
);
19861 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19863 /* If the instruction will fail, see if we can fix things up by
19864 changing the opcode. */
19865 if (newimm
== (unsigned int) FAIL
19866 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19869 _("invalid constant (%lx) after fixup"),
19870 (unsigned long) value
);
19874 newimm
|= (temp
& 0xfffff000);
19875 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19878 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19880 unsigned int highpart
= 0;
19881 unsigned int newinsn
= 0xe1a00000; /* nop. */
19883 if (fixP
->fx_addsy
)
19885 const char *msg
= 0;
19887 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19888 msg
= _("undefined symbol %s used as an immediate value");
19889 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19890 msg
= _("symbol %s is in a different section");
19891 else if (S_IS_WEAK (fixP
->fx_addsy
))
19892 msg
= _("symbol %s is weak and may be overridden later");
19896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19897 msg
, S_GET_NAME (fixP
->fx_addsy
));
19902 newimm
= encode_arm_immediate (value
);
19903 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19905 /* If the instruction will fail, see if we can fix things up by
19906 changing the opcode. */
19907 if (newimm
== (unsigned int) FAIL
19908 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19910 /* No ? OK - try using two ADD instructions to generate
19912 newimm
= validate_immediate_twopart (value
, & highpart
);
19914 /* Yes - then make sure that the second instruction is
19916 if (newimm
!= (unsigned int) FAIL
)
19918 /* Still No ? Try using a negated value. */
19919 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19920 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19921 /* Otherwise - give up. */
19924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19925 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19930 /* Replace the first operand in the 2nd instruction (which
19931 is the PC) with the destination register. We have
19932 already added in the PC in the first instruction and we
19933 do not want to do it again. */
19934 newinsn
&= ~ 0xf0000;
19935 newinsn
|= ((newinsn
& 0x0f000) << 4);
19938 newimm
|= (temp
& 0xfffff000);
19939 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19941 highpart
|= (newinsn
& 0xfffff000);
19942 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19946 case BFD_RELOC_ARM_OFFSET_IMM
:
19947 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19950 case BFD_RELOC_ARM_LITERAL
:
19956 if (validate_offset_imm (value
, 0) == FAIL
)
19958 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19960 _("invalid literal constant: pool needs to be closer"));
19962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19963 _("bad immediate value for offset (%ld)"),
19968 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19969 newval
&= 0xff7ff000;
19970 newval
|= value
| (sign
? INDEX_UP
: 0);
19971 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19974 case BFD_RELOC_ARM_OFFSET_IMM8
:
19975 case BFD_RELOC_ARM_HWLITERAL
:
19981 if (validate_offset_imm (value
, 1) == FAIL
)
19983 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19985 _("invalid literal constant: pool needs to be closer"));
19987 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19992 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19993 newval
&= 0xff7ff0f0;
19994 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19995 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19998 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19999 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20001 _("bad immediate value for offset (%ld)"), (long) value
);
20004 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20006 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20009 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20010 /* This is a complicated relocation used for all varieties of Thumb32
20011 load/store instruction with immediate offset:
20013 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20014 *4, optional writeback(W)
20015 (doubleword load/store)
20017 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20018 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20019 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20020 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20021 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20023 Uppercase letters indicate bits that are already encoded at
20024 this point. Lowercase letters are our problem. For the
20025 second block of instructions, the secondary opcode nybble
20026 (bits 8..11) is present, and bit 23 is zero, even if this is
20027 a PC-relative operation. */
20028 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20030 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20032 if ((newval
& 0xf0000000) == 0xe0000000)
20034 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20036 newval
|= (1 << 23);
20039 if (value
% 4 != 0)
20041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20042 _("offset not a multiple of 4"));
20048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20049 _("offset out of range"));
20054 else if ((newval
& 0x000f0000) == 0x000f0000)
20056 /* PC-relative, 12-bit offset. */
20058 newval
|= (1 << 23);
20063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20064 _("offset out of range"));
20069 else if ((newval
& 0x00000100) == 0x00000100)
20071 /* Writeback: 8-bit, +/- offset. */
20073 newval
|= (1 << 9);
20078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20079 _("offset out of range"));
20084 else if ((newval
& 0x00000f00) == 0x00000e00)
20086 /* T-instruction: positive 8-bit offset. */
20087 if (value
< 0 || value
> 0xff)
20089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20090 _("offset out of range"));
20098 /* Positive 12-bit or negative 8-bit offset. */
20102 newval
|= (1 << 23);
20112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20113 _("offset out of range"));
20120 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20121 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20124 case BFD_RELOC_ARM_SHIFT_IMM
:
20125 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20126 if (((unsigned long) value
) > 32
20128 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20131 _("shift expression is too large"));
20136 /* Shifts of zero must be done as lsl. */
20138 else if (value
== 32)
20140 newval
&= 0xfffff07f;
20141 newval
|= (value
& 0x1f) << 7;
20142 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20145 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20146 case BFD_RELOC_ARM_T32_ADD_IMM
:
20147 case BFD_RELOC_ARM_T32_IMM12
:
20148 case BFD_RELOC_ARM_T32_ADD_PC12
:
20149 /* We claim that this fixup has been processed here,
20150 even if in fact we generate an error because we do
20151 not have a reloc for it, so tc_gen_reloc will reject it. */
20155 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20158 _("undefined symbol %s used as an immediate value"),
20159 S_GET_NAME (fixP
->fx_addsy
));
20163 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20165 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20168 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20169 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20171 newimm
= encode_thumb32_immediate (value
);
20172 if (newimm
== (unsigned int) FAIL
)
20173 newimm
= thumb32_negate_data_op (&newval
, value
);
20175 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20176 && newimm
== (unsigned int) FAIL
)
20178 /* Turn add/sum into addw/subw. */
20179 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20180 newval
= (newval
& 0xfeffffff) | 0x02000000;
20182 /* 12 bit immediate for addw/subw. */
20186 newval
^= 0x00a00000;
20189 newimm
= (unsigned int) FAIL
;
20194 if (newimm
== (unsigned int)FAIL
)
20196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20197 _("invalid constant (%lx) after fixup"),
20198 (unsigned long) value
);
20202 newval
|= (newimm
& 0x800) << 15;
20203 newval
|= (newimm
& 0x700) << 4;
20204 newval
|= (newimm
& 0x0ff);
20206 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20207 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20210 case BFD_RELOC_ARM_SMC
:
20211 if (((unsigned long) value
) > 0xffff)
20212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20213 _("invalid smc expression"));
20214 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20215 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20216 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20219 case BFD_RELOC_ARM_SWI
:
20220 if (fixP
->tc_fix_data
!= 0)
20222 if (((unsigned long) value
) > 0xff)
20223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20224 _("invalid swi expression"));
20225 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20227 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20231 if (((unsigned long) value
) > 0x00ffffff)
20232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20233 _("invalid swi expression"));
20234 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20236 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20240 case BFD_RELOC_ARM_MULTI
:
20241 if (((unsigned long) value
) > 0xffff)
20242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20243 _("invalid expression in load/store multiple"));
20244 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20245 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20249 case BFD_RELOC_ARM_PCREL_CALL
:
20251 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20253 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20254 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20255 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20256 /* Flip the bl to blx. This is a simple flip
20257 bit here because we generate PCREL_CALL for
20258 unconditional bls. */
20260 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20261 newval
= newval
| 0x10000000;
20262 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20268 goto arm_branch_common
;
20270 case BFD_RELOC_ARM_PCREL_JUMP
:
20271 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20273 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20274 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20275 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20277 /* This would map to a bl<cond>, b<cond>,
20278 b<always> to a Thumb function. We
20279 need to force a relocation for this particular
20281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20285 case BFD_RELOC_ARM_PLT32
:
20287 case BFD_RELOC_ARM_PCREL_BRANCH
:
20289 goto arm_branch_common
;
20291 case BFD_RELOC_ARM_PCREL_BLX
:
20294 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20296 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20297 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20298 && ARM_IS_FUNC (fixP
->fx_addsy
))
20300 /* Flip the blx to a bl and warn. */
20301 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20302 newval
= 0xeb000000;
20303 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20304 _("blx to '%s' an ARM ISA state function changed to bl"),
20306 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20312 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20313 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20317 /* We are going to store value (shifted right by two) in the
20318 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20319 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20320 also be be clear. */
20322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20323 _("misaligned branch destination"));
20324 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20325 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20327 _("branch out of range"));
20329 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20331 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20332 newval
|= (value
>> 2) & 0x00ffffff;
20333 /* Set the H bit on BLX instructions. */
20337 newval
|= 0x01000000;
20339 newval
&= ~0x01000000;
20341 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20345 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20346 /* CBZ can only branch forward. */
20348 /* Attempts to use CBZ to branch to the next instruction
20349 (which, strictly speaking, are prohibited) will be turned into
20352 FIXME: It may be better to remove the instruction completely and
20353 perform relaxation. */
20356 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20357 newval
= 0xbf00; /* NOP encoding T1 */
20358 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20364 _("branch out of range"));
20366 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20368 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20369 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20370 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20375 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20376 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20378 _("branch out of range"));
20380 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20382 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20383 newval
|= (value
& 0x1ff) >> 1;
20384 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20388 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20389 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20391 _("branch out of range"));
20393 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20395 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20396 newval
|= (value
& 0xfff) >> 1;
20397 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20401 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20403 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20404 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20405 && S_IS_DEFINED (fixP
->fx_addsy
)
20406 && ARM_IS_FUNC (fixP
->fx_addsy
)
20407 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20409 /* Force a relocation for a branch 20 bits wide. */
20412 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20414 _("conditional branch out of range"));
20416 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20419 addressT S
, J1
, J2
, lo
, hi
;
20421 S
= (value
& 0x00100000) >> 20;
20422 J2
= (value
& 0x00080000) >> 19;
20423 J1
= (value
& 0x00040000) >> 18;
20424 hi
= (value
& 0x0003f000) >> 12;
20425 lo
= (value
& 0x00000ffe) >> 1;
20427 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20428 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20429 newval
|= (S
<< 10) | hi
;
20430 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20431 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20432 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20436 case BFD_RELOC_THUMB_PCREL_BLX
:
20438 /* If there is a blx from a thumb state function to
20439 another thumb function flip this to a bl and warn
20443 && S_IS_DEFINED (fixP
->fx_addsy
)
20444 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20445 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20446 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20448 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20449 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20450 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20452 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20453 newval
= newval
| 0x1000;
20454 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20455 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20460 goto thumb_bl_common
;
20462 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20464 /* A bl from Thumb state ISA to an internal ARM state function
20465 is converted to a blx. */
20467 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20468 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20469 && S_IS_DEFINED (fixP
->fx_addsy
)
20470 && ARM_IS_FUNC (fixP
->fx_addsy
)
20471 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20473 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20474 newval
= newval
& ~0x1000;
20475 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20476 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20483 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20484 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20485 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20488 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20489 /* For a BLX instruction, make sure that the relocation is rounded up
20490 to a word boundary. This follows the semantics of the instruction
20491 which specifies that bit 1 of the target address will come from bit
20492 1 of the base address. */
20493 value
= (value
+ 1) & ~ 1;
20496 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20498 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20501 _("branch out of range"));
20503 else if ((value
& ~0x1ffffff)
20504 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20507 _("Thumb2 branch out of range"));
20511 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20512 encode_thumb2_b_bl_offset (buf
, value
);
20516 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20517 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20519 _("branch out of range"));
20521 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20522 encode_thumb2_b_bl_offset (buf
, value
);
20527 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20528 md_number_to_chars (buf
, value
, 1);
20532 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20533 md_number_to_chars (buf
, value
, 2);
20537 case BFD_RELOC_ARM_TLS_GD32
:
20538 case BFD_RELOC_ARM_TLS_LE32
:
20539 case BFD_RELOC_ARM_TLS_IE32
:
20540 case BFD_RELOC_ARM_TLS_LDM32
:
20541 case BFD_RELOC_ARM_TLS_LDO32
:
20542 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20545 case BFD_RELOC_ARM_GOT32
:
20546 case BFD_RELOC_ARM_GOTOFF
:
20547 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20548 md_number_to_chars (buf
, 0, 4);
20551 case BFD_RELOC_ARM_GOT_PREL
:
20552 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20553 md_number_to_chars (buf
, value
, 4);
20556 case BFD_RELOC_ARM_TARGET2
:
20557 /* TARGET2 is not partial-inplace, so we need to write the
20558 addend here for REL targets, because it won't be written out
20559 during reloc processing later. */
20560 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20561 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20565 case BFD_RELOC_RVA
:
20567 case BFD_RELOC_ARM_TARGET1
:
20568 case BFD_RELOC_ARM_ROSEGREL32
:
20569 case BFD_RELOC_ARM_SBREL32
:
20570 case BFD_RELOC_32_PCREL
:
20572 case BFD_RELOC_32_SECREL
:
20574 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20576 /* For WinCE we only do this for pcrel fixups. */
20577 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20579 md_number_to_chars (buf
, value
, 4);
20583 case BFD_RELOC_ARM_PREL31
:
20584 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20586 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20587 if ((value
^ (value
>> 1)) & 0x40000000)
20589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20590 _("rel31 relocation overflow"));
20592 newval
|= value
& 0x7fffffff;
20593 md_number_to_chars (buf
, newval
, 4);
20598 case BFD_RELOC_ARM_CP_OFF_IMM
:
20599 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20600 if (value
< -1023 || value
> 1023 || (value
& 3))
20601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20602 _("co-processor offset out of range"));
20607 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20608 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20609 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20611 newval
= get_thumb32_insn (buf
);
20612 newval
&= 0xff7fff00;
20613 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20614 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20615 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20616 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20618 put_thumb32_insn (buf
, newval
);
20621 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20622 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20623 if (value
< -255 || value
> 255)
20624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20625 _("co-processor offset out of range"));
20627 goto cp_off_common
;
20629 case BFD_RELOC_ARM_THUMB_OFFSET
:
20630 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20631 /* Exactly what ranges, and where the offset is inserted depends
20632 on the type of instruction, we can establish this from the
20634 switch (newval
>> 12)
20636 case 4: /* PC load. */
20637 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20638 forced to zero for these loads; md_pcrel_from has already
20639 compensated for this. */
20641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20642 _("invalid offset, target not word aligned (0x%08lX)"),
20643 (((unsigned long) fixP
->fx_frag
->fr_address
20644 + (unsigned long) fixP
->fx_where
) & ~3)
20645 + (unsigned long) value
);
20647 if (value
& ~0x3fc)
20648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20649 _("invalid offset, value too big (0x%08lX)"),
20652 newval
|= value
>> 2;
20655 case 9: /* SP load/store. */
20656 if (value
& ~0x3fc)
20657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20658 _("invalid offset, value too big (0x%08lX)"),
20660 newval
|= value
>> 2;
20663 case 6: /* Word load/store. */
20665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20666 _("invalid offset, value too big (0x%08lX)"),
20668 newval
|= value
<< 4; /* 6 - 2. */
20671 case 7: /* Byte load/store. */
20673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20674 _("invalid offset, value too big (0x%08lX)"),
20676 newval
|= value
<< 6;
20679 case 8: /* Halfword load/store. */
20681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20682 _("invalid offset, value too big (0x%08lX)"),
20684 newval
|= value
<< 5; /* 6 - 1. */
20688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20689 "Unable to process relocation for thumb opcode: %lx",
20690 (unsigned long) newval
);
20693 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20696 case BFD_RELOC_ARM_THUMB_ADD
:
20697 /* This is a complicated relocation, since we use it for all of
20698 the following immediate relocations:
20702 9bit ADD/SUB SP word-aligned
20703 10bit ADD PC/SP word-aligned
20705 The type of instruction being processed is encoded in the
20712 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20714 int rd
= (newval
>> 4) & 0xf;
20715 int rs
= newval
& 0xf;
20716 int subtract
= !!(newval
& 0x8000);
20718 /* Check for HI regs, only very restricted cases allowed:
20719 Adjusting SP, and using PC or SP to get an address. */
20720 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20721 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20723 _("invalid Hi register with immediate"));
20725 /* If value is negative, choose the opposite instruction. */
20729 subtract
= !subtract
;
20731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20732 _("immediate value out of range"));
20737 if (value
& ~0x1fc)
20738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20739 _("invalid immediate for stack address calculation"));
20740 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20741 newval
|= value
>> 2;
20743 else if (rs
== REG_PC
|| rs
== REG_SP
)
20745 if (subtract
|| value
& ~0x3fc)
20746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20747 _("invalid immediate for address calculation (value = 0x%08lX)"),
20748 (unsigned long) value
);
20749 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20751 newval
|= value
>> 2;
20756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20757 _("immediate value out of range"));
20758 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20759 newval
|= (rd
<< 8) | value
;
20764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20765 _("immediate value out of range"));
20766 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20767 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20770 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20773 case BFD_RELOC_ARM_THUMB_IMM
:
20774 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20775 if (value
< 0 || value
> 255)
20776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20777 _("invalid immediate: %ld is out of range"),
20780 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20783 case BFD_RELOC_ARM_THUMB_SHIFT
:
20784 /* 5bit shift value (0..32). LSL cannot take 32. */
20785 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20786 temp
= newval
& 0xf800;
20787 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20789 _("invalid shift value: %ld"), (long) value
);
20790 /* Shifts of zero must be encoded as LSL. */
20792 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20793 /* Shifts of 32 are encoded as zero. */
20794 else if (value
== 32)
20796 newval
|= value
<< 6;
20797 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20800 case BFD_RELOC_VTABLE_INHERIT
:
20801 case BFD_RELOC_VTABLE_ENTRY
:
20805 case BFD_RELOC_ARM_MOVW
:
20806 case BFD_RELOC_ARM_MOVT
:
20807 case BFD_RELOC_ARM_THUMB_MOVW
:
20808 case BFD_RELOC_ARM_THUMB_MOVT
:
20809 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20811 /* REL format relocations are limited to a 16-bit addend. */
20812 if (!fixP
->fx_done
)
20814 if (value
< -0x8000 || value
> 0x7fff)
20815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20816 _("offset out of range"));
20818 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20819 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20824 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20825 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20827 newval
= get_thumb32_insn (buf
);
20828 newval
&= 0xfbf08f00;
20829 newval
|= (value
& 0xf000) << 4;
20830 newval
|= (value
& 0x0800) << 15;
20831 newval
|= (value
& 0x0700) << 4;
20832 newval
|= (value
& 0x00ff);
20833 put_thumb32_insn (buf
, newval
);
20837 newval
= md_chars_to_number (buf
, 4);
20838 newval
&= 0xfff0f000;
20839 newval
|= value
& 0x0fff;
20840 newval
|= (value
& 0xf000) << 4;
20841 md_number_to_chars (buf
, newval
, 4);
20846 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20847 case BFD_RELOC_ARM_ALU_PC_G0
:
20848 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20849 case BFD_RELOC_ARM_ALU_PC_G1
:
20850 case BFD_RELOC_ARM_ALU_PC_G2
:
20851 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20852 case BFD_RELOC_ARM_ALU_SB_G0
:
20853 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20854 case BFD_RELOC_ARM_ALU_SB_G1
:
20855 case BFD_RELOC_ARM_ALU_SB_G2
:
20856 gas_assert (!fixP
->fx_done
);
20857 if (!seg
->use_rela_p
)
20860 bfd_vma encoded_addend
;
20861 bfd_vma addend_abs
= abs (value
);
20863 /* Check that the absolute value of the addend can be
20864 expressed as an 8-bit constant plus a rotation. */
20865 encoded_addend
= encode_arm_immediate (addend_abs
);
20866 if (encoded_addend
== (unsigned int) FAIL
)
20867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20868 _("the offset 0x%08lX is not representable"),
20869 (unsigned long) addend_abs
);
20871 /* Extract the instruction. */
20872 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20874 /* If the addend is positive, use an ADD instruction.
20875 Otherwise use a SUB. Take care not to destroy the S bit. */
20876 insn
&= 0xff1fffff;
20882 /* Place the encoded addend into the first 12 bits of the
20884 insn
&= 0xfffff000;
20885 insn
|= encoded_addend
;
20887 /* Update the instruction. */
20888 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20892 case BFD_RELOC_ARM_LDR_PC_G0
:
20893 case BFD_RELOC_ARM_LDR_PC_G1
:
20894 case BFD_RELOC_ARM_LDR_PC_G2
:
20895 case BFD_RELOC_ARM_LDR_SB_G0
:
20896 case BFD_RELOC_ARM_LDR_SB_G1
:
20897 case BFD_RELOC_ARM_LDR_SB_G2
:
20898 gas_assert (!fixP
->fx_done
);
20899 if (!seg
->use_rela_p
)
20902 bfd_vma addend_abs
= abs (value
);
20904 /* Check that the absolute value of the addend can be
20905 encoded in 12 bits. */
20906 if (addend_abs
>= 0x1000)
20907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20908 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20909 (unsigned long) addend_abs
);
20911 /* Extract the instruction. */
20912 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20914 /* If the addend is negative, clear bit 23 of the instruction.
20915 Otherwise set it. */
20917 insn
&= ~(1 << 23);
20921 /* Place the absolute value of the addend into the first 12 bits
20922 of the instruction. */
20923 insn
&= 0xfffff000;
20924 insn
|= addend_abs
;
20926 /* Update the instruction. */
20927 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20931 case BFD_RELOC_ARM_LDRS_PC_G0
:
20932 case BFD_RELOC_ARM_LDRS_PC_G1
:
20933 case BFD_RELOC_ARM_LDRS_PC_G2
:
20934 case BFD_RELOC_ARM_LDRS_SB_G0
:
20935 case BFD_RELOC_ARM_LDRS_SB_G1
:
20936 case BFD_RELOC_ARM_LDRS_SB_G2
:
20937 gas_assert (!fixP
->fx_done
);
20938 if (!seg
->use_rela_p
)
20941 bfd_vma addend_abs
= abs (value
);
20943 /* Check that the absolute value of the addend can be
20944 encoded in 8 bits. */
20945 if (addend_abs
>= 0x100)
20946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20947 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20948 (unsigned long) addend_abs
);
20950 /* Extract the instruction. */
20951 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20953 /* If the addend is negative, clear bit 23 of the instruction.
20954 Otherwise set it. */
20956 insn
&= ~(1 << 23);
20960 /* Place the first four bits of the absolute value of the addend
20961 into the first 4 bits of the instruction, and the remaining
20962 four into bits 8 .. 11. */
20963 insn
&= 0xfffff0f0;
20964 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20966 /* Update the instruction. */
20967 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20971 case BFD_RELOC_ARM_LDC_PC_G0
:
20972 case BFD_RELOC_ARM_LDC_PC_G1
:
20973 case BFD_RELOC_ARM_LDC_PC_G2
:
20974 case BFD_RELOC_ARM_LDC_SB_G0
:
20975 case BFD_RELOC_ARM_LDC_SB_G1
:
20976 case BFD_RELOC_ARM_LDC_SB_G2
:
20977 gas_assert (!fixP
->fx_done
);
20978 if (!seg
->use_rela_p
)
20981 bfd_vma addend_abs
= abs (value
);
20983 /* Check that the absolute value of the addend is a multiple of
20984 four and, when divided by four, fits in 8 bits. */
20985 if (addend_abs
& 0x3)
20986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20987 _("bad offset 0x%08lX (must be word-aligned)"),
20988 (unsigned long) addend_abs
);
20990 if ((addend_abs
>> 2) > 0xff)
20991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20992 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20993 (unsigned long) addend_abs
);
20995 /* Extract the instruction. */
20996 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20998 /* If the addend is negative, clear bit 23 of the instruction.
20999 Otherwise set it. */
21001 insn
&= ~(1 << 23);
21005 /* Place the addend (divided by four) into the first eight
21006 bits of the instruction. */
21007 insn
&= 0xfffffff0;
21008 insn
|= addend_abs
>> 2;
21010 /* Update the instruction. */
21011 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21015 case BFD_RELOC_ARM_V4BX
:
21016 /* This will need to go in the object file. */
21020 case BFD_RELOC_UNUSED
:
21022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21023 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21027 /* Translate internal representation of relocation info to BFD target
21031 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21034 bfd_reloc_code_real_type code
;
21036 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21038 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21039 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21040 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21042 if (fixp
->fx_pcrel
)
21044 if (section
->use_rela_p
)
21045 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21047 fixp
->fx_offset
= reloc
->address
;
21049 reloc
->addend
= fixp
->fx_offset
;
21051 switch (fixp
->fx_r_type
)
21054 if (fixp
->fx_pcrel
)
21056 code
= BFD_RELOC_8_PCREL
;
21061 if (fixp
->fx_pcrel
)
21063 code
= BFD_RELOC_16_PCREL
;
21068 if (fixp
->fx_pcrel
)
21070 code
= BFD_RELOC_32_PCREL
;
21074 case BFD_RELOC_ARM_MOVW
:
21075 if (fixp
->fx_pcrel
)
21077 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21081 case BFD_RELOC_ARM_MOVT
:
21082 if (fixp
->fx_pcrel
)
21084 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21088 case BFD_RELOC_ARM_THUMB_MOVW
:
21089 if (fixp
->fx_pcrel
)
21091 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21095 case BFD_RELOC_ARM_THUMB_MOVT
:
21096 if (fixp
->fx_pcrel
)
21098 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21102 case BFD_RELOC_NONE
:
21103 case BFD_RELOC_ARM_PCREL_BRANCH
:
21104 case BFD_RELOC_ARM_PCREL_BLX
:
21105 case BFD_RELOC_RVA
:
21106 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21107 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21108 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21109 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21110 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21111 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21112 case BFD_RELOC_VTABLE_ENTRY
:
21113 case BFD_RELOC_VTABLE_INHERIT
:
21115 case BFD_RELOC_32_SECREL
:
21117 code
= fixp
->fx_r_type
;
21120 case BFD_RELOC_THUMB_PCREL_BLX
:
21122 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21123 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21126 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21129 case BFD_RELOC_ARM_LITERAL
:
21130 case BFD_RELOC_ARM_HWLITERAL
:
21131 /* If this is called then the a literal has
21132 been referenced across a section boundary. */
21133 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21134 _("literal referenced across section boundary"));
21138 case BFD_RELOC_ARM_GOT32
:
21139 case BFD_RELOC_ARM_GOTOFF
:
21140 case BFD_RELOC_ARM_GOT_PREL
:
21141 case BFD_RELOC_ARM_PLT32
:
21142 case BFD_RELOC_ARM_TARGET1
:
21143 case BFD_RELOC_ARM_ROSEGREL32
:
21144 case BFD_RELOC_ARM_SBREL32
:
21145 case BFD_RELOC_ARM_PREL31
:
21146 case BFD_RELOC_ARM_TARGET2
:
21147 case BFD_RELOC_ARM_TLS_LE32
:
21148 case BFD_RELOC_ARM_TLS_LDO32
:
21149 case BFD_RELOC_ARM_PCREL_CALL
:
21150 case BFD_RELOC_ARM_PCREL_JUMP
:
21151 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21152 case BFD_RELOC_ARM_ALU_PC_G0
:
21153 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21154 case BFD_RELOC_ARM_ALU_PC_G1
:
21155 case BFD_RELOC_ARM_ALU_PC_G2
:
21156 case BFD_RELOC_ARM_LDR_PC_G0
:
21157 case BFD_RELOC_ARM_LDR_PC_G1
:
21158 case BFD_RELOC_ARM_LDR_PC_G2
:
21159 case BFD_RELOC_ARM_LDRS_PC_G0
:
21160 case BFD_RELOC_ARM_LDRS_PC_G1
:
21161 case BFD_RELOC_ARM_LDRS_PC_G2
:
21162 case BFD_RELOC_ARM_LDC_PC_G0
:
21163 case BFD_RELOC_ARM_LDC_PC_G1
:
21164 case BFD_RELOC_ARM_LDC_PC_G2
:
21165 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21166 case BFD_RELOC_ARM_ALU_SB_G0
:
21167 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21168 case BFD_RELOC_ARM_ALU_SB_G1
:
21169 case BFD_RELOC_ARM_ALU_SB_G2
:
21170 case BFD_RELOC_ARM_LDR_SB_G0
:
21171 case BFD_RELOC_ARM_LDR_SB_G1
:
21172 case BFD_RELOC_ARM_LDR_SB_G2
:
21173 case BFD_RELOC_ARM_LDRS_SB_G0
:
21174 case BFD_RELOC_ARM_LDRS_SB_G1
:
21175 case BFD_RELOC_ARM_LDRS_SB_G2
:
21176 case BFD_RELOC_ARM_LDC_SB_G0
:
21177 case BFD_RELOC_ARM_LDC_SB_G1
:
21178 case BFD_RELOC_ARM_LDC_SB_G2
:
21179 case BFD_RELOC_ARM_V4BX
:
21180 code
= fixp
->fx_r_type
;
21183 case BFD_RELOC_ARM_TLS_GD32
:
21184 case BFD_RELOC_ARM_TLS_IE32
:
21185 case BFD_RELOC_ARM_TLS_LDM32
:
21186 /* BFD will include the symbol's address in the addend.
21187 But we don't want that, so subtract it out again here. */
21188 if (!S_IS_COMMON (fixp
->fx_addsy
))
21189 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21190 code
= fixp
->fx_r_type
;
21194 case BFD_RELOC_ARM_IMMEDIATE
:
21195 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21196 _("internal relocation (type: IMMEDIATE) not fixed up"));
21199 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21200 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21201 _("ADRL used for a symbol not defined in the same file"));
21204 case BFD_RELOC_ARM_OFFSET_IMM
:
21205 if (section
->use_rela_p
)
21207 code
= fixp
->fx_r_type
;
21211 if (fixp
->fx_addsy
!= NULL
21212 && !S_IS_DEFINED (fixp
->fx_addsy
)
21213 && S_IS_LOCAL (fixp
->fx_addsy
))
21215 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21216 _("undefined local label `%s'"),
21217 S_GET_NAME (fixp
->fx_addsy
));
21221 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21222 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21229 switch (fixp
->fx_r_type
)
21231 case BFD_RELOC_NONE
: type
= "NONE"; break;
21232 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21233 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21234 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21235 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21236 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21237 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21238 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21239 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21240 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21241 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21242 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21243 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21244 default: type
= _("<unknown>"); break;
21246 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21247 _("cannot represent %s relocation in this object file format"),
21254 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21256 && fixp
->fx_addsy
== GOT_symbol
)
21258 code
= BFD_RELOC_ARM_GOTPC
;
21259 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21263 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21265 if (reloc
->howto
== NULL
)
21267 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21268 _("cannot represent %s relocation in this object file format"),
21269 bfd_get_reloc_code_name (code
));
21273 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21274 vtable entry to be used in the relocation's section offset. */
21275 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21276 reloc
->address
= fixp
->fx_offset
;
21281 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21284 cons_fix_new_arm (fragS
* frag
,
21289 bfd_reloc_code_real_type type
;
21293 FIXME: @@ Should look at CPU word size. */
21297 type
= BFD_RELOC_8
;
21300 type
= BFD_RELOC_16
;
21304 type
= BFD_RELOC_32
;
21307 type
= BFD_RELOC_64
;
21312 if (exp
->X_op
== O_secrel
)
21314 exp
->X_op
= O_symbol
;
21315 type
= BFD_RELOC_32_SECREL
;
21319 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21322 #if defined (OBJ_COFF)
21324 arm_validate_fix (fixS
* fixP
)
21326 /* If the destination of the branch is a defined symbol which does not have
21327 the THUMB_FUNC attribute, then we must be calling a function which has
21328 the (interfacearm) attribute. We look for the Thumb entry point to that
21329 function and change the branch to refer to that function instead. */
21330 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21331 && fixP
->fx_addsy
!= NULL
21332 && S_IS_DEFINED (fixP
->fx_addsy
)
21333 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21335 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21342 arm_force_relocation (struct fix
* fixp
)
21344 #if defined (OBJ_COFF) && defined (TE_PE)
21345 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21349 /* In case we have a call or a branch to a function in ARM ISA mode from
21350 a thumb function or vice-versa force the relocation. These relocations
21351 are cleared off for some cores that might have blx and simple transformations
21355 switch (fixp
->fx_r_type
)
21357 case BFD_RELOC_ARM_PCREL_JUMP
:
21358 case BFD_RELOC_ARM_PCREL_CALL
:
21359 case BFD_RELOC_THUMB_PCREL_BLX
:
21360 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21364 case BFD_RELOC_ARM_PCREL_BLX
:
21365 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21366 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21367 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21368 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21377 /* Resolve these relocations even if the symbol is extern or weak. */
21378 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21379 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21380 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21387 /* Always leave these relocations for the linker. */
21388 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21389 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21390 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21393 /* Always generate relocations against function symbols. */
21394 if (fixp
->fx_r_type
== BFD_RELOC_32
21396 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21399 return generic_force_reloc (fixp
);
21402 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21403 /* Relocations against function names must be left unadjusted,
21404 so that the linker can use this information to generate interworking
21405 stubs. The MIPS version of this function
21406 also prevents relocations that are mips-16 specific, but I do not
21407 know why it does this.
21410 There is one other problem that ought to be addressed here, but
21411 which currently is not: Taking the address of a label (rather
21412 than a function) and then later jumping to that address. Such
21413 addresses also ought to have their bottom bit set (assuming that
21414 they reside in Thumb code), but at the moment they will not. */
21417 arm_fix_adjustable (fixS
* fixP
)
21419 if (fixP
->fx_addsy
== NULL
)
21422 /* Preserve relocations against symbols with function type. */
21423 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21426 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21427 && fixP
->fx_subsy
== NULL
)
21430 /* We need the symbol name for the VTABLE entries. */
21431 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21435 /* Don't allow symbols to be discarded on GOT related relocs. */
21436 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21437 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21438 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21447 /* Similarly for group relocations. */
21448 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21449 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21450 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21453 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21454 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21455 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21456 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21457 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21458 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21459 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21460 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21461 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21466 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21471 elf32_arm_target_format (void)
21474 return (target_big_endian
21475 ? "elf32-bigarm-symbian"
21476 : "elf32-littlearm-symbian");
21477 #elif defined (TE_VXWORKS)
21478 return (target_big_endian
21479 ? "elf32-bigarm-vxworks"
21480 : "elf32-littlearm-vxworks");
21482 if (target_big_endian
)
21483 return "elf32-bigarm";
21485 return "elf32-littlearm";
21490 armelf_frob_symbol (symbolS
* symp
,
21493 elf_frob_symbol (symp
, puntp
);
21497 /* MD interface: Finalization. */
21502 literal_pool
* pool
;
21504 /* Ensure that all the IT blocks are properly closed. */
21505 check_it_blocks_finished ();
21507 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21509 /* Put it at the end of the relevant section. */
21510 subseg_set (pool
->section
, pool
->sub_section
);
21512 arm_elf_change_section ();
21519 /* Remove any excess mapping symbols generated for alignment frags in
21520 SEC. We may have created a mapping symbol before a zero byte
21521 alignment; remove it if there's a mapping symbol after the
21524 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21525 void *dummy ATTRIBUTE_UNUSED
)
21527 segment_info_type
*seginfo
= seg_info (sec
);
21530 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21533 for (fragp
= seginfo
->frchainP
->frch_root
;
21535 fragp
= fragp
->fr_next
)
21537 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21538 fragS
*next
= fragp
->fr_next
;
21540 /* Variable-sized frags have been converted to fixed size by
21541 this point. But if this was variable-sized to start with,
21542 there will be a fixed-size frag after it. So don't handle
21544 if (sym
== NULL
|| next
== NULL
)
21547 if (S_GET_VALUE (sym
) < next
->fr_address
)
21548 /* Not at the end of this frag. */
21550 know (S_GET_VALUE (sym
) == next
->fr_address
);
21554 if (next
->tc_frag_data
.first_map
!= NULL
)
21556 /* Next frag starts with a mapping symbol. Discard this
21558 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21562 if (next
->fr_next
== NULL
)
21564 /* This mapping symbol is at the end of the section. Discard
21566 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21567 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21571 /* As long as we have empty frags without any mapping symbols,
21573 /* If the next frag is non-empty and does not start with a
21574 mapping symbol, then this mapping symbol is required. */
21575 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21578 next
= next
->fr_next
;
21580 while (next
!= NULL
);
21585 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21589 arm_adjust_symtab (void)
21594 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21596 if (ARM_IS_THUMB (sym
))
21598 if (THUMB_IS_FUNC (sym
))
21600 /* Mark the symbol as a Thumb function. */
21601 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21602 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21603 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21605 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21606 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21608 as_bad (_("%s: unexpected function type: %d"),
21609 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21611 else switch (S_GET_STORAGE_CLASS (sym
))
21614 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21617 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21620 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21628 if (ARM_IS_INTERWORK (sym
))
21629 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21636 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21638 if (ARM_IS_THUMB (sym
))
21640 elf_symbol_type
* elf_sym
;
21642 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21643 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21645 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21646 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21648 /* If it's a .thumb_func, declare it as so,
21649 otherwise tag label as .code 16. */
21650 if (THUMB_IS_FUNC (sym
))
21651 elf_sym
->internal_elf_sym
.st_info
=
21652 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21653 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21654 elf_sym
->internal_elf_sym
.st_info
=
21655 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21660 /* Remove any overlapping mapping symbols generated by alignment frags. */
21661 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21665 /* MD interface: Initialization. */
21668 set_constant_flonums (void)
21672 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21673 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21677 /* Auto-select Thumb mode if it's the only available instruction set for the
21678 given architecture. */
21681 autoselect_thumb_from_cpu_variant (void)
21683 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21684 opcode_select (16);
21693 if ( (arm_ops_hsh
= hash_new ()) == NULL
21694 || (arm_cond_hsh
= hash_new ()) == NULL
21695 || (arm_shift_hsh
= hash_new ()) == NULL
21696 || (arm_psr_hsh
= hash_new ()) == NULL
21697 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21698 || (arm_reg_hsh
= hash_new ()) == NULL
21699 || (arm_reloc_hsh
= hash_new ()) == NULL
21700 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21701 as_fatal (_("virtual memory exhausted"));
21703 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21704 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21705 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21706 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21707 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21708 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21709 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21710 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21711 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21712 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21713 (void *) (v7m_psrs
+ i
));
21714 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21715 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21717 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21719 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21720 (void *) (barrier_opt_names
+ i
));
21722 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21723 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21726 set_constant_flonums ();
21728 /* Set the cpu variant based on the command-line options. We prefer
21729 -mcpu= over -march= if both are set (as for GCC); and we prefer
21730 -mfpu= over any other way of setting the floating point unit.
21731 Use of legacy options with new options are faulted. */
21734 if (mcpu_cpu_opt
|| march_cpu_opt
)
21735 as_bad (_("use of old and new-style options to set CPU type"));
21737 mcpu_cpu_opt
= legacy_cpu
;
21739 else if (!mcpu_cpu_opt
)
21740 mcpu_cpu_opt
= march_cpu_opt
;
21745 as_bad (_("use of old and new-style options to set FPU type"));
21747 mfpu_opt
= legacy_fpu
;
21749 else if (!mfpu_opt
)
21751 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21752 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21753 /* Some environments specify a default FPU. If they don't, infer it
21754 from the processor. */
21756 mfpu_opt
= mcpu_fpu_opt
;
21758 mfpu_opt
= march_fpu_opt
;
21760 mfpu_opt
= &fpu_default
;
21766 if (mcpu_cpu_opt
!= NULL
)
21767 mfpu_opt
= &fpu_default
;
21768 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21769 mfpu_opt
= &fpu_arch_vfp_v2
;
21771 mfpu_opt
= &fpu_arch_fpa
;
21777 mcpu_cpu_opt
= &cpu_default
;
21778 selected_cpu
= cpu_default
;
21782 selected_cpu
= *mcpu_cpu_opt
;
21784 mcpu_cpu_opt
= &arm_arch_any
;
21787 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21789 autoselect_thumb_from_cpu_variant ();
21791 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21793 #if defined OBJ_COFF || defined OBJ_ELF
21795 unsigned int flags
= 0;
21797 #if defined OBJ_ELF
21798 flags
= meabi_flags
;
21800 switch (meabi_flags
)
21802 case EF_ARM_EABI_UNKNOWN
:
21804 /* Set the flags in the private structure. */
21805 if (uses_apcs_26
) flags
|= F_APCS26
;
21806 if (support_interwork
) flags
|= F_INTERWORK
;
21807 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21808 if (pic_code
) flags
|= F_PIC
;
21809 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21810 flags
|= F_SOFT_FLOAT
;
21812 switch (mfloat_abi_opt
)
21814 case ARM_FLOAT_ABI_SOFT
:
21815 case ARM_FLOAT_ABI_SOFTFP
:
21816 flags
|= F_SOFT_FLOAT
;
21819 case ARM_FLOAT_ABI_HARD
:
21820 if (flags
& F_SOFT_FLOAT
)
21821 as_bad (_("hard-float conflicts with specified fpu"));
21825 /* Using pure-endian doubles (even if soft-float). */
21826 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21827 flags
|= F_VFP_FLOAT
;
21829 #if defined OBJ_ELF
21830 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21831 flags
|= EF_ARM_MAVERICK_FLOAT
;
21834 case EF_ARM_EABI_VER4
:
21835 case EF_ARM_EABI_VER5
:
21836 /* No additional flags to set. */
21843 bfd_set_private_flags (stdoutput
, flags
);
21845 /* We have run out flags in the COFF header to encode the
21846 status of ATPCS support, so instead we create a dummy,
21847 empty, debug section called .arm.atpcs. */
21852 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21856 bfd_set_section_flags
21857 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21858 bfd_set_section_size (stdoutput
, sec
, 0);
21859 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21865 /* Record the CPU type as well. */
21866 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21867 mach
= bfd_mach_arm_iWMMXt2
;
21868 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21869 mach
= bfd_mach_arm_iWMMXt
;
21870 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21871 mach
= bfd_mach_arm_XScale
;
21872 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21873 mach
= bfd_mach_arm_ep9312
;
21874 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21875 mach
= bfd_mach_arm_5TE
;
21876 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21879 mach
= bfd_mach_arm_5T
;
21881 mach
= bfd_mach_arm_5
;
21883 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21885 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21886 mach
= bfd_mach_arm_4T
;
21888 mach
= bfd_mach_arm_4
;
21890 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21891 mach
= bfd_mach_arm_3M
;
21892 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21893 mach
= bfd_mach_arm_3
;
21894 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21895 mach
= bfd_mach_arm_2a
;
21896 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21897 mach
= bfd_mach_arm_2
;
21899 mach
= bfd_mach_arm_unknown
;
21901 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21904 /* Command line processing. */
21907 Invocation line includes a switch not recognized by the base assembler.
21908 See if it's a processor-specific option.
21910 This routine is somewhat complicated by the need for backwards
21911 compatibility (since older releases of gcc can't be changed).
21912 The new options try to make the interface as compatible as
21915 New options (supported) are:
21917 -mcpu=<cpu name> Assemble for selected processor
21918 -march=<architecture name> Assemble for selected architecture
21919 -mfpu=<fpu architecture> Assemble for selected FPU.
21920 -EB/-mbig-endian Big-endian
21921 -EL/-mlittle-endian Little-endian
21922 -k Generate PIC code
21923 -mthumb Start in Thumb mode
21924 -mthumb-interwork Code supports ARM/Thumb interworking
21926 -m[no-]warn-deprecated Warn about deprecated features
21928 For now we will also provide support for:
21930 -mapcs-32 32-bit Program counter
21931 -mapcs-26 26-bit Program counter
21932 -macps-float Floats passed in FP registers
21933 -mapcs-reentrant Reentrant code
21935 (sometime these will probably be replaced with -mapcs=<list of options>
21936 and -matpcs=<list of options>)
21938 The remaining options are only supported for back-wards compatibility.
21939 Cpu variants, the arm part is optional:
21940 -m[arm]1 Currently not supported.
21941 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21942 -m[arm]3 Arm 3 processor
21943 -m[arm]6[xx], Arm 6 processors
21944 -m[arm]7[xx][t][[d]m] Arm 7 processors
21945 -m[arm]8[10] Arm 8 processors
21946 -m[arm]9[20][tdmi] Arm 9 processors
21947 -mstrongarm[110[0]] StrongARM processors
21948 -mxscale XScale processors
21949 -m[arm]v[2345[t[e]]] Arm architectures
21950 -mall All (except the ARM1)
21952 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21953 -mfpe-old (No float load/store multiples)
21954 -mvfpxd VFP Single precision
21956 -mno-fpu Disable all floating point instructions
21958 The following CPU names are recognized:
21959 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21960 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21961 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21962 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21963 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21964 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21965 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21969 const char * md_shortopts
= "m:k";
21971 #ifdef ARM_BI_ENDIAN
21972 #define OPTION_EB (OPTION_MD_BASE + 0)
21973 #define OPTION_EL (OPTION_MD_BASE + 1)
21975 #if TARGET_BYTES_BIG_ENDIAN
21976 #define OPTION_EB (OPTION_MD_BASE + 0)
21978 #define OPTION_EL (OPTION_MD_BASE + 1)
21981 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21983 struct option md_longopts
[] =
21986 {"EB", no_argument
, NULL
, OPTION_EB
},
21989 {"EL", no_argument
, NULL
, OPTION_EL
},
21991 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21992 {NULL
, no_argument
, NULL
, 0}
21995 size_t md_longopts_size
= sizeof (md_longopts
);
21997 struct arm_option_table
21999 char *option
; /* Option name to match. */
22000 char *help
; /* Help information. */
22001 int *var
; /* Variable to change. */
22002 int value
; /* What to change it to. */
22003 char *deprecated
; /* If non-null, print this message. */
22006 struct arm_option_table arm_opts
[] =
22008 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22009 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22010 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22011 &support_interwork
, 1, NULL
},
22012 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22013 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22014 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22016 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22017 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22018 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22019 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22022 /* These are recognized by the assembler, but have no affect on code. */
22023 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22024 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22026 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22027 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22028 &warn_on_deprecated
, 0, NULL
},
22029 {NULL
, NULL
, NULL
, 0, NULL
}
22032 struct arm_legacy_option_table
22034 char *option
; /* Option name to match. */
22035 const arm_feature_set
**var
; /* Variable to change. */
22036 const arm_feature_set value
; /* What to change it to. */
22037 char *deprecated
; /* If non-null, print this message. */
22040 const struct arm_legacy_option_table arm_legacy_opts
[] =
22042 /* DON'T add any new processors to this list -- we want the whole list
22043 to go away... Add them to the processors table instead. */
22044 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22045 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22046 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22047 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22048 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22049 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22050 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22051 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22052 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22053 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22054 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22055 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22056 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22057 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22058 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22059 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22060 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22061 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22062 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22063 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22064 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22065 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22066 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22067 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22068 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22069 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22070 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22071 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22072 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22073 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22074 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22075 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22076 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22077 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22078 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22079 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22080 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22081 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22082 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22083 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22084 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22085 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22086 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22087 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22088 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22089 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22090 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22091 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22092 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22093 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22094 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22095 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22096 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22097 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22098 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22099 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22100 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22101 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22102 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22103 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22104 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22105 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22106 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22107 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22108 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22109 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22110 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22111 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22112 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22113 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22114 N_("use -mcpu=strongarm110")},
22115 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22116 N_("use -mcpu=strongarm1100")},
22117 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22118 N_("use -mcpu=strongarm1110")},
22119 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22120 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22121 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22123 /* Architecture variants -- don't add any more to this list either. */
22124 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22125 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22126 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22127 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22128 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22129 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22130 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22131 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22132 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22133 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22134 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22135 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22136 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22137 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22138 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22139 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22140 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22141 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22143 /* Floating point variants -- don't add any more to this list either. */
22144 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22145 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22146 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22147 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22148 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22150 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22153 struct arm_cpu_option_table
22156 const arm_feature_set value
;
22157 /* For some CPUs we assume an FPU unless the user explicitly sets
22159 const arm_feature_set default_fpu
;
22160 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22162 const char *canonical_name
;
22165 /* This list should, at a minimum, contain all the cpu names
22166 recognized by GCC. */
22167 static const struct arm_cpu_option_table arm_cpus
[] =
22169 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22170 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22171 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22172 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22173 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22174 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22175 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22176 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22177 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22178 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22179 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22180 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22181 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22182 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22183 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22184 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22185 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22186 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22187 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22188 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22189 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22190 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22191 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22192 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22193 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22194 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22195 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22196 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22197 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22198 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22199 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22200 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22201 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22202 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22203 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22204 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22205 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22206 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22207 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22208 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22209 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22210 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22211 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22212 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22213 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22214 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22215 /* For V5 or later processors we default to using VFP; but the user
22216 should really set the FPU type explicitly. */
22217 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22218 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22219 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22220 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22221 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22222 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22223 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22224 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22225 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22226 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22227 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22228 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22229 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22230 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22231 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22232 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22233 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22234 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22235 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22236 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22237 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22238 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22239 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22240 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22241 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22242 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22243 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22244 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22245 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22246 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22247 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22248 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22249 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22250 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22251 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22252 | FPU_NEON_EXT_V1
),
22254 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22255 | FPU_NEON_EXT_V1
),
22257 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22258 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22259 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22260 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22261 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22262 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22263 /* ??? XSCALE is really an architecture. */
22264 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22265 /* ??? iwmmxt is not a processor. */
22266 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22267 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22268 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22270 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22271 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22274 struct arm_arch_option_table
22277 const arm_feature_set value
;
22278 const arm_feature_set default_fpu
;
22281 /* This list should, at a minimum, contain all the architecture names
22282 recognized by GCC. */
22283 static const struct arm_arch_option_table arm_archs
[] =
22285 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22286 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22287 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22288 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22289 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22290 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22291 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22292 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22293 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22294 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22295 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22296 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22297 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22298 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22299 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22300 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22301 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22302 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22303 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22304 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22305 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22306 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22307 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22308 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22309 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22310 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22311 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22312 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22313 /* The official spelling of the ARMv7 profile variants is the dashed form.
22314 Accept the non-dashed form for compatibility with old toolchains. */
22315 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22316 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22317 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22318 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22319 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22320 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22321 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22322 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22323 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22324 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22325 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22328 /* ISA extensions in the co-processor space. */
22329 struct arm_option_cpu_value_table
22332 const arm_feature_set value
;
22335 static const struct arm_option_cpu_value_table arm_extensions
[] =
22337 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22338 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22339 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22340 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22341 {NULL
, ARM_ARCH_NONE
}
22344 /* This list should, at a minimum, contain all the fpu names
22345 recognized by GCC. */
22346 static const struct arm_option_cpu_value_table arm_fpus
[] =
22348 {"softfpa", FPU_NONE
},
22349 {"fpe", FPU_ARCH_FPE
},
22350 {"fpe2", FPU_ARCH_FPE
},
22351 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22352 {"fpa", FPU_ARCH_FPA
},
22353 {"fpa10", FPU_ARCH_FPA
},
22354 {"fpa11", FPU_ARCH_FPA
},
22355 {"arm7500fe", FPU_ARCH_FPA
},
22356 {"softvfp", FPU_ARCH_VFP
},
22357 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22358 {"vfp", FPU_ARCH_VFP_V2
},
22359 {"vfp9", FPU_ARCH_VFP_V2
},
22360 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22361 {"vfp10", FPU_ARCH_VFP_V2
},
22362 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22363 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22364 {"vfpv2", FPU_ARCH_VFP_V2
},
22365 {"vfpv3", FPU_ARCH_VFP_V3
},
22366 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22367 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22368 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22369 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22370 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22371 {"arm1020t", FPU_ARCH_VFP_V1
},
22372 {"arm1020e", FPU_ARCH_VFP_V2
},
22373 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22374 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22375 {"maverick", FPU_ARCH_MAVERICK
},
22376 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22377 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22378 {"vfpv4", FPU_ARCH_VFP_V4
},
22379 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22380 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22381 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22382 {NULL
, ARM_ARCH_NONE
}
22385 struct arm_option_value_table
22391 static const struct arm_option_value_table arm_float_abis
[] =
22393 {"hard", ARM_FLOAT_ABI_HARD
},
22394 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22395 {"soft", ARM_FLOAT_ABI_SOFT
},
22400 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22401 static const struct arm_option_value_table arm_eabis
[] =
22403 {"gnu", EF_ARM_EABI_UNKNOWN
},
22404 {"4", EF_ARM_EABI_VER4
},
22405 {"5", EF_ARM_EABI_VER5
},
22410 struct arm_long_option_table
22412 char * option
; /* Substring to match. */
22413 char * help
; /* Help information. */
22414 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22415 char * deprecated
; /* If non-null, print this message. */
22419 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22421 arm_feature_set
*ext_set
= (arm_feature_set
*)
22422 xmalloc (sizeof (arm_feature_set
));
22424 /* Copy the feature set, so that we can modify it. */
22425 *ext_set
= **opt_p
;
22428 while (str
!= NULL
&& *str
!= 0)
22430 const struct arm_option_cpu_value_table
* opt
;
22436 as_bad (_("invalid architectural extension"));
22441 ext
= strchr (str
, '+');
22444 optlen
= ext
- str
;
22446 optlen
= strlen (str
);
22450 as_bad (_("missing architectural extension"));
22454 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22455 if (strncmp (opt
->name
, str
, optlen
) == 0)
22457 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22461 if (opt
->name
== NULL
)
22463 as_bad (_("unknown architectural extension `%s'"), str
);
22474 arm_parse_cpu (char * str
)
22476 const struct arm_cpu_option_table
* opt
;
22477 char * ext
= strchr (str
, '+');
22481 optlen
= ext
- str
;
22483 optlen
= strlen (str
);
22487 as_bad (_("missing cpu name `%s'"), str
);
22491 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22492 if (strncmp (opt
->name
, str
, optlen
) == 0)
22494 mcpu_cpu_opt
= &opt
->value
;
22495 mcpu_fpu_opt
= &opt
->default_fpu
;
22496 if (opt
->canonical_name
)
22497 strcpy (selected_cpu_name
, opt
->canonical_name
);
22502 for (i
= 0; i
< optlen
; i
++)
22503 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22504 selected_cpu_name
[i
] = 0;
22508 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22513 as_bad (_("unknown cpu `%s'"), str
);
22518 arm_parse_arch (char * str
)
22520 const struct arm_arch_option_table
*opt
;
22521 char *ext
= strchr (str
, '+');
22525 optlen
= ext
- str
;
22527 optlen
= strlen (str
);
22531 as_bad (_("missing architecture name `%s'"), str
);
22535 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22536 if (streq (opt
->name
, str
))
22538 march_cpu_opt
= &opt
->value
;
22539 march_fpu_opt
= &opt
->default_fpu
;
22540 strcpy (selected_cpu_name
, opt
->name
);
22543 return arm_parse_extension (ext
, &march_cpu_opt
);
22548 as_bad (_("unknown architecture `%s'\n"), str
);
22553 arm_parse_fpu (char * str
)
22555 const struct arm_option_cpu_value_table
* opt
;
22557 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22558 if (streq (opt
->name
, str
))
22560 mfpu_opt
= &opt
->value
;
22564 as_bad (_("unknown floating point format `%s'\n"), str
);
22569 arm_parse_float_abi (char * str
)
22571 const struct arm_option_value_table
* opt
;
22573 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22574 if (streq (opt
->name
, str
))
22576 mfloat_abi_opt
= opt
->value
;
22580 as_bad (_("unknown floating point abi `%s'\n"), str
);
22586 arm_parse_eabi (char * str
)
22588 const struct arm_option_value_table
*opt
;
22590 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22591 if (streq (opt
->name
, str
))
22593 meabi_flags
= opt
->value
;
22596 as_bad (_("unknown EABI `%s'\n"), str
);
22602 arm_parse_it_mode (char * str
)
22604 bfd_boolean ret
= TRUE
;
22606 if (streq ("arm", str
))
22607 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22608 else if (streq ("thumb", str
))
22609 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22610 else if (streq ("always", str
))
22611 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22612 else if (streq ("never", str
))
22613 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22616 as_bad (_("unknown implicit IT mode `%s', should be "\
22617 "arm, thumb, always, or never."), str
);
22624 struct arm_long_option_table arm_long_opts
[] =
22626 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22627 arm_parse_cpu
, NULL
},
22628 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22629 arm_parse_arch
, NULL
},
22630 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22631 arm_parse_fpu
, NULL
},
22632 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22633 arm_parse_float_abi
, NULL
},
22635 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22636 arm_parse_eabi
, NULL
},
22638 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22639 arm_parse_it_mode
, NULL
},
22640 {NULL
, NULL
, 0, NULL
}
22644 md_parse_option (int c
, char * arg
)
22646 struct arm_option_table
*opt
;
22647 const struct arm_legacy_option_table
*fopt
;
22648 struct arm_long_option_table
*lopt
;
22654 target_big_endian
= 1;
22660 target_big_endian
= 0;
22664 case OPTION_FIX_V4BX
:
22669 /* Listing option. Just ignore these, we don't support additional
22674 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22676 if (c
== opt
->option
[0]
22677 && ((arg
== NULL
&& opt
->option
[1] == 0)
22678 || streq (arg
, opt
->option
+ 1)))
22680 /* If the option is deprecated, tell the user. */
22681 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22682 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22683 arg
? arg
: "", _(opt
->deprecated
));
22685 if (opt
->var
!= NULL
)
22686 *opt
->var
= opt
->value
;
22692 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22694 if (c
== fopt
->option
[0]
22695 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22696 || streq (arg
, fopt
->option
+ 1)))
22698 /* If the option is deprecated, tell the user. */
22699 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22700 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22701 arg
? arg
: "", _(fopt
->deprecated
));
22703 if (fopt
->var
!= NULL
)
22704 *fopt
->var
= &fopt
->value
;
22710 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22712 /* These options are expected to have an argument. */
22713 if (c
== lopt
->option
[0]
22715 && strncmp (arg
, lopt
->option
+ 1,
22716 strlen (lopt
->option
+ 1)) == 0)
22718 /* If the option is deprecated, tell the user. */
22719 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22720 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22721 _(lopt
->deprecated
));
22723 /* Call the sup-option parser. */
22724 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22735 md_show_usage (FILE * fp
)
22737 struct arm_option_table
*opt
;
22738 struct arm_long_option_table
*lopt
;
22740 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22742 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22743 if (opt
->help
!= NULL
)
22744 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22746 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22747 if (lopt
->help
!= NULL
)
22748 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22752 -EB assemble code for a big-endian cpu\n"));
22757 -EL assemble code for a little-endian cpu\n"));
22761 --fix-v4bx Allow BX in ARMv4 code\n"));
22769 arm_feature_set flags
;
22770 } cpu_arch_ver_table
;
22772 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22773 least features first. */
22774 static const cpu_arch_ver_table cpu_arch_ver
[] =
22780 {4, ARM_ARCH_V5TE
},
22781 {5, ARM_ARCH_V5TEJ
},
22785 {11, ARM_ARCH_V6M
},
22786 {8, ARM_ARCH_V6T2
},
22787 {10, ARM_ARCH_V7A
},
22788 {10, ARM_ARCH_V7R
},
22789 {10, ARM_ARCH_V7M
},
22793 /* Set an attribute if it has not already been set by the user. */
22795 aeabi_set_attribute_int (int tag
, int value
)
22798 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22799 || !attributes_set_explicitly
[tag
])
22800 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22804 aeabi_set_attribute_string (int tag
, const char *value
)
22807 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22808 || !attributes_set_explicitly
[tag
])
22809 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22812 /* Set the public EABI object attributes. */
22814 aeabi_set_public_attributes (void)
22817 arm_feature_set flags
;
22818 arm_feature_set tmp
;
22819 const cpu_arch_ver_table
*p
;
22821 /* Choose the architecture based on the capabilities of the requested cpu
22822 (if any) and/or the instructions actually used. */
22823 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22824 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22825 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22826 /*Allow the user to override the reported architecture. */
22829 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22830 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22835 for (p
= cpu_arch_ver
; p
->val
; p
++)
22837 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22840 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22844 /* The table lookup above finds the last architecture to contribute
22845 a new feature. Unfortunately, Tag13 is a subset of the union of
22846 v6T2 and v7-M, so it is never seen as contributing a new feature.
22847 We can not search for the last entry which is entirely used,
22848 because if no CPU is specified we build up only those flags
22849 actually used. Perhaps we should separate out the specified
22850 and implicit cases. Avoid taking this path for -march=all by
22851 checking for contradictory v7-A / v7-M features. */
22853 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22854 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22855 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22858 /* Tag_CPU_name. */
22859 if (selected_cpu_name
[0])
22863 q
= selected_cpu_name
;
22864 if (strncmp (q
, "armv", 4) == 0)
22869 for (i
= 0; q
[i
]; i
++)
22870 q
[i
] = TOUPPER (q
[i
]);
22872 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22875 /* Tag_CPU_arch. */
22876 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22878 /* Tag_CPU_arch_profile. */
22879 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22880 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22881 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22882 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22883 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22884 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22886 /* Tag_ARM_ISA_use. */
22887 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22889 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22891 /* Tag_THUMB_ISA_use. */
22892 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22894 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22895 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22897 /* Tag_VFP_arch. */
22898 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22899 aeabi_set_attribute_int (Tag_VFP_arch
,
22900 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22902 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22903 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22904 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22905 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22906 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22907 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22908 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22909 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22910 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22912 /* Tag_ABI_HardFP_use. */
22913 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22914 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22915 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22917 /* Tag_WMMX_arch. */
22918 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22919 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22920 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22921 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22923 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22924 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22925 aeabi_set_attribute_int
22926 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22929 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22930 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22931 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22934 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
22935 aeabi_set_attribute_int (Tag_DIV_use
, 0);
22936 /* Fill this in when gas supports v7a sdiv/udiv.
22937 else if (... v7a with div extension used ...)
22938 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22940 aeabi_set_attribute_int (Tag_DIV_use
, 1);
22943 /* Add the default contents for the .ARM.attributes section. */
22947 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22950 aeabi_set_public_attributes ();
22952 #endif /* OBJ_ELF */
22955 /* Parse a .cpu directive. */
22958 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22960 const struct arm_cpu_option_table
*opt
;
22964 name
= input_line_pointer
;
22965 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22966 input_line_pointer
++;
22967 saved_char
= *input_line_pointer
;
22968 *input_line_pointer
= 0;
22970 /* Skip the first "all" entry. */
22971 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22972 if (streq (opt
->name
, name
))
22974 mcpu_cpu_opt
= &opt
->value
;
22975 selected_cpu
= opt
->value
;
22976 if (opt
->canonical_name
)
22977 strcpy (selected_cpu_name
, opt
->canonical_name
);
22981 for (i
= 0; opt
->name
[i
]; i
++)
22982 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22983 selected_cpu_name
[i
] = 0;
22985 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22986 *input_line_pointer
= saved_char
;
22987 demand_empty_rest_of_line ();
22990 as_bad (_("unknown cpu `%s'"), name
);
22991 *input_line_pointer
= saved_char
;
22992 ignore_rest_of_line ();
22996 /* Parse a .arch directive. */
22999 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23001 const struct arm_arch_option_table
*opt
;
23005 name
= input_line_pointer
;
23006 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23007 input_line_pointer
++;
23008 saved_char
= *input_line_pointer
;
23009 *input_line_pointer
= 0;
23011 /* Skip the first "all" entry. */
23012 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23013 if (streq (opt
->name
, name
))
23015 mcpu_cpu_opt
= &opt
->value
;
23016 selected_cpu
= opt
->value
;
23017 strcpy (selected_cpu_name
, opt
->name
);
23018 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23019 *input_line_pointer
= saved_char
;
23020 demand_empty_rest_of_line ();
23024 as_bad (_("unknown architecture `%s'\n"), name
);
23025 *input_line_pointer
= saved_char
;
23026 ignore_rest_of_line ();
23030 /* Parse a .object_arch directive. */
23033 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23035 const struct arm_arch_option_table
*opt
;
23039 name
= input_line_pointer
;
23040 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23041 input_line_pointer
++;
23042 saved_char
= *input_line_pointer
;
23043 *input_line_pointer
= 0;
23045 /* Skip the first "all" entry. */
23046 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23047 if (streq (opt
->name
, name
))
23049 object_arch
= &opt
->value
;
23050 *input_line_pointer
= saved_char
;
23051 demand_empty_rest_of_line ();
23055 as_bad (_("unknown architecture `%s'\n"), name
);
23056 *input_line_pointer
= saved_char
;
23057 ignore_rest_of_line ();
23060 /* Parse a .fpu directive. */
23063 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23065 const struct arm_option_cpu_value_table
*opt
;
23069 name
= input_line_pointer
;
23070 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23071 input_line_pointer
++;
23072 saved_char
= *input_line_pointer
;
23073 *input_line_pointer
= 0;
23075 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23076 if (streq (opt
->name
, name
))
23078 mfpu_opt
= &opt
->value
;
23079 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23080 *input_line_pointer
= saved_char
;
23081 demand_empty_rest_of_line ();
23085 as_bad (_("unknown floating point format `%s'\n"), name
);
23086 *input_line_pointer
= saved_char
;
23087 ignore_rest_of_line ();
23090 /* Copy symbol information. */
23093 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23095 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23099 /* Given a symbolic attribute NAME, return the proper integer value.
23100 Returns -1 if the attribute is not known. */
23103 arm_convert_symbolic_attribute (const char *name
)
23105 static const struct
23110 attribute_table
[] =
23112 /* When you modify this table you should
23113 also modify the list in doc/c-arm.texi. */
23114 #define T(tag) {#tag, tag}
23115 T (Tag_CPU_raw_name
),
23118 T (Tag_CPU_arch_profile
),
23119 T (Tag_ARM_ISA_use
),
23120 T (Tag_THUMB_ISA_use
),
23124 T (Tag_Advanced_SIMD_arch
),
23125 T (Tag_PCS_config
),
23126 T (Tag_ABI_PCS_R9_use
),
23127 T (Tag_ABI_PCS_RW_data
),
23128 T (Tag_ABI_PCS_RO_data
),
23129 T (Tag_ABI_PCS_GOT_use
),
23130 T (Tag_ABI_PCS_wchar_t
),
23131 T (Tag_ABI_FP_rounding
),
23132 T (Tag_ABI_FP_denormal
),
23133 T (Tag_ABI_FP_exceptions
),
23134 T (Tag_ABI_FP_user_exceptions
),
23135 T (Tag_ABI_FP_number_model
),
23136 T (Tag_ABI_align_needed
),
23137 T (Tag_ABI_align8_needed
),
23138 T (Tag_ABI_align_preserved
),
23139 T (Tag_ABI_align8_preserved
),
23140 T (Tag_ABI_enum_size
),
23141 T (Tag_ABI_HardFP_use
),
23142 T (Tag_ABI_VFP_args
),
23143 T (Tag_ABI_WMMX_args
),
23144 T (Tag_ABI_optimization_goals
),
23145 T (Tag_ABI_FP_optimization_goals
),
23146 T (Tag_compatibility
),
23147 T (Tag_CPU_unaligned_access
),
23148 T (Tag_FP_HP_extension
),
23149 T (Tag_VFP_HP_extension
),
23150 T (Tag_ABI_FP_16bit_format
),
23151 T (Tag_MPextension_use
),
23153 T (Tag_nodefaults
),
23154 T (Tag_also_compatible_with
),
23155 T (Tag_conformance
),
23157 T (Tag_Virtualization_use
),
23158 /* We deliberately do not include Tag_MPextension_use_legacy. */
23166 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23167 if (streq (name
, attribute_table
[i
].name
))
23168 return attribute_table
[i
].tag
;
23174 /* Apply sym value for relocations only in the case that
23175 they are for local symbols and you have the respective
23176 architectural feature for blx and simple switches. */
23178 arm_apply_sym_value (struct fix
* fixP
)
23181 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23182 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23184 switch (fixP
->fx_r_type
)
23186 case BFD_RELOC_ARM_PCREL_BLX
:
23187 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23188 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23192 case BFD_RELOC_ARM_PCREL_CALL
:
23193 case BFD_RELOC_THUMB_PCREL_BLX
:
23194 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23205 #endif /* OBJ_ELF */