1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
205 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
206 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
207 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
208 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
209 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
210 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
211 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
213 static const arm_feature_set arm_ext_v8m_main
=
214 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
215 /* Instructions in ARMv8-M only found in M profile architectures. */
216 static const arm_feature_set arm_ext_v8m_m_only
=
217 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
218 static const arm_feature_set arm_ext_v6t2_v8m
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
220 /* Instructions shared between ARMv8-A and ARMv8-M. */
221 static const arm_feature_set arm_ext_atomics
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
223 /* DSP instructions Tag_DSP_extension refers to. */
224 static const arm_feature_set arm_ext_dsp
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
226 static const arm_feature_set arm_ext_v8_2
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
228 /* FP16 instructions. */
229 static const arm_feature_set arm_ext_fp16
=
230 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
232 static const arm_feature_set arm_arch_any
= ARM_ANY
;
233 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
234 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
235 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
236 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
238 static const arm_feature_set arm_cext_iwmmxt2
=
239 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
240 static const arm_feature_set arm_cext_iwmmxt
=
241 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
242 static const arm_feature_set arm_cext_xscale
=
243 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
244 static const arm_feature_set arm_cext_maverick
=
245 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
246 static const arm_feature_set fpu_fpa_ext_v1
=
247 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
248 static const arm_feature_set fpu_fpa_ext_v2
=
249 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
250 static const arm_feature_set fpu_vfp_ext_v1xd
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
252 static const arm_feature_set fpu_vfp_ext_v1
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
254 static const arm_feature_set fpu_vfp_ext_v2
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
256 static const arm_feature_set fpu_vfp_ext_v3xd
=
257 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
258 static const arm_feature_set fpu_vfp_ext_v3
=
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
260 static const arm_feature_set fpu_vfp_ext_d32
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
262 static const arm_feature_set fpu_neon_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
264 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
265 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
266 static const arm_feature_set fpu_vfp_fp16
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
268 static const arm_feature_set fpu_neon_ext_fma
=
269 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
270 static const arm_feature_set fpu_vfp_ext_fma
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
272 static const arm_feature_set fpu_vfp_ext_armv8
=
273 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
274 static const arm_feature_set fpu_vfp_ext_armv8xd
=
275 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
276 static const arm_feature_set fpu_neon_ext_armv8
=
277 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
278 static const arm_feature_set fpu_crypto_ext_armv8
=
279 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
280 static const arm_feature_set crc_ext_armv8
=
281 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
282 static const arm_feature_set fpu_neon_ext_v8_1
=
283 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
285 static int mfloat_abi_opt
= -1;
286 /* Record user cpu selection for object attributes. */
287 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
288 /* Must be long enough to hold any of the names in arm_cpus. */
289 static char selected_cpu_name
[20];
291 extern FLONUM_TYPE generic_floating_point_number
;
293 /* Return if no cpu was selected on command-line. */
295 no_cpu_selected (void)
297 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
302 static int meabi_flags
= EABI_DEFAULT
;
304 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
307 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
312 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
317 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
318 symbolS
* GOT_symbol
;
321 /* 0: assemble for ARM,
322 1: assemble for Thumb,
323 2: assemble for Thumb even though target CPU does not support thumb
325 static int thumb_mode
= 0;
326 /* A value distinct from the possible values for thumb_mode that we
327 can use to record whether thumb_mode has been copied into the
328 tc_frag_data field of a frag. */
329 #define MODE_RECORDED (1 << 4)
331 /* Specifies the intrinsic IT insn behavior mode. */
332 enum implicit_it_mode
334 IMPLICIT_IT_MODE_NEVER
= 0x00,
335 IMPLICIT_IT_MODE_ARM
= 0x01,
336 IMPLICIT_IT_MODE_THUMB
= 0x02,
337 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
339 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
341 /* If unified_syntax is true, we are processing the new unified
342 ARM/Thumb syntax. Important differences from the old ARM mode:
344 - Immediate operands do not require a # prefix.
345 - Conditional affixes always appear at the end of the
346 instruction. (For backward compatibility, those instructions
347 that formerly had them in the middle, continue to accept them
349 - The IT instruction may appear, and if it does is validated
350 against subsequent conditional affixes. It does not generate
353 Important differences from the old Thumb mode:
355 - Immediate operands do not require a # prefix.
356 - Most of the V6T2 instructions are only available in unified mode.
357 - The .N and .W suffixes are recognized and honored (it is an error
358 if they cannot be honored).
359 - All instructions set the flags if and only if they have an 's' affix.
360 - Conditional affixes may be used. They are validated against
361 preceding IT instructions. Unlike ARM mode, you cannot use a
362 conditional affix except in the scope of an IT instruction. */
364 static bfd_boolean unified_syntax
= FALSE
;
366 /* An immediate operand can start with #, and ld*, st*, pld operands
367 can contain [ and ]. We need to tell APP not to elide whitespace
368 before a [, which can appear as the first operand for pld.
369 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
370 const char arm_symbol_chars
[] = "#[]{}";
385 enum neon_el_type type
;
389 #define NEON_MAX_TYPE_ELS 4
393 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
397 enum it_instruction_type
402 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
403 if inside, should be the last one. */
404 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
405 i.e. BKPT and NOP. */
406 IT_INSN
/* The IT insn has been parsed. */
409 /* The maximum number of operands we need. */
410 #define ARM_IT_MAX_OPERANDS 6
415 unsigned long instruction
;
419 /* "uncond_value" is set to the value in place of the conditional field in
420 unconditional versions of the instruction, or -1 if nothing is
423 struct neon_type vectype
;
424 /* This does not indicate an actual NEON instruction, only that
425 the mnemonic accepts neon-style type suffixes. */
427 /* Set to the opcode if the instruction needs relaxation.
428 Zero if the instruction is not relaxed. */
432 bfd_reloc_code_real_type type
;
437 enum it_instruction_type it_insn_type
;
443 struct neon_type_el vectype
;
444 unsigned present
: 1; /* Operand present. */
445 unsigned isreg
: 1; /* Operand was a register. */
446 unsigned immisreg
: 1; /* .imm field is a second register. */
447 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
448 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
449 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
450 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
451 instructions. This allows us to disambiguate ARM <-> vector insns. */
452 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
453 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
454 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
455 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
456 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
457 unsigned writeback
: 1; /* Operand has trailing ! */
458 unsigned preind
: 1; /* Preindexed address. */
459 unsigned postind
: 1; /* Postindexed address. */
460 unsigned negative
: 1; /* Index register was negated. */
461 unsigned shifted
: 1; /* Shift applied to operation. */
462 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
463 } operands
[ARM_IT_MAX_OPERANDS
];
466 static struct arm_it inst
;
468 #define NUM_FLOAT_VALS 8
470 const char * fp_const
[] =
472 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
475 /* Number of littlenums required to hold an extended precision number. */
476 #define MAX_LITTLENUMS 6
478 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
488 #define CP_T_X 0x00008000
489 #define CP_T_Y 0x00400000
491 #define CONDS_BIT 0x00100000
492 #define LOAD_BIT 0x00100000
494 #define DOUBLE_LOAD_FLAG 0x00000001
498 const char * template_name
;
502 #define COND_ALWAYS 0xE
506 const char * template_name
;
510 struct asm_barrier_opt
512 const char * template_name
;
514 const arm_feature_set arch
;
517 /* The bit that distinguishes CPSR and SPSR. */
518 #define SPSR_BIT (1 << 22)
520 /* The individual PSR flag bits. */
521 #define PSR_c (1 << 16)
522 #define PSR_x (1 << 17)
523 #define PSR_s (1 << 18)
524 #define PSR_f (1 << 19)
529 bfd_reloc_code_real_type reloc
;
534 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
535 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
540 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
543 /* Bits for DEFINED field in neon_typed_alias. */
544 #define NTA_HASTYPE 1
545 #define NTA_HASINDEX 2
547 struct neon_typed_alias
549 unsigned char defined
;
551 struct neon_type_el eltype
;
554 /* ARM register categories. This includes coprocessor numbers and various
555 architecture extensions' registers. */
582 /* Structure for a hash table entry for a register.
583 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
584 information which states whether a vector type or index is specified (for a
585 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
591 unsigned char builtin
;
592 struct neon_typed_alias
* neon
;
595 /* Diagnostics used when we don't get a register of the expected type. */
596 const char * const reg_expected_msgs
[] =
598 N_("ARM register expected"),
599 N_("bad or missing co-processor number"),
600 N_("co-processor register expected"),
601 N_("FPA register expected"),
602 N_("VFP single precision register expected"),
603 N_("VFP/Neon double precision register expected"),
604 N_("Neon quad precision register expected"),
605 N_("VFP single or double precision register expected"),
606 N_("Neon double or quad precision register expected"),
607 N_("VFP single, double or Neon quad precision register expected"),
608 N_("VFP system register expected"),
609 N_("Maverick MVF register expected"),
610 N_("Maverick MVD register expected"),
611 N_("Maverick MVFX register expected"),
612 N_("Maverick MVDX register expected"),
613 N_("Maverick MVAX register expected"),
614 N_("Maverick DSPSC register expected"),
615 N_("iWMMXt data register expected"),
616 N_("iWMMXt control register expected"),
617 N_("iWMMXt scalar register expected"),
618 N_("XScale accumulator register expected"),
621 /* Some well known registers that we refer to directly elsewhere. */
627 /* ARM instructions take 4bytes in the object file, Thumb instructions
633 /* Basic string to match. */
634 const char * template_name
;
636 /* Parameters to instruction. */
637 unsigned int operands
[8];
639 /* Conditional tag - see opcode_lookup. */
640 unsigned int tag
: 4;
642 /* Basic instruction code. */
643 unsigned int avalue
: 28;
645 /* Thumb-format instruction code. */
648 /* Which architecture variant provides this instruction. */
649 const arm_feature_set
* avariant
;
650 const arm_feature_set
* tvariant
;
652 /* Function to call to encode instruction in ARM format. */
653 void (* aencode
) (void);
655 /* Function to call to encode instruction in Thumb format. */
656 void (* tencode
) (void);
659 /* Defines for various bits that we will want to toggle. */
660 #define INST_IMMEDIATE 0x02000000
661 #define OFFSET_REG 0x02000000
662 #define HWOFFSET_IMM 0x00400000
663 #define SHIFT_BY_REG 0x00000010
664 #define PRE_INDEX 0x01000000
665 #define INDEX_UP 0x00800000
666 #define WRITE_BACK 0x00200000
667 #define LDM_TYPE_2_OR_3 0x00400000
668 #define CPSI_MMOD 0x00020000
670 #define LITERAL_MASK 0xf000f000
671 #define OPCODE_MASK 0xfe1fffff
672 #define V4_STR_BIT 0x00000020
673 #define VLDR_VMOV_SAME 0x0040f000
675 #define T2_SUBS_PC_LR 0xf3de8f00
677 #define DATA_OP_SHIFT 21
679 #define T2_OPCODE_MASK 0xfe1fffff
680 #define T2_DATA_OP_SHIFT 21
682 #define A_COND_MASK 0xf0000000
683 #define A_PUSH_POP_OP_MASK 0x0fff0000
685 /* Opcodes for pushing/poping registers to/from the stack. */
686 #define A1_OPCODE_PUSH 0x092d0000
687 #define A2_OPCODE_PUSH 0x052d0004
688 #define A2_OPCODE_POP 0x049d0004
690 /* Codes to distinguish the arithmetic instructions. */
701 #define OPCODE_CMP 10
702 #define OPCODE_CMN 11
703 #define OPCODE_ORR 12
704 #define OPCODE_MOV 13
705 #define OPCODE_BIC 14
706 #define OPCODE_MVN 15
708 #define T2_OPCODE_AND 0
709 #define T2_OPCODE_BIC 1
710 #define T2_OPCODE_ORR 2
711 #define T2_OPCODE_ORN 3
712 #define T2_OPCODE_EOR 4
713 #define T2_OPCODE_ADD 8
714 #define T2_OPCODE_ADC 10
715 #define T2_OPCODE_SBC 11
716 #define T2_OPCODE_SUB 13
717 #define T2_OPCODE_RSB 14
719 #define T_OPCODE_MUL 0x4340
720 #define T_OPCODE_TST 0x4200
721 #define T_OPCODE_CMN 0x42c0
722 #define T_OPCODE_NEG 0x4240
723 #define T_OPCODE_MVN 0x43c0
725 #define T_OPCODE_ADD_R3 0x1800
726 #define T_OPCODE_SUB_R3 0x1a00
727 #define T_OPCODE_ADD_HI 0x4400
728 #define T_OPCODE_ADD_ST 0xb000
729 #define T_OPCODE_SUB_ST 0xb080
730 #define T_OPCODE_ADD_SP 0xa800
731 #define T_OPCODE_ADD_PC 0xa000
732 #define T_OPCODE_ADD_I8 0x3000
733 #define T_OPCODE_SUB_I8 0x3800
734 #define T_OPCODE_ADD_I3 0x1c00
735 #define T_OPCODE_SUB_I3 0x1e00
737 #define T_OPCODE_ASR_R 0x4100
738 #define T_OPCODE_LSL_R 0x4080
739 #define T_OPCODE_LSR_R 0x40c0
740 #define T_OPCODE_ROR_R 0x41c0
741 #define T_OPCODE_ASR_I 0x1000
742 #define T_OPCODE_LSL_I 0x0000
743 #define T_OPCODE_LSR_I 0x0800
745 #define T_OPCODE_MOV_I8 0x2000
746 #define T_OPCODE_CMP_I8 0x2800
747 #define T_OPCODE_CMP_LR 0x4280
748 #define T_OPCODE_MOV_HR 0x4600
749 #define T_OPCODE_CMP_HR 0x4500
751 #define T_OPCODE_LDR_PC 0x4800
752 #define T_OPCODE_LDR_SP 0x9800
753 #define T_OPCODE_STR_SP 0x9000
754 #define T_OPCODE_LDR_IW 0x6800
755 #define T_OPCODE_STR_IW 0x6000
756 #define T_OPCODE_LDR_IH 0x8800
757 #define T_OPCODE_STR_IH 0x8000
758 #define T_OPCODE_LDR_IB 0x7800
759 #define T_OPCODE_STR_IB 0x7000
760 #define T_OPCODE_LDR_RW 0x5800
761 #define T_OPCODE_STR_RW 0x5000
762 #define T_OPCODE_LDR_RH 0x5a00
763 #define T_OPCODE_STR_RH 0x5200
764 #define T_OPCODE_LDR_RB 0x5c00
765 #define T_OPCODE_STR_RB 0x5400
767 #define T_OPCODE_PUSH 0xb400
768 #define T_OPCODE_POP 0xbc00
770 #define T_OPCODE_BRANCH 0xe000
772 #define THUMB_SIZE 2 /* Size of thumb instruction. */
773 #define THUMB_PP_PC_LR 0x0100
774 #define THUMB_LOAD_BIT 0x0800
775 #define THUMB2_LOAD_BIT 0x00100000
777 #define BAD_ARGS _("bad arguments to instruction")
778 #define BAD_SP _("r13 not allowed here")
779 #define BAD_PC _("r15 not allowed here")
780 #define BAD_COND _("instruction cannot be conditional")
781 #define BAD_OVERLAP _("registers may not be the same")
782 #define BAD_HIREG _("lo register required")
783 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
784 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
785 #define BAD_BRANCH _("branch must be last instruction in IT block")
786 #define BAD_NOT_IT _("instruction not allowed in IT block")
787 #define BAD_FPU _("selected FPU does not support instruction")
788 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
789 #define BAD_IT_COND _("incorrect condition in IT block")
790 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
791 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
792 #define BAD_PC_ADDRESSING \
793 _("cannot use register index with PC-relative addressing")
794 #define BAD_PC_WRITEBACK \
795 _("cannot use writeback with PC-relative addressing")
796 #define BAD_RANGE _("branch out of range")
797 #define BAD_FP16 _("selected processor does not support fp16 instruction")
798 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
799 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
801 static struct hash_control
* arm_ops_hsh
;
802 static struct hash_control
* arm_cond_hsh
;
803 static struct hash_control
* arm_shift_hsh
;
804 static struct hash_control
* arm_psr_hsh
;
805 static struct hash_control
* arm_v7m_psr_hsh
;
806 static struct hash_control
* arm_reg_hsh
;
807 static struct hash_control
* arm_reloc_hsh
;
808 static struct hash_control
* arm_barrier_opt_hsh
;
810 /* Stuff needed to resolve the label ambiguity
819 symbolS
* last_label_seen
;
820 static int label_is_thumb_function_name
= FALSE
;
822 /* Literal pool structure. Held on a per-section
823 and per-sub-section basis. */
825 #define MAX_LITERAL_POOL_SIZE 1024
826 typedef struct literal_pool
828 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
829 unsigned int next_free_entry
;
835 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
837 struct literal_pool
* next
;
838 unsigned int alignment
;
841 /* Pointer to a linked list of literal pools. */
842 literal_pool
* list_of_pools
= NULL
;
844 typedef enum asmfunc_states
847 WAITING_ASMFUNC_NAME
,
851 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
854 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
856 static struct current_it now_it
;
860 now_it_compatible (int cond
)
862 return (cond
& ~1) == (now_it
.cc
& ~1);
866 conditional_insn (void)
868 return inst
.cond
!= COND_ALWAYS
;
871 static int in_it_block (void);
873 static int handle_it_state (void);
875 static void force_automatic_it_block_close (void);
877 static void it_fsm_post_encode (void);
879 #define set_it_insn_type(type) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_nonvoid(type, failret) \
891 inst.it_insn_type = type; \
892 if (handle_it_state () == FAIL) \
897 #define set_it_insn_type_last() \
900 if (inst.cond == COND_ALWAYS) \
901 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
903 set_it_insn_type (INSIDE_IT_LAST_INSN); \
909 /* This array holds the chars that always start a comment. If the
910 pre-processor is disabled, these aren't very useful. */
911 char arm_comment_chars
[] = "@";
913 /* This array holds the chars that only start a comment at the beginning of
914 a line. If the line seems to have the form '# 123 filename'
915 .line and .file directives will appear in the pre-processed output. */
916 /* Note that input_file.c hand checks for '#' at the beginning of the
917 first line of the input file. This is because the compiler outputs
918 #NO_APP at the beginning of its output. */
919 /* Also note that comments like this one will always work. */
920 const char line_comment_chars
[] = "#";
922 char arm_line_separator_chars
[] = ";";
924 /* Chars that can be used to separate mant
925 from exp in floating point numbers. */
926 const char EXP_CHARS
[] = "eE";
928 /* Chars that mean this number is a floating point constant. */
932 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
934 /* Prefix characters that indicate the start of an immediate
936 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
938 /* Separator character handling. */
940 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
943 skip_past_char (char ** str
, char c
)
945 /* PR gas/14987: Allow for whitespace before the expected character. */
946 skip_whitespace (*str
);
957 #define skip_past_comma(str) skip_past_char (str, ',')
959 /* Arithmetic expressions (possibly involving symbols). */
961 /* Return TRUE if anything in the expression is a bignum. */
964 walk_no_bignums (symbolS
* sp
)
966 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
969 if (symbol_get_value_expression (sp
)->X_add_symbol
)
971 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
972 || (symbol_get_value_expression (sp
)->X_op_symbol
973 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
979 static int in_my_get_expression
= 0;
981 /* Third argument to my_get_expression. */
982 #define GE_NO_PREFIX 0
983 #define GE_IMM_PREFIX 1
984 #define GE_OPT_PREFIX 2
985 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
986 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
987 #define GE_OPT_PREFIX_BIG 3
990 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
995 /* In unified syntax, all prefixes are optional. */
997 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1000 switch (prefix_mode
)
1002 case GE_NO_PREFIX
: break;
1004 if (!is_immediate_prefix (**str
))
1006 inst
.error
= _("immediate expression requires a # prefix");
1012 case GE_OPT_PREFIX_BIG
:
1013 if (is_immediate_prefix (**str
))
1019 memset (ep
, 0, sizeof (expressionS
));
1021 save_in
= input_line_pointer
;
1022 input_line_pointer
= *str
;
1023 in_my_get_expression
= 1;
1024 seg
= expression (ep
);
1025 in_my_get_expression
= 0;
1027 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1029 /* We found a bad or missing expression in md_operand(). */
1030 *str
= input_line_pointer
;
1031 input_line_pointer
= save_in
;
1032 if (inst
.error
== NULL
)
1033 inst
.error
= (ep
->X_op
== O_absent
1034 ? _("missing expression") :_("bad expression"));
1039 if (seg
!= absolute_section
1040 && seg
!= text_section
1041 && seg
!= data_section
1042 && seg
!= bss_section
1043 && seg
!= undefined_section
)
1045 inst
.error
= _("bad segment");
1046 *str
= input_line_pointer
;
1047 input_line_pointer
= save_in
;
1054 /* Get rid of any bignums now, so that we don't generate an error for which
1055 we can't establish a line number later on. Big numbers are never valid
1056 in instructions, which is where this routine is always called. */
1057 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1058 && (ep
->X_op
== O_big
1059 || (ep
->X_add_symbol
1060 && (walk_no_bignums (ep
->X_add_symbol
)
1062 && walk_no_bignums (ep
->X_op_symbol
))))))
1064 inst
.error
= _("invalid constant");
1065 *str
= input_line_pointer
;
1066 input_line_pointer
= save_in
;
1070 *str
= input_line_pointer
;
1071 input_line_pointer
= save_in
;
1075 /* Turn a string in input_line_pointer into a floating point constant
1076 of type TYPE, and store the appropriate bytes in *LITP. The number
1077 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1078 returned, or NULL on OK.
1080 Note that fp constants aren't represent in the normal way on the ARM.
1081 In big endian mode, things are as expected. However, in little endian
1082 mode fp constants are big-endian word-wise, and little-endian byte-wise
1083 within the words. For example, (double) 1.1 in big endian mode is
1084 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1085 the byte sequence 99 99 f1 3f 9a 99 99 99.
1087 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1090 md_atof (int type
, char * litP
, int * sizeP
)
1093 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1125 return _("Unrecognized or unsupported floating point constant");
1128 t
= atof_ieee (input_line_pointer
, type
, words
);
1130 input_line_pointer
= t
;
1131 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1133 if (target_big_endian
)
1135 for (i
= 0; i
< prec
; i
++)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1143 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1144 for (i
= prec
- 1; i
>= 0; i
--)
1146 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1147 litP
+= sizeof (LITTLENUM_TYPE
);
1150 /* For a 4 byte float the order of elements in `words' is 1 0.
1151 For an 8 byte float the order is 1 0 3 2. */
1152 for (i
= 0; i
< prec
; i
+= 2)
1154 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1155 sizeof (LITTLENUM_TYPE
));
1156 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1157 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1158 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1165 /* We handle all bad expressions here, so that we can report the faulty
1166 instruction in the error message. */
1168 md_operand (expressionS
* exp
)
1170 if (in_my_get_expression
)
1171 exp
->X_op
= O_illegal
;
1174 /* Immediate values. */
1176 /* Generic immediate-value read function for use in directives.
1177 Accepts anything that 'expression' can fold to a constant.
1178 *val receives the number. */
1181 immediate_for_directive (int *val
)
1184 exp
.X_op
= O_illegal
;
1186 if (is_immediate_prefix (*input_line_pointer
))
1188 input_line_pointer
++;
1192 if (exp
.X_op
!= O_constant
)
1194 as_bad (_("expected #constant"));
1195 ignore_rest_of_line ();
1198 *val
= exp
.X_add_number
;
1203 /* Register parsing. */
1205 /* Generic register parser. CCP points to what should be the
1206 beginning of a register name. If it is indeed a valid register
1207 name, advance CCP over it and return the reg_entry structure;
1208 otherwise return NULL. Does not issue diagnostics. */
1210 static struct reg_entry
*
1211 arm_reg_parse_multi (char **ccp
)
1215 struct reg_entry
*reg
;
1217 skip_whitespace (start
);
1219 #ifdef REGISTER_PREFIX
1220 if (*start
!= REGISTER_PREFIX
)
1224 #ifdef OPTIONAL_REGISTER_PREFIX
1225 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1230 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1235 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1237 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1247 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1248 enum arm_reg_type type
)
1250 /* Alternative syntaxes are accepted for a few register classes. */
1257 /* Generic coprocessor register names are allowed for these. */
1258 if (reg
&& reg
->type
== REG_TYPE_CN
)
1263 /* For backward compatibility, a bare number is valid here. */
1265 unsigned long processor
= strtoul (start
, ccp
, 10);
1266 if (*ccp
!= start
&& processor
<= 15)
1270 case REG_TYPE_MMXWC
:
1271 /* WC includes WCG. ??? I'm not sure this is true for all
1272 instructions that take WC registers. */
1273 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1284 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1285 return value is the register number or FAIL. */
1288 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1291 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1294 /* Do not allow a scalar (reg+index) to parse as a register. */
1295 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1298 if (reg
&& reg
->type
== type
)
1301 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1308 /* Parse a Neon type specifier. *STR should point at the leading '.'
1309 character. Does no verification at this stage that the type fits the opcode
1316 Can all be legally parsed by this function.
1318 Fills in neon_type struct pointer with parsed information, and updates STR
1319 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1320 type, FAIL if not. */
1323 parse_neon_type (struct neon_type
*type
, char **str
)
1330 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1332 enum neon_el_type thistype
= NT_untyped
;
1333 unsigned thissize
= -1u;
1340 /* Just a size without an explicit type. */
1344 switch (TOLOWER (*ptr
))
1346 case 'i': thistype
= NT_integer
; break;
1347 case 'f': thistype
= NT_float
; break;
1348 case 'p': thistype
= NT_poly
; break;
1349 case 's': thistype
= NT_signed
; break;
1350 case 'u': thistype
= NT_unsigned
; break;
1352 thistype
= NT_float
;
1357 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1363 /* .f is an abbreviation for .f32. */
1364 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1369 thissize
= strtoul (ptr
, &ptr
, 10);
1371 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1374 as_bad (_("bad size %d in type specifier"), thissize
);
1382 type
->el
[type
->elems
].type
= thistype
;
1383 type
->el
[type
->elems
].size
= thissize
;
1388 /* Empty/missing type is not a successful parse. */
1389 if (type
->elems
== 0)
1397 /* Errors may be set multiple times during parsing or bit encoding
1398 (particularly in the Neon bits), but usually the earliest error which is set
1399 will be the most meaningful. Avoid overwriting it with later (cascading)
1400 errors by calling this function. */
1403 first_error (const char *err
)
1409 /* Parse a single type, e.g. ".s32", leading period included. */
1411 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1414 struct neon_type optype
;
1418 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1420 if (optype
.elems
== 1)
1421 *vectype
= optype
.el
[0];
1424 first_error (_("only one type should be specified for operand"));
1430 first_error (_("vector type expected"));
1442 /* Special meanings for indices (which have a range of 0-7), which will fit into
1445 #define NEON_ALL_LANES 15
1446 #define NEON_INTERLEAVE_LANES 14
1448 /* Parse either a register or a scalar, with an optional type. Return the
1449 register number, and optionally fill in the actual type of the register
1450 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1451 type/index information in *TYPEINFO. */
1454 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1455 enum arm_reg_type
*rtype
,
1456 struct neon_typed_alias
*typeinfo
)
1459 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1460 struct neon_typed_alias atype
;
1461 struct neon_type_el parsetype
;
1465 atype
.eltype
.type
= NT_invtype
;
1466 atype
.eltype
.size
= -1;
1468 /* Try alternate syntax for some types of register. Note these are mutually
1469 exclusive with the Neon syntax extensions. */
1472 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1480 /* Undo polymorphism when a set of register types may be accepted. */
1481 if ((type
== REG_TYPE_NDQ
1482 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1483 || (type
== REG_TYPE_VFSD
1484 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1485 || (type
== REG_TYPE_NSDQ
1486 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1487 || reg
->type
== REG_TYPE_NQ
))
1488 || (type
== REG_TYPE_MMXWC
1489 && (reg
->type
== REG_TYPE_MMXWCG
)))
1490 type
= (enum arm_reg_type
) reg
->type
;
1492 if (type
!= reg
->type
)
1498 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1500 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1502 first_error (_("can't redefine type for operand"));
1505 atype
.defined
|= NTA_HASTYPE
;
1506 atype
.eltype
= parsetype
;
1509 if (skip_past_char (&str
, '[') == SUCCESS
)
1511 if (type
!= REG_TYPE_VFD
)
1513 first_error (_("only D registers may be indexed"));
1517 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1519 first_error (_("can't change index for operand"));
1523 atype
.defined
|= NTA_HASINDEX
;
1525 if (skip_past_char (&str
, ']') == SUCCESS
)
1526 atype
.index
= NEON_ALL_LANES
;
1531 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1533 if (exp
.X_op
!= O_constant
)
1535 first_error (_("constant expression required"));
1539 if (skip_past_char (&str
, ']') == FAIL
)
1542 atype
.index
= exp
.X_add_number
;
1557 /* Like arm_reg_parse, but allow allow the following extra features:
1558 - If RTYPE is non-zero, return the (possibly restricted) type of the
1559 register (e.g. Neon double or quad reg when either has been requested).
1560 - If this is a Neon vector type with additional type information, fill
1561 in the struct pointed to by VECTYPE (if non-NULL).
1562 This function will fault on encountering a scalar. */
1565 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1566 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1568 struct neon_typed_alias atype
;
1570 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1575 /* Do not allow regname(... to parse as a register. */
1579 /* Do not allow a scalar (reg+index) to parse as a register. */
1580 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1582 first_error (_("register operand expected, but got scalar"));
1587 *vectype
= atype
.eltype
;
1594 #define NEON_SCALAR_REG(X) ((X) >> 4)
1595 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1597 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1598 have enough information to be able to do a good job bounds-checking. So, we
1599 just do easy checks here, and do further checks later. */
1602 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1606 struct neon_typed_alias atype
;
1608 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1610 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1613 if (atype
.index
== NEON_ALL_LANES
)
1615 first_error (_("scalar must have an index"));
1618 else if (atype
.index
>= 64 / elsize
)
1620 first_error (_("scalar index out of range"));
1625 *type
= atype
.eltype
;
1629 return reg
* 16 + atype
.index
;
1632 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1635 parse_reg_list (char ** strp
)
1637 char * str
= * strp
;
1641 /* We come back here if we get ranges concatenated by '+' or '|'. */
1644 skip_whitespace (str
);
1658 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1660 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1670 first_error (_("bad range in register list"));
1674 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1676 if (range
& (1 << i
))
1678 (_("Warning: duplicated register (r%d) in register list"),
1686 if (range
& (1 << reg
))
1687 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1689 else if (reg
<= cur_reg
)
1690 as_tsktsk (_("Warning: register range not in ascending order"));
1695 while (skip_past_comma (&str
) != FAIL
1696 || (in_range
= 1, *str
++ == '-'));
1699 if (skip_past_char (&str
, '}') == FAIL
)
1701 first_error (_("missing `}'"));
1709 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1712 if (exp
.X_op
== O_constant
)
1714 if (exp
.X_add_number
1715 != (exp
.X_add_number
& 0x0000ffff))
1717 inst
.error
= _("invalid register mask");
1721 if ((range
& exp
.X_add_number
) != 0)
1723 int regno
= range
& exp
.X_add_number
;
1726 regno
= (1 << regno
) - 1;
1728 (_("Warning: duplicated register (r%d) in register list"),
1732 range
|= exp
.X_add_number
;
1736 if (inst
.reloc
.type
!= 0)
1738 inst
.error
= _("expression too complex");
1742 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1743 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1744 inst
.reloc
.pc_rel
= 0;
1748 if (*str
== '|' || *str
== '+')
1754 while (another_range
);
1760 /* Types of registers in a list. */
1769 /* Parse a VFP register list. If the string is invalid return FAIL.
1770 Otherwise return the number of registers, and set PBASE to the first
1771 register. Parses registers of type ETYPE.
1772 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1773 - Q registers can be used to specify pairs of D registers
1774 - { } can be omitted from around a singleton register list
1775 FIXME: This is not implemented, as it would require backtracking in
1778 This could be done (the meaning isn't really ambiguous), but doesn't
1779 fit in well with the current parsing framework.
1780 - 32 D registers may be used (also true for VFPv3).
1781 FIXME: Types are ignored in these register lists, which is probably a
1785 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1790 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1794 unsigned long mask
= 0;
1797 if (skip_past_char (&str
, '{') == FAIL
)
1799 inst
.error
= _("expecting {");
1806 regtype
= REG_TYPE_VFS
;
1811 regtype
= REG_TYPE_VFD
;
1814 case REGLIST_NEON_D
:
1815 regtype
= REG_TYPE_NDQ
;
1819 if (etype
!= REGLIST_VFP_S
)
1821 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1822 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1826 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1829 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1836 base_reg
= max_regs
;
1840 int setmask
= 1, addregs
= 1;
1842 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1844 if (new_base
== FAIL
)
1846 first_error (_(reg_expected_msgs
[regtype
]));
1850 if (new_base
>= max_regs
)
1852 first_error (_("register out of range in list"));
1856 /* Note: a value of 2 * n is returned for the register Q<n>. */
1857 if (regtype
== REG_TYPE_NQ
)
1863 if (new_base
< base_reg
)
1864 base_reg
= new_base
;
1866 if (mask
& (setmask
<< new_base
))
1868 first_error (_("invalid register list"));
1872 if ((mask
>> new_base
) != 0 && ! warned
)
1874 as_tsktsk (_("register list not in ascending order"));
1878 mask
|= setmask
<< new_base
;
1881 if (*str
== '-') /* We have the start of a range expression */
1887 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1890 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1894 if (high_range
>= max_regs
)
1896 first_error (_("register out of range in list"));
1900 if (regtype
== REG_TYPE_NQ
)
1901 high_range
= high_range
+ 1;
1903 if (high_range
<= new_base
)
1905 inst
.error
= _("register range not in ascending order");
1909 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1911 if (mask
& (setmask
<< new_base
))
1913 inst
.error
= _("invalid register list");
1917 mask
|= setmask
<< new_base
;
1922 while (skip_past_comma (&str
) != FAIL
);
1926 /* Sanity check -- should have raised a parse error above. */
1927 if (count
== 0 || count
> max_regs
)
1932 /* Final test -- the registers must be consecutive. */
1934 for (i
= 0; i
< count
; i
++)
1936 if ((mask
& (1u << i
)) == 0)
1938 inst
.error
= _("non-contiguous register range");
1948 /* True if two alias types are the same. */
1951 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1959 if (a
->defined
!= b
->defined
)
1962 if ((a
->defined
& NTA_HASTYPE
) != 0
1963 && (a
->eltype
.type
!= b
->eltype
.type
1964 || a
->eltype
.size
!= b
->eltype
.size
))
1967 if ((a
->defined
& NTA_HASINDEX
) != 0
1968 && (a
->index
!= b
->index
))
1974 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1975 The base register is put in *PBASE.
1976 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1978 The register stride (minus one) is put in bit 4 of the return value.
1979 Bits [6:5] encode the list length (minus one).
1980 The type of the list elements is put in *ELTYPE, if non-NULL. */
1982 #define NEON_LANE(X) ((X) & 0xf)
1983 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1984 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1987 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1988 struct neon_type_el
*eltype
)
1995 int leading_brace
= 0;
1996 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1997 const char *const incr_error
= _("register stride must be 1 or 2");
1998 const char *const type_error
= _("mismatched element/structure types in list");
1999 struct neon_typed_alias firsttype
;
2000 firsttype
.defined
= 0;
2001 firsttype
.eltype
.type
= NT_invtype
;
2002 firsttype
.eltype
.size
= -1;
2003 firsttype
.index
= -1;
2005 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2010 struct neon_typed_alias atype
;
2011 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2015 first_error (_(reg_expected_msgs
[rtype
]));
2022 if (rtype
== REG_TYPE_NQ
)
2028 else if (reg_incr
== -1)
2030 reg_incr
= getreg
- base_reg
;
2031 if (reg_incr
< 1 || reg_incr
> 2)
2033 first_error (_(incr_error
));
2037 else if (getreg
!= base_reg
+ reg_incr
* count
)
2039 first_error (_(incr_error
));
2043 if (! neon_alias_types_same (&atype
, &firsttype
))
2045 first_error (_(type_error
));
2049 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2053 struct neon_typed_alias htype
;
2054 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2056 lane
= NEON_INTERLEAVE_LANES
;
2057 else if (lane
!= NEON_INTERLEAVE_LANES
)
2059 first_error (_(type_error
));
2064 else if (reg_incr
!= 1)
2066 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2070 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2073 first_error (_(reg_expected_msgs
[rtype
]));
2076 if (! neon_alias_types_same (&htype
, &firsttype
))
2078 first_error (_(type_error
));
2081 count
+= hireg
+ dregs
- getreg
;
2085 /* If we're using Q registers, we can't use [] or [n] syntax. */
2086 if (rtype
== REG_TYPE_NQ
)
2092 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2096 else if (lane
!= atype
.index
)
2098 first_error (_(type_error
));
2102 else if (lane
== -1)
2103 lane
= NEON_INTERLEAVE_LANES
;
2104 else if (lane
!= NEON_INTERLEAVE_LANES
)
2106 first_error (_(type_error
));
2111 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2113 /* No lane set by [x]. We must be interleaving structures. */
2115 lane
= NEON_INTERLEAVE_LANES
;
2118 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2119 || (count
> 1 && reg_incr
== -1))
2121 first_error (_("error parsing element/structure list"));
2125 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2127 first_error (_("expected }"));
2135 *eltype
= firsttype
.eltype
;
2140 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2143 /* Parse an explicit relocation suffix on an expression. This is
2144 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2145 arm_reloc_hsh contains no entries, so this function can only
2146 succeed if there is no () after the word. Returns -1 on error,
2147 BFD_RELOC_UNUSED if there wasn't any suffix. */
2150 parse_reloc (char **str
)
2152 struct reloc_entry
*r
;
2156 return BFD_RELOC_UNUSED
;
2161 while (*q
&& *q
!= ')' && *q
!= ',')
2166 if ((r
= (struct reloc_entry
*)
2167 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2174 /* Directives: register aliases. */
2176 static struct reg_entry
*
2177 insert_reg_alias (char *str
, unsigned number
, int type
)
2179 struct reg_entry
*new_reg
;
2182 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2184 if (new_reg
->builtin
)
2185 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2187 /* Only warn about a redefinition if it's not defined as the
2189 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2190 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2195 name
= xstrdup (str
);
2196 new_reg
= XNEW (struct reg_entry
);
2198 new_reg
->name
= name
;
2199 new_reg
->number
= number
;
2200 new_reg
->type
= type
;
2201 new_reg
->builtin
= FALSE
;
2202 new_reg
->neon
= NULL
;
2204 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2211 insert_neon_reg_alias (char *str
, int number
, int type
,
2212 struct neon_typed_alias
*atype
)
2214 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2218 first_error (_("attempt to redefine typed alias"));
2224 reg
->neon
= XNEW (struct neon_typed_alias
);
2225 *reg
->neon
= *atype
;
2229 /* Look for the .req directive. This is of the form:
2231 new_register_name .req existing_register_name
2233 If we find one, or if it looks sufficiently like one that we want to
2234 handle any error here, return TRUE. Otherwise return FALSE. */
2237 create_register_alias (char * newname
, char *p
)
2239 struct reg_entry
*old
;
2240 char *oldname
, *nbuf
;
2243 /* The input scrubber ensures that whitespace after the mnemonic is
2244 collapsed to single spaces. */
2246 if (strncmp (oldname
, " .req ", 6) != 0)
2250 if (*oldname
== '\0')
2253 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2256 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2260 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2261 the desired alias name, and p points to its end. If not, then
2262 the desired alias name is in the global original_case_string. */
2263 #ifdef TC_CASE_SENSITIVE
2266 newname
= original_case_string
;
2267 nlen
= strlen (newname
);
2270 nbuf
= xmalloc (nlen
+ 1);
2271 memcpy (nbuf
, newname
, nlen
);
2274 /* Create aliases under the new name as stated; an all-lowercase
2275 version of the new name; and an all-uppercase version of the new
2277 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2279 for (p
= nbuf
; *p
; p
++)
2282 if (strncmp (nbuf
, newname
, nlen
))
2284 /* If this attempt to create an additional alias fails, do not bother
2285 trying to create the all-lower case alias. We will fail and issue
2286 a second, duplicate error message. This situation arises when the
2287 programmer does something like:
2290 The second .req creates the "Foo" alias but then fails to create
2291 the artificial FOO alias because it has already been created by the
2293 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2300 for (p
= nbuf
; *p
; p
++)
2303 if (strncmp (nbuf
, newname
, nlen
))
2304 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2311 /* Create a Neon typed/indexed register alias using directives, e.g.:
2316 These typed registers can be used instead of the types specified after the
2317 Neon mnemonic, so long as all operands given have types. Types can also be
2318 specified directly, e.g.:
2319 vadd d0.s32, d1.s32, d2.s32 */
2322 create_neon_reg_alias (char *newname
, char *p
)
2324 enum arm_reg_type basetype
;
2325 struct reg_entry
*basereg
;
2326 struct reg_entry mybasereg
;
2327 struct neon_type ntype
;
2328 struct neon_typed_alias typeinfo
;
2329 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2332 typeinfo
.defined
= 0;
2333 typeinfo
.eltype
.type
= NT_invtype
;
2334 typeinfo
.eltype
.size
= -1;
2335 typeinfo
.index
= -1;
2339 if (strncmp (p
, " .dn ", 5) == 0)
2340 basetype
= REG_TYPE_VFD
;
2341 else if (strncmp (p
, " .qn ", 5) == 0)
2342 basetype
= REG_TYPE_NQ
;
2351 basereg
= arm_reg_parse_multi (&p
);
2353 if (basereg
&& basereg
->type
!= basetype
)
2355 as_bad (_("bad type for register"));
2359 if (basereg
== NULL
)
2362 /* Try parsing as an integer. */
2363 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2364 if (exp
.X_op
!= O_constant
)
2366 as_bad (_("expression must be constant"));
2369 basereg
= &mybasereg
;
2370 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2376 typeinfo
= *basereg
->neon
;
2378 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2380 /* We got a type. */
2381 if (typeinfo
.defined
& NTA_HASTYPE
)
2383 as_bad (_("can't redefine the type of a register alias"));
2387 typeinfo
.defined
|= NTA_HASTYPE
;
2388 if (ntype
.elems
!= 1)
2390 as_bad (_("you must specify a single type only"));
2393 typeinfo
.eltype
= ntype
.el
[0];
2396 if (skip_past_char (&p
, '[') == SUCCESS
)
2399 /* We got a scalar index. */
2401 if (typeinfo
.defined
& NTA_HASINDEX
)
2403 as_bad (_("can't redefine the index of a scalar alias"));
2407 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2409 if (exp
.X_op
!= O_constant
)
2411 as_bad (_("scalar index must be constant"));
2415 typeinfo
.defined
|= NTA_HASINDEX
;
2416 typeinfo
.index
= exp
.X_add_number
;
2418 if (skip_past_char (&p
, ']') == FAIL
)
2420 as_bad (_("expecting ]"));
2425 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2426 the desired alias name, and p points to its end. If not, then
2427 the desired alias name is in the global original_case_string. */
2428 #ifdef TC_CASE_SENSITIVE
2429 namelen
= nameend
- newname
;
2431 newname
= original_case_string
;
2432 namelen
= strlen (newname
);
2435 namebuf
= xmalloc (namelen
+ 1);
2436 strncpy (namebuf
, newname
, namelen
);
2437 namebuf
[namelen
] = '\0';
2439 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2440 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2442 /* Insert name in all uppercase. */
2443 for (p
= namebuf
; *p
; p
++)
2446 if (strncmp (namebuf
, newname
, namelen
))
2447 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2448 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2450 /* Insert name in all lowercase. */
2451 for (p
= namebuf
; *p
; p
++)
2454 if (strncmp (namebuf
, newname
, namelen
))
2455 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2456 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2462 /* Should never be called, as .req goes between the alias and the
2463 register name, not at the beginning of the line. */
2466 s_req (int a ATTRIBUTE_UNUSED
)
2468 as_bad (_("invalid syntax for .req directive"));
2472 s_dn (int a ATTRIBUTE_UNUSED
)
2474 as_bad (_("invalid syntax for .dn directive"));
2478 s_qn (int a ATTRIBUTE_UNUSED
)
2480 as_bad (_("invalid syntax for .qn directive"));
2483 /* The .unreq directive deletes an alias which was previously defined
2484 by .req. For example:
2490 s_unreq (int a ATTRIBUTE_UNUSED
)
2495 name
= input_line_pointer
;
2497 while (*input_line_pointer
!= 0
2498 && *input_line_pointer
!= ' '
2499 && *input_line_pointer
!= '\n')
2500 ++input_line_pointer
;
2502 saved_char
= *input_line_pointer
;
2503 *input_line_pointer
= 0;
2506 as_bad (_("invalid syntax for .unreq directive"));
2509 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2513 as_bad (_("unknown register alias '%s'"), name
);
2514 else if (reg
->builtin
)
2515 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2522 hash_delete (arm_reg_hsh
, name
, FALSE
);
2523 free ((char *) reg
->name
);
2528 /* Also locate the all upper case and all lower case versions.
2529 Do not complain if we cannot find one or the other as it
2530 was probably deleted above. */
2532 nbuf
= strdup (name
);
2533 for (p
= nbuf
; *p
; p
++)
2535 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2538 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2539 free ((char *) reg
->name
);
2545 for (p
= nbuf
; *p
; p
++)
2547 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2550 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2551 free ((char *) reg
->name
);
2561 *input_line_pointer
= saved_char
;
2562 demand_empty_rest_of_line ();
2565 /* Directives: Instruction set selection. */
2568 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2569 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2570 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2571 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2573 /* Create a new mapping symbol for the transition to STATE. */
2576 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2579 const char * symname
;
2586 type
= BSF_NO_FLAGS
;
2590 type
= BSF_NO_FLAGS
;
2594 type
= BSF_NO_FLAGS
;
2600 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2601 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2606 THUMB_SET_FUNC (symbolP
, 0);
2607 ARM_SET_THUMB (symbolP
, 0);
2608 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2612 THUMB_SET_FUNC (symbolP
, 1);
2613 ARM_SET_THUMB (symbolP
, 1);
2614 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2622 /* Save the mapping symbols for future reference. Also check that
2623 we do not place two mapping symbols at the same offset within a
2624 frag. We'll handle overlap between frags in
2625 check_mapping_symbols.
2627 If .fill or other data filling directive generates zero sized data,
2628 the mapping symbol for the following code will have the same value
2629 as the one generated for the data filling directive. In this case,
2630 we replace the old symbol with the new one at the same address. */
2633 if (frag
->tc_frag_data
.first_map
!= NULL
)
2635 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2636 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2638 frag
->tc_frag_data
.first_map
= symbolP
;
2640 if (frag
->tc_frag_data
.last_map
!= NULL
)
2642 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2643 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2644 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2646 frag
->tc_frag_data
.last_map
= symbolP
;
2649 /* We must sometimes convert a region marked as code to data during
2650 code alignment, if an odd number of bytes have to be padded. The
2651 code mapping symbol is pushed to an aligned address. */
2654 insert_data_mapping_symbol (enum mstate state
,
2655 valueT value
, fragS
*frag
, offsetT bytes
)
2657 /* If there was already a mapping symbol, remove it. */
2658 if (frag
->tc_frag_data
.last_map
!= NULL
2659 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2661 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2665 know (frag
->tc_frag_data
.first_map
== symp
);
2666 frag
->tc_frag_data
.first_map
= NULL
;
2668 frag
->tc_frag_data
.last_map
= NULL
;
2669 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2672 make_mapping_symbol (MAP_DATA
, value
, frag
);
2673 make_mapping_symbol (state
, value
+ bytes
, frag
);
2676 static void mapping_state_2 (enum mstate state
, int max_chars
);
2678 /* Set the mapping state to STATE. Only call this when about to
2679 emit some STATE bytes to the file. */
2681 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2683 mapping_state (enum mstate state
)
2685 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2687 if (mapstate
== state
)
2688 /* The mapping symbol has already been emitted.
2689 There is nothing else to do. */
2692 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2694 All ARM instructions require 4-byte alignment.
2695 (Almost) all Thumb instructions require 2-byte alignment.
2697 When emitting instructions into any section, mark the section
2700 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2701 but themselves require 2-byte alignment; this applies to some
2702 PC- relative forms. However, these cases will invovle implicit
2703 literal pool generation or an explicit .align >=2, both of
2704 which will cause the section to me marked with sufficient
2705 alignment. Thus, we don't handle those cases here. */
2706 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2708 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2709 /* This case will be evaluated later. */
2712 mapping_state_2 (state
, 0);
2715 /* Same as mapping_state, but MAX_CHARS bytes have already been
2716 allocated. Put the mapping symbol that far back. */
2719 mapping_state_2 (enum mstate state
, int max_chars
)
2721 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2723 if (!SEG_NORMAL (now_seg
))
2726 if (mapstate
== state
)
2727 /* The mapping symbol has already been emitted.
2728 There is nothing else to do. */
2731 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2732 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2734 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2735 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2738 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2741 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2742 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2746 #define mapping_state(x) ((void)0)
2747 #define mapping_state_2(x, y) ((void)0)
2750 /* Find the real, Thumb encoded start of a Thumb function. */
2754 find_real_start (symbolS
* symbolP
)
2757 const char * name
= S_GET_NAME (symbolP
);
2758 symbolS
* new_target
;
2760 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2761 #define STUB_NAME ".real_start_of"
2766 /* The compiler may generate BL instructions to local labels because
2767 it needs to perform a branch to a far away location. These labels
2768 do not have a corresponding ".real_start_of" label. We check
2769 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2770 the ".real_start_of" convention for nonlocal branches. */
2771 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2774 real_start
= concat (STUB_NAME
, name
, NULL
);
2775 new_target
= symbol_find (real_start
);
2778 if (new_target
== NULL
)
2780 as_warn (_("Failed to find real start of function: %s\n"), name
);
2781 new_target
= symbolP
;
2789 opcode_select (int width
)
2796 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2797 as_bad (_("selected processor does not support THUMB opcodes"));
2800 /* No need to force the alignment, since we will have been
2801 coming from ARM mode, which is word-aligned. */
2802 record_alignment (now_seg
, 1);
2809 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2810 as_bad (_("selected processor does not support ARM opcodes"));
2815 frag_align (2, 0, 0);
2817 record_alignment (now_seg
, 1);
2822 as_bad (_("invalid instruction size selected (%d)"), width
);
2827 s_arm (int ignore ATTRIBUTE_UNUSED
)
2830 demand_empty_rest_of_line ();
2834 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2837 demand_empty_rest_of_line ();
2841 s_code (int unused ATTRIBUTE_UNUSED
)
2845 temp
= get_absolute_expression ();
2850 opcode_select (temp
);
2854 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2859 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2861 /* If we are not already in thumb mode go into it, EVEN if
2862 the target processor does not support thumb instructions.
2863 This is used by gcc/config/arm/lib1funcs.asm for example
2864 to compile interworking support functions even if the
2865 target processor should not support interworking. */
2869 record_alignment (now_seg
, 1);
2872 demand_empty_rest_of_line ();
2876 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2880 /* The following label is the name/address of the start of a Thumb function.
2881 We need to know this for the interworking support. */
2882 label_is_thumb_function_name
= TRUE
;
2885 /* Perform a .set directive, but also mark the alias as
2886 being a thumb function. */
2889 s_thumb_set (int equiv
)
2891 /* XXX the following is a duplicate of the code for s_set() in read.c
2892 We cannot just call that code as we need to get at the symbol that
2899 /* Especial apologies for the random logic:
2900 This just grew, and could be parsed much more simply!
2902 delim
= get_symbol_name (& name
);
2903 end_name
= input_line_pointer
;
2904 (void) restore_line_pointer (delim
);
2906 if (*input_line_pointer
!= ',')
2909 as_bad (_("expected comma after name \"%s\""), name
);
2911 ignore_rest_of_line ();
2915 input_line_pointer
++;
2918 if (name
[0] == '.' && name
[1] == '\0')
2920 /* XXX - this should not happen to .thumb_set. */
2924 if ((symbolP
= symbol_find (name
)) == NULL
2925 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2928 /* When doing symbol listings, play games with dummy fragments living
2929 outside the normal fragment chain to record the file and line info
2931 if (listing
& LISTING_SYMBOLS
)
2933 extern struct list_info_struct
* listing_tail
;
2934 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2936 memset (dummy_frag
, 0, sizeof (fragS
));
2937 dummy_frag
->fr_type
= rs_fill
;
2938 dummy_frag
->line
= listing_tail
;
2939 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2940 dummy_frag
->fr_symbol
= symbolP
;
2944 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2947 /* "set" symbols are local unless otherwise specified. */
2948 SF_SET_LOCAL (symbolP
);
2949 #endif /* OBJ_COFF */
2950 } /* Make a new symbol. */
2952 symbol_table_insert (symbolP
);
2957 && S_IS_DEFINED (symbolP
)
2958 && S_GET_SEGMENT (symbolP
) != reg_section
)
2959 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2961 pseudo_set (symbolP
);
2963 demand_empty_rest_of_line ();
2965 /* XXX Now we come to the Thumb specific bit of code. */
2967 THUMB_SET_FUNC (symbolP
, 1);
2968 ARM_SET_THUMB (symbolP
, 1);
2969 #if defined OBJ_ELF || defined OBJ_COFF
2970 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2974 /* Directives: Mode selection. */
2976 /* .syntax [unified|divided] - choose the new unified syntax
2977 (same for Arm and Thumb encoding, modulo slight differences in what
2978 can be represented) or the old divergent syntax for each mode. */
2980 s_syntax (int unused ATTRIBUTE_UNUSED
)
2984 delim
= get_symbol_name (& name
);
2986 if (!strcasecmp (name
, "unified"))
2987 unified_syntax
= TRUE
;
2988 else if (!strcasecmp (name
, "divided"))
2989 unified_syntax
= FALSE
;
2992 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2995 (void) restore_line_pointer (delim
);
2996 demand_empty_rest_of_line ();
2999 /* Directives: sectioning and alignment. */
3002 s_bss (int ignore ATTRIBUTE_UNUSED
)
3004 /* We don't support putting frags in the BSS segment, we fake it by
3005 marking in_bss, then looking at s_skip for clues. */
3006 subseg_set (bss_section
, 0);
3007 demand_empty_rest_of_line ();
3009 #ifdef md_elf_section_change_hook
3010 md_elf_section_change_hook ();
3015 s_even (int ignore ATTRIBUTE_UNUSED
)
3017 /* Never make frag if expect extra pass. */
3019 frag_align (1, 0, 0);
3021 record_alignment (now_seg
, 1);
3023 demand_empty_rest_of_line ();
3026 /* Directives: CodeComposer Studio. */
3028 /* .ref (for CodeComposer Studio syntax only). */
3030 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3032 if (codecomposer_syntax
)
3033 ignore_rest_of_line ();
3035 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3038 /* If name is not NULL, then it is used for marking the beginning of a
3039 function, wherease if it is NULL then it means the function end. */
3041 asmfunc_debug (const char * name
)
3043 static const char * last_name
= NULL
;
3047 gas_assert (last_name
== NULL
);
3050 if (debug_type
== DEBUG_STABS
)
3051 stabs_generate_asm_func (name
, name
);
3055 gas_assert (last_name
!= NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_endfunc (last_name
, last_name
);
3065 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3067 if (codecomposer_syntax
)
3069 switch (asmfunc_state
)
3071 case OUTSIDE_ASMFUNC
:
3072 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3075 case WAITING_ASMFUNC_NAME
:
3076 as_bad (_(".asmfunc repeated."));
3079 case WAITING_ENDASMFUNC
:
3080 as_bad (_(".asmfunc without function."));
3083 demand_empty_rest_of_line ();
3086 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3090 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3092 if (codecomposer_syntax
)
3094 switch (asmfunc_state
)
3096 case OUTSIDE_ASMFUNC
:
3097 as_bad (_(".endasmfunc without a .asmfunc."));
3100 case WAITING_ASMFUNC_NAME
:
3101 as_bad (_(".endasmfunc without function."));
3104 case WAITING_ENDASMFUNC
:
3105 asmfunc_state
= OUTSIDE_ASMFUNC
;
3106 asmfunc_debug (NULL
);
3109 demand_empty_rest_of_line ();
3112 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3116 s_ccs_def (int name
)
3118 if (codecomposer_syntax
)
3121 as_bad (_(".def pseudo-op only available with -mccs flag."));
3124 /* Directives: Literal pools. */
3126 static literal_pool
*
3127 find_literal_pool (void)
3129 literal_pool
* pool
;
3131 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3133 if (pool
->section
== now_seg
3134 && pool
->sub_section
== now_subseg
)
3141 static literal_pool
*
3142 find_or_make_literal_pool (void)
3144 /* Next literal pool ID number. */
3145 static unsigned int latest_pool_num
= 1;
3146 literal_pool
* pool
;
3148 pool
= find_literal_pool ();
3152 /* Create a new pool. */
3153 pool
= XNEW (literal_pool
);
3157 pool
->next_free_entry
= 0;
3158 pool
->section
= now_seg
;
3159 pool
->sub_section
= now_subseg
;
3160 pool
->next
= list_of_pools
;
3161 pool
->symbol
= NULL
;
3162 pool
->alignment
= 2;
3164 /* Add it to the list. */
3165 list_of_pools
= pool
;
3168 /* New pools, and emptied pools, will have a NULL symbol. */
3169 if (pool
->symbol
== NULL
)
3171 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3172 (valueT
) 0, &zero_address_frag
);
3173 pool
->id
= latest_pool_num
++;
3180 /* Add the literal in the global 'inst'
3181 structure to the relevant literal pool. */
3184 add_to_lit_pool (unsigned int nbytes
)
3186 #define PADDING_SLOT 0x1
3187 #define LIT_ENTRY_SIZE_MASK 0xFF
3188 literal_pool
* pool
;
3189 unsigned int entry
, pool_size
= 0;
3190 bfd_boolean padding_slot_p
= FALSE
;
3196 imm1
= inst
.operands
[1].imm
;
3197 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3198 : inst
.reloc
.exp
.X_unsigned
? 0
3199 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3200 if (target_big_endian
)
3203 imm2
= inst
.operands
[1].imm
;
3207 pool
= find_or_make_literal_pool ();
3209 /* Check if this literal value is already in the pool. */
3210 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3214 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3215 && (inst
.reloc
.exp
.X_op
== O_constant
)
3216 && (pool
->literals
[entry
].X_add_number
3217 == inst
.reloc
.exp
.X_add_number
)
3218 && (pool
->literals
[entry
].X_md
== nbytes
)
3219 && (pool
->literals
[entry
].X_unsigned
3220 == inst
.reloc
.exp
.X_unsigned
))
3223 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3224 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3225 && (pool
->literals
[entry
].X_add_number
3226 == inst
.reloc
.exp
.X_add_number
)
3227 && (pool
->literals
[entry
].X_add_symbol
3228 == inst
.reloc
.exp
.X_add_symbol
)
3229 && (pool
->literals
[entry
].X_op_symbol
3230 == inst
.reloc
.exp
.X_op_symbol
)
3231 && (pool
->literals
[entry
].X_md
== nbytes
))
3234 else if ((nbytes
== 8)
3235 && !(pool_size
& 0x7)
3236 && ((entry
+ 1) != pool
->next_free_entry
)
3237 && (pool
->literals
[entry
].X_op
== O_constant
)
3238 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3239 && (pool
->literals
[entry
].X_unsigned
3240 == inst
.reloc
.exp
.X_unsigned
)
3241 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3242 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3243 && (pool
->literals
[entry
+ 1].X_unsigned
3244 == inst
.reloc
.exp
.X_unsigned
))
3247 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3248 if (padding_slot_p
&& (nbytes
== 4))
3254 /* Do we need to create a new entry? */
3255 if (entry
== pool
->next_free_entry
)
3257 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3259 inst
.error
= _("literal pool overflow");
3265 /* For 8-byte entries, we align to an 8-byte boundary,
3266 and split it into two 4-byte entries, because on 32-bit
3267 host, 8-byte constants are treated as big num, thus
3268 saved in "generic_bignum" which will be overwritten
3269 by later assignments.
3271 We also need to make sure there is enough space for
3274 We also check to make sure the literal operand is a
3276 if (!(inst
.reloc
.exp
.X_op
== O_constant
3277 || inst
.reloc
.exp
.X_op
== O_big
))
3279 inst
.error
= _("invalid type for literal pool");
3282 else if (pool_size
& 0x7)
3284 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3286 inst
.error
= _("literal pool overflow");
3290 pool
->literals
[entry
] = inst
.reloc
.exp
;
3291 pool
->literals
[entry
].X_op
= O_constant
;
3292 pool
->literals
[entry
].X_add_number
= 0;
3293 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3294 pool
->next_free_entry
+= 1;
3297 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3299 inst
.error
= _("literal pool overflow");
3303 pool
->literals
[entry
] = inst
.reloc
.exp
;
3304 pool
->literals
[entry
].X_op
= O_constant
;
3305 pool
->literals
[entry
].X_add_number
= imm1
;
3306 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3307 pool
->literals
[entry
++].X_md
= 4;
3308 pool
->literals
[entry
] = inst
.reloc
.exp
;
3309 pool
->literals
[entry
].X_op
= O_constant
;
3310 pool
->literals
[entry
].X_add_number
= imm2
;
3311 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3312 pool
->literals
[entry
].X_md
= 4;
3313 pool
->alignment
= 3;
3314 pool
->next_free_entry
+= 1;
3318 pool
->literals
[entry
] = inst
.reloc
.exp
;
3319 pool
->literals
[entry
].X_md
= 4;
3323 /* PR ld/12974: Record the location of the first source line to reference
3324 this entry in the literal pool. If it turns out during linking that the
3325 symbol does not exist we will be able to give an accurate line number for
3326 the (first use of the) missing reference. */
3327 if (debug_type
== DEBUG_DWARF2
)
3328 dwarf2_where (pool
->locs
+ entry
);
3330 pool
->next_free_entry
+= 1;
3332 else if (padding_slot_p
)
3334 pool
->literals
[entry
] = inst
.reloc
.exp
;
3335 pool
->literals
[entry
].X_md
= nbytes
;
3338 inst
.reloc
.exp
.X_op
= O_symbol
;
3339 inst
.reloc
.exp
.X_add_number
= pool_size
;
3340 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3346 tc_start_label_without_colon (void)
3348 bfd_boolean ret
= TRUE
;
3350 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3352 const char *label
= input_line_pointer
;
3354 while (!is_end_of_line
[(int) label
[-1]])
3359 as_bad (_("Invalid label '%s'"), label
);
3363 asmfunc_debug (label
);
3365 asmfunc_state
= WAITING_ENDASMFUNC
;
3371 /* Can't use symbol_new here, so have to create a symbol and then at
3372 a later date assign it a value. Thats what these functions do. */
3375 symbol_locate (symbolS
* symbolP
,
3376 const char * name
, /* It is copied, the caller can modify. */
3377 segT segment
, /* Segment identifier (SEG_<something>). */
3378 valueT valu
, /* Symbol value. */
3379 fragS
* frag
) /* Associated fragment. */
3382 char * preserved_copy_of_name
;
3384 name_length
= strlen (name
) + 1; /* +1 for \0. */
3385 obstack_grow (¬es
, name
, name_length
);
3386 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3388 #ifdef tc_canonicalize_symbol_name
3389 preserved_copy_of_name
=
3390 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3393 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3395 S_SET_SEGMENT (symbolP
, segment
);
3396 S_SET_VALUE (symbolP
, valu
);
3397 symbol_clear_list_pointers (symbolP
);
3399 symbol_set_frag (symbolP
, frag
);
3401 /* Link to end of symbol chain. */
3403 extern int symbol_table_frozen
;
3405 if (symbol_table_frozen
)
3409 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3411 obj_symbol_new_hook (symbolP
);
3413 #ifdef tc_symbol_new_hook
3414 tc_symbol_new_hook (symbolP
);
3418 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3419 #endif /* DEBUG_SYMS */
3423 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3426 literal_pool
* pool
;
3429 pool
= find_literal_pool ();
3431 || pool
->symbol
== NULL
3432 || pool
->next_free_entry
== 0)
3435 /* Align pool as you have word accesses.
3436 Only make a frag if we have to. */
3438 frag_align (pool
->alignment
, 0, 0);
3440 record_alignment (now_seg
, 2);
3443 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3444 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3446 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3448 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3449 (valueT
) frag_now_fix (), frag_now
);
3450 symbol_table_insert (pool
->symbol
);
3452 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3454 #if defined OBJ_COFF || defined OBJ_ELF
3455 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3458 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3461 if (debug_type
== DEBUG_DWARF2
)
3462 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3464 /* First output the expression in the instruction to the pool. */
3465 emit_expr (&(pool
->literals
[entry
]),
3466 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3469 /* Mark the pool as empty. */
3470 pool
->next_free_entry
= 0;
3471 pool
->symbol
= NULL
;
3475 /* Forward declarations for functions below, in the MD interface
3477 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3478 static valueT
create_unwind_entry (int);
3479 static void start_unwind_section (const segT
, int);
3480 static void add_unwind_opcode (valueT
, int);
3481 static void flush_pending_unwind (void);
3483 /* Directives: Data. */
3486 s_arm_elf_cons (int nbytes
)
3490 #ifdef md_flush_pending_output
3491 md_flush_pending_output ();
3494 if (is_it_end_of_statement ())
3496 demand_empty_rest_of_line ();
3500 #ifdef md_cons_align
3501 md_cons_align (nbytes
);
3504 mapping_state (MAP_DATA
);
3508 char *base
= input_line_pointer
;
3512 if (exp
.X_op
!= O_symbol
)
3513 emit_expr (&exp
, (unsigned int) nbytes
);
3516 char *before_reloc
= input_line_pointer
;
3517 reloc
= parse_reloc (&input_line_pointer
);
3520 as_bad (_("unrecognized relocation suffix"));
3521 ignore_rest_of_line ();
3524 else if (reloc
== BFD_RELOC_UNUSED
)
3525 emit_expr (&exp
, (unsigned int) nbytes
);
3528 reloc_howto_type
*howto
= (reloc_howto_type
*)
3529 bfd_reloc_type_lookup (stdoutput
,
3530 (bfd_reloc_code_real_type
) reloc
);
3531 int size
= bfd_get_reloc_size (howto
);
3533 if (reloc
== BFD_RELOC_ARM_PLT32
)
3535 as_bad (_("(plt) is only valid on branch targets"));
3536 reloc
= BFD_RELOC_UNUSED
;
3541 as_bad (_("%s relocations do not fit in %d bytes"),
3542 howto
->name
, nbytes
);
3545 /* We've parsed an expression stopping at O_symbol.
3546 But there may be more expression left now that we
3547 have parsed the relocation marker. Parse it again.
3548 XXX Surely there is a cleaner way to do this. */
3549 char *p
= input_line_pointer
;
3551 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3553 memcpy (save_buf
, base
, input_line_pointer
- base
);
3554 memmove (base
+ (input_line_pointer
- before_reloc
),
3555 base
, before_reloc
- base
);
3557 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3559 memcpy (base
, save_buf
, p
- base
);
3561 offset
= nbytes
- size
;
3562 p
= frag_more (nbytes
);
3563 memset (p
, 0, nbytes
);
3564 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3565 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3571 while (*input_line_pointer
++ == ',');
3573 /* Put terminator back into stream. */
3574 input_line_pointer
--;
3575 demand_empty_rest_of_line ();
3578 /* Emit an expression containing a 32-bit thumb instruction.
3579 Implementation based on put_thumb32_insn. */
3582 emit_thumb32_expr (expressionS
* exp
)
3584 expressionS exp_high
= *exp
;
3586 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3587 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3588 exp
->X_add_number
&= 0xffff;
3589 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3592 /* Guess the instruction size based on the opcode. */
3595 thumb_insn_size (int opcode
)
3597 if ((unsigned int) opcode
< 0xe800u
)
3599 else if ((unsigned int) opcode
>= 0xe8000000u
)
3606 emit_insn (expressionS
*exp
, int nbytes
)
3610 if (exp
->X_op
== O_constant
)
3615 size
= thumb_insn_size (exp
->X_add_number
);
3619 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3621 as_bad (_(".inst.n operand too big. "\
3622 "Use .inst.w instead"));
3627 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3628 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3630 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3632 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3633 emit_thumb32_expr (exp
);
3635 emit_expr (exp
, (unsigned int) size
);
3637 it_fsm_post_encode ();
3641 as_bad (_("cannot determine Thumb instruction size. " \
3642 "Use .inst.n/.inst.w instead"));
3645 as_bad (_("constant expression required"));
3650 /* Like s_arm_elf_cons but do not use md_cons_align and
3651 set the mapping state to MAP_ARM/MAP_THUMB. */
3654 s_arm_elf_inst (int nbytes
)
3656 if (is_it_end_of_statement ())
3658 demand_empty_rest_of_line ();
3662 /* Calling mapping_state () here will not change ARM/THUMB,
3663 but will ensure not to be in DATA state. */
3666 mapping_state (MAP_THUMB
);
3671 as_bad (_("width suffixes are invalid in ARM mode"));
3672 ignore_rest_of_line ();
3678 mapping_state (MAP_ARM
);
3687 if (! emit_insn (& exp
, nbytes
))
3689 ignore_rest_of_line ();
3693 while (*input_line_pointer
++ == ',');
3695 /* Put terminator back into stream. */
3696 input_line_pointer
--;
3697 demand_empty_rest_of_line ();
3700 /* Parse a .rel31 directive. */
3703 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3710 if (*input_line_pointer
== '1')
3711 highbit
= 0x80000000;
3712 else if (*input_line_pointer
!= '0')
3713 as_bad (_("expected 0 or 1"));
3715 input_line_pointer
++;
3716 if (*input_line_pointer
!= ',')
3717 as_bad (_("missing comma"));
3718 input_line_pointer
++;
3720 #ifdef md_flush_pending_output
3721 md_flush_pending_output ();
3724 #ifdef md_cons_align
3728 mapping_state (MAP_DATA
);
3733 md_number_to_chars (p
, highbit
, 4);
3734 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3735 BFD_RELOC_ARM_PREL31
);
3737 demand_empty_rest_of_line ();
3740 /* Directives: AEABI stack-unwind tables. */
3742 /* Parse an unwind_fnstart directive. Simply records the current location. */
3745 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3747 demand_empty_rest_of_line ();
3748 if (unwind
.proc_start
)
3750 as_bad (_("duplicate .fnstart directive"));
3754 /* Mark the start of the function. */
3755 unwind
.proc_start
= expr_build_dot ();
3757 /* Reset the rest of the unwind info. */
3758 unwind
.opcode_count
= 0;
3759 unwind
.table_entry
= NULL
;
3760 unwind
.personality_routine
= NULL
;
3761 unwind
.personality_index
= -1;
3762 unwind
.frame_size
= 0;
3763 unwind
.fp_offset
= 0;
3764 unwind
.fp_reg
= REG_SP
;
3766 unwind
.sp_restored
= 0;
3770 /* Parse a handlerdata directive. Creates the exception handling table entry
3771 for the function. */
3774 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3776 demand_empty_rest_of_line ();
3777 if (!unwind
.proc_start
)
3778 as_bad (MISSING_FNSTART
);
3780 if (unwind
.table_entry
)
3781 as_bad (_("duplicate .handlerdata directive"));
3783 create_unwind_entry (1);
3786 /* Parse an unwind_fnend directive. Generates the index table entry. */
3789 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3794 unsigned int marked_pr_dependency
;
3796 demand_empty_rest_of_line ();
3798 if (!unwind
.proc_start
)
3800 as_bad (_(".fnend directive without .fnstart"));
3804 /* Add eh table entry. */
3805 if (unwind
.table_entry
== NULL
)
3806 val
= create_unwind_entry (0);
3810 /* Add index table entry. This is two words. */
3811 start_unwind_section (unwind
.saved_seg
, 1);
3812 frag_align (2, 0, 0);
3813 record_alignment (now_seg
, 2);
3815 ptr
= frag_more (8);
3817 where
= frag_now_fix () - 8;
3819 /* Self relative offset of the function start. */
3820 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3821 BFD_RELOC_ARM_PREL31
);
3823 /* Indicate dependency on EHABI-defined personality routines to the
3824 linker, if it hasn't been done already. */
3825 marked_pr_dependency
3826 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3827 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3828 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3830 static const char *const name
[] =
3832 "__aeabi_unwind_cpp_pr0",
3833 "__aeabi_unwind_cpp_pr1",
3834 "__aeabi_unwind_cpp_pr2"
3836 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3837 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3838 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3839 |= 1 << unwind
.personality_index
;
3843 /* Inline exception table entry. */
3844 md_number_to_chars (ptr
+ 4, val
, 4);
3846 /* Self relative offset of the table entry. */
3847 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3848 BFD_RELOC_ARM_PREL31
);
3850 /* Restore the original section. */
3851 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3853 unwind
.proc_start
= NULL
;
3857 /* Parse an unwind_cantunwind directive. */
3860 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3862 demand_empty_rest_of_line ();
3863 if (!unwind
.proc_start
)
3864 as_bad (MISSING_FNSTART
);
3866 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3867 as_bad (_("personality routine specified for cantunwind frame"));
3869 unwind
.personality_index
= -2;
3873 /* Parse a personalityindex directive. */
3876 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3880 if (!unwind
.proc_start
)
3881 as_bad (MISSING_FNSTART
);
3883 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3884 as_bad (_("duplicate .personalityindex directive"));
3888 if (exp
.X_op
!= O_constant
3889 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3891 as_bad (_("bad personality routine number"));
3892 ignore_rest_of_line ();
3896 unwind
.personality_index
= exp
.X_add_number
;
3898 demand_empty_rest_of_line ();
3902 /* Parse a personality directive. */
3905 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3909 if (!unwind
.proc_start
)
3910 as_bad (MISSING_FNSTART
);
3912 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3913 as_bad (_("duplicate .personality directive"));
3915 c
= get_symbol_name (& name
);
3916 p
= input_line_pointer
;
3918 ++ input_line_pointer
;
3919 unwind
.personality_routine
= symbol_find_or_make (name
);
3921 demand_empty_rest_of_line ();
3925 /* Parse a directive saving core registers. */
3928 s_arm_unwind_save_core (void)
3934 range
= parse_reg_list (&input_line_pointer
);
3937 as_bad (_("expected register list"));
3938 ignore_rest_of_line ();
3942 demand_empty_rest_of_line ();
3944 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3945 into .unwind_save {..., sp...}. We aren't bothered about the value of
3946 ip because it is clobbered by calls. */
3947 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3948 && (range
& 0x3000) == 0x1000)
3950 unwind
.opcode_count
--;
3951 unwind
.sp_restored
= 0;
3952 range
= (range
| 0x2000) & ~0x1000;
3953 unwind
.pending_offset
= 0;
3959 /* See if we can use the short opcodes. These pop a block of up to 8
3960 registers starting with r4, plus maybe r14. */
3961 for (n
= 0; n
< 8; n
++)
3963 /* Break at the first non-saved register. */
3964 if ((range
& (1 << (n
+ 4))) == 0)
3967 /* See if there are any other bits set. */
3968 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3970 /* Use the long form. */
3971 op
= 0x8000 | ((range
>> 4) & 0xfff);
3972 add_unwind_opcode (op
, 2);
3976 /* Use the short form. */
3978 op
= 0xa8; /* Pop r14. */
3980 op
= 0xa0; /* Do not pop r14. */
3982 add_unwind_opcode (op
, 1);
3989 op
= 0xb100 | (range
& 0xf);
3990 add_unwind_opcode (op
, 2);
3993 /* Record the number of bytes pushed. */
3994 for (n
= 0; n
< 16; n
++)
3996 if (range
& (1 << n
))
3997 unwind
.frame_size
+= 4;
4002 /* Parse a directive saving FPA registers. */
4005 s_arm_unwind_save_fpa (int reg
)
4011 /* Get Number of registers to transfer. */
4012 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4015 exp
.X_op
= O_illegal
;
4017 if (exp
.X_op
!= O_constant
)
4019 as_bad (_("expected , <constant>"));
4020 ignore_rest_of_line ();
4024 num_regs
= exp
.X_add_number
;
4026 if (num_regs
< 1 || num_regs
> 4)
4028 as_bad (_("number of registers must be in the range [1:4]"));
4029 ignore_rest_of_line ();
4033 demand_empty_rest_of_line ();
4038 op
= 0xb4 | (num_regs
- 1);
4039 add_unwind_opcode (op
, 1);
4044 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4045 add_unwind_opcode (op
, 2);
4047 unwind
.frame_size
+= num_regs
* 12;
4051 /* Parse a directive saving VFP registers for ARMv6 and above. */
4054 s_arm_unwind_save_vfp_armv6 (void)
4059 int num_vfpv3_regs
= 0;
4060 int num_regs_below_16
;
4062 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4065 as_bad (_("expected register list"));
4066 ignore_rest_of_line ();
4070 demand_empty_rest_of_line ();
4072 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4073 than FSTMX/FLDMX-style ones). */
4075 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4077 num_vfpv3_regs
= count
;
4078 else if (start
+ count
> 16)
4079 num_vfpv3_regs
= start
+ count
- 16;
4081 if (num_vfpv3_regs
> 0)
4083 int start_offset
= start
> 16 ? start
- 16 : 0;
4084 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4085 add_unwind_opcode (op
, 2);
4088 /* Generate opcode for registers numbered in the range 0 .. 15. */
4089 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4090 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4091 if (num_regs_below_16
> 0)
4093 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4094 add_unwind_opcode (op
, 2);
4097 unwind
.frame_size
+= count
* 8;
4101 /* Parse a directive saving VFP registers for pre-ARMv6. */
4104 s_arm_unwind_save_vfp (void)
4110 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4113 as_bad (_("expected register list"));
4114 ignore_rest_of_line ();
4118 demand_empty_rest_of_line ();
4123 op
= 0xb8 | (count
- 1);
4124 add_unwind_opcode (op
, 1);
4129 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4130 add_unwind_opcode (op
, 2);
4132 unwind
.frame_size
+= count
* 8 + 4;
4136 /* Parse a directive saving iWMMXt data registers. */
4139 s_arm_unwind_save_mmxwr (void)
4147 if (*input_line_pointer
== '{')
4148 input_line_pointer
++;
4152 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4156 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4161 as_tsktsk (_("register list not in ascending order"));
4164 if (*input_line_pointer
== '-')
4166 input_line_pointer
++;
4167 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4170 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4173 else if (reg
>= hi_reg
)
4175 as_bad (_("bad register range"));
4178 for (; reg
< hi_reg
; reg
++)
4182 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4184 skip_past_char (&input_line_pointer
, '}');
4186 demand_empty_rest_of_line ();
4188 /* Generate any deferred opcodes because we're going to be looking at
4190 flush_pending_unwind ();
4192 for (i
= 0; i
< 16; i
++)
4194 if (mask
& (1 << i
))
4195 unwind
.frame_size
+= 8;
4198 /* Attempt to combine with a previous opcode. We do this because gcc
4199 likes to output separate unwind directives for a single block of
4201 if (unwind
.opcode_count
> 0)
4203 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4204 if ((i
& 0xf8) == 0xc0)
4207 /* Only merge if the blocks are contiguous. */
4210 if ((mask
& 0xfe00) == (1 << 9))
4212 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4213 unwind
.opcode_count
--;
4216 else if (i
== 6 && unwind
.opcode_count
>= 2)
4218 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4222 op
= 0xffff << (reg
- 1);
4224 && ((mask
& op
) == (1u << (reg
- 1))))
4226 op
= (1 << (reg
+ i
+ 1)) - 1;
4227 op
&= ~((1 << reg
) - 1);
4229 unwind
.opcode_count
-= 2;
4236 /* We want to generate opcodes in the order the registers have been
4237 saved, ie. descending order. */
4238 for (reg
= 15; reg
>= -1; reg
--)
4240 /* Save registers in blocks. */
4242 || !(mask
& (1 << reg
)))
4244 /* We found an unsaved reg. Generate opcodes to save the
4251 op
= 0xc0 | (hi_reg
- 10);
4252 add_unwind_opcode (op
, 1);
4257 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4258 add_unwind_opcode (op
, 2);
4267 ignore_rest_of_line ();
4271 s_arm_unwind_save_mmxwcg (void)
4278 if (*input_line_pointer
== '{')
4279 input_line_pointer
++;
4281 skip_whitespace (input_line_pointer
);
4285 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4289 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4295 as_tsktsk (_("register list not in ascending order"));
4298 if (*input_line_pointer
== '-')
4300 input_line_pointer
++;
4301 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4304 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4307 else if (reg
>= hi_reg
)
4309 as_bad (_("bad register range"));
4312 for (; reg
< hi_reg
; reg
++)
4316 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4318 skip_past_char (&input_line_pointer
, '}');
4320 demand_empty_rest_of_line ();
4322 /* Generate any deferred opcodes because we're going to be looking at
4324 flush_pending_unwind ();
4326 for (reg
= 0; reg
< 16; reg
++)
4328 if (mask
& (1 << reg
))
4329 unwind
.frame_size
+= 4;
4332 add_unwind_opcode (op
, 2);
4335 ignore_rest_of_line ();
4339 /* Parse an unwind_save directive.
4340 If the argument is non-zero, this is a .vsave directive. */
4343 s_arm_unwind_save (int arch_v6
)
4346 struct reg_entry
*reg
;
4347 bfd_boolean had_brace
= FALSE
;
4349 if (!unwind
.proc_start
)
4350 as_bad (MISSING_FNSTART
);
4352 /* Figure out what sort of save we have. */
4353 peek
= input_line_pointer
;
4361 reg
= arm_reg_parse_multi (&peek
);
4365 as_bad (_("register expected"));
4366 ignore_rest_of_line ();
4375 as_bad (_("FPA .unwind_save does not take a register list"));
4376 ignore_rest_of_line ();
4379 input_line_pointer
= peek
;
4380 s_arm_unwind_save_fpa (reg
->number
);
4384 s_arm_unwind_save_core ();
4389 s_arm_unwind_save_vfp_armv6 ();
4391 s_arm_unwind_save_vfp ();
4394 case REG_TYPE_MMXWR
:
4395 s_arm_unwind_save_mmxwr ();
4398 case REG_TYPE_MMXWCG
:
4399 s_arm_unwind_save_mmxwcg ();
4403 as_bad (_(".unwind_save does not support this kind of register"));
4404 ignore_rest_of_line ();
4409 /* Parse an unwind_movsp directive. */
4412 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4418 if (!unwind
.proc_start
)
4419 as_bad (MISSING_FNSTART
);
4421 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4424 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4425 ignore_rest_of_line ();
4429 /* Optional constant. */
4430 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4432 if (immediate_for_directive (&offset
) == FAIL
)
4438 demand_empty_rest_of_line ();
4440 if (reg
== REG_SP
|| reg
== REG_PC
)
4442 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4446 if (unwind
.fp_reg
!= REG_SP
)
4447 as_bad (_("unexpected .unwind_movsp directive"));
4449 /* Generate opcode to restore the value. */
4451 add_unwind_opcode (op
, 1);
4453 /* Record the information for later. */
4454 unwind
.fp_reg
= reg
;
4455 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4456 unwind
.sp_restored
= 1;
4459 /* Parse an unwind_pad directive. */
4462 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4466 if (!unwind
.proc_start
)
4467 as_bad (MISSING_FNSTART
);
4469 if (immediate_for_directive (&offset
) == FAIL
)
4474 as_bad (_("stack increment must be multiple of 4"));
4475 ignore_rest_of_line ();
4479 /* Don't generate any opcodes, just record the details for later. */
4480 unwind
.frame_size
+= offset
;
4481 unwind
.pending_offset
+= offset
;
4483 demand_empty_rest_of_line ();
4486 /* Parse an unwind_setfp directive. */
4489 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4495 if (!unwind
.proc_start
)
4496 as_bad (MISSING_FNSTART
);
4498 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4499 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4502 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4504 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4506 as_bad (_("expected <reg>, <reg>"));
4507 ignore_rest_of_line ();
4511 /* Optional constant. */
4512 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4514 if (immediate_for_directive (&offset
) == FAIL
)
4520 demand_empty_rest_of_line ();
4522 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4524 as_bad (_("register must be either sp or set by a previous"
4525 "unwind_movsp directive"));
4529 /* Don't generate any opcodes, just record the information for later. */
4530 unwind
.fp_reg
= fp_reg
;
4532 if (sp_reg
== REG_SP
)
4533 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4535 unwind
.fp_offset
-= offset
;
4538 /* Parse an unwind_raw directive. */
4541 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4544 /* This is an arbitrary limit. */
4545 unsigned char op
[16];
4548 if (!unwind
.proc_start
)
4549 as_bad (MISSING_FNSTART
);
4552 if (exp
.X_op
== O_constant
4553 && skip_past_comma (&input_line_pointer
) != FAIL
)
4555 unwind
.frame_size
+= exp
.X_add_number
;
4559 exp
.X_op
= O_illegal
;
4561 if (exp
.X_op
!= O_constant
)
4563 as_bad (_("expected <offset>, <opcode>"));
4564 ignore_rest_of_line ();
4570 /* Parse the opcode. */
4575 as_bad (_("unwind opcode too long"));
4576 ignore_rest_of_line ();
4578 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4580 as_bad (_("invalid unwind opcode"));
4581 ignore_rest_of_line ();
4584 op
[count
++] = exp
.X_add_number
;
4586 /* Parse the next byte. */
4587 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4593 /* Add the opcode bytes in reverse order. */
4595 add_unwind_opcode (op
[count
], 1);
4597 demand_empty_rest_of_line ();
4601 /* Parse a .eabi_attribute directive. */
4604 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4606 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4608 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4609 attributes_set_explicitly
[tag
] = 1;
4612 /* Emit a tls fix for the symbol. */
4615 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4619 #ifdef md_flush_pending_output
4620 md_flush_pending_output ();
4623 #ifdef md_cons_align
4627 /* Since we're just labelling the code, there's no need to define a
4630 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4631 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4632 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4633 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4635 #endif /* OBJ_ELF */
4637 static void s_arm_arch (int);
4638 static void s_arm_object_arch (int);
4639 static void s_arm_cpu (int);
4640 static void s_arm_fpu (int);
4641 static void s_arm_arch_extension (int);
4646 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4653 if (exp
.X_op
== O_symbol
)
4654 exp
.X_op
= O_secrel
;
4656 emit_expr (&exp
, 4);
4658 while (*input_line_pointer
++ == ',');
4660 input_line_pointer
--;
4661 demand_empty_rest_of_line ();
4665 /* This table describes all the machine specific pseudo-ops the assembler
4666 has to support. The fields are:
4667 pseudo-op name without dot
4668 function to call to execute this pseudo-op
4669 Integer arg to pass to the function. */
4671 const pseudo_typeS md_pseudo_table
[] =
4673 /* Never called because '.req' does not start a line. */
4674 { "req", s_req
, 0 },
4675 /* Following two are likewise never called. */
4678 { "unreq", s_unreq
, 0 },
4679 { "bss", s_bss
, 0 },
4680 { "align", s_align_ptwo
, 2 },
4681 { "arm", s_arm
, 0 },
4682 { "thumb", s_thumb
, 0 },
4683 { "code", s_code
, 0 },
4684 { "force_thumb", s_force_thumb
, 0 },
4685 { "thumb_func", s_thumb_func
, 0 },
4686 { "thumb_set", s_thumb_set
, 0 },
4687 { "even", s_even
, 0 },
4688 { "ltorg", s_ltorg
, 0 },
4689 { "pool", s_ltorg
, 0 },
4690 { "syntax", s_syntax
, 0 },
4691 { "cpu", s_arm_cpu
, 0 },
4692 { "arch", s_arm_arch
, 0 },
4693 { "object_arch", s_arm_object_arch
, 0 },
4694 { "fpu", s_arm_fpu
, 0 },
4695 { "arch_extension", s_arm_arch_extension
, 0 },
4697 { "word", s_arm_elf_cons
, 4 },
4698 { "long", s_arm_elf_cons
, 4 },
4699 { "inst.n", s_arm_elf_inst
, 2 },
4700 { "inst.w", s_arm_elf_inst
, 4 },
4701 { "inst", s_arm_elf_inst
, 0 },
4702 { "rel31", s_arm_rel31
, 0 },
4703 { "fnstart", s_arm_unwind_fnstart
, 0 },
4704 { "fnend", s_arm_unwind_fnend
, 0 },
4705 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4706 { "personality", s_arm_unwind_personality
, 0 },
4707 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4708 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4709 { "save", s_arm_unwind_save
, 0 },
4710 { "vsave", s_arm_unwind_save
, 1 },
4711 { "movsp", s_arm_unwind_movsp
, 0 },
4712 { "pad", s_arm_unwind_pad
, 0 },
4713 { "setfp", s_arm_unwind_setfp
, 0 },
4714 { "unwind_raw", s_arm_unwind_raw
, 0 },
4715 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4716 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4720 /* These are used for dwarf. */
4724 /* These are used for dwarf2. */
4725 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4726 { "loc", dwarf2_directive_loc
, 0 },
4727 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4729 { "extend", float_cons
, 'x' },
4730 { "ldouble", float_cons
, 'x' },
4731 { "packed", float_cons
, 'p' },
4733 {"secrel32", pe_directive_secrel
, 0},
4736 /* These are for compatibility with CodeComposer Studio. */
4737 {"ref", s_ccs_ref
, 0},
4738 {"def", s_ccs_def
, 0},
4739 {"asmfunc", s_ccs_asmfunc
, 0},
4740 {"endasmfunc", s_ccs_endasmfunc
, 0},
4745 /* Parser functions used exclusively in instruction operands. */
4747 /* Generic immediate-value read function for use in insn parsing.
4748 STR points to the beginning of the immediate (the leading #);
4749 VAL receives the value; if the value is outside [MIN, MAX]
4750 issue an error. PREFIX_OPT is true if the immediate prefix is
4754 parse_immediate (char **str
, int *val
, int min
, int max
,
4755 bfd_boolean prefix_opt
)
4758 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4759 if (exp
.X_op
!= O_constant
)
4761 inst
.error
= _("constant expression required");
4765 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4767 inst
.error
= _("immediate value out of range");
4771 *val
= exp
.X_add_number
;
4775 /* Less-generic immediate-value read function with the possibility of loading a
4776 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4777 instructions. Puts the result directly in inst.operands[i]. */
4780 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4781 bfd_boolean allow_symbol_p
)
4784 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4787 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4789 if (exp_p
->X_op
== O_constant
)
4791 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4792 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4793 O_constant. We have to be careful not to break compilation for
4794 32-bit X_add_number, though. */
4795 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4797 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4798 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4800 inst
.operands
[i
].regisimm
= 1;
4803 else if (exp_p
->X_op
== O_big
4804 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4806 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4808 /* Bignums have their least significant bits in
4809 generic_bignum[0]. Make sure we put 32 bits in imm and
4810 32 bits in reg, in a (hopefully) portable way. */
4811 gas_assert (parts
!= 0);
4813 /* Make sure that the number is not too big.
4814 PR 11972: Bignums can now be sign-extended to the
4815 size of a .octa so check that the out of range bits
4816 are all zero or all one. */
4817 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4819 LITTLENUM_TYPE m
= -1;
4821 if (generic_bignum
[parts
* 2] != 0
4822 && generic_bignum
[parts
* 2] != m
)
4825 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4826 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4830 inst
.operands
[i
].imm
= 0;
4831 for (j
= 0; j
< parts
; j
++, idx
++)
4832 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4833 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4834 inst
.operands
[i
].reg
= 0;
4835 for (j
= 0; j
< parts
; j
++, idx
++)
4836 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4837 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4838 inst
.operands
[i
].regisimm
= 1;
4840 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4848 /* Returns the pseudo-register number of an FPA immediate constant,
4849 or FAIL if there isn't a valid constant here. */
4852 parse_fpa_immediate (char ** str
)
4854 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4860 /* First try and match exact strings, this is to guarantee
4861 that some formats will work even for cross assembly. */
4863 for (i
= 0; fp_const
[i
]; i
++)
4865 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4869 *str
+= strlen (fp_const
[i
]);
4870 if (is_end_of_line
[(unsigned char) **str
])
4876 /* Just because we didn't get a match doesn't mean that the constant
4877 isn't valid, just that it is in a format that we don't
4878 automatically recognize. Try parsing it with the standard
4879 expression routines. */
4881 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4883 /* Look for a raw floating point number. */
4884 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4885 && is_end_of_line
[(unsigned char) *save_in
])
4887 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4889 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4891 if (words
[j
] != fp_values
[i
][j
])
4895 if (j
== MAX_LITTLENUMS
)
4903 /* Try and parse a more complex expression, this will probably fail
4904 unless the code uses a floating point prefix (eg "0f"). */
4905 save_in
= input_line_pointer
;
4906 input_line_pointer
= *str
;
4907 if (expression (&exp
) == absolute_section
4908 && exp
.X_op
== O_big
4909 && exp
.X_add_number
< 0)
4911 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4913 #define X_PRECISION 5
4914 #define E_PRECISION 15L
4915 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4917 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4919 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4921 if (words
[j
] != fp_values
[i
][j
])
4925 if (j
== MAX_LITTLENUMS
)
4927 *str
= input_line_pointer
;
4928 input_line_pointer
= save_in
;
4935 *str
= input_line_pointer
;
4936 input_line_pointer
= save_in
;
4937 inst
.error
= _("invalid FPA immediate expression");
4941 /* Returns 1 if a number has "quarter-precision" float format
4942 0baBbbbbbc defgh000 00000000 00000000. */
4945 is_quarter_float (unsigned imm
)
4947 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4948 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4952 /* Detect the presence of a floating point or integer zero constant,
4956 parse_ifimm_zero (char **in
)
4960 if (!is_immediate_prefix (**in
))
4965 /* Accept #0x0 as a synonym for #0. */
4966 if (strncmp (*in
, "0x", 2) == 0)
4969 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4974 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4975 &generic_floating_point_number
);
4978 && generic_floating_point_number
.sign
== '+'
4979 && (generic_floating_point_number
.low
4980 > generic_floating_point_number
.leader
))
4986 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4987 0baBbbbbbc defgh000 00000000 00000000.
4988 The zero and minus-zero cases need special handling, since they can't be
4989 encoded in the "quarter-precision" float format, but can nonetheless be
4990 loaded as integer constants. */
4993 parse_qfloat_immediate (char **ccp
, int *immed
)
4997 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4998 int found_fpchar
= 0;
5000 skip_past_char (&str
, '#');
5002 /* We must not accidentally parse an integer as a floating-point number. Make
5003 sure that the value we parse is not an integer by checking for special
5004 characters '.' or 'e'.
5005 FIXME: This is a horrible hack, but doing better is tricky because type
5006 information isn't in a very usable state at parse time. */
5008 skip_whitespace (fpnum
);
5010 if (strncmp (fpnum
, "0x", 2) == 0)
5014 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5015 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5025 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5027 unsigned fpword
= 0;
5030 /* Our FP word must be 32 bits (single-precision FP). */
5031 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5033 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5037 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5050 /* Shift operands. */
5053 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5056 struct asm_shift_name
5059 enum shift_kind kind
;
5062 /* Third argument to parse_shift. */
5063 enum parse_shift_mode
5065 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5066 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5067 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5068 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5069 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5072 /* Parse a <shift> specifier on an ARM data processing instruction.
5073 This has three forms:
5075 (LSL|LSR|ASL|ASR|ROR) Rs
5076 (LSL|LSR|ASL|ASR|ROR) #imm
5079 Note that ASL is assimilated to LSL in the instruction encoding, and
5080 RRX to ROR #0 (which cannot be written as such). */
5083 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5085 const struct asm_shift_name
*shift_name
;
5086 enum shift_kind shift
;
5091 for (p
= *str
; ISALPHA (*p
); p
++)
5096 inst
.error
= _("shift expression expected");
5100 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5103 if (shift_name
== NULL
)
5105 inst
.error
= _("shift expression expected");
5109 shift
= shift_name
->kind
;
5113 case NO_SHIFT_RESTRICT
:
5114 case SHIFT_IMMEDIATE
: break;
5116 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5117 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5119 inst
.error
= _("'LSL' or 'ASR' required");
5124 case SHIFT_LSL_IMMEDIATE
:
5125 if (shift
!= SHIFT_LSL
)
5127 inst
.error
= _("'LSL' required");
5132 case SHIFT_ASR_IMMEDIATE
:
5133 if (shift
!= SHIFT_ASR
)
5135 inst
.error
= _("'ASR' required");
5143 if (shift
!= SHIFT_RRX
)
5145 /* Whitespace can appear here if the next thing is a bare digit. */
5146 skip_whitespace (p
);
5148 if (mode
== NO_SHIFT_RESTRICT
5149 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5151 inst
.operands
[i
].imm
= reg
;
5152 inst
.operands
[i
].immisreg
= 1;
5154 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5157 inst
.operands
[i
].shift_kind
= shift
;
5158 inst
.operands
[i
].shifted
= 1;
5163 /* Parse a <shifter_operand> for an ARM data processing instruction:
5166 #<immediate>, <rotate>
5170 where <shift> is defined by parse_shift above, and <rotate> is a
5171 multiple of 2 between 0 and 30. Validation of immediate operands
5172 is deferred to md_apply_fix. */
5175 parse_shifter_operand (char **str
, int i
)
5180 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5182 inst
.operands
[i
].reg
= value
;
5183 inst
.operands
[i
].isreg
= 1;
5185 /* parse_shift will override this if appropriate */
5186 inst
.reloc
.exp
.X_op
= O_constant
;
5187 inst
.reloc
.exp
.X_add_number
= 0;
5189 if (skip_past_comma (str
) == FAIL
)
5192 /* Shift operation on register. */
5193 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5196 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5199 if (skip_past_comma (str
) == SUCCESS
)
5201 /* #x, y -- ie explicit rotation by Y. */
5202 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5205 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5207 inst
.error
= _("constant expression expected");
5211 value
= exp
.X_add_number
;
5212 if (value
< 0 || value
> 30 || value
% 2 != 0)
5214 inst
.error
= _("invalid rotation");
5217 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5219 inst
.error
= _("invalid constant");
5223 /* Encode as specified. */
5224 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5228 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5229 inst
.reloc
.pc_rel
= 0;
5233 /* Group relocation information. Each entry in the table contains the
5234 textual name of the relocation as may appear in assembler source
5235 and must end with a colon.
5236 Along with this textual name are the relocation codes to be used if
5237 the corresponding instruction is an ALU instruction (ADD or SUB only),
5238 an LDR, an LDRS, or an LDC. */
5240 struct group_reloc_table_entry
5251 /* Varieties of non-ALU group relocation. */
5258 static struct group_reloc_table_entry group_reloc_table
[] =
5259 { /* Program counter relative: */
5261 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5266 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5267 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5268 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5269 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5271 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5276 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5277 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5278 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5279 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5281 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5282 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5285 /* Section base relative */
5287 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5292 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5293 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5297 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5302 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5303 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5304 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5305 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5307 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5308 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5311 /* Absolute thumb alu relocations. */
5313 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5318 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5323 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5328 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5333 /* Given the address of a pointer pointing to the textual name of a group
5334 relocation as may appear in assembler source, attempt to find its details
5335 in group_reloc_table. The pointer will be updated to the character after
5336 the trailing colon. On failure, FAIL will be returned; SUCCESS
5337 otherwise. On success, *entry will be updated to point at the relevant
5338 group_reloc_table entry. */
5341 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5344 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5346 int length
= strlen (group_reloc_table
[i
].name
);
5348 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5349 && (*str
)[length
] == ':')
5351 *out
= &group_reloc_table
[i
];
5352 *str
+= (length
+ 1);
5360 /* Parse a <shifter_operand> for an ARM data processing instruction
5361 (as for parse_shifter_operand) where group relocations are allowed:
5364 #<immediate>, <rotate>
5365 #:<group_reloc>:<expression>
5369 where <group_reloc> is one of the strings defined in group_reloc_table.
5370 The hashes are optional.
5372 Everything else is as for parse_shifter_operand. */
5374 static parse_operand_result
5375 parse_shifter_operand_group_reloc (char **str
, int i
)
5377 /* Determine if we have the sequence of characters #: or just :
5378 coming next. If we do, then we check for a group relocation.
5379 If we don't, punt the whole lot to parse_shifter_operand. */
5381 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5382 || (*str
)[0] == ':')
5384 struct group_reloc_table_entry
*entry
;
5386 if ((*str
)[0] == '#')
5391 /* Try to parse a group relocation. Anything else is an error. */
5392 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5394 inst
.error
= _("unknown group relocation");
5395 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5398 /* We now have the group relocation table entry corresponding to
5399 the name in the assembler source. Next, we parse the expression. */
5400 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5401 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5403 /* Record the relocation type (always the ALU variant here). */
5404 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5405 gas_assert (inst
.reloc
.type
!= 0);
5407 return PARSE_OPERAND_SUCCESS
;
5410 return parse_shifter_operand (str
, i
) == SUCCESS
5411 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5413 /* Never reached. */
5416 /* Parse a Neon alignment expression. Information is written to
5417 inst.operands[i]. We assume the initial ':' has been skipped.
5419 align .imm = align << 8, .immisalign=1, .preind=0 */
5420 static parse_operand_result
5421 parse_neon_alignment (char **str
, int i
)
5426 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5428 if (exp
.X_op
!= O_constant
)
5430 inst
.error
= _("alignment must be constant");
5431 return PARSE_OPERAND_FAIL
;
5434 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5435 inst
.operands
[i
].immisalign
= 1;
5436 /* Alignments are not pre-indexes. */
5437 inst
.operands
[i
].preind
= 0;
5440 return PARSE_OPERAND_SUCCESS
;
5443 /* Parse all forms of an ARM address expression. Information is written
5444 to inst.operands[i] and/or inst.reloc.
5446 Preindexed addressing (.preind=1):
5448 [Rn, #offset] .reg=Rn .reloc.exp=offset
5449 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5450 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5451 .shift_kind=shift .reloc.exp=shift_imm
5453 These three may have a trailing ! which causes .writeback to be set also.
5455 Postindexed addressing (.postind=1, .writeback=1):
5457 [Rn], #offset .reg=Rn .reloc.exp=offset
5458 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5459 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5460 .shift_kind=shift .reloc.exp=shift_imm
5462 Unindexed addressing (.preind=0, .postind=0):
5464 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5468 [Rn]{!} shorthand for [Rn,#0]{!}
5469 =immediate .isreg=0 .reloc.exp=immediate
5470 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5472 It is the caller's responsibility to check for addressing modes not
5473 supported by the instruction, and to set inst.reloc.type. */
5475 static parse_operand_result
5476 parse_address_main (char **str
, int i
, int group_relocations
,
5477 group_reloc_type group_type
)
5482 if (skip_past_char (&p
, '[') == FAIL
)
5484 if (skip_past_char (&p
, '=') == FAIL
)
5486 /* Bare address - translate to PC-relative offset. */
5487 inst
.reloc
.pc_rel
= 1;
5488 inst
.operands
[i
].reg
= REG_PC
;
5489 inst
.operands
[i
].isreg
= 1;
5490 inst
.operands
[i
].preind
= 1;
5492 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5493 return PARSE_OPERAND_FAIL
;
5495 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5496 /*allow_symbol_p=*/TRUE
))
5497 return PARSE_OPERAND_FAIL
;
5500 return PARSE_OPERAND_SUCCESS
;
5503 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5504 skip_whitespace (p
);
5506 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5508 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5509 return PARSE_OPERAND_FAIL
;
5511 inst
.operands
[i
].reg
= reg
;
5512 inst
.operands
[i
].isreg
= 1;
5514 if (skip_past_comma (&p
) == SUCCESS
)
5516 inst
.operands
[i
].preind
= 1;
5519 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5521 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5523 inst
.operands
[i
].imm
= reg
;
5524 inst
.operands
[i
].immisreg
= 1;
5526 if (skip_past_comma (&p
) == SUCCESS
)
5527 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5528 return PARSE_OPERAND_FAIL
;
5530 else if (skip_past_char (&p
, ':') == SUCCESS
)
5532 /* FIXME: '@' should be used here, but it's filtered out by generic
5533 code before we get to see it here. This may be subject to
5535 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5537 if (result
!= PARSE_OPERAND_SUCCESS
)
5542 if (inst
.operands
[i
].negative
)
5544 inst
.operands
[i
].negative
= 0;
5548 if (group_relocations
5549 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5551 struct group_reloc_table_entry
*entry
;
5553 /* Skip over the #: or : sequence. */
5559 /* Try to parse a group relocation. Anything else is an
5561 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5563 inst
.error
= _("unknown group relocation");
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5567 /* We now have the group relocation table entry corresponding to
5568 the name in the assembler source. Next, we parse the
5570 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5571 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5573 /* Record the relocation type. */
5577 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5581 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5585 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5592 if (inst
.reloc
.type
== 0)
5594 inst
.error
= _("this group relocation is not allowed on this instruction");
5595 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5601 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5602 return PARSE_OPERAND_FAIL
;
5603 /* If the offset is 0, find out if it's a +0 or -0. */
5604 if (inst
.reloc
.exp
.X_op
== O_constant
5605 && inst
.reloc
.exp
.X_add_number
== 0)
5607 skip_whitespace (q
);
5611 skip_whitespace (q
);
5614 inst
.operands
[i
].negative
= 1;
5619 else if (skip_past_char (&p
, ':') == SUCCESS
)
5621 /* FIXME: '@' should be used here, but it's filtered out by generic code
5622 before we get to see it here. This may be subject to change. */
5623 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5625 if (result
!= PARSE_OPERAND_SUCCESS
)
5629 if (skip_past_char (&p
, ']') == FAIL
)
5631 inst
.error
= _("']' expected");
5632 return PARSE_OPERAND_FAIL
;
5635 if (skip_past_char (&p
, '!') == SUCCESS
)
5636 inst
.operands
[i
].writeback
= 1;
5638 else if (skip_past_comma (&p
) == SUCCESS
)
5640 if (skip_past_char (&p
, '{') == SUCCESS
)
5642 /* [Rn], {expr} - unindexed, with option */
5643 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5644 0, 255, TRUE
) == FAIL
)
5645 return PARSE_OPERAND_FAIL
;
5647 if (skip_past_char (&p
, '}') == FAIL
)
5649 inst
.error
= _("'}' expected at end of 'option' field");
5650 return PARSE_OPERAND_FAIL
;
5652 if (inst
.operands
[i
].preind
)
5654 inst
.error
= _("cannot combine index with option");
5655 return PARSE_OPERAND_FAIL
;
5658 return PARSE_OPERAND_SUCCESS
;
5662 inst
.operands
[i
].postind
= 1;
5663 inst
.operands
[i
].writeback
= 1;
5665 if (inst
.operands
[i
].preind
)
5667 inst
.error
= _("cannot combine pre- and post-indexing");
5668 return PARSE_OPERAND_FAIL
;
5672 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5674 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5676 /* We might be using the immediate for alignment already. If we
5677 are, OR the register number into the low-order bits. */
5678 if (inst
.operands
[i
].immisalign
)
5679 inst
.operands
[i
].imm
|= reg
;
5681 inst
.operands
[i
].imm
= reg
;
5682 inst
.operands
[i
].immisreg
= 1;
5684 if (skip_past_comma (&p
) == SUCCESS
)
5685 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5686 return PARSE_OPERAND_FAIL
;
5691 if (inst
.operands
[i
].negative
)
5693 inst
.operands
[i
].negative
= 0;
5696 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5697 return PARSE_OPERAND_FAIL
;
5698 /* If the offset is 0, find out if it's a +0 or -0. */
5699 if (inst
.reloc
.exp
.X_op
== O_constant
5700 && inst
.reloc
.exp
.X_add_number
== 0)
5702 skip_whitespace (q
);
5706 skip_whitespace (q
);
5709 inst
.operands
[i
].negative
= 1;
5715 /* If at this point neither .preind nor .postind is set, we have a
5716 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5717 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5719 inst
.operands
[i
].preind
= 1;
5720 inst
.reloc
.exp
.X_op
= O_constant
;
5721 inst
.reloc
.exp
.X_add_number
= 0;
5724 return PARSE_OPERAND_SUCCESS
;
5728 parse_address (char **str
, int i
)
5730 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5734 static parse_operand_result
5735 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5737 return parse_address_main (str
, i
, 1, type
);
5740 /* Parse an operand for a MOVW or MOVT instruction. */
5742 parse_half (char **str
)
5747 skip_past_char (&p
, '#');
5748 if (strncasecmp (p
, ":lower16:", 9) == 0)
5749 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5750 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5751 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5753 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5756 skip_whitespace (p
);
5759 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5762 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5764 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5766 inst
.error
= _("constant expression expected");
5769 if (inst
.reloc
.exp
.X_add_number
< 0
5770 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5772 inst
.error
= _("immediate value out of range");
5780 /* Miscellaneous. */
5782 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5783 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5785 parse_psr (char **str
, bfd_boolean lhs
)
5788 unsigned long psr_field
;
5789 const struct asm_psr
*psr
;
5791 bfd_boolean is_apsr
= FALSE
;
5792 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5794 /* PR gas/12698: If the user has specified -march=all then m_profile will
5795 be TRUE, but we want to ignore it in this case as we are building for any
5796 CPU type, including non-m variants. */
5797 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5800 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5801 feature for ease of use and backwards compatibility. */
5803 if (strncasecmp (p
, "SPSR", 4) == 0)
5806 goto unsupported_psr
;
5808 psr_field
= SPSR_BIT
;
5810 else if (strncasecmp (p
, "CPSR", 4) == 0)
5813 goto unsupported_psr
;
5817 else if (strncasecmp (p
, "APSR", 4) == 0)
5819 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5820 and ARMv7-R architecture CPUs. */
5829 while (ISALNUM (*p
) || *p
== '_');
5831 if (strncasecmp (start
, "iapsr", 5) == 0
5832 || strncasecmp (start
, "eapsr", 5) == 0
5833 || strncasecmp (start
, "xpsr", 4) == 0
5834 || strncasecmp (start
, "psr", 3) == 0)
5835 p
= start
+ strcspn (start
, "rR") + 1;
5837 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5843 /* If APSR is being written, a bitfield may be specified. Note that
5844 APSR itself is handled above. */
5845 if (psr
->field
<= 3)
5847 psr_field
= psr
->field
;
5853 /* M-profile MSR instructions have the mask field set to "10", except
5854 *PSR variants which modify APSR, which may use a different mask (and
5855 have been handled already). Do that by setting the PSR_f field
5857 return psr
->field
| (lhs
? PSR_f
: 0);
5860 goto unsupported_psr
;
5866 /* A suffix follows. */
5872 while (ISALNUM (*p
) || *p
== '_');
5876 /* APSR uses a notation for bits, rather than fields. */
5877 unsigned int nzcvq_bits
= 0;
5878 unsigned int g_bit
= 0;
5881 for (bit
= start
; bit
!= p
; bit
++)
5883 switch (TOLOWER (*bit
))
5886 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5890 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5894 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5898 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5902 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5906 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5910 inst
.error
= _("unexpected bit specified after APSR");
5915 if (nzcvq_bits
== 0x1f)
5920 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5922 inst
.error
= _("selected processor does not "
5923 "support DSP extension");
5930 if ((nzcvq_bits
& 0x20) != 0
5931 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5932 || (g_bit
& 0x2) != 0)
5934 inst
.error
= _("bad bitmask specified after APSR");
5940 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5945 psr_field
|= psr
->field
;
5951 goto error
; /* Garbage after "[CS]PSR". */
5953 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5954 is deprecated, but allow it anyway. */
5958 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5961 else if (!m_profile
)
5962 /* These bits are never right for M-profile devices: don't set them
5963 (only code paths which read/write APSR reach here). */
5964 psr_field
|= (PSR_c
| PSR_f
);
5970 inst
.error
= _("selected processor does not support requested special "
5971 "purpose register");
5975 inst
.error
= _("flag for {c}psr instruction expected");
5979 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5980 value suitable for splatting into the AIF field of the instruction. */
5983 parse_cps_flags (char **str
)
5992 case '\0': case ',':
5995 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5996 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5997 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6000 inst
.error
= _("unrecognized CPS flag");
6005 if (saw_a_flag
== 0)
6007 inst
.error
= _("missing CPS flags");
6015 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6016 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6019 parse_endian_specifier (char **str
)
6024 if (strncasecmp (s
, "BE", 2))
6026 else if (strncasecmp (s
, "LE", 2))
6030 inst
.error
= _("valid endian specifiers are be or le");
6034 if (ISALNUM (s
[2]) || s
[2] == '_')
6036 inst
.error
= _("valid endian specifiers are be or le");
6041 return little_endian
;
6044 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6045 value suitable for poking into the rotate field of an sxt or sxta
6046 instruction, or FAIL on error. */
6049 parse_ror (char **str
)
6054 if (strncasecmp (s
, "ROR", 3) == 0)
6058 inst
.error
= _("missing rotation field after comma");
6062 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6067 case 0: *str
= s
; return 0x0;
6068 case 8: *str
= s
; return 0x1;
6069 case 16: *str
= s
; return 0x2;
6070 case 24: *str
= s
; return 0x3;
6073 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6078 /* Parse a conditional code (from conds[] below). The value returned is in the
6079 range 0 .. 14, or FAIL. */
6081 parse_cond (char **str
)
6084 const struct asm_cond
*c
;
6086 /* Condition codes are always 2 characters, so matching up to
6087 3 characters is sufficient. */
6092 while (ISALPHA (*q
) && n
< 3)
6094 cond
[n
] = TOLOWER (*q
);
6099 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6102 inst
.error
= _("condition required");
6110 /* Record a use of the given feature. */
6112 record_feature_use (const arm_feature_set
*feature
)
6115 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6117 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6120 /* If the given feature available in the selected CPU, mark it as used.
6121 Returns TRUE iff feature is available. */
6123 mark_feature_used (const arm_feature_set
*feature
)
6125 /* Ensure the option is valid on the current architecture. */
6126 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6129 /* Add the appropriate architecture feature for the barrier option used.
6131 record_feature_use (feature
);
6136 /* Parse an option for a barrier instruction. Returns the encoding for the
6139 parse_barrier (char **str
)
6142 const struct asm_barrier_opt
*o
;
6145 while (ISALPHA (*q
))
6148 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6153 if (!mark_feature_used (&o
->arch
))
6160 /* Parse the operands of a table branch instruction. Similar to a memory
6163 parse_tb (char **str
)
6168 if (skip_past_char (&p
, '[') == FAIL
)
6170 inst
.error
= _("'[' expected");
6174 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6176 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6179 inst
.operands
[0].reg
= reg
;
6181 if (skip_past_comma (&p
) == FAIL
)
6183 inst
.error
= _("',' expected");
6187 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6189 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6192 inst
.operands
[0].imm
= reg
;
6194 if (skip_past_comma (&p
) == SUCCESS
)
6196 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6198 if (inst
.reloc
.exp
.X_add_number
!= 1)
6200 inst
.error
= _("invalid shift");
6203 inst
.operands
[0].shifted
= 1;
6206 if (skip_past_char (&p
, ']') == FAIL
)
6208 inst
.error
= _("']' expected");
6215 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6216 information on the types the operands can take and how they are encoded.
6217 Up to four operands may be read; this function handles setting the
6218 ".present" field for each read operand itself.
6219 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6220 else returns FAIL. */
6223 parse_neon_mov (char **str
, int *which_operand
)
6225 int i
= *which_operand
, val
;
6226 enum arm_reg_type rtype
;
6228 struct neon_type_el optype
;
6230 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6232 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6233 inst
.operands
[i
].reg
= val
;
6234 inst
.operands
[i
].isscalar
= 1;
6235 inst
.operands
[i
].vectype
= optype
;
6236 inst
.operands
[i
++].present
= 1;
6238 if (skip_past_comma (&ptr
) == FAIL
)
6241 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6244 inst
.operands
[i
].reg
= val
;
6245 inst
.operands
[i
].isreg
= 1;
6246 inst
.operands
[i
].present
= 1;
6248 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6251 /* Cases 0, 1, 2, 3, 5 (D only). */
6252 if (skip_past_comma (&ptr
) == FAIL
)
6255 inst
.operands
[i
].reg
= val
;
6256 inst
.operands
[i
].isreg
= 1;
6257 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6258 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6259 inst
.operands
[i
].isvec
= 1;
6260 inst
.operands
[i
].vectype
= optype
;
6261 inst
.operands
[i
++].present
= 1;
6263 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6265 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6266 Case 13: VMOV <Sd>, <Rm> */
6267 inst
.operands
[i
].reg
= val
;
6268 inst
.operands
[i
].isreg
= 1;
6269 inst
.operands
[i
].present
= 1;
6271 if (rtype
== REG_TYPE_NQ
)
6273 first_error (_("can't use Neon quad register here"));
6276 else if (rtype
!= REG_TYPE_VFS
)
6279 if (skip_past_comma (&ptr
) == FAIL
)
6281 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6283 inst
.operands
[i
].reg
= val
;
6284 inst
.operands
[i
].isreg
= 1;
6285 inst
.operands
[i
].present
= 1;
6288 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6291 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6292 Case 1: VMOV<c><q> <Dd>, <Dm>
6293 Case 8: VMOV.F32 <Sd>, <Sm>
6294 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6296 inst
.operands
[i
].reg
= val
;
6297 inst
.operands
[i
].isreg
= 1;
6298 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6299 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6300 inst
.operands
[i
].isvec
= 1;
6301 inst
.operands
[i
].vectype
= optype
;
6302 inst
.operands
[i
].present
= 1;
6304 if (skip_past_comma (&ptr
) == SUCCESS
)
6309 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6312 inst
.operands
[i
].reg
= val
;
6313 inst
.operands
[i
].isreg
= 1;
6314 inst
.operands
[i
++].present
= 1;
6316 if (skip_past_comma (&ptr
) == FAIL
)
6319 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6322 inst
.operands
[i
].reg
= val
;
6323 inst
.operands
[i
].isreg
= 1;
6324 inst
.operands
[i
].present
= 1;
6327 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6328 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6329 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6330 Case 10: VMOV.F32 <Sd>, #<imm>
6331 Case 11: VMOV.F64 <Dd>, #<imm> */
6332 inst
.operands
[i
].immisfloat
= 1;
6333 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6335 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6336 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6340 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6344 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6347 inst
.operands
[i
].reg
= val
;
6348 inst
.operands
[i
].isreg
= 1;
6349 inst
.operands
[i
++].present
= 1;
6351 if (skip_past_comma (&ptr
) == FAIL
)
6354 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6356 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6357 inst
.operands
[i
].reg
= val
;
6358 inst
.operands
[i
].isscalar
= 1;
6359 inst
.operands
[i
].present
= 1;
6360 inst
.operands
[i
].vectype
= optype
;
6362 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6364 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
++].present
= 1;
6369 if (skip_past_comma (&ptr
) == FAIL
)
6372 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6375 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6379 inst
.operands
[i
].reg
= val
;
6380 inst
.operands
[i
].isreg
= 1;
6381 inst
.operands
[i
].isvec
= 1;
6382 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6383 inst
.operands
[i
].vectype
= optype
;
6384 inst
.operands
[i
].present
= 1;
6386 if (rtype
== REG_TYPE_VFS
)
6390 if (skip_past_comma (&ptr
) == FAIL
)
6392 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6395 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6398 inst
.operands
[i
].reg
= val
;
6399 inst
.operands
[i
].isreg
= 1;
6400 inst
.operands
[i
].isvec
= 1;
6401 inst
.operands
[i
].issingle
= 1;
6402 inst
.operands
[i
].vectype
= optype
;
6403 inst
.operands
[i
].present
= 1;
6406 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6410 inst
.operands
[i
].reg
= val
;
6411 inst
.operands
[i
].isreg
= 1;
6412 inst
.operands
[i
].isvec
= 1;
6413 inst
.operands
[i
].issingle
= 1;
6414 inst
.operands
[i
].vectype
= optype
;
6415 inst
.operands
[i
].present
= 1;
6420 first_error (_("parse error"));
6424 /* Successfully parsed the operands. Update args. */
6430 first_error (_("expected comma"));
6434 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6438 /* Use this macro when the operand constraints are different
6439 for ARM and THUMB (e.g. ldrd). */
6440 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6441 ((arm_operand) | ((thumb_operand) << 16))
6443 /* Matcher codes for parse_operands. */
6444 enum operand_parse_code
6446 OP_stop
, /* end of line */
6448 OP_RR
, /* ARM register */
6449 OP_RRnpc
, /* ARM register, not r15 */
6450 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6451 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6452 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6453 optional trailing ! */
6454 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6455 OP_RCP
, /* Coprocessor number */
6456 OP_RCN
, /* Coprocessor register */
6457 OP_RF
, /* FPA register */
6458 OP_RVS
, /* VFP single precision register */
6459 OP_RVD
, /* VFP double precision register (0..15) */
6460 OP_RND
, /* Neon double precision register (0..31) */
6461 OP_RNQ
, /* Neon quad precision register */
6462 OP_RVSD
, /* VFP single or double precision register */
6463 OP_RNDQ
, /* Neon double or quad precision register */
6464 OP_RNSDQ
, /* Neon single, double or quad precision register */
6465 OP_RNSC
, /* Neon scalar D[X] */
6466 OP_RVC
, /* VFP control register */
6467 OP_RMF
, /* Maverick F register */
6468 OP_RMD
, /* Maverick D register */
6469 OP_RMFX
, /* Maverick FX register */
6470 OP_RMDX
, /* Maverick DX register */
6471 OP_RMAX
, /* Maverick AX register */
6472 OP_RMDS
, /* Maverick DSPSC register */
6473 OP_RIWR
, /* iWMMXt wR register */
6474 OP_RIWC
, /* iWMMXt wC register */
6475 OP_RIWG
, /* iWMMXt wCG register */
6476 OP_RXA
, /* XScale accumulator register */
6478 OP_REGLST
, /* ARM register list */
6479 OP_VRSLST
, /* VFP single-precision register list */
6480 OP_VRDLST
, /* VFP double-precision register list */
6481 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6482 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6483 OP_NSTRLST
, /* Neon element/structure list */
6485 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6486 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6487 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6488 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6489 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6490 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6491 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6492 OP_VMOV
, /* Neon VMOV operands. */
6493 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6494 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6495 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6497 OP_I0
, /* immediate zero */
6498 OP_I7
, /* immediate value 0 .. 7 */
6499 OP_I15
, /* 0 .. 15 */
6500 OP_I16
, /* 1 .. 16 */
6501 OP_I16z
, /* 0 .. 16 */
6502 OP_I31
, /* 0 .. 31 */
6503 OP_I31w
, /* 0 .. 31, optional trailing ! */
6504 OP_I32
, /* 1 .. 32 */
6505 OP_I32z
, /* 0 .. 32 */
6506 OP_I63
, /* 0 .. 63 */
6507 OP_I63s
, /* -64 .. 63 */
6508 OP_I64
, /* 1 .. 64 */
6509 OP_I64z
, /* 0 .. 64 */
6510 OP_I255
, /* 0 .. 255 */
6512 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6513 OP_I7b
, /* 0 .. 7 */
6514 OP_I15b
, /* 0 .. 15 */
6515 OP_I31b
, /* 0 .. 31 */
6517 OP_SH
, /* shifter operand */
6518 OP_SHG
, /* shifter operand with possible group relocation */
6519 OP_ADDR
, /* Memory address expression (any mode) */
6520 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6521 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6522 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6523 OP_EXP
, /* arbitrary expression */
6524 OP_EXPi
, /* same, with optional immediate prefix */
6525 OP_EXPr
, /* same, with optional relocation suffix */
6526 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6528 OP_CPSF
, /* CPS flags */
6529 OP_ENDI
, /* Endianness specifier */
6530 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6531 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6532 OP_COND
, /* conditional code */
6533 OP_TB
, /* Table branch. */
6535 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6537 OP_RRnpc_I0
, /* ARM register or literal 0 */
6538 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6539 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6540 OP_RF_IF
, /* FPA register or immediate */
6541 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6542 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6544 /* Optional operands. */
6545 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6546 OP_oI31b
, /* 0 .. 31 */
6547 OP_oI32b
, /* 1 .. 32 */
6548 OP_oI32z
, /* 0 .. 32 */
6549 OP_oIffffb
, /* 0 .. 65535 */
6550 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6552 OP_oRR
, /* ARM register */
6553 OP_oRRnpc
, /* ARM register, not the PC */
6554 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6555 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6556 OP_oRND
, /* Optional Neon double precision register */
6557 OP_oRNQ
, /* Optional Neon quad precision register */
6558 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6559 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6560 OP_oSHll
, /* LSL immediate */
6561 OP_oSHar
, /* ASR immediate */
6562 OP_oSHllar
, /* LSL or ASR immediate */
6563 OP_oROR
, /* ROR 0/8/16/24 */
6564 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6566 /* Some pre-defined mixed (ARM/THUMB) operands. */
6567 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6568 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6569 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6571 OP_FIRST_OPTIONAL
= OP_oI7b
6574 /* Generic instruction operand parser. This does no encoding and no
6575 semantic validation; it merely squirrels values away in the inst
6576 structure. Returns SUCCESS or FAIL depending on whether the
6577 specified grammar matched. */
6579 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6581 unsigned const int *upat
= pattern
;
6582 char *backtrack_pos
= 0;
6583 const char *backtrack_error
= 0;
6584 int i
, val
= 0, backtrack_index
= 0;
6585 enum arm_reg_type rtype
;
6586 parse_operand_result result
;
6587 unsigned int op_parse_code
;
6589 #define po_char_or_fail(chr) \
6592 if (skip_past_char (&str, chr) == FAIL) \
6597 #define po_reg_or_fail(regtype) \
6600 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6601 & inst.operands[i].vectype); \
6604 first_error (_(reg_expected_msgs[regtype])); \
6607 inst.operands[i].reg = val; \
6608 inst.operands[i].isreg = 1; \
6609 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6610 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6611 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6612 || rtype == REG_TYPE_VFD \
6613 || rtype == REG_TYPE_NQ); \
6617 #define po_reg_or_goto(regtype, label) \
6620 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6621 & inst.operands[i].vectype); \
6625 inst.operands[i].reg = val; \
6626 inst.operands[i].isreg = 1; \
6627 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6628 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6629 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6630 || rtype == REG_TYPE_VFD \
6631 || rtype == REG_TYPE_NQ); \
6635 #define po_imm_or_fail(min, max, popt) \
6638 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6640 inst.operands[i].imm = val; \
6644 #define po_scalar_or_goto(elsz, label) \
6647 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6650 inst.operands[i].reg = val; \
6651 inst.operands[i].isscalar = 1; \
6655 #define po_misc_or_fail(expr) \
6663 #define po_misc_or_fail_no_backtrack(expr) \
6667 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6668 backtrack_pos = 0; \
6669 if (result != PARSE_OPERAND_SUCCESS) \
6674 #define po_barrier_or_imm(str) \
6677 val = parse_barrier (&str); \
6678 if (val == FAIL && ! ISALPHA (*str)) \
6681 /* ISB can only take SY as an option. */ \
6682 || ((inst.instruction & 0xf0) == 0x60 \
6685 inst.error = _("invalid barrier type"); \
6686 backtrack_pos = 0; \
6692 skip_whitespace (str
);
6694 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6696 op_parse_code
= upat
[i
];
6697 if (op_parse_code
>= 1<<16)
6698 op_parse_code
= thumb
? (op_parse_code
>> 16)
6699 : (op_parse_code
& ((1<<16)-1));
6701 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6703 /* Remember where we are in case we need to backtrack. */
6704 gas_assert (!backtrack_pos
);
6705 backtrack_pos
= str
;
6706 backtrack_error
= inst
.error
;
6707 backtrack_index
= i
;
6710 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6711 po_char_or_fail (',');
6713 switch (op_parse_code
)
6721 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6722 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6723 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6724 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6725 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6726 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6728 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6730 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6732 /* Also accept generic coprocessor regs for unknown registers. */
6734 po_reg_or_fail (REG_TYPE_CN
);
6736 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6737 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6738 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6739 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6740 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6741 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6742 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6743 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6744 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6745 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6747 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6749 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6750 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6752 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6754 /* Neon scalar. Using an element size of 8 means that some invalid
6755 scalars are accepted here, so deal with those in later code. */
6756 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6760 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6763 po_imm_or_fail (0, 0, TRUE
);
6768 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6773 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6776 if (parse_ifimm_zero (&str
))
6777 inst
.operands
[i
].imm
= 0;
6781 = _("only floating point zero is allowed as immediate value");
6789 po_scalar_or_goto (8, try_rr
);
6792 po_reg_or_fail (REG_TYPE_RN
);
6798 po_scalar_or_goto (8, try_nsdq
);
6801 po_reg_or_fail (REG_TYPE_NSDQ
);
6807 po_scalar_or_goto (8, try_ndq
);
6810 po_reg_or_fail (REG_TYPE_NDQ
);
6816 po_scalar_or_goto (8, try_vfd
);
6819 po_reg_or_fail (REG_TYPE_VFD
);
6824 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6825 not careful then bad things might happen. */
6826 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6831 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6834 /* There's a possibility of getting a 64-bit immediate here, so
6835 we need special handling. */
6836 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6839 inst
.error
= _("immediate value is out of range");
6847 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6850 po_imm_or_fail (0, 63, TRUE
);
6855 po_char_or_fail ('[');
6856 po_reg_or_fail (REG_TYPE_RN
);
6857 po_char_or_fail (']');
6863 po_reg_or_fail (REG_TYPE_RN
);
6864 if (skip_past_char (&str
, '!') == SUCCESS
)
6865 inst
.operands
[i
].writeback
= 1;
6869 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6870 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6871 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6872 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6873 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6874 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6875 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6876 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6877 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6878 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6879 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6880 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6882 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6884 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6885 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6887 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6888 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6889 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6890 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6892 /* Immediate variants */
6894 po_char_or_fail ('{');
6895 po_imm_or_fail (0, 255, TRUE
);
6896 po_char_or_fail ('}');
6900 /* The expression parser chokes on a trailing !, so we have
6901 to find it first and zap it. */
6904 while (*s
&& *s
!= ',')
6909 inst
.operands
[i
].writeback
= 1;
6911 po_imm_or_fail (0, 31, TRUE
);
6919 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6924 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6929 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6931 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6933 val
= parse_reloc (&str
);
6936 inst
.error
= _("unrecognized relocation suffix");
6939 else if (val
!= BFD_RELOC_UNUSED
)
6941 inst
.operands
[i
].imm
= val
;
6942 inst
.operands
[i
].hasreloc
= 1;
6947 /* Operand for MOVW or MOVT. */
6949 po_misc_or_fail (parse_half (&str
));
6952 /* Register or expression. */
6953 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6954 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6956 /* Register or immediate. */
6957 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6958 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6960 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6962 if (!is_immediate_prefix (*str
))
6965 val
= parse_fpa_immediate (&str
);
6968 /* FPA immediates are encoded as registers 8-15.
6969 parse_fpa_immediate has already applied the offset. */
6970 inst
.operands
[i
].reg
= val
;
6971 inst
.operands
[i
].isreg
= 1;
6974 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6975 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6977 /* Two kinds of register. */
6980 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6982 || (rege
->type
!= REG_TYPE_MMXWR
6983 && rege
->type
!= REG_TYPE_MMXWC
6984 && rege
->type
!= REG_TYPE_MMXWCG
))
6986 inst
.error
= _("iWMMXt data or control register expected");
6989 inst
.operands
[i
].reg
= rege
->number
;
6990 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6996 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6998 || (rege
->type
!= REG_TYPE_MMXWC
6999 && rege
->type
!= REG_TYPE_MMXWCG
))
7001 inst
.error
= _("iWMMXt control register expected");
7004 inst
.operands
[i
].reg
= rege
->number
;
7005 inst
.operands
[i
].isreg
= 1;
7010 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7011 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7012 case OP_oROR
: val
= parse_ror (&str
); break;
7013 case OP_COND
: val
= parse_cond (&str
); break;
7014 case OP_oBARRIER_I15
:
7015 po_barrier_or_imm (str
); break;
7017 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7023 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7024 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7026 inst
.error
= _("Banked registers are not available with this "
7032 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7036 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7039 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7041 if (strncasecmp (str
, "APSR_", 5) == 0)
7048 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7049 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7050 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7051 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7052 default: found
= 16;
7056 inst
.operands
[i
].isvec
= 1;
7057 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7058 inst
.operands
[i
].reg
= REG_PC
;
7065 po_misc_or_fail (parse_tb (&str
));
7068 /* Register lists. */
7070 val
= parse_reg_list (&str
);
7073 inst
.operands
[i
].writeback
= 1;
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7083 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7087 /* Allow Q registers too. */
7088 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7093 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7095 inst
.operands
[i
].issingle
= 1;
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7105 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7106 &inst
.operands
[i
].vectype
);
7109 /* Addressing modes */
7111 po_misc_or_fail (parse_address (&str
, i
));
7115 po_misc_or_fail_no_backtrack (
7116 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7120 po_misc_or_fail_no_backtrack (
7121 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7125 po_misc_or_fail_no_backtrack (
7126 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7130 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7134 po_misc_or_fail_no_backtrack (
7135 parse_shifter_operand_group_reloc (&str
, i
));
7139 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7143 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7147 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7151 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7154 /* Various value-based sanity checks and shared operations. We
7155 do not signal immediate failures for the register constraints;
7156 this allows a syntax error to take precedence. */
7157 switch (op_parse_code
)
7165 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7166 inst
.error
= BAD_PC
;
7171 if (inst
.operands
[i
].isreg
)
7173 if (inst
.operands
[i
].reg
== REG_PC
)
7174 inst
.error
= BAD_PC
;
7175 else if (inst
.operands
[i
].reg
== REG_SP
)
7176 inst
.error
= BAD_SP
;
7181 if (inst
.operands
[i
].isreg
7182 && inst
.operands
[i
].reg
== REG_PC
7183 && (inst
.operands
[i
].writeback
|| thumb
))
7184 inst
.error
= BAD_PC
;
7193 case OP_oBARRIER_I15
:
7202 inst
.operands
[i
].imm
= val
;
7209 /* If we get here, this operand was successfully parsed. */
7210 inst
.operands
[i
].present
= 1;
7214 inst
.error
= BAD_ARGS
;
7219 /* The parse routine should already have set inst.error, but set a
7220 default here just in case. */
7222 inst
.error
= _("syntax error");
7226 /* Do not backtrack over a trailing optional argument that
7227 absorbed some text. We will only fail again, with the
7228 'garbage following instruction' error message, which is
7229 probably less helpful than the current one. */
7230 if (backtrack_index
== i
&& backtrack_pos
!= str
7231 && upat
[i
+1] == OP_stop
)
7234 inst
.error
= _("syntax error");
7238 /* Try again, skipping the optional argument at backtrack_pos. */
7239 str
= backtrack_pos
;
7240 inst
.error
= backtrack_error
;
7241 inst
.operands
[backtrack_index
].present
= 0;
7242 i
= backtrack_index
;
7246 /* Check that we have parsed all the arguments. */
7247 if (*str
!= '\0' && !inst
.error
)
7248 inst
.error
= _("garbage following instruction");
7250 return inst
.error
? FAIL
: SUCCESS
;
7253 #undef po_char_or_fail
7254 #undef po_reg_or_fail
7255 #undef po_reg_or_goto
7256 #undef po_imm_or_fail
7257 #undef po_scalar_or_fail
7258 #undef po_barrier_or_imm
7260 /* Shorthand macro for instruction encoding functions issuing errors. */
7261 #define constraint(expr, err) \
7272 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7273 instructions are unpredictable if these registers are used. This
7274 is the BadReg predicate in ARM's Thumb-2 documentation. */
7275 #define reject_bad_reg(reg) \
7277 if (reg == REG_SP || reg == REG_PC) \
7279 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7284 /* If REG is R13 (the stack pointer), warn that its use is
7286 #define warn_deprecated_sp(reg) \
7288 if (warn_on_deprecated && reg == REG_SP) \
7289 as_tsktsk (_("use of r13 is deprecated")); \
7292 /* Functions for operand encoding. ARM, then Thumb. */
7294 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7296 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7298 The only binary encoding difference is the Coprocessor number. Coprocessor
7299 9 is used for half-precision calculations or conversions. The format of the
7300 instruction is the same as the equivalent Coprocessor 10 instuction that
7301 exists for Single-Precision operation. */
7304 do_scalar_fp16_v82_encode (void)
7306 if (inst
.cond
!= COND_ALWAYS
)
7307 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7308 " the behaviour is UNPREDICTABLE"));
7309 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7312 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7313 mark_feature_used (&arm_ext_fp16
);
7316 /* If VAL can be encoded in the immediate field of an ARM instruction,
7317 return the encoded form. Otherwise, return FAIL. */
7320 encode_arm_immediate (unsigned int val
)
7327 for (i
= 2; i
< 32; i
+= 2)
7328 if ((a
= rotate_left (val
, i
)) <= 0xff)
7329 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7334 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7335 return the encoded form. Otherwise, return FAIL. */
7337 encode_thumb32_immediate (unsigned int val
)
7344 for (i
= 1; i
<= 24; i
++)
7347 if ((val
& ~(0xff << i
)) == 0)
7348 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7352 if (val
== ((a
<< 16) | a
))
7354 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7358 if (val
== ((a
<< 16) | a
))
7359 return 0x200 | (a
>> 8);
7363 /* Encode a VFP SP or DP register number into inst.instruction. */
7366 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7368 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7371 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7374 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7377 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7382 first_error (_("D register out of range for selected VFP version"));
7390 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7394 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7398 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7402 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7406 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7410 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7418 /* Encode a <shift> in an ARM-format instruction. The immediate,
7419 if any, is handled by md_apply_fix. */
7421 encode_arm_shift (int i
)
7423 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7424 inst
.instruction
|= SHIFT_ROR
<< 5;
7427 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7428 if (inst
.operands
[i
].immisreg
)
7430 inst
.instruction
|= SHIFT_BY_REG
;
7431 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7434 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7439 encode_arm_shifter_operand (int i
)
7441 if (inst
.operands
[i
].isreg
)
7443 inst
.instruction
|= inst
.operands
[i
].reg
;
7444 encode_arm_shift (i
);
7448 inst
.instruction
|= INST_IMMEDIATE
;
7449 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7450 inst
.instruction
|= inst
.operands
[i
].imm
;
7454 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7456 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7459 Generate an error if the operand is not a register. */
7460 constraint (!inst
.operands
[i
].isreg
,
7461 _("Instruction does not support =N addresses"));
7463 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7465 if (inst
.operands
[i
].preind
)
7469 inst
.error
= _("instruction does not accept preindexed addressing");
7472 inst
.instruction
|= PRE_INDEX
;
7473 if (inst
.operands
[i
].writeback
)
7474 inst
.instruction
|= WRITE_BACK
;
7477 else if (inst
.operands
[i
].postind
)
7479 gas_assert (inst
.operands
[i
].writeback
);
7481 inst
.instruction
|= WRITE_BACK
;
7483 else /* unindexed - only for coprocessor */
7485 inst
.error
= _("instruction does not accept unindexed addressing");
7489 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7490 && (((inst
.instruction
& 0x000f0000) >> 16)
7491 == ((inst
.instruction
& 0x0000f000) >> 12)))
7492 as_warn ((inst
.instruction
& LOAD_BIT
)
7493 ? _("destination register same as write-back base")
7494 : _("source register same as write-back base"));
7497 /* inst.operands[i] was set up by parse_address. Encode it into an
7498 ARM-format mode 2 load or store instruction. If is_t is true,
7499 reject forms that cannot be used with a T instruction (i.e. not
7502 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7504 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7506 encode_arm_addr_mode_common (i
, is_t
);
7508 if (inst
.operands
[i
].immisreg
)
7510 constraint ((inst
.operands
[i
].imm
== REG_PC
7511 || (is_pc
&& inst
.operands
[i
].writeback
)),
7513 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7514 inst
.instruction
|= inst
.operands
[i
].imm
;
7515 if (!inst
.operands
[i
].negative
)
7516 inst
.instruction
|= INDEX_UP
;
7517 if (inst
.operands
[i
].shifted
)
7519 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7520 inst
.instruction
|= SHIFT_ROR
<< 5;
7523 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7524 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7528 else /* immediate offset in inst.reloc */
7530 if (is_pc
&& !inst
.reloc
.pc_rel
)
7532 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7534 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7535 cannot use PC in addressing.
7536 PC cannot be used in writeback addressing, either. */
7537 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7540 /* Use of PC in str is deprecated for ARMv7. */
7541 if (warn_on_deprecated
7543 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7544 as_tsktsk (_("use of PC in this instruction is deprecated"));
7547 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7549 /* Prefer + for zero encoded value. */
7550 if (!inst
.operands
[i
].negative
)
7551 inst
.instruction
|= INDEX_UP
;
7552 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7557 /* inst.operands[i] was set up by parse_address. Encode it into an
7558 ARM-format mode 3 load or store instruction. Reject forms that
7559 cannot be used with such instructions. If is_t is true, reject
7560 forms that cannot be used with a T instruction (i.e. not
7563 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7565 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7567 inst
.error
= _("instruction does not accept scaled register index");
7571 encode_arm_addr_mode_common (i
, is_t
);
7573 if (inst
.operands
[i
].immisreg
)
7575 constraint ((inst
.operands
[i
].imm
== REG_PC
7576 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7578 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7580 inst
.instruction
|= inst
.operands
[i
].imm
;
7581 if (!inst
.operands
[i
].negative
)
7582 inst
.instruction
|= INDEX_UP
;
7584 else /* immediate offset in inst.reloc */
7586 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7587 && inst
.operands
[i
].writeback
),
7589 inst
.instruction
|= HWOFFSET_IMM
;
7590 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7592 /* Prefer + for zero encoded value. */
7593 if (!inst
.operands
[i
].negative
)
7594 inst
.instruction
|= INDEX_UP
;
7596 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7601 /* Write immediate bits [7:0] to the following locations:
7603 |28/24|23 19|18 16|15 4|3 0|
7604 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7606 This function is used by VMOV/VMVN/VORR/VBIC. */
7609 neon_write_immbits (unsigned immbits
)
7611 inst
.instruction
|= immbits
& 0xf;
7612 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7613 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7616 /* Invert low-order SIZE bits of XHI:XLO. */
7619 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7621 unsigned immlo
= xlo
? *xlo
: 0;
7622 unsigned immhi
= xhi
? *xhi
: 0;
7627 immlo
= (~immlo
) & 0xff;
7631 immlo
= (~immlo
) & 0xffff;
7635 immhi
= (~immhi
) & 0xffffffff;
7639 immlo
= (~immlo
) & 0xffffffff;
7653 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7657 neon_bits_same_in_bytes (unsigned imm
)
7659 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7660 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7661 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7662 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7665 /* For immediate of above form, return 0bABCD. */
7668 neon_squash_bits (unsigned imm
)
7670 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7671 | ((imm
& 0x01000000) >> 21);
7674 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7677 neon_qfloat_bits (unsigned imm
)
7679 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7682 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7683 the instruction. *OP is passed as the initial value of the op field, and
7684 may be set to a different value depending on the constant (i.e.
7685 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7686 MVN). If the immediate looks like a repeated pattern then also
7687 try smaller element sizes. */
7690 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7691 unsigned *immbits
, int *op
, int size
,
7692 enum neon_el_type type
)
7694 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7696 if (type
== NT_float
&& !float_p
)
7699 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7701 if (size
!= 32 || *op
== 1)
7703 *immbits
= neon_qfloat_bits (immlo
);
7709 if (neon_bits_same_in_bytes (immhi
)
7710 && neon_bits_same_in_bytes (immlo
))
7714 *immbits
= (neon_squash_bits (immhi
) << 4)
7715 | neon_squash_bits (immlo
);
7726 if (immlo
== (immlo
& 0x000000ff))
7731 else if (immlo
== (immlo
& 0x0000ff00))
7733 *immbits
= immlo
>> 8;
7736 else if (immlo
== (immlo
& 0x00ff0000))
7738 *immbits
= immlo
>> 16;
7741 else if (immlo
== (immlo
& 0xff000000))
7743 *immbits
= immlo
>> 24;
7746 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7748 *immbits
= (immlo
>> 8) & 0xff;
7751 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7753 *immbits
= (immlo
>> 16) & 0xff;
7757 if ((immlo
& 0xffff) != (immlo
>> 16))
7764 if (immlo
== (immlo
& 0x000000ff))
7769 else if (immlo
== (immlo
& 0x0000ff00))
7771 *immbits
= immlo
>> 8;
7775 if ((immlo
& 0xff) != (immlo
>> 8))
7780 if (immlo
== (immlo
& 0x000000ff))
7782 /* Don't allow MVN with 8-bit immediate. */
7792 #if defined BFD_HOST_64_BIT
7793 /* Returns TRUE if double precision value V may be cast
7794 to single precision without loss of accuracy. */
7797 is_double_a_single (bfd_int64_t v
)
7799 int exp
= (int)((v
>> 52) & 0x7FF);
7800 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7802 return (exp
== 0 || exp
== 0x7FF
7803 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7804 && (mantissa
& 0x1FFFFFFFl
) == 0;
7807 /* Returns a double precision value casted to single precision
7808 (ignoring the least significant bits in exponent and mantissa). */
7811 double_to_single (bfd_int64_t v
)
7813 int sign
= (int) ((v
>> 63) & 1l);
7814 int exp
= (int) ((v
>> 52) & 0x7FF);
7815 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7821 exp
= exp
- 1023 + 127;
7830 /* No denormalized numbers. */
7836 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7838 #endif /* BFD_HOST_64_BIT */
7847 static void do_vfp_nsyn_opcode (const char *);
7849 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7850 Determine whether it can be performed with a move instruction; if
7851 it can, convert inst.instruction to that move instruction and
7852 return TRUE; if it can't, convert inst.instruction to a literal-pool
7853 load and return FALSE. If this is not a valid thing to do in the
7854 current context, set inst.error and return TRUE.
7856 inst.operands[i] describes the destination register. */
7859 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7862 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7863 bfd_boolean arm_p
= (t
== CONST_ARM
);
7866 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7870 if ((inst
.instruction
& tbit
) == 0)
7872 inst
.error
= _("invalid pseudo operation");
7876 if (inst
.reloc
.exp
.X_op
!= O_constant
7877 && inst
.reloc
.exp
.X_op
!= O_symbol
7878 && inst
.reloc
.exp
.X_op
!= O_big
)
7880 inst
.error
= _("constant expression expected");
7884 if (inst
.reloc
.exp
.X_op
== O_constant
7885 || inst
.reloc
.exp
.X_op
== O_big
)
7887 #if defined BFD_HOST_64_BIT
7892 if (inst
.reloc
.exp
.X_op
== O_big
)
7894 LITTLENUM_TYPE w
[X_PRECISION
];
7897 if (inst
.reloc
.exp
.X_add_number
== -1)
7899 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7901 /* FIXME: Should we check words w[2..5] ? */
7906 #if defined BFD_HOST_64_BIT
7908 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7909 << LITTLENUM_NUMBER_OF_BITS
)
7910 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7911 << LITTLENUM_NUMBER_OF_BITS
)
7912 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7913 << LITTLENUM_NUMBER_OF_BITS
)
7914 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7916 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7917 | (l
[0] & LITTLENUM_MASK
);
7921 v
= inst
.reloc
.exp
.X_add_number
;
7923 if (!inst
.operands
[i
].issingle
)
7927 /* This can be encoded only for a low register. */
7928 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7930 /* This can be done with a mov(1) instruction. */
7931 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7932 inst
.instruction
|= v
;
7936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7937 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7939 /* Check if on thumb2 it can be done with a mov.w, mvn or
7940 movw instruction. */
7941 unsigned int newimm
;
7942 bfd_boolean isNegated
;
7944 newimm
= encode_thumb32_immediate (v
);
7945 if (newimm
!= (unsigned int) FAIL
)
7949 newimm
= encode_thumb32_immediate (~v
);
7950 if (newimm
!= (unsigned int) FAIL
)
7954 /* The number can be loaded with a mov.w or mvn
7956 if (newimm
!= (unsigned int) FAIL
7957 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7959 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7960 | (inst
.operands
[i
].reg
<< 8));
7961 /* Change to MOVN. */
7962 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7963 inst
.instruction
|= (newimm
& 0x800) << 15;
7964 inst
.instruction
|= (newimm
& 0x700) << 4;
7965 inst
.instruction
|= (newimm
& 0x0ff);
7968 /* The number can be loaded with a movw instruction. */
7969 else if ((v
& ~0xFFFF) == 0
7970 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7972 int imm
= v
& 0xFFFF;
7974 inst
.instruction
= 0xf2400000; /* MOVW. */
7975 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7976 inst
.instruction
|= (imm
& 0xf000) << 4;
7977 inst
.instruction
|= (imm
& 0x0800) << 15;
7978 inst
.instruction
|= (imm
& 0x0700) << 4;
7979 inst
.instruction
|= (imm
& 0x00ff);
7986 int value
= encode_arm_immediate (v
);
7990 /* This can be done with a mov instruction. */
7991 inst
.instruction
&= LITERAL_MASK
;
7992 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7993 inst
.instruction
|= value
& 0xfff;
7997 value
= encode_arm_immediate (~ v
);
8000 /* This can be done with a mvn instruction. */
8001 inst
.instruction
&= LITERAL_MASK
;
8002 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8003 inst
.instruction
|= value
& 0xfff;
8007 else if (t
== CONST_VEC
)
8010 unsigned immbits
= 0;
8011 unsigned immlo
= inst
.operands
[1].imm
;
8012 unsigned immhi
= inst
.operands
[1].regisimm
8013 ? inst
.operands
[1].reg
8014 : inst
.reloc
.exp
.X_unsigned
8016 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8017 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8018 &op
, 64, NT_invtype
);
8022 neon_invert_size (&immlo
, &immhi
, 64);
8024 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8025 &op
, 64, NT_invtype
);
8030 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8036 /* Fill other bits in vmov encoding for both thumb and arm. */
8038 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8040 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8041 neon_write_immbits (immbits
);
8049 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8050 if (inst
.operands
[i
].issingle
8051 && is_quarter_float (inst
.operands
[1].imm
)
8052 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8054 inst
.operands
[1].imm
=
8055 neon_qfloat_bits (v
);
8056 do_vfp_nsyn_opcode ("fconsts");
8060 /* If our host does not support a 64-bit type then we cannot perform
8061 the following optimization. This mean that there will be a
8062 discrepancy between the output produced by an assembler built for
8063 a 32-bit-only host and the output produced from a 64-bit host, but
8064 this cannot be helped. */
8065 #if defined BFD_HOST_64_BIT
8066 else if (!inst
.operands
[1].issingle
8067 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8069 if (is_double_a_single (v
)
8070 && is_quarter_float (double_to_single (v
)))
8072 inst
.operands
[1].imm
=
8073 neon_qfloat_bits (double_to_single (v
));
8074 do_vfp_nsyn_opcode ("fconstd");
8082 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8083 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8086 inst
.operands
[1].reg
= REG_PC
;
8087 inst
.operands
[1].isreg
= 1;
8088 inst
.operands
[1].preind
= 1;
8089 inst
.reloc
.pc_rel
= 1;
8090 inst
.reloc
.type
= (thumb_p
8091 ? BFD_RELOC_ARM_THUMB_OFFSET
8093 ? BFD_RELOC_ARM_HWLITERAL
8094 : BFD_RELOC_ARM_LITERAL
));
8098 /* inst.operands[i] was set up by parse_address. Encode it into an
8099 ARM-format instruction. Reject all forms which cannot be encoded
8100 into a coprocessor load/store instruction. If wb_ok is false,
8101 reject use of writeback; if unind_ok is false, reject use of
8102 unindexed addressing. If reloc_override is not 0, use it instead
8103 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8104 (in which case it is preserved). */
8107 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8109 if (!inst
.operands
[i
].isreg
)
8112 if (! inst
.operands
[0].isvec
)
8114 inst
.error
= _("invalid co-processor operand");
8117 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8121 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8123 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8125 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8127 gas_assert (!inst
.operands
[i
].writeback
);
8130 inst
.error
= _("instruction does not support unindexed addressing");
8133 inst
.instruction
|= inst
.operands
[i
].imm
;
8134 inst
.instruction
|= INDEX_UP
;
8138 if (inst
.operands
[i
].preind
)
8139 inst
.instruction
|= PRE_INDEX
;
8141 if (inst
.operands
[i
].writeback
)
8143 if (inst
.operands
[i
].reg
== REG_PC
)
8145 inst
.error
= _("pc may not be used with write-back");
8150 inst
.error
= _("instruction does not support writeback");
8153 inst
.instruction
|= WRITE_BACK
;
8157 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8158 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8159 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8160 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8163 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8165 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8168 /* Prefer + for zero encoded value. */
8169 if (!inst
.operands
[i
].negative
)
8170 inst
.instruction
|= INDEX_UP
;
8175 /* Functions for instruction encoding, sorted by sub-architecture.
8176 First some generics; their names are taken from the conventional
8177 bit positions for register arguments in ARM format instructions. */
8187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8200 inst
.instruction
|= inst
.operands
[1].reg
;
8206 inst
.instruction
|= inst
.operands
[0].reg
;
8207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8213 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8214 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8220 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8221 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8227 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8232 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8234 if (ARM_CPU_IS_ANY (cpu_variant
))
8236 as_tsktsk ("%s", msg
);
8239 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8251 unsigned Rn
= inst
.operands
[2].reg
;
8252 /* Enforce restrictions on SWP instruction. */
8253 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8255 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8256 _("Rn must not overlap other operands"));
8258 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8260 if (!check_obsolete (&arm_ext_v8
,
8261 _("swp{b} use is obsoleted for ARMv8 and later"))
8262 && warn_on_deprecated
8263 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8264 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8268 inst
.instruction
|= inst
.operands
[1].reg
;
8269 inst
.instruction
|= Rn
<< 16;
8275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8276 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8277 inst
.instruction
|= inst
.operands
[2].reg
;
8283 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8284 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8285 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8286 || inst
.reloc
.exp
.X_add_number
!= 0),
8288 inst
.instruction
|= inst
.operands
[0].reg
;
8289 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8290 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8296 inst
.instruction
|= inst
.operands
[0].imm
;
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8306 /* ARM instructions, in alphabetical order by function name (except
8307 that wrapper functions appear immediately after the function they
8310 /* This is a pseudo-op of the form "adr rd, label" to be converted
8311 into a relative address of the form "add rd, pc, #label-.-8". */
8316 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8318 /* Frag hacking will turn this into a sub instruction if the offset turns
8319 out to be negative. */
8320 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8321 inst
.reloc
.pc_rel
= 1;
8322 inst
.reloc
.exp
.X_add_number
-= 8;
8325 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8326 into a relative address of the form:
8327 add rd, pc, #low(label-.-8)"
8328 add rd, rd, #high(label-.-8)" */
8333 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8335 /* Frag hacking will turn this into a sub instruction if the offset turns
8336 out to be negative. */
8337 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8338 inst
.reloc
.pc_rel
= 1;
8339 inst
.size
= INSN_SIZE
* 2;
8340 inst
.reloc
.exp
.X_add_number
-= 8;
8346 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8347 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8349 if (!inst
.operands
[1].present
)
8350 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8353 encode_arm_shifter_operand (2);
8359 if (inst
.operands
[0].present
)
8360 inst
.instruction
|= inst
.operands
[0].imm
;
8362 inst
.instruction
|= 0xf;
8368 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8369 constraint (msb
> 32, _("bit-field extends past end of register"));
8370 /* The instruction encoding stores the LSB and MSB,
8371 not the LSB and width. */
8372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8373 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8374 inst
.instruction
|= (msb
- 1) << 16;
8382 /* #0 in second position is alternative syntax for bfc, which is
8383 the same instruction but with REG_PC in the Rm field. */
8384 if (!inst
.operands
[1].isreg
)
8385 inst
.operands
[1].reg
= REG_PC
;
8387 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8388 constraint (msb
> 32, _("bit-field extends past end of register"));
8389 /* The instruction encoding stores the LSB and MSB,
8390 not the LSB and width. */
8391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8392 inst
.instruction
|= inst
.operands
[1].reg
;
8393 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8394 inst
.instruction
|= (msb
- 1) << 16;
8400 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8401 _("bit-field extends past end of register"));
8402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8403 inst
.instruction
|= inst
.operands
[1].reg
;
8404 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8405 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8408 /* ARM V5 breakpoint instruction (argument parse)
8409 BKPT <16 bit unsigned immediate>
8410 Instruction is not conditional.
8411 The bit pattern given in insns[] has the COND_ALWAYS condition,
8412 and it is an error if the caller tried to override that. */
8417 /* Top 12 of 16 bits to bits 19:8. */
8418 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8420 /* Bottom 4 of 16 bits to bits 3:0. */
8421 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8425 encode_branch (int default_reloc
)
8427 if (inst
.operands
[0].hasreloc
)
8429 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8430 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8431 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8432 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8433 ? BFD_RELOC_ARM_PLT32
8434 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8437 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8438 inst
.reloc
.pc_rel
= 1;
8445 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8446 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8449 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8456 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8458 if (inst
.cond
== COND_ALWAYS
)
8459 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8461 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8465 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8468 /* ARM V5 branch-link-exchange instruction (argument parse)
8469 BLX <target_addr> ie BLX(1)
8470 BLX{<condition>} <Rm> ie BLX(2)
8471 Unfortunately, there are two different opcodes for this mnemonic.
8472 So, the insns[].value is not used, and the code here zaps values
8473 into inst.instruction.
8474 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8479 if (inst
.operands
[0].isreg
)
8481 /* Arg is a register; the opcode provided by insns[] is correct.
8482 It is not illegal to do "blx pc", just useless. */
8483 if (inst
.operands
[0].reg
== REG_PC
)
8484 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8486 inst
.instruction
|= inst
.operands
[0].reg
;
8490 /* Arg is an address; this instruction cannot be executed
8491 conditionally, and the opcode must be adjusted.
8492 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8493 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8494 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8495 inst
.instruction
= 0xfa000000;
8496 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8503 bfd_boolean want_reloc
;
8505 if (inst
.operands
[0].reg
== REG_PC
)
8506 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8508 inst
.instruction
|= inst
.operands
[0].reg
;
8509 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8510 it is for ARMv4t or earlier. */
8511 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8512 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8516 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8521 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8525 /* ARM v5TEJ. Jump to Jazelle code. */
8530 if (inst
.operands
[0].reg
== REG_PC
)
8531 as_tsktsk (_("use of r15 in bxj is not really useful"));
8533 inst
.instruction
|= inst
.operands
[0].reg
;
8536 /* Co-processor data operation:
8537 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8538 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8542 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8543 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8544 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8545 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8546 inst
.instruction
|= inst
.operands
[4].reg
;
8547 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8553 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8554 encode_arm_shifter_operand (1);
8557 /* Transfer between coprocessor and ARM registers.
8558 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8563 No special properties. */
8565 struct deprecated_coproc_regs_s
8572 arm_feature_set deprecated
;
8573 arm_feature_set obsoleted
;
8574 const char *dep_msg
;
8575 const char *obs_msg
;
8578 #define DEPR_ACCESS_V8 \
8579 N_("This coprocessor register access is deprecated in ARMv8")
8581 /* Table of all deprecated coprocessor registers. */
8582 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8584 {15, 0, 7, 10, 5, /* CP15DMB. */
8585 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8586 DEPR_ACCESS_V8
, NULL
},
8587 {15, 0, 7, 10, 4, /* CP15DSB. */
8588 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8589 DEPR_ACCESS_V8
, NULL
},
8590 {15, 0, 7, 5, 4, /* CP15ISB. */
8591 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8592 DEPR_ACCESS_V8
, NULL
},
8593 {14, 6, 1, 0, 0, /* TEEHBR. */
8594 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8595 DEPR_ACCESS_V8
, NULL
},
8596 {14, 6, 0, 0, 0, /* TEECR. */
8597 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8598 DEPR_ACCESS_V8
, NULL
},
8601 #undef DEPR_ACCESS_V8
8603 static const size_t deprecated_coproc_reg_count
=
8604 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8612 Rd
= inst
.operands
[2].reg
;
8615 if (inst
.instruction
== 0xee000010
8616 || inst
.instruction
== 0xfe000010)
8618 reject_bad_reg (Rd
);
8621 constraint (Rd
== REG_SP
, BAD_SP
);
8626 if (inst
.instruction
== 0xe000010)
8627 constraint (Rd
== REG_PC
, BAD_PC
);
8630 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8632 const struct deprecated_coproc_regs_s
*r
=
8633 deprecated_coproc_regs
+ i
;
8635 if (inst
.operands
[0].reg
== r
->cp
8636 && inst
.operands
[1].imm
== r
->opc1
8637 && inst
.operands
[3].reg
== r
->crn
8638 && inst
.operands
[4].reg
== r
->crm
8639 && inst
.operands
[5].imm
== r
->opc2
)
8641 if (! ARM_CPU_IS_ANY (cpu_variant
)
8642 && warn_on_deprecated
8643 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8644 as_tsktsk ("%s", r
->dep_msg
);
8648 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8649 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8650 inst
.instruction
|= Rd
<< 12;
8651 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8652 inst
.instruction
|= inst
.operands
[4].reg
;
8653 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8656 /* Transfer between coprocessor register and pair of ARM registers.
8657 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8662 Two XScale instructions are special cases of these:
8664 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8665 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8667 Result unpredictable if Rd or Rn is R15. */
8674 Rd
= inst
.operands
[2].reg
;
8675 Rn
= inst
.operands
[3].reg
;
8679 reject_bad_reg (Rd
);
8680 reject_bad_reg (Rn
);
8684 constraint (Rd
== REG_PC
, BAD_PC
);
8685 constraint (Rn
== REG_PC
, BAD_PC
);
8688 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8689 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8690 inst
.instruction
|= Rd
<< 12;
8691 inst
.instruction
|= Rn
<< 16;
8692 inst
.instruction
|= inst
.operands
[4].reg
;
8698 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8699 if (inst
.operands
[1].present
)
8701 inst
.instruction
|= CPSI_MMOD
;
8702 inst
.instruction
|= inst
.operands
[1].imm
;
8709 inst
.instruction
|= inst
.operands
[0].imm
;
8715 unsigned Rd
, Rn
, Rm
;
8717 Rd
= inst
.operands
[0].reg
;
8718 Rn
= (inst
.operands
[1].present
8719 ? inst
.operands
[1].reg
: Rd
);
8720 Rm
= inst
.operands
[2].reg
;
8722 constraint ((Rd
== REG_PC
), BAD_PC
);
8723 constraint ((Rn
== REG_PC
), BAD_PC
);
8724 constraint ((Rm
== REG_PC
), BAD_PC
);
8726 inst
.instruction
|= Rd
<< 16;
8727 inst
.instruction
|= Rn
<< 0;
8728 inst
.instruction
|= Rm
<< 8;
8734 /* There is no IT instruction in ARM mode. We
8735 process it to do the validation as if in
8736 thumb mode, just in case the code gets
8737 assembled for thumb using the unified syntax. */
8742 set_it_insn_type (IT_INSN
);
8743 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8744 now_it
.cc
= inst
.operands
[0].imm
;
8748 /* If there is only one register in the register list,
8749 then return its register number. Otherwise return -1. */
8751 only_one_reg_in_list (int range
)
8753 int i
= ffs (range
) - 1;
8754 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8758 encode_ldmstm(int from_push_pop_mnem
)
8760 int base_reg
= inst
.operands
[0].reg
;
8761 int range
= inst
.operands
[1].imm
;
8764 inst
.instruction
|= base_reg
<< 16;
8765 inst
.instruction
|= range
;
8767 if (inst
.operands
[1].writeback
)
8768 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8770 if (inst
.operands
[0].writeback
)
8772 inst
.instruction
|= WRITE_BACK
;
8773 /* Check for unpredictable uses of writeback. */
8774 if (inst
.instruction
& LOAD_BIT
)
8776 /* Not allowed in LDM type 2. */
8777 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8778 && ((range
& (1 << REG_PC
)) == 0))
8779 as_warn (_("writeback of base register is UNPREDICTABLE"));
8780 /* Only allowed if base reg not in list for other types. */
8781 else if (range
& (1 << base_reg
))
8782 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8786 /* Not allowed for type 2. */
8787 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8788 as_warn (_("writeback of base register is UNPREDICTABLE"));
8789 /* Only allowed if base reg not in list, or first in list. */
8790 else if ((range
& (1 << base_reg
))
8791 && (range
& ((1 << base_reg
) - 1)))
8792 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8796 /* If PUSH/POP has only one register, then use the A2 encoding. */
8797 one_reg
= only_one_reg_in_list (range
);
8798 if (from_push_pop_mnem
&& one_reg
>= 0)
8800 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8802 inst
.instruction
&= A_COND_MASK
;
8803 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8804 inst
.instruction
|= one_reg
<< 12;
8811 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8814 /* ARMv5TE load-consecutive (argument parse)
8823 constraint (inst
.operands
[0].reg
% 2 != 0,
8824 _("first transfer register must be even"));
8825 constraint (inst
.operands
[1].present
8826 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8827 _("can only transfer two consecutive registers"));
8828 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8829 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8831 if (!inst
.operands
[1].present
)
8832 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8834 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8835 register and the first register written; we have to diagnose
8836 overlap between the base and the second register written here. */
8838 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8839 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8840 as_warn (_("base register written back, and overlaps "
8841 "second transfer register"));
8843 if (!(inst
.instruction
& V4_STR_BIT
))
8845 /* For an index-register load, the index register must not overlap the
8846 destination (even if not write-back). */
8847 if (inst
.operands
[2].immisreg
8848 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8849 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8850 as_warn (_("index register overlaps transfer register"));
8852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8853 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8859 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8860 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8861 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8862 || inst
.operands
[1].negative
8863 /* This can arise if the programmer has written
8865 or if they have mistakenly used a register name as the last
8868 It is very difficult to distinguish between these two cases
8869 because "rX" might actually be a label. ie the register
8870 name has been occluded by a symbol of the same name. So we
8871 just generate a general 'bad addressing mode' type error
8872 message and leave it up to the programmer to discover the
8873 true cause and fix their mistake. */
8874 || (inst
.operands
[1].reg
== REG_PC
),
8877 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8878 || inst
.reloc
.exp
.X_add_number
!= 0,
8879 _("offset must be zero in ARM encoding"));
8881 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8884 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8885 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8891 constraint (inst
.operands
[0].reg
% 2 != 0,
8892 _("even register required"));
8893 constraint (inst
.operands
[1].present
8894 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8895 _("can only load two consecutive registers"));
8896 /* If op 1 were present and equal to PC, this function wouldn't
8897 have been called in the first place. */
8898 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8900 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8901 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8904 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8905 which is not a multiple of four is UNPREDICTABLE. */
8907 check_ldr_r15_aligned (void)
8909 constraint (!(inst
.operands
[1].immisreg
)
8910 && (inst
.operands
[0].reg
== REG_PC
8911 && inst
.operands
[1].reg
== REG_PC
8912 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8913 _("ldr to register 15 must be 4-byte alligned"));
8919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8920 if (!inst
.operands
[1].isreg
)
8921 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8923 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8924 check_ldr_r15_aligned ();
8930 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8932 if (inst
.operands
[1].preind
)
8934 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8935 || inst
.reloc
.exp
.X_add_number
!= 0,
8936 _("this instruction requires a post-indexed address"));
8938 inst
.operands
[1].preind
= 0;
8939 inst
.operands
[1].postind
= 1;
8940 inst
.operands
[1].writeback
= 1;
8942 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8943 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8946 /* Halfword and signed-byte load/store operations. */
8951 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8953 if (!inst
.operands
[1].isreg
)
8954 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8956 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8962 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8964 if (inst
.operands
[1].preind
)
8966 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8967 || inst
.reloc
.exp
.X_add_number
!= 0,
8968 _("this instruction requires a post-indexed address"));
8970 inst
.operands
[1].preind
= 0;
8971 inst
.operands
[1].postind
= 1;
8972 inst
.operands
[1].writeback
= 1;
8974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8975 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8978 /* Co-processor register load/store.
8979 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8983 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8984 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8985 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8991 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8992 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8993 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8994 && !(inst
.instruction
& 0x00400000))
8995 as_tsktsk (_("Rd and Rm should be different in mla"));
8997 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8998 inst
.instruction
|= inst
.operands
[1].reg
;
8999 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9000 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9006 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9007 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9010 encode_arm_shifter_operand (1);
9013 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9020 top
= (inst
.instruction
& 0x00400000) != 0;
9021 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9022 _(":lower16: not allowed this instruction"));
9023 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9024 _(":upper16: not allowed instruction"));
9025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9026 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9028 imm
= inst
.reloc
.exp
.X_add_number
;
9029 /* The value is in two pieces: 0:11, 16:19. */
9030 inst
.instruction
|= (imm
& 0x00000fff);
9031 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9036 do_vfp_nsyn_mrs (void)
9038 if (inst
.operands
[0].isvec
)
9040 if (inst
.operands
[1].reg
!= 1)
9041 first_error (_("operand 1 must be FPSCR"));
9042 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9043 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9044 do_vfp_nsyn_opcode ("fmstat");
9046 else if (inst
.operands
[1].isvec
)
9047 do_vfp_nsyn_opcode ("fmrx");
9055 do_vfp_nsyn_msr (void)
9057 if (inst
.operands
[0].isvec
)
9058 do_vfp_nsyn_opcode ("fmxr");
9068 unsigned Rt
= inst
.operands
[0].reg
;
9070 if (thumb_mode
&& Rt
== REG_SP
)
9072 inst
.error
= BAD_SP
;
9076 /* APSR_ sets isvec. All other refs to PC are illegal. */
9077 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9079 inst
.error
= BAD_PC
;
9083 /* If we get through parsing the register name, we just insert the number
9084 generated into the instruction without further validation. */
9085 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9086 inst
.instruction
|= (Rt
<< 12);
9092 unsigned Rt
= inst
.operands
[1].reg
;
9095 reject_bad_reg (Rt
);
9096 else if (Rt
== REG_PC
)
9098 inst
.error
= BAD_PC
;
9102 /* If we get through parsing the register name, we just insert the number
9103 generated into the instruction without further validation. */
9104 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9105 inst
.instruction
|= (Rt
<< 12);
9113 if (do_vfp_nsyn_mrs () == SUCCESS
)
9116 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9119 if (inst
.operands
[1].isreg
)
9121 br
= inst
.operands
[1].reg
;
9122 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9123 as_bad (_("bad register for mrs"));
9127 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9128 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9130 _("'APSR', 'CPSR' or 'SPSR' expected"));
9131 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9134 inst
.instruction
|= br
;
9137 /* Two possible forms:
9138 "{C|S}PSR_<field>, Rm",
9139 "{C|S}PSR_f, #expression". */
9144 if (do_vfp_nsyn_msr () == SUCCESS
)
9147 inst
.instruction
|= inst
.operands
[0].imm
;
9148 if (inst
.operands
[1].isreg
)
9149 inst
.instruction
|= inst
.operands
[1].reg
;
9152 inst
.instruction
|= INST_IMMEDIATE
;
9153 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9154 inst
.reloc
.pc_rel
= 0;
9161 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9163 if (!inst
.operands
[2].present
)
9164 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9165 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9166 inst
.instruction
|= inst
.operands
[1].reg
;
9167 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9169 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9170 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9171 as_tsktsk (_("Rd and Rm should be different in mul"));
9174 /* Long Multiply Parser
9175 UMULL RdLo, RdHi, Rm, Rs
9176 SMULL RdLo, RdHi, Rm, Rs
9177 UMLAL RdLo, RdHi, Rm, Rs
9178 SMLAL RdLo, RdHi, Rm, Rs. */
9183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9185 inst
.instruction
|= inst
.operands
[2].reg
;
9186 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9188 /* rdhi and rdlo must be different. */
9189 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9190 as_tsktsk (_("rdhi and rdlo must be different"));
9192 /* rdhi, rdlo and rm must all be different before armv6. */
9193 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9194 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9195 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9196 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9202 if (inst
.operands
[0].present
9203 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9205 /* Architectural NOP hints are CPSR sets with no bits selected. */
9206 inst
.instruction
&= 0xf0000000;
9207 inst
.instruction
|= 0x0320f000;
9208 if (inst
.operands
[0].present
)
9209 inst
.instruction
|= inst
.operands
[0].imm
;
9213 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9214 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9215 Condition defaults to COND_ALWAYS.
9216 Error if Rd, Rn or Rm are R15. */
9221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9222 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9223 inst
.instruction
|= inst
.operands
[2].reg
;
9224 if (inst
.operands
[3].present
)
9225 encode_arm_shift (3);
9228 /* ARM V6 PKHTB (Argument Parse). */
9233 if (!inst
.operands
[3].present
)
9235 /* If the shift specifier is omitted, turn the instruction
9236 into pkhbt rd, rm, rn. */
9237 inst
.instruction
&= 0xfff00010;
9238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9239 inst
.instruction
|= inst
.operands
[1].reg
;
9240 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9246 inst
.instruction
|= inst
.operands
[2].reg
;
9247 encode_arm_shift (3);
9251 /* ARMv5TE: Preload-Cache
9252 MP Extensions: Preload for write
9256 Syntactically, like LDR with B=1, W=0, L=1. */
9261 constraint (!inst
.operands
[0].isreg
,
9262 _("'[' expected after PLD mnemonic"));
9263 constraint (inst
.operands
[0].postind
,
9264 _("post-indexed expression used in preload instruction"));
9265 constraint (inst
.operands
[0].writeback
,
9266 _("writeback used in preload instruction"));
9267 constraint (!inst
.operands
[0].preind
,
9268 _("unindexed addressing used in preload instruction"));
9269 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9272 /* ARMv7: PLI <addr_mode> */
9276 constraint (!inst
.operands
[0].isreg
,
9277 _("'[' expected after PLI mnemonic"));
9278 constraint (inst
.operands
[0].postind
,
9279 _("post-indexed expression used in preload instruction"));
9280 constraint (inst
.operands
[0].writeback
,
9281 _("writeback used in preload instruction"));
9282 constraint (!inst
.operands
[0].preind
,
9283 _("unindexed addressing used in preload instruction"));
9284 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9285 inst
.instruction
&= ~PRE_INDEX
;
9291 constraint (inst
.operands
[0].writeback
,
9292 _("push/pop do not support {reglist}^"));
9293 inst
.operands
[1] = inst
.operands
[0];
9294 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9295 inst
.operands
[0].isreg
= 1;
9296 inst
.operands
[0].writeback
= 1;
9297 inst
.operands
[0].reg
= REG_SP
;
9298 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9301 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9302 word at the specified address and the following word
9304 Unconditionally executed.
9305 Error if Rn is R15. */
9310 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9311 if (inst
.operands
[0].writeback
)
9312 inst
.instruction
|= WRITE_BACK
;
9315 /* ARM V6 ssat (argument parse). */
9320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9321 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9322 inst
.instruction
|= inst
.operands
[2].reg
;
9324 if (inst
.operands
[3].present
)
9325 encode_arm_shift (3);
9328 /* ARM V6 usat (argument parse). */
9333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9334 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9335 inst
.instruction
|= inst
.operands
[2].reg
;
9337 if (inst
.operands
[3].present
)
9338 encode_arm_shift (3);
9341 /* ARM V6 ssat16 (argument parse). */
9346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9347 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9348 inst
.instruction
|= inst
.operands
[2].reg
;
9354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9355 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9356 inst
.instruction
|= inst
.operands
[2].reg
;
9359 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9360 preserving the other bits.
9362 setend <endian_specifier>, where <endian_specifier> is either
9368 if (warn_on_deprecated
9369 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9370 as_tsktsk (_("setend use is deprecated for ARMv8"));
9372 if (inst
.operands
[0].imm
)
9373 inst
.instruction
|= 0x200;
9379 unsigned int Rm
= (inst
.operands
[1].present
9380 ? inst
.operands
[1].reg
9381 : inst
.operands
[0].reg
);
9383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9384 inst
.instruction
|= Rm
;
9385 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9387 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9388 inst
.instruction
|= SHIFT_BY_REG
;
9389 /* PR 12854: Error on extraneous shifts. */
9390 constraint (inst
.operands
[2].shifted
,
9391 _("extraneous shift as part of operand to shift insn"));
9394 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9400 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9401 inst
.reloc
.pc_rel
= 0;
9407 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9408 inst
.reloc
.pc_rel
= 0;
9414 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9415 inst
.reloc
.pc_rel
= 0;
9421 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9422 _("selected processor does not support SETPAN instruction"));
9424 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9430 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9431 _("selected processor does not support SETPAN instruction"));
9433 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9436 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9437 SMLAxy{cond} Rd,Rm,Rs,Rn
9438 SMLAWy{cond} Rd,Rm,Rs,Rn
9439 Error if any register is R15. */
9444 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9445 inst
.instruction
|= inst
.operands
[1].reg
;
9446 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9447 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9450 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9451 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9452 Error if any register is R15.
9453 Warning if Rdlo == Rdhi. */
9458 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9459 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9460 inst
.instruction
|= inst
.operands
[2].reg
;
9461 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9463 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9464 as_tsktsk (_("rdhi and rdlo must be different"));
9467 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9468 SMULxy{cond} Rd,Rm,Rs
9469 Error if any register is R15. */
9474 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9475 inst
.instruction
|= inst
.operands
[1].reg
;
9476 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9479 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9480 the same for both ARM and Thumb-2. */
9487 if (inst
.operands
[0].present
)
9489 reg
= inst
.operands
[0].reg
;
9490 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9495 inst
.instruction
|= reg
<< 16;
9496 inst
.instruction
|= inst
.operands
[1].imm
;
9497 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9498 inst
.instruction
|= WRITE_BACK
;
9501 /* ARM V6 strex (argument parse). */
9506 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9507 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9508 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9509 || inst
.operands
[2].negative
9510 /* See comment in do_ldrex(). */
9511 || (inst
.operands
[2].reg
== REG_PC
),
9514 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9515 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9517 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9518 || inst
.reloc
.exp
.X_add_number
!= 0,
9519 _("offset must be zero in ARM encoding"));
9521 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9522 inst
.instruction
|= inst
.operands
[1].reg
;
9523 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9524 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9530 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9531 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9532 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9533 || inst
.operands
[2].negative
,
9536 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9537 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9545 constraint (inst
.operands
[1].reg
% 2 != 0,
9546 _("even register required"));
9547 constraint (inst
.operands
[2].present
9548 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9549 _("can only store two consecutive registers"));
9550 /* If op 2 were present and equal to PC, this function wouldn't
9551 have been called in the first place. */
9552 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9554 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9555 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9556 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9560 inst
.instruction
|= inst
.operands
[1].reg
;
9561 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9568 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9569 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9577 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9578 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9583 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9584 extends it to 32-bits, and adds the result to a value in another
9585 register. You can specify a rotation by 0, 8, 16, or 24 bits
9586 before extracting the 16-bit value.
9587 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9588 Condition defaults to COND_ALWAYS.
9589 Error if any register uses R15. */
9594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9595 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9596 inst
.instruction
|= inst
.operands
[2].reg
;
9597 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9602 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9603 Condition defaults to COND_ALWAYS.
9604 Error if any register uses R15. */
9609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9610 inst
.instruction
|= inst
.operands
[1].reg
;
9611 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9614 /* VFP instructions. In a logical order: SP variant first, monad
9615 before dyad, arithmetic then move then load/store. */
9618 do_vfp_sp_monadic (void)
9620 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9621 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9625 do_vfp_sp_dyadic (void)
9627 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9628 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9629 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9633 do_vfp_sp_compare_z (void)
9635 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9639 do_vfp_dp_sp_cvt (void)
9641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9642 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9646 do_vfp_sp_dp_cvt (void)
9648 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9649 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9653 do_vfp_reg_from_sp (void)
9655 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9656 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9660 do_vfp_reg2_from_sp2 (void)
9662 constraint (inst
.operands
[2].imm
!= 2,
9663 _("only two consecutive VFP SP registers allowed here"));
9664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9665 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9666 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9670 do_vfp_sp_from_reg (void)
9672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9673 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9677 do_vfp_sp2_from_reg2 (void)
9679 constraint (inst
.operands
[0].imm
!= 2,
9680 _("only two consecutive VFP SP registers allowed here"));
9681 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9682 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9683 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9687 do_vfp_sp_ldst (void)
9689 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9690 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9694 do_vfp_dp_ldst (void)
9696 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9697 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9702 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9704 if (inst
.operands
[0].writeback
)
9705 inst
.instruction
|= WRITE_BACK
;
9707 constraint (ldstm_type
!= VFP_LDSTMIA
,
9708 _("this addressing mode requires base-register writeback"));
9709 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9710 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9711 inst
.instruction
|= inst
.operands
[1].imm
;
9715 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9719 if (inst
.operands
[0].writeback
)
9720 inst
.instruction
|= WRITE_BACK
;
9722 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9723 _("this addressing mode requires base-register writeback"));
9725 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9726 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9728 count
= inst
.operands
[1].imm
<< 1;
9729 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9732 inst
.instruction
|= count
;
9736 do_vfp_sp_ldstmia (void)
9738 vfp_sp_ldstm (VFP_LDSTMIA
);
9742 do_vfp_sp_ldstmdb (void)
9744 vfp_sp_ldstm (VFP_LDSTMDB
);
9748 do_vfp_dp_ldstmia (void)
9750 vfp_dp_ldstm (VFP_LDSTMIA
);
9754 do_vfp_dp_ldstmdb (void)
9756 vfp_dp_ldstm (VFP_LDSTMDB
);
9760 do_vfp_xp_ldstmia (void)
9762 vfp_dp_ldstm (VFP_LDSTMIAX
);
9766 do_vfp_xp_ldstmdb (void)
9768 vfp_dp_ldstm (VFP_LDSTMDBX
);
9772 do_vfp_dp_rd_rm (void)
9774 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9775 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9779 do_vfp_dp_rn_rd (void)
9781 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9782 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9786 do_vfp_dp_rd_rn (void)
9788 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9789 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9793 do_vfp_dp_rd_rn_rm (void)
9795 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9796 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9797 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9807 do_vfp_dp_rm_rd_rn (void)
9809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9810 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9811 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9814 /* VFPv3 instructions. */
9816 do_vfp_sp_const (void)
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9819 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9820 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9824 do_vfp_dp_const (void)
9826 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9827 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9828 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9832 vfp_conv (int srcsize
)
9834 int immbits
= srcsize
- inst
.operands
[1].imm
;
9836 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9838 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9839 i.e. immbits must be in range 0 - 16. */
9840 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9843 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9845 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9846 i.e. immbits must be in range 0 - 31. */
9847 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9851 inst
.instruction
|= (immbits
& 1) << 5;
9852 inst
.instruction
|= (immbits
>> 1);
9856 do_vfp_sp_conv_16 (void)
9858 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9863 do_vfp_dp_conv_16 (void)
9865 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9870 do_vfp_sp_conv_32 (void)
9872 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9877 do_vfp_dp_conv_32 (void)
9879 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9883 /* FPA instructions. Also in a logical order. */
9888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9889 inst
.instruction
|= inst
.operands
[1].reg
;
9893 do_fpa_ldmstm (void)
9895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9896 switch (inst
.operands
[1].imm
)
9898 case 1: inst
.instruction
|= CP_T_X
; break;
9899 case 2: inst
.instruction
|= CP_T_Y
; break;
9900 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9905 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9907 /* The instruction specified "ea" or "fd", so we can only accept
9908 [Rn]{!}. The instruction does not really support stacking or
9909 unstacking, so we have to emulate these by setting appropriate
9910 bits and offsets. */
9911 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9912 || inst
.reloc
.exp
.X_add_number
!= 0,
9913 _("this instruction does not support indexing"));
9915 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9916 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9918 if (!(inst
.instruction
& INDEX_UP
))
9919 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9921 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9923 inst
.operands
[2].preind
= 0;
9924 inst
.operands
[2].postind
= 1;
9928 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9931 /* iWMMXt instructions: strictly in alphabetical order. */
9934 do_iwmmxt_tandorc (void)
9936 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9940 do_iwmmxt_textrc (void)
9942 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9943 inst
.instruction
|= inst
.operands
[1].imm
;
9947 do_iwmmxt_textrm (void)
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9951 inst
.instruction
|= inst
.operands
[2].imm
;
9955 do_iwmmxt_tinsr (void)
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9958 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9959 inst
.instruction
|= inst
.operands
[2].imm
;
9963 do_iwmmxt_tmia (void)
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9966 inst
.instruction
|= inst
.operands
[1].reg
;
9967 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9971 do_iwmmxt_waligni (void)
9973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9974 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9975 inst
.instruction
|= inst
.operands
[2].reg
;
9976 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9980 do_iwmmxt_wmerge (void)
9982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9983 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9984 inst
.instruction
|= inst
.operands
[2].reg
;
9985 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9989 do_iwmmxt_wmov (void)
9991 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9994 inst
.instruction
|= inst
.operands
[1].reg
;
9998 do_iwmmxt_wldstbh (void)
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10003 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10005 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10006 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10010 do_iwmmxt_wldstw (void)
10012 /* RIWR_RIWC clears .isreg for a control register. */
10013 if (!inst
.operands
[0].isreg
)
10015 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10016 inst
.instruction
|= 0xf0000000;
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10020 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10024 do_iwmmxt_wldstd (void)
10026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10027 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10028 && inst
.operands
[1].immisreg
)
10030 inst
.instruction
&= ~0x1a000ff;
10031 inst
.instruction
|= (0xfU
<< 28);
10032 if (inst
.operands
[1].preind
)
10033 inst
.instruction
|= PRE_INDEX
;
10034 if (!inst
.operands
[1].negative
)
10035 inst
.instruction
|= INDEX_UP
;
10036 if (inst
.operands
[1].writeback
)
10037 inst
.instruction
|= WRITE_BACK
;
10038 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10039 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10040 inst
.instruction
|= inst
.operands
[1].imm
;
10043 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10047 do_iwmmxt_wshufh (void)
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10051 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10052 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10056 do_iwmmxt_wzero (void)
10058 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10059 inst
.instruction
|= inst
.operands
[0].reg
;
10060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10065 do_iwmmxt_wrwrwr_or_imm5 (void)
10067 if (inst
.operands
[2].isreg
)
10070 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10071 _("immediate operand requires iWMMXt2"));
10073 if (inst
.operands
[2].imm
== 0)
10075 switch ((inst
.instruction
>> 20) & 0xf)
10081 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10082 inst
.operands
[2].imm
= 16;
10083 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10089 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10090 inst
.operands
[2].imm
= 32;
10091 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10098 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10100 wrn
= (inst
.instruction
>> 16) & 0xf;
10101 inst
.instruction
&= 0xff0fff0f;
10102 inst
.instruction
|= wrn
;
10103 /* Bail out here; the instruction is now assembled. */
10108 /* Map 32 -> 0, etc. */
10109 inst
.operands
[2].imm
&= 0x1f;
10110 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10114 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10115 operations first, then control, shift, and load/store. */
10117 /* Insns like "foo X,Y,Z". */
10120 do_mav_triple (void)
10122 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10123 inst
.instruction
|= inst
.operands
[1].reg
;
10124 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10127 /* Insns like "foo W,X,Y,Z".
10128 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10133 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10134 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10135 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10136 inst
.instruction
|= inst
.operands
[3].reg
;
10139 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10141 do_mav_dspsc (void)
10143 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10146 /* Maverick shift immediate instructions.
10147 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10148 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10151 do_mav_shift (void)
10153 int imm
= inst
.operands
[2].imm
;
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10156 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10158 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10159 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10160 Bit 4 should be 0. */
10161 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10163 inst
.instruction
|= imm
;
10166 /* XScale instructions. Also sorted arithmetic before move. */
10168 /* Xscale multiply-accumulate (argument parse)
10171 MIAxycc acc0,Rm,Rs. */
10176 inst
.instruction
|= inst
.operands
[1].reg
;
10177 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10180 /* Xscale move-accumulator-register (argument parse)
10182 MARcc acc0,RdLo,RdHi. */
10187 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10188 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10191 /* Xscale move-register-accumulator (argument parse)
10193 MRAcc RdLo,RdHi,acc0. */
10198 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10200 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10203 /* Encoding functions relevant only to Thumb. */
10205 /* inst.operands[i] is a shifted-register operand; encode
10206 it into inst.instruction in the format used by Thumb32. */
10209 encode_thumb32_shifted_operand (int i
)
10211 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10212 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10214 constraint (inst
.operands
[i
].immisreg
,
10215 _("shift by register not allowed in thumb mode"));
10216 inst
.instruction
|= inst
.operands
[i
].reg
;
10217 if (shift
== SHIFT_RRX
)
10218 inst
.instruction
|= SHIFT_ROR
<< 4;
10221 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10222 _("expression too complex"));
10224 constraint (value
> 32
10225 || (value
== 32 && (shift
== SHIFT_LSL
10226 || shift
== SHIFT_ROR
)),
10227 _("shift expression is too large"));
10231 else if (value
== 32)
10234 inst
.instruction
|= shift
<< 4;
10235 inst
.instruction
|= (value
& 0x1c) << 10;
10236 inst
.instruction
|= (value
& 0x03) << 6;
10241 /* inst.operands[i] was set up by parse_address. Encode it into a
10242 Thumb32 format load or store instruction. Reject forms that cannot
10243 be used with such instructions. If is_t is true, reject forms that
10244 cannot be used with a T instruction; if is_d is true, reject forms
10245 that cannot be used with a D instruction. If it is a store insn,
10246 reject PC in Rn. */
10249 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10251 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10253 constraint (!inst
.operands
[i
].isreg
,
10254 _("Instruction does not support =N addresses"));
10256 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10257 if (inst
.operands
[i
].immisreg
)
10259 constraint (is_pc
, BAD_PC_ADDRESSING
);
10260 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10261 constraint (inst
.operands
[i
].negative
,
10262 _("Thumb does not support negative register indexing"));
10263 constraint (inst
.operands
[i
].postind
,
10264 _("Thumb does not support register post-indexing"));
10265 constraint (inst
.operands
[i
].writeback
,
10266 _("Thumb does not support register indexing with writeback"));
10267 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10268 _("Thumb supports only LSL in shifted register indexing"));
10270 inst
.instruction
|= inst
.operands
[i
].imm
;
10271 if (inst
.operands
[i
].shifted
)
10273 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10274 _("expression too complex"));
10275 constraint (inst
.reloc
.exp
.X_add_number
< 0
10276 || inst
.reloc
.exp
.X_add_number
> 3,
10277 _("shift out of range"));
10278 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10280 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10282 else if (inst
.operands
[i
].preind
)
10284 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10285 constraint (is_t
&& inst
.operands
[i
].writeback
,
10286 _("cannot use writeback with this instruction"));
10287 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10288 BAD_PC_ADDRESSING
);
10292 inst
.instruction
|= 0x01000000;
10293 if (inst
.operands
[i
].writeback
)
10294 inst
.instruction
|= 0x00200000;
10298 inst
.instruction
|= 0x00000c00;
10299 if (inst
.operands
[i
].writeback
)
10300 inst
.instruction
|= 0x00000100;
10302 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10304 else if (inst
.operands
[i
].postind
)
10306 gas_assert (inst
.operands
[i
].writeback
);
10307 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10308 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10311 inst
.instruction
|= 0x00200000;
10313 inst
.instruction
|= 0x00000900;
10314 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10316 else /* unindexed - only for coprocessor */
10317 inst
.error
= _("instruction does not accept unindexed addressing");
10320 /* Table of Thumb instructions which exist in both 16- and 32-bit
10321 encodings (the latter only in post-V6T2 cores). The index is the
10322 value used in the insns table below. When there is more than one
10323 possible 16-bit encoding for the instruction, this table always
10325 Also contains several pseudo-instructions used during relaxation. */
10326 #define T16_32_TAB \
10327 X(_adc, 4140, eb400000), \
10328 X(_adcs, 4140, eb500000), \
10329 X(_add, 1c00, eb000000), \
10330 X(_adds, 1c00, eb100000), \
10331 X(_addi, 0000, f1000000), \
10332 X(_addis, 0000, f1100000), \
10333 X(_add_pc,000f, f20f0000), \
10334 X(_add_sp,000d, f10d0000), \
10335 X(_adr, 000f, f20f0000), \
10336 X(_and, 4000, ea000000), \
10337 X(_ands, 4000, ea100000), \
10338 X(_asr, 1000, fa40f000), \
10339 X(_asrs, 1000, fa50f000), \
10340 X(_b, e000, f000b000), \
10341 X(_bcond, d000, f0008000), \
10342 X(_bic, 4380, ea200000), \
10343 X(_bics, 4380, ea300000), \
10344 X(_cmn, 42c0, eb100f00), \
10345 X(_cmp, 2800, ebb00f00), \
10346 X(_cpsie, b660, f3af8400), \
10347 X(_cpsid, b670, f3af8600), \
10348 X(_cpy, 4600, ea4f0000), \
10349 X(_dec_sp,80dd, f1ad0d00), \
10350 X(_eor, 4040, ea800000), \
10351 X(_eors, 4040, ea900000), \
10352 X(_inc_sp,00dd, f10d0d00), \
10353 X(_ldmia, c800, e8900000), \
10354 X(_ldr, 6800, f8500000), \
10355 X(_ldrb, 7800, f8100000), \
10356 X(_ldrh, 8800, f8300000), \
10357 X(_ldrsb, 5600, f9100000), \
10358 X(_ldrsh, 5e00, f9300000), \
10359 X(_ldr_pc,4800, f85f0000), \
10360 X(_ldr_pc2,4800, f85f0000), \
10361 X(_ldr_sp,9800, f85d0000), \
10362 X(_lsl, 0000, fa00f000), \
10363 X(_lsls, 0000, fa10f000), \
10364 X(_lsr, 0800, fa20f000), \
10365 X(_lsrs, 0800, fa30f000), \
10366 X(_mov, 2000, ea4f0000), \
10367 X(_movs, 2000, ea5f0000), \
10368 X(_mul, 4340, fb00f000), \
10369 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10370 X(_mvn, 43c0, ea6f0000), \
10371 X(_mvns, 43c0, ea7f0000), \
10372 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10373 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10374 X(_orr, 4300, ea400000), \
10375 X(_orrs, 4300, ea500000), \
10376 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10377 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10378 X(_rev, ba00, fa90f080), \
10379 X(_rev16, ba40, fa90f090), \
10380 X(_revsh, bac0, fa90f0b0), \
10381 X(_ror, 41c0, fa60f000), \
10382 X(_rors, 41c0, fa70f000), \
10383 X(_sbc, 4180, eb600000), \
10384 X(_sbcs, 4180, eb700000), \
10385 X(_stmia, c000, e8800000), \
10386 X(_str, 6000, f8400000), \
10387 X(_strb, 7000, f8000000), \
10388 X(_strh, 8000, f8200000), \
10389 X(_str_sp,9000, f84d0000), \
10390 X(_sub, 1e00, eba00000), \
10391 X(_subs, 1e00, ebb00000), \
10392 X(_subi, 8000, f1a00000), \
10393 X(_subis, 8000, f1b00000), \
10394 X(_sxtb, b240, fa4ff080), \
10395 X(_sxth, b200, fa0ff080), \
10396 X(_tst, 4200, ea100f00), \
10397 X(_uxtb, b2c0, fa5ff080), \
10398 X(_uxth, b280, fa1ff080), \
10399 X(_nop, bf00, f3af8000), \
10400 X(_yield, bf10, f3af8001), \
10401 X(_wfe, bf20, f3af8002), \
10402 X(_wfi, bf30, f3af8003), \
10403 X(_sev, bf40, f3af8004), \
10404 X(_sevl, bf50, f3af8005), \
10405 X(_udf, de00, f7f0a000)
10407 /* To catch errors in encoding functions, the codes are all offset by
10408 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10409 as 16-bit instructions. */
10410 #define X(a,b,c) T_MNEM##a
10411 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10414 #define X(a,b,c) 0x##b
10415 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10416 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10419 #define X(a,b,c) 0x##c
10420 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10421 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10422 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10426 /* Thumb instruction encoders, in alphabetical order. */
10428 /* ADDW or SUBW. */
10431 do_t_add_sub_w (void)
10435 Rd
= inst
.operands
[0].reg
;
10436 Rn
= inst
.operands
[1].reg
;
10438 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10439 is the SP-{plus,minus}-immediate form of the instruction. */
10441 constraint (Rd
== REG_PC
, BAD_PC
);
10443 reject_bad_reg (Rd
);
10445 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10446 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10449 /* Parse an add or subtract instruction. We get here with inst.instruction
10450 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10453 do_t_add_sub (void)
10457 Rd
= inst
.operands
[0].reg
;
10458 Rs
= (inst
.operands
[1].present
10459 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10460 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10463 set_it_insn_type_last ();
10465 if (unified_syntax
)
10468 bfd_boolean narrow
;
10471 flags
= (inst
.instruction
== T_MNEM_adds
10472 || inst
.instruction
== T_MNEM_subs
);
10474 narrow
= !in_it_block ();
10476 narrow
= in_it_block ();
10477 if (!inst
.operands
[2].isreg
)
10481 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10483 add
= (inst
.instruction
== T_MNEM_add
10484 || inst
.instruction
== T_MNEM_adds
);
10486 if (inst
.size_req
!= 4)
10488 /* Attempt to use a narrow opcode, with relaxation if
10490 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10491 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10492 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10493 opcode
= T_MNEM_add_sp
;
10494 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10495 opcode
= T_MNEM_add_pc
;
10496 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10499 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10501 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10505 inst
.instruction
= THUMB_OP16(opcode
);
10506 inst
.instruction
|= (Rd
<< 4) | Rs
;
10507 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10508 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10510 if (inst
.size_req
== 2)
10511 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10513 inst
.relax
= opcode
;
10517 constraint (inst
.size_req
== 2, BAD_HIREG
);
10519 if (inst
.size_req
== 4
10520 || (inst
.size_req
!= 2 && !opcode
))
10522 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10523 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10524 THUMB1_RELOC_ONLY
);
10527 constraint (add
, BAD_PC
);
10528 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10529 _("only SUBS PC, LR, #const allowed"));
10530 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10531 _("expression too complex"));
10532 constraint (inst
.reloc
.exp
.X_add_number
< 0
10533 || inst
.reloc
.exp
.X_add_number
> 0xff,
10534 _("immediate value out of range"));
10535 inst
.instruction
= T2_SUBS_PC_LR
10536 | inst
.reloc
.exp
.X_add_number
;
10537 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10540 else if (Rs
== REG_PC
)
10542 /* Always use addw/subw. */
10543 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10544 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10548 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10549 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10552 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10554 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10556 inst
.instruction
|= Rd
<< 8;
10557 inst
.instruction
|= Rs
<< 16;
10562 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10563 unsigned int shift
= inst
.operands
[2].shift_kind
;
10565 Rn
= inst
.operands
[2].reg
;
10566 /* See if we can do this with a 16-bit instruction. */
10567 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10569 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10574 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10575 || inst
.instruction
== T_MNEM_add
)
10577 : T_OPCODE_SUB_R3
);
10578 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10582 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10584 /* Thumb-1 cores (except v6-M) require at least one high
10585 register in a narrow non flag setting add. */
10586 if (Rd
> 7 || Rn
> 7
10587 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10588 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10595 inst
.instruction
= T_OPCODE_ADD_HI
;
10596 inst
.instruction
|= (Rd
& 8) << 4;
10597 inst
.instruction
|= (Rd
& 7);
10598 inst
.instruction
|= Rn
<< 3;
10604 constraint (Rd
== REG_PC
, BAD_PC
);
10605 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10606 constraint (Rs
== REG_PC
, BAD_PC
);
10607 reject_bad_reg (Rn
);
10609 /* If we get here, it can't be done in 16 bits. */
10610 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10611 _("shift must be constant"));
10612 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10613 inst
.instruction
|= Rd
<< 8;
10614 inst
.instruction
|= Rs
<< 16;
10615 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10616 _("shift value over 3 not allowed in thumb mode"));
10617 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10618 _("only LSL shift allowed in thumb mode"));
10619 encode_thumb32_shifted_operand (2);
10624 constraint (inst
.instruction
== T_MNEM_adds
10625 || inst
.instruction
== T_MNEM_subs
,
10628 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10630 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10631 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10634 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10635 ? 0x0000 : 0x8000);
10636 inst
.instruction
|= (Rd
<< 4) | Rs
;
10637 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10641 Rn
= inst
.operands
[2].reg
;
10642 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10644 /* We now have Rd, Rs, and Rn set to registers. */
10645 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10647 /* Can't do this for SUB. */
10648 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10649 inst
.instruction
= T_OPCODE_ADD_HI
;
10650 inst
.instruction
|= (Rd
& 8) << 4;
10651 inst
.instruction
|= (Rd
& 7);
10653 inst
.instruction
|= Rn
<< 3;
10655 inst
.instruction
|= Rs
<< 3;
10657 constraint (1, _("dest must overlap one source register"));
10661 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10662 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10663 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10673 Rd
= inst
.operands
[0].reg
;
10674 reject_bad_reg (Rd
);
10676 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10678 /* Defer to section relaxation. */
10679 inst
.relax
= inst
.instruction
;
10680 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10681 inst
.instruction
|= Rd
<< 4;
10683 else if (unified_syntax
&& inst
.size_req
!= 2)
10685 /* Generate a 32-bit opcode. */
10686 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10687 inst
.instruction
|= Rd
<< 8;
10688 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10689 inst
.reloc
.pc_rel
= 1;
10693 /* Generate a 16-bit opcode. */
10694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10695 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10696 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10697 inst
.reloc
.pc_rel
= 1;
10699 inst
.instruction
|= Rd
<< 4;
10703 /* Arithmetic instructions for which there is just one 16-bit
10704 instruction encoding, and it allows only two low registers.
10705 For maximal compatibility with ARM syntax, we allow three register
10706 operands even when Thumb-32 instructions are not available, as long
10707 as the first two are identical. For instance, both "sbc r0,r1" and
10708 "sbc r0,r0,r1" are allowed. */
10714 Rd
= inst
.operands
[0].reg
;
10715 Rs
= (inst
.operands
[1].present
10716 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10717 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10718 Rn
= inst
.operands
[2].reg
;
10720 reject_bad_reg (Rd
);
10721 reject_bad_reg (Rs
);
10722 if (inst
.operands
[2].isreg
)
10723 reject_bad_reg (Rn
);
10725 if (unified_syntax
)
10727 if (!inst
.operands
[2].isreg
)
10729 /* For an immediate, we always generate a 32-bit opcode;
10730 section relaxation will shrink it later if possible. */
10731 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10732 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10733 inst
.instruction
|= Rd
<< 8;
10734 inst
.instruction
|= Rs
<< 16;
10735 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10739 bfd_boolean narrow
;
10741 /* See if we can do this with a 16-bit instruction. */
10742 if (THUMB_SETS_FLAGS (inst
.instruction
))
10743 narrow
= !in_it_block ();
10745 narrow
= in_it_block ();
10747 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10749 if (inst
.operands
[2].shifted
)
10751 if (inst
.size_req
== 4)
10757 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10758 inst
.instruction
|= Rd
;
10759 inst
.instruction
|= Rn
<< 3;
10763 /* If we get here, it can't be done in 16 bits. */
10764 constraint (inst
.operands
[2].shifted
10765 && inst
.operands
[2].immisreg
,
10766 _("shift must be constant"));
10767 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10768 inst
.instruction
|= Rd
<< 8;
10769 inst
.instruction
|= Rs
<< 16;
10770 encode_thumb32_shifted_operand (2);
10775 /* On its face this is a lie - the instruction does set the
10776 flags. However, the only supported mnemonic in this mode
10777 says it doesn't. */
10778 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10780 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10781 _("unshifted register required"));
10782 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10783 constraint (Rd
!= Rs
,
10784 _("dest and source1 must be the same register"));
10786 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10787 inst
.instruction
|= Rd
;
10788 inst
.instruction
|= Rn
<< 3;
10792 /* Similarly, but for instructions where the arithmetic operation is
10793 commutative, so we can allow either of them to be different from
10794 the destination operand in a 16-bit instruction. For instance, all
10795 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10802 Rd
= inst
.operands
[0].reg
;
10803 Rs
= (inst
.operands
[1].present
10804 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10805 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10806 Rn
= inst
.operands
[2].reg
;
10808 reject_bad_reg (Rd
);
10809 reject_bad_reg (Rs
);
10810 if (inst
.operands
[2].isreg
)
10811 reject_bad_reg (Rn
);
10813 if (unified_syntax
)
10815 if (!inst
.operands
[2].isreg
)
10817 /* For an immediate, we always generate a 32-bit opcode;
10818 section relaxation will shrink it later if possible. */
10819 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10820 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10821 inst
.instruction
|= Rd
<< 8;
10822 inst
.instruction
|= Rs
<< 16;
10823 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10827 bfd_boolean narrow
;
10829 /* See if we can do this with a 16-bit instruction. */
10830 if (THUMB_SETS_FLAGS (inst
.instruction
))
10831 narrow
= !in_it_block ();
10833 narrow
= in_it_block ();
10835 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10837 if (inst
.operands
[2].shifted
)
10839 if (inst
.size_req
== 4)
10846 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10847 inst
.instruction
|= Rd
;
10848 inst
.instruction
|= Rn
<< 3;
10853 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10854 inst
.instruction
|= Rd
;
10855 inst
.instruction
|= Rs
<< 3;
10860 /* If we get here, it can't be done in 16 bits. */
10861 constraint (inst
.operands
[2].shifted
10862 && inst
.operands
[2].immisreg
,
10863 _("shift must be constant"));
10864 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10865 inst
.instruction
|= Rd
<< 8;
10866 inst
.instruction
|= Rs
<< 16;
10867 encode_thumb32_shifted_operand (2);
10872 /* On its face this is a lie - the instruction does set the
10873 flags. However, the only supported mnemonic in this mode
10874 says it doesn't. */
10875 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10877 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10878 _("unshifted register required"));
10879 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10881 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10882 inst
.instruction
|= Rd
;
10885 inst
.instruction
|= Rn
<< 3;
10887 inst
.instruction
|= Rs
<< 3;
10889 constraint (1, _("dest must overlap one source register"));
10897 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10898 constraint (msb
> 32, _("bit-field extends past end of register"));
10899 /* The instruction encoding stores the LSB and MSB,
10900 not the LSB and width. */
10901 Rd
= inst
.operands
[0].reg
;
10902 reject_bad_reg (Rd
);
10903 inst
.instruction
|= Rd
<< 8;
10904 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10905 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10906 inst
.instruction
|= msb
- 1;
10915 Rd
= inst
.operands
[0].reg
;
10916 reject_bad_reg (Rd
);
10918 /* #0 in second position is alternative syntax for bfc, which is
10919 the same instruction but with REG_PC in the Rm field. */
10920 if (!inst
.operands
[1].isreg
)
10924 Rn
= inst
.operands
[1].reg
;
10925 reject_bad_reg (Rn
);
10928 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10929 constraint (msb
> 32, _("bit-field extends past end of register"));
10930 /* The instruction encoding stores the LSB and MSB,
10931 not the LSB and width. */
10932 inst
.instruction
|= Rd
<< 8;
10933 inst
.instruction
|= Rn
<< 16;
10934 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10935 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10936 inst
.instruction
|= msb
- 1;
10944 Rd
= inst
.operands
[0].reg
;
10945 Rn
= inst
.operands
[1].reg
;
10947 reject_bad_reg (Rd
);
10948 reject_bad_reg (Rn
);
10950 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10951 _("bit-field extends past end of register"));
10952 inst
.instruction
|= Rd
<< 8;
10953 inst
.instruction
|= Rn
<< 16;
10954 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10955 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10956 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10959 /* ARM V5 Thumb BLX (argument parse)
10960 BLX <target_addr> which is BLX(1)
10961 BLX <Rm> which is BLX(2)
10962 Unfortunately, there are two different opcodes for this mnemonic.
10963 So, the insns[].value is not used, and the code here zaps values
10964 into inst.instruction.
10966 ??? How to take advantage of the additional two bits of displacement
10967 available in Thumb32 mode? Need new relocation? */
10972 set_it_insn_type_last ();
10974 if (inst
.operands
[0].isreg
)
10976 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10977 /* We have a register, so this is BLX(2). */
10978 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10982 /* No register. This must be BLX(1). */
10983 inst
.instruction
= 0xf000e800;
10984 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10993 bfd_reloc_code_real_type reloc
;
10996 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10998 if (in_it_block ())
11000 /* Conditional branches inside IT blocks are encoded as unconditional
11002 cond
= COND_ALWAYS
;
11007 if (cond
!= COND_ALWAYS
)
11008 opcode
= T_MNEM_bcond
;
11010 opcode
= inst
.instruction
;
11013 && (inst
.size_req
== 4
11014 || (inst
.size_req
!= 2
11015 && (inst
.operands
[0].hasreloc
11016 || inst
.reloc
.exp
.X_op
== O_constant
))))
11018 inst
.instruction
= THUMB_OP32(opcode
);
11019 if (cond
== COND_ALWAYS
)
11020 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11023 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11024 _("selected architecture does not support "
11025 "wide conditional branch instruction"));
11027 gas_assert (cond
!= 0xF);
11028 inst
.instruction
|= cond
<< 22;
11029 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11034 inst
.instruction
= THUMB_OP16(opcode
);
11035 if (cond
== COND_ALWAYS
)
11036 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11039 inst
.instruction
|= cond
<< 8;
11040 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11042 /* Allow section relaxation. */
11043 if (unified_syntax
&& inst
.size_req
!= 2)
11044 inst
.relax
= opcode
;
11046 inst
.reloc
.type
= reloc
;
11047 inst
.reloc
.pc_rel
= 1;
11050 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11051 between the two is the maximum immediate allowed - which is passed in
11054 do_t_bkpt_hlt1 (int range
)
11056 constraint (inst
.cond
!= COND_ALWAYS
,
11057 _("instruction is always unconditional"));
11058 if (inst
.operands
[0].present
)
11060 constraint (inst
.operands
[0].imm
> range
,
11061 _("immediate value out of range"));
11062 inst
.instruction
|= inst
.operands
[0].imm
;
11065 set_it_insn_type (NEUTRAL_IT_INSN
);
11071 do_t_bkpt_hlt1 (63);
11077 do_t_bkpt_hlt1 (255);
11081 do_t_branch23 (void)
11083 set_it_insn_type_last ();
11084 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11086 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11087 this file. We used to simply ignore the PLT reloc type here --
11088 the branch encoding is now needed to deal with TLSCALL relocs.
11089 So if we see a PLT reloc now, put it back to how it used to be to
11090 keep the preexisting behaviour. */
11091 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11092 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11094 #if defined(OBJ_COFF)
11095 /* If the destination of the branch is a defined symbol which does not have
11096 the THUMB_FUNC attribute, then we must be calling a function which has
11097 the (interfacearm) attribute. We look for the Thumb entry point to that
11098 function and change the branch to refer to that function instead. */
11099 if ( inst
.reloc
.exp
.X_op
== O_symbol
11100 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11101 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11102 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11103 inst
.reloc
.exp
.X_add_symbol
=
11104 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11111 set_it_insn_type_last ();
11112 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11113 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11114 should cause the alignment to be checked once it is known. This is
11115 because BX PC only works if the instruction is word aligned. */
11123 set_it_insn_type_last ();
11124 Rm
= inst
.operands
[0].reg
;
11125 reject_bad_reg (Rm
);
11126 inst
.instruction
|= Rm
<< 16;
11135 Rd
= inst
.operands
[0].reg
;
11136 Rm
= inst
.operands
[1].reg
;
11138 reject_bad_reg (Rd
);
11139 reject_bad_reg (Rm
);
11141 inst
.instruction
|= Rd
<< 8;
11142 inst
.instruction
|= Rm
<< 16;
11143 inst
.instruction
|= Rm
;
11149 set_it_insn_type (OUTSIDE_IT_INSN
);
11150 inst
.instruction
|= inst
.operands
[0].imm
;
11156 set_it_insn_type (OUTSIDE_IT_INSN
);
11158 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11159 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11161 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11162 inst
.instruction
= 0xf3af8000;
11163 inst
.instruction
|= imod
<< 9;
11164 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11165 if (inst
.operands
[1].present
)
11166 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11170 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11171 && (inst
.operands
[0].imm
& 4),
11172 _("selected processor does not support 'A' form "
11173 "of this instruction"));
11174 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11175 _("Thumb does not support the 2-argument "
11176 "form of this instruction"));
11177 inst
.instruction
|= inst
.operands
[0].imm
;
11181 /* THUMB CPY instruction (argument parse). */
11186 if (inst
.size_req
== 4)
11188 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11189 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11190 inst
.instruction
|= inst
.operands
[1].reg
;
11194 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11195 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11196 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11203 set_it_insn_type (OUTSIDE_IT_INSN
);
11204 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11205 inst
.instruction
|= inst
.operands
[0].reg
;
11206 inst
.reloc
.pc_rel
= 1;
11207 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11213 inst
.instruction
|= inst
.operands
[0].imm
;
11219 unsigned Rd
, Rn
, Rm
;
11221 Rd
= inst
.operands
[0].reg
;
11222 Rn
= (inst
.operands
[1].present
11223 ? inst
.operands
[1].reg
: Rd
);
11224 Rm
= inst
.operands
[2].reg
;
11226 reject_bad_reg (Rd
);
11227 reject_bad_reg (Rn
);
11228 reject_bad_reg (Rm
);
11230 inst
.instruction
|= Rd
<< 8;
11231 inst
.instruction
|= Rn
<< 16;
11232 inst
.instruction
|= Rm
;
11238 if (unified_syntax
&& inst
.size_req
== 4)
11239 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11241 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11247 unsigned int cond
= inst
.operands
[0].imm
;
11249 set_it_insn_type (IT_INSN
);
11250 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11252 now_it
.warn_deprecated
= FALSE
;
11254 /* If the condition is a negative condition, invert the mask. */
11255 if ((cond
& 0x1) == 0x0)
11257 unsigned int mask
= inst
.instruction
& 0x000f;
11259 if ((mask
& 0x7) == 0)
11261 /* No conversion needed. */
11262 now_it
.block_length
= 1;
11264 else if ((mask
& 0x3) == 0)
11267 now_it
.block_length
= 2;
11269 else if ((mask
& 0x1) == 0)
11272 now_it
.block_length
= 3;
11277 now_it
.block_length
= 4;
11280 inst
.instruction
&= 0xfff0;
11281 inst
.instruction
|= mask
;
11284 inst
.instruction
|= cond
<< 4;
11287 /* Helper function used for both push/pop and ldm/stm. */
11289 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11293 load
= (inst
.instruction
& (1 << 20)) != 0;
11295 if (mask
& (1 << 13))
11296 inst
.error
= _("SP not allowed in register list");
11298 if ((mask
& (1 << base
)) != 0
11300 inst
.error
= _("having the base register in the register list when "
11301 "using write back is UNPREDICTABLE");
11305 if (mask
& (1 << 15))
11307 if (mask
& (1 << 14))
11308 inst
.error
= _("LR and PC should not both be in register list");
11310 set_it_insn_type_last ();
11315 if (mask
& (1 << 15))
11316 inst
.error
= _("PC not allowed in register list");
11319 if ((mask
& (mask
- 1)) == 0)
11321 /* Single register transfers implemented as str/ldr. */
11324 if (inst
.instruction
& (1 << 23))
11325 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11327 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11331 if (inst
.instruction
& (1 << 23))
11332 inst
.instruction
= 0x00800000; /* ia -> [base] */
11334 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11337 inst
.instruction
|= 0xf8400000;
11339 inst
.instruction
|= 0x00100000;
11341 mask
= ffs (mask
) - 1;
11344 else if (writeback
)
11345 inst
.instruction
|= WRITE_BACK
;
11347 inst
.instruction
|= mask
;
11348 inst
.instruction
|= base
<< 16;
11354 /* This really doesn't seem worth it. */
11355 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11356 _("expression too complex"));
11357 constraint (inst
.operands
[1].writeback
,
11358 _("Thumb load/store multiple does not support {reglist}^"));
11360 if (unified_syntax
)
11362 bfd_boolean narrow
;
11366 /* See if we can use a 16-bit instruction. */
11367 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11368 && inst
.size_req
!= 4
11369 && !(inst
.operands
[1].imm
& ~0xff))
11371 mask
= 1 << inst
.operands
[0].reg
;
11373 if (inst
.operands
[0].reg
<= 7)
11375 if (inst
.instruction
== T_MNEM_stmia
11376 ? inst
.operands
[0].writeback
11377 : (inst
.operands
[0].writeback
11378 == !(inst
.operands
[1].imm
& mask
)))
11380 if (inst
.instruction
== T_MNEM_stmia
11381 && (inst
.operands
[1].imm
& mask
)
11382 && (inst
.operands
[1].imm
& (mask
- 1)))
11383 as_warn (_("value stored for r%d is UNKNOWN"),
11384 inst
.operands
[0].reg
);
11386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11388 inst
.instruction
|= inst
.operands
[1].imm
;
11391 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11393 /* This means 1 register in reg list one of 3 situations:
11394 1. Instruction is stmia, but without writeback.
11395 2. lmdia without writeback, but with Rn not in
11397 3. ldmia with writeback, but with Rn in reglist.
11398 Case 3 is UNPREDICTABLE behaviour, so we handle
11399 case 1 and 2 which can be converted into a 16-bit
11400 str or ldr. The SP cases are handled below. */
11401 unsigned long opcode
;
11402 /* First, record an error for Case 3. */
11403 if (inst
.operands
[1].imm
& mask
11404 && inst
.operands
[0].writeback
)
11406 _("having the base register in the register list when "
11407 "using write back is UNPREDICTABLE");
11409 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11411 inst
.instruction
= THUMB_OP16 (opcode
);
11412 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11413 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11417 else if (inst
.operands
[0] .reg
== REG_SP
)
11419 if (inst
.operands
[0].writeback
)
11422 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11423 ? T_MNEM_push
: T_MNEM_pop
);
11424 inst
.instruction
|= inst
.operands
[1].imm
;
11427 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11430 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11431 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11432 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11440 if (inst
.instruction
< 0xffff)
11441 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11443 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11444 inst
.operands
[0].writeback
);
11449 constraint (inst
.operands
[0].reg
> 7
11450 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11451 constraint (inst
.instruction
!= T_MNEM_ldmia
11452 && inst
.instruction
!= T_MNEM_stmia
,
11453 _("Thumb-2 instruction only valid in unified syntax"));
11454 if (inst
.instruction
== T_MNEM_stmia
)
11456 if (!inst
.operands
[0].writeback
)
11457 as_warn (_("this instruction will write back the base register"));
11458 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11459 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11460 as_warn (_("value stored for r%d is UNKNOWN"),
11461 inst
.operands
[0].reg
);
11465 if (!inst
.operands
[0].writeback
11466 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11467 as_warn (_("this instruction will write back the base register"));
11468 else if (inst
.operands
[0].writeback
11469 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11470 as_warn (_("this instruction will not write back the base register"));
11473 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11474 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11475 inst
.instruction
|= inst
.operands
[1].imm
;
11482 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11483 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11484 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11485 || inst
.operands
[1].negative
,
11488 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11490 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11491 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11492 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11498 if (!inst
.operands
[1].present
)
11500 constraint (inst
.operands
[0].reg
== REG_LR
,
11501 _("r14 not allowed as first register "
11502 "when second register is omitted"));
11503 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11505 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11508 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11509 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11510 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11516 unsigned long opcode
;
11519 if (inst
.operands
[0].isreg
11520 && !inst
.operands
[0].preind
11521 && inst
.operands
[0].reg
== REG_PC
)
11522 set_it_insn_type_last ();
11524 opcode
= inst
.instruction
;
11525 if (unified_syntax
)
11527 if (!inst
.operands
[1].isreg
)
11529 if (opcode
<= 0xffff)
11530 inst
.instruction
= THUMB_OP32 (opcode
);
11531 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11534 if (inst
.operands
[1].isreg
11535 && !inst
.operands
[1].writeback
11536 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11537 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11538 && opcode
<= 0xffff
11539 && inst
.size_req
!= 4)
11541 /* Insn may have a 16-bit form. */
11542 Rn
= inst
.operands
[1].reg
;
11543 if (inst
.operands
[1].immisreg
)
11545 inst
.instruction
= THUMB_OP16 (opcode
);
11547 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11549 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11550 reject_bad_reg (inst
.operands
[1].imm
);
11552 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11553 && opcode
!= T_MNEM_ldrsb
)
11554 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11555 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11562 if (inst
.reloc
.pc_rel
)
11563 opcode
= T_MNEM_ldr_pc2
;
11565 opcode
= T_MNEM_ldr_pc
;
11569 if (opcode
== T_MNEM_ldr
)
11570 opcode
= T_MNEM_ldr_sp
;
11572 opcode
= T_MNEM_str_sp
;
11574 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11578 inst
.instruction
= inst
.operands
[0].reg
;
11579 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11581 inst
.instruction
|= THUMB_OP16 (opcode
);
11582 if (inst
.size_req
== 2)
11583 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11585 inst
.relax
= opcode
;
11589 /* Definitely a 32-bit variant. */
11591 /* Warning for Erratum 752419. */
11592 if (opcode
== T_MNEM_ldr
11593 && inst
.operands
[0].reg
== REG_SP
11594 && inst
.operands
[1].writeback
== 1
11595 && !inst
.operands
[1].immisreg
)
11597 if (no_cpu_selected ()
11598 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11599 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11600 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11601 as_warn (_("This instruction may be unpredictable "
11602 "if executed on M-profile cores "
11603 "with interrupts enabled."));
11606 /* Do some validations regarding addressing modes. */
11607 if (inst
.operands
[1].immisreg
)
11608 reject_bad_reg (inst
.operands
[1].imm
);
11610 constraint (inst
.operands
[1].writeback
== 1
11611 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11614 inst
.instruction
= THUMB_OP32 (opcode
);
11615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11616 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11617 check_ldr_r15_aligned ();
11621 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11623 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11625 /* Only [Rn,Rm] is acceptable. */
11626 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11627 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11628 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11629 || inst
.operands
[1].negative
,
11630 _("Thumb does not support this addressing mode"));
11631 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11635 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11636 if (!inst
.operands
[1].isreg
)
11637 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11640 constraint (!inst
.operands
[1].preind
11641 || inst
.operands
[1].shifted
11642 || inst
.operands
[1].writeback
,
11643 _("Thumb does not support this addressing mode"));
11644 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11646 constraint (inst
.instruction
& 0x0600,
11647 _("byte or halfword not valid for base register"));
11648 constraint (inst
.operands
[1].reg
== REG_PC
11649 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11650 _("r15 based store not allowed"));
11651 constraint (inst
.operands
[1].immisreg
,
11652 _("invalid base register for register offset"));
11654 if (inst
.operands
[1].reg
== REG_PC
)
11655 inst
.instruction
= T_OPCODE_LDR_PC
;
11656 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11657 inst
.instruction
= T_OPCODE_LDR_SP
;
11659 inst
.instruction
= T_OPCODE_STR_SP
;
11661 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11662 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11666 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11667 if (!inst
.operands
[1].immisreg
)
11669 /* Immediate offset. */
11670 inst
.instruction
|= inst
.operands
[0].reg
;
11671 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11672 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11676 /* Register offset. */
11677 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11678 constraint (inst
.operands
[1].negative
,
11679 _("Thumb does not support this addressing mode"));
11682 switch (inst
.instruction
)
11684 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11685 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11686 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11687 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11688 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11689 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11690 case 0x5600 /* ldrsb */:
11691 case 0x5e00 /* ldrsh */: break;
11695 inst
.instruction
|= inst
.operands
[0].reg
;
11696 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11697 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11703 if (!inst
.operands
[1].present
)
11705 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11706 constraint (inst
.operands
[0].reg
== REG_LR
,
11707 _("r14 not allowed here"));
11708 constraint (inst
.operands
[0].reg
== REG_R12
,
11709 _("r12 not allowed here"));
11712 if (inst
.operands
[2].writeback
11713 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11714 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11715 as_warn (_("base register written back, and overlaps "
11716 "one of transfer registers"));
11718 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11719 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11720 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11727 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11733 unsigned Rd
, Rn
, Rm
, Ra
;
11735 Rd
= inst
.operands
[0].reg
;
11736 Rn
= inst
.operands
[1].reg
;
11737 Rm
= inst
.operands
[2].reg
;
11738 Ra
= inst
.operands
[3].reg
;
11740 reject_bad_reg (Rd
);
11741 reject_bad_reg (Rn
);
11742 reject_bad_reg (Rm
);
11743 reject_bad_reg (Ra
);
11745 inst
.instruction
|= Rd
<< 8;
11746 inst
.instruction
|= Rn
<< 16;
11747 inst
.instruction
|= Rm
;
11748 inst
.instruction
|= Ra
<< 12;
11754 unsigned RdLo
, RdHi
, Rn
, Rm
;
11756 RdLo
= inst
.operands
[0].reg
;
11757 RdHi
= inst
.operands
[1].reg
;
11758 Rn
= inst
.operands
[2].reg
;
11759 Rm
= inst
.operands
[3].reg
;
11761 reject_bad_reg (RdLo
);
11762 reject_bad_reg (RdHi
);
11763 reject_bad_reg (Rn
);
11764 reject_bad_reg (Rm
);
11766 inst
.instruction
|= RdLo
<< 12;
11767 inst
.instruction
|= RdHi
<< 8;
11768 inst
.instruction
|= Rn
<< 16;
11769 inst
.instruction
|= Rm
;
11773 do_t_mov_cmp (void)
11777 Rn
= inst
.operands
[0].reg
;
11778 Rm
= inst
.operands
[1].reg
;
11781 set_it_insn_type_last ();
11783 if (unified_syntax
)
11785 int r0off
= (inst
.instruction
== T_MNEM_mov
11786 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11787 unsigned long opcode
;
11788 bfd_boolean narrow
;
11789 bfd_boolean low_regs
;
11791 low_regs
= (Rn
<= 7 && Rm
<= 7);
11792 opcode
= inst
.instruction
;
11793 if (in_it_block ())
11794 narrow
= opcode
!= T_MNEM_movs
;
11796 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11797 if (inst
.size_req
== 4
11798 || inst
.operands
[1].shifted
)
11801 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11802 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11803 && !inst
.operands
[1].shifted
11807 inst
.instruction
= T2_SUBS_PC_LR
;
11811 if (opcode
== T_MNEM_cmp
)
11813 constraint (Rn
== REG_PC
, BAD_PC
);
11816 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11818 warn_deprecated_sp (Rm
);
11819 /* R15 was documented as a valid choice for Rm in ARMv6,
11820 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11821 tools reject R15, so we do too. */
11822 constraint (Rm
== REG_PC
, BAD_PC
);
11825 reject_bad_reg (Rm
);
11827 else if (opcode
== T_MNEM_mov
11828 || opcode
== T_MNEM_movs
)
11830 if (inst
.operands
[1].isreg
)
11832 if (opcode
== T_MNEM_movs
)
11834 reject_bad_reg (Rn
);
11835 reject_bad_reg (Rm
);
11839 /* This is mov.n. */
11840 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11841 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11843 as_tsktsk (_("Use of r%u as a source register is "
11844 "deprecated when r%u is the destination "
11845 "register."), Rm
, Rn
);
11850 /* This is mov.w. */
11851 constraint (Rn
== REG_PC
, BAD_PC
);
11852 constraint (Rm
== REG_PC
, BAD_PC
);
11853 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11857 reject_bad_reg (Rn
);
11860 if (!inst
.operands
[1].isreg
)
11862 /* Immediate operand. */
11863 if (!in_it_block () && opcode
== T_MNEM_mov
)
11865 if (low_regs
&& narrow
)
11867 inst
.instruction
= THUMB_OP16 (opcode
);
11868 inst
.instruction
|= Rn
<< 8;
11869 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11870 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11872 if (inst
.size_req
== 2)
11873 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11875 inst
.relax
= opcode
;
11880 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11881 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11882 THUMB1_RELOC_ONLY
);
11884 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11885 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11886 inst
.instruction
|= Rn
<< r0off
;
11887 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11890 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11891 && (inst
.instruction
== T_MNEM_mov
11892 || inst
.instruction
== T_MNEM_movs
))
11894 /* Register shifts are encoded as separate shift instructions. */
11895 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11897 if (in_it_block ())
11902 if (inst
.size_req
== 4)
11905 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11911 switch (inst
.operands
[1].shift_kind
)
11914 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11917 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11920 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11923 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11929 inst
.instruction
= opcode
;
11932 inst
.instruction
|= Rn
;
11933 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11938 inst
.instruction
|= CONDS_BIT
;
11940 inst
.instruction
|= Rn
<< 8;
11941 inst
.instruction
|= Rm
<< 16;
11942 inst
.instruction
|= inst
.operands
[1].imm
;
11947 /* Some mov with immediate shift have narrow variants.
11948 Register shifts are handled above. */
11949 if (low_regs
&& inst
.operands
[1].shifted
11950 && (inst
.instruction
== T_MNEM_mov
11951 || inst
.instruction
== T_MNEM_movs
))
11953 if (in_it_block ())
11954 narrow
= (inst
.instruction
== T_MNEM_mov
);
11956 narrow
= (inst
.instruction
== T_MNEM_movs
);
11961 switch (inst
.operands
[1].shift_kind
)
11963 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11964 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11965 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11966 default: narrow
= FALSE
; break;
11972 inst
.instruction
|= Rn
;
11973 inst
.instruction
|= Rm
<< 3;
11974 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11978 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11979 inst
.instruction
|= Rn
<< r0off
;
11980 encode_thumb32_shifted_operand (1);
11984 switch (inst
.instruction
)
11987 /* In v4t or v5t a move of two lowregs produces unpredictable
11988 results. Don't allow this. */
11991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11992 "MOV Rd, Rs with two low registers is not "
11993 "permitted on this architecture");
11994 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11998 inst
.instruction
= T_OPCODE_MOV_HR
;
11999 inst
.instruction
|= (Rn
& 0x8) << 4;
12000 inst
.instruction
|= (Rn
& 0x7);
12001 inst
.instruction
|= Rm
<< 3;
12005 /* We know we have low registers at this point.
12006 Generate LSLS Rd, Rs, #0. */
12007 inst
.instruction
= T_OPCODE_LSL_I
;
12008 inst
.instruction
|= Rn
;
12009 inst
.instruction
|= Rm
<< 3;
12015 inst
.instruction
= T_OPCODE_CMP_LR
;
12016 inst
.instruction
|= Rn
;
12017 inst
.instruction
|= Rm
<< 3;
12021 inst
.instruction
= T_OPCODE_CMP_HR
;
12022 inst
.instruction
|= (Rn
& 0x8) << 4;
12023 inst
.instruction
|= (Rn
& 0x7);
12024 inst
.instruction
|= Rm
<< 3;
12031 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12033 /* PR 10443: Do not silently ignore shifted operands. */
12034 constraint (inst
.operands
[1].shifted
,
12035 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12037 if (inst
.operands
[1].isreg
)
12039 if (Rn
< 8 && Rm
< 8)
12041 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12042 since a MOV instruction produces unpredictable results. */
12043 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12044 inst
.instruction
= T_OPCODE_ADD_I3
;
12046 inst
.instruction
= T_OPCODE_CMP_LR
;
12048 inst
.instruction
|= Rn
;
12049 inst
.instruction
|= Rm
<< 3;
12053 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12054 inst
.instruction
= T_OPCODE_MOV_HR
;
12056 inst
.instruction
= T_OPCODE_CMP_HR
;
12062 constraint (Rn
> 7,
12063 _("only lo regs allowed with immediate"));
12064 inst
.instruction
|= Rn
<< 8;
12065 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12076 top
= (inst
.instruction
& 0x00800000) != 0;
12077 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12079 constraint (top
, _(":lower16: not allowed this instruction"));
12080 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12082 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12084 constraint (!top
, _(":upper16: not allowed this instruction"));
12085 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12088 Rd
= inst
.operands
[0].reg
;
12089 reject_bad_reg (Rd
);
12091 inst
.instruction
|= Rd
<< 8;
12092 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12094 imm
= inst
.reloc
.exp
.X_add_number
;
12095 inst
.instruction
|= (imm
& 0xf000) << 4;
12096 inst
.instruction
|= (imm
& 0x0800) << 15;
12097 inst
.instruction
|= (imm
& 0x0700) << 4;
12098 inst
.instruction
|= (imm
& 0x00ff);
12103 do_t_mvn_tst (void)
12107 Rn
= inst
.operands
[0].reg
;
12108 Rm
= inst
.operands
[1].reg
;
12110 if (inst
.instruction
== T_MNEM_cmp
12111 || inst
.instruction
== T_MNEM_cmn
)
12112 constraint (Rn
== REG_PC
, BAD_PC
);
12114 reject_bad_reg (Rn
);
12115 reject_bad_reg (Rm
);
12117 if (unified_syntax
)
12119 int r0off
= (inst
.instruction
== T_MNEM_mvn
12120 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12121 bfd_boolean narrow
;
12123 if (inst
.size_req
== 4
12124 || inst
.instruction
> 0xffff
12125 || inst
.operands
[1].shifted
12126 || Rn
> 7 || Rm
> 7)
12128 else if (inst
.instruction
== T_MNEM_cmn
12129 || inst
.instruction
== T_MNEM_tst
)
12131 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12132 narrow
= !in_it_block ();
12134 narrow
= in_it_block ();
12136 if (!inst
.operands
[1].isreg
)
12138 /* For an immediate, we always generate a 32-bit opcode;
12139 section relaxation will shrink it later if possible. */
12140 if (inst
.instruction
< 0xffff)
12141 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12142 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12143 inst
.instruction
|= Rn
<< r0off
;
12144 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12148 /* See if we can do this with a 16-bit instruction. */
12151 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12152 inst
.instruction
|= Rn
;
12153 inst
.instruction
|= Rm
<< 3;
12157 constraint (inst
.operands
[1].shifted
12158 && inst
.operands
[1].immisreg
,
12159 _("shift must be constant"));
12160 if (inst
.instruction
< 0xffff)
12161 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12162 inst
.instruction
|= Rn
<< r0off
;
12163 encode_thumb32_shifted_operand (1);
12169 constraint (inst
.instruction
> 0xffff
12170 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12171 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12172 _("unshifted register required"));
12173 constraint (Rn
> 7 || Rm
> 7,
12176 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12177 inst
.instruction
|= Rn
;
12178 inst
.instruction
|= Rm
<< 3;
12187 if (do_vfp_nsyn_mrs () == SUCCESS
)
12190 Rd
= inst
.operands
[0].reg
;
12191 reject_bad_reg (Rd
);
12192 inst
.instruction
|= Rd
<< 8;
12194 if (inst
.operands
[1].isreg
)
12196 unsigned br
= inst
.operands
[1].reg
;
12197 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12198 as_bad (_("bad register for mrs"));
12200 inst
.instruction
|= br
& (0xf << 16);
12201 inst
.instruction
|= (br
& 0x300) >> 4;
12202 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12206 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12208 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12210 /* PR gas/12698: The constraint is only applied for m_profile.
12211 If the user has specified -march=all, we want to ignore it as
12212 we are building for any CPU type, including non-m variants. */
12213 bfd_boolean m_profile
=
12214 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12215 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12216 "not support requested special purpose register"));
12219 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12221 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12222 _("'APSR', 'CPSR' or 'SPSR' expected"));
12224 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12225 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12226 inst
.instruction
|= 0xf0000;
12236 if (do_vfp_nsyn_msr () == SUCCESS
)
12239 constraint (!inst
.operands
[1].isreg
,
12240 _("Thumb encoding does not support an immediate here"));
12242 if (inst
.operands
[0].isreg
)
12243 flags
= (int)(inst
.operands
[0].reg
);
12245 flags
= inst
.operands
[0].imm
;
12247 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12249 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12251 /* PR gas/12698: The constraint is only applied for m_profile.
12252 If the user has specified -march=all, we want to ignore it as
12253 we are building for any CPU type, including non-m variants. */
12254 bfd_boolean m_profile
=
12255 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12256 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12257 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12258 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12259 && bits
!= PSR_f
)) && m_profile
,
12260 _("selected processor does not support requested special "
12261 "purpose register"));
12264 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12265 "requested special purpose register"));
12267 Rn
= inst
.operands
[1].reg
;
12268 reject_bad_reg (Rn
);
12270 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12271 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12272 inst
.instruction
|= (flags
& 0x300) >> 4;
12273 inst
.instruction
|= (flags
& 0xff);
12274 inst
.instruction
|= Rn
<< 16;
12280 bfd_boolean narrow
;
12281 unsigned Rd
, Rn
, Rm
;
12283 if (!inst
.operands
[2].present
)
12284 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12286 Rd
= inst
.operands
[0].reg
;
12287 Rn
= inst
.operands
[1].reg
;
12288 Rm
= inst
.operands
[2].reg
;
12290 if (unified_syntax
)
12292 if (inst
.size_req
== 4
12298 else if (inst
.instruction
== T_MNEM_muls
)
12299 narrow
= !in_it_block ();
12301 narrow
= in_it_block ();
12305 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12306 constraint (Rn
> 7 || Rm
> 7,
12313 /* 16-bit MULS/Conditional MUL. */
12314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12315 inst
.instruction
|= Rd
;
12318 inst
.instruction
|= Rm
<< 3;
12320 inst
.instruction
|= Rn
<< 3;
12322 constraint (1, _("dest must overlap one source register"));
12326 constraint (inst
.instruction
!= T_MNEM_mul
,
12327 _("Thumb-2 MUL must not set flags"));
12329 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12330 inst
.instruction
|= Rd
<< 8;
12331 inst
.instruction
|= Rn
<< 16;
12332 inst
.instruction
|= Rm
<< 0;
12334 reject_bad_reg (Rd
);
12335 reject_bad_reg (Rn
);
12336 reject_bad_reg (Rm
);
12343 unsigned RdLo
, RdHi
, Rn
, Rm
;
12345 RdLo
= inst
.operands
[0].reg
;
12346 RdHi
= inst
.operands
[1].reg
;
12347 Rn
= inst
.operands
[2].reg
;
12348 Rm
= inst
.operands
[3].reg
;
12350 reject_bad_reg (RdLo
);
12351 reject_bad_reg (RdHi
);
12352 reject_bad_reg (Rn
);
12353 reject_bad_reg (Rm
);
12355 inst
.instruction
|= RdLo
<< 12;
12356 inst
.instruction
|= RdHi
<< 8;
12357 inst
.instruction
|= Rn
<< 16;
12358 inst
.instruction
|= Rm
;
12361 as_tsktsk (_("rdhi and rdlo must be different"));
12367 set_it_insn_type (NEUTRAL_IT_INSN
);
12369 if (unified_syntax
)
12371 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12373 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12374 inst
.instruction
|= inst
.operands
[0].imm
;
12378 /* PR9722: Check for Thumb2 availability before
12379 generating a thumb2 nop instruction. */
12380 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12382 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12383 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12386 inst
.instruction
= 0x46c0;
12391 constraint (inst
.operands
[0].present
,
12392 _("Thumb does not support NOP with hints"));
12393 inst
.instruction
= 0x46c0;
12400 if (unified_syntax
)
12402 bfd_boolean narrow
;
12404 if (THUMB_SETS_FLAGS (inst
.instruction
))
12405 narrow
= !in_it_block ();
12407 narrow
= in_it_block ();
12408 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12410 if (inst
.size_req
== 4)
12415 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12416 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12417 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12421 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12422 inst
.instruction
|= inst
.operands
[0].reg
;
12423 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12428 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12430 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12432 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12433 inst
.instruction
|= inst
.operands
[0].reg
;
12434 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12443 Rd
= inst
.operands
[0].reg
;
12444 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12446 reject_bad_reg (Rd
);
12447 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12448 reject_bad_reg (Rn
);
12450 inst
.instruction
|= Rd
<< 8;
12451 inst
.instruction
|= Rn
<< 16;
12453 if (!inst
.operands
[2].isreg
)
12455 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12456 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12462 Rm
= inst
.operands
[2].reg
;
12463 reject_bad_reg (Rm
);
12465 constraint (inst
.operands
[2].shifted
12466 && inst
.operands
[2].immisreg
,
12467 _("shift must be constant"));
12468 encode_thumb32_shifted_operand (2);
12475 unsigned Rd
, Rn
, Rm
;
12477 Rd
= inst
.operands
[0].reg
;
12478 Rn
= inst
.operands
[1].reg
;
12479 Rm
= inst
.operands
[2].reg
;
12481 reject_bad_reg (Rd
);
12482 reject_bad_reg (Rn
);
12483 reject_bad_reg (Rm
);
12485 inst
.instruction
|= Rd
<< 8;
12486 inst
.instruction
|= Rn
<< 16;
12487 inst
.instruction
|= Rm
;
12488 if (inst
.operands
[3].present
)
12490 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12491 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12492 _("expression too complex"));
12493 inst
.instruction
|= (val
& 0x1c) << 10;
12494 inst
.instruction
|= (val
& 0x03) << 6;
12501 if (!inst
.operands
[3].present
)
12505 inst
.instruction
&= ~0x00000020;
12507 /* PR 10168. Swap the Rm and Rn registers. */
12508 Rtmp
= inst
.operands
[1].reg
;
12509 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12510 inst
.operands
[2].reg
= Rtmp
;
12518 if (inst
.operands
[0].immisreg
)
12519 reject_bad_reg (inst
.operands
[0].imm
);
12521 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12525 do_t_push_pop (void)
12529 constraint (inst
.operands
[0].writeback
,
12530 _("push/pop do not support {reglist}^"));
12531 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12532 _("expression too complex"));
12534 mask
= inst
.operands
[0].imm
;
12535 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12536 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12537 else if (inst
.size_req
!= 4
12538 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12539 ? REG_LR
: REG_PC
)))
12541 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12542 inst
.instruction
|= THUMB_PP_PC_LR
;
12543 inst
.instruction
|= mask
& 0xff;
12545 else if (unified_syntax
)
12547 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12548 encode_thumb2_ldmstm (13, mask
, TRUE
);
12552 inst
.error
= _("invalid register list to push/pop instruction");
12562 Rd
= inst
.operands
[0].reg
;
12563 Rm
= inst
.operands
[1].reg
;
12565 reject_bad_reg (Rd
);
12566 reject_bad_reg (Rm
);
12568 inst
.instruction
|= Rd
<< 8;
12569 inst
.instruction
|= Rm
<< 16;
12570 inst
.instruction
|= Rm
;
12578 Rd
= inst
.operands
[0].reg
;
12579 Rm
= inst
.operands
[1].reg
;
12581 reject_bad_reg (Rd
);
12582 reject_bad_reg (Rm
);
12584 if (Rd
<= 7 && Rm
<= 7
12585 && inst
.size_req
!= 4)
12587 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12588 inst
.instruction
|= Rd
;
12589 inst
.instruction
|= Rm
<< 3;
12591 else if (unified_syntax
)
12593 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12594 inst
.instruction
|= Rd
<< 8;
12595 inst
.instruction
|= Rm
<< 16;
12596 inst
.instruction
|= Rm
;
12599 inst
.error
= BAD_HIREG
;
12607 Rd
= inst
.operands
[0].reg
;
12608 Rm
= inst
.operands
[1].reg
;
12610 reject_bad_reg (Rd
);
12611 reject_bad_reg (Rm
);
12613 inst
.instruction
|= Rd
<< 8;
12614 inst
.instruction
|= Rm
;
12622 Rd
= inst
.operands
[0].reg
;
12623 Rs
= (inst
.operands
[1].present
12624 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12625 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12627 reject_bad_reg (Rd
);
12628 reject_bad_reg (Rs
);
12629 if (inst
.operands
[2].isreg
)
12630 reject_bad_reg (inst
.operands
[2].reg
);
12632 inst
.instruction
|= Rd
<< 8;
12633 inst
.instruction
|= Rs
<< 16;
12634 if (!inst
.operands
[2].isreg
)
12636 bfd_boolean narrow
;
12638 if ((inst
.instruction
& 0x00100000) != 0)
12639 narrow
= !in_it_block ();
12641 narrow
= in_it_block ();
12643 if (Rd
> 7 || Rs
> 7)
12646 if (inst
.size_req
== 4 || !unified_syntax
)
12649 if (inst
.reloc
.exp
.X_op
!= O_constant
12650 || inst
.reloc
.exp
.X_add_number
!= 0)
12653 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12654 relaxation, but it doesn't seem worth the hassle. */
12657 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12658 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12659 inst
.instruction
|= Rs
<< 3;
12660 inst
.instruction
|= Rd
;
12664 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12665 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12669 encode_thumb32_shifted_operand (2);
12675 if (warn_on_deprecated
12676 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12677 as_tsktsk (_("setend use is deprecated for ARMv8"));
12679 set_it_insn_type (OUTSIDE_IT_INSN
);
12680 if (inst
.operands
[0].imm
)
12681 inst
.instruction
|= 0x8;
12687 if (!inst
.operands
[1].present
)
12688 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12690 if (unified_syntax
)
12692 bfd_boolean narrow
;
12695 switch (inst
.instruction
)
12698 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12700 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12702 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12704 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12708 if (THUMB_SETS_FLAGS (inst
.instruction
))
12709 narrow
= !in_it_block ();
12711 narrow
= in_it_block ();
12712 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12714 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12716 if (inst
.operands
[2].isreg
12717 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12718 || inst
.operands
[2].reg
> 7))
12720 if (inst
.size_req
== 4)
12723 reject_bad_reg (inst
.operands
[0].reg
);
12724 reject_bad_reg (inst
.operands
[1].reg
);
12728 if (inst
.operands
[2].isreg
)
12730 reject_bad_reg (inst
.operands
[2].reg
);
12731 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12732 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12733 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12734 inst
.instruction
|= inst
.operands
[2].reg
;
12736 /* PR 12854: Error on extraneous shifts. */
12737 constraint (inst
.operands
[2].shifted
,
12738 _("extraneous shift as part of operand to shift insn"));
12742 inst
.operands
[1].shifted
= 1;
12743 inst
.operands
[1].shift_kind
= shift_kind
;
12744 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12745 ? T_MNEM_movs
: T_MNEM_mov
);
12746 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12747 encode_thumb32_shifted_operand (1);
12748 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12749 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12754 if (inst
.operands
[2].isreg
)
12756 switch (shift_kind
)
12758 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12759 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12760 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12761 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12765 inst
.instruction
|= inst
.operands
[0].reg
;
12766 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12768 /* PR 12854: Error on extraneous shifts. */
12769 constraint (inst
.operands
[2].shifted
,
12770 _("extraneous shift as part of operand to shift insn"));
12774 switch (shift_kind
)
12776 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12777 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12778 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12781 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12782 inst
.instruction
|= inst
.operands
[0].reg
;
12783 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12789 constraint (inst
.operands
[0].reg
> 7
12790 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12791 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12793 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12795 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12796 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12797 _("source1 and dest must be same register"));
12799 switch (inst
.instruction
)
12801 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12802 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12803 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12804 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12808 inst
.instruction
|= inst
.operands
[0].reg
;
12809 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12811 /* PR 12854: Error on extraneous shifts. */
12812 constraint (inst
.operands
[2].shifted
,
12813 _("extraneous shift as part of operand to shift insn"));
12817 switch (inst
.instruction
)
12819 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12820 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12821 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12822 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12825 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12826 inst
.instruction
|= inst
.operands
[0].reg
;
12827 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12835 unsigned Rd
, Rn
, Rm
;
12837 Rd
= inst
.operands
[0].reg
;
12838 Rn
= inst
.operands
[1].reg
;
12839 Rm
= inst
.operands
[2].reg
;
12841 reject_bad_reg (Rd
);
12842 reject_bad_reg (Rn
);
12843 reject_bad_reg (Rm
);
12845 inst
.instruction
|= Rd
<< 8;
12846 inst
.instruction
|= Rn
<< 16;
12847 inst
.instruction
|= Rm
;
12853 unsigned Rd
, Rn
, Rm
;
12855 Rd
= inst
.operands
[0].reg
;
12856 Rm
= inst
.operands
[1].reg
;
12857 Rn
= inst
.operands
[2].reg
;
12859 reject_bad_reg (Rd
);
12860 reject_bad_reg (Rn
);
12861 reject_bad_reg (Rm
);
12863 inst
.instruction
|= Rd
<< 8;
12864 inst
.instruction
|= Rn
<< 16;
12865 inst
.instruction
|= Rm
;
12871 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12872 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12873 _("SMC is not permitted on this architecture"));
12874 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12875 _("expression too complex"));
12876 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12877 inst
.instruction
|= (value
& 0xf000) >> 12;
12878 inst
.instruction
|= (value
& 0x0ff0);
12879 inst
.instruction
|= (value
& 0x000f) << 16;
12880 /* PR gas/15623: SMC instructions must be last in an IT block. */
12881 set_it_insn_type_last ();
12887 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12889 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12890 inst
.instruction
|= (value
& 0x0fff);
12891 inst
.instruction
|= (value
& 0xf000) << 4;
12895 do_t_ssat_usat (int bias
)
12899 Rd
= inst
.operands
[0].reg
;
12900 Rn
= inst
.operands
[2].reg
;
12902 reject_bad_reg (Rd
);
12903 reject_bad_reg (Rn
);
12905 inst
.instruction
|= Rd
<< 8;
12906 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12907 inst
.instruction
|= Rn
<< 16;
12909 if (inst
.operands
[3].present
)
12911 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12913 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12915 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12916 _("expression too complex"));
12918 if (shift_amount
!= 0)
12920 constraint (shift_amount
> 31,
12921 _("shift expression is too large"));
12923 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12924 inst
.instruction
|= 0x00200000; /* sh bit. */
12926 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12927 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12935 do_t_ssat_usat (1);
12943 Rd
= inst
.operands
[0].reg
;
12944 Rn
= inst
.operands
[2].reg
;
12946 reject_bad_reg (Rd
);
12947 reject_bad_reg (Rn
);
12949 inst
.instruction
|= Rd
<< 8;
12950 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12951 inst
.instruction
|= Rn
<< 16;
12957 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12958 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12959 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12960 || inst
.operands
[2].negative
,
12963 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12965 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12966 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12967 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12968 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12974 if (!inst
.operands
[2].present
)
12975 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12977 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12978 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12979 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12982 inst
.instruction
|= inst
.operands
[0].reg
;
12983 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12984 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12985 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12991 unsigned Rd
, Rn
, Rm
;
12993 Rd
= inst
.operands
[0].reg
;
12994 Rn
= inst
.operands
[1].reg
;
12995 Rm
= inst
.operands
[2].reg
;
12997 reject_bad_reg (Rd
);
12998 reject_bad_reg (Rn
);
12999 reject_bad_reg (Rm
);
13001 inst
.instruction
|= Rd
<< 8;
13002 inst
.instruction
|= Rn
<< 16;
13003 inst
.instruction
|= Rm
;
13004 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13012 Rd
= inst
.operands
[0].reg
;
13013 Rm
= inst
.operands
[1].reg
;
13015 reject_bad_reg (Rd
);
13016 reject_bad_reg (Rm
);
13018 if (inst
.instruction
<= 0xffff
13019 && inst
.size_req
!= 4
13020 && Rd
<= 7 && Rm
<= 7
13021 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13023 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13024 inst
.instruction
|= Rd
;
13025 inst
.instruction
|= Rm
<< 3;
13027 else if (unified_syntax
)
13029 if (inst
.instruction
<= 0xffff)
13030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13031 inst
.instruction
|= Rd
<< 8;
13032 inst
.instruction
|= Rm
;
13033 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13037 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13038 _("Thumb encoding does not support rotation"));
13039 constraint (1, BAD_HIREG
);
13046 /* We have to do the following check manually as ARM_EXT_OS only applies
13048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13051 /* This only applies to the v6m howver, not later architectures. */
13052 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13053 as_bad (_("SVC is not permitted on this architecture"));
13054 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13057 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13066 half
= (inst
.instruction
& 0x10) != 0;
13067 set_it_insn_type_last ();
13068 constraint (inst
.operands
[0].immisreg
,
13069 _("instruction requires register index"));
13071 Rn
= inst
.operands
[0].reg
;
13072 Rm
= inst
.operands
[0].imm
;
13074 constraint (Rn
== REG_SP
, BAD_SP
);
13075 reject_bad_reg (Rm
);
13077 constraint (!half
&& inst
.operands
[0].shifted
,
13078 _("instruction does not allow shifted index"));
13079 inst
.instruction
|= (Rn
<< 16) | Rm
;
13085 if (!inst
.operands
[0].present
)
13086 inst
.operands
[0].imm
= 0;
13088 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13090 constraint (inst
.size_req
== 2,
13091 _("immediate value out of range"));
13092 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13093 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13094 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13098 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13099 inst
.instruction
|= inst
.operands
[0].imm
;
13102 set_it_insn_type (NEUTRAL_IT_INSN
);
13109 do_t_ssat_usat (0);
13117 Rd
= inst
.operands
[0].reg
;
13118 Rn
= inst
.operands
[2].reg
;
13120 reject_bad_reg (Rd
);
13121 reject_bad_reg (Rn
);
13123 inst
.instruction
|= Rd
<< 8;
13124 inst
.instruction
|= inst
.operands
[1].imm
;
13125 inst
.instruction
|= Rn
<< 16;
13128 /* Neon instruction encoder helpers. */
13130 /* Encodings for the different types for various Neon opcodes. */
13132 /* An "invalid" code for the following tables. */
13135 struct neon_tab_entry
13138 unsigned float_or_poly
;
13139 unsigned scalar_or_imm
;
13142 /* Map overloaded Neon opcodes to their respective encodings. */
13143 #define NEON_ENC_TAB \
13144 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13145 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13146 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13147 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13148 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13149 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13150 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13151 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13152 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13153 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13154 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13155 /* Register variants of the following two instructions are encoded as
13156 vcge / vcgt with the operands reversed. */ \
13157 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13158 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13159 X(vfma, N_INV, 0x0000c10, N_INV), \
13160 X(vfms, N_INV, 0x0200c10, N_INV), \
13161 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13162 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13163 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13164 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13165 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13166 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13167 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13168 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13169 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13170 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13171 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13172 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13173 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13174 X(vshl, 0x0000400, N_INV, 0x0800510), \
13175 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13176 X(vand, 0x0000110, N_INV, 0x0800030), \
13177 X(vbic, 0x0100110, N_INV, 0x0800030), \
13178 X(veor, 0x1000110, N_INV, N_INV), \
13179 X(vorn, 0x0300110, N_INV, 0x0800010), \
13180 X(vorr, 0x0200110, N_INV, 0x0800010), \
13181 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13182 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13183 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13184 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13185 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13186 X(vst1, 0x0000000, 0x0800000, N_INV), \
13187 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13188 X(vst2, 0x0000100, 0x0800100, N_INV), \
13189 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13190 X(vst3, 0x0000200, 0x0800200, N_INV), \
13191 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13192 X(vst4, 0x0000300, 0x0800300, N_INV), \
13193 X(vmovn, 0x1b20200, N_INV, N_INV), \
13194 X(vtrn, 0x1b20080, N_INV, N_INV), \
13195 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13196 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13197 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13198 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13199 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13200 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13201 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13202 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13203 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13204 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13205 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13206 X(vseleq, 0xe000a00, N_INV, N_INV), \
13207 X(vselvs, 0xe100a00, N_INV, N_INV), \
13208 X(vselge, 0xe200a00, N_INV, N_INV), \
13209 X(vselgt, 0xe300a00, N_INV, N_INV), \
13210 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13211 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13212 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13213 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13214 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13215 X(aes, 0x3b00300, N_INV, N_INV), \
13216 X(sha3op, 0x2000c00, N_INV, N_INV), \
13217 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13218 X(sha2op, 0x3ba0380, N_INV, N_INV)
13222 #define X(OPC,I,F,S) N_MNEM_##OPC
13227 static const struct neon_tab_entry neon_enc_tab
[] =
13229 #define X(OPC,I,F,S) { (I), (F), (S) }
13234 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13235 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13236 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13237 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13238 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13239 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13240 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13241 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13242 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13243 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13244 #define NEON_ENC_SINGLE_(X) \
13245 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13246 #define NEON_ENC_DOUBLE_(X) \
13247 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13248 #define NEON_ENC_FPV8_(X) \
13249 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13251 #define NEON_ENCODE(type, inst) \
13254 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13255 inst.is_neon = 1; \
13259 #define check_neon_suffixes \
13262 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13264 as_bad (_("invalid neon suffix for non neon instruction")); \
13270 /* Define shapes for instruction operands. The following mnemonic characters
13271 are used in this table:
13273 F - VFP S<n> register
13274 D - Neon D<n> register
13275 Q - Neon Q<n> register
13279 L - D<n> register list
13281 This table is used to generate various data:
13282 - enumerations of the form NS_DDR to be used as arguments to
13284 - a table classifying shapes into single, double, quad, mixed.
13285 - a table used to drive neon_select_shape. */
13287 #define NEON_SHAPE_DEF \
13288 X(3, (D, D, D), DOUBLE), \
13289 X(3, (Q, Q, Q), QUAD), \
13290 X(3, (D, D, I), DOUBLE), \
13291 X(3, (Q, Q, I), QUAD), \
13292 X(3, (D, D, S), DOUBLE), \
13293 X(3, (Q, Q, S), QUAD), \
13294 X(2, (D, D), DOUBLE), \
13295 X(2, (Q, Q), QUAD), \
13296 X(2, (D, S), DOUBLE), \
13297 X(2, (Q, S), QUAD), \
13298 X(2, (D, R), DOUBLE), \
13299 X(2, (Q, R), QUAD), \
13300 X(2, (D, I), DOUBLE), \
13301 X(2, (Q, I), QUAD), \
13302 X(3, (D, L, D), DOUBLE), \
13303 X(2, (D, Q), MIXED), \
13304 X(2, (Q, D), MIXED), \
13305 X(3, (D, Q, I), MIXED), \
13306 X(3, (Q, D, I), MIXED), \
13307 X(3, (Q, D, D), MIXED), \
13308 X(3, (D, Q, Q), MIXED), \
13309 X(3, (Q, Q, D), MIXED), \
13310 X(3, (Q, D, S), MIXED), \
13311 X(3, (D, Q, S), MIXED), \
13312 X(4, (D, D, D, I), DOUBLE), \
13313 X(4, (Q, Q, Q, I), QUAD), \
13314 X(2, (F, F), SINGLE), \
13315 X(3, (F, F, F), SINGLE), \
13316 X(2, (F, I), SINGLE), \
13317 X(2, (F, D), MIXED), \
13318 X(2, (D, F), MIXED), \
13319 X(3, (F, F, I), MIXED), \
13320 X(4, (R, R, F, F), SINGLE), \
13321 X(4, (F, F, R, R), SINGLE), \
13322 X(3, (D, R, R), DOUBLE), \
13323 X(3, (R, R, D), DOUBLE), \
13324 X(2, (S, R), SINGLE), \
13325 X(2, (R, S), SINGLE), \
13326 X(2, (F, R), SINGLE), \
13327 X(2, (R, F), SINGLE), \
13328 /* Half float shape supported so far. */\
13329 X (2, (H, D), MIXED), \
13330 X (2, (D, H), MIXED), \
13331 X (2, (H, F), MIXED), \
13332 X (2, (F, H), MIXED), \
13333 X (2, (H, H), HALF), \
13334 X (2, (H, R), HALF), \
13335 X (2, (R, H), HALF), \
13336 X (2, (H, I), HALF), \
13337 X (3, (H, H, H), HALF), \
13338 X (3, (H, F, I), MIXED), \
13339 X (3, (F, H, I), MIXED)
13341 #define S2(A,B) NS_##A##B
13342 #define S3(A,B,C) NS_##A##B##C
13343 #define S4(A,B,C,D) NS_##A##B##C##D
13345 #define X(N, L, C) S##N L
13358 enum neon_shape_class
13367 #define X(N, L, C) SC_##C
13369 static enum neon_shape_class neon_shape_class
[] =
13388 /* Register widths of above. */
13389 static unsigned neon_shape_el_size
[] =
13401 struct neon_shape_info
13404 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13407 #define S2(A,B) { SE_##A, SE_##B }
13408 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13409 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13411 #define X(N, L, C) { N, S##N L }
13413 static struct neon_shape_info neon_shape_tab
[] =
13423 /* Bit masks used in type checking given instructions.
13424 'N_EQK' means the type must be the same as (or based on in some way) the key
13425 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13426 set, various other bits can be set as well in order to modify the meaning of
13427 the type constraint. */
13429 enum neon_type_mask
13453 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13454 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13455 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13456 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13457 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13458 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13459 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13460 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13461 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13462 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13463 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13465 N_MAX_NONSPECIAL
= N_P64
13468 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13470 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13471 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13472 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13473 #define N_S_32 (N_S8 | N_S16 | N_S32)
13474 #define N_F_16_32 (N_F16 | N_F32)
13475 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13476 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13477 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13478 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13480 /* Pass this as the first type argument to neon_check_type to ignore types
13482 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13484 /* Select a "shape" for the current instruction (describing register types or
13485 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13486 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13487 function of operand parsing, so this function doesn't need to be called.
13488 Shapes should be listed in order of decreasing length. */
13490 static enum neon_shape
13491 neon_select_shape (enum neon_shape shape
, ...)
13494 enum neon_shape first_shape
= shape
;
13496 /* Fix missing optional operands. FIXME: we don't know at this point how
13497 many arguments we should have, so this makes the assumption that we have
13498 > 1. This is true of all current Neon opcodes, I think, but may not be
13499 true in the future. */
13500 if (!inst
.operands
[1].present
)
13501 inst
.operands
[1] = inst
.operands
[0];
13503 va_start (ap
, shape
);
13505 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13510 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13512 if (!inst
.operands
[j
].present
)
13518 switch (neon_shape_tab
[shape
].el
[j
])
13520 /* If a .f16, .16, .u16, .s16 type specifier is given over
13521 a VFP single precision register operand, it's essentially
13522 means only half of the register is used.
13524 If the type specifier is given after the mnemonics, the
13525 information is stored in inst.vectype. If the type specifier
13526 is given after register operand, the information is stored
13527 in inst.operands[].vectype.
13529 When there is only one type specifier, and all the register
13530 operands are the same type of hardware register, the type
13531 specifier applies to all register operands.
13533 If no type specifier is given, the shape is inferred from
13534 operand information.
13537 vadd.f16 s0, s1, s2: NS_HHH
13538 vabs.f16 s0, s1: NS_HH
13539 vmov.f16 s0, r1: NS_HR
13540 vmov.f16 r0, s1: NS_RH
13541 vcvt.f16 r0, s1: NS_RH
13542 vcvt.f16.s32 s2, s2, #29: NS_HFI
13543 vcvt.f16.s32 s2, s2: NS_HF
13546 if (!(inst
.operands
[j
].isreg
13547 && inst
.operands
[j
].isvec
13548 && inst
.operands
[j
].issingle
13549 && !inst
.operands
[j
].isquad
13550 && ((inst
.vectype
.elems
== 1
13551 && inst
.vectype
.el
[0].size
== 16)
13552 || (inst
.vectype
.elems
> 1
13553 && inst
.vectype
.el
[j
].size
== 16)
13554 || (inst
.vectype
.elems
== 0
13555 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13556 && inst
.operands
[j
].vectype
.size
== 16))))
13561 if (!(inst
.operands
[j
].isreg
13562 && inst
.operands
[j
].isvec
13563 && inst
.operands
[j
].issingle
13564 && !inst
.operands
[j
].isquad
13565 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13566 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13567 || (inst
.vectype
.elems
== 0
13568 && (inst
.operands
[j
].vectype
.size
== 32
13569 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13574 if (!(inst
.operands
[j
].isreg
13575 && inst
.operands
[j
].isvec
13576 && !inst
.operands
[j
].isquad
13577 && !inst
.operands
[j
].issingle
))
13582 if (!(inst
.operands
[j
].isreg
13583 && !inst
.operands
[j
].isvec
))
13588 if (!(inst
.operands
[j
].isreg
13589 && inst
.operands
[j
].isvec
13590 && inst
.operands
[j
].isquad
13591 && !inst
.operands
[j
].issingle
))
13596 if (!(!inst
.operands
[j
].isreg
13597 && !inst
.operands
[j
].isscalar
))
13602 if (!(!inst
.operands
[j
].isreg
13603 && inst
.operands
[j
].isscalar
))
13613 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13614 /* We've matched all the entries in the shape table, and we don't
13615 have any left over operands which have not been matched. */
13621 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13622 first_error (_("invalid instruction shape"));
13627 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13628 means the Q bit should be set). */
13631 neon_quad (enum neon_shape shape
)
13633 return neon_shape_class
[shape
] == SC_QUAD
;
13637 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13640 /* Allow modification to be made to types which are constrained to be
13641 based on the key element, based on bits set alongside N_EQK. */
13642 if ((typebits
& N_EQK
) != 0)
13644 if ((typebits
& N_HLF
) != 0)
13646 else if ((typebits
& N_DBL
) != 0)
13648 if ((typebits
& N_SGN
) != 0)
13649 *g_type
= NT_signed
;
13650 else if ((typebits
& N_UNS
) != 0)
13651 *g_type
= NT_unsigned
;
13652 else if ((typebits
& N_INT
) != 0)
13653 *g_type
= NT_integer
;
13654 else if ((typebits
& N_FLT
) != 0)
13655 *g_type
= NT_float
;
13656 else if ((typebits
& N_SIZ
) != 0)
13657 *g_type
= NT_untyped
;
13661 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13662 operand type, i.e. the single type specified in a Neon instruction when it
13663 is the only one given. */
13665 static struct neon_type_el
13666 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13668 struct neon_type_el dest
= *key
;
13670 gas_assert ((thisarg
& N_EQK
) != 0);
13672 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13677 /* Convert Neon type and size into compact bitmask representation. */
13679 static enum neon_type_mask
13680 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13687 case 8: return N_8
;
13688 case 16: return N_16
;
13689 case 32: return N_32
;
13690 case 64: return N_64
;
13698 case 8: return N_I8
;
13699 case 16: return N_I16
;
13700 case 32: return N_I32
;
13701 case 64: return N_I64
;
13709 case 16: return N_F16
;
13710 case 32: return N_F32
;
13711 case 64: return N_F64
;
13719 case 8: return N_P8
;
13720 case 16: return N_P16
;
13721 case 64: return N_P64
;
13729 case 8: return N_S8
;
13730 case 16: return N_S16
;
13731 case 32: return N_S32
;
13732 case 64: return N_S64
;
13740 case 8: return N_U8
;
13741 case 16: return N_U16
;
13742 case 32: return N_U32
;
13743 case 64: return N_U64
;
13754 /* Convert compact Neon bitmask type representation to a type and size. Only
13755 handles the case where a single bit is set in the mask. */
13758 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13759 enum neon_type_mask mask
)
13761 if ((mask
& N_EQK
) != 0)
13764 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13766 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13768 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13770 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13775 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13777 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13778 *type
= NT_unsigned
;
13779 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13780 *type
= NT_integer
;
13781 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13782 *type
= NT_untyped
;
13783 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13785 else if ((mask
& (N_F_ALL
)) != 0)
13793 /* Modify a bitmask of allowed types. This is only needed for type
13797 modify_types_allowed (unsigned allowed
, unsigned mods
)
13800 enum neon_el_type type
;
13806 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13808 if (el_type_of_type_chk (&type
, &size
,
13809 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13811 neon_modify_type_size (mods
, &type
, &size
);
13812 destmask
|= type_chk_of_el_type (type
, size
);
13819 /* Check type and return type classification.
13820 The manual states (paraphrase): If one datatype is given, it indicates the
13822 - the second operand, if there is one
13823 - the operand, if there is no second operand
13824 - the result, if there are no operands.
13825 This isn't quite good enough though, so we use a concept of a "key" datatype
13826 which is set on a per-instruction basis, which is the one which matters when
13827 only one data type is written.
13828 Note: this function has side-effects (e.g. filling in missing operands). All
13829 Neon instructions should call it before performing bit encoding. */
13831 static struct neon_type_el
13832 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13835 unsigned i
, pass
, key_el
= 0;
13836 unsigned types
[NEON_MAX_TYPE_ELS
];
13837 enum neon_el_type k_type
= NT_invtype
;
13838 unsigned k_size
= -1u;
13839 struct neon_type_el badtype
= {NT_invtype
, -1};
13840 unsigned key_allowed
= 0;
13842 /* Optional registers in Neon instructions are always (not) in operand 1.
13843 Fill in the missing operand here, if it was omitted. */
13844 if (els
> 1 && !inst
.operands
[1].present
)
13845 inst
.operands
[1] = inst
.operands
[0];
13847 /* Suck up all the varargs. */
13849 for (i
= 0; i
< els
; i
++)
13851 unsigned thisarg
= va_arg (ap
, unsigned);
13852 if (thisarg
== N_IGNORE_TYPE
)
13857 types
[i
] = thisarg
;
13858 if ((thisarg
& N_KEY
) != 0)
13863 if (inst
.vectype
.elems
> 0)
13864 for (i
= 0; i
< els
; i
++)
13865 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13867 first_error (_("types specified in both the mnemonic and operands"));
13871 /* Duplicate inst.vectype elements here as necessary.
13872 FIXME: No idea if this is exactly the same as the ARM assembler,
13873 particularly when an insn takes one register and one non-register
13875 if (inst
.vectype
.elems
== 1 && els
> 1)
13878 inst
.vectype
.elems
= els
;
13879 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13880 for (j
= 0; j
< els
; j
++)
13882 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13885 else if (inst
.vectype
.elems
== 0 && els
> 0)
13888 /* No types were given after the mnemonic, so look for types specified
13889 after each operand. We allow some flexibility here; as long as the
13890 "key" operand has a type, we can infer the others. */
13891 for (j
= 0; j
< els
; j
++)
13892 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13893 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13895 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13897 for (j
= 0; j
< els
; j
++)
13898 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13899 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13904 first_error (_("operand types can't be inferred"));
13908 else if (inst
.vectype
.elems
!= els
)
13910 first_error (_("type specifier has the wrong number of parts"));
13914 for (pass
= 0; pass
< 2; pass
++)
13916 for (i
= 0; i
< els
; i
++)
13918 unsigned thisarg
= types
[i
];
13919 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13920 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13921 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13922 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13924 /* Decay more-specific signed & unsigned types to sign-insensitive
13925 integer types if sign-specific variants are unavailable. */
13926 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13927 && (types_allowed
& N_SU_ALL
) == 0)
13928 g_type
= NT_integer
;
13930 /* If only untyped args are allowed, decay any more specific types to
13931 them. Some instructions only care about signs for some element
13932 sizes, so handle that properly. */
13933 if (((types_allowed
& N_UNT
) == 0)
13934 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13935 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13936 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13937 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13938 g_type
= NT_untyped
;
13942 if ((thisarg
& N_KEY
) != 0)
13946 key_allowed
= thisarg
& ~N_KEY
;
13948 /* Check architecture constraint on FP16 extension. */
13950 && k_type
== NT_float
13951 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13953 inst
.error
= _(BAD_FP16
);
13960 if ((thisarg
& N_VFP
) != 0)
13962 enum neon_shape_el regshape
;
13963 unsigned regwidth
, match
;
13965 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13968 first_error (_("invalid instruction shape"));
13971 regshape
= neon_shape_tab
[ns
].el
[i
];
13972 regwidth
= neon_shape_el_size
[regshape
];
13974 /* In VFP mode, operands must match register widths. If we
13975 have a key operand, use its width, else use the width of
13976 the current operand. */
13982 /* FP16 will use a single precision register. */
13983 if (regwidth
== 32 && match
== 16)
13985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13989 inst
.error
= _(BAD_FP16
);
13994 if (regwidth
!= match
)
13996 first_error (_("operand size must match register width"));
14001 if ((thisarg
& N_EQK
) == 0)
14003 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14005 if ((given_type
& types_allowed
) == 0)
14007 first_error (_("bad type in Neon instruction"));
14013 enum neon_el_type mod_k_type
= k_type
;
14014 unsigned mod_k_size
= k_size
;
14015 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14016 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14018 first_error (_("inconsistent types in Neon instruction"));
14026 return inst
.vectype
.el
[key_el
];
14029 /* Neon-style VFP instruction forwarding. */
14031 /* Thumb VFP instructions have 0xE in the condition field. */
14034 do_vfp_cond_or_thumb (void)
14039 inst
.instruction
|= 0xe0000000;
14041 inst
.instruction
|= inst
.cond
<< 28;
14044 /* Look up and encode a simple mnemonic, for use as a helper function for the
14045 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14046 etc. It is assumed that operand parsing has already been done, and that the
14047 operands are in the form expected by the given opcode (this isn't necessarily
14048 the same as the form in which they were parsed, hence some massaging must
14049 take place before this function is called).
14050 Checks current arch version against that in the looked-up opcode. */
14053 do_vfp_nsyn_opcode (const char *opname
)
14055 const struct asm_opcode
*opcode
;
14057 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14063 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14070 inst
.instruction
= opcode
->tvalue
;
14071 opcode
->tencode ();
14075 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14076 opcode
->aencode ();
14081 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14083 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14085 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14088 do_vfp_nsyn_opcode ("fadds");
14090 do_vfp_nsyn_opcode ("fsubs");
14092 /* ARMv8.2 fp16 instruction. */
14094 do_scalar_fp16_v82_encode ();
14099 do_vfp_nsyn_opcode ("faddd");
14101 do_vfp_nsyn_opcode ("fsubd");
14105 /* Check operand types to see if this is a VFP instruction, and if so call
14109 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14111 enum neon_shape rs
;
14112 struct neon_type_el et
;
14117 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14118 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14122 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14123 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14124 N_F_ALL
| N_KEY
| N_VFP
);
14131 if (et
.type
!= NT_invtype
)
14142 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14144 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14146 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14149 do_vfp_nsyn_opcode ("fmacs");
14151 do_vfp_nsyn_opcode ("fnmacs");
14153 /* ARMv8.2 fp16 instruction. */
14155 do_scalar_fp16_v82_encode ();
14160 do_vfp_nsyn_opcode ("fmacd");
14162 do_vfp_nsyn_opcode ("fnmacd");
14167 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14169 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14171 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14174 do_vfp_nsyn_opcode ("ffmas");
14176 do_vfp_nsyn_opcode ("ffnmas");
14178 /* ARMv8.2 fp16 instruction. */
14180 do_scalar_fp16_v82_encode ();
14185 do_vfp_nsyn_opcode ("ffmad");
14187 do_vfp_nsyn_opcode ("ffnmad");
14192 do_vfp_nsyn_mul (enum neon_shape rs
)
14194 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14196 do_vfp_nsyn_opcode ("fmuls");
14198 /* ARMv8.2 fp16 instruction. */
14200 do_scalar_fp16_v82_encode ();
14203 do_vfp_nsyn_opcode ("fmuld");
14207 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14209 int is_neg
= (inst
.instruction
& 0x80) != 0;
14210 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14212 if (rs
== NS_FF
|| rs
== NS_HH
)
14215 do_vfp_nsyn_opcode ("fnegs");
14217 do_vfp_nsyn_opcode ("fabss");
14219 /* ARMv8.2 fp16 instruction. */
14221 do_scalar_fp16_v82_encode ();
14226 do_vfp_nsyn_opcode ("fnegd");
14228 do_vfp_nsyn_opcode ("fabsd");
14232 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14233 insns belong to Neon, and are handled elsewhere. */
14236 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14238 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14242 do_vfp_nsyn_opcode ("fldmdbs");
14244 do_vfp_nsyn_opcode ("fldmias");
14249 do_vfp_nsyn_opcode ("fstmdbs");
14251 do_vfp_nsyn_opcode ("fstmias");
14256 do_vfp_nsyn_sqrt (void)
14258 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14259 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14261 if (rs
== NS_FF
|| rs
== NS_HH
)
14263 do_vfp_nsyn_opcode ("fsqrts");
14265 /* ARMv8.2 fp16 instruction. */
14267 do_scalar_fp16_v82_encode ();
14270 do_vfp_nsyn_opcode ("fsqrtd");
14274 do_vfp_nsyn_div (void)
14276 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14277 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14278 N_F_ALL
| N_KEY
| N_VFP
);
14280 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14282 do_vfp_nsyn_opcode ("fdivs");
14284 /* ARMv8.2 fp16 instruction. */
14286 do_scalar_fp16_v82_encode ();
14289 do_vfp_nsyn_opcode ("fdivd");
14293 do_vfp_nsyn_nmul (void)
14295 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14296 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14297 N_F_ALL
| N_KEY
| N_VFP
);
14299 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14301 NEON_ENCODE (SINGLE
, inst
);
14302 do_vfp_sp_dyadic ();
14304 /* ARMv8.2 fp16 instruction. */
14306 do_scalar_fp16_v82_encode ();
14310 NEON_ENCODE (DOUBLE
, inst
);
14311 do_vfp_dp_rd_rn_rm ();
14313 do_vfp_cond_or_thumb ();
14318 do_vfp_nsyn_cmp (void)
14320 enum neon_shape rs
;
14321 if (inst
.operands
[1].isreg
)
14323 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14324 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14326 if (rs
== NS_FF
|| rs
== NS_HH
)
14328 NEON_ENCODE (SINGLE
, inst
);
14329 do_vfp_sp_monadic ();
14333 NEON_ENCODE (DOUBLE
, inst
);
14334 do_vfp_dp_rd_rm ();
14339 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14340 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14342 switch (inst
.instruction
& 0x0fffffff)
14345 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14348 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14354 if (rs
== NS_FI
|| rs
== NS_HI
)
14356 NEON_ENCODE (SINGLE
, inst
);
14357 do_vfp_sp_compare_z ();
14361 NEON_ENCODE (DOUBLE
, inst
);
14365 do_vfp_cond_or_thumb ();
14367 /* ARMv8.2 fp16 instruction. */
14368 if (rs
== NS_HI
|| rs
== NS_HH
)
14369 do_scalar_fp16_v82_encode ();
14373 nsyn_insert_sp (void)
14375 inst
.operands
[1] = inst
.operands
[0];
14376 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14377 inst
.operands
[0].reg
= REG_SP
;
14378 inst
.operands
[0].isreg
= 1;
14379 inst
.operands
[0].writeback
= 1;
14380 inst
.operands
[0].present
= 1;
14384 do_vfp_nsyn_push (void)
14387 if (inst
.operands
[1].issingle
)
14388 do_vfp_nsyn_opcode ("fstmdbs");
14390 do_vfp_nsyn_opcode ("fstmdbd");
14394 do_vfp_nsyn_pop (void)
14397 if (inst
.operands
[1].issingle
)
14398 do_vfp_nsyn_opcode ("fldmias");
14400 do_vfp_nsyn_opcode ("fldmiad");
14403 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14404 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14407 neon_dp_fixup (struct arm_it
* insn
)
14409 unsigned int i
= insn
->instruction
;
14414 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14425 insn
->instruction
= i
;
14428 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14432 neon_logbits (unsigned x
)
14434 return ffs (x
) - 4;
14437 #define LOW4(R) ((R) & 0xf)
14438 #define HI1(R) (((R) >> 4) & 1)
14440 /* Encode insns with bit pattern:
14442 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14443 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14445 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14446 different meaning for some instruction. */
14449 neon_three_same (int isquad
, int ubit
, int size
)
14451 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14453 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14455 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14456 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14457 inst
.instruction
|= (isquad
!= 0) << 6;
14458 inst
.instruction
|= (ubit
!= 0) << 24;
14460 inst
.instruction
|= neon_logbits (size
) << 20;
14462 neon_dp_fixup (&inst
);
14465 /* Encode instructions of the form:
14467 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14468 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14470 Don't write size if SIZE == -1. */
14473 neon_two_same (int qbit
, int ubit
, int size
)
14475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14479 inst
.instruction
|= (qbit
!= 0) << 6;
14480 inst
.instruction
|= (ubit
!= 0) << 24;
14483 inst
.instruction
|= neon_logbits (size
) << 18;
14485 neon_dp_fixup (&inst
);
14488 /* Neon instruction encoders, in approximate order of appearance. */
14491 do_neon_dyadic_i_su (void)
14493 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14494 struct neon_type_el et
= neon_check_type (3, rs
,
14495 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14496 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14500 do_neon_dyadic_i64_su (void)
14502 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14503 struct neon_type_el et
= neon_check_type (3, rs
,
14504 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14505 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14509 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14512 unsigned size
= et
.size
>> 3;
14513 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14514 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14515 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14516 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14517 inst
.instruction
|= (isquad
!= 0) << 6;
14518 inst
.instruction
|= immbits
<< 16;
14519 inst
.instruction
|= (size
>> 3) << 7;
14520 inst
.instruction
|= (size
& 0x7) << 19;
14522 inst
.instruction
|= (uval
!= 0) << 24;
14524 neon_dp_fixup (&inst
);
14528 do_neon_shl_imm (void)
14530 if (!inst
.operands
[2].isreg
)
14532 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14533 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14534 int imm
= inst
.operands
[2].imm
;
14536 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14537 _("immediate out of range for shift"));
14538 NEON_ENCODE (IMMED
, inst
);
14539 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14543 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14544 struct neon_type_el et
= neon_check_type (3, rs
,
14545 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14548 /* VSHL/VQSHL 3-register variants have syntax such as:
14550 whereas other 3-register operations encoded by neon_three_same have
14553 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14555 tmp
= inst
.operands
[2].reg
;
14556 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14557 inst
.operands
[1].reg
= tmp
;
14558 NEON_ENCODE (INTEGER
, inst
);
14559 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14564 do_neon_qshl_imm (void)
14566 if (!inst
.operands
[2].isreg
)
14568 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14569 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14570 int imm
= inst
.operands
[2].imm
;
14572 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14573 _("immediate out of range for shift"));
14574 NEON_ENCODE (IMMED
, inst
);
14575 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14579 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14580 struct neon_type_el et
= neon_check_type (3, rs
,
14581 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14584 /* See note in do_neon_shl_imm. */
14585 tmp
= inst
.operands
[2].reg
;
14586 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14587 inst
.operands
[1].reg
= tmp
;
14588 NEON_ENCODE (INTEGER
, inst
);
14589 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14594 do_neon_rshl (void)
14596 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14597 struct neon_type_el et
= neon_check_type (3, rs
,
14598 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14601 tmp
= inst
.operands
[2].reg
;
14602 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14603 inst
.operands
[1].reg
= tmp
;
14604 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14608 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14610 /* Handle .I8 pseudo-instructions. */
14613 /* Unfortunately, this will make everything apart from zero out-of-range.
14614 FIXME is this the intended semantics? There doesn't seem much point in
14615 accepting .I8 if so. */
14616 immediate
|= immediate
<< 8;
14622 if (immediate
== (immediate
& 0x000000ff))
14624 *immbits
= immediate
;
14627 else if (immediate
== (immediate
& 0x0000ff00))
14629 *immbits
= immediate
>> 8;
14632 else if (immediate
== (immediate
& 0x00ff0000))
14634 *immbits
= immediate
>> 16;
14637 else if (immediate
== (immediate
& 0xff000000))
14639 *immbits
= immediate
>> 24;
14642 if ((immediate
& 0xffff) != (immediate
>> 16))
14643 goto bad_immediate
;
14644 immediate
&= 0xffff;
14647 if (immediate
== (immediate
& 0x000000ff))
14649 *immbits
= immediate
;
14652 else if (immediate
== (immediate
& 0x0000ff00))
14654 *immbits
= immediate
>> 8;
14659 first_error (_("immediate value out of range"));
14664 do_neon_logic (void)
14666 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14668 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14669 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14670 /* U bit and size field were set as part of the bitmask. */
14671 NEON_ENCODE (INTEGER
, inst
);
14672 neon_three_same (neon_quad (rs
), 0, -1);
14676 const int three_ops_form
= (inst
.operands
[2].present
14677 && !inst
.operands
[2].isreg
);
14678 const int immoperand
= (three_ops_form
? 2 : 1);
14679 enum neon_shape rs
= (three_ops_form
14680 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14681 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14682 struct neon_type_el et
= neon_check_type (2, rs
,
14683 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14684 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14688 if (et
.type
== NT_invtype
)
14691 if (three_ops_form
)
14692 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14693 _("first and second operands shall be the same register"));
14695 NEON_ENCODE (IMMED
, inst
);
14697 immbits
= inst
.operands
[immoperand
].imm
;
14700 /* .i64 is a pseudo-op, so the immediate must be a repeating
14702 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14703 inst
.operands
[immoperand
].reg
: 0))
14705 /* Set immbits to an invalid constant. */
14706 immbits
= 0xdeadbeef;
14713 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14717 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14721 /* Pseudo-instruction for VBIC. */
14722 neon_invert_size (&immbits
, 0, et
.size
);
14723 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14727 /* Pseudo-instruction for VORR. */
14728 neon_invert_size (&immbits
, 0, et
.size
);
14729 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14739 inst
.instruction
|= neon_quad (rs
) << 6;
14740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14742 inst
.instruction
|= cmode
<< 8;
14743 neon_write_immbits (immbits
);
14745 neon_dp_fixup (&inst
);
14750 do_neon_bitfield (void)
14752 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14753 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14754 neon_three_same (neon_quad (rs
), 0, -1);
14758 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14761 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14762 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14764 if (et
.type
== NT_float
)
14766 NEON_ENCODE (FLOAT
, inst
);
14767 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14771 NEON_ENCODE (INTEGER
, inst
);
14772 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14777 do_neon_dyadic_if_su (void)
14779 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14783 do_neon_dyadic_if_su_d (void)
14785 /* This version only allow D registers, but that constraint is enforced during
14786 operand parsing so we don't need to do anything extra here. */
14787 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14791 do_neon_dyadic_if_i_d (void)
14793 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14794 affected if we specify unsigned args. */
14795 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14798 enum vfp_or_neon_is_neon_bits
14801 NEON_CHECK_ARCH
= 2,
14802 NEON_CHECK_ARCH8
= 4
14805 /* Call this function if an instruction which may have belonged to the VFP or
14806 Neon instruction sets, but turned out to be a Neon instruction (due to the
14807 operand types involved, etc.). We have to check and/or fix-up a couple of
14810 - Make sure the user hasn't attempted to make a Neon instruction
14812 - Alter the value in the condition code field if necessary.
14813 - Make sure that the arch supports Neon instructions.
14815 Which of these operations take place depends on bits from enum
14816 vfp_or_neon_is_neon_bits.
14818 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14819 current instruction's condition is COND_ALWAYS, the condition field is
14820 changed to inst.uncond_value. This is necessary because instructions shared
14821 between VFP and Neon may be conditional for the VFP variants only, and the
14822 unconditional Neon version must have, e.g., 0xF in the condition field. */
14825 vfp_or_neon_is_neon (unsigned check
)
14827 /* Conditions are always legal in Thumb mode (IT blocks). */
14828 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14830 if (inst
.cond
!= COND_ALWAYS
)
14832 first_error (_(BAD_COND
));
14835 if (inst
.uncond_value
!= -1)
14836 inst
.instruction
|= inst
.uncond_value
<< 28;
14839 if ((check
& NEON_CHECK_ARCH
)
14840 && !mark_feature_used (&fpu_neon_ext_v1
))
14842 first_error (_(BAD_FPU
));
14846 if ((check
& NEON_CHECK_ARCH8
)
14847 && !mark_feature_used (&fpu_neon_ext_armv8
))
14849 first_error (_(BAD_FPU
));
14857 do_neon_addsub_if_i (void)
14859 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14862 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14865 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14866 affected if we specify unsigned args. */
14867 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14870 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14872 V<op> A,B (A is operand 0, B is operand 2)
14877 so handle that case specially. */
14880 neon_exchange_operands (void)
14882 if (inst
.operands
[1].present
)
14884 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14886 /* Swap operands[1] and operands[2]. */
14887 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14888 inst
.operands
[1] = inst
.operands
[2];
14889 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14894 inst
.operands
[1] = inst
.operands
[2];
14895 inst
.operands
[2] = inst
.operands
[0];
14900 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14902 if (inst
.operands
[2].isreg
)
14905 neon_exchange_operands ();
14906 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14910 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14911 struct neon_type_el et
= neon_check_type (2, rs
,
14912 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14914 NEON_ENCODE (IMMED
, inst
);
14915 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14916 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14917 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14918 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14919 inst
.instruction
|= neon_quad (rs
) << 6;
14920 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14921 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14923 neon_dp_fixup (&inst
);
14930 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14934 do_neon_cmp_inv (void)
14936 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14942 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14945 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14946 scalars, which are encoded in 5 bits, M : Rm.
14947 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14948 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14952 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14954 unsigned regno
= NEON_SCALAR_REG (scalar
);
14955 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14960 if (regno
> 7 || elno
> 3)
14962 return regno
| (elno
<< 3);
14965 if (regno
> 15 || elno
> 1)
14967 return regno
| (elno
<< 4);
14971 first_error (_("scalar out of range for multiply instruction"));
14977 /* Encode multiply / multiply-accumulate scalar instructions. */
14980 neon_mul_mac (struct neon_type_el et
, int ubit
)
14984 /* Give a more helpful error message if we have an invalid type. */
14985 if (et
.type
== NT_invtype
)
14988 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14989 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14990 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14991 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14992 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14993 inst
.instruction
|= LOW4 (scalar
);
14994 inst
.instruction
|= HI1 (scalar
) << 5;
14995 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14996 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14997 inst
.instruction
|= (ubit
!= 0) << 24;
14999 neon_dp_fixup (&inst
);
15003 do_neon_mac_maybe_scalar (void)
15005 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15008 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15011 if (inst
.operands
[2].isscalar
)
15013 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15014 struct neon_type_el et
= neon_check_type (3, rs
,
15015 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15016 NEON_ENCODE (SCALAR
, inst
);
15017 neon_mul_mac (et
, neon_quad (rs
));
15021 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15022 affected if we specify unsigned args. */
15023 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15028 do_neon_fmac (void)
15030 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15033 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15036 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15042 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15043 struct neon_type_el et
= neon_check_type (3, rs
,
15044 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15045 neon_three_same (neon_quad (rs
), 0, et
.size
);
15048 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15049 same types as the MAC equivalents. The polynomial type for this instruction
15050 is encoded the same as the integer type. */
15055 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15058 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15061 if (inst
.operands
[2].isscalar
)
15062 do_neon_mac_maybe_scalar ();
15064 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15068 do_neon_qdmulh (void)
15070 if (inst
.operands
[2].isscalar
)
15072 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15073 struct neon_type_el et
= neon_check_type (3, rs
,
15074 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15075 NEON_ENCODE (SCALAR
, inst
);
15076 neon_mul_mac (et
, neon_quad (rs
));
15080 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15081 struct neon_type_el et
= neon_check_type (3, rs
,
15082 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15083 NEON_ENCODE (INTEGER
, inst
);
15084 /* The U bit (rounding) comes from bit mask. */
15085 neon_three_same (neon_quad (rs
), 0, et
.size
);
15090 do_neon_qrdmlah (void)
15092 /* Check we're on the correct architecture. */
15093 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15095 _("instruction form not available on this architecture.");
15096 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15098 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15099 record_feature_use (&fpu_neon_ext_v8_1
);
15102 if (inst
.operands
[2].isscalar
)
15104 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15105 struct neon_type_el et
= neon_check_type (3, rs
,
15106 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15107 NEON_ENCODE (SCALAR
, inst
);
15108 neon_mul_mac (et
, neon_quad (rs
));
15112 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15113 struct neon_type_el et
= neon_check_type (3, rs
,
15114 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15115 NEON_ENCODE (INTEGER
, inst
);
15116 /* The U bit (rounding) comes from bit mask. */
15117 neon_three_same (neon_quad (rs
), 0, et
.size
);
15122 do_neon_fcmp_absolute (void)
15124 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15125 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15126 N_F_16_32
| N_KEY
);
15127 /* Size field comes from bit mask. */
15128 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15132 do_neon_fcmp_absolute_inv (void)
15134 neon_exchange_operands ();
15135 do_neon_fcmp_absolute ();
15139 do_neon_step (void)
15141 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15142 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15143 N_F_16_32
| N_KEY
);
15144 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15148 do_neon_abs_neg (void)
15150 enum neon_shape rs
;
15151 struct neon_type_el et
;
15153 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15156 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15159 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15160 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15162 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15163 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15164 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15165 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15166 inst
.instruction
|= neon_quad (rs
) << 6;
15167 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15168 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15170 neon_dp_fixup (&inst
);
15176 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15177 struct neon_type_el et
= neon_check_type (2, rs
,
15178 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15179 int imm
= inst
.operands
[2].imm
;
15180 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15181 _("immediate out of range for insert"));
15182 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15188 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15189 struct neon_type_el et
= neon_check_type (2, rs
,
15190 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15191 int imm
= inst
.operands
[2].imm
;
15192 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15193 _("immediate out of range for insert"));
15194 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15198 do_neon_qshlu_imm (void)
15200 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15201 struct neon_type_el et
= neon_check_type (2, rs
,
15202 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15203 int imm
= inst
.operands
[2].imm
;
15204 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15205 _("immediate out of range for shift"));
15206 /* Only encodes the 'U present' variant of the instruction.
15207 In this case, signed types have OP (bit 8) set to 0.
15208 Unsigned types have OP set to 1. */
15209 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15210 /* The rest of the bits are the same as other immediate shifts. */
15211 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15215 do_neon_qmovn (void)
15217 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15218 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15219 /* Saturating move where operands can be signed or unsigned, and the
15220 destination has the same signedness. */
15221 NEON_ENCODE (INTEGER
, inst
);
15222 if (et
.type
== NT_unsigned
)
15223 inst
.instruction
|= 0xc0;
15225 inst
.instruction
|= 0x80;
15226 neon_two_same (0, 1, et
.size
/ 2);
15230 do_neon_qmovun (void)
15232 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15233 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15234 /* Saturating move with unsigned results. Operands must be signed. */
15235 NEON_ENCODE (INTEGER
, inst
);
15236 neon_two_same (0, 1, et
.size
/ 2);
15240 do_neon_rshift_sat_narrow (void)
15242 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15243 or unsigned. If operands are unsigned, results must also be unsigned. */
15244 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15245 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15246 int imm
= inst
.operands
[2].imm
;
15247 /* This gets the bounds check, size encoding and immediate bits calculation
15251 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15252 VQMOVN.I<size> <Dd>, <Qm>. */
15255 inst
.operands
[2].present
= 0;
15256 inst
.instruction
= N_MNEM_vqmovn
;
15261 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15262 _("immediate out of range"));
15263 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15267 do_neon_rshift_sat_narrow_u (void)
15269 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15270 or unsigned. If operands are unsigned, results must also be unsigned. */
15271 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15272 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15273 int imm
= inst
.operands
[2].imm
;
15274 /* This gets the bounds check, size encoding and immediate bits calculation
15278 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15279 VQMOVUN.I<size> <Dd>, <Qm>. */
15282 inst
.operands
[2].present
= 0;
15283 inst
.instruction
= N_MNEM_vqmovun
;
15288 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15289 _("immediate out of range"));
15290 /* FIXME: The manual is kind of unclear about what value U should have in
15291 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15293 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15297 do_neon_movn (void)
15299 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15300 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15301 NEON_ENCODE (INTEGER
, inst
);
15302 neon_two_same (0, 1, et
.size
/ 2);
15306 do_neon_rshift_narrow (void)
15308 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15309 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15310 int imm
= inst
.operands
[2].imm
;
15311 /* This gets the bounds check, size encoding and immediate bits calculation
15315 /* If immediate is zero then we are a pseudo-instruction for
15316 VMOVN.I<size> <Dd>, <Qm> */
15319 inst
.operands
[2].present
= 0;
15320 inst
.instruction
= N_MNEM_vmovn
;
15325 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15326 _("immediate out of range for narrowing operation"));
15327 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15331 do_neon_shll (void)
15333 /* FIXME: Type checking when lengthening. */
15334 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15335 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15336 unsigned imm
= inst
.operands
[2].imm
;
15338 if (imm
== et
.size
)
15340 /* Maximum shift variant. */
15341 NEON_ENCODE (INTEGER
, inst
);
15342 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15343 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15344 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15345 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15346 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15348 neon_dp_fixup (&inst
);
15352 /* A more-specific type check for non-max versions. */
15353 et
= neon_check_type (2, NS_QDI
,
15354 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15355 NEON_ENCODE (IMMED
, inst
);
15356 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15360 /* Check the various types for the VCVT instruction, and return which version
15361 the current instruction is. */
15363 #define CVT_FLAVOUR_VAR \
15364 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15365 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15366 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15367 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15368 /* Half-precision conversions. */ \
15369 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15370 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15371 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15372 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15373 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15374 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15375 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15376 Compared with single/double precision variants, only the co-processor \
15377 field is different, so the encoding flow is reused here. */ \
15378 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15379 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15380 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15381 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15382 /* VFP instructions. */ \
15383 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15384 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15385 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15386 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15387 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15388 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15389 /* VFP instructions with bitshift. */ \
15390 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15391 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15392 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15393 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15394 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15395 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15396 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15397 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15399 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15400 neon_cvt_flavour_##C,
15402 /* The different types of conversions we can do. */
15403 enum neon_cvt_flavour
15406 neon_cvt_flavour_invalid
,
15407 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15412 static enum neon_cvt_flavour
15413 get_neon_cvt_flavour (enum neon_shape rs
)
15415 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15416 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15417 if (et.type != NT_invtype) \
15419 inst.error = NULL; \
15420 return (neon_cvt_flavour_##C); \
15423 struct neon_type_el et
;
15424 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15425 || rs
== NS_FF
) ? N_VFP
: 0;
15426 /* The instruction versions which take an immediate take one register
15427 argument, which is extended to the width of the full register. Thus the
15428 "source" and "destination" registers must have the same width. Hack that
15429 here by making the size equal to the key (wider, in this case) operand. */
15430 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15434 return neon_cvt_flavour_invalid
;
15449 /* Neon-syntax VFP conversions. */
15452 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15454 const char *opname
= 0;
15456 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15457 || rs
== NS_FHI
|| rs
== NS_HFI
)
15459 /* Conversions with immediate bitshift. */
15460 const char *enc
[] =
15462 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15468 if (flavour
< (int) ARRAY_SIZE (enc
))
15470 opname
= enc
[flavour
];
15471 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15472 _("operands 0 and 1 must be the same register"));
15473 inst
.operands
[1] = inst
.operands
[2];
15474 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15479 /* Conversions without bitshift. */
15480 const char *enc
[] =
15482 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15488 if (flavour
< (int) ARRAY_SIZE (enc
))
15489 opname
= enc
[flavour
];
15493 do_vfp_nsyn_opcode (opname
);
15495 /* ARMv8.2 fp16 VCVT instruction. */
15496 if (flavour
== neon_cvt_flavour_s32_f16
15497 || flavour
== neon_cvt_flavour_u32_f16
15498 || flavour
== neon_cvt_flavour_f16_u32
15499 || flavour
== neon_cvt_flavour_f16_s32
)
15500 do_scalar_fp16_v82_encode ();
15504 do_vfp_nsyn_cvtz (void)
15506 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15507 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15508 const char *enc
[] =
15510 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15516 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15517 do_vfp_nsyn_opcode (enc
[flavour
]);
15521 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15522 enum neon_cvt_mode mode
)
15527 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15528 D register operands. */
15529 if (flavour
== neon_cvt_flavour_s32_f64
15530 || flavour
== neon_cvt_flavour_u32_f64
)
15531 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15534 if (flavour
== neon_cvt_flavour_s32_f16
15535 || flavour
== neon_cvt_flavour_u32_f16
)
15536 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15539 set_it_insn_type (OUTSIDE_IT_INSN
);
15543 case neon_cvt_flavour_s32_f64
:
15547 case neon_cvt_flavour_s32_f32
:
15551 case neon_cvt_flavour_s32_f16
:
15555 case neon_cvt_flavour_u32_f64
:
15559 case neon_cvt_flavour_u32_f32
:
15563 case neon_cvt_flavour_u32_f16
:
15568 first_error (_("invalid instruction shape"));
15574 case neon_cvt_mode_a
: rm
= 0; break;
15575 case neon_cvt_mode_n
: rm
= 1; break;
15576 case neon_cvt_mode_p
: rm
= 2; break;
15577 case neon_cvt_mode_m
: rm
= 3; break;
15578 default: first_error (_("invalid rounding mode")); return;
15581 NEON_ENCODE (FPV8
, inst
);
15582 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15583 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15584 inst
.instruction
|= sz
<< 8;
15586 /* ARMv8.2 fp16 VCVT instruction. */
15587 if (flavour
== neon_cvt_flavour_s32_f16
15588 ||flavour
== neon_cvt_flavour_u32_f16
)
15589 do_scalar_fp16_v82_encode ();
15590 inst
.instruction
|= op
<< 7;
15591 inst
.instruction
|= rm
<< 16;
15592 inst
.instruction
|= 0xf0000000;
15593 inst
.is_neon
= TRUE
;
15597 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15599 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15600 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15601 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15603 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15605 if (flavour
== neon_cvt_flavour_invalid
)
15608 /* PR11109: Handle round-to-zero for VCVT conversions. */
15609 if (mode
== neon_cvt_mode_z
15610 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15611 && (flavour
== neon_cvt_flavour_s16_f16
15612 || flavour
== neon_cvt_flavour_u16_f16
15613 || flavour
== neon_cvt_flavour_s32_f32
15614 || flavour
== neon_cvt_flavour_u32_f32
15615 || flavour
== neon_cvt_flavour_s32_f64
15616 || flavour
== neon_cvt_flavour_u32_f64
)
15617 && (rs
== NS_FD
|| rs
== NS_FF
))
15619 do_vfp_nsyn_cvtz ();
15623 /* ARMv8.2 fp16 VCVT conversions. */
15624 if (mode
== neon_cvt_mode_z
15625 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15626 && (flavour
== neon_cvt_flavour_s32_f16
15627 || flavour
== neon_cvt_flavour_u32_f16
)
15630 do_vfp_nsyn_cvtz ();
15631 do_scalar_fp16_v82_encode ();
15635 /* VFP rather than Neon conversions. */
15636 if (flavour
>= neon_cvt_flavour_first_fp
)
15638 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15639 do_vfp_nsyn_cvt (rs
, flavour
);
15641 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15652 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15653 0x0000100, 0x1000100, 0x0, 0x1000000};
15655 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15658 /* Fixed-point conversion with #0 immediate is encoded as an
15659 integer conversion. */
15660 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15662 NEON_ENCODE (IMMED
, inst
);
15663 if (flavour
!= neon_cvt_flavour_invalid
)
15664 inst
.instruction
|= enctab
[flavour
];
15665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15667 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15668 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15669 inst
.instruction
|= neon_quad (rs
) << 6;
15670 inst
.instruction
|= 1 << 21;
15671 if (flavour
< neon_cvt_flavour_s16_f16
)
15673 inst
.instruction
|= 1 << 21;
15674 immbits
= 32 - inst
.operands
[2].imm
;
15675 inst
.instruction
|= immbits
<< 16;
15679 inst
.instruction
|= 3 << 20;
15680 immbits
= 16 - inst
.operands
[2].imm
;
15681 inst
.instruction
|= immbits
<< 16;
15682 inst
.instruction
&= ~(1 << 9);
15685 neon_dp_fixup (&inst
);
15691 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15693 NEON_ENCODE (FLOAT
, inst
);
15694 set_it_insn_type (OUTSIDE_IT_INSN
);
15696 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15700 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15701 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15702 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15703 inst
.instruction
|= neon_quad (rs
) << 6;
15704 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15705 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15706 inst
.instruction
|= mode
<< 8;
15707 if (flavour
== neon_cvt_flavour_u16_f16
15708 || flavour
== neon_cvt_flavour_s16_f16
)
15709 /* Mask off the original size bits and reencode them. */
15710 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15713 inst
.instruction
|= 0xfc000000;
15715 inst
.instruction
|= 0xf0000000;
15721 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15722 0x100, 0x180, 0x0, 0x080};
15724 NEON_ENCODE (INTEGER
, inst
);
15726 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15729 if (flavour
!= neon_cvt_flavour_invalid
)
15730 inst
.instruction
|= enctab
[flavour
];
15732 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15733 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15734 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15735 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15736 inst
.instruction
|= neon_quad (rs
) << 6;
15737 if (flavour
>= neon_cvt_flavour_s16_f16
15738 && flavour
<= neon_cvt_flavour_f16_u16
)
15739 /* Half precision. */
15740 inst
.instruction
|= 1 << 18;
15742 inst
.instruction
|= 2 << 18;
15744 neon_dp_fixup (&inst
);
15749 /* Half-precision conversions for Advanced SIMD -- neon. */
15754 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15756 as_bad (_("operand size must match register width"));
15761 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15763 as_bad (_("operand size must match register width"));
15768 inst
.instruction
= 0x3b60600;
15770 inst
.instruction
= 0x3b60700;
15772 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15773 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15774 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15775 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15776 neon_dp_fixup (&inst
);
15780 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15781 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15782 do_vfp_nsyn_cvt (rs
, flavour
);
15784 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15789 do_neon_cvtr (void)
15791 do_neon_cvt_1 (neon_cvt_mode_x
);
15797 do_neon_cvt_1 (neon_cvt_mode_z
);
15801 do_neon_cvta (void)
15803 do_neon_cvt_1 (neon_cvt_mode_a
);
15807 do_neon_cvtn (void)
15809 do_neon_cvt_1 (neon_cvt_mode_n
);
15813 do_neon_cvtp (void)
15815 do_neon_cvt_1 (neon_cvt_mode_p
);
15819 do_neon_cvtm (void)
15821 do_neon_cvt_1 (neon_cvt_mode_m
);
15825 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15828 mark_feature_used (&fpu_vfp_ext_armv8
);
15830 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15831 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15832 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15833 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15834 inst
.instruction
|= to
? 0x10000 : 0;
15835 inst
.instruction
|= t
? 0x80 : 0;
15836 inst
.instruction
|= is_double
? 0x100 : 0;
15837 do_vfp_cond_or_thumb ();
15841 do_neon_cvttb_1 (bfd_boolean t
)
15843 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15844 NS_DF
, NS_DH
, NS_NULL
);
15848 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15851 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15853 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15856 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15858 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15860 /* The VCVTB and VCVTT instructions with D-register operands
15861 don't work for SP only targets. */
15862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15866 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15868 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15870 /* The VCVTB and VCVTT instructions with D-register operands
15871 don't work for SP only targets. */
15872 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15876 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15883 do_neon_cvtb (void)
15885 do_neon_cvttb_1 (FALSE
);
15890 do_neon_cvtt (void)
15892 do_neon_cvttb_1 (TRUE
);
15896 neon_move_immediate (void)
15898 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15899 struct neon_type_el et
= neon_check_type (2, rs
,
15900 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15901 unsigned immlo
, immhi
= 0, immbits
;
15902 int op
, cmode
, float_p
;
15904 constraint (et
.type
== NT_invtype
,
15905 _("operand size must be specified for immediate VMOV"));
15907 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15908 op
= (inst
.instruction
& (1 << 5)) != 0;
15910 immlo
= inst
.operands
[1].imm
;
15911 if (inst
.operands
[1].regisimm
)
15912 immhi
= inst
.operands
[1].reg
;
15914 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15915 _("immediate has bits set outside the operand size"));
15917 float_p
= inst
.operands
[1].immisfloat
;
15919 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15920 et
.size
, et
.type
)) == FAIL
)
15922 /* Invert relevant bits only. */
15923 neon_invert_size (&immlo
, &immhi
, et
.size
);
15924 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15925 with one or the other; those cases are caught by
15926 neon_cmode_for_move_imm. */
15928 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15929 &op
, et
.size
, et
.type
)) == FAIL
)
15931 first_error (_("immediate out of range"));
15936 inst
.instruction
&= ~(1 << 5);
15937 inst
.instruction
|= op
<< 5;
15939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15941 inst
.instruction
|= neon_quad (rs
) << 6;
15942 inst
.instruction
|= cmode
<< 8;
15944 neon_write_immbits (immbits
);
15950 if (inst
.operands
[1].isreg
)
15952 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15954 NEON_ENCODE (INTEGER
, inst
);
15955 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15956 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15957 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15958 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15959 inst
.instruction
|= neon_quad (rs
) << 6;
15963 NEON_ENCODE (IMMED
, inst
);
15964 neon_move_immediate ();
15967 neon_dp_fixup (&inst
);
15970 /* Encode instructions of form:
15972 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15973 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15976 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15980 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15982 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15983 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15984 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15985 inst
.instruction
|= neon_logbits (size
) << 20;
15987 neon_dp_fixup (&inst
);
15991 do_neon_dyadic_long (void)
15993 /* FIXME: Type checking for lengthening op. */
15994 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15995 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15996 neon_mixed_length (et
, et
.size
);
16000 do_neon_abal (void)
16002 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16003 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16004 neon_mixed_length (et
, et
.size
);
16008 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16010 if (inst
.operands
[2].isscalar
)
16012 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16013 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16014 NEON_ENCODE (SCALAR
, inst
);
16015 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16019 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16020 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16021 NEON_ENCODE (INTEGER
, inst
);
16022 neon_mixed_length (et
, et
.size
);
16027 do_neon_mac_maybe_scalar_long (void)
16029 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16033 do_neon_dyadic_wide (void)
16035 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16036 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16037 neon_mixed_length (et
, et
.size
);
16041 do_neon_dyadic_narrow (void)
16043 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16044 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16045 /* Operand sign is unimportant, and the U bit is part of the opcode,
16046 so force the operand type to integer. */
16047 et
.type
= NT_integer
;
16048 neon_mixed_length (et
, et
.size
/ 2);
16052 do_neon_mul_sat_scalar_long (void)
16054 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16058 do_neon_vmull (void)
16060 if (inst
.operands
[2].isscalar
)
16061 do_neon_mac_maybe_scalar_long ();
16064 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16065 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16067 if (et
.type
== NT_poly
)
16068 NEON_ENCODE (POLY
, inst
);
16070 NEON_ENCODE (INTEGER
, inst
);
16072 /* For polynomial encoding the U bit must be zero, and the size must
16073 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16074 obviously, as 0b10). */
16077 /* Check we're on the correct architecture. */
16078 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16080 _("Instruction form not available on this architecture.");
16085 neon_mixed_length (et
, et
.size
);
16092 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16093 struct neon_type_el et
= neon_check_type (3, rs
,
16094 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16095 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16097 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16098 _("shift out of range"));
16099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16103 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16104 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16105 inst
.instruction
|= neon_quad (rs
) << 6;
16106 inst
.instruction
|= imm
<< 8;
16108 neon_dp_fixup (&inst
);
16114 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16115 struct neon_type_el et
= neon_check_type (2, rs
,
16116 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16117 unsigned op
= (inst
.instruction
>> 7) & 3;
16118 /* N (width of reversed regions) is encoded as part of the bitmask. We
16119 extract it here to check the elements to be reversed are smaller.
16120 Otherwise we'd get a reserved instruction. */
16121 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16122 gas_assert (elsize
!= 0);
16123 constraint (et
.size
>= elsize
,
16124 _("elements must be smaller than reversal region"));
16125 neon_two_same (neon_quad (rs
), 1, et
.size
);
16131 if (inst
.operands
[1].isscalar
)
16133 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16134 struct neon_type_el et
= neon_check_type (2, rs
,
16135 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16136 unsigned sizebits
= et
.size
>> 3;
16137 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16138 int logsize
= neon_logbits (et
.size
);
16139 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16141 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16144 NEON_ENCODE (SCALAR
, inst
);
16145 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16146 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16147 inst
.instruction
|= LOW4 (dm
);
16148 inst
.instruction
|= HI1 (dm
) << 5;
16149 inst
.instruction
|= neon_quad (rs
) << 6;
16150 inst
.instruction
|= x
<< 17;
16151 inst
.instruction
|= sizebits
<< 16;
16153 neon_dp_fixup (&inst
);
16157 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16158 struct neon_type_el et
= neon_check_type (2, rs
,
16159 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16160 /* Duplicate ARM register to lanes of vector. */
16161 NEON_ENCODE (ARMREG
, inst
);
16164 case 8: inst
.instruction
|= 0x400000; break;
16165 case 16: inst
.instruction
|= 0x000020; break;
16166 case 32: inst
.instruction
|= 0x000000; break;
16169 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16172 inst
.instruction
|= neon_quad (rs
) << 21;
16173 /* The encoding for this instruction is identical for the ARM and Thumb
16174 variants, except for the condition field. */
16175 do_vfp_cond_or_thumb ();
16179 /* VMOV has particularly many variations. It can be one of:
16180 0. VMOV<c><q> <Qd>, <Qm>
16181 1. VMOV<c><q> <Dd>, <Dm>
16182 (Register operations, which are VORR with Rm = Rn.)
16183 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16184 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16186 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16187 (ARM register to scalar.)
16188 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16189 (Two ARM registers to vector.)
16190 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16191 (Scalar to ARM register.)
16192 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16193 (Vector to two ARM registers.)
16194 8. VMOV.F32 <Sd>, <Sm>
16195 9. VMOV.F64 <Dd>, <Dm>
16196 (VFP register moves.)
16197 10. VMOV.F32 <Sd>, #imm
16198 11. VMOV.F64 <Dd>, #imm
16199 (VFP float immediate load.)
16200 12. VMOV <Rd>, <Sm>
16201 (VFP single to ARM reg.)
16202 13. VMOV <Sd>, <Rm>
16203 (ARM reg to VFP single.)
16204 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16205 (Two ARM regs to two VFP singles.)
16206 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16207 (Two VFP singles to two ARM regs.)
16209 These cases can be disambiguated using neon_select_shape, except cases 1/9
16210 and 3/11 which depend on the operand type too.
16212 All the encoded bits are hardcoded by this function.
16214 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16215 Cases 5, 7 may be used with VFPv2 and above.
16217 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16218 can specify a type where it doesn't make sense to, and is ignored). */
16223 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16224 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16225 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16226 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16227 struct neon_type_el et
;
16228 const char *ldconst
= 0;
16232 case NS_DD
: /* case 1/9. */
16233 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16234 /* It is not an error here if no type is given. */
16236 if (et
.type
== NT_float
&& et
.size
== 64)
16238 do_vfp_nsyn_opcode ("fcpyd");
16241 /* fall through. */
16243 case NS_QQ
: /* case 0/1. */
16245 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16247 /* The architecture manual I have doesn't explicitly state which
16248 value the U bit should have for register->register moves, but
16249 the equivalent VORR instruction has U = 0, so do that. */
16250 inst
.instruction
= 0x0200110;
16251 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16252 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16253 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16254 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16257 inst
.instruction
|= neon_quad (rs
) << 6;
16259 neon_dp_fixup (&inst
);
16263 case NS_DI
: /* case 3/11. */
16264 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16266 if (et
.type
== NT_float
&& et
.size
== 64)
16268 /* case 11 (fconstd). */
16269 ldconst
= "fconstd";
16270 goto encode_fconstd
;
16272 /* fall through. */
16274 case NS_QI
: /* case 2/3. */
16275 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16277 inst
.instruction
= 0x0800010;
16278 neon_move_immediate ();
16279 neon_dp_fixup (&inst
);
16282 case NS_SR
: /* case 4. */
16284 unsigned bcdebits
= 0;
16286 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16287 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16289 /* .<size> is optional here, defaulting to .32. */
16290 if (inst
.vectype
.elems
== 0
16291 && inst
.operands
[0].vectype
.type
== NT_invtype
16292 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16294 inst
.vectype
.el
[0].type
= NT_untyped
;
16295 inst
.vectype
.el
[0].size
= 32;
16296 inst
.vectype
.elems
= 1;
16299 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16300 logsize
= neon_logbits (et
.size
);
16302 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16304 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16305 && et
.size
!= 32, _(BAD_FPU
));
16306 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16307 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16311 case 8: bcdebits
= 0x8; break;
16312 case 16: bcdebits
= 0x1; break;
16313 case 32: bcdebits
= 0x0; break;
16317 bcdebits
|= x
<< logsize
;
16319 inst
.instruction
= 0xe000b10;
16320 do_vfp_cond_or_thumb ();
16321 inst
.instruction
|= LOW4 (dn
) << 16;
16322 inst
.instruction
|= HI1 (dn
) << 7;
16323 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16324 inst
.instruction
|= (bcdebits
& 3) << 5;
16325 inst
.instruction
|= (bcdebits
>> 2) << 21;
16329 case NS_DRR
: /* case 5 (fmdrr). */
16330 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16333 inst
.instruction
= 0xc400b10;
16334 do_vfp_cond_or_thumb ();
16335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16337 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16338 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16341 case NS_RS
: /* case 6. */
16344 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16345 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16346 unsigned abcdebits
= 0;
16348 /* .<dt> is optional here, defaulting to .32. */
16349 if (inst
.vectype
.elems
== 0
16350 && inst
.operands
[0].vectype
.type
== NT_invtype
16351 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16353 inst
.vectype
.el
[0].type
= NT_untyped
;
16354 inst
.vectype
.el
[0].size
= 32;
16355 inst
.vectype
.elems
= 1;
16358 et
= neon_check_type (2, NS_NULL
,
16359 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16360 logsize
= neon_logbits (et
.size
);
16362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16364 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16365 && et
.size
!= 32, _(BAD_FPU
));
16366 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16367 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16371 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16372 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16373 case 32: abcdebits
= 0x00; break;
16377 abcdebits
|= x
<< logsize
;
16378 inst
.instruction
= 0xe100b10;
16379 do_vfp_cond_or_thumb ();
16380 inst
.instruction
|= LOW4 (dn
) << 16;
16381 inst
.instruction
|= HI1 (dn
) << 7;
16382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16383 inst
.instruction
|= (abcdebits
& 3) << 5;
16384 inst
.instruction
|= (abcdebits
>> 2) << 21;
16388 case NS_RRD
: /* case 7 (fmrrd). */
16389 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16392 inst
.instruction
= 0xc500b10;
16393 do_vfp_cond_or_thumb ();
16394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16395 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16396 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16397 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16400 case NS_FF
: /* case 8 (fcpys). */
16401 do_vfp_nsyn_opcode ("fcpys");
16405 case NS_FI
: /* case 10 (fconsts). */
16406 ldconst
= "fconsts";
16408 if (is_quarter_float (inst
.operands
[1].imm
))
16410 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16411 do_vfp_nsyn_opcode (ldconst
);
16413 /* ARMv8.2 fp16 vmov.f16 instruction. */
16415 do_scalar_fp16_v82_encode ();
16418 first_error (_("immediate out of range"));
16422 case NS_RF
: /* case 12 (fmrs). */
16423 do_vfp_nsyn_opcode ("fmrs");
16424 /* ARMv8.2 fp16 vmov.f16 instruction. */
16426 do_scalar_fp16_v82_encode ();
16430 case NS_FR
: /* case 13 (fmsr). */
16431 do_vfp_nsyn_opcode ("fmsr");
16432 /* ARMv8.2 fp16 vmov.f16 instruction. */
16434 do_scalar_fp16_v82_encode ();
16437 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16438 (one of which is a list), but we have parsed four. Do some fiddling to
16439 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16441 case NS_RRFF
: /* case 14 (fmrrs). */
16442 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16443 _("VFP registers must be adjacent"));
16444 inst
.operands
[2].imm
= 2;
16445 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16446 do_vfp_nsyn_opcode ("fmrrs");
16449 case NS_FFRR
: /* case 15 (fmsrr). */
16450 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16451 _("VFP registers must be adjacent"));
16452 inst
.operands
[1] = inst
.operands
[2];
16453 inst
.operands
[2] = inst
.operands
[3];
16454 inst
.operands
[0].imm
= 2;
16455 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16456 do_vfp_nsyn_opcode ("fmsrr");
16460 /* neon_select_shape has determined that the instruction
16461 shape is wrong and has already set the error message. */
16470 do_neon_rshift_round_imm (void)
16472 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16473 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16474 int imm
= inst
.operands
[2].imm
;
16476 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16479 inst
.operands
[2].present
= 0;
16484 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16485 _("immediate out of range for shift"));
16486 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16491 do_neon_movhf (void)
16493 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16494 constraint (rs
!= NS_HH
, _("invalid suffix"));
16496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16499 do_vfp_sp_monadic ();
16502 inst
.instruction
|= 0xf0000000;
16506 do_neon_movl (void)
16508 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16509 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16510 unsigned sizebits
= et
.size
>> 3;
16511 inst
.instruction
|= sizebits
<< 19;
16512 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16518 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16519 struct neon_type_el et
= neon_check_type (2, rs
,
16520 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16521 NEON_ENCODE (INTEGER
, inst
);
16522 neon_two_same (neon_quad (rs
), 1, et
.size
);
16526 do_neon_zip_uzp (void)
16528 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16529 struct neon_type_el et
= neon_check_type (2, rs
,
16530 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16531 if (rs
== NS_DD
&& et
.size
== 32)
16533 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16534 inst
.instruction
= N_MNEM_vtrn
;
16538 neon_two_same (neon_quad (rs
), 1, et
.size
);
16542 do_neon_sat_abs_neg (void)
16544 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16545 struct neon_type_el et
= neon_check_type (2, rs
,
16546 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16547 neon_two_same (neon_quad (rs
), 1, et
.size
);
16551 do_neon_pair_long (void)
16553 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16554 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16555 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16556 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16557 neon_two_same (neon_quad (rs
), 1, et
.size
);
16561 do_neon_recip_est (void)
16563 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16564 struct neon_type_el et
= neon_check_type (2, rs
,
16565 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16566 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16567 neon_two_same (neon_quad (rs
), 1, et
.size
);
16573 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16574 struct neon_type_el et
= neon_check_type (2, rs
,
16575 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16576 neon_two_same (neon_quad (rs
), 1, et
.size
);
16582 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16583 struct neon_type_el et
= neon_check_type (2, rs
,
16584 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16585 neon_two_same (neon_quad (rs
), 1, et
.size
);
16591 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16592 struct neon_type_el et
= neon_check_type (2, rs
,
16593 N_EQK
| N_INT
, N_8
| N_KEY
);
16594 neon_two_same (neon_quad (rs
), 1, et
.size
);
16600 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16601 neon_two_same (neon_quad (rs
), 1, -1);
16605 do_neon_tbl_tbx (void)
16607 unsigned listlenbits
;
16608 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16610 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16612 first_error (_("bad list length for table lookup"));
16616 listlenbits
= inst
.operands
[1].imm
- 1;
16617 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16618 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16619 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16620 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16621 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16622 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16623 inst
.instruction
|= listlenbits
<< 8;
16625 neon_dp_fixup (&inst
);
16629 do_neon_ldm_stm (void)
16631 /* P, U and L bits are part of bitmask. */
16632 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16633 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16635 if (inst
.operands
[1].issingle
)
16637 do_vfp_nsyn_ldm_stm (is_dbmode
);
16641 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16642 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16644 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16645 _("register list must contain at least 1 and at most 16 "
16648 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16649 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16650 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16651 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16653 inst
.instruction
|= offsetbits
;
16655 do_vfp_cond_or_thumb ();
16659 do_neon_ldr_str (void)
16661 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16663 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16664 And is UNPREDICTABLE in thumb mode. */
16666 && inst
.operands
[1].reg
== REG_PC
16667 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16670 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16671 else if (warn_on_deprecated
)
16672 as_tsktsk (_("Use of PC here is deprecated"));
16675 if (inst
.operands
[0].issingle
)
16678 do_vfp_nsyn_opcode ("flds");
16680 do_vfp_nsyn_opcode ("fsts");
16682 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16683 if (inst
.vectype
.el
[0].size
== 16)
16684 do_scalar_fp16_v82_encode ();
16689 do_vfp_nsyn_opcode ("fldd");
16691 do_vfp_nsyn_opcode ("fstd");
16695 /* "interleave" version also handles non-interleaving register VLD1/VST1
16699 do_neon_ld_st_interleave (void)
16701 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16702 N_8
| N_16
| N_32
| N_64
);
16703 unsigned alignbits
= 0;
16705 /* The bits in this table go:
16706 0: register stride of one (0) or two (1)
16707 1,2: register list length, minus one (1, 2, 3, 4).
16708 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16709 We use -1 for invalid entries. */
16710 const int typetable
[] =
16712 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16713 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16714 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16715 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16719 if (et
.type
== NT_invtype
)
16722 if (inst
.operands
[1].immisalign
)
16723 switch (inst
.operands
[1].imm
>> 8)
16725 case 64: alignbits
= 1; break;
16727 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16728 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16729 goto bad_alignment
;
16733 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16734 goto bad_alignment
;
16739 first_error (_("bad alignment"));
16743 inst
.instruction
|= alignbits
<< 4;
16744 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16746 /* Bits [4:6] of the immediate in a list specifier encode register stride
16747 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16748 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16749 up the right value for "type" in a table based on this value and the given
16750 list style, then stick it back. */
16751 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16752 | (((inst
.instruction
>> 8) & 3) << 3);
16754 typebits
= typetable
[idx
];
16756 constraint (typebits
== -1, _("bad list type for instruction"));
16757 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16758 _("bad element type for instruction"));
16760 inst
.instruction
&= ~0xf00;
16761 inst
.instruction
|= typebits
<< 8;
16764 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16765 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16766 otherwise. The variable arguments are a list of pairs of legal (size, align)
16767 values, terminated with -1. */
16770 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16773 int result
= FAIL
, thissize
, thisalign
;
16775 if (!inst
.operands
[1].immisalign
)
16781 va_start (ap
, do_alignment
);
16785 thissize
= va_arg (ap
, int);
16786 if (thissize
== -1)
16788 thisalign
= va_arg (ap
, int);
16790 if (size
== thissize
&& align
== thisalign
)
16793 while (result
!= SUCCESS
);
16797 if (result
== SUCCESS
)
16800 first_error (_("unsupported alignment for instruction"));
16806 do_neon_ld_st_lane (void)
16808 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16809 int align_good
, do_alignment
= 0;
16810 int logsize
= neon_logbits (et
.size
);
16811 int align
= inst
.operands
[1].imm
>> 8;
16812 int n
= (inst
.instruction
>> 8) & 3;
16813 int max_el
= 64 / et
.size
;
16815 if (et
.type
== NT_invtype
)
16818 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16819 _("bad list length"));
16820 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16821 _("scalar index out of range"));
16822 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16824 _("stride of 2 unavailable when element size is 8"));
16828 case 0: /* VLD1 / VST1. */
16829 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16831 if (align_good
== FAIL
)
16835 unsigned alignbits
= 0;
16838 case 16: alignbits
= 0x1; break;
16839 case 32: alignbits
= 0x3; break;
16842 inst
.instruction
|= alignbits
<< 4;
16846 case 1: /* VLD2 / VST2. */
16847 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16848 16, 32, 32, 64, -1);
16849 if (align_good
== FAIL
)
16852 inst
.instruction
|= 1 << 4;
16855 case 2: /* VLD3 / VST3. */
16856 constraint (inst
.operands
[1].immisalign
,
16857 _("can't use alignment with this instruction"));
16860 case 3: /* VLD4 / VST4. */
16861 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16862 16, 64, 32, 64, 32, 128, -1);
16863 if (align_good
== FAIL
)
16867 unsigned alignbits
= 0;
16870 case 8: alignbits
= 0x1; break;
16871 case 16: alignbits
= 0x1; break;
16872 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16875 inst
.instruction
|= alignbits
<< 4;
16882 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16883 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16884 inst
.instruction
|= 1 << (4 + logsize
);
16886 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16887 inst
.instruction
|= logsize
<< 10;
16890 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16893 do_neon_ld_dup (void)
16895 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16896 int align_good
, do_alignment
= 0;
16898 if (et
.type
== NT_invtype
)
16901 switch ((inst
.instruction
>> 8) & 3)
16903 case 0: /* VLD1. */
16904 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16905 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16906 &do_alignment
, 16, 16, 32, 32, -1);
16907 if (align_good
== FAIL
)
16909 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16912 case 2: inst
.instruction
|= 1 << 5; break;
16913 default: first_error (_("bad list length")); return;
16915 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16918 case 1: /* VLD2. */
16919 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16920 &do_alignment
, 8, 16, 16, 32, 32, 64,
16922 if (align_good
== FAIL
)
16924 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16925 _("bad list length"));
16926 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16927 inst
.instruction
|= 1 << 5;
16928 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16931 case 2: /* VLD3. */
16932 constraint (inst
.operands
[1].immisalign
,
16933 _("can't use alignment with this instruction"));
16934 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16935 _("bad list length"));
16936 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16937 inst
.instruction
|= 1 << 5;
16938 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16941 case 3: /* VLD4. */
16943 int align
= inst
.operands
[1].imm
>> 8;
16944 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16945 16, 64, 32, 64, 32, 128, -1);
16946 if (align_good
== FAIL
)
16948 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16949 _("bad list length"));
16950 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16951 inst
.instruction
|= 1 << 5;
16952 if (et
.size
== 32 && align
== 128)
16953 inst
.instruction
|= 0x3 << 6;
16955 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16962 inst
.instruction
|= do_alignment
<< 4;
16965 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16966 apart from bits [11:4]. */
16969 do_neon_ldx_stx (void)
16971 if (inst
.operands
[1].isreg
)
16972 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16974 switch (NEON_LANE (inst
.operands
[0].imm
))
16976 case NEON_INTERLEAVE_LANES
:
16977 NEON_ENCODE (INTERLV
, inst
);
16978 do_neon_ld_st_interleave ();
16981 case NEON_ALL_LANES
:
16982 NEON_ENCODE (DUP
, inst
);
16983 if (inst
.instruction
== N_INV
)
16985 first_error ("only loads support such operands");
16992 NEON_ENCODE (LANE
, inst
);
16993 do_neon_ld_st_lane ();
16996 /* L bit comes from bit mask. */
16997 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16998 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16999 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17001 if (inst
.operands
[1].postind
)
17003 int postreg
= inst
.operands
[1].imm
& 0xf;
17004 constraint (!inst
.operands
[1].immisreg
,
17005 _("post-index must be a register"));
17006 constraint (postreg
== 0xd || postreg
== 0xf,
17007 _("bad register for post-index"));
17008 inst
.instruction
|= postreg
;
17012 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17013 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17014 || inst
.reloc
.exp
.X_add_number
!= 0,
17017 if (inst
.operands
[1].writeback
)
17019 inst
.instruction
|= 0xd;
17022 inst
.instruction
|= 0xf;
17026 inst
.instruction
|= 0xf9000000;
17028 inst
.instruction
|= 0xf4000000;
17033 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17035 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17036 D register operands. */
17037 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17038 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17041 NEON_ENCODE (FPV8
, inst
);
17043 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17045 do_vfp_sp_dyadic ();
17047 /* ARMv8.2 fp16 instruction. */
17049 do_scalar_fp16_v82_encode ();
17052 do_vfp_dp_rd_rn_rm ();
17055 inst
.instruction
|= 0x100;
17057 inst
.instruction
|= 0xf0000000;
17063 set_it_insn_type (OUTSIDE_IT_INSN
);
17065 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17066 first_error (_("invalid instruction shape"));
17072 set_it_insn_type (OUTSIDE_IT_INSN
);
17074 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17077 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17080 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17084 do_vrint_1 (enum neon_cvt_mode mode
)
17086 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17087 struct neon_type_el et
;
17092 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17093 D register operands. */
17094 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17098 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17100 if (et
.type
!= NT_invtype
)
17102 /* VFP encodings. */
17103 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17104 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17105 set_it_insn_type (OUTSIDE_IT_INSN
);
17107 NEON_ENCODE (FPV8
, inst
);
17108 if (rs
== NS_FF
|| rs
== NS_HH
)
17109 do_vfp_sp_monadic ();
17111 do_vfp_dp_rd_rm ();
17115 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17116 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17117 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17118 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17119 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17120 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17121 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17125 inst
.instruction
|= (rs
== NS_DD
) << 8;
17126 do_vfp_cond_or_thumb ();
17128 /* ARMv8.2 fp16 vrint instruction. */
17130 do_scalar_fp16_v82_encode ();
17134 /* Neon encodings (or something broken...). */
17136 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17138 if (et
.type
== NT_invtype
)
17141 set_it_insn_type (OUTSIDE_IT_INSN
);
17142 NEON_ENCODE (FLOAT
, inst
);
17144 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17147 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17148 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17149 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17150 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17151 inst
.instruction
|= neon_quad (rs
) << 6;
17152 /* Mask off the original size bits and reencode them. */
17153 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17154 | neon_logbits (et
.size
) << 18);
17158 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17159 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17160 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17161 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17162 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17163 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17164 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17169 inst
.instruction
|= 0xfc000000;
17171 inst
.instruction
|= 0xf0000000;
17178 do_vrint_1 (neon_cvt_mode_x
);
17184 do_vrint_1 (neon_cvt_mode_z
);
17190 do_vrint_1 (neon_cvt_mode_r
);
17196 do_vrint_1 (neon_cvt_mode_a
);
17202 do_vrint_1 (neon_cvt_mode_n
);
17208 do_vrint_1 (neon_cvt_mode_p
);
17214 do_vrint_1 (neon_cvt_mode_m
);
17217 /* Crypto v1 instructions. */
17219 do_crypto_2op_1 (unsigned elttype
, int op
)
17221 set_it_insn_type (OUTSIDE_IT_INSN
);
17223 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17229 NEON_ENCODE (INTEGER
, inst
);
17230 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17231 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17232 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17233 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17235 inst
.instruction
|= op
<< 6;
17238 inst
.instruction
|= 0xfc000000;
17240 inst
.instruction
|= 0xf0000000;
17244 do_crypto_3op_1 (int u
, int op
)
17246 set_it_insn_type (OUTSIDE_IT_INSN
);
17248 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17249 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17254 NEON_ENCODE (INTEGER
, inst
);
17255 neon_three_same (1, u
, 8 << op
);
17261 do_crypto_2op_1 (N_8
, 0);
17267 do_crypto_2op_1 (N_8
, 1);
17273 do_crypto_2op_1 (N_8
, 2);
17279 do_crypto_2op_1 (N_8
, 3);
17285 do_crypto_3op_1 (0, 0);
17291 do_crypto_3op_1 (0, 1);
17297 do_crypto_3op_1 (0, 2);
17303 do_crypto_3op_1 (0, 3);
17309 do_crypto_3op_1 (1, 0);
17315 do_crypto_3op_1 (1, 1);
17319 do_sha256su1 (void)
17321 do_crypto_3op_1 (1, 2);
17327 do_crypto_2op_1 (N_32
, -1);
17333 do_crypto_2op_1 (N_32
, 0);
17337 do_sha256su0 (void)
17339 do_crypto_2op_1 (N_32
, 1);
17343 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17345 unsigned int Rd
= inst
.operands
[0].reg
;
17346 unsigned int Rn
= inst
.operands
[1].reg
;
17347 unsigned int Rm
= inst
.operands
[2].reg
;
17349 set_it_insn_type (OUTSIDE_IT_INSN
);
17350 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17351 inst
.instruction
|= LOW4 (Rn
) << 16;
17352 inst
.instruction
|= LOW4 (Rm
);
17353 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17354 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17356 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17357 as_warn (UNPRED_REG ("r15"));
17358 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17359 as_warn (UNPRED_REG ("r13"));
17399 /* Overall per-instruction processing. */
17401 /* We need to be able to fix up arbitrary expressions in some statements.
17402 This is so that we can handle symbols that are an arbitrary distance from
17403 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17404 which returns part of an address in a form which will be valid for
17405 a data instruction. We do this by pushing the expression into a symbol
17406 in the expr_section, and creating a fix for that. */
17409 fix_new_arm (fragS
* frag
,
17423 /* Create an absolute valued symbol, so we have something to
17424 refer to in the object file. Unfortunately for us, gas's
17425 generic expression parsing will already have folded out
17426 any use of .set foo/.type foo %function that may have
17427 been used to set type information of the target location,
17428 that's being specified symbolically. We have to presume
17429 the user knows what they are doing. */
17433 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17435 symbol
= symbol_find_or_make (name
);
17436 S_SET_SEGMENT (symbol
, absolute_section
);
17437 symbol_set_frag (symbol
, &zero_address_frag
);
17438 S_SET_VALUE (symbol
, exp
->X_add_number
);
17439 exp
->X_op
= O_symbol
;
17440 exp
->X_add_symbol
= symbol
;
17441 exp
->X_add_number
= 0;
17447 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17448 (enum bfd_reloc_code_real
) reloc
);
17452 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17453 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17457 /* Mark whether the fix is to a THUMB instruction, or an ARM
17459 new_fix
->tc_fix_data
= thumb_mode
;
17462 /* Create a frg for an instruction requiring relaxation. */
17464 output_relax_insn (void)
17470 /* The size of the instruction is unknown, so tie the debug info to the
17471 start of the instruction. */
17472 dwarf2_emit_insn (0);
17474 switch (inst
.reloc
.exp
.X_op
)
17477 sym
= inst
.reloc
.exp
.X_add_symbol
;
17478 offset
= inst
.reloc
.exp
.X_add_number
;
17482 offset
= inst
.reloc
.exp
.X_add_number
;
17485 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17489 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17490 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17491 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17494 /* Write a 32-bit thumb instruction to buf. */
17496 put_thumb32_insn (char * buf
, unsigned long insn
)
17498 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17499 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17503 output_inst (const char * str
)
17509 as_bad ("%s -- `%s'", inst
.error
, str
);
17514 output_relax_insn ();
17517 if (inst
.size
== 0)
17520 to
= frag_more (inst
.size
);
17521 /* PR 9814: Record the thumb mode into the current frag so that we know
17522 what type of NOP padding to use, if necessary. We override any previous
17523 setting so that if the mode has changed then the NOPS that we use will
17524 match the encoding of the last instruction in the frag. */
17525 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17527 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17529 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17530 put_thumb32_insn (to
, inst
.instruction
);
17532 else if (inst
.size
> INSN_SIZE
)
17534 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17535 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17536 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17539 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17541 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17542 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17543 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17546 dwarf2_emit_insn (inst
.size
);
17550 output_it_inst (int cond
, int mask
, char * to
)
17552 unsigned long instruction
= 0xbf00;
17555 instruction
|= mask
;
17556 instruction
|= cond
<< 4;
17560 to
= frag_more (2);
17562 dwarf2_emit_insn (2);
17566 md_number_to_chars (to
, instruction
, 2);
17571 /* Tag values used in struct asm_opcode's tag field. */
17574 OT_unconditional
, /* Instruction cannot be conditionalized.
17575 The ARM condition field is still 0xE. */
17576 OT_unconditionalF
, /* Instruction cannot be conditionalized
17577 and carries 0xF in its ARM condition field. */
17578 OT_csuffix
, /* Instruction takes a conditional suffix. */
17579 OT_csuffixF
, /* Some forms of the instruction take a conditional
17580 suffix, others place 0xF where the condition field
17582 OT_cinfix3
, /* Instruction takes a conditional infix,
17583 beginning at character index 3. (In
17584 unified mode, it becomes a suffix.) */
17585 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17586 tsts, cmps, cmns, and teqs. */
17587 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17588 character index 3, even in unified mode. Used for
17589 legacy instructions where suffix and infix forms
17590 may be ambiguous. */
17591 OT_csuf_or_in3
, /* Instruction takes either a conditional
17592 suffix or an infix at character index 3. */
17593 OT_odd_infix_unc
, /* This is the unconditional variant of an
17594 instruction that takes a conditional infix
17595 at an unusual position. In unified mode,
17596 this variant will accept a suffix. */
17597 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17598 are the conditional variants of instructions that
17599 take conditional infixes in unusual positions.
17600 The infix appears at character index
17601 (tag - OT_odd_infix_0). These are not accepted
17602 in unified mode. */
17605 /* Subroutine of md_assemble, responsible for looking up the primary
17606 opcode from the mnemonic the user wrote. STR points to the
17607 beginning of the mnemonic.
17609 This is not simply a hash table lookup, because of conditional
17610 variants. Most instructions have conditional variants, which are
17611 expressed with a _conditional affix_ to the mnemonic. If we were
17612 to encode each conditional variant as a literal string in the opcode
17613 table, it would have approximately 20,000 entries.
17615 Most mnemonics take this affix as a suffix, and in unified syntax,
17616 'most' is upgraded to 'all'. However, in the divided syntax, some
17617 instructions take the affix as an infix, notably the s-variants of
17618 the arithmetic instructions. Of those instructions, all but six
17619 have the infix appear after the third character of the mnemonic.
17621 Accordingly, the algorithm for looking up primary opcodes given
17624 1. Look up the identifier in the opcode table.
17625 If we find a match, go to step U.
17627 2. Look up the last two characters of the identifier in the
17628 conditions table. If we find a match, look up the first N-2
17629 characters of the identifier in the opcode table. If we
17630 find a match, go to step CE.
17632 3. Look up the fourth and fifth characters of the identifier in
17633 the conditions table. If we find a match, extract those
17634 characters from the identifier, and look up the remaining
17635 characters in the opcode table. If we find a match, go
17640 U. Examine the tag field of the opcode structure, in case this is
17641 one of the six instructions with its conditional infix in an
17642 unusual place. If it is, the tag tells us where to find the
17643 infix; look it up in the conditions table and set inst.cond
17644 accordingly. Otherwise, this is an unconditional instruction.
17645 Again set inst.cond accordingly. Return the opcode structure.
17647 CE. Examine the tag field to make sure this is an instruction that
17648 should receive a conditional suffix. If it is not, fail.
17649 Otherwise, set inst.cond from the suffix we already looked up,
17650 and return the opcode structure.
17652 CM. Examine the tag field to make sure this is an instruction that
17653 should receive a conditional infix after the third character.
17654 If it is not, fail. Otherwise, undo the edits to the current
17655 line of input and proceed as for case CE. */
17657 static const struct asm_opcode
*
17658 opcode_lookup (char **str
)
17662 const struct asm_opcode
*opcode
;
17663 const struct asm_cond
*cond
;
17666 /* Scan up to the end of the mnemonic, which must end in white space,
17667 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17668 for (base
= end
= *str
; *end
!= '\0'; end
++)
17669 if (*end
== ' ' || *end
== '.')
17675 /* Handle a possible width suffix and/or Neon type suffix. */
17680 /* The .w and .n suffixes are only valid if the unified syntax is in
17682 if (unified_syntax
&& end
[1] == 'w')
17684 else if (unified_syntax
&& end
[1] == 'n')
17689 inst
.vectype
.elems
= 0;
17691 *str
= end
+ offset
;
17693 if (end
[offset
] == '.')
17695 /* See if we have a Neon type suffix (possible in either unified or
17696 non-unified ARM syntax mode). */
17697 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17700 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17706 /* Look for unaffixed or special-case affixed mnemonic. */
17707 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17712 if (opcode
->tag
< OT_odd_infix_0
)
17714 inst
.cond
= COND_ALWAYS
;
17718 if (warn_on_deprecated
&& unified_syntax
)
17719 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17720 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17721 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17724 inst
.cond
= cond
->value
;
17728 /* Cannot have a conditional suffix on a mnemonic of less than two
17730 if (end
- base
< 3)
17733 /* Look for suffixed mnemonic. */
17735 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17736 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17738 if (opcode
&& cond
)
17741 switch (opcode
->tag
)
17743 case OT_cinfix3_legacy
:
17744 /* Ignore conditional suffixes matched on infix only mnemonics. */
17748 case OT_cinfix3_deprecated
:
17749 case OT_odd_infix_unc
:
17750 if (!unified_syntax
)
17752 /* else fall through */
17756 case OT_csuf_or_in3
:
17757 inst
.cond
= cond
->value
;
17760 case OT_unconditional
:
17761 case OT_unconditionalF
:
17763 inst
.cond
= cond
->value
;
17766 /* Delayed diagnostic. */
17767 inst
.error
= BAD_COND
;
17768 inst
.cond
= COND_ALWAYS
;
17777 /* Cannot have a usual-position infix on a mnemonic of less than
17778 six characters (five would be a suffix). */
17779 if (end
- base
< 6)
17782 /* Look for infixed mnemonic in the usual position. */
17784 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17788 memcpy (save
, affix
, 2);
17789 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17790 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17792 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17793 memcpy (affix
, save
, 2);
17796 && (opcode
->tag
== OT_cinfix3
17797 || opcode
->tag
== OT_cinfix3_deprecated
17798 || opcode
->tag
== OT_csuf_or_in3
17799 || opcode
->tag
== OT_cinfix3_legacy
))
17802 if (warn_on_deprecated
&& unified_syntax
17803 && (opcode
->tag
== OT_cinfix3
17804 || opcode
->tag
== OT_cinfix3_deprecated
))
17805 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17807 inst
.cond
= cond
->value
;
17814 /* This function generates an initial IT instruction, leaving its block
17815 virtually open for the new instructions. Eventually,
17816 the mask will be updated by now_it_add_mask () each time
17817 a new instruction needs to be included in the IT block.
17818 Finally, the block is closed with close_automatic_it_block ().
17819 The block closure can be requested either from md_assemble (),
17820 a tencode (), or due to a label hook. */
17823 new_automatic_it_block (int cond
)
17825 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17826 now_it
.mask
= 0x18;
17828 now_it
.block_length
= 1;
17829 mapping_state (MAP_THUMB
);
17830 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17831 now_it
.warn_deprecated
= FALSE
;
17832 now_it
.insn_cond
= TRUE
;
17835 /* Close an automatic IT block.
17836 See comments in new_automatic_it_block (). */
17839 close_automatic_it_block (void)
17841 now_it
.mask
= 0x10;
17842 now_it
.block_length
= 0;
17845 /* Update the mask of the current automatically-generated IT
17846 instruction. See comments in new_automatic_it_block (). */
17849 now_it_add_mask (int cond
)
17851 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17852 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17853 | ((bitvalue) << (nbit)))
17854 const int resulting_bit
= (cond
& 1);
17856 now_it
.mask
&= 0xf;
17857 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17859 (5 - now_it
.block_length
));
17860 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17862 ((5 - now_it
.block_length
) - 1) );
17863 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17866 #undef SET_BIT_VALUE
17869 /* The IT blocks handling machinery is accessed through the these functions:
17870 it_fsm_pre_encode () from md_assemble ()
17871 set_it_insn_type () optional, from the tencode functions
17872 set_it_insn_type_last () ditto
17873 in_it_block () ditto
17874 it_fsm_post_encode () from md_assemble ()
17875 force_automatic_it_block_close () from label habdling functions
17878 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17879 initializing the IT insn type with a generic initial value depending
17880 on the inst.condition.
17881 2) During the tencode function, two things may happen:
17882 a) The tencode function overrides the IT insn type by
17883 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17884 b) The tencode function queries the IT block state by
17885 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17887 Both set_it_insn_type and in_it_block run the internal FSM state
17888 handling function (handle_it_state), because: a) setting the IT insn
17889 type may incur in an invalid state (exiting the function),
17890 and b) querying the state requires the FSM to be updated.
17891 Specifically we want to avoid creating an IT block for conditional
17892 branches, so it_fsm_pre_encode is actually a guess and we can't
17893 determine whether an IT block is required until the tencode () routine
17894 has decided what type of instruction this actually it.
17895 Because of this, if set_it_insn_type and in_it_block have to be used,
17896 set_it_insn_type has to be called first.
17898 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17899 determines the insn IT type depending on the inst.cond code.
17900 When a tencode () routine encodes an instruction that can be
17901 either outside an IT block, or, in the case of being inside, has to be
17902 the last one, set_it_insn_type_last () will determine the proper
17903 IT instruction type based on the inst.cond code. Otherwise,
17904 set_it_insn_type can be called for overriding that logic or
17905 for covering other cases.
17907 Calling handle_it_state () may not transition the IT block state to
17908 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17909 still queried. Instead, if the FSM determines that the state should
17910 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17911 after the tencode () function: that's what it_fsm_post_encode () does.
17913 Since in_it_block () calls the state handling function to get an
17914 updated state, an error may occur (due to invalid insns combination).
17915 In that case, inst.error is set.
17916 Therefore, inst.error has to be checked after the execution of
17917 the tencode () routine.
17919 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17920 any pending state change (if any) that didn't take place in
17921 handle_it_state () as explained above. */
17924 it_fsm_pre_encode (void)
17926 if (inst
.cond
!= COND_ALWAYS
)
17927 inst
.it_insn_type
= INSIDE_IT_INSN
;
17929 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17931 now_it
.state_handled
= 0;
17934 /* IT state FSM handling function. */
17937 handle_it_state (void)
17939 now_it
.state_handled
= 1;
17940 now_it
.insn_cond
= FALSE
;
17942 switch (now_it
.state
)
17944 case OUTSIDE_IT_BLOCK
:
17945 switch (inst
.it_insn_type
)
17947 case OUTSIDE_IT_INSN
:
17950 case INSIDE_IT_INSN
:
17951 case INSIDE_IT_LAST_INSN
:
17952 if (thumb_mode
== 0)
17955 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17956 as_tsktsk (_("Warning: conditional outside an IT block"\
17961 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17962 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17964 /* Automatically generate the IT instruction. */
17965 new_automatic_it_block (inst
.cond
);
17966 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17967 close_automatic_it_block ();
17971 inst
.error
= BAD_OUT_IT
;
17977 case IF_INSIDE_IT_LAST_INSN
:
17978 case NEUTRAL_IT_INSN
:
17982 now_it
.state
= MANUAL_IT_BLOCK
;
17983 now_it
.block_length
= 0;
17988 case AUTOMATIC_IT_BLOCK
:
17989 /* Three things may happen now:
17990 a) We should increment current it block size;
17991 b) We should close current it block (closing insn or 4 insns);
17992 c) We should close current it block and start a new one (due
17993 to incompatible conditions or
17994 4 insns-length block reached). */
17996 switch (inst
.it_insn_type
)
17998 case OUTSIDE_IT_INSN
:
17999 /* The closure of the block shall happen immediatelly,
18000 so any in_it_block () call reports the block as closed. */
18001 force_automatic_it_block_close ();
18004 case INSIDE_IT_INSN
:
18005 case INSIDE_IT_LAST_INSN
:
18006 case IF_INSIDE_IT_LAST_INSN
:
18007 now_it
.block_length
++;
18009 if (now_it
.block_length
> 4
18010 || !now_it_compatible (inst
.cond
))
18012 force_automatic_it_block_close ();
18013 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18014 new_automatic_it_block (inst
.cond
);
18018 now_it
.insn_cond
= TRUE
;
18019 now_it_add_mask (inst
.cond
);
18022 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18023 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18024 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18025 close_automatic_it_block ();
18028 case NEUTRAL_IT_INSN
:
18029 now_it
.block_length
++;
18030 now_it
.insn_cond
= TRUE
;
18032 if (now_it
.block_length
> 4)
18033 force_automatic_it_block_close ();
18035 now_it_add_mask (now_it
.cc
& 1);
18039 close_automatic_it_block ();
18040 now_it
.state
= MANUAL_IT_BLOCK
;
18045 case MANUAL_IT_BLOCK
:
18047 /* Check conditional suffixes. */
18048 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18051 now_it
.mask
&= 0x1f;
18052 is_last
= (now_it
.mask
== 0x10);
18053 now_it
.insn_cond
= TRUE
;
18055 switch (inst
.it_insn_type
)
18057 case OUTSIDE_IT_INSN
:
18058 inst
.error
= BAD_NOT_IT
;
18061 case INSIDE_IT_INSN
:
18062 if (cond
!= inst
.cond
)
18064 inst
.error
= BAD_IT_COND
;
18069 case INSIDE_IT_LAST_INSN
:
18070 case IF_INSIDE_IT_LAST_INSN
:
18071 if (cond
!= inst
.cond
)
18073 inst
.error
= BAD_IT_COND
;
18078 inst
.error
= BAD_BRANCH
;
18083 case NEUTRAL_IT_INSN
:
18084 /* The BKPT instruction is unconditional even in an IT block. */
18088 inst
.error
= BAD_IT_IT
;
18098 struct depr_insn_mask
18100 unsigned long pattern
;
18101 unsigned long mask
;
18102 const char* description
;
18105 /* List of 16-bit instruction patterns deprecated in an IT block in
18107 static const struct depr_insn_mask depr_it_insns
[] = {
18108 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18109 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18110 { 0xa000, 0xb800, N_("ADR") },
18111 { 0x4800, 0xf800, N_("Literal loads") },
18112 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18113 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18114 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18115 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18116 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18121 it_fsm_post_encode (void)
18125 if (!now_it
.state_handled
)
18126 handle_it_state ();
18128 if (now_it
.insn_cond
18129 && !now_it
.warn_deprecated
18130 && warn_on_deprecated
18131 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18133 if (inst
.instruction
>= 0x10000)
18135 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18136 "deprecated in ARMv8"));
18137 now_it
.warn_deprecated
= TRUE
;
18141 const struct depr_insn_mask
*p
= depr_it_insns
;
18143 while (p
->mask
!= 0)
18145 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18147 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18148 "of the following class are deprecated in ARMv8: "
18149 "%s"), p
->description
);
18150 now_it
.warn_deprecated
= TRUE
;
18158 if (now_it
.block_length
> 1)
18160 as_tsktsk (_("IT blocks containing more than one conditional "
18161 "instruction are deprecated in ARMv8"));
18162 now_it
.warn_deprecated
= TRUE
;
18166 is_last
= (now_it
.mask
== 0x10);
18169 now_it
.state
= OUTSIDE_IT_BLOCK
;
18175 force_automatic_it_block_close (void)
18177 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18179 close_automatic_it_block ();
18180 now_it
.state
= OUTSIDE_IT_BLOCK
;
18188 if (!now_it
.state_handled
)
18189 handle_it_state ();
18191 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18194 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18195 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18196 here, hence the "known" in the function name. */
18199 known_t32_only_insn (const struct asm_opcode
*opcode
)
18201 /* Original Thumb-1 wide instruction. */
18202 if (opcode
->tencode
== do_t_blx
18203 || opcode
->tencode
== do_t_branch23
18204 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18205 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18208 /* Wide-only instruction added to ARMv8-M Baseline. */
18209 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18210 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18211 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18212 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18218 /* Whether wide instruction variant can be used if available for a valid OPCODE
18222 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18224 if (known_t32_only_insn (opcode
))
18227 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18228 of variant T3 of B.W is checked in do_t_branch. */
18229 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18230 && opcode
->tencode
== do_t_branch
)
18233 /* Wide instruction variants of all instructions with narrow *and* wide
18234 variants become available with ARMv6t2. Other opcodes are either
18235 narrow-only or wide-only and are thus available if OPCODE is valid. */
18236 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18239 /* OPCODE with narrow only instruction variant or wide variant not
18245 md_assemble (char *str
)
18248 const struct asm_opcode
* opcode
;
18250 /* Align the previous label if needed. */
18251 if (last_label_seen
!= NULL
)
18253 symbol_set_frag (last_label_seen
, frag_now
);
18254 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18255 S_SET_SEGMENT (last_label_seen
, now_seg
);
18258 memset (&inst
, '\0', sizeof (inst
));
18259 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18261 opcode
= opcode_lookup (&p
);
18264 /* It wasn't an instruction, but it might be a register alias of
18265 the form alias .req reg, or a Neon .dn/.qn directive. */
18266 if (! create_register_alias (str
, p
)
18267 && ! create_neon_reg_alias (str
, p
))
18268 as_bad (_("bad instruction `%s'"), str
);
18273 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18274 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18276 /* The value which unconditional instructions should have in place of the
18277 condition field. */
18278 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18282 arm_feature_set variant
;
18284 variant
= cpu_variant
;
18285 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18286 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18287 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18288 /* Check that this instruction is supported for this CPU. */
18289 if (!opcode
->tvariant
18290 || (thumb_mode
== 1
18291 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18293 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18296 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18297 && opcode
->tencode
!= do_t_branch
)
18299 as_bad (_("Thumb does not support conditional execution"));
18303 /* Two things are addressed here:
18304 1) Implicit require narrow instructions on Thumb-1.
18305 This avoids relaxation accidentally introducing Thumb-2
18307 2) Reject wide instructions in non Thumb-2 cores.
18309 Only instructions with narrow and wide variants need to be handled
18310 but selecting all non wide-only instructions is easier. */
18311 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18312 && !t32_insn_ok (variant
, opcode
))
18314 if (inst
.size_req
== 0)
18316 else if (inst
.size_req
== 4)
18318 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18319 as_bad (_("selected processor does not support 32bit wide "
18320 "variant of instruction `%s'"), str
);
18322 as_bad (_("selected processor does not support `%s' in "
18323 "Thumb-2 mode"), str
);
18328 inst
.instruction
= opcode
->tvalue
;
18330 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18332 /* Prepare the it_insn_type for those encodings that don't set
18334 it_fsm_pre_encode ();
18336 opcode
->tencode ();
18338 it_fsm_post_encode ();
18341 if (!(inst
.error
|| inst
.relax
))
18343 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18344 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18345 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18347 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18352 /* Something has gone badly wrong if we try to relax a fixed size
18354 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18356 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18357 *opcode
->tvariant
);
18358 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18359 set those bits when Thumb-2 32-bit instructions are seen. The impact
18360 of relaxable instructions will be considered later after we finish all
18362 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18363 variant
= arm_arch_none
;
18365 variant
= cpu_variant
;
18366 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18367 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18370 check_neon_suffixes
;
18374 mapping_state (MAP_THUMB
);
18377 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18381 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18382 is_bx
= (opcode
->aencode
== do_bx
);
18384 /* Check that this instruction is supported for this CPU. */
18385 if (!(is_bx
&& fix_v4bx
)
18386 && !(opcode
->avariant
&&
18387 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18389 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18394 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18398 inst
.instruction
= opcode
->avalue
;
18399 if (opcode
->tag
== OT_unconditionalF
)
18400 inst
.instruction
|= 0xFU
<< 28;
18402 inst
.instruction
|= inst
.cond
<< 28;
18403 inst
.size
= INSN_SIZE
;
18404 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18406 it_fsm_pre_encode ();
18407 opcode
->aencode ();
18408 it_fsm_post_encode ();
18410 /* Arm mode bx is marked as both v4T and v5 because it's still required
18411 on a hypothetical non-thumb v5 core. */
18413 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18415 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18416 *opcode
->avariant
);
18418 check_neon_suffixes
;
18422 mapping_state (MAP_ARM
);
18427 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18435 check_it_blocks_finished (void)
18440 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18441 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18442 == MANUAL_IT_BLOCK
)
18444 as_warn (_("section '%s' finished with an open IT block."),
18448 if (now_it
.state
== MANUAL_IT_BLOCK
)
18449 as_warn (_("file finished with an open IT block."));
18453 /* Various frobbings of labels and their addresses. */
18456 arm_start_line_hook (void)
18458 last_label_seen
= NULL
;
18462 arm_frob_label (symbolS
* sym
)
18464 last_label_seen
= sym
;
18466 ARM_SET_THUMB (sym
, thumb_mode
);
18468 #if defined OBJ_COFF || defined OBJ_ELF
18469 ARM_SET_INTERWORK (sym
, support_interwork
);
18472 force_automatic_it_block_close ();
18474 /* Note - do not allow local symbols (.Lxxx) to be labelled
18475 as Thumb functions. This is because these labels, whilst
18476 they exist inside Thumb code, are not the entry points for
18477 possible ARM->Thumb calls. Also, these labels can be used
18478 as part of a computed goto or switch statement. eg gcc
18479 can generate code that looks like this:
18481 ldr r2, [pc, .Laaa]
18491 The first instruction loads the address of the jump table.
18492 The second instruction converts a table index into a byte offset.
18493 The third instruction gets the jump address out of the table.
18494 The fourth instruction performs the jump.
18496 If the address stored at .Laaa is that of a symbol which has the
18497 Thumb_Func bit set, then the linker will arrange for this address
18498 to have the bottom bit set, which in turn would mean that the
18499 address computation performed by the third instruction would end
18500 up with the bottom bit set. Since the ARM is capable of unaligned
18501 word loads, the instruction would then load the incorrect address
18502 out of the jump table, and chaos would ensue. */
18503 if (label_is_thumb_function_name
18504 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18505 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18507 /* When the address of a Thumb function is taken the bottom
18508 bit of that address should be set. This will allow
18509 interworking between Arm and Thumb functions to work
18512 THUMB_SET_FUNC (sym
, 1);
18514 label_is_thumb_function_name
= FALSE
;
18517 dwarf2_emit_label (sym
);
18521 arm_data_in_code (void)
18523 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18525 *input_line_pointer
= '/';
18526 input_line_pointer
+= 5;
18527 *input_line_pointer
= 0;
18535 arm_canonicalize_symbol_name (char * name
)
18539 if (thumb_mode
&& (len
= strlen (name
)) > 5
18540 && streq (name
+ len
- 5, "/data"))
18541 *(name
+ len
- 5) = 0;
18546 /* Table of all register names defined by default. The user can
18547 define additional names with .req. Note that all register names
18548 should appear in both upper and lowercase variants. Some registers
18549 also have mixed-case names. */
18551 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18552 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18553 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18554 #define REGSET(p,t) \
18555 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18556 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18557 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18558 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18559 #define REGSETH(p,t) \
18560 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18561 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18562 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18563 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18564 #define REGSET2(p,t) \
18565 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18566 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18567 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18568 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18569 #define SPLRBANK(base,bank,t) \
18570 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18571 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18572 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18573 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18574 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18575 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18577 static const struct reg_entry reg_names
[] =
18579 /* ARM integer registers. */
18580 REGSET(r
, RN
), REGSET(R
, RN
),
18582 /* ATPCS synonyms. */
18583 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18584 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18585 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18587 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18588 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18589 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18591 /* Well-known aliases. */
18592 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18593 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18595 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18596 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18598 /* Coprocessor numbers. */
18599 REGSET(p
, CP
), REGSET(P
, CP
),
18601 /* Coprocessor register numbers. The "cr" variants are for backward
18603 REGSET(c
, CN
), REGSET(C
, CN
),
18604 REGSET(cr
, CN
), REGSET(CR
, CN
),
18606 /* ARM banked registers. */
18607 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18608 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18609 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18610 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18611 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18612 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18613 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18615 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18616 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18617 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18618 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18619 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18620 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18621 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18622 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18624 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18625 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18626 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18627 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18628 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18629 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18630 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18631 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18632 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18634 /* FPA registers. */
18635 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18636 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18638 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18639 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18641 /* VFP SP registers. */
18642 REGSET(s
,VFS
), REGSET(S
,VFS
),
18643 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18645 /* VFP DP Registers. */
18646 REGSET(d
,VFD
), REGSET(D
,VFD
),
18647 /* Extra Neon DP registers. */
18648 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18650 /* Neon QP registers. */
18651 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18653 /* VFP control registers. */
18654 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18655 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18656 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18657 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18658 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18659 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18661 /* Maverick DSP coprocessor registers. */
18662 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18663 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18665 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18666 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18667 REGDEF(dspsc
,0,DSPSC
),
18669 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18670 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18671 REGDEF(DSPSC
,0,DSPSC
),
18673 /* iWMMXt data registers - p0, c0-15. */
18674 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18676 /* iWMMXt control registers - p1, c0-3. */
18677 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18678 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18679 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18680 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18682 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18683 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18684 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18685 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18686 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18688 /* XScale accumulator registers. */
18689 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18695 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18696 within psr_required_here. */
18697 static const struct asm_psr psrs
[] =
18699 /* Backward compatibility notation. Note that "all" is no longer
18700 truly all possible PSR bits. */
18701 {"all", PSR_c
| PSR_f
},
18705 /* Individual flags. */
18711 /* Combinations of flags. */
18712 {"fs", PSR_f
| PSR_s
},
18713 {"fx", PSR_f
| PSR_x
},
18714 {"fc", PSR_f
| PSR_c
},
18715 {"sf", PSR_s
| PSR_f
},
18716 {"sx", PSR_s
| PSR_x
},
18717 {"sc", PSR_s
| PSR_c
},
18718 {"xf", PSR_x
| PSR_f
},
18719 {"xs", PSR_x
| PSR_s
},
18720 {"xc", PSR_x
| PSR_c
},
18721 {"cf", PSR_c
| PSR_f
},
18722 {"cs", PSR_c
| PSR_s
},
18723 {"cx", PSR_c
| PSR_x
},
18724 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18725 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18726 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18727 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18728 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18729 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18730 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18731 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18732 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18733 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18734 {"scf", PSR_s
| PSR_c
| PSR_f
},
18735 {"scx", PSR_s
| PSR_c
| PSR_x
},
18736 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18737 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18738 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18739 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18740 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18741 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18742 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18743 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18744 {"csf", PSR_c
| PSR_s
| PSR_f
},
18745 {"csx", PSR_c
| PSR_s
| PSR_x
},
18746 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18747 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18748 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18749 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18750 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18751 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18752 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18753 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18754 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18755 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18756 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18757 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18758 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18759 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18760 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18761 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18762 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18763 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18764 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18765 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18766 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18767 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18768 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18769 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18770 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18771 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18774 /* Table of V7M psr names. */
18775 static const struct asm_psr v7m_psrs
[] =
18777 {"apsr", 0 }, {"APSR", 0 },
18778 {"iapsr", 1 }, {"IAPSR", 1 },
18779 {"eapsr", 2 }, {"EAPSR", 2 },
18780 {"psr", 3 }, {"PSR", 3 },
18781 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18782 {"ipsr", 5 }, {"IPSR", 5 },
18783 {"epsr", 6 }, {"EPSR", 6 },
18784 {"iepsr", 7 }, {"IEPSR", 7 },
18785 {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
18786 {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
18787 {"primask", 16}, {"PRIMASK", 16},
18788 {"basepri", 17}, {"BASEPRI", 17},
18789 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18790 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18791 {"faultmask", 19}, {"FAULTMASK", 19},
18792 {"control", 20}, {"CONTROL", 20},
18793 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18794 {"psp_ns", 0x89}, {"PSP_NS", 0x89}
18797 /* Table of all shift-in-operand names. */
18798 static const struct asm_shift_name shift_names
[] =
18800 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18801 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18802 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18803 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18804 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18805 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18808 /* Table of all explicit relocation names. */
18810 static struct reloc_entry reloc_names
[] =
18812 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18813 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18814 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18815 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18816 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18817 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18818 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18819 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18820 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18821 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18822 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18823 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18824 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18825 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18826 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18827 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18828 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18829 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18833 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18834 static const struct asm_cond conds
[] =
18838 {"cs", 0x2}, {"hs", 0x2},
18839 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18853 #define UL_BARRIER(L,U,CODE,FEAT) \
18854 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18855 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18857 static struct asm_barrier_opt barrier_opt_names
[] =
18859 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18860 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18861 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18862 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18863 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18864 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18865 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18866 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18867 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18868 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18869 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18870 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18871 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18872 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18873 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18874 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18879 /* Table of ARM-format instructions. */
18881 /* Macros for gluing together operand strings. N.B. In all cases
18882 other than OPS0, the trailing OP_stop comes from default
18883 zero-initialization of the unspecified elements of the array. */
18884 #define OPS0() { OP_stop, }
18885 #define OPS1(a) { OP_##a, }
18886 #define OPS2(a,b) { OP_##a,OP_##b, }
18887 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18888 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18889 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18890 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18892 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18893 This is useful when mixing operands for ARM and THUMB, i.e. using the
18894 MIX_ARM_THUMB_OPERANDS macro.
18895 In order to use these macros, prefix the number of operands with _
18897 #define OPS_1(a) { a, }
18898 #define OPS_2(a,b) { a,b, }
18899 #define OPS_3(a,b,c) { a,b,c, }
18900 #define OPS_4(a,b,c,d) { a,b,c,d, }
18901 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18902 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18904 /* These macros abstract out the exact format of the mnemonic table and
18905 save some repeated characters. */
18907 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18908 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18909 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18910 THUMB_VARIANT, do_##ae, do_##te }
18912 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18913 a T_MNEM_xyz enumerator. */
18914 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18915 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18916 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18917 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18919 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18920 infix after the third character. */
18921 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18922 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18923 THUMB_VARIANT, do_##ae, do_##te }
18924 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18925 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18926 THUMB_VARIANT, do_##ae, do_##te }
18927 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18928 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18929 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18930 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18931 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18932 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18933 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18934 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18936 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18937 field is still 0xE. Many of the Thumb variants can be executed
18938 conditionally, so this is checked separately. */
18939 #define TUE(mnem, op, top, nops, ops, ae, te) \
18940 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18941 THUMB_VARIANT, do_##ae, do_##te }
18943 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18944 Used by mnemonics that have very minimal differences in the encoding for
18945 ARM and Thumb variants and can be handled in a common function. */
18946 #define TUEc(mnem, op, top, nops, ops, en) \
18947 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18948 THUMB_VARIANT, do_##en, do_##en }
18950 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18951 condition code field. */
18952 #define TUF(mnem, op, top, nops, ops, ae, te) \
18953 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18954 THUMB_VARIANT, do_##ae, do_##te }
18956 /* ARM-only variants of all the above. */
18957 #define CE(mnem, op, nops, ops, ae) \
18958 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18960 #define C3(mnem, op, nops, ops, ae) \
18961 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18963 /* Legacy mnemonics that always have conditional infix after the third
18965 #define CL(mnem, op, nops, ops, ae) \
18966 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18967 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18969 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18970 #define cCE(mnem, op, nops, ops, ae) \
18971 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18973 /* Legacy coprocessor instructions where conditional infix and conditional
18974 suffix are ambiguous. For consistency this includes all FPA instructions,
18975 not just the potentially ambiguous ones. */
18976 #define cCL(mnem, op, nops, ops, ae) \
18977 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18978 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18980 /* Coprocessor, takes either a suffix or a position-3 infix
18981 (for an FPA corner case). */
18982 #define C3E(mnem, op, nops, ops, ae) \
18983 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18984 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18986 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18987 { m1 #m2 m3, OPS##nops ops, \
18988 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18989 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18991 #define CM(m1, m2, op, nops, ops, ae) \
18992 xCM_ (m1, , m2, op, nops, ops, ae), \
18993 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18994 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18995 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18996 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18997 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18998 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18999 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19000 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19001 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19002 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19003 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19004 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19005 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19006 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19007 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19008 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19009 xCM_ (m1, le, m2, op, nops, ops, ae), \
19010 xCM_ (m1, al, m2, op, nops, ops, ae)
19012 #define UE(mnem, op, nops, ops, ae) \
19013 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19015 #define UF(mnem, op, nops, ops, ae) \
19016 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19018 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19019 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19020 use the same encoding function for each. */
19021 #define NUF(mnem, op, nops, ops, enc) \
19022 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19023 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19025 /* Neon data processing, version which indirects through neon_enc_tab for
19026 the various overloaded versions of opcodes. */
19027 #define nUF(mnem, op, nops, ops, enc) \
19028 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19029 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19031 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19033 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19034 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19035 THUMB_VARIANT, do_##enc, do_##enc }
19037 #define NCE(mnem, op, nops, ops, enc) \
19038 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19040 #define NCEF(mnem, op, nops, ops, enc) \
19041 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19043 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19044 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19045 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19046 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19048 #define nCE(mnem, op, nops, ops, enc) \
19049 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19051 #define nCEF(mnem, op, nops, ops, enc) \
19052 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19056 static const struct asm_opcode insns
[] =
19058 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19059 #define THUMB_VARIANT & arm_ext_v4t
19060 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19061 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19062 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19063 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19064 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19065 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19066 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19067 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19068 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19069 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19070 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19071 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19072 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19073 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19074 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19075 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19077 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19078 for setting PSR flag bits. They are obsolete in V6 and do not
19079 have Thumb equivalents. */
19080 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19081 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19082 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19083 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19084 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19085 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19086 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19087 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19088 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19090 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19091 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19092 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19093 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19095 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19096 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19097 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19099 OP_ADDRGLDR
),ldst
, t_ldst
),
19100 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19102 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19103 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19104 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19105 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19106 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19107 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19109 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19110 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19111 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19112 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19115 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19116 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19117 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19118 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19120 /* Thumb-compatibility pseudo ops. */
19121 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19122 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19123 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19124 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19125 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19126 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19127 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19128 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19129 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19130 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19131 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19132 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19134 /* These may simplify to neg. */
19135 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19136 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19138 #undef THUMB_VARIANT
19139 #define THUMB_VARIANT & arm_ext_v6
19141 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19143 /* V1 instructions with no Thumb analogue prior to V6T2. */
19144 #undef THUMB_VARIANT
19145 #define THUMB_VARIANT & arm_ext_v6t2
19147 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19148 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19149 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19151 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19152 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19153 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19154 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19156 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19157 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19159 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19160 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19162 /* V1 instructions with no Thumb analogue at all. */
19163 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19164 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19166 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19167 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19168 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19169 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19170 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19171 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19172 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19173 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19176 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19177 #undef THUMB_VARIANT
19178 #define THUMB_VARIANT & arm_ext_v4t
19180 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19181 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19183 #undef THUMB_VARIANT
19184 #define THUMB_VARIANT & arm_ext_v6t2
19186 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19187 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19189 /* Generic coprocessor instructions. */
19190 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19191 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19192 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19193 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19194 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19195 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19196 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19199 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19201 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19202 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19205 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19206 #undef THUMB_VARIANT
19207 #define THUMB_VARIANT & arm_ext_msr
19209 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19210 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19213 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19214 #undef THUMB_VARIANT
19215 #define THUMB_VARIANT & arm_ext_v6t2
19217 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19218 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19219 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19220 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19221 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19222 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19223 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19224 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19227 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19228 #undef THUMB_VARIANT
19229 #define THUMB_VARIANT & arm_ext_v4t
19231 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19232 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19233 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19234 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19235 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19236 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19239 #define ARM_VARIANT & arm_ext_v4t_5
19241 /* ARM Architecture 4T. */
19242 /* Note: bx (and blx) are required on V5, even if the processor does
19243 not support Thumb. */
19244 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19247 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19248 #undef THUMB_VARIANT
19249 #define THUMB_VARIANT & arm_ext_v5t
19251 /* Note: blx has 2 variants; the .value coded here is for
19252 BLX(2). Only this variant has conditional execution. */
19253 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19254 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19256 #undef THUMB_VARIANT
19257 #define THUMB_VARIANT & arm_ext_v6t2
19259 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19260 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19261 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19262 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19263 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19264 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19265 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19266 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19269 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19270 #undef THUMB_VARIANT
19271 #define THUMB_VARIANT & arm_ext_v5exp
19273 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19274 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19275 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19276 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19278 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19279 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19281 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19282 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19283 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19284 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19286 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19287 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19288 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19289 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19291 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19292 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19294 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19295 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19296 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19297 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19300 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19301 #undef THUMB_VARIANT
19302 #define THUMB_VARIANT & arm_ext_v6t2
19304 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19305 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19307 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19308 ADDRGLDRS
), ldrd
, t_ldstd
),
19310 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19311 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19314 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19316 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19319 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19320 #undef THUMB_VARIANT
19321 #define THUMB_VARIANT & arm_ext_v6
19323 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19324 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19325 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19326 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19327 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19328 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19329 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19330 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19331 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19332 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19334 #undef THUMB_VARIANT
19335 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19337 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19338 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19340 #undef THUMB_VARIANT
19341 #define THUMB_VARIANT & arm_ext_v6t2
19343 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19344 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19346 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19347 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19349 /* ARM V6 not included in V7M. */
19350 #undef THUMB_VARIANT
19351 #define THUMB_VARIANT & arm_ext_v6_notm
19352 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19353 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19354 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19355 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19356 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19357 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19358 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19359 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19360 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19361 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19362 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19363 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19364 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19365 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19366 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19367 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19368 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19369 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19370 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19372 /* ARM V6 not included in V7M (eg. integer SIMD). */
19373 #undef THUMB_VARIANT
19374 #define THUMB_VARIANT & arm_ext_v6_dsp
19375 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19376 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19377 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19378 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19379 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19380 /* Old name for QASX. */
19381 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19382 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19383 /* Old name for QSAX. */
19384 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19385 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19386 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19387 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19388 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19389 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19390 /* Old name for SASX. */
19391 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19392 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19393 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19394 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19395 /* Old name for SHASX. */
19396 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19397 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19398 /* Old name for SHSAX. */
19399 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19400 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19401 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19402 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 /* Old name for SSAX. */
19404 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19405 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19407 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19408 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19409 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19410 /* Old name for UASX. */
19411 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19412 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19413 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19414 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 /* Old name for UHASX. */
19416 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19417 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19418 /* Old name for UHSAX. */
19419 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19420 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19421 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19422 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19423 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19424 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19425 /* Old name for UQASX. */
19426 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19427 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 /* Old name for UQSAX. */
19429 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19430 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19431 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19432 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19433 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19434 /* Old name for USAX. */
19435 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19436 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19437 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19438 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19439 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19440 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19441 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19442 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19443 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19444 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19445 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19446 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19447 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19448 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19449 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19450 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19451 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19452 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19453 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19454 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19455 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19456 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19457 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19458 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19459 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19460 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19461 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19462 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19463 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19464 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19465 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19466 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19467 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19468 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19471 #define ARM_VARIANT & arm_ext_v6k
19472 #undef THUMB_VARIANT
19473 #define THUMB_VARIANT & arm_ext_v6k
19475 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19476 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19477 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19478 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19480 #undef THUMB_VARIANT
19481 #define THUMB_VARIANT & arm_ext_v6_notm
19482 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19484 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19485 RRnpcb
), strexd
, t_strexd
),
19487 #undef THUMB_VARIANT
19488 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19489 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19491 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19493 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19495 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19497 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19500 #define ARM_VARIANT & arm_ext_sec
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & arm_ext_sec
19504 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19507 #define ARM_VARIANT & arm_ext_virt
19508 #undef THUMB_VARIANT
19509 #define THUMB_VARIANT & arm_ext_virt
19511 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19512 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19515 #define ARM_VARIANT & arm_ext_pan
19516 #undef THUMB_VARIANT
19517 #define THUMB_VARIANT & arm_ext_pan
19519 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19522 #define ARM_VARIANT & arm_ext_v6t2
19523 #undef THUMB_VARIANT
19524 #define THUMB_VARIANT & arm_ext_v6t2
19526 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19527 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19528 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19529 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19531 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19532 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19534 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19535 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19536 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19537 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19539 #undef THUMB_VARIANT
19540 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19541 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19542 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19544 /* Thumb-only instructions. */
19546 #define ARM_VARIANT NULL
19547 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19548 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19550 /* ARM does not really have an IT instruction, so always allow it.
19551 The opcode is copied from Thumb in order to allow warnings in
19552 -mimplicit-it=[never | arm] modes. */
19554 #define ARM_VARIANT & arm_ext_v1
19555 #undef THUMB_VARIANT
19556 #define THUMB_VARIANT & arm_ext_v6t2
19558 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19559 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19560 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19561 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19562 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19563 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19564 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19565 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19566 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19567 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19568 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19569 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19570 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19571 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19572 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19573 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19574 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19575 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19577 /* Thumb2 only instructions. */
19579 #define ARM_VARIANT NULL
19581 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19582 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19583 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19584 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19585 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19586 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19588 /* Hardware division instructions. */
19590 #define ARM_VARIANT & arm_ext_adiv
19591 #undef THUMB_VARIANT
19592 #define THUMB_VARIANT & arm_ext_div
19594 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19595 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19597 /* ARM V6M/V7 instructions. */
19599 #define ARM_VARIANT & arm_ext_barrier
19600 #undef THUMB_VARIANT
19601 #define THUMB_VARIANT & arm_ext_barrier
19603 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19604 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19605 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19607 /* ARM V7 instructions. */
19609 #define ARM_VARIANT & arm_ext_v7
19610 #undef THUMB_VARIANT
19611 #define THUMB_VARIANT & arm_ext_v7
19613 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19614 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19617 #define ARM_VARIANT & arm_ext_mp
19618 #undef THUMB_VARIANT
19619 #define THUMB_VARIANT & arm_ext_mp
19621 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19623 /* AArchv8 instructions. */
19625 #define ARM_VARIANT & arm_ext_v8
19627 /* Instructions shared between armv8-a and armv8-m. */
19628 #undef THUMB_VARIANT
19629 #define THUMB_VARIANT & arm_ext_atomics
19631 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19632 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19633 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19634 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19635 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19636 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19637 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19638 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19639 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19640 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19642 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19644 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19646 #undef THUMB_VARIANT
19647 #define THUMB_VARIANT & arm_ext_v8
19649 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19650 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19651 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19653 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19655 /* ARMv8 T32 only. */
19657 #define ARM_VARIANT NULL
19658 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19659 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19660 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19662 /* FP for ARMv8. */
19664 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19665 #undef THUMB_VARIANT
19666 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19668 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19669 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19670 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19671 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19672 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19673 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19674 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19675 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19676 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19677 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19678 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19679 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19680 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19681 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19682 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19683 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19684 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19686 /* Crypto v1 extensions. */
19688 #define ARM_VARIANT & fpu_crypto_ext_armv8
19689 #undef THUMB_VARIANT
19690 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19692 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19693 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19694 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19695 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19696 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19697 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19698 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19699 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19700 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19701 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19702 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19703 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19704 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19705 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19708 #define ARM_VARIANT & crc_ext_armv8
19709 #undef THUMB_VARIANT
19710 #define THUMB_VARIANT & crc_ext_armv8
19711 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19712 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19713 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19714 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19715 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19716 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19718 /* ARMv8.2 RAS extension. */
19720 #define ARM_VARIANT & arm_ext_v8_2
19721 #undef THUMB_VARIANT
19722 #define THUMB_VARIANT & arm_ext_v8_2
19723 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19726 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19727 #undef THUMB_VARIANT
19728 #define THUMB_VARIANT NULL
19730 cCE("wfs", e200110
, 1, (RR
), rd
),
19731 cCE("rfs", e300110
, 1, (RR
), rd
),
19732 cCE("wfc", e400110
, 1, (RR
), rd
),
19733 cCE("rfc", e500110
, 1, (RR
), rd
),
19735 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19736 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19737 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19738 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19740 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19741 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19742 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19743 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19745 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20104 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20123 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20124 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20125 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20127 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20128 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20129 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20130 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20131 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20132 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20133 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20134 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20135 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20136 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20137 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20138 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20140 /* The implementation of the FIX instruction is broken on some
20141 assemblers, in that it accepts a precision specifier as well as a
20142 rounding specifier, despite the fact that this is meaningless.
20143 To be more compatible, we accept it as well, though of course it
20144 does not set any bits. */
20145 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20146 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20147 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20148 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20149 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20150 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20151 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20152 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20153 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20154 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20155 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20156 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20157 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20159 /* Instructions that were new with the real FPA, call them V2. */
20161 #define ARM_VARIANT & fpu_fpa_ext_v2
20163 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20164 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20165 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20166 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20167 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20168 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20171 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20173 /* Moves and type conversions. */
20174 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20175 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20176 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20177 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20178 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20179 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20180 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20181 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20182 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20183 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20184 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20185 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20186 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20187 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20189 /* Memory operations. */
20190 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20191 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20192 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20193 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20194 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20195 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20196 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20197 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20198 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20199 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20200 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20201 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20202 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20203 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20204 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20205 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20206 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20207 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20209 /* Monadic operations. */
20210 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20211 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20212 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20214 /* Dyadic operations. */
20215 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20216 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20217 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20218 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20219 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20220 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20221 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20222 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20223 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20226 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20227 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20228 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20229 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20231 /* Double precision load/store are still present on single precision
20232 implementations. */
20233 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20234 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20235 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20236 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20237 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20238 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20239 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20240 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20241 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20242 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20245 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20247 /* Moves and type conversions. */
20248 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20249 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20250 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20251 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20252 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20253 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20254 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20255 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20256 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20257 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20258 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20259 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20260 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20262 /* Monadic operations. */
20263 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20264 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20265 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20267 /* Dyadic operations. */
20268 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20269 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20270 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20271 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20272 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20273 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20274 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20275 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20276 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20279 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20280 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20281 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20282 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20285 #define ARM_VARIANT & fpu_vfp_ext_v2
20287 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20288 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20289 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20290 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20292 /* Instructions which may belong to either the Neon or VFP instruction sets.
20293 Individual encoder functions perform additional architecture checks. */
20295 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20296 #undef THUMB_VARIANT
20297 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20299 /* These mnemonics are unique to VFP. */
20300 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20301 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20302 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20303 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20304 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20305 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20306 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20307 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20308 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20309 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20311 /* Mnemonics shared by Neon and VFP. */
20312 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20313 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20314 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20316 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20317 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20319 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20320 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20322 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20323 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20324 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20325 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20326 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20327 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20328 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20329 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20331 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20332 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20333 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20334 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20337 /* NOTE: All VMOV encoding is special-cased! */
20338 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20339 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20342 #define ARM_VARIANT & arm_ext_fp16
20343 #undef THUMB_VARIANT
20344 #define THUMB_VARIANT & arm_ext_fp16
20345 /* New instructions added from v8.2, allowing the extraction and insertion of
20346 the upper 16 bits of a 32-bit vector register. */
20347 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20348 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20350 #undef THUMB_VARIANT
20351 #define THUMB_VARIANT & fpu_neon_ext_v1
20353 #define ARM_VARIANT & fpu_neon_ext_v1
20355 /* Data processing with three registers of the same length. */
20356 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20357 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20358 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20359 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20360 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20361 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20362 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20363 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20364 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20365 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20366 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20367 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20368 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20369 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20370 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20371 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20372 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20373 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20374 /* If not immediate, fall back to neon_dyadic_i64_su.
20375 shl_imm should accept I8 I16 I32 I64,
20376 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20377 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20378 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20379 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20380 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20381 /* Logic ops, types optional & ignored. */
20382 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20383 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20384 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20385 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20386 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20387 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20388 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20389 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20390 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20391 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20392 /* Bitfield ops, untyped. */
20393 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20394 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20395 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20396 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20397 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20398 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20399 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20400 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20401 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20402 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20403 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20404 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20405 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20406 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20407 back to neon_dyadic_if_su. */
20408 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20409 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20410 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20411 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20412 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20413 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20414 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20415 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20416 /* Comparison. Type I8 I16 I32 F32. */
20417 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20418 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20419 /* As above, D registers only. */
20420 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20421 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20422 /* Int and float variants, signedness unimportant. */
20423 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20424 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20425 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20426 /* Add/sub take types I8 I16 I32 I64 F32. */
20427 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20428 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20429 /* vtst takes sizes 8, 16, 32. */
20430 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20431 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20432 /* VMUL takes I8 I16 I32 F32 P8. */
20433 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20434 /* VQD{R}MULH takes S16 S32. */
20435 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20436 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20437 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20438 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20439 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20440 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20441 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20442 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20443 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20444 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20445 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20446 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20447 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20448 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20449 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20450 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20451 /* ARM v8.1 extension. */
20452 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20453 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20454 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20455 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20457 /* Two address, int/float. Types S8 S16 S32 F32. */
20458 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20459 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20461 /* Data processing with two registers and a shift amount. */
20462 /* Right shifts, and variants with rounding.
20463 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20464 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20465 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20466 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20467 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20468 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20469 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20470 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20471 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20472 /* Shift and insert. Sizes accepted 8 16 32 64. */
20473 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20474 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20475 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20476 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20477 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20478 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20479 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20480 /* Right shift immediate, saturating & narrowing, with rounding variants.
20481 Types accepted S16 S32 S64 U16 U32 U64. */
20482 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20483 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20484 /* As above, unsigned. Types accepted S16 S32 S64. */
20485 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20486 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20487 /* Right shift narrowing. Types accepted I16 I32 I64. */
20488 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20489 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20490 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20491 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20492 /* CVT with optional immediate for fixed-point variant. */
20493 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20495 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20496 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20498 /* Data processing, three registers of different lengths. */
20499 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20500 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20501 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20502 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20503 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20504 /* If not scalar, fall back to neon_dyadic_long.
20505 Vector types as above, scalar types S16 S32 U16 U32. */
20506 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20507 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20508 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20509 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20510 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20511 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20512 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20513 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20514 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20515 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20516 /* Saturating doubling multiplies. Types S16 S32. */
20517 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20518 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20519 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20520 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20521 S16 S32 U16 U32. */
20522 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20524 /* Extract. Size 8. */
20525 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20526 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20528 /* Two registers, miscellaneous. */
20529 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20530 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20531 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20532 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20533 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20534 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20535 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20536 /* Vector replicate. Sizes 8 16 32. */
20537 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20538 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20539 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20540 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20541 /* VMOVN. Types I16 I32 I64. */
20542 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20543 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20544 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20545 /* VQMOVUN. Types S16 S32 S64. */
20546 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20547 /* VZIP / VUZP. Sizes 8 16 32. */
20548 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20549 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20550 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20551 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20552 /* VQABS / VQNEG. Types S8 S16 S32. */
20553 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20554 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20555 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20556 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20557 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20558 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20559 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20560 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20561 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20562 /* Reciprocal estimates. Types U32 F16 F32. */
20563 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20564 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20565 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20566 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20567 /* VCLS. Types S8 S16 S32. */
20568 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20569 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20570 /* VCLZ. Types I8 I16 I32. */
20571 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20572 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20573 /* VCNT. Size 8. */
20574 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20575 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20576 /* Two address, untyped. */
20577 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20578 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20579 /* VTRN. Sizes 8 16 32. */
20580 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20581 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20583 /* Table lookup. Size 8. */
20584 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20585 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20587 #undef THUMB_VARIANT
20588 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20590 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20592 /* Neon element/structure load/store. */
20593 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20594 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20595 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20596 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20597 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20598 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20599 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20600 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20602 #undef THUMB_VARIANT
20603 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20605 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20606 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20607 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20608 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20609 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20610 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20611 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20612 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20613 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20614 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20616 #undef THUMB_VARIANT
20617 #define THUMB_VARIANT & fpu_vfp_ext_v3
20619 #define ARM_VARIANT & fpu_vfp_ext_v3
20621 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20622 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20623 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20624 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20625 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20626 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20627 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20628 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20629 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20632 #define ARM_VARIANT & fpu_vfp_ext_fma
20633 #undef THUMB_VARIANT
20634 #define THUMB_VARIANT & fpu_vfp_ext_fma
20635 /* Mnemonics shared by Neon and VFP. These are included in the
20636 VFP FMA variant; NEON and VFP FMA always includes the NEON
20637 FMA instructions. */
20638 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20639 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20640 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20641 the v form should always be used. */
20642 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20643 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20644 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20645 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20646 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20647 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20649 #undef THUMB_VARIANT
20651 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20653 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20654 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20655 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20656 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20657 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20658 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20659 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20660 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20663 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20665 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20666 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20667 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20668 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20669 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20670 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20671 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20672 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20673 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20674 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20675 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20676 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20677 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20678 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20679 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20680 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20681 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20682 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20683 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20684 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20685 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20686 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20687 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20688 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20689 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20690 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20691 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20692 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20693 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20694 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20695 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20696 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20697 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20698 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20699 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20700 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20701 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20702 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20703 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20704 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20708 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20710 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20711 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20712 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20713 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20714 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20728 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20729 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20730 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20731 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20732 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20733 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20734 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20735 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20736 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20738 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20748 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20749 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20750 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20754 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20760 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20765 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20766 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20767 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20768 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20769 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20770 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20771 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20776 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20777 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20778 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20779 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20780 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20781 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20782 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20783 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20784 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20785 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20786 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20787 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20788 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20789 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20790 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20791 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20792 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20793 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20794 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20795 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20796 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20797 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20798 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20799 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20800 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20802 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20804 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20808 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20809 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20810 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20811 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20812 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20813 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20814 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20815 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20816 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20817 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20818 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20819 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20820 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20821 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20822 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20824 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20825 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20826 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20829 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20831 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20832 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20833 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20834 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20835 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20836 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20837 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20852 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20858 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20860 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20870 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20892 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20893 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20894 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20895 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20896 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20897 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20898 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20899 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20900 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20901 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20902 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20903 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20904 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20905 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20906 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20907 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20908 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20909 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20910 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20911 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20912 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20913 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20914 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20915 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20916 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20917 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20918 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20919 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20920 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20921 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20922 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20923 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20924 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20925 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20926 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20927 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20928 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20929 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20930 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20931 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20932 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20933 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20934 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20935 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20936 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20937 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20938 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20939 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20940 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20941 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20942 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20943 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20944 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20945 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20946 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20947 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20948 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20949 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20950 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20951 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20952 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20953 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20954 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20955 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20956 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20957 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20958 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20959 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20960 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20961 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20962 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20963 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20964 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20965 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20966 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20967 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20969 /* ARMv8-M instructions. */
20971 #define ARM_VARIANT NULL
20972 #undef THUMB_VARIANT
20973 #define THUMB_VARIANT & arm_ext_v8m
20974 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
20975 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
20976 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
20977 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20978 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20979 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
20980 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
20982 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
20983 instructions behave as nop if no VFP is present. */
20984 #undef THUMB_VARIANT
20985 #define THUMB_VARIANT & arm_ext_v8m_main
20986 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
20987 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
20990 #undef THUMB_VARIANT
21016 /* MD interface: bits in the object file. */
21018 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21019 for use in the a.out file, and stores them in the array pointed to by buf.
21020 This knows about the endian-ness of the target machine and does
21021 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21022 2 (short) and 4 (long) Floating numbers are put out as a series of
21023 LITTLENUMS (shorts, here at least). */
21026 md_number_to_chars (char * buf
, valueT val
, int n
)
21028 if (target_big_endian
)
21029 number_to_chars_bigendian (buf
, val
, n
);
21031 number_to_chars_littleendian (buf
, val
, n
);
21035 md_chars_to_number (char * buf
, int n
)
21038 unsigned char * where
= (unsigned char *) buf
;
21040 if (target_big_endian
)
21045 result
|= (*where
++ & 255);
21053 result
|= (where
[n
] & 255);
21060 /* MD interface: Sections. */
21062 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21063 that an rs_machine_dependent frag may reach. */
21066 arm_frag_max_var (fragS
*fragp
)
21068 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21069 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21071 Note that we generate relaxable instructions even for cases that don't
21072 really need it, like an immediate that's a trivial constant. So we're
21073 overestimating the instruction size for some of those cases. Rather
21074 than putting more intelligence here, it would probably be better to
21075 avoid generating a relaxation frag in the first place when it can be
21076 determined up front that a short instruction will suffice. */
21078 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21082 /* Estimate the size of a frag before relaxing. Assume everything fits in
21086 md_estimate_size_before_relax (fragS
* fragp
,
21087 segT segtype ATTRIBUTE_UNUSED
)
21093 /* Convert a machine dependent frag. */
21096 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21098 unsigned long insn
;
21099 unsigned long old_op
;
21107 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21109 old_op
= bfd_get_16(abfd
, buf
);
21110 if (fragp
->fr_symbol
)
21112 exp
.X_op
= O_symbol
;
21113 exp
.X_add_symbol
= fragp
->fr_symbol
;
21117 exp
.X_op
= O_constant
;
21119 exp
.X_add_number
= fragp
->fr_offset
;
21120 opcode
= fragp
->fr_subtype
;
21123 case T_MNEM_ldr_pc
:
21124 case T_MNEM_ldr_pc2
:
21125 case T_MNEM_ldr_sp
:
21126 case T_MNEM_str_sp
:
21133 if (fragp
->fr_var
== 4)
21135 insn
= THUMB_OP32 (opcode
);
21136 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21138 insn
|= (old_op
& 0x700) << 4;
21142 insn
|= (old_op
& 7) << 12;
21143 insn
|= (old_op
& 0x38) << 13;
21145 insn
|= 0x00000c00;
21146 put_thumb32_insn (buf
, insn
);
21147 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21151 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21153 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21156 if (fragp
->fr_var
== 4)
21158 insn
= THUMB_OP32 (opcode
);
21159 insn
|= (old_op
& 0xf0) << 4;
21160 put_thumb32_insn (buf
, insn
);
21161 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21165 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21166 exp
.X_add_number
-= 4;
21174 if (fragp
->fr_var
== 4)
21176 int r0off
= (opcode
== T_MNEM_mov
21177 || opcode
== T_MNEM_movs
) ? 0 : 8;
21178 insn
= THUMB_OP32 (opcode
);
21179 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21180 insn
|= (old_op
& 0x700) << r0off
;
21181 put_thumb32_insn (buf
, insn
);
21182 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21186 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21191 if (fragp
->fr_var
== 4)
21193 insn
= THUMB_OP32(opcode
);
21194 put_thumb32_insn (buf
, insn
);
21195 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21198 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21202 if (fragp
->fr_var
== 4)
21204 insn
= THUMB_OP32(opcode
);
21205 insn
|= (old_op
& 0xf00) << 14;
21206 put_thumb32_insn (buf
, insn
);
21207 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21210 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21213 case T_MNEM_add_sp
:
21214 case T_MNEM_add_pc
:
21215 case T_MNEM_inc_sp
:
21216 case T_MNEM_dec_sp
:
21217 if (fragp
->fr_var
== 4)
21219 /* ??? Choose between add and addw. */
21220 insn
= THUMB_OP32 (opcode
);
21221 insn
|= (old_op
& 0xf0) << 4;
21222 put_thumb32_insn (buf
, insn
);
21223 if (opcode
== T_MNEM_add_pc
)
21224 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21226 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21229 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21237 if (fragp
->fr_var
== 4)
21239 insn
= THUMB_OP32 (opcode
);
21240 insn
|= (old_op
& 0xf0) << 4;
21241 insn
|= (old_op
& 0xf) << 16;
21242 put_thumb32_insn (buf
, insn
);
21243 if (insn
& (1 << 20))
21244 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21246 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21249 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21255 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21256 (enum bfd_reloc_code_real
) reloc_type
);
21257 fixp
->fx_file
= fragp
->fr_file
;
21258 fixp
->fx_line
= fragp
->fr_line
;
21259 fragp
->fr_fix
+= fragp
->fr_var
;
21261 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21262 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21263 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21264 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21267 /* Return the size of a relaxable immediate operand instruction.
21268 SHIFT and SIZE specify the form of the allowable immediate. */
21270 relax_immediate (fragS
*fragp
, int size
, int shift
)
21276 /* ??? Should be able to do better than this. */
21277 if (fragp
->fr_symbol
)
21280 low
= (1 << shift
) - 1;
21281 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21282 offset
= fragp
->fr_offset
;
21283 /* Force misaligned offsets to 32-bit variant. */
21286 if (offset
& ~mask
)
21291 /* Get the address of a symbol during relaxation. */
21293 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21299 sym
= fragp
->fr_symbol
;
21300 sym_frag
= symbol_get_frag (sym
);
21301 know (S_GET_SEGMENT (sym
) != absolute_section
21302 || sym_frag
== &zero_address_frag
);
21303 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21305 /* If frag has yet to be reached on this pass, assume it will
21306 move by STRETCH just as we did. If this is not so, it will
21307 be because some frag between grows, and that will force
21311 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21315 /* Adjust stretch for any alignment frag. Note that if have
21316 been expanding the earlier code, the symbol may be
21317 defined in what appears to be an earlier frag. FIXME:
21318 This doesn't handle the fr_subtype field, which specifies
21319 a maximum number of bytes to skip when doing an
21321 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21323 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21326 stretch
= - ((- stretch
)
21327 & ~ ((1 << (int) f
->fr_offset
) - 1));
21329 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21341 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21344 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21349 /* Assume worst case for symbols not known to be in the same section. */
21350 if (fragp
->fr_symbol
== NULL
21351 || !S_IS_DEFINED (fragp
->fr_symbol
)
21352 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21353 || S_IS_WEAK (fragp
->fr_symbol
))
21356 val
= relaxed_symbol_addr (fragp
, stretch
);
21357 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21358 addr
= (addr
+ 4) & ~3;
21359 /* Force misaligned targets to 32-bit variant. */
21363 if (val
< 0 || val
> 1020)
21368 /* Return the size of a relaxable add/sub immediate instruction. */
21370 relax_addsub (fragS
*fragp
, asection
*sec
)
21375 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21376 op
= bfd_get_16(sec
->owner
, buf
);
21377 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21378 return relax_immediate (fragp
, 8, 0);
21380 return relax_immediate (fragp
, 3, 0);
21383 /* Return TRUE iff the definition of symbol S could be pre-empted
21384 (overridden) at link or load time. */
21386 symbol_preemptible (symbolS
*s
)
21388 /* Weak symbols can always be pre-empted. */
21392 /* Non-global symbols cannot be pre-empted. */
21393 if (! S_IS_EXTERNAL (s
))
21397 /* In ELF, a global symbol can be marked protected, or private. In that
21398 case it can't be pre-empted (other definitions in the same link unit
21399 would violate the ODR). */
21400 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21404 /* Other global symbols might be pre-empted. */
21408 /* Return the size of a relaxable branch instruction. BITS is the
21409 size of the offset field in the narrow instruction. */
21412 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21418 /* Assume worst case for symbols not known to be in the same section. */
21419 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21420 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21421 || S_IS_WEAK (fragp
->fr_symbol
))
21425 /* A branch to a function in ARM state will require interworking. */
21426 if (S_IS_DEFINED (fragp
->fr_symbol
)
21427 && ARM_IS_FUNC (fragp
->fr_symbol
))
21431 if (symbol_preemptible (fragp
->fr_symbol
))
21434 val
= relaxed_symbol_addr (fragp
, stretch
);
21435 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21438 /* Offset is a signed value *2 */
21440 if (val
>= limit
|| val
< -limit
)
21446 /* Relax a machine dependent frag. This returns the amount by which
21447 the current size of the frag should change. */
21450 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21455 oldsize
= fragp
->fr_var
;
21456 switch (fragp
->fr_subtype
)
21458 case T_MNEM_ldr_pc2
:
21459 newsize
= relax_adr (fragp
, sec
, stretch
);
21461 case T_MNEM_ldr_pc
:
21462 case T_MNEM_ldr_sp
:
21463 case T_MNEM_str_sp
:
21464 newsize
= relax_immediate (fragp
, 8, 2);
21468 newsize
= relax_immediate (fragp
, 5, 2);
21472 newsize
= relax_immediate (fragp
, 5, 1);
21476 newsize
= relax_immediate (fragp
, 5, 0);
21479 newsize
= relax_adr (fragp
, sec
, stretch
);
21485 newsize
= relax_immediate (fragp
, 8, 0);
21488 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21491 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21493 case T_MNEM_add_sp
:
21494 case T_MNEM_add_pc
:
21495 newsize
= relax_immediate (fragp
, 8, 2);
21497 case T_MNEM_inc_sp
:
21498 case T_MNEM_dec_sp
:
21499 newsize
= relax_immediate (fragp
, 7, 2);
21505 newsize
= relax_addsub (fragp
, sec
);
21511 fragp
->fr_var
= newsize
;
21512 /* Freeze wide instructions that are at or before the same location as
21513 in the previous pass. This avoids infinite loops.
21514 Don't freeze them unconditionally because targets may be artificially
21515 misaligned by the expansion of preceding frags. */
21516 if (stretch
<= 0 && newsize
> 2)
21518 md_convert_frag (sec
->owner
, sec
, fragp
);
21522 return newsize
- oldsize
;
21525 /* Round up a section size to the appropriate boundary. */
21528 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21531 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21532 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21534 /* For a.out, force the section size to be aligned. If we don't do
21535 this, BFD will align it for us, but it will not write out the
21536 final bytes of the section. This may be a bug in BFD, but it is
21537 easier to fix it here since that is how the other a.out targets
21541 align
= bfd_get_section_alignment (stdoutput
, segment
);
21542 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21549 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21550 of an rs_align_code fragment. */
21553 arm_handle_align (fragS
* fragP
)
21555 static unsigned char const arm_noop
[2][2][4] =
21558 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21559 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21562 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21563 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21566 static unsigned char const thumb_noop
[2][2][2] =
21569 {0xc0, 0x46}, /* LE */
21570 {0x46, 0xc0}, /* BE */
21573 {0x00, 0xbf}, /* LE */
21574 {0xbf, 0x00} /* BE */
21577 static unsigned char const wide_thumb_noop
[2][4] =
21578 { /* Wide Thumb-2 */
21579 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21580 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21583 unsigned bytes
, fix
, noop_size
;
21585 const unsigned char * noop
;
21586 const unsigned char *narrow_noop
= NULL
;
21591 if (fragP
->fr_type
!= rs_align_code
)
21594 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21595 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21598 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21599 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21601 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21603 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21605 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21606 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21608 narrow_noop
= thumb_noop
[1][target_big_endian
];
21609 noop
= wide_thumb_noop
[target_big_endian
];
21612 noop
= thumb_noop
[0][target_big_endian
];
21620 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21621 ? selected_cpu
: arm_arch_none
,
21623 [target_big_endian
];
21630 fragP
->fr_var
= noop_size
;
21632 if (bytes
& (noop_size
- 1))
21634 fix
= bytes
& (noop_size
- 1);
21636 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21638 memset (p
, 0, fix
);
21645 if (bytes
& noop_size
)
21647 /* Insert a narrow noop. */
21648 memcpy (p
, narrow_noop
, noop_size
);
21650 bytes
-= noop_size
;
21654 /* Use wide noops for the remainder */
21658 while (bytes
>= noop_size
)
21660 memcpy (p
, noop
, noop_size
);
21662 bytes
-= noop_size
;
21666 fragP
->fr_fix
+= fix
;
21669 /* Called from md_do_align. Used to create an alignment
21670 frag in a code section. */
21673 arm_frag_align_code (int n
, int max
)
21677 /* We assume that there will never be a requirement
21678 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21679 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21684 _("alignments greater than %d bytes not supported in .text sections."),
21685 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21686 as_fatal ("%s", err_msg
);
21689 p
= frag_var (rs_align_code
,
21690 MAX_MEM_FOR_RS_ALIGN_CODE
,
21692 (relax_substateT
) max
,
21699 /* Perform target specific initialisation of a frag.
21700 Note - despite the name this initialisation is not done when the frag
21701 is created, but only when its type is assigned. A frag can be created
21702 and used a long time before its type is set, so beware of assuming that
21703 this initialisationis performed first. */
21707 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21709 /* Record whether this frag is in an ARM or a THUMB area. */
21710 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21713 #else /* OBJ_ELF is defined. */
21715 arm_init_frag (fragS
* fragP
, int max_chars
)
21717 int frag_thumb_mode
;
21719 /* If the current ARM vs THUMB mode has not already
21720 been recorded into this frag then do so now. */
21721 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21722 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21724 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21726 /* Record a mapping symbol for alignment frags. We will delete this
21727 later if the alignment ends up empty. */
21728 switch (fragP
->fr_type
)
21731 case rs_align_test
:
21733 mapping_state_2 (MAP_DATA
, max_chars
);
21735 case rs_align_code
:
21736 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21743 /* When we change sections we need to issue a new mapping symbol. */
21746 arm_elf_change_section (void)
21748 /* Link an unlinked unwind index table section to the .text section. */
21749 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21750 && elf_linked_to_section (now_seg
) == NULL
)
21751 elf_linked_to_section (now_seg
) = text_section
;
21755 arm_elf_section_type (const char * str
, size_t len
)
21757 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21758 return SHT_ARM_EXIDX
;
21763 /* Code to deal with unwinding tables. */
21765 static void add_unwind_adjustsp (offsetT
);
21767 /* Generate any deferred unwind frame offset. */
21770 flush_pending_unwind (void)
21774 offset
= unwind
.pending_offset
;
21775 unwind
.pending_offset
= 0;
21777 add_unwind_adjustsp (offset
);
21780 /* Add an opcode to this list for this function. Two-byte opcodes should
21781 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21785 add_unwind_opcode (valueT op
, int length
)
21787 /* Add any deferred stack adjustment. */
21788 if (unwind
.pending_offset
)
21789 flush_pending_unwind ();
21791 unwind
.sp_restored
= 0;
21793 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21795 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21796 if (unwind
.opcodes
)
21797 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21798 unwind
.opcode_alloc
);
21800 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21805 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21807 unwind
.opcode_count
++;
21811 /* Add unwind opcodes to adjust the stack pointer. */
21814 add_unwind_adjustsp (offsetT offset
)
21818 if (offset
> 0x200)
21820 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21825 /* Long form: 0xb2, uleb128. */
21826 /* This might not fit in a word so add the individual bytes,
21827 remembering the list is built in reverse order. */
21828 o
= (valueT
) ((offset
- 0x204) >> 2);
21830 add_unwind_opcode (0, 1);
21832 /* Calculate the uleb128 encoding of the offset. */
21836 bytes
[n
] = o
& 0x7f;
21842 /* Add the insn. */
21844 add_unwind_opcode (bytes
[n
- 1], 1);
21845 add_unwind_opcode (0xb2, 1);
21847 else if (offset
> 0x100)
21849 /* Two short opcodes. */
21850 add_unwind_opcode (0x3f, 1);
21851 op
= (offset
- 0x104) >> 2;
21852 add_unwind_opcode (op
, 1);
21854 else if (offset
> 0)
21856 /* Short opcode. */
21857 op
= (offset
- 4) >> 2;
21858 add_unwind_opcode (op
, 1);
21860 else if (offset
< 0)
21863 while (offset
> 0x100)
21865 add_unwind_opcode (0x7f, 1);
21868 op
= ((offset
- 4) >> 2) | 0x40;
21869 add_unwind_opcode (op
, 1);
21873 /* Finish the list of unwind opcodes for this function. */
21875 finish_unwind_opcodes (void)
21879 if (unwind
.fp_used
)
21881 /* Adjust sp as necessary. */
21882 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21883 flush_pending_unwind ();
21885 /* After restoring sp from the frame pointer. */
21886 op
= 0x90 | unwind
.fp_reg
;
21887 add_unwind_opcode (op
, 1);
21890 flush_pending_unwind ();
21894 /* Start an exception table entry. If idx is nonzero this is an index table
21898 start_unwind_section (const segT text_seg
, int idx
)
21900 const char * text_name
;
21901 const char * prefix
;
21902 const char * prefix_once
;
21903 const char * group_name
;
21907 size_t sec_name_len
;
21914 prefix
= ELF_STRING_ARM_unwind
;
21915 prefix_once
= ELF_STRING_ARM_unwind_once
;
21916 type
= SHT_ARM_EXIDX
;
21920 prefix
= ELF_STRING_ARM_unwind_info
;
21921 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21922 type
= SHT_PROGBITS
;
21925 text_name
= segment_name (text_seg
);
21926 if (streq (text_name
, ".text"))
21929 if (strncmp (text_name
, ".gnu.linkonce.t.",
21930 strlen (".gnu.linkonce.t.")) == 0)
21932 prefix
= prefix_once
;
21933 text_name
+= strlen (".gnu.linkonce.t.");
21936 prefix_len
= strlen (prefix
);
21937 text_len
= strlen (text_name
);
21938 sec_name_len
= prefix_len
+ text_len
;
21939 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21940 memcpy (sec_name
, prefix
, prefix_len
);
21941 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21942 sec_name
[prefix_len
+ text_len
] = '\0';
21948 /* Handle COMDAT group. */
21949 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21951 group_name
= elf_group_name (text_seg
);
21952 if (group_name
== NULL
)
21954 as_bad (_("Group section `%s' has no group signature"),
21955 segment_name (text_seg
));
21956 ignore_rest_of_line ();
21959 flags
|= SHF_GROUP
;
21963 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21965 /* Set the section link for index tables. */
21967 elf_linked_to_section (now_seg
) = text_seg
;
21971 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21972 personality routine data. Returns zero, or the index table value for
21973 an inline entry. */
21976 create_unwind_entry (int have_data
)
21981 /* The current word of data. */
21983 /* The number of bytes left in this word. */
21986 finish_unwind_opcodes ();
21988 /* Remember the current text section. */
21989 unwind
.saved_seg
= now_seg
;
21990 unwind
.saved_subseg
= now_subseg
;
21992 start_unwind_section (now_seg
, 0);
21994 if (unwind
.personality_routine
== NULL
)
21996 if (unwind
.personality_index
== -2)
21999 as_bad (_("handlerdata in cantunwind frame"));
22000 return 1; /* EXIDX_CANTUNWIND. */
22003 /* Use a default personality routine if none is specified. */
22004 if (unwind
.personality_index
== -1)
22006 if (unwind
.opcode_count
> 3)
22007 unwind
.personality_index
= 1;
22009 unwind
.personality_index
= 0;
22012 /* Space for the personality routine entry. */
22013 if (unwind
.personality_index
== 0)
22015 if (unwind
.opcode_count
> 3)
22016 as_bad (_("too many unwind opcodes for personality routine 0"));
22020 /* All the data is inline in the index table. */
22023 while (unwind
.opcode_count
> 0)
22025 unwind
.opcode_count
--;
22026 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22030 /* Pad with "finish" opcodes. */
22032 data
= (data
<< 8) | 0xb0;
22039 /* We get two opcodes "free" in the first word. */
22040 size
= unwind
.opcode_count
- 2;
22044 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22045 if (unwind
.personality_index
!= -1)
22047 as_bad (_("attempt to recreate an unwind entry"));
22051 /* An extra byte is required for the opcode count. */
22052 size
= unwind
.opcode_count
+ 1;
22055 size
= (size
+ 3) >> 2;
22057 as_bad (_("too many unwind opcodes"));
22059 frag_align (2, 0, 0);
22060 record_alignment (now_seg
, 2);
22061 unwind
.table_entry
= expr_build_dot ();
22063 /* Allocate the table entry. */
22064 ptr
= frag_more ((size
<< 2) + 4);
22065 /* PR 13449: Zero the table entries in case some of them are not used. */
22066 memset (ptr
, 0, (size
<< 2) + 4);
22067 where
= frag_now_fix () - ((size
<< 2) + 4);
22069 switch (unwind
.personality_index
)
22072 /* ??? Should this be a PLT generating relocation? */
22073 /* Custom personality routine. */
22074 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22075 BFD_RELOC_ARM_PREL31
);
22080 /* Set the first byte to the number of additional words. */
22081 data
= size
> 0 ? size
- 1 : 0;
22085 /* ABI defined personality routines. */
22087 /* Three opcodes bytes are packed into the first word. */
22094 /* The size and first two opcode bytes go in the first word. */
22095 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22100 /* Should never happen. */
22104 /* Pack the opcodes into words (MSB first), reversing the list at the same
22106 while (unwind
.opcode_count
> 0)
22110 md_number_to_chars (ptr
, data
, 4);
22115 unwind
.opcode_count
--;
22117 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22120 /* Finish off the last word. */
22123 /* Pad with "finish" opcodes. */
22125 data
= (data
<< 8) | 0xb0;
22127 md_number_to_chars (ptr
, data
, 4);
22132 /* Add an empty descriptor if there is no user-specified data. */
22133 ptr
= frag_more (4);
22134 md_number_to_chars (ptr
, 0, 4);
22141 /* Initialize the DWARF-2 unwind information for this procedure. */
22144 tc_arm_frame_initial_instructions (void)
22146 cfi_add_CFA_def_cfa (REG_SP
, 0);
22148 #endif /* OBJ_ELF */
22150 /* Convert REGNAME to a DWARF-2 register number. */
22153 tc_arm_regname_to_dw2regnum (char *regname
)
22155 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22159 /* PR 16694: Allow VFP registers as well. */
22160 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22164 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22173 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22177 exp
.X_op
= O_secrel
;
22178 exp
.X_add_symbol
= symbol
;
22179 exp
.X_add_number
= 0;
22180 emit_expr (&exp
, size
);
22184 /* MD interface: Symbol and relocation handling. */
22186 /* Return the address within the segment that a PC-relative fixup is
22187 relative to. For ARM, PC-relative fixups applied to instructions
22188 are generally relative to the location of the fixup plus 8 bytes.
22189 Thumb branches are offset by 4, and Thumb loads relative to PC
22190 require special handling. */
22193 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22195 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22197 /* If this is pc-relative and we are going to emit a relocation
22198 then we just want to put out any pipeline compensation that the linker
22199 will need. Otherwise we want to use the calculated base.
22200 For WinCE we skip the bias for externals as well, since this
22201 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22203 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22204 || (arm_force_relocation (fixP
)
22206 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22212 switch (fixP
->fx_r_type
)
22214 /* PC relative addressing on the Thumb is slightly odd as the
22215 bottom two bits of the PC are forced to zero for the
22216 calculation. This happens *after* application of the
22217 pipeline offset. However, Thumb adrl already adjusts for
22218 this, so we need not do it again. */
22219 case BFD_RELOC_ARM_THUMB_ADD
:
22222 case BFD_RELOC_ARM_THUMB_OFFSET
:
22223 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22224 case BFD_RELOC_ARM_T32_ADD_PC12
:
22225 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22226 return (base
+ 4) & ~3;
22228 /* Thumb branches are simply offset by +4. */
22229 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22230 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22231 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22232 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22233 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22236 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22238 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22239 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22240 && ARM_IS_FUNC (fixP
->fx_addsy
)
22241 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22242 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22245 /* BLX is like branches above, but forces the low two bits of PC to
22247 case BFD_RELOC_THUMB_PCREL_BLX
:
22249 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22250 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22251 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22252 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22253 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22254 return (base
+ 4) & ~3;
22256 /* ARM mode branches are offset by +8. However, the Windows CE
22257 loader expects the relocation not to take this into account. */
22258 case BFD_RELOC_ARM_PCREL_BLX
:
22260 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22261 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22262 && ARM_IS_FUNC (fixP
->fx_addsy
)
22263 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22264 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22267 case BFD_RELOC_ARM_PCREL_CALL
:
22269 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22270 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22271 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22272 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22273 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22276 case BFD_RELOC_ARM_PCREL_BRANCH
:
22277 case BFD_RELOC_ARM_PCREL_JUMP
:
22278 case BFD_RELOC_ARM_PLT32
:
22280 /* When handling fixups immediately, because we have already
22281 discovered the value of a symbol, or the address of the frag involved
22282 we must account for the offset by +8, as the OS loader will never see the reloc.
22283 see fixup_segment() in write.c
22284 The S_IS_EXTERNAL test handles the case of global symbols.
22285 Those need the calculated base, not just the pipe compensation the linker will need. */
22287 && fixP
->fx_addsy
!= NULL
22288 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22289 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22297 /* ARM mode loads relative to PC are also offset by +8. Unlike
22298 branches, the Windows CE loader *does* expect the relocation
22299 to take this into account. */
22300 case BFD_RELOC_ARM_OFFSET_IMM
:
22301 case BFD_RELOC_ARM_OFFSET_IMM8
:
22302 case BFD_RELOC_ARM_HWLITERAL
:
22303 case BFD_RELOC_ARM_LITERAL
:
22304 case BFD_RELOC_ARM_CP_OFF_IMM
:
22308 /* Other PC-relative relocations are un-offset. */
22314 static bfd_boolean flag_warn_syms
= TRUE
;
22317 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22319 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22320 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22321 does mean that the resulting code might be very confusing to the reader.
22322 Also this warning can be triggered if the user omits an operand before
22323 an immediate address, eg:
22327 GAS treats this as an assignment of the value of the symbol foo to a
22328 symbol LDR, and so (without this code) it will not issue any kind of
22329 warning or error message.
22331 Note - ARM instructions are case-insensitive but the strings in the hash
22332 table are all stored in lower case, so we must first ensure that name is
22334 if (flag_warn_syms
&& arm_ops_hsh
)
22336 char * nbuf
= strdup (name
);
22339 for (p
= nbuf
; *p
; p
++)
22341 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22343 static struct hash_control
* already_warned
= NULL
;
22345 if (already_warned
== NULL
)
22346 already_warned
= hash_new ();
22347 /* Only warn about the symbol once. To keep the code
22348 simple we let hash_insert do the lookup for us. */
22349 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22350 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22359 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22360 Otherwise we have no need to default values of symbols. */
22363 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22366 if (name
[0] == '_' && name
[1] == 'G'
22367 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22371 if (symbol_find (name
))
22372 as_bad (_("GOT already in the symbol table"));
22374 GOT_symbol
= symbol_new (name
, undefined_section
,
22375 (valueT
) 0, & zero_address_frag
);
22385 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22386 computed as two separate immediate values, added together. We
22387 already know that this value cannot be computed by just one ARM
22390 static unsigned int
22391 validate_immediate_twopart (unsigned int val
,
22392 unsigned int * highpart
)
22397 for (i
= 0; i
< 32; i
+= 2)
22398 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22404 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22406 else if (a
& 0xff0000)
22408 if (a
& 0xff000000)
22410 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22414 gas_assert (a
& 0xff000000);
22415 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22418 return (a
& 0xff) | (i
<< 7);
22425 validate_offset_imm (unsigned int val
, int hwse
)
22427 if ((hwse
&& val
> 255) || val
> 4095)
22432 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22433 negative immediate constant by altering the instruction. A bit of
22438 by inverting the second operand, and
22441 by negating the second operand. */
22444 negate_data_op (unsigned long * instruction
,
22445 unsigned long value
)
22448 unsigned long negated
, inverted
;
22450 negated
= encode_arm_immediate (-value
);
22451 inverted
= encode_arm_immediate (~value
);
22453 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22456 /* First negates. */
22457 case OPCODE_SUB
: /* ADD <-> SUB */
22458 new_inst
= OPCODE_ADD
;
22463 new_inst
= OPCODE_SUB
;
22467 case OPCODE_CMP
: /* CMP <-> CMN */
22468 new_inst
= OPCODE_CMN
;
22473 new_inst
= OPCODE_CMP
;
22477 /* Now Inverted ops. */
22478 case OPCODE_MOV
: /* MOV <-> MVN */
22479 new_inst
= OPCODE_MVN
;
22484 new_inst
= OPCODE_MOV
;
22488 case OPCODE_AND
: /* AND <-> BIC */
22489 new_inst
= OPCODE_BIC
;
22494 new_inst
= OPCODE_AND
;
22498 case OPCODE_ADC
: /* ADC <-> SBC */
22499 new_inst
= OPCODE_SBC
;
22504 new_inst
= OPCODE_ADC
;
22508 /* We cannot do anything. */
22513 if (value
== (unsigned) FAIL
)
22516 *instruction
&= OPCODE_MASK
;
22517 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22521 /* Like negate_data_op, but for Thumb-2. */
22523 static unsigned int
22524 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22528 unsigned int negated
, inverted
;
22530 negated
= encode_thumb32_immediate (-value
);
22531 inverted
= encode_thumb32_immediate (~value
);
22533 rd
= (*instruction
>> 8) & 0xf;
22534 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22537 /* ADD <-> SUB. Includes CMP <-> CMN. */
22538 case T2_OPCODE_SUB
:
22539 new_inst
= T2_OPCODE_ADD
;
22543 case T2_OPCODE_ADD
:
22544 new_inst
= T2_OPCODE_SUB
;
22548 /* ORR <-> ORN. Includes MOV <-> MVN. */
22549 case T2_OPCODE_ORR
:
22550 new_inst
= T2_OPCODE_ORN
;
22554 case T2_OPCODE_ORN
:
22555 new_inst
= T2_OPCODE_ORR
;
22559 /* AND <-> BIC. TST has no inverted equivalent. */
22560 case T2_OPCODE_AND
:
22561 new_inst
= T2_OPCODE_BIC
;
22568 case T2_OPCODE_BIC
:
22569 new_inst
= T2_OPCODE_AND
;
22574 case T2_OPCODE_ADC
:
22575 new_inst
= T2_OPCODE_SBC
;
22579 case T2_OPCODE_SBC
:
22580 new_inst
= T2_OPCODE_ADC
;
22584 /* We cannot do anything. */
22589 if (value
== (unsigned int)FAIL
)
22592 *instruction
&= T2_OPCODE_MASK
;
22593 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22597 /* Read a 32-bit thumb instruction from buf. */
22598 static unsigned long
22599 get_thumb32_insn (char * buf
)
22601 unsigned long insn
;
22602 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22603 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22609 /* We usually want to set the low bit on the address of thumb function
22610 symbols. In particular .word foo - . should have the low bit set.
22611 Generic code tries to fold the difference of two symbols to
22612 a constant. Prevent this and force a relocation when the first symbols
22613 is a thumb function. */
22616 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22618 if (op
== O_subtract
22619 && l
->X_op
== O_symbol
22620 && r
->X_op
== O_symbol
22621 && THUMB_IS_FUNC (l
->X_add_symbol
))
22623 l
->X_op
= O_subtract
;
22624 l
->X_op_symbol
= r
->X_add_symbol
;
22625 l
->X_add_number
-= r
->X_add_number
;
22629 /* Process as normal. */
22633 /* Encode Thumb2 unconditional branches and calls. The encoding
22634 for the 2 are identical for the immediate values. */
22637 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22639 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22642 addressT S
, I1
, I2
, lo
, hi
;
22644 S
= (value
>> 24) & 0x01;
22645 I1
= (value
>> 23) & 0x01;
22646 I2
= (value
>> 22) & 0x01;
22647 hi
= (value
>> 12) & 0x3ff;
22648 lo
= (value
>> 1) & 0x7ff;
22649 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22650 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22651 newval
|= (S
<< 10) | hi
;
22652 newval2
&= ~T2I1I2MASK
;
22653 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22654 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22655 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22659 md_apply_fix (fixS
* fixP
,
22663 offsetT value
= * valP
;
22665 unsigned int newimm
;
22666 unsigned long temp
;
22668 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22670 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22672 /* Note whether this will delete the relocation. */
22674 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22677 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22678 consistency with the behaviour on 32-bit hosts. Remember value
22680 value
&= 0xffffffff;
22681 value
^= 0x80000000;
22682 value
-= 0x80000000;
22685 fixP
->fx_addnumber
= value
;
22687 /* Same treatment for fixP->fx_offset. */
22688 fixP
->fx_offset
&= 0xffffffff;
22689 fixP
->fx_offset
^= 0x80000000;
22690 fixP
->fx_offset
-= 0x80000000;
22692 switch (fixP
->fx_r_type
)
22694 case BFD_RELOC_NONE
:
22695 /* This will need to go in the object file. */
22699 case BFD_RELOC_ARM_IMMEDIATE
:
22700 /* We claim that this fixup has been processed here,
22701 even if in fact we generate an error because we do
22702 not have a reloc for it, so tc_gen_reloc will reject it. */
22705 if (fixP
->fx_addsy
)
22707 const char *msg
= 0;
22709 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22710 msg
= _("undefined symbol %s used as an immediate value");
22711 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22712 msg
= _("symbol %s is in a different section");
22713 else if (S_IS_WEAK (fixP
->fx_addsy
))
22714 msg
= _("symbol %s is weak and may be overridden later");
22718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22719 msg
, S_GET_NAME (fixP
->fx_addsy
));
22724 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22726 /* If the offset is negative, we should use encoding A2 for ADR. */
22727 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22728 newimm
= negate_data_op (&temp
, value
);
22731 newimm
= encode_arm_immediate (value
);
22733 /* If the instruction will fail, see if we can fix things up by
22734 changing the opcode. */
22735 if (newimm
== (unsigned int) FAIL
)
22736 newimm
= negate_data_op (&temp
, value
);
22739 if (newimm
== (unsigned int) FAIL
)
22741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22742 _("invalid constant (%lx) after fixup"),
22743 (unsigned long) value
);
22747 newimm
|= (temp
& 0xfffff000);
22748 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22751 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22753 unsigned int highpart
= 0;
22754 unsigned int newinsn
= 0xe1a00000; /* nop. */
22756 if (fixP
->fx_addsy
)
22758 const char *msg
= 0;
22760 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22761 msg
= _("undefined symbol %s used as an immediate value");
22762 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22763 msg
= _("symbol %s is in a different section");
22764 else if (S_IS_WEAK (fixP
->fx_addsy
))
22765 msg
= _("symbol %s is weak and may be overridden later");
22769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22770 msg
, S_GET_NAME (fixP
->fx_addsy
));
22775 newimm
= encode_arm_immediate (value
);
22776 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22778 /* If the instruction will fail, see if we can fix things up by
22779 changing the opcode. */
22780 if (newimm
== (unsigned int) FAIL
22781 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22783 /* No ? OK - try using two ADD instructions to generate
22785 newimm
= validate_immediate_twopart (value
, & highpart
);
22787 /* Yes - then make sure that the second instruction is
22789 if (newimm
!= (unsigned int) FAIL
)
22791 /* Still No ? Try using a negated value. */
22792 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22793 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22794 /* Otherwise - give up. */
22797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22798 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22803 /* Replace the first operand in the 2nd instruction (which
22804 is the PC) with the destination register. We have
22805 already added in the PC in the first instruction and we
22806 do not want to do it again. */
22807 newinsn
&= ~ 0xf0000;
22808 newinsn
|= ((newinsn
& 0x0f000) << 4);
22811 newimm
|= (temp
& 0xfffff000);
22812 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22814 highpart
|= (newinsn
& 0xfffff000);
22815 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22819 case BFD_RELOC_ARM_OFFSET_IMM
:
22820 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22823 case BFD_RELOC_ARM_LITERAL
:
22829 if (validate_offset_imm (value
, 0) == FAIL
)
22831 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22833 _("invalid literal constant: pool needs to be closer"));
22835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22836 _("bad immediate value for offset (%ld)"),
22841 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22843 newval
&= 0xfffff000;
22846 newval
&= 0xff7ff000;
22847 newval
|= value
| (sign
? INDEX_UP
: 0);
22849 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22852 case BFD_RELOC_ARM_OFFSET_IMM8
:
22853 case BFD_RELOC_ARM_HWLITERAL
:
22859 if (validate_offset_imm (value
, 1) == FAIL
)
22861 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22863 _("invalid literal constant: pool needs to be closer"));
22865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22866 _("bad immediate value for 8-bit offset (%ld)"),
22871 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22873 newval
&= 0xfffff0f0;
22876 newval
&= 0xff7ff0f0;
22877 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22879 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22882 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22883 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22885 _("bad immediate value for offset (%ld)"), (long) value
);
22888 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22890 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22893 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22894 /* This is a complicated relocation used for all varieties of Thumb32
22895 load/store instruction with immediate offset:
22897 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22898 *4, optional writeback(W)
22899 (doubleword load/store)
22901 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22902 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22903 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22904 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22905 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22907 Uppercase letters indicate bits that are already encoded at
22908 this point. Lowercase letters are our problem. For the
22909 second block of instructions, the secondary opcode nybble
22910 (bits 8..11) is present, and bit 23 is zero, even if this is
22911 a PC-relative operation. */
22912 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22914 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22916 if ((newval
& 0xf0000000) == 0xe0000000)
22918 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22920 newval
|= (1 << 23);
22923 if (value
% 4 != 0)
22925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22926 _("offset not a multiple of 4"));
22932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22933 _("offset out of range"));
22938 else if ((newval
& 0x000f0000) == 0x000f0000)
22940 /* PC-relative, 12-bit offset. */
22942 newval
|= (1 << 23);
22947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22948 _("offset out of range"));
22953 else if ((newval
& 0x00000100) == 0x00000100)
22955 /* Writeback: 8-bit, +/- offset. */
22957 newval
|= (1 << 9);
22962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22963 _("offset out of range"));
22968 else if ((newval
& 0x00000f00) == 0x00000e00)
22970 /* T-instruction: positive 8-bit offset. */
22971 if (value
< 0 || value
> 0xff)
22973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22974 _("offset out of range"));
22982 /* Positive 12-bit or negative 8-bit offset. */
22986 newval
|= (1 << 23);
22996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22997 _("offset out of range"));
23004 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23005 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23008 case BFD_RELOC_ARM_SHIFT_IMM
:
23009 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23010 if (((unsigned long) value
) > 32
23012 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23015 _("shift expression is too large"));
23020 /* Shifts of zero must be done as lsl. */
23022 else if (value
== 32)
23024 newval
&= 0xfffff07f;
23025 newval
|= (value
& 0x1f) << 7;
23026 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23029 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23030 case BFD_RELOC_ARM_T32_ADD_IMM
:
23031 case BFD_RELOC_ARM_T32_IMM12
:
23032 case BFD_RELOC_ARM_T32_ADD_PC12
:
23033 /* We claim that this fixup has been processed here,
23034 even if in fact we generate an error because we do
23035 not have a reloc for it, so tc_gen_reloc will reject it. */
23039 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23042 _("undefined symbol %s used as an immediate value"),
23043 S_GET_NAME (fixP
->fx_addsy
));
23047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23049 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23052 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23053 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23055 newimm
= encode_thumb32_immediate (value
);
23056 if (newimm
== (unsigned int) FAIL
)
23057 newimm
= thumb32_negate_data_op (&newval
, value
);
23059 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23060 && newimm
== (unsigned int) FAIL
)
23062 /* Turn add/sum into addw/subw. */
23063 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23064 newval
= (newval
& 0xfeffffff) | 0x02000000;
23065 /* No flat 12-bit imm encoding for addsw/subsw. */
23066 if ((newval
& 0x00100000) == 0)
23068 /* 12 bit immediate for addw/subw. */
23072 newval
^= 0x00a00000;
23075 newimm
= (unsigned int) FAIL
;
23081 if (newimm
== (unsigned int)FAIL
)
23083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23084 _("invalid constant (%lx) after fixup"),
23085 (unsigned long) value
);
23089 newval
|= (newimm
& 0x800) << 15;
23090 newval
|= (newimm
& 0x700) << 4;
23091 newval
|= (newimm
& 0x0ff);
23093 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23094 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23097 case BFD_RELOC_ARM_SMC
:
23098 if (((unsigned long) value
) > 0xffff)
23099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23100 _("invalid smc expression"));
23101 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23102 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23103 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23106 case BFD_RELOC_ARM_HVC
:
23107 if (((unsigned long) value
) > 0xffff)
23108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23109 _("invalid hvc expression"));
23110 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23111 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23112 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23115 case BFD_RELOC_ARM_SWI
:
23116 if (fixP
->tc_fix_data
!= 0)
23118 if (((unsigned long) value
) > 0xff)
23119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23120 _("invalid swi expression"));
23121 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23123 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23127 if (((unsigned long) value
) > 0x00ffffff)
23128 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23129 _("invalid swi expression"));
23130 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23132 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23136 case BFD_RELOC_ARM_MULTI
:
23137 if (((unsigned long) value
) > 0xffff)
23138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23139 _("invalid expression in load/store multiple"));
23140 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23141 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23145 case BFD_RELOC_ARM_PCREL_CALL
:
23147 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23149 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23150 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23151 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23152 /* Flip the bl to blx. This is a simple flip
23153 bit here because we generate PCREL_CALL for
23154 unconditional bls. */
23156 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23157 newval
= newval
| 0x10000000;
23158 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23164 goto arm_branch_common
;
23166 case BFD_RELOC_ARM_PCREL_JUMP
:
23167 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23169 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23170 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23171 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23173 /* This would map to a bl<cond>, b<cond>,
23174 b<always> to a Thumb function. We
23175 need to force a relocation for this particular
23177 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23181 case BFD_RELOC_ARM_PLT32
:
23183 case BFD_RELOC_ARM_PCREL_BRANCH
:
23185 goto arm_branch_common
;
23187 case BFD_RELOC_ARM_PCREL_BLX
:
23190 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23192 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23193 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23194 && ARM_IS_FUNC (fixP
->fx_addsy
))
23196 /* Flip the blx to a bl and warn. */
23197 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23198 newval
= 0xeb000000;
23199 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23200 _("blx to '%s' an ARM ISA state function changed to bl"),
23202 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23208 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23209 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23213 /* We are going to store value (shifted right by two) in the
23214 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23215 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23216 also be be clear. */
23218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23219 _("misaligned branch destination"));
23220 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23221 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23224 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23226 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23227 newval
|= (value
>> 2) & 0x00ffffff;
23228 /* Set the H bit on BLX instructions. */
23232 newval
|= 0x01000000;
23234 newval
&= ~0x01000000;
23236 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23240 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23241 /* CBZ can only branch forward. */
23243 /* Attempts to use CBZ to branch to the next instruction
23244 (which, strictly speaking, are prohibited) will be turned into
23247 FIXME: It may be better to remove the instruction completely and
23248 perform relaxation. */
23251 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23252 newval
= 0xbf00; /* NOP encoding T1 */
23253 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23260 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23262 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23263 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23269 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23270 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23273 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23275 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23276 newval
|= (value
& 0x1ff) >> 1;
23277 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23281 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23282 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23285 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23287 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23288 newval
|= (value
& 0xfff) >> 1;
23289 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23293 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23295 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23296 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23297 && ARM_IS_FUNC (fixP
->fx_addsy
)
23298 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23300 /* Force a relocation for a branch 20 bits wide. */
23303 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23305 _("conditional branch out of range"));
23307 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23310 addressT S
, J1
, J2
, lo
, hi
;
23312 S
= (value
& 0x00100000) >> 20;
23313 J2
= (value
& 0x00080000) >> 19;
23314 J1
= (value
& 0x00040000) >> 18;
23315 hi
= (value
& 0x0003f000) >> 12;
23316 lo
= (value
& 0x00000ffe) >> 1;
23318 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23319 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23320 newval
|= (S
<< 10) | hi
;
23321 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23322 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23323 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23327 case BFD_RELOC_THUMB_PCREL_BLX
:
23328 /* If there is a blx from a thumb state function to
23329 another thumb function flip this to a bl and warn
23333 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23334 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23335 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23337 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23338 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23339 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23341 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23342 newval
= newval
| 0x1000;
23343 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23344 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23349 goto thumb_bl_common
;
23351 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23352 /* A bl from Thumb state ISA to an internal ARM state function
23353 is converted to a blx. */
23355 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23356 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23357 && ARM_IS_FUNC (fixP
->fx_addsy
)
23358 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23360 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23361 newval
= newval
& ~0x1000;
23362 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23363 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23369 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23370 /* For a BLX instruction, make sure that the relocation is rounded up
23371 to a word boundary. This follows the semantics of the instruction
23372 which specifies that bit 1 of the target address will come from bit
23373 1 of the base address. */
23374 value
= (value
+ 3) & ~ 3;
23377 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23378 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23379 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23382 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23384 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23386 else if ((value
& ~0x1ffffff)
23387 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23389 _("Thumb2 branch out of range"));
23392 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23393 encode_thumb2_b_bl_offset (buf
, value
);
23397 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23398 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23401 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23402 encode_thumb2_b_bl_offset (buf
, value
);
23407 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23412 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23413 md_number_to_chars (buf
, value
, 2);
23417 case BFD_RELOC_ARM_TLS_CALL
:
23418 case BFD_RELOC_ARM_THM_TLS_CALL
:
23419 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23420 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23421 case BFD_RELOC_ARM_TLS_GOTDESC
:
23422 case BFD_RELOC_ARM_TLS_GD32
:
23423 case BFD_RELOC_ARM_TLS_LE32
:
23424 case BFD_RELOC_ARM_TLS_IE32
:
23425 case BFD_RELOC_ARM_TLS_LDM32
:
23426 case BFD_RELOC_ARM_TLS_LDO32
:
23427 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23430 case BFD_RELOC_ARM_GOT32
:
23431 case BFD_RELOC_ARM_GOTOFF
:
23434 case BFD_RELOC_ARM_GOT_PREL
:
23435 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23436 md_number_to_chars (buf
, value
, 4);
23439 case BFD_RELOC_ARM_TARGET2
:
23440 /* TARGET2 is not partial-inplace, so we need to write the
23441 addend here for REL targets, because it won't be written out
23442 during reloc processing later. */
23443 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23444 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23448 case BFD_RELOC_RVA
:
23450 case BFD_RELOC_ARM_TARGET1
:
23451 case BFD_RELOC_ARM_ROSEGREL32
:
23452 case BFD_RELOC_ARM_SBREL32
:
23453 case BFD_RELOC_32_PCREL
:
23455 case BFD_RELOC_32_SECREL
:
23457 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23459 /* For WinCE we only do this for pcrel fixups. */
23460 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23462 md_number_to_chars (buf
, value
, 4);
23466 case BFD_RELOC_ARM_PREL31
:
23467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23469 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23470 if ((value
^ (value
>> 1)) & 0x40000000)
23472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23473 _("rel31 relocation overflow"));
23475 newval
|= value
& 0x7fffffff;
23476 md_number_to_chars (buf
, newval
, 4);
23481 case BFD_RELOC_ARM_CP_OFF_IMM
:
23482 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23483 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23484 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23486 newval
= get_thumb32_insn (buf
);
23487 if ((newval
& 0x0f200f00) == 0x0d000900)
23489 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23490 has permitted values that are multiples of 2, in the range 0
23492 if (value
< -510 || value
> 510 || (value
& 1))
23493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23494 _("co-processor offset out of range"));
23496 else if (value
< -1023 || value
> 1023 || (value
& 3))
23497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23498 _("co-processor offset out of range"));
23503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23504 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23505 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23507 newval
= get_thumb32_insn (buf
);
23509 newval
&= 0xffffff00;
23512 newval
&= 0xff7fff00;
23513 if ((newval
& 0x0f200f00) == 0x0d000900)
23515 /* This is a fp16 vstr/vldr.
23517 It requires the immediate offset in the instruction is shifted
23518 left by 1 to be a half-word offset.
23520 Here, left shift by 1 first, and later right shift by 2
23521 should get the right offset. */
23524 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23526 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23527 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23528 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23530 put_thumb32_insn (buf
, newval
);
23533 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23534 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23535 if (value
< -255 || value
> 255)
23536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23537 _("co-processor offset out of range"));
23539 goto cp_off_common
;
23541 case BFD_RELOC_ARM_THUMB_OFFSET
:
23542 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23543 /* Exactly what ranges, and where the offset is inserted depends
23544 on the type of instruction, we can establish this from the
23546 switch (newval
>> 12)
23548 case 4: /* PC load. */
23549 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23550 forced to zero for these loads; md_pcrel_from has already
23551 compensated for this. */
23553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23554 _("invalid offset, target not word aligned (0x%08lX)"),
23555 (((unsigned long) fixP
->fx_frag
->fr_address
23556 + (unsigned long) fixP
->fx_where
) & ~3)
23557 + (unsigned long) value
);
23559 if (value
& ~0x3fc)
23560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23561 _("invalid offset, value too big (0x%08lX)"),
23564 newval
|= value
>> 2;
23567 case 9: /* SP load/store. */
23568 if (value
& ~0x3fc)
23569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23570 _("invalid offset, value too big (0x%08lX)"),
23572 newval
|= value
>> 2;
23575 case 6: /* Word load/store. */
23577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23578 _("invalid offset, value too big (0x%08lX)"),
23580 newval
|= value
<< 4; /* 6 - 2. */
23583 case 7: /* Byte load/store. */
23585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23586 _("invalid offset, value too big (0x%08lX)"),
23588 newval
|= value
<< 6;
23591 case 8: /* Halfword load/store. */
23593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23594 _("invalid offset, value too big (0x%08lX)"),
23596 newval
|= value
<< 5; /* 6 - 1. */
23600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23601 "Unable to process relocation for thumb opcode: %lx",
23602 (unsigned long) newval
);
23605 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23608 case BFD_RELOC_ARM_THUMB_ADD
:
23609 /* This is a complicated relocation, since we use it for all of
23610 the following immediate relocations:
23614 9bit ADD/SUB SP word-aligned
23615 10bit ADD PC/SP word-aligned
23617 The type of instruction being processed is encoded in the
23624 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23626 int rd
= (newval
>> 4) & 0xf;
23627 int rs
= newval
& 0xf;
23628 int subtract
= !!(newval
& 0x8000);
23630 /* Check for HI regs, only very restricted cases allowed:
23631 Adjusting SP, and using PC or SP to get an address. */
23632 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23633 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23635 _("invalid Hi register with immediate"));
23637 /* If value is negative, choose the opposite instruction. */
23641 subtract
= !subtract
;
23643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23644 _("immediate value out of range"));
23649 if (value
& ~0x1fc)
23650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23651 _("invalid immediate for stack address calculation"));
23652 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23653 newval
|= value
>> 2;
23655 else if (rs
== REG_PC
|| rs
== REG_SP
)
23657 /* PR gas/18541. If the addition is for a defined symbol
23658 within range of an ADR instruction then accept it. */
23661 && fixP
->fx_addsy
!= NULL
)
23665 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23666 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23667 || S_IS_WEAK (fixP
->fx_addsy
))
23669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23670 _("address calculation needs a strongly defined nearby symbol"));
23674 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23676 /* Round up to the next 4-byte boundary. */
23681 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23686 _("symbol too far away"));
23696 if (subtract
|| value
& ~0x3fc)
23697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23698 _("invalid immediate for address calculation (value = 0x%08lX)"),
23699 (unsigned long) (subtract
? - value
: value
));
23700 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23702 newval
|= value
>> 2;
23707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23708 _("immediate value out of range"));
23709 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23710 newval
|= (rd
<< 8) | value
;
23715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23716 _("immediate value out of range"));
23717 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23718 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23721 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23724 case BFD_RELOC_ARM_THUMB_IMM
:
23725 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23726 if (value
< 0 || value
> 255)
23727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23728 _("invalid immediate: %ld is out of range"),
23731 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23734 case BFD_RELOC_ARM_THUMB_SHIFT
:
23735 /* 5bit shift value (0..32). LSL cannot take 32. */
23736 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23737 temp
= newval
& 0xf800;
23738 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23740 _("invalid shift value: %ld"), (long) value
);
23741 /* Shifts of zero must be encoded as LSL. */
23743 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23744 /* Shifts of 32 are encoded as zero. */
23745 else if (value
== 32)
23747 newval
|= value
<< 6;
23748 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23751 case BFD_RELOC_VTABLE_INHERIT
:
23752 case BFD_RELOC_VTABLE_ENTRY
:
23756 case BFD_RELOC_ARM_MOVW
:
23757 case BFD_RELOC_ARM_MOVT
:
23758 case BFD_RELOC_ARM_THUMB_MOVW
:
23759 case BFD_RELOC_ARM_THUMB_MOVT
:
23760 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23762 /* REL format relocations are limited to a 16-bit addend. */
23763 if (!fixP
->fx_done
)
23765 if (value
< -0x8000 || value
> 0x7fff)
23766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23767 _("offset out of range"));
23769 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23770 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23775 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23776 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23778 newval
= get_thumb32_insn (buf
);
23779 newval
&= 0xfbf08f00;
23780 newval
|= (value
& 0xf000) << 4;
23781 newval
|= (value
& 0x0800) << 15;
23782 newval
|= (value
& 0x0700) << 4;
23783 newval
|= (value
& 0x00ff);
23784 put_thumb32_insn (buf
, newval
);
23788 newval
= md_chars_to_number (buf
, 4);
23789 newval
&= 0xfff0f000;
23790 newval
|= value
& 0x0fff;
23791 newval
|= (value
& 0xf000) << 4;
23792 md_number_to_chars (buf
, newval
, 4);
23797 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23798 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23799 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23800 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23801 gas_assert (!fixP
->fx_done
);
23804 bfd_boolean is_mov
;
23805 bfd_vma encoded_addend
= value
;
23807 /* Check that addend can be encoded in instruction. */
23808 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23810 _("the offset 0x%08lX is not representable"),
23811 (unsigned long) encoded_addend
);
23813 /* Extract the instruction. */
23814 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23815 is_mov
= (insn
& 0xf800) == 0x2000;
23820 if (!seg
->use_rela_p
)
23821 insn
|= encoded_addend
;
23827 /* Extract the instruction. */
23828 /* Encoding is the following
23833 /* The following conditions must be true :
23838 rd
= (insn
>> 4) & 0xf;
23840 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23842 _("Unable to process relocation for thumb opcode: %lx"),
23843 (unsigned long) insn
);
23845 /* Encode as ADD immediate8 thumb 1 code. */
23846 insn
= 0x3000 | (rd
<< 8);
23848 /* Place the encoded addend into the first 8 bits of the
23850 if (!seg
->use_rela_p
)
23851 insn
|= encoded_addend
;
23854 /* Update the instruction. */
23855 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23859 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23860 case BFD_RELOC_ARM_ALU_PC_G0
:
23861 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23862 case BFD_RELOC_ARM_ALU_PC_G1
:
23863 case BFD_RELOC_ARM_ALU_PC_G2
:
23864 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23865 case BFD_RELOC_ARM_ALU_SB_G0
:
23866 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23867 case BFD_RELOC_ARM_ALU_SB_G1
:
23868 case BFD_RELOC_ARM_ALU_SB_G2
:
23869 gas_assert (!fixP
->fx_done
);
23870 if (!seg
->use_rela_p
)
23873 bfd_vma encoded_addend
;
23874 bfd_vma addend_abs
= abs (value
);
23876 /* Check that the absolute value of the addend can be
23877 expressed as an 8-bit constant plus a rotation. */
23878 encoded_addend
= encode_arm_immediate (addend_abs
);
23879 if (encoded_addend
== (unsigned int) FAIL
)
23880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23881 _("the offset 0x%08lX is not representable"),
23882 (unsigned long) addend_abs
);
23884 /* Extract the instruction. */
23885 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23887 /* If the addend is positive, use an ADD instruction.
23888 Otherwise use a SUB. Take care not to destroy the S bit. */
23889 insn
&= 0xff1fffff;
23895 /* Place the encoded addend into the first 12 bits of the
23897 insn
&= 0xfffff000;
23898 insn
|= encoded_addend
;
23900 /* Update the instruction. */
23901 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23905 case BFD_RELOC_ARM_LDR_PC_G0
:
23906 case BFD_RELOC_ARM_LDR_PC_G1
:
23907 case BFD_RELOC_ARM_LDR_PC_G2
:
23908 case BFD_RELOC_ARM_LDR_SB_G0
:
23909 case BFD_RELOC_ARM_LDR_SB_G1
:
23910 case BFD_RELOC_ARM_LDR_SB_G2
:
23911 gas_assert (!fixP
->fx_done
);
23912 if (!seg
->use_rela_p
)
23915 bfd_vma addend_abs
= abs (value
);
23917 /* Check that the absolute value of the addend can be
23918 encoded in 12 bits. */
23919 if (addend_abs
>= 0x1000)
23920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23921 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23922 (unsigned long) addend_abs
);
23924 /* Extract the instruction. */
23925 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23927 /* If the addend is negative, clear bit 23 of the instruction.
23928 Otherwise set it. */
23930 insn
&= ~(1 << 23);
23934 /* Place the absolute value of the addend into the first 12 bits
23935 of the instruction. */
23936 insn
&= 0xfffff000;
23937 insn
|= addend_abs
;
23939 /* Update the instruction. */
23940 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23944 case BFD_RELOC_ARM_LDRS_PC_G0
:
23945 case BFD_RELOC_ARM_LDRS_PC_G1
:
23946 case BFD_RELOC_ARM_LDRS_PC_G2
:
23947 case BFD_RELOC_ARM_LDRS_SB_G0
:
23948 case BFD_RELOC_ARM_LDRS_SB_G1
:
23949 case BFD_RELOC_ARM_LDRS_SB_G2
:
23950 gas_assert (!fixP
->fx_done
);
23951 if (!seg
->use_rela_p
)
23954 bfd_vma addend_abs
= abs (value
);
23956 /* Check that the absolute value of the addend can be
23957 encoded in 8 bits. */
23958 if (addend_abs
>= 0x100)
23959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23960 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23961 (unsigned long) addend_abs
);
23963 /* Extract the instruction. */
23964 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23966 /* If the addend is negative, clear bit 23 of the instruction.
23967 Otherwise set it. */
23969 insn
&= ~(1 << 23);
23973 /* Place the first four bits of the absolute value of the addend
23974 into the first 4 bits of the instruction, and the remaining
23975 four into bits 8 .. 11. */
23976 insn
&= 0xfffff0f0;
23977 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23979 /* Update the instruction. */
23980 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23984 case BFD_RELOC_ARM_LDC_PC_G0
:
23985 case BFD_RELOC_ARM_LDC_PC_G1
:
23986 case BFD_RELOC_ARM_LDC_PC_G2
:
23987 case BFD_RELOC_ARM_LDC_SB_G0
:
23988 case BFD_RELOC_ARM_LDC_SB_G1
:
23989 case BFD_RELOC_ARM_LDC_SB_G2
:
23990 gas_assert (!fixP
->fx_done
);
23991 if (!seg
->use_rela_p
)
23994 bfd_vma addend_abs
= abs (value
);
23996 /* Check that the absolute value of the addend is a multiple of
23997 four and, when divided by four, fits in 8 bits. */
23998 if (addend_abs
& 0x3)
23999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24000 _("bad offset 0x%08lX (must be word-aligned)"),
24001 (unsigned long) addend_abs
);
24003 if ((addend_abs
>> 2) > 0xff)
24004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24005 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24006 (unsigned long) addend_abs
);
24008 /* Extract the instruction. */
24009 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24011 /* If the addend is negative, clear bit 23 of the instruction.
24012 Otherwise set it. */
24014 insn
&= ~(1 << 23);
24018 /* Place the addend (divided by four) into the first eight
24019 bits of the instruction. */
24020 insn
&= 0xfffffff0;
24021 insn
|= addend_abs
>> 2;
24023 /* Update the instruction. */
24024 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24028 case BFD_RELOC_ARM_V4BX
:
24029 /* This will need to go in the object file. */
24033 case BFD_RELOC_UNUSED
:
24035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24036 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24040 /* Translate internal representation of relocation info to BFD target
24044 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24047 bfd_reloc_code_real_type code
;
24049 reloc
= XNEW (arelent
);
24051 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24052 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24053 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24055 if (fixp
->fx_pcrel
)
24057 if (section
->use_rela_p
)
24058 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24060 fixp
->fx_offset
= reloc
->address
;
24062 reloc
->addend
= fixp
->fx_offset
;
24064 switch (fixp
->fx_r_type
)
24067 if (fixp
->fx_pcrel
)
24069 code
= BFD_RELOC_8_PCREL
;
24074 if (fixp
->fx_pcrel
)
24076 code
= BFD_RELOC_16_PCREL
;
24081 if (fixp
->fx_pcrel
)
24083 code
= BFD_RELOC_32_PCREL
;
24087 case BFD_RELOC_ARM_MOVW
:
24088 if (fixp
->fx_pcrel
)
24090 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24094 case BFD_RELOC_ARM_MOVT
:
24095 if (fixp
->fx_pcrel
)
24097 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24101 case BFD_RELOC_ARM_THUMB_MOVW
:
24102 if (fixp
->fx_pcrel
)
24104 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24108 case BFD_RELOC_ARM_THUMB_MOVT
:
24109 if (fixp
->fx_pcrel
)
24111 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24115 case BFD_RELOC_NONE
:
24116 case BFD_RELOC_ARM_PCREL_BRANCH
:
24117 case BFD_RELOC_ARM_PCREL_BLX
:
24118 case BFD_RELOC_RVA
:
24119 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24120 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24121 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24122 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24123 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24124 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24125 case BFD_RELOC_VTABLE_ENTRY
:
24126 case BFD_RELOC_VTABLE_INHERIT
:
24128 case BFD_RELOC_32_SECREL
:
24130 code
= fixp
->fx_r_type
;
24133 case BFD_RELOC_THUMB_PCREL_BLX
:
24135 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24136 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24139 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24142 case BFD_RELOC_ARM_LITERAL
:
24143 case BFD_RELOC_ARM_HWLITERAL
:
24144 /* If this is called then the a literal has
24145 been referenced across a section boundary. */
24146 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24147 _("literal referenced across section boundary"));
24151 case BFD_RELOC_ARM_TLS_CALL
:
24152 case BFD_RELOC_ARM_THM_TLS_CALL
:
24153 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24154 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24155 case BFD_RELOC_ARM_GOT32
:
24156 case BFD_RELOC_ARM_GOTOFF
:
24157 case BFD_RELOC_ARM_GOT_PREL
:
24158 case BFD_RELOC_ARM_PLT32
:
24159 case BFD_RELOC_ARM_TARGET1
:
24160 case BFD_RELOC_ARM_ROSEGREL32
:
24161 case BFD_RELOC_ARM_SBREL32
:
24162 case BFD_RELOC_ARM_PREL31
:
24163 case BFD_RELOC_ARM_TARGET2
:
24164 case BFD_RELOC_ARM_TLS_LDO32
:
24165 case BFD_RELOC_ARM_PCREL_CALL
:
24166 case BFD_RELOC_ARM_PCREL_JUMP
:
24167 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24168 case BFD_RELOC_ARM_ALU_PC_G0
:
24169 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24170 case BFD_RELOC_ARM_ALU_PC_G1
:
24171 case BFD_RELOC_ARM_ALU_PC_G2
:
24172 case BFD_RELOC_ARM_LDR_PC_G0
:
24173 case BFD_RELOC_ARM_LDR_PC_G1
:
24174 case BFD_RELOC_ARM_LDR_PC_G2
:
24175 case BFD_RELOC_ARM_LDRS_PC_G0
:
24176 case BFD_RELOC_ARM_LDRS_PC_G1
:
24177 case BFD_RELOC_ARM_LDRS_PC_G2
:
24178 case BFD_RELOC_ARM_LDC_PC_G0
:
24179 case BFD_RELOC_ARM_LDC_PC_G1
:
24180 case BFD_RELOC_ARM_LDC_PC_G2
:
24181 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24182 case BFD_RELOC_ARM_ALU_SB_G0
:
24183 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24184 case BFD_RELOC_ARM_ALU_SB_G1
:
24185 case BFD_RELOC_ARM_ALU_SB_G2
:
24186 case BFD_RELOC_ARM_LDR_SB_G0
:
24187 case BFD_RELOC_ARM_LDR_SB_G1
:
24188 case BFD_RELOC_ARM_LDR_SB_G2
:
24189 case BFD_RELOC_ARM_LDRS_SB_G0
:
24190 case BFD_RELOC_ARM_LDRS_SB_G1
:
24191 case BFD_RELOC_ARM_LDRS_SB_G2
:
24192 case BFD_RELOC_ARM_LDC_SB_G0
:
24193 case BFD_RELOC_ARM_LDC_SB_G1
:
24194 case BFD_RELOC_ARM_LDC_SB_G2
:
24195 case BFD_RELOC_ARM_V4BX
:
24196 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24197 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24198 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24199 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24200 code
= fixp
->fx_r_type
;
24203 case BFD_RELOC_ARM_TLS_GOTDESC
:
24204 case BFD_RELOC_ARM_TLS_GD32
:
24205 case BFD_RELOC_ARM_TLS_LE32
:
24206 case BFD_RELOC_ARM_TLS_IE32
:
24207 case BFD_RELOC_ARM_TLS_LDM32
:
24208 /* BFD will include the symbol's address in the addend.
24209 But we don't want that, so subtract it out again here. */
24210 if (!S_IS_COMMON (fixp
->fx_addsy
))
24211 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24212 code
= fixp
->fx_r_type
;
24216 case BFD_RELOC_ARM_IMMEDIATE
:
24217 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24218 _("internal relocation (type: IMMEDIATE) not fixed up"));
24221 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24222 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24223 _("ADRL used for a symbol not defined in the same file"));
24226 case BFD_RELOC_ARM_OFFSET_IMM
:
24227 if (section
->use_rela_p
)
24229 code
= fixp
->fx_r_type
;
24233 if (fixp
->fx_addsy
!= NULL
24234 && !S_IS_DEFINED (fixp
->fx_addsy
)
24235 && S_IS_LOCAL (fixp
->fx_addsy
))
24237 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24238 _("undefined local label `%s'"),
24239 S_GET_NAME (fixp
->fx_addsy
));
24243 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24244 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24251 switch (fixp
->fx_r_type
)
24253 case BFD_RELOC_NONE
: type
= "NONE"; break;
24254 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24255 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24256 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24257 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24258 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24259 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24260 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24261 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24262 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24263 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24264 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24265 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24266 default: type
= _("<unknown>"); break;
24268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24269 _("cannot represent %s relocation in this object file format"),
24276 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24278 && fixp
->fx_addsy
== GOT_symbol
)
24280 code
= BFD_RELOC_ARM_GOTPC
;
24281 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24285 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24287 if (reloc
->howto
== NULL
)
24289 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24290 _("cannot represent %s relocation in this object file format"),
24291 bfd_get_reloc_code_name (code
));
24295 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24296 vtable entry to be used in the relocation's section offset. */
24297 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24298 reloc
->address
= fixp
->fx_offset
;
24303 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24306 cons_fix_new_arm (fragS
* frag
,
24310 bfd_reloc_code_real_type reloc
)
24315 FIXME: @@ Should look at CPU word size. */
24319 reloc
= BFD_RELOC_8
;
24322 reloc
= BFD_RELOC_16
;
24326 reloc
= BFD_RELOC_32
;
24329 reloc
= BFD_RELOC_64
;
24334 if (exp
->X_op
== O_secrel
)
24336 exp
->X_op
= O_symbol
;
24337 reloc
= BFD_RELOC_32_SECREL
;
24341 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24344 #if defined (OBJ_COFF)
24346 arm_validate_fix (fixS
* fixP
)
24348 /* If the destination of the branch is a defined symbol which does not have
24349 the THUMB_FUNC attribute, then we must be calling a function which has
24350 the (interfacearm) attribute. We look for the Thumb entry point to that
24351 function and change the branch to refer to that function instead. */
24352 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24353 && fixP
->fx_addsy
!= NULL
24354 && S_IS_DEFINED (fixP
->fx_addsy
)
24355 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24357 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24364 arm_force_relocation (struct fix
* fixp
)
24366 #if defined (OBJ_COFF) && defined (TE_PE)
24367 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24371 /* In case we have a call or a branch to a function in ARM ISA mode from
24372 a thumb function or vice-versa force the relocation. These relocations
24373 are cleared off for some cores that might have blx and simple transformations
24377 switch (fixp
->fx_r_type
)
24379 case BFD_RELOC_ARM_PCREL_JUMP
:
24380 case BFD_RELOC_ARM_PCREL_CALL
:
24381 case BFD_RELOC_THUMB_PCREL_BLX
:
24382 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24386 case BFD_RELOC_ARM_PCREL_BLX
:
24387 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24388 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24389 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24390 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24399 /* Resolve these relocations even if the symbol is extern or weak.
24400 Technically this is probably wrong due to symbol preemption.
24401 In practice these relocations do not have enough range to be useful
24402 at dynamic link time, and some code (e.g. in the Linux kernel)
24403 expects these references to be resolved. */
24404 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24405 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24406 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24407 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24408 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24409 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24410 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24411 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24412 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24413 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24414 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24415 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24416 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24417 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24420 /* Always leave these relocations for the linker. */
24421 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24422 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24423 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24426 /* Always generate relocations against function symbols. */
24427 if (fixp
->fx_r_type
== BFD_RELOC_32
24429 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24432 return generic_force_reloc (fixp
);
24435 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24436 /* Relocations against function names must be left unadjusted,
24437 so that the linker can use this information to generate interworking
24438 stubs. The MIPS version of this function
24439 also prevents relocations that are mips-16 specific, but I do not
24440 know why it does this.
24443 There is one other problem that ought to be addressed here, but
24444 which currently is not: Taking the address of a label (rather
24445 than a function) and then later jumping to that address. Such
24446 addresses also ought to have their bottom bit set (assuming that
24447 they reside in Thumb code), but at the moment they will not. */
24450 arm_fix_adjustable (fixS
* fixP
)
24452 if (fixP
->fx_addsy
== NULL
)
24455 /* Preserve relocations against symbols with function type. */
24456 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24459 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24460 && fixP
->fx_subsy
== NULL
)
24463 /* We need the symbol name for the VTABLE entries. */
24464 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24465 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24468 /* Don't allow symbols to be discarded on GOT related relocs. */
24469 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24470 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24471 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24472 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24473 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24474 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24475 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24476 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24477 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24478 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24479 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24480 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24481 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24482 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24485 /* Similarly for group relocations. */
24486 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24487 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24488 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24491 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24492 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24493 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24494 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24495 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24496 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24497 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24498 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24499 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24502 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24503 offsets, so keep these symbols. */
24504 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24505 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24510 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24514 elf32_arm_target_format (void)
24517 return (target_big_endian
24518 ? "elf32-bigarm-symbian"
24519 : "elf32-littlearm-symbian");
24520 #elif defined (TE_VXWORKS)
24521 return (target_big_endian
24522 ? "elf32-bigarm-vxworks"
24523 : "elf32-littlearm-vxworks");
24524 #elif defined (TE_NACL)
24525 return (target_big_endian
24526 ? "elf32-bigarm-nacl"
24527 : "elf32-littlearm-nacl");
24529 if (target_big_endian
)
24530 return "elf32-bigarm";
24532 return "elf32-littlearm";
24537 armelf_frob_symbol (symbolS
* symp
,
24540 elf_frob_symbol (symp
, puntp
);
24544 /* MD interface: Finalization. */
24549 literal_pool
* pool
;
24551 /* Ensure that all the IT blocks are properly closed. */
24552 check_it_blocks_finished ();
24554 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24556 /* Put it at the end of the relevant section. */
24557 subseg_set (pool
->section
, pool
->sub_section
);
24559 arm_elf_change_section ();
24566 /* Remove any excess mapping symbols generated for alignment frags in
24567 SEC. We may have created a mapping symbol before a zero byte
24568 alignment; remove it if there's a mapping symbol after the
24571 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24572 void *dummy ATTRIBUTE_UNUSED
)
24574 segment_info_type
*seginfo
= seg_info (sec
);
24577 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24580 for (fragp
= seginfo
->frchainP
->frch_root
;
24582 fragp
= fragp
->fr_next
)
24584 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24585 fragS
*next
= fragp
->fr_next
;
24587 /* Variable-sized frags have been converted to fixed size by
24588 this point. But if this was variable-sized to start with,
24589 there will be a fixed-size frag after it. So don't handle
24591 if (sym
== NULL
|| next
== NULL
)
24594 if (S_GET_VALUE (sym
) < next
->fr_address
)
24595 /* Not at the end of this frag. */
24597 know (S_GET_VALUE (sym
) == next
->fr_address
);
24601 if (next
->tc_frag_data
.first_map
!= NULL
)
24603 /* Next frag starts with a mapping symbol. Discard this
24605 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24609 if (next
->fr_next
== NULL
)
24611 /* This mapping symbol is at the end of the section. Discard
24613 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24614 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24618 /* As long as we have empty frags without any mapping symbols,
24620 /* If the next frag is non-empty and does not start with a
24621 mapping symbol, then this mapping symbol is required. */
24622 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24625 next
= next
->fr_next
;
24627 while (next
!= NULL
);
24632 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24636 arm_adjust_symtab (void)
24641 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24643 if (ARM_IS_THUMB (sym
))
24645 if (THUMB_IS_FUNC (sym
))
24647 /* Mark the symbol as a Thumb function. */
24648 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24649 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24650 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24652 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24653 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24655 as_bad (_("%s: unexpected function type: %d"),
24656 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24658 else switch (S_GET_STORAGE_CLASS (sym
))
24661 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24664 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24667 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24675 if (ARM_IS_INTERWORK (sym
))
24676 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24683 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24685 if (ARM_IS_THUMB (sym
))
24687 elf_symbol_type
* elf_sym
;
24689 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24690 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24692 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24693 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24695 /* If it's a .thumb_func, declare it as so,
24696 otherwise tag label as .code 16. */
24697 if (THUMB_IS_FUNC (sym
))
24698 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24699 ST_BRANCH_TO_THUMB
);
24700 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24701 elf_sym
->internal_elf_sym
.st_info
=
24702 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24707 /* Remove any overlapping mapping symbols generated by alignment frags. */
24708 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24709 /* Now do generic ELF adjustments. */
24710 elf_adjust_symtab ();
24714 /* MD interface: Initialization. */
24717 set_constant_flonums (void)
24721 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24722 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24726 /* Auto-select Thumb mode if it's the only available instruction set for the
24727 given architecture. */
24730 autoselect_thumb_from_cpu_variant (void)
24732 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24733 opcode_select (16);
24742 if ( (arm_ops_hsh
= hash_new ()) == NULL
24743 || (arm_cond_hsh
= hash_new ()) == NULL
24744 || (arm_shift_hsh
= hash_new ()) == NULL
24745 || (arm_psr_hsh
= hash_new ()) == NULL
24746 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24747 || (arm_reg_hsh
= hash_new ()) == NULL
24748 || (arm_reloc_hsh
= hash_new ()) == NULL
24749 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24750 as_fatal (_("virtual memory exhausted"));
24752 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24753 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24754 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24755 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24756 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24757 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24758 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24759 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24760 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24761 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24762 (void *) (v7m_psrs
+ i
));
24763 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24764 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24766 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24768 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24769 (void *) (barrier_opt_names
+ i
));
24771 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24773 struct reloc_entry
* entry
= reloc_names
+ i
;
24775 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24776 /* This makes encode_branch() use the EABI versions of this relocation. */
24777 entry
->reloc
= BFD_RELOC_UNUSED
;
24779 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24783 set_constant_flonums ();
24785 /* Set the cpu variant based on the command-line options. We prefer
24786 -mcpu= over -march= if both are set (as for GCC); and we prefer
24787 -mfpu= over any other way of setting the floating point unit.
24788 Use of legacy options with new options are faulted. */
24791 if (mcpu_cpu_opt
|| march_cpu_opt
)
24792 as_bad (_("use of old and new-style options to set CPU type"));
24794 mcpu_cpu_opt
= legacy_cpu
;
24796 else if (!mcpu_cpu_opt
)
24797 mcpu_cpu_opt
= march_cpu_opt
;
24802 as_bad (_("use of old and new-style options to set FPU type"));
24804 mfpu_opt
= legacy_fpu
;
24806 else if (!mfpu_opt
)
24808 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24809 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24810 /* Some environments specify a default FPU. If they don't, infer it
24811 from the processor. */
24813 mfpu_opt
= mcpu_fpu_opt
;
24815 mfpu_opt
= march_fpu_opt
;
24817 mfpu_opt
= &fpu_default
;
24823 if (mcpu_cpu_opt
!= NULL
)
24824 mfpu_opt
= &fpu_default
;
24825 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24826 mfpu_opt
= &fpu_arch_vfp_v2
;
24828 mfpu_opt
= &fpu_arch_fpa
;
24834 mcpu_cpu_opt
= &cpu_default
;
24835 selected_cpu
= cpu_default
;
24837 else if (no_cpu_selected ())
24838 selected_cpu
= cpu_default
;
24841 selected_cpu
= *mcpu_cpu_opt
;
24843 mcpu_cpu_opt
= &arm_arch_any
;
24846 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24848 autoselect_thumb_from_cpu_variant ();
24850 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24852 #if defined OBJ_COFF || defined OBJ_ELF
24854 unsigned int flags
= 0;
24856 #if defined OBJ_ELF
24857 flags
= meabi_flags
;
24859 switch (meabi_flags
)
24861 case EF_ARM_EABI_UNKNOWN
:
24863 /* Set the flags in the private structure. */
24864 if (uses_apcs_26
) flags
|= F_APCS26
;
24865 if (support_interwork
) flags
|= F_INTERWORK
;
24866 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24867 if (pic_code
) flags
|= F_PIC
;
24868 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24869 flags
|= F_SOFT_FLOAT
;
24871 switch (mfloat_abi_opt
)
24873 case ARM_FLOAT_ABI_SOFT
:
24874 case ARM_FLOAT_ABI_SOFTFP
:
24875 flags
|= F_SOFT_FLOAT
;
24878 case ARM_FLOAT_ABI_HARD
:
24879 if (flags
& F_SOFT_FLOAT
)
24880 as_bad (_("hard-float conflicts with specified fpu"));
24884 /* Using pure-endian doubles (even if soft-float). */
24885 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24886 flags
|= F_VFP_FLOAT
;
24888 #if defined OBJ_ELF
24889 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24890 flags
|= EF_ARM_MAVERICK_FLOAT
;
24893 case EF_ARM_EABI_VER4
:
24894 case EF_ARM_EABI_VER5
:
24895 /* No additional flags to set. */
24902 bfd_set_private_flags (stdoutput
, flags
);
24904 /* We have run out flags in the COFF header to encode the
24905 status of ATPCS support, so instead we create a dummy,
24906 empty, debug section called .arm.atpcs. */
24911 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24915 bfd_set_section_flags
24916 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24917 bfd_set_section_size (stdoutput
, sec
, 0);
24918 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24924 /* Record the CPU type as well. */
24925 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24926 mach
= bfd_mach_arm_iWMMXt2
;
24927 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24928 mach
= bfd_mach_arm_iWMMXt
;
24929 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24930 mach
= bfd_mach_arm_XScale
;
24931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24932 mach
= bfd_mach_arm_ep9312
;
24933 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24934 mach
= bfd_mach_arm_5TE
;
24935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24938 mach
= bfd_mach_arm_5T
;
24940 mach
= bfd_mach_arm_5
;
24942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24944 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24945 mach
= bfd_mach_arm_4T
;
24947 mach
= bfd_mach_arm_4
;
24949 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24950 mach
= bfd_mach_arm_3M
;
24951 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24952 mach
= bfd_mach_arm_3
;
24953 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24954 mach
= bfd_mach_arm_2a
;
24955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24956 mach
= bfd_mach_arm_2
;
24958 mach
= bfd_mach_arm_unknown
;
24960 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24963 /* Command line processing. */
24966 Invocation line includes a switch not recognized by the base assembler.
24967 See if it's a processor-specific option.
24969 This routine is somewhat complicated by the need for backwards
24970 compatibility (since older releases of gcc can't be changed).
24971 The new options try to make the interface as compatible as
24974 New options (supported) are:
24976 -mcpu=<cpu name> Assemble for selected processor
24977 -march=<architecture name> Assemble for selected architecture
24978 -mfpu=<fpu architecture> Assemble for selected FPU.
24979 -EB/-mbig-endian Big-endian
24980 -EL/-mlittle-endian Little-endian
24981 -k Generate PIC code
24982 -mthumb Start in Thumb mode
24983 -mthumb-interwork Code supports ARM/Thumb interworking
24985 -m[no-]warn-deprecated Warn about deprecated features
24986 -m[no-]warn-syms Warn when symbols match instructions
24988 For now we will also provide support for:
24990 -mapcs-32 32-bit Program counter
24991 -mapcs-26 26-bit Program counter
24992 -macps-float Floats passed in FP registers
24993 -mapcs-reentrant Reentrant code
24995 (sometime these will probably be replaced with -mapcs=<list of options>
24996 and -matpcs=<list of options>)
24998 The remaining options are only supported for back-wards compatibility.
24999 Cpu variants, the arm part is optional:
25000 -m[arm]1 Currently not supported.
25001 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25002 -m[arm]3 Arm 3 processor
25003 -m[arm]6[xx], Arm 6 processors
25004 -m[arm]7[xx][t][[d]m] Arm 7 processors
25005 -m[arm]8[10] Arm 8 processors
25006 -m[arm]9[20][tdmi] Arm 9 processors
25007 -mstrongarm[110[0]] StrongARM processors
25008 -mxscale XScale processors
25009 -m[arm]v[2345[t[e]]] Arm architectures
25010 -mall All (except the ARM1)
25012 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25013 -mfpe-old (No float load/store multiples)
25014 -mvfpxd VFP Single precision
25016 -mno-fpu Disable all floating point instructions
25018 The following CPU names are recognized:
25019 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25020 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25021 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25022 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25023 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25024 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25025 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25029 const char * md_shortopts
= "m:k";
25031 #ifdef ARM_BI_ENDIAN
25032 #define OPTION_EB (OPTION_MD_BASE + 0)
25033 #define OPTION_EL (OPTION_MD_BASE + 1)
25035 #if TARGET_BYTES_BIG_ENDIAN
25036 #define OPTION_EB (OPTION_MD_BASE + 0)
25038 #define OPTION_EL (OPTION_MD_BASE + 1)
25041 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25043 struct option md_longopts
[] =
25046 {"EB", no_argument
, NULL
, OPTION_EB
},
25049 {"EL", no_argument
, NULL
, OPTION_EL
},
25051 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25052 {NULL
, no_argument
, NULL
, 0}
25056 size_t md_longopts_size
= sizeof (md_longopts
);
25058 struct arm_option_table
25060 const char *option
; /* Option name to match. */
25061 const char *help
; /* Help information. */
25062 int *var
; /* Variable to change. */
25063 int value
; /* What to change it to. */
25064 const char *deprecated
; /* If non-null, print this message. */
25067 struct arm_option_table arm_opts
[] =
25069 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25070 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25071 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25072 &support_interwork
, 1, NULL
},
25073 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25074 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25075 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25077 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25078 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25079 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25080 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25083 /* These are recognized by the assembler, but have no affect on code. */
25084 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25085 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25087 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25088 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25089 &warn_on_deprecated
, 0, NULL
},
25090 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25091 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25092 {NULL
, NULL
, NULL
, 0, NULL
}
25095 struct arm_legacy_option_table
25097 const char *option
; /* Option name to match. */
25098 const arm_feature_set
**var
; /* Variable to change. */
25099 const arm_feature_set value
; /* What to change it to. */
25100 const char *deprecated
; /* If non-null, print this message. */
25103 const struct arm_legacy_option_table arm_legacy_opts
[] =
25105 /* DON'T add any new processors to this list -- we want the whole list
25106 to go away... Add them to the processors table instead. */
25107 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25108 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25109 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25110 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25111 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25112 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25113 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25114 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25115 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25116 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25117 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25118 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25119 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25120 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25121 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25122 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25123 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25124 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25125 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25126 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25127 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25128 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25129 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25130 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25131 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25132 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25133 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25134 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25135 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25136 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25137 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25138 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25139 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25140 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25141 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25142 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25143 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25144 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25145 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25146 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25147 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25148 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25149 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25150 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25151 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25152 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25153 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25154 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25155 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25156 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25157 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25158 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25159 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25160 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25161 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25162 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25163 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25164 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25165 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25166 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25167 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25168 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25169 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25170 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25171 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25172 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25173 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25174 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25175 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25176 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25177 N_("use -mcpu=strongarm110")},
25178 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25179 N_("use -mcpu=strongarm1100")},
25180 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25181 N_("use -mcpu=strongarm1110")},
25182 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25183 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25184 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25186 /* Architecture variants -- don't add any more to this list either. */
25187 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25188 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25189 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25190 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25191 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25192 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25193 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25194 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25195 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25196 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25197 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25198 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25199 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25200 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25201 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25202 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25203 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25204 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25206 /* Floating point variants -- don't add any more to this list either. */
25207 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25208 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25209 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25210 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25211 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25213 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25216 struct arm_cpu_option_table
25220 const arm_feature_set value
;
25221 /* For some CPUs we assume an FPU unless the user explicitly sets
25223 const arm_feature_set default_fpu
;
25224 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25226 const char *canonical_name
;
25229 /* This list should, at a minimum, contain all the cpu names
25230 recognized by GCC. */
25231 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25232 static const struct arm_cpu_option_table arm_cpus
[] =
25234 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25236 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25237 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25238 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25239 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25240 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25241 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25242 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25243 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25244 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25245 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25246 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25247 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25248 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25249 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25250 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25251 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25252 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25253 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25254 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25255 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25256 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25257 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25258 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25259 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25260 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25261 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25262 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25263 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25264 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25265 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25266 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25267 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25268 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25269 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25270 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25271 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25272 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25273 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25274 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25275 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25276 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25277 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25278 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25279 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25280 /* For V5 or later processors we default to using VFP; but the user
25281 should really set the FPU type explicitly. */
25282 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25283 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25284 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25285 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25286 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25287 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25288 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25289 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25290 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25291 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25292 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25293 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25294 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25295 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25296 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25297 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25298 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25299 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25300 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25301 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25303 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25304 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25305 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25306 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25307 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25308 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25309 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25310 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25311 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25313 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25314 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25315 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25316 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25317 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25318 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25319 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25320 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25321 FPU_NONE
, "Cortex-A5"),
25322 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25324 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25325 ARM_FEATURE_COPROC (FPU_VFP_V3
25326 | FPU_NEON_EXT_V1
),
25328 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25329 ARM_FEATURE_COPROC (FPU_VFP_V3
25330 | FPU_NEON_EXT_V1
),
25332 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25334 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25336 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25338 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25340 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25342 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25344 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25346 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25348 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25349 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25351 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25352 FPU_NONE
, "Cortex-R5"),
25353 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25354 FPU_ARCH_VFP_V3D16
,
25356 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25357 FPU_ARCH_VFP_V3D16
,
25359 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25360 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25361 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25362 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25363 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25364 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25365 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25368 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25372 /* ??? XSCALE is really an architecture. */
25373 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25374 /* ??? iwmmxt is not a processor. */
25375 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25376 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25377 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25379 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25380 FPU_ARCH_MAVERICK
, "ARM920T"),
25381 /* Marvell processors. */
25382 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25384 ARM_EXT2_V6T2_V8M
),
25385 FPU_ARCH_VFP_V3D16
, NULL
),
25386 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25388 ARM_EXT2_V6T2_V8M
),
25389 FPU_ARCH_NEON_VFP_V4
, NULL
),
25390 /* APM X-Gene family. */
25391 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25393 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25396 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25400 struct arm_arch_option_table
25404 const arm_feature_set value
;
25405 const arm_feature_set default_fpu
;
25408 /* This list should, at a minimum, contain all the architecture names
25409 recognized by GCC. */
25410 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25411 static const struct arm_arch_option_table arm_archs
[] =
25413 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25414 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25415 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25416 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25417 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25418 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25419 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25420 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25421 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25422 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25423 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25424 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25425 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25426 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25427 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25428 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25429 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25430 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25431 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25432 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25433 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25434 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25435 kept to preserve existing behaviour. */
25436 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25437 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25438 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25439 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25440 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25441 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25442 kept to preserve existing behaviour. */
25443 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25444 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25445 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25446 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25447 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25448 /* The official spelling of the ARMv7 profile variants is the dashed form.
25449 Accept the non-dashed form for compatibility with old toolchains. */
25450 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25451 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25452 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25453 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25454 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25455 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25456 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25457 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25458 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25459 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25460 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25461 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25462 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25463 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25464 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25465 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25466 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25468 #undef ARM_ARCH_OPT
25470 /* ISA extensions in the co-processor and main instruction set space. */
25471 struct arm_option_extension_value_table
25475 const arm_feature_set merge_value
;
25476 const arm_feature_set clear_value
;
25477 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25478 indicates that an extension is available for all architectures while
25479 ARM_ANY marks an empty entry. */
25480 const arm_feature_set allowed_archs
[2];
25483 /* The following table must be in alphabetical order with a NULL last entry.
25485 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25486 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25487 static const struct arm_option_extension_value_table arm_extensions
[] =
25489 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25490 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25491 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25492 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25493 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25494 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25495 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25496 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25497 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25498 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25499 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25500 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25502 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25503 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25504 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25505 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25506 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25507 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25508 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25509 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25510 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25511 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25512 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25513 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25514 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25515 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25516 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25517 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25518 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25519 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25520 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25521 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25522 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25523 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25524 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25525 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25526 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25527 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25528 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25529 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25530 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25531 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25532 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25534 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25535 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25536 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25537 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25538 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25542 /* ISA floating-point and Advanced SIMD extensions. */
25543 struct arm_option_fpu_value_table
25546 const arm_feature_set value
;
25549 /* This list should, at a minimum, contain all the fpu names
25550 recognized by GCC. */
25551 static const struct arm_option_fpu_value_table arm_fpus
[] =
25553 {"softfpa", FPU_NONE
},
25554 {"fpe", FPU_ARCH_FPE
},
25555 {"fpe2", FPU_ARCH_FPE
},
25556 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25557 {"fpa", FPU_ARCH_FPA
},
25558 {"fpa10", FPU_ARCH_FPA
},
25559 {"fpa11", FPU_ARCH_FPA
},
25560 {"arm7500fe", FPU_ARCH_FPA
},
25561 {"softvfp", FPU_ARCH_VFP
},
25562 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25563 {"vfp", FPU_ARCH_VFP_V2
},
25564 {"vfp9", FPU_ARCH_VFP_V2
},
25565 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25566 {"vfp10", FPU_ARCH_VFP_V2
},
25567 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25568 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25569 {"vfpv2", FPU_ARCH_VFP_V2
},
25570 {"vfpv3", FPU_ARCH_VFP_V3
},
25571 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25572 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25573 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25574 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25575 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25576 {"arm1020t", FPU_ARCH_VFP_V1
},
25577 {"arm1020e", FPU_ARCH_VFP_V2
},
25578 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25579 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25580 {"maverick", FPU_ARCH_MAVERICK
},
25581 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25582 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25583 {"vfpv4", FPU_ARCH_VFP_V4
},
25584 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25585 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25586 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25587 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25588 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25589 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25590 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25591 {"crypto-neon-fp-armv8",
25592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25593 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25594 {"crypto-neon-fp-armv8.1",
25595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25596 {NULL
, ARM_ARCH_NONE
}
25599 struct arm_option_value_table
25605 static const struct arm_option_value_table arm_float_abis
[] =
25607 {"hard", ARM_FLOAT_ABI_HARD
},
25608 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25609 {"soft", ARM_FLOAT_ABI_SOFT
},
25614 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25615 static const struct arm_option_value_table arm_eabis
[] =
25617 {"gnu", EF_ARM_EABI_UNKNOWN
},
25618 {"4", EF_ARM_EABI_VER4
},
25619 {"5", EF_ARM_EABI_VER5
},
25624 struct arm_long_option_table
25626 const char * option
; /* Substring to match. */
25627 const char * help
; /* Help information. */
25628 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25629 const char * deprecated
; /* If non-null, print this message. */
25633 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25635 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25637 /* We insist on extensions being specified in alphabetical order, and with
25638 extensions being added before being removed. We achieve this by having
25639 the global ARM_EXTENSIONS table in alphabetical order, and using the
25640 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25641 or removing it (0) and only allowing it to change in the order
25643 const struct arm_option_extension_value_table
* opt
= NULL
;
25644 const arm_feature_set arm_any
= ARM_ANY
;
25645 int adding_value
= -1;
25647 /* Copy the feature set, so that we can modify it. */
25648 *ext_set
= **opt_p
;
25651 while (str
!= NULL
&& *str
!= 0)
25658 as_bad (_("invalid architectural extension"));
25663 ext
= strchr (str
, '+');
25668 len
= strlen (str
);
25670 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25672 if (adding_value
!= 0)
25675 opt
= arm_extensions
;
25683 if (adding_value
== -1)
25686 opt
= arm_extensions
;
25688 else if (adding_value
!= 1)
25690 as_bad (_("must specify extensions to add before specifying "
25691 "those to remove"));
25698 as_bad (_("missing architectural extension"));
25702 gas_assert (adding_value
!= -1);
25703 gas_assert (opt
!= NULL
);
25705 /* Scan over the options table trying to find an exact match. */
25706 for (; opt
->name
!= NULL
; opt
++)
25707 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25709 int i
, nb_allowed_archs
=
25710 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25711 /* Check we can apply the extension to this architecture. */
25712 for (i
= 0; i
< nb_allowed_archs
; i
++)
25715 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25717 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25720 if (i
== nb_allowed_archs
)
25722 as_bad (_("extension does not apply to the base architecture"));
25726 /* Add or remove the extension. */
25728 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25730 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25735 if (opt
->name
== NULL
)
25737 /* Did we fail to find an extension because it wasn't specified in
25738 alphabetical order, or because it does not exist? */
25740 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25741 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25744 if (opt
->name
== NULL
)
25745 as_bad (_("unknown architectural extension `%s'"), str
);
25747 as_bad (_("architectural extensions must be specified in "
25748 "alphabetical order"));
25754 /* We should skip the extension we've just matched the next time
25766 arm_parse_cpu (const char *str
)
25768 const struct arm_cpu_option_table
*opt
;
25769 const char *ext
= strchr (str
, '+');
25775 len
= strlen (str
);
25779 as_bad (_("missing cpu name `%s'"), str
);
25783 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25784 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25786 mcpu_cpu_opt
= &opt
->value
;
25787 mcpu_fpu_opt
= &opt
->default_fpu
;
25788 if (opt
->canonical_name
)
25790 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25791 strcpy (selected_cpu_name
, opt
->canonical_name
);
25797 if (len
>= sizeof selected_cpu_name
)
25798 len
= (sizeof selected_cpu_name
) - 1;
25800 for (i
= 0; i
< len
; i
++)
25801 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25802 selected_cpu_name
[i
] = 0;
25806 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25811 as_bad (_("unknown cpu `%s'"), str
);
25816 arm_parse_arch (const char *str
)
25818 const struct arm_arch_option_table
*opt
;
25819 const char *ext
= strchr (str
, '+');
25825 len
= strlen (str
);
25829 as_bad (_("missing architecture name `%s'"), str
);
25833 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25834 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25836 march_cpu_opt
= &opt
->value
;
25837 march_fpu_opt
= &opt
->default_fpu
;
25838 strcpy (selected_cpu_name
, opt
->name
);
25841 return arm_parse_extension (ext
, &march_cpu_opt
);
25846 as_bad (_("unknown architecture `%s'\n"), str
);
25851 arm_parse_fpu (const char * str
)
25853 const struct arm_option_fpu_value_table
* opt
;
25855 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25856 if (streq (opt
->name
, str
))
25858 mfpu_opt
= &opt
->value
;
25862 as_bad (_("unknown floating point format `%s'\n"), str
);
25867 arm_parse_float_abi (const char * str
)
25869 const struct arm_option_value_table
* opt
;
25871 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25872 if (streq (opt
->name
, str
))
25874 mfloat_abi_opt
= opt
->value
;
25878 as_bad (_("unknown floating point abi `%s'\n"), str
);
25884 arm_parse_eabi (const char * str
)
25886 const struct arm_option_value_table
*opt
;
25888 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25889 if (streq (opt
->name
, str
))
25891 meabi_flags
= opt
->value
;
25894 as_bad (_("unknown EABI `%s'\n"), str
);
25900 arm_parse_it_mode (const char * str
)
25902 bfd_boolean ret
= TRUE
;
25904 if (streq ("arm", str
))
25905 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25906 else if (streq ("thumb", str
))
25907 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25908 else if (streq ("always", str
))
25909 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25910 else if (streq ("never", str
))
25911 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25914 as_bad (_("unknown implicit IT mode `%s', should be "\
25915 "arm, thumb, always, or never."), str
);
25923 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25925 codecomposer_syntax
= TRUE
;
25926 arm_comment_chars
[0] = ';';
25927 arm_line_separator_chars
[0] = 0;
25931 struct arm_long_option_table arm_long_opts
[] =
25933 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25934 arm_parse_cpu
, NULL
},
25935 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25936 arm_parse_arch
, NULL
},
25937 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25938 arm_parse_fpu
, NULL
},
25939 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25940 arm_parse_float_abi
, NULL
},
25942 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25943 arm_parse_eabi
, NULL
},
25945 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25946 arm_parse_it_mode
, NULL
},
25947 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25948 arm_ccs_mode
, NULL
},
25949 {NULL
, NULL
, 0, NULL
}
25953 md_parse_option (int c
, const char * arg
)
25955 struct arm_option_table
*opt
;
25956 const struct arm_legacy_option_table
*fopt
;
25957 struct arm_long_option_table
*lopt
;
25963 target_big_endian
= 1;
25969 target_big_endian
= 0;
25973 case OPTION_FIX_V4BX
:
25978 /* Listing option. Just ignore these, we don't support additional
25983 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25985 if (c
== opt
->option
[0]
25986 && ((arg
== NULL
&& opt
->option
[1] == 0)
25987 || streq (arg
, opt
->option
+ 1)))
25989 /* If the option is deprecated, tell the user. */
25990 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25991 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25992 arg
? arg
: "", _(opt
->deprecated
));
25994 if (opt
->var
!= NULL
)
25995 *opt
->var
= opt
->value
;
26001 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26003 if (c
== fopt
->option
[0]
26004 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26005 || streq (arg
, fopt
->option
+ 1)))
26007 /* If the option is deprecated, tell the user. */
26008 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26009 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26010 arg
? arg
: "", _(fopt
->deprecated
));
26012 if (fopt
->var
!= NULL
)
26013 *fopt
->var
= &fopt
->value
;
26019 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26021 /* These options are expected to have an argument. */
26022 if (c
== lopt
->option
[0]
26024 && strncmp (arg
, lopt
->option
+ 1,
26025 strlen (lopt
->option
+ 1)) == 0)
26027 /* If the option is deprecated, tell the user. */
26028 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26029 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26030 _(lopt
->deprecated
));
26032 /* Call the sup-option parser. */
26033 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26044 md_show_usage (FILE * fp
)
26046 struct arm_option_table
*opt
;
26047 struct arm_long_option_table
*lopt
;
26049 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26051 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26052 if (opt
->help
!= NULL
)
26053 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26055 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26056 if (lopt
->help
!= NULL
)
26057 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26061 -EB assemble code for a big-endian cpu\n"));
26066 -EL assemble code for a little-endian cpu\n"));
26070 --fix-v4bx Allow BX in ARMv4 code\n"));
26078 arm_feature_set flags
;
26079 } cpu_arch_ver_table
;
26081 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26082 must be sorted least features first but some reordering is needed, eg. for
26083 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26084 static const cpu_arch_ver_table cpu_arch_ver
[] =
26090 {4, ARM_ARCH_V5TE
},
26091 {5, ARM_ARCH_V5TEJ
},
26095 {11, ARM_ARCH_V6M
},
26096 {12, ARM_ARCH_V6SM
},
26097 {8, ARM_ARCH_V6T2
},
26098 {10, ARM_ARCH_V7VE
},
26099 {10, ARM_ARCH_V7R
},
26100 {10, ARM_ARCH_V7M
},
26101 {14, ARM_ARCH_V8A
},
26102 {16, ARM_ARCH_V8M_BASE
},
26103 {17, ARM_ARCH_V8M_MAIN
},
26107 /* Set an attribute if it has not already been set by the user. */
26109 aeabi_set_attribute_int (int tag
, int value
)
26112 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26113 || !attributes_set_explicitly
[tag
])
26114 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26118 aeabi_set_attribute_string (int tag
, const char *value
)
26121 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26122 || !attributes_set_explicitly
[tag
])
26123 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26126 /* Set the public EABI object attributes. */
26128 aeabi_set_public_attributes (void)
26133 int fp16_optional
= 0;
26134 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26135 arm_feature_set flags
;
26136 arm_feature_set tmp
;
26137 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26138 const cpu_arch_ver_table
*p
;
26140 /* Choose the architecture based on the capabilities of the requested cpu
26141 (if any) and/or the instructions actually used. */
26142 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26143 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26144 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26146 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26147 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26149 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26150 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26152 selected_cpu
= flags
;
26154 /* Allow the user to override the reported architecture. */
26157 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26158 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26161 /* We need to make sure that the attributes do not identify us as v6S-M
26162 when the only v6S-M feature in use is the Operating System Extensions. */
26163 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26164 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26165 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26169 for (p
= cpu_arch_ver
; p
->val
; p
++)
26171 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26174 arm_arch
= p
->flags
;
26175 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26179 /* The table lookup above finds the last architecture to contribute
26180 a new feature. Unfortunately, Tag13 is a subset of the union of
26181 v6T2 and v7-M, so it is never seen as contributing a new feature.
26182 We can not search for the last entry which is entirely used,
26183 because if no CPU is specified we build up only those flags
26184 actually used. Perhaps we should separate out the specified
26185 and implicit cases. Avoid taking this path for -march=all by
26186 checking for contradictory v7-A / v7-M features. */
26187 if (arch
== TAG_CPU_ARCH_V7
26188 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26189 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26190 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26192 arch
= TAG_CPU_ARCH_V7E_M
;
26193 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26196 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26197 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26199 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26200 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26203 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26204 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26205 ARMv8-M, -march=all must be detected as ARMv8-A. */
26206 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26207 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26209 arch
= TAG_CPU_ARCH_V8
;
26210 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26213 /* Tag_CPU_name. */
26214 if (selected_cpu_name
[0])
26218 q
= selected_cpu_name
;
26219 if (strncmp (q
, "armv", 4) == 0)
26224 for (i
= 0; q
[i
]; i
++)
26225 q
[i
] = TOUPPER (q
[i
]);
26227 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26230 /* Tag_CPU_arch. */
26231 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26233 /* Tag_CPU_arch_profile. */
26234 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26235 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26236 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26237 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26239 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26241 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26246 if (profile
!= '\0')
26247 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26249 /* Tag_DSP_extension. */
26250 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26252 arm_feature_set ext
;
26254 /* DSP instructions not in architecture. */
26255 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26256 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26257 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26260 /* Tag_ARM_ISA_use. */
26261 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26263 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26265 /* Tag_THUMB_ISA_use. */
26266 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26271 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26272 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26274 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26278 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26281 /* Tag_VFP_arch. */
26282 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26283 aeabi_set_attribute_int (Tag_VFP_arch
,
26284 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26286 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26287 aeabi_set_attribute_int (Tag_VFP_arch
,
26288 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26290 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26293 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26295 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26297 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26300 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26301 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26302 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26303 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26304 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26306 /* Tag_ABI_HardFP_use. */
26307 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26308 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26309 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26311 /* Tag_WMMX_arch. */
26312 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26313 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26314 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26315 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26317 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26318 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26319 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26320 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26321 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26322 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26324 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26326 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26330 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26335 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26336 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26337 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26341 We set Tag_DIV_use to two when integer divide instructions have been used
26342 in ARM state, or when Thumb integer divide instructions have been used,
26343 but we have no architecture profile set, nor have we any ARM instructions.
26345 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26346 by the base architecture.
26348 For new architectures we will have to check these tests. */
26349 gas_assert (arch
<= TAG_CPU_ARCH_V8
26350 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26351 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26352 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26353 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26354 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26355 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26356 || (profile
== '\0'
26357 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26358 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26359 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26361 /* Tag_MP_extension_use. */
26362 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26363 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26365 /* Tag Virtualization_use. */
26366 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26368 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26371 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26374 /* Add the default contents for the .ARM.attributes section. */
26378 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26381 aeabi_set_public_attributes ();
26383 #endif /* OBJ_ELF */
26386 /* Parse a .cpu directive. */
26389 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26391 const struct arm_cpu_option_table
*opt
;
26395 name
= input_line_pointer
;
26396 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26397 input_line_pointer
++;
26398 saved_char
= *input_line_pointer
;
26399 *input_line_pointer
= 0;
26401 /* Skip the first "all" entry. */
26402 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26403 if (streq (opt
->name
, name
))
26405 mcpu_cpu_opt
= &opt
->value
;
26406 selected_cpu
= opt
->value
;
26407 if (opt
->canonical_name
)
26408 strcpy (selected_cpu_name
, opt
->canonical_name
);
26412 for (i
= 0; opt
->name
[i
]; i
++)
26413 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26415 selected_cpu_name
[i
] = 0;
26417 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26418 *input_line_pointer
= saved_char
;
26419 demand_empty_rest_of_line ();
26422 as_bad (_("unknown cpu `%s'"), name
);
26423 *input_line_pointer
= saved_char
;
26424 ignore_rest_of_line ();
26428 /* Parse a .arch directive. */
26431 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26433 const struct arm_arch_option_table
*opt
;
26437 name
= input_line_pointer
;
26438 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26439 input_line_pointer
++;
26440 saved_char
= *input_line_pointer
;
26441 *input_line_pointer
= 0;
26443 /* Skip the first "all" entry. */
26444 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26445 if (streq (opt
->name
, name
))
26447 mcpu_cpu_opt
= &opt
->value
;
26448 selected_cpu
= opt
->value
;
26449 strcpy (selected_cpu_name
, opt
->name
);
26450 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26451 *input_line_pointer
= saved_char
;
26452 demand_empty_rest_of_line ();
26456 as_bad (_("unknown architecture `%s'\n"), name
);
26457 *input_line_pointer
= saved_char
;
26458 ignore_rest_of_line ();
26462 /* Parse a .object_arch directive. */
26465 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26467 const struct arm_arch_option_table
*opt
;
26471 name
= input_line_pointer
;
26472 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26473 input_line_pointer
++;
26474 saved_char
= *input_line_pointer
;
26475 *input_line_pointer
= 0;
26477 /* Skip the first "all" entry. */
26478 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26479 if (streq (opt
->name
, name
))
26481 object_arch
= &opt
->value
;
26482 *input_line_pointer
= saved_char
;
26483 demand_empty_rest_of_line ();
26487 as_bad (_("unknown architecture `%s'\n"), name
);
26488 *input_line_pointer
= saved_char
;
26489 ignore_rest_of_line ();
26492 /* Parse a .arch_extension directive. */
26495 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26497 const struct arm_option_extension_value_table
*opt
;
26498 const arm_feature_set arm_any
= ARM_ANY
;
26501 int adding_value
= 1;
26503 name
= input_line_pointer
;
26504 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26505 input_line_pointer
++;
26506 saved_char
= *input_line_pointer
;
26507 *input_line_pointer
= 0;
26509 if (strlen (name
) >= 2
26510 && strncmp (name
, "no", 2) == 0)
26516 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26517 if (streq (opt
->name
, name
))
26519 int i
, nb_allowed_archs
=
26520 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26521 for (i
= 0; i
< nb_allowed_archs
; i
++)
26524 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26526 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26530 if (i
== nb_allowed_archs
)
26532 as_bad (_("architectural extension `%s' is not allowed for the "
26533 "current base architecture"), name
);
26538 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26541 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26543 mcpu_cpu_opt
= &selected_cpu
;
26544 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26545 *input_line_pointer
= saved_char
;
26546 demand_empty_rest_of_line ();
26550 if (opt
->name
== NULL
)
26551 as_bad (_("unknown architecture extension `%s'\n"), name
);
26553 *input_line_pointer
= saved_char
;
26554 ignore_rest_of_line ();
26557 /* Parse a .fpu directive. */
26560 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26562 const struct arm_option_fpu_value_table
*opt
;
26566 name
= input_line_pointer
;
26567 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26568 input_line_pointer
++;
26569 saved_char
= *input_line_pointer
;
26570 *input_line_pointer
= 0;
26572 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26573 if (streq (opt
->name
, name
))
26575 mfpu_opt
= &opt
->value
;
26576 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26577 *input_line_pointer
= saved_char
;
26578 demand_empty_rest_of_line ();
26582 as_bad (_("unknown floating point format `%s'\n"), name
);
26583 *input_line_pointer
= saved_char
;
26584 ignore_rest_of_line ();
26587 /* Copy symbol information. */
26590 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26592 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26596 /* Given a symbolic attribute NAME, return the proper integer value.
26597 Returns -1 if the attribute is not known. */
26600 arm_convert_symbolic_attribute (const char *name
)
26602 static const struct
26607 attribute_table
[] =
26609 /* When you modify this table you should
26610 also modify the list in doc/c-arm.texi. */
26611 #define T(tag) {#tag, tag}
26612 T (Tag_CPU_raw_name
),
26615 T (Tag_CPU_arch_profile
),
26616 T (Tag_ARM_ISA_use
),
26617 T (Tag_THUMB_ISA_use
),
26621 T (Tag_Advanced_SIMD_arch
),
26622 T (Tag_PCS_config
),
26623 T (Tag_ABI_PCS_R9_use
),
26624 T (Tag_ABI_PCS_RW_data
),
26625 T (Tag_ABI_PCS_RO_data
),
26626 T (Tag_ABI_PCS_GOT_use
),
26627 T (Tag_ABI_PCS_wchar_t
),
26628 T (Tag_ABI_FP_rounding
),
26629 T (Tag_ABI_FP_denormal
),
26630 T (Tag_ABI_FP_exceptions
),
26631 T (Tag_ABI_FP_user_exceptions
),
26632 T (Tag_ABI_FP_number_model
),
26633 T (Tag_ABI_align_needed
),
26634 T (Tag_ABI_align8_needed
),
26635 T (Tag_ABI_align_preserved
),
26636 T (Tag_ABI_align8_preserved
),
26637 T (Tag_ABI_enum_size
),
26638 T (Tag_ABI_HardFP_use
),
26639 T (Tag_ABI_VFP_args
),
26640 T (Tag_ABI_WMMX_args
),
26641 T (Tag_ABI_optimization_goals
),
26642 T (Tag_ABI_FP_optimization_goals
),
26643 T (Tag_compatibility
),
26644 T (Tag_CPU_unaligned_access
),
26645 T (Tag_FP_HP_extension
),
26646 T (Tag_VFP_HP_extension
),
26647 T (Tag_ABI_FP_16bit_format
),
26648 T (Tag_MPextension_use
),
26650 T (Tag_nodefaults
),
26651 T (Tag_also_compatible_with
),
26652 T (Tag_conformance
),
26654 T (Tag_Virtualization_use
),
26655 T (Tag_DSP_extension
),
26656 /* We deliberately do not include Tag_MPextension_use_legacy. */
26664 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26665 if (streq (name
, attribute_table
[i
].name
))
26666 return attribute_table
[i
].tag
;
26672 /* Apply sym value for relocations only in the case that they are for
26673 local symbols in the same segment as the fixup and you have the
26674 respective architectural feature for blx and simple switches. */
26676 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26679 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26680 /* PR 17444: If the local symbol is in a different section then a reloc
26681 will always be generated for it, so applying the symbol value now
26682 will result in a double offset being stored in the relocation. */
26683 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26684 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26686 switch (fixP
->fx_r_type
)
26688 case BFD_RELOC_ARM_PCREL_BLX
:
26689 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26690 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26694 case BFD_RELOC_ARM_PCREL_CALL
:
26695 case BFD_RELOC_THUMB_PCREL_BLX
:
26696 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26707 #endif /* OBJ_ELF */