1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
237 static const arm_feature_set arm_ext_v8_3
=
238 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
240 static const arm_feature_set arm_arch_any
= ARM_ANY
;
241 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
242 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
243 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
245 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
248 static const arm_feature_set arm_cext_iwmmxt2
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
250 static const arm_feature_set arm_cext_iwmmxt
=
251 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
252 static const arm_feature_set arm_cext_xscale
=
253 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
254 static const arm_feature_set arm_cext_maverick
=
255 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
256 static const arm_feature_set fpu_fpa_ext_v1
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
258 static const arm_feature_set fpu_fpa_ext_v2
=
259 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
260 static const arm_feature_set fpu_vfp_ext_v1xd
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
262 static const arm_feature_set fpu_vfp_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
264 static const arm_feature_set fpu_vfp_ext_v2
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
266 static const arm_feature_set fpu_vfp_ext_v3xd
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
268 static const arm_feature_set fpu_vfp_ext_v3
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
270 static const arm_feature_set fpu_vfp_ext_d32
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
272 static const arm_feature_set fpu_neon_ext_v1
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
274 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
275 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
277 static const arm_feature_set fpu_vfp_fp16
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
279 static const arm_feature_set fpu_neon_ext_fma
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
284 static const arm_feature_set fpu_vfp_ext_armv8
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
286 static const arm_feature_set fpu_vfp_ext_armv8xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
288 static const arm_feature_set fpu_neon_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
290 static const arm_feature_set fpu_crypto_ext_armv8
=
291 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
292 static const arm_feature_set crc_ext_armv8
=
293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
294 static const arm_feature_set fpu_neon_ext_v8_1
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static int mfloat_abi_opt
= -1;
298 /* Record user cpu selection for object attributes. */
299 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
300 /* Must be long enough to hold any of the names in arm_cpus. */
301 static char selected_cpu_name
[20];
303 extern FLONUM_TYPE generic_floating_point_number
;
305 /* Return if no cpu was selected on command-line. */
307 no_cpu_selected (void)
309 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
314 static int meabi_flags
= EABI_DEFAULT
;
316 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
319 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
324 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
330 symbolS
* GOT_symbol
;
333 /* 0: assemble for ARM,
334 1: assemble for Thumb,
335 2: assemble for Thumb even though target CPU does not support thumb
337 static int thumb_mode
= 0;
338 /* A value distinct from the possible values for thumb_mode that we
339 can use to record whether thumb_mode has been copied into the
340 tc_frag_data field of a frag. */
341 #define MODE_RECORDED (1 << 4)
343 /* Specifies the intrinsic IT insn behavior mode. */
344 enum implicit_it_mode
346 IMPLICIT_IT_MODE_NEVER
= 0x00,
347 IMPLICIT_IT_MODE_ARM
= 0x01,
348 IMPLICIT_IT_MODE_THUMB
= 0x02,
349 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
351 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
353 /* If unified_syntax is true, we are processing the new unified
354 ARM/Thumb syntax. Important differences from the old ARM mode:
356 - Immediate operands do not require a # prefix.
357 - Conditional affixes always appear at the end of the
358 instruction. (For backward compatibility, those instructions
359 that formerly had them in the middle, continue to accept them
361 - The IT instruction may appear, and if it does is validated
362 against subsequent conditional affixes. It does not generate
365 Important differences from the old Thumb mode:
367 - Immediate operands do not require a # prefix.
368 - Most of the V6T2 instructions are only available in unified mode.
369 - The .N and .W suffixes are recognized and honored (it is an error
370 if they cannot be honored).
371 - All instructions set the flags if and only if they have an 's' affix.
372 - Conditional affixes may be used. They are validated against
373 preceding IT instructions. Unlike ARM mode, you cannot use a
374 conditional affix except in the scope of an IT instruction. */
376 static bfd_boolean unified_syntax
= FALSE
;
378 /* An immediate operand can start with #, and ld*, st*, pld operands
379 can contain [ and ]. We need to tell APP not to elide whitespace
380 before a [, which can appear as the first operand for pld.
381 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
382 const char arm_symbol_chars
[] = "#[]{}";
397 enum neon_el_type type
;
401 #define NEON_MAX_TYPE_ELS 4
405 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
409 enum it_instruction_type
414 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
415 if inside, should be the last one. */
416 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
417 i.e. BKPT and NOP. */
418 IT_INSN
/* The IT insn has been parsed. */
421 /* The maximum number of operands we need. */
422 #define ARM_IT_MAX_OPERANDS 6
427 unsigned long instruction
;
431 /* "uncond_value" is set to the value in place of the conditional field in
432 unconditional versions of the instruction, or -1 if nothing is
435 struct neon_type vectype
;
436 /* This does not indicate an actual NEON instruction, only that
437 the mnemonic accepts neon-style type suffixes. */
439 /* Set to the opcode if the instruction needs relaxation.
440 Zero if the instruction is not relaxed. */
444 bfd_reloc_code_real_type type
;
449 enum it_instruction_type it_insn_type
;
455 struct neon_type_el vectype
;
456 unsigned present
: 1; /* Operand present. */
457 unsigned isreg
: 1; /* Operand was a register. */
458 unsigned immisreg
: 1; /* .imm field is a second register. */
459 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
460 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
461 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
462 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 instructions. This allows us to disambiguate ARM <-> vector insns. */
464 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
465 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
466 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
467 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
468 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
469 unsigned writeback
: 1; /* Operand has trailing ! */
470 unsigned preind
: 1; /* Preindexed address. */
471 unsigned postind
: 1; /* Postindexed address. */
472 unsigned negative
: 1; /* Index register was negated. */
473 unsigned shifted
: 1; /* Shift applied to operation. */
474 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
475 } operands
[ARM_IT_MAX_OPERANDS
];
478 static struct arm_it inst
;
480 #define NUM_FLOAT_VALS 8
482 const char * fp_const
[] =
484 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
487 /* Number of littlenums required to hold an extended precision number. */
488 #define MAX_LITTLENUMS 6
490 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
500 #define CP_T_X 0x00008000
501 #define CP_T_Y 0x00400000
503 #define CONDS_BIT 0x00100000
504 #define LOAD_BIT 0x00100000
506 #define DOUBLE_LOAD_FLAG 0x00000001
510 const char * template_name
;
514 #define COND_ALWAYS 0xE
518 const char * template_name
;
522 struct asm_barrier_opt
524 const char * template_name
;
526 const arm_feature_set arch
;
529 /* The bit that distinguishes CPSR and SPSR. */
530 #define SPSR_BIT (1 << 22)
532 /* The individual PSR flag bits. */
533 #define PSR_c (1 << 16)
534 #define PSR_x (1 << 17)
535 #define PSR_s (1 << 18)
536 #define PSR_f (1 << 19)
541 bfd_reloc_code_real_type reloc
;
546 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
547 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
552 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
555 /* Bits for DEFINED field in neon_typed_alias. */
556 #define NTA_HASTYPE 1
557 #define NTA_HASINDEX 2
559 struct neon_typed_alias
561 unsigned char defined
;
563 struct neon_type_el eltype
;
566 /* ARM register categories. This includes coprocessor numbers and various
567 architecture extensions' registers. */
594 /* Structure for a hash table entry for a register.
595 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
596 information which states whether a vector type or index is specified (for a
597 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
603 unsigned char builtin
;
604 struct neon_typed_alias
* neon
;
607 /* Diagnostics used when we don't get a register of the expected type. */
608 const char * const reg_expected_msgs
[] =
610 N_("ARM register expected"),
611 N_("bad or missing co-processor number"),
612 N_("co-processor register expected"),
613 N_("FPA register expected"),
614 N_("VFP single precision register expected"),
615 N_("VFP/Neon double precision register expected"),
616 N_("Neon quad precision register expected"),
617 N_("VFP single or double precision register expected"),
618 N_("Neon double or quad precision register expected"),
619 N_("VFP single, double or Neon quad precision register expected"),
620 N_("VFP system register expected"),
621 N_("Maverick MVF register expected"),
622 N_("Maverick MVD register expected"),
623 N_("Maverick MVFX register expected"),
624 N_("Maverick MVDX register expected"),
625 N_("Maverick MVAX register expected"),
626 N_("Maverick DSPSC register expected"),
627 N_("iWMMXt data register expected"),
628 N_("iWMMXt control register expected"),
629 N_("iWMMXt scalar register expected"),
630 N_("XScale accumulator register expected"),
633 /* Some well known registers that we refer to directly elsewhere. */
639 /* ARM instructions take 4bytes in the object file, Thumb instructions
645 /* Basic string to match. */
646 const char * template_name
;
648 /* Parameters to instruction. */
649 unsigned int operands
[8];
651 /* Conditional tag - see opcode_lookup. */
652 unsigned int tag
: 4;
654 /* Basic instruction code. */
655 unsigned int avalue
: 28;
657 /* Thumb-format instruction code. */
660 /* Which architecture variant provides this instruction. */
661 const arm_feature_set
* avariant
;
662 const arm_feature_set
* tvariant
;
664 /* Function to call to encode instruction in ARM format. */
665 void (* aencode
) (void);
667 /* Function to call to encode instruction in Thumb format. */
668 void (* tencode
) (void);
671 /* Defines for various bits that we will want to toggle. */
672 #define INST_IMMEDIATE 0x02000000
673 #define OFFSET_REG 0x02000000
674 #define HWOFFSET_IMM 0x00400000
675 #define SHIFT_BY_REG 0x00000010
676 #define PRE_INDEX 0x01000000
677 #define INDEX_UP 0x00800000
678 #define WRITE_BACK 0x00200000
679 #define LDM_TYPE_2_OR_3 0x00400000
680 #define CPSI_MMOD 0x00020000
682 #define LITERAL_MASK 0xf000f000
683 #define OPCODE_MASK 0xfe1fffff
684 #define V4_STR_BIT 0x00000020
685 #define VLDR_VMOV_SAME 0x0040f000
687 #define T2_SUBS_PC_LR 0xf3de8f00
689 #define DATA_OP_SHIFT 21
690 #define SBIT_SHIFT 20
692 #define T2_OPCODE_MASK 0xfe1fffff
693 #define T2_DATA_OP_SHIFT 21
694 #define T2_SBIT_SHIFT 20
696 #define A_COND_MASK 0xf0000000
697 #define A_PUSH_POP_OP_MASK 0x0fff0000
699 /* Opcodes for pushing/poping registers to/from the stack. */
700 #define A1_OPCODE_PUSH 0x092d0000
701 #define A2_OPCODE_PUSH 0x052d0004
702 #define A2_OPCODE_POP 0x049d0004
704 /* Codes to distinguish the arithmetic instructions. */
715 #define OPCODE_CMP 10
716 #define OPCODE_CMN 11
717 #define OPCODE_ORR 12
718 #define OPCODE_MOV 13
719 #define OPCODE_BIC 14
720 #define OPCODE_MVN 15
722 #define T2_OPCODE_AND 0
723 #define T2_OPCODE_BIC 1
724 #define T2_OPCODE_ORR 2
725 #define T2_OPCODE_ORN 3
726 #define T2_OPCODE_EOR 4
727 #define T2_OPCODE_ADD 8
728 #define T2_OPCODE_ADC 10
729 #define T2_OPCODE_SBC 11
730 #define T2_OPCODE_SUB 13
731 #define T2_OPCODE_RSB 14
733 #define T_OPCODE_MUL 0x4340
734 #define T_OPCODE_TST 0x4200
735 #define T_OPCODE_CMN 0x42c0
736 #define T_OPCODE_NEG 0x4240
737 #define T_OPCODE_MVN 0x43c0
739 #define T_OPCODE_ADD_R3 0x1800
740 #define T_OPCODE_SUB_R3 0x1a00
741 #define T_OPCODE_ADD_HI 0x4400
742 #define T_OPCODE_ADD_ST 0xb000
743 #define T_OPCODE_SUB_ST 0xb080
744 #define T_OPCODE_ADD_SP 0xa800
745 #define T_OPCODE_ADD_PC 0xa000
746 #define T_OPCODE_ADD_I8 0x3000
747 #define T_OPCODE_SUB_I8 0x3800
748 #define T_OPCODE_ADD_I3 0x1c00
749 #define T_OPCODE_SUB_I3 0x1e00
751 #define T_OPCODE_ASR_R 0x4100
752 #define T_OPCODE_LSL_R 0x4080
753 #define T_OPCODE_LSR_R 0x40c0
754 #define T_OPCODE_ROR_R 0x41c0
755 #define T_OPCODE_ASR_I 0x1000
756 #define T_OPCODE_LSL_I 0x0000
757 #define T_OPCODE_LSR_I 0x0800
759 #define T_OPCODE_MOV_I8 0x2000
760 #define T_OPCODE_CMP_I8 0x2800
761 #define T_OPCODE_CMP_LR 0x4280
762 #define T_OPCODE_MOV_HR 0x4600
763 #define T_OPCODE_CMP_HR 0x4500
765 #define T_OPCODE_LDR_PC 0x4800
766 #define T_OPCODE_LDR_SP 0x9800
767 #define T_OPCODE_STR_SP 0x9000
768 #define T_OPCODE_LDR_IW 0x6800
769 #define T_OPCODE_STR_IW 0x6000
770 #define T_OPCODE_LDR_IH 0x8800
771 #define T_OPCODE_STR_IH 0x8000
772 #define T_OPCODE_LDR_IB 0x7800
773 #define T_OPCODE_STR_IB 0x7000
774 #define T_OPCODE_LDR_RW 0x5800
775 #define T_OPCODE_STR_RW 0x5000
776 #define T_OPCODE_LDR_RH 0x5a00
777 #define T_OPCODE_STR_RH 0x5200
778 #define T_OPCODE_LDR_RB 0x5c00
779 #define T_OPCODE_STR_RB 0x5400
781 #define T_OPCODE_PUSH 0xb400
782 #define T_OPCODE_POP 0xbc00
784 #define T_OPCODE_BRANCH 0xe000
786 #define THUMB_SIZE 2 /* Size of thumb instruction. */
787 #define THUMB_PP_PC_LR 0x0100
788 #define THUMB_LOAD_BIT 0x0800
789 #define THUMB2_LOAD_BIT 0x00100000
791 #define BAD_ARGS _("bad arguments to instruction")
792 #define BAD_SP _("r13 not allowed here")
793 #define BAD_PC _("r15 not allowed here")
794 #define BAD_COND _("instruction cannot be conditional")
795 #define BAD_OVERLAP _("registers may not be the same")
796 #define BAD_HIREG _("lo register required")
797 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
798 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
799 #define BAD_BRANCH _("branch must be last instruction in IT block")
800 #define BAD_NOT_IT _("instruction not allowed in IT block")
801 #define BAD_FPU _("selected FPU does not support instruction")
802 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
803 #define BAD_IT_COND _("incorrect condition in IT block")
804 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
805 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
806 #define BAD_PC_ADDRESSING \
807 _("cannot use register index with PC-relative addressing")
808 #define BAD_PC_WRITEBACK \
809 _("cannot use writeback with PC-relative addressing")
810 #define BAD_RANGE _("branch out of range")
811 #define BAD_FP16 _("selected processor does not support fp16 instruction")
812 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
813 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
815 static struct hash_control
* arm_ops_hsh
;
816 static struct hash_control
* arm_cond_hsh
;
817 static struct hash_control
* arm_shift_hsh
;
818 static struct hash_control
* arm_psr_hsh
;
819 static struct hash_control
* arm_v7m_psr_hsh
;
820 static struct hash_control
* arm_reg_hsh
;
821 static struct hash_control
* arm_reloc_hsh
;
822 static struct hash_control
* arm_barrier_opt_hsh
;
824 /* Stuff needed to resolve the label ambiguity
833 symbolS
* last_label_seen
;
834 static int label_is_thumb_function_name
= FALSE
;
836 /* Literal pool structure. Held on a per-section
837 and per-sub-section basis. */
839 #define MAX_LITERAL_POOL_SIZE 1024
840 typedef struct literal_pool
842 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
843 unsigned int next_free_entry
;
849 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
851 struct literal_pool
* next
;
852 unsigned int alignment
;
855 /* Pointer to a linked list of literal pools. */
856 literal_pool
* list_of_pools
= NULL
;
858 typedef enum asmfunc_states
861 WAITING_ASMFUNC_NAME
,
865 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
868 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
870 static struct current_it now_it
;
874 now_it_compatible (int cond
)
876 return (cond
& ~1) == (now_it
.cc
& ~1);
880 conditional_insn (void)
882 return inst
.cond
!= COND_ALWAYS
;
885 static int in_it_block (void);
887 static int handle_it_state (void);
889 static void force_automatic_it_block_close (void);
891 static void it_fsm_post_encode (void);
893 #define set_it_insn_type(type) \
896 inst.it_insn_type = type; \
897 if (handle_it_state () == FAIL) \
902 #define set_it_insn_type_nonvoid(type, failret) \
905 inst.it_insn_type = type; \
906 if (handle_it_state () == FAIL) \
911 #define set_it_insn_type_last() \
914 if (inst.cond == COND_ALWAYS) \
915 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
917 set_it_insn_type (INSIDE_IT_LAST_INSN); \
923 /* This array holds the chars that always start a comment. If the
924 pre-processor is disabled, these aren't very useful. */
925 char arm_comment_chars
[] = "@";
927 /* This array holds the chars that only start a comment at the beginning of
928 a line. If the line seems to have the form '# 123 filename'
929 .line and .file directives will appear in the pre-processed output. */
930 /* Note that input_file.c hand checks for '#' at the beginning of the
931 first line of the input file. This is because the compiler outputs
932 #NO_APP at the beginning of its output. */
933 /* Also note that comments like this one will always work. */
934 const char line_comment_chars
[] = "#";
936 char arm_line_separator_chars
[] = ";";
938 /* Chars that can be used to separate mant
939 from exp in floating point numbers. */
940 const char EXP_CHARS
[] = "eE";
942 /* Chars that mean this number is a floating point constant. */
946 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
948 /* Prefix characters that indicate the start of an immediate
950 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
952 /* Separator character handling. */
954 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
957 skip_past_char (char ** str
, char c
)
959 /* PR gas/14987: Allow for whitespace before the expected character. */
960 skip_whitespace (*str
);
971 #define skip_past_comma(str) skip_past_char (str, ',')
973 /* Arithmetic expressions (possibly involving symbols). */
975 /* Return TRUE if anything in the expression is a bignum. */
978 walk_no_bignums (symbolS
* sp
)
980 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
983 if (symbol_get_value_expression (sp
)->X_add_symbol
)
985 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
986 || (symbol_get_value_expression (sp
)->X_op_symbol
987 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
993 static int in_my_get_expression
= 0;
995 /* Third argument to my_get_expression. */
996 #define GE_NO_PREFIX 0
997 #define GE_IMM_PREFIX 1
998 #define GE_OPT_PREFIX 2
999 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1000 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1001 #define GE_OPT_PREFIX_BIG 3
1004 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1009 /* In unified syntax, all prefixes are optional. */
1011 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1014 switch (prefix_mode
)
1016 case GE_NO_PREFIX
: break;
1018 if (!is_immediate_prefix (**str
))
1020 inst
.error
= _("immediate expression requires a # prefix");
1026 case GE_OPT_PREFIX_BIG
:
1027 if (is_immediate_prefix (**str
))
1033 memset (ep
, 0, sizeof (expressionS
));
1035 save_in
= input_line_pointer
;
1036 input_line_pointer
= *str
;
1037 in_my_get_expression
= 1;
1038 seg
= expression (ep
);
1039 in_my_get_expression
= 0;
1041 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1043 /* We found a bad or missing expression in md_operand(). */
1044 *str
= input_line_pointer
;
1045 input_line_pointer
= save_in
;
1046 if (inst
.error
== NULL
)
1047 inst
.error
= (ep
->X_op
== O_absent
1048 ? _("missing expression") :_("bad expression"));
1053 if (seg
!= absolute_section
1054 && seg
!= text_section
1055 && seg
!= data_section
1056 && seg
!= bss_section
1057 && seg
!= undefined_section
)
1059 inst
.error
= _("bad segment");
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1068 /* Get rid of any bignums now, so that we don't generate an error for which
1069 we can't establish a line number later on. Big numbers are never valid
1070 in instructions, which is where this routine is always called. */
1071 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1072 && (ep
->X_op
== O_big
1073 || (ep
->X_add_symbol
1074 && (walk_no_bignums (ep
->X_add_symbol
)
1076 && walk_no_bignums (ep
->X_op_symbol
))))))
1078 inst
.error
= _("invalid constant");
1079 *str
= input_line_pointer
;
1080 input_line_pointer
= save_in
;
1084 *str
= input_line_pointer
;
1085 input_line_pointer
= save_in
;
1089 /* Turn a string in input_line_pointer into a floating point constant
1090 of type TYPE, and store the appropriate bytes in *LITP. The number
1091 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1092 returned, or NULL on OK.
1094 Note that fp constants aren't represent in the normal way on the ARM.
1095 In big endian mode, things are as expected. However, in little endian
1096 mode fp constants are big-endian word-wise, and little-endian byte-wise
1097 within the words. For example, (double) 1.1 in big endian mode is
1098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1099 the byte sequence 99 99 f1 3f 9a 99 99 99.
1101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1104 md_atof (int type
, char * litP
, int * sizeP
)
1107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1139 return _("Unrecognized or unsupported floating point constant");
1142 t
= atof_ieee (input_line_pointer
, type
, words
);
1144 input_line_pointer
= t
;
1145 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1147 if (target_big_endian
)
1149 for (i
= 0; i
< prec
; i
++)
1151 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1152 litP
+= sizeof (LITTLENUM_TYPE
);
1157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1158 for (i
= prec
- 1; i
>= 0; i
--)
1160 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1161 litP
+= sizeof (LITTLENUM_TYPE
);
1164 /* For a 4 byte float the order of elements in `words' is 1 0.
1165 For an 8 byte float the order is 1 0 3 2. */
1166 for (i
= 0; i
< prec
; i
+= 2)
1168 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1169 sizeof (LITTLENUM_TYPE
));
1170 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1171 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1172 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1179 /* We handle all bad expressions here, so that we can report the faulty
1180 instruction in the error message. */
1182 md_operand (expressionS
* exp
)
1184 if (in_my_get_expression
)
1185 exp
->X_op
= O_illegal
;
1188 /* Immediate values. */
1190 /* Generic immediate-value read function for use in directives.
1191 Accepts anything that 'expression' can fold to a constant.
1192 *val receives the number. */
1195 immediate_for_directive (int *val
)
1198 exp
.X_op
= O_illegal
;
1200 if (is_immediate_prefix (*input_line_pointer
))
1202 input_line_pointer
++;
1206 if (exp
.X_op
!= O_constant
)
1208 as_bad (_("expected #constant"));
1209 ignore_rest_of_line ();
1212 *val
= exp
.X_add_number
;
1217 /* Register parsing. */
1219 /* Generic register parser. CCP points to what should be the
1220 beginning of a register name. If it is indeed a valid register
1221 name, advance CCP over it and return the reg_entry structure;
1222 otherwise return NULL. Does not issue diagnostics. */
1224 static struct reg_entry
*
1225 arm_reg_parse_multi (char **ccp
)
1229 struct reg_entry
*reg
;
1231 skip_whitespace (start
);
1233 #ifdef REGISTER_PREFIX
1234 if (*start
!= REGISTER_PREFIX
)
1238 #ifdef OPTIONAL_REGISTER_PREFIX
1239 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1244 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1249 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1251 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1261 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1262 enum arm_reg_type type
)
1264 /* Alternative syntaxes are accepted for a few register classes. */
1271 /* Generic coprocessor register names are allowed for these. */
1272 if (reg
&& reg
->type
== REG_TYPE_CN
)
1277 /* For backward compatibility, a bare number is valid here. */
1279 unsigned long processor
= strtoul (start
, ccp
, 10);
1280 if (*ccp
!= start
&& processor
<= 15)
1285 case REG_TYPE_MMXWC
:
1286 /* WC includes WCG. ??? I'm not sure this is true for all
1287 instructions that take WC registers. */
1288 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1299 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1300 return value is the register number or FAIL. */
1303 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1306 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1309 /* Do not allow a scalar (reg+index) to parse as a register. */
1310 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1313 if (reg
&& reg
->type
== type
)
1316 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1323 /* Parse a Neon type specifier. *STR should point at the leading '.'
1324 character. Does no verification at this stage that the type fits the opcode
1331 Can all be legally parsed by this function.
1333 Fills in neon_type struct pointer with parsed information, and updates STR
1334 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1335 type, FAIL if not. */
1338 parse_neon_type (struct neon_type
*type
, char **str
)
1345 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1347 enum neon_el_type thistype
= NT_untyped
;
1348 unsigned thissize
= -1u;
1355 /* Just a size without an explicit type. */
1359 switch (TOLOWER (*ptr
))
1361 case 'i': thistype
= NT_integer
; break;
1362 case 'f': thistype
= NT_float
; break;
1363 case 'p': thistype
= NT_poly
; break;
1364 case 's': thistype
= NT_signed
; break;
1365 case 'u': thistype
= NT_unsigned
; break;
1367 thistype
= NT_float
;
1372 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1378 /* .f is an abbreviation for .f32. */
1379 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1384 thissize
= strtoul (ptr
, &ptr
, 10);
1386 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1389 as_bad (_("bad size %d in type specifier"), thissize
);
1397 type
->el
[type
->elems
].type
= thistype
;
1398 type
->el
[type
->elems
].size
= thissize
;
1403 /* Empty/missing type is not a successful parse. */
1404 if (type
->elems
== 0)
1412 /* Errors may be set multiple times during parsing or bit encoding
1413 (particularly in the Neon bits), but usually the earliest error which is set
1414 will be the most meaningful. Avoid overwriting it with later (cascading)
1415 errors by calling this function. */
1418 first_error (const char *err
)
1424 /* Parse a single type, e.g. ".s32", leading period included. */
1426 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1429 struct neon_type optype
;
1433 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1435 if (optype
.elems
== 1)
1436 *vectype
= optype
.el
[0];
1439 first_error (_("only one type should be specified for operand"));
1445 first_error (_("vector type expected"));
1457 /* Special meanings for indices (which have a range of 0-7), which will fit into
1460 #define NEON_ALL_LANES 15
1461 #define NEON_INTERLEAVE_LANES 14
1463 /* Parse either a register or a scalar, with an optional type. Return the
1464 register number, and optionally fill in the actual type of the register
1465 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1466 type/index information in *TYPEINFO. */
1469 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1470 enum arm_reg_type
*rtype
,
1471 struct neon_typed_alias
*typeinfo
)
1474 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1475 struct neon_typed_alias atype
;
1476 struct neon_type_el parsetype
;
1480 atype
.eltype
.type
= NT_invtype
;
1481 atype
.eltype
.size
= -1;
1483 /* Try alternate syntax for some types of register. Note these are mutually
1484 exclusive with the Neon syntax extensions. */
1487 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1495 /* Undo polymorphism when a set of register types may be accepted. */
1496 if ((type
== REG_TYPE_NDQ
1497 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1498 || (type
== REG_TYPE_VFSD
1499 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1500 || (type
== REG_TYPE_NSDQ
1501 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1502 || reg
->type
== REG_TYPE_NQ
))
1503 || (type
== REG_TYPE_MMXWC
1504 && (reg
->type
== REG_TYPE_MMXWCG
)))
1505 type
= (enum arm_reg_type
) reg
->type
;
1507 if (type
!= reg
->type
)
1513 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1515 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1517 first_error (_("can't redefine type for operand"));
1520 atype
.defined
|= NTA_HASTYPE
;
1521 atype
.eltype
= parsetype
;
1524 if (skip_past_char (&str
, '[') == SUCCESS
)
1526 if (type
!= REG_TYPE_VFD
)
1528 first_error (_("only D registers may be indexed"));
1532 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1534 first_error (_("can't change index for operand"));
1538 atype
.defined
|= NTA_HASINDEX
;
1540 if (skip_past_char (&str
, ']') == SUCCESS
)
1541 atype
.index
= NEON_ALL_LANES
;
1546 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1548 if (exp
.X_op
!= O_constant
)
1550 first_error (_("constant expression required"));
1554 if (skip_past_char (&str
, ']') == FAIL
)
1557 atype
.index
= exp
.X_add_number
;
1572 /* Like arm_reg_parse, but allow allow the following extra features:
1573 - If RTYPE is non-zero, return the (possibly restricted) type of the
1574 register (e.g. Neon double or quad reg when either has been requested).
1575 - If this is a Neon vector type with additional type information, fill
1576 in the struct pointed to by VECTYPE (if non-NULL).
1577 This function will fault on encountering a scalar. */
1580 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1581 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1583 struct neon_typed_alias atype
;
1585 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1590 /* Do not allow regname(... to parse as a register. */
1594 /* Do not allow a scalar (reg+index) to parse as a register. */
1595 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1597 first_error (_("register operand expected, but got scalar"));
1602 *vectype
= atype
.eltype
;
1609 #define NEON_SCALAR_REG(X) ((X) >> 4)
1610 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1612 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1613 have enough information to be able to do a good job bounds-checking. So, we
1614 just do easy checks here, and do further checks later. */
1617 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1621 struct neon_typed_alias atype
;
1623 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1625 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1628 if (atype
.index
== NEON_ALL_LANES
)
1630 first_error (_("scalar must have an index"));
1633 else if (atype
.index
>= 64 / elsize
)
1635 first_error (_("scalar index out of range"));
1640 *type
= atype
.eltype
;
1644 return reg
* 16 + atype
.index
;
1647 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1650 parse_reg_list (char ** strp
)
1652 char * str
= * strp
;
1656 /* We come back here if we get ranges concatenated by '+' or '|'. */
1659 skip_whitespace (str
);
1673 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1675 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1685 first_error (_("bad range in register list"));
1689 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1691 if (range
& (1 << i
))
1693 (_("Warning: duplicated register (r%d) in register list"),
1701 if (range
& (1 << reg
))
1702 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1704 else if (reg
<= cur_reg
)
1705 as_tsktsk (_("Warning: register range not in ascending order"));
1710 while (skip_past_comma (&str
) != FAIL
1711 || (in_range
= 1, *str
++ == '-'));
1714 if (skip_past_char (&str
, '}') == FAIL
)
1716 first_error (_("missing `}'"));
1724 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1727 if (exp
.X_op
== O_constant
)
1729 if (exp
.X_add_number
1730 != (exp
.X_add_number
& 0x0000ffff))
1732 inst
.error
= _("invalid register mask");
1736 if ((range
& exp
.X_add_number
) != 0)
1738 int regno
= range
& exp
.X_add_number
;
1741 regno
= (1 << regno
) - 1;
1743 (_("Warning: duplicated register (r%d) in register list"),
1747 range
|= exp
.X_add_number
;
1751 if (inst
.reloc
.type
!= 0)
1753 inst
.error
= _("expression too complex");
1757 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1758 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1759 inst
.reloc
.pc_rel
= 0;
1763 if (*str
== '|' || *str
== '+')
1769 while (another_range
);
1775 /* Types of registers in a list. */
1784 /* Parse a VFP register list. If the string is invalid return FAIL.
1785 Otherwise return the number of registers, and set PBASE to the first
1786 register. Parses registers of type ETYPE.
1787 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1788 - Q registers can be used to specify pairs of D registers
1789 - { } can be omitted from around a singleton register list
1790 FIXME: This is not implemented, as it would require backtracking in
1793 This could be done (the meaning isn't really ambiguous), but doesn't
1794 fit in well with the current parsing framework.
1795 - 32 D registers may be used (also true for VFPv3).
1796 FIXME: Types are ignored in these register lists, which is probably a
1800 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1805 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1809 unsigned long mask
= 0;
1812 if (skip_past_char (&str
, '{') == FAIL
)
1814 inst
.error
= _("expecting {");
1821 regtype
= REG_TYPE_VFS
;
1826 regtype
= REG_TYPE_VFD
;
1829 case REGLIST_NEON_D
:
1830 regtype
= REG_TYPE_NDQ
;
1834 if (etype
!= REGLIST_VFP_S
)
1836 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1841 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1844 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1851 base_reg
= max_regs
;
1855 int setmask
= 1, addregs
= 1;
1857 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1859 if (new_base
== FAIL
)
1861 first_error (_(reg_expected_msgs
[regtype
]));
1865 if (new_base
>= max_regs
)
1867 first_error (_("register out of range in list"));
1871 /* Note: a value of 2 * n is returned for the register Q<n>. */
1872 if (regtype
== REG_TYPE_NQ
)
1878 if (new_base
< base_reg
)
1879 base_reg
= new_base
;
1881 if (mask
& (setmask
<< new_base
))
1883 first_error (_("invalid register list"));
1887 if ((mask
>> new_base
) != 0 && ! warned
)
1889 as_tsktsk (_("register list not in ascending order"));
1893 mask
|= setmask
<< new_base
;
1896 if (*str
== '-') /* We have the start of a range expression */
1902 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1905 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1909 if (high_range
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 if (regtype
== REG_TYPE_NQ
)
1916 high_range
= high_range
+ 1;
1918 if (high_range
<= new_base
)
1920 inst
.error
= _("register range not in ascending order");
1924 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1926 if (mask
& (setmask
<< new_base
))
1928 inst
.error
= _("invalid register list");
1932 mask
|= setmask
<< new_base
;
1937 while (skip_past_comma (&str
) != FAIL
);
1941 /* Sanity check -- should have raised a parse error above. */
1942 if (count
== 0 || count
> max_regs
)
1947 /* Final test -- the registers must be consecutive. */
1949 for (i
= 0; i
< count
; i
++)
1951 if ((mask
& (1u << i
)) == 0)
1953 inst
.error
= _("non-contiguous register range");
1963 /* True if two alias types are the same. */
1966 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1974 if (a
->defined
!= b
->defined
)
1977 if ((a
->defined
& NTA_HASTYPE
) != 0
1978 && (a
->eltype
.type
!= b
->eltype
.type
1979 || a
->eltype
.size
!= b
->eltype
.size
))
1982 if ((a
->defined
& NTA_HASINDEX
) != 0
1983 && (a
->index
!= b
->index
))
1989 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1990 The base register is put in *PBASE.
1991 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1993 The register stride (minus one) is put in bit 4 of the return value.
1994 Bits [6:5] encode the list length (minus one).
1995 The type of the list elements is put in *ELTYPE, if non-NULL. */
1997 #define NEON_LANE(X) ((X) & 0xf)
1998 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1999 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2002 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2003 struct neon_type_el
*eltype
)
2010 int leading_brace
= 0;
2011 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2012 const char *const incr_error
= _("register stride must be 1 or 2");
2013 const char *const type_error
= _("mismatched element/structure types in list");
2014 struct neon_typed_alias firsttype
;
2015 firsttype
.defined
= 0;
2016 firsttype
.eltype
.type
= NT_invtype
;
2017 firsttype
.eltype
.size
= -1;
2018 firsttype
.index
= -1;
2020 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2025 struct neon_typed_alias atype
;
2026 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2030 first_error (_(reg_expected_msgs
[rtype
]));
2037 if (rtype
== REG_TYPE_NQ
)
2043 else if (reg_incr
== -1)
2045 reg_incr
= getreg
- base_reg
;
2046 if (reg_incr
< 1 || reg_incr
> 2)
2048 first_error (_(incr_error
));
2052 else if (getreg
!= base_reg
+ reg_incr
* count
)
2054 first_error (_(incr_error
));
2058 if (! neon_alias_types_same (&atype
, &firsttype
))
2060 first_error (_(type_error
));
2064 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2068 struct neon_typed_alias htype
;
2069 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2071 lane
= NEON_INTERLEAVE_LANES
;
2072 else if (lane
!= NEON_INTERLEAVE_LANES
)
2074 first_error (_(type_error
));
2079 else if (reg_incr
!= 1)
2081 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2085 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2088 first_error (_(reg_expected_msgs
[rtype
]));
2091 if (! neon_alias_types_same (&htype
, &firsttype
))
2093 first_error (_(type_error
));
2096 count
+= hireg
+ dregs
- getreg
;
2100 /* If we're using Q registers, we can't use [] or [n] syntax. */
2101 if (rtype
== REG_TYPE_NQ
)
2107 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2111 else if (lane
!= atype
.index
)
2113 first_error (_(type_error
));
2117 else if (lane
== -1)
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2128 /* No lane set by [x]. We must be interleaving structures. */
2130 lane
= NEON_INTERLEAVE_LANES
;
2133 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2134 || (count
> 1 && reg_incr
== -1))
2136 first_error (_("error parsing element/structure list"));
2140 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2142 first_error (_("expected }"));
2150 *eltype
= firsttype
.eltype
;
2155 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2158 /* Parse an explicit relocation suffix on an expression. This is
2159 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2160 arm_reloc_hsh contains no entries, so this function can only
2161 succeed if there is no () after the word. Returns -1 on error,
2162 BFD_RELOC_UNUSED if there wasn't any suffix. */
2165 parse_reloc (char **str
)
2167 struct reloc_entry
*r
;
2171 return BFD_RELOC_UNUSED
;
2176 while (*q
&& *q
!= ')' && *q
!= ',')
2181 if ((r
= (struct reloc_entry
*)
2182 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2189 /* Directives: register aliases. */
2191 static struct reg_entry
*
2192 insert_reg_alias (char *str
, unsigned number
, int type
)
2194 struct reg_entry
*new_reg
;
2197 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2199 if (new_reg
->builtin
)
2200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2202 /* Only warn about a redefinition if it's not defined as the
2204 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2205 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2210 name
= xstrdup (str
);
2211 new_reg
= XNEW (struct reg_entry
);
2213 new_reg
->name
= name
;
2214 new_reg
->number
= number
;
2215 new_reg
->type
= type
;
2216 new_reg
->builtin
= FALSE
;
2217 new_reg
->neon
= NULL
;
2219 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2226 insert_neon_reg_alias (char *str
, int number
, int type
,
2227 struct neon_typed_alias
*atype
)
2229 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2233 first_error (_("attempt to redefine typed alias"));
2239 reg
->neon
= XNEW (struct neon_typed_alias
);
2240 *reg
->neon
= *atype
;
2244 /* Look for the .req directive. This is of the form:
2246 new_register_name .req existing_register_name
2248 If we find one, or if it looks sufficiently like one that we want to
2249 handle any error here, return TRUE. Otherwise return FALSE. */
2252 create_register_alias (char * newname
, char *p
)
2254 struct reg_entry
*old
;
2255 char *oldname
, *nbuf
;
2258 /* The input scrubber ensures that whitespace after the mnemonic is
2259 collapsed to single spaces. */
2261 if (strncmp (oldname
, " .req ", 6) != 0)
2265 if (*oldname
== '\0')
2268 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2271 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2275 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2276 the desired alias name, and p points to its end. If not, then
2277 the desired alias name is in the global original_case_string. */
2278 #ifdef TC_CASE_SENSITIVE
2281 newname
= original_case_string
;
2282 nlen
= strlen (newname
);
2285 nbuf
= xmemdup0 (newname
, nlen
);
2287 /* Create aliases under the new name as stated; an all-lowercase
2288 version of the new name; and an all-uppercase version of the new
2290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2292 for (p
= nbuf
; *p
; p
++)
2295 if (strncmp (nbuf
, newname
, nlen
))
2297 /* If this attempt to create an additional alias fails, do not bother
2298 trying to create the all-lower case alias. We will fail and issue
2299 a second, duplicate error message. This situation arises when the
2300 programmer does something like:
2303 The second .req creates the "Foo" alias but then fails to create
2304 the artificial FOO alias because it has already been created by the
2306 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2313 for (p
= nbuf
; *p
; p
++)
2316 if (strncmp (nbuf
, newname
, nlen
))
2317 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2324 /* Create a Neon typed/indexed register alias using directives, e.g.:
2329 These typed registers can be used instead of the types specified after the
2330 Neon mnemonic, so long as all operands given have types. Types can also be
2331 specified directly, e.g.:
2332 vadd d0.s32, d1.s32, d2.s32 */
2335 create_neon_reg_alias (char *newname
, char *p
)
2337 enum arm_reg_type basetype
;
2338 struct reg_entry
*basereg
;
2339 struct reg_entry mybasereg
;
2340 struct neon_type ntype
;
2341 struct neon_typed_alias typeinfo
;
2342 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2345 typeinfo
.defined
= 0;
2346 typeinfo
.eltype
.type
= NT_invtype
;
2347 typeinfo
.eltype
.size
= -1;
2348 typeinfo
.index
= -1;
2352 if (strncmp (p
, " .dn ", 5) == 0)
2353 basetype
= REG_TYPE_VFD
;
2354 else if (strncmp (p
, " .qn ", 5) == 0)
2355 basetype
= REG_TYPE_NQ
;
2364 basereg
= arm_reg_parse_multi (&p
);
2366 if (basereg
&& basereg
->type
!= basetype
)
2368 as_bad (_("bad type for register"));
2372 if (basereg
== NULL
)
2375 /* Try parsing as an integer. */
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2377 if (exp
.X_op
!= O_constant
)
2379 as_bad (_("expression must be constant"));
2382 basereg
= &mybasereg
;
2383 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2389 typeinfo
= *basereg
->neon
;
2391 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2393 /* We got a type. */
2394 if (typeinfo
.defined
& NTA_HASTYPE
)
2396 as_bad (_("can't redefine the type of a register alias"));
2400 typeinfo
.defined
|= NTA_HASTYPE
;
2401 if (ntype
.elems
!= 1)
2403 as_bad (_("you must specify a single type only"));
2406 typeinfo
.eltype
= ntype
.el
[0];
2409 if (skip_past_char (&p
, '[') == SUCCESS
)
2412 /* We got a scalar index. */
2414 if (typeinfo
.defined
& NTA_HASINDEX
)
2416 as_bad (_("can't redefine the index of a scalar alias"));
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2422 if (exp
.X_op
!= O_constant
)
2424 as_bad (_("scalar index must be constant"));
2428 typeinfo
.defined
|= NTA_HASINDEX
;
2429 typeinfo
.index
= exp
.X_add_number
;
2431 if (skip_past_char (&p
, ']') == FAIL
)
2433 as_bad (_("expecting ]"));
2438 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2439 the desired alias name, and p points to its end. If not, then
2440 the desired alias name is in the global original_case_string. */
2441 #ifdef TC_CASE_SENSITIVE
2442 namelen
= nameend
- newname
;
2444 newname
= original_case_string
;
2445 namelen
= strlen (newname
);
2448 namebuf
= xmemdup0 (newname
, namelen
);
2450 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2451 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Insert name in all uppercase. */
2454 for (p
= namebuf
; *p
; p
++)
2457 if (strncmp (namebuf
, newname
, namelen
))
2458 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2459 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2461 /* Insert name in all lowercase. */
2462 for (p
= namebuf
; *p
; p
++)
2465 if (strncmp (namebuf
, newname
, namelen
))
2466 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2467 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2473 /* Should never be called, as .req goes between the alias and the
2474 register name, not at the beginning of the line. */
2477 s_req (int a ATTRIBUTE_UNUSED
)
2479 as_bad (_("invalid syntax for .req directive"));
2483 s_dn (int a ATTRIBUTE_UNUSED
)
2485 as_bad (_("invalid syntax for .dn directive"));
2489 s_qn (int a ATTRIBUTE_UNUSED
)
2491 as_bad (_("invalid syntax for .qn directive"));
2494 /* The .unreq directive deletes an alias which was previously defined
2495 by .req. For example:
2501 s_unreq (int a ATTRIBUTE_UNUSED
)
2506 name
= input_line_pointer
;
2508 while (*input_line_pointer
!= 0
2509 && *input_line_pointer
!= ' '
2510 && *input_line_pointer
!= '\n')
2511 ++input_line_pointer
;
2513 saved_char
= *input_line_pointer
;
2514 *input_line_pointer
= 0;
2517 as_bad (_("invalid syntax for .unreq directive"));
2520 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2524 as_bad (_("unknown register alias '%s'"), name
);
2525 else if (reg
->builtin
)
2526 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2533 hash_delete (arm_reg_hsh
, name
, FALSE
);
2534 free ((char *) reg
->name
);
2539 /* Also locate the all upper case and all lower case versions.
2540 Do not complain if we cannot find one or the other as it
2541 was probably deleted above. */
2543 nbuf
= strdup (name
);
2544 for (p
= nbuf
; *p
; p
++)
2546 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2549 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2550 free ((char *) reg
->name
);
2556 for (p
= nbuf
; *p
; p
++)
2558 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2561 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2562 free ((char *) reg
->name
);
2572 *input_line_pointer
= saved_char
;
2573 demand_empty_rest_of_line ();
2576 /* Directives: Instruction set selection. */
2579 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2580 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2581 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2582 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2584 /* Create a new mapping symbol for the transition to STATE. */
2587 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2590 const char * symname
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2605 type
= BSF_NO_FLAGS
;
2611 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2612 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2617 THUMB_SET_FUNC (symbolP
, 0);
2618 ARM_SET_THUMB (symbolP
, 0);
2619 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2623 THUMB_SET_FUNC (symbolP
, 1);
2624 ARM_SET_THUMB (symbolP
, 1);
2625 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2633 /* Save the mapping symbols for future reference. Also check that
2634 we do not place two mapping symbols at the same offset within a
2635 frag. We'll handle overlap between frags in
2636 check_mapping_symbols.
2638 If .fill or other data filling directive generates zero sized data,
2639 the mapping symbol for the following code will have the same value
2640 as the one generated for the data filling directive. In this case,
2641 we replace the old symbol with the new one at the same address. */
2644 if (frag
->tc_frag_data
.first_map
!= NULL
)
2646 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2647 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2649 frag
->tc_frag_data
.first_map
= symbolP
;
2651 if (frag
->tc_frag_data
.last_map
!= NULL
)
2653 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2654 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2655 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2657 frag
->tc_frag_data
.last_map
= symbolP
;
2660 /* We must sometimes convert a region marked as code to data during
2661 code alignment, if an odd number of bytes have to be padded. The
2662 code mapping symbol is pushed to an aligned address. */
2665 insert_data_mapping_symbol (enum mstate state
,
2666 valueT value
, fragS
*frag
, offsetT bytes
)
2668 /* If there was already a mapping symbol, remove it. */
2669 if (frag
->tc_frag_data
.last_map
!= NULL
2670 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2672 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2676 know (frag
->tc_frag_data
.first_map
== symp
);
2677 frag
->tc_frag_data
.first_map
= NULL
;
2679 frag
->tc_frag_data
.last_map
= NULL
;
2680 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2683 make_mapping_symbol (MAP_DATA
, value
, frag
);
2684 make_mapping_symbol (state
, value
+ bytes
, frag
);
2687 static void mapping_state_2 (enum mstate state
, int max_chars
);
2689 /* Set the mapping state to STATE. Only call this when about to
2690 emit some STATE bytes to the file. */
2692 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2694 mapping_state (enum mstate state
)
2696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2698 if (mapstate
== state
)
2699 /* The mapping symbol has already been emitted.
2700 There is nothing else to do. */
2703 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2705 All ARM instructions require 4-byte alignment.
2706 (Almost) all Thumb instructions require 2-byte alignment.
2708 When emitting instructions into any section, mark the section
2711 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2712 but themselves require 2-byte alignment; this applies to some
2713 PC- relative forms. However, these cases will invovle implicit
2714 literal pool generation or an explicit .align >=2, both of
2715 which will cause the section to me marked with sufficient
2716 alignment. Thus, we don't handle those cases here. */
2717 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2719 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2720 /* This case will be evaluated later. */
2723 mapping_state_2 (state
, 0);
2726 /* Same as mapping_state, but MAX_CHARS bytes have already been
2727 allocated. Put the mapping symbol that far back. */
2730 mapping_state_2 (enum mstate state
, int max_chars
)
2732 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2734 if (!SEG_NORMAL (now_seg
))
2737 if (mapstate
== state
)
2738 /* The mapping symbol has already been emitted.
2739 There is nothing else to do. */
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2743 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2745 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2746 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2749 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2752 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2753 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2757 #define mapping_state(x) ((void)0)
2758 #define mapping_state_2(x, y) ((void)0)
2761 /* Find the real, Thumb encoded start of a Thumb function. */
2765 find_real_start (symbolS
* symbolP
)
2768 const char * name
= S_GET_NAME (symbolP
);
2769 symbolS
* new_target
;
2771 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2772 #define STUB_NAME ".real_start_of"
2777 /* The compiler may generate BL instructions to local labels because
2778 it needs to perform a branch to a far away location. These labels
2779 do not have a corresponding ".real_start_of" label. We check
2780 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2781 the ".real_start_of" convention for nonlocal branches. */
2782 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2785 real_start
= concat (STUB_NAME
, name
, NULL
);
2786 new_target
= symbol_find (real_start
);
2789 if (new_target
== NULL
)
2791 as_warn (_("Failed to find real start of function: %s\n"), name
);
2792 new_target
= symbolP
;
2800 opcode_select (int width
)
2807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2808 as_bad (_("selected processor does not support THUMB opcodes"));
2811 /* No need to force the alignment, since we will have been
2812 coming from ARM mode, which is word-aligned. */
2813 record_alignment (now_seg
, 1);
2820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2821 as_bad (_("selected processor does not support ARM opcodes"));
2826 frag_align (2, 0, 0);
2828 record_alignment (now_seg
, 1);
2833 as_bad (_("invalid instruction size selected (%d)"), width
);
2838 s_arm (int ignore ATTRIBUTE_UNUSED
)
2841 demand_empty_rest_of_line ();
2845 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 demand_empty_rest_of_line ();
2852 s_code (int unused ATTRIBUTE_UNUSED
)
2856 temp
= get_absolute_expression ();
2861 opcode_select (temp
);
2865 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2870 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2872 /* If we are not already in thumb mode go into it, EVEN if
2873 the target processor does not support thumb instructions.
2874 This is used by gcc/config/arm/lib1funcs.asm for example
2875 to compile interworking support functions even if the
2876 target processor should not support interworking. */
2880 record_alignment (now_seg
, 1);
2883 demand_empty_rest_of_line ();
2887 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2891 /* The following label is the name/address of the start of a Thumb function.
2892 We need to know this for the interworking support. */
2893 label_is_thumb_function_name
= TRUE
;
2896 /* Perform a .set directive, but also mark the alias as
2897 being a thumb function. */
2900 s_thumb_set (int equiv
)
2902 /* XXX the following is a duplicate of the code for s_set() in read.c
2903 We cannot just call that code as we need to get at the symbol that
2910 /* Especial apologies for the random logic:
2911 This just grew, and could be parsed much more simply!
2913 delim
= get_symbol_name (& name
);
2914 end_name
= input_line_pointer
;
2915 (void) restore_line_pointer (delim
);
2917 if (*input_line_pointer
!= ',')
2920 as_bad (_("expected comma after name \"%s\""), name
);
2922 ignore_rest_of_line ();
2926 input_line_pointer
++;
2929 if (name
[0] == '.' && name
[1] == '\0')
2931 /* XXX - this should not happen to .thumb_set. */
2935 if ((symbolP
= symbol_find (name
)) == NULL
2936 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2939 /* When doing symbol listings, play games with dummy fragments living
2940 outside the normal fragment chain to record the file and line info
2942 if (listing
& LISTING_SYMBOLS
)
2944 extern struct list_info_struct
* listing_tail
;
2945 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2947 memset (dummy_frag
, 0, sizeof (fragS
));
2948 dummy_frag
->fr_type
= rs_fill
;
2949 dummy_frag
->line
= listing_tail
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2951 dummy_frag
->fr_symbol
= symbolP
;
2955 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2958 /* "set" symbols are local unless otherwise specified. */
2959 SF_SET_LOCAL (symbolP
);
2960 #endif /* OBJ_COFF */
2961 } /* Make a new symbol. */
2963 symbol_table_insert (symbolP
);
2968 && S_IS_DEFINED (symbolP
)
2969 && S_GET_SEGMENT (symbolP
) != reg_section
)
2970 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2972 pseudo_set (symbolP
);
2974 demand_empty_rest_of_line ();
2976 /* XXX Now we come to the Thumb specific bit of code. */
2978 THUMB_SET_FUNC (symbolP
, 1);
2979 ARM_SET_THUMB (symbolP
, 1);
2980 #if defined OBJ_ELF || defined OBJ_COFF
2981 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2985 /* Directives: Mode selection. */
2987 /* .syntax [unified|divided] - choose the new unified syntax
2988 (same for Arm and Thumb encoding, modulo slight differences in what
2989 can be represented) or the old divergent syntax for each mode. */
2991 s_syntax (int unused ATTRIBUTE_UNUSED
)
2995 delim
= get_symbol_name (& name
);
2997 if (!strcasecmp (name
, "unified"))
2998 unified_syntax
= TRUE
;
2999 else if (!strcasecmp (name
, "divided"))
3000 unified_syntax
= FALSE
;
3003 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3006 (void) restore_line_pointer (delim
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: sectioning and alignment. */
3013 s_bss (int ignore ATTRIBUTE_UNUSED
)
3015 /* We don't support putting frags in the BSS segment, we fake it by
3016 marking in_bss, then looking at s_skip for clues. */
3017 subseg_set (bss_section
, 0);
3018 demand_empty_rest_of_line ();
3020 #ifdef md_elf_section_change_hook
3021 md_elf_section_change_hook ();
3026 s_even (int ignore ATTRIBUTE_UNUSED
)
3028 /* Never make frag if expect extra pass. */
3030 frag_align (1, 0, 0);
3032 record_alignment (now_seg
, 1);
3034 demand_empty_rest_of_line ();
3037 /* Directives: CodeComposer Studio. */
3039 /* .ref (for CodeComposer Studio syntax only). */
3041 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3043 if (codecomposer_syntax
)
3044 ignore_rest_of_line ();
3046 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3049 /* If name is not NULL, then it is used for marking the beginning of a
3050 function, whereas if it is NULL then it means the function end. */
3052 asmfunc_debug (const char * name
)
3054 static const char * last_name
= NULL
;
3058 gas_assert (last_name
== NULL
);
3061 if (debug_type
== DEBUG_STABS
)
3062 stabs_generate_asm_func (name
, name
);
3066 gas_assert (last_name
!= NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_endfunc (last_name
, last_name
);
3076 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3078 if (codecomposer_syntax
)
3080 switch (asmfunc_state
)
3082 case OUTSIDE_ASMFUNC
:
3083 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3086 case WAITING_ASMFUNC_NAME
:
3087 as_bad (_(".asmfunc repeated."));
3090 case WAITING_ENDASMFUNC
:
3091 as_bad (_(".asmfunc without function."));
3094 demand_empty_rest_of_line ();
3097 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3101 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3103 if (codecomposer_syntax
)
3105 switch (asmfunc_state
)
3107 case OUTSIDE_ASMFUNC
:
3108 as_bad (_(".endasmfunc without a .asmfunc."));
3111 case WAITING_ASMFUNC_NAME
:
3112 as_bad (_(".endasmfunc without function."));
3115 case WAITING_ENDASMFUNC
:
3116 asmfunc_state
= OUTSIDE_ASMFUNC
;
3117 asmfunc_debug (NULL
);
3120 demand_empty_rest_of_line ();
3123 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3127 s_ccs_def (int name
)
3129 if (codecomposer_syntax
)
3132 as_bad (_(".def pseudo-op only available with -mccs flag."));
3135 /* Directives: Literal pools. */
3137 static literal_pool
*
3138 find_literal_pool (void)
3140 literal_pool
* pool
;
3142 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3144 if (pool
->section
== now_seg
3145 && pool
->sub_section
== now_subseg
)
3152 static literal_pool
*
3153 find_or_make_literal_pool (void)
3155 /* Next literal pool ID number. */
3156 static unsigned int latest_pool_num
= 1;
3157 literal_pool
* pool
;
3159 pool
= find_literal_pool ();
3163 /* Create a new pool. */
3164 pool
= XNEW (literal_pool
);
3168 pool
->next_free_entry
= 0;
3169 pool
->section
= now_seg
;
3170 pool
->sub_section
= now_subseg
;
3171 pool
->next
= list_of_pools
;
3172 pool
->symbol
= NULL
;
3173 pool
->alignment
= 2;
3175 /* Add it to the list. */
3176 list_of_pools
= pool
;
3179 /* New pools, and emptied pools, will have a NULL symbol. */
3180 if (pool
->symbol
== NULL
)
3182 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3183 (valueT
) 0, &zero_address_frag
);
3184 pool
->id
= latest_pool_num
++;
3191 /* Add the literal in the global 'inst'
3192 structure to the relevant literal pool. */
3195 add_to_lit_pool (unsigned int nbytes
)
3197 #define PADDING_SLOT 0x1
3198 #define LIT_ENTRY_SIZE_MASK 0xFF
3199 literal_pool
* pool
;
3200 unsigned int entry
, pool_size
= 0;
3201 bfd_boolean padding_slot_p
= FALSE
;
3207 imm1
= inst
.operands
[1].imm
;
3208 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3209 : inst
.reloc
.exp
.X_unsigned
? 0
3210 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3211 if (target_big_endian
)
3214 imm2
= inst
.operands
[1].imm
;
3218 pool
= find_or_make_literal_pool ();
3220 /* Check if this literal value is already in the pool. */
3221 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_constant
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_md
== nbytes
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3235 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3236 && (pool
->literals
[entry
].X_add_number
3237 == inst
.reloc
.exp
.X_add_number
)
3238 && (pool
->literals
[entry
].X_add_symbol
3239 == inst
.reloc
.exp
.X_add_symbol
)
3240 && (pool
->literals
[entry
].X_op_symbol
3241 == inst
.reloc
.exp
.X_op_symbol
)
3242 && (pool
->literals
[entry
].X_md
== nbytes
))
3245 else if ((nbytes
== 8)
3246 && !(pool_size
& 0x7)
3247 && ((entry
+ 1) != pool
->next_free_entry
)
3248 && (pool
->literals
[entry
].X_op
== O_constant
)
3249 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3250 && (pool
->literals
[entry
].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
)
3252 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3253 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3254 && (pool
->literals
[entry
+ 1].X_unsigned
3255 == inst
.reloc
.exp
.X_unsigned
))
3258 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3259 if (padding_slot_p
&& (nbytes
== 4))
3265 /* Do we need to create a new entry? */
3266 if (entry
== pool
->next_free_entry
)
3268 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3270 inst
.error
= _("literal pool overflow");
3276 /* For 8-byte entries, we align to an 8-byte boundary,
3277 and split it into two 4-byte entries, because on 32-bit
3278 host, 8-byte constants are treated as big num, thus
3279 saved in "generic_bignum" which will be overwritten
3280 by later assignments.
3282 We also need to make sure there is enough space for
3285 We also check to make sure the literal operand is a
3287 if (!(inst
.reloc
.exp
.X_op
== O_constant
3288 || inst
.reloc
.exp
.X_op
== O_big
))
3290 inst
.error
= _("invalid type for literal pool");
3293 else if (pool_size
& 0x7)
3295 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3297 inst
.error
= _("literal pool overflow");
3301 pool
->literals
[entry
] = inst
.reloc
.exp
;
3302 pool
->literals
[entry
].X_op
= O_constant
;
3303 pool
->literals
[entry
].X_add_number
= 0;
3304 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3305 pool
->next_free_entry
+= 1;
3308 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm1
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
++].X_md
= 4;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= imm2
;
3322 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3323 pool
->literals
[entry
].X_md
= 4;
3324 pool
->alignment
= 3;
3325 pool
->next_free_entry
+= 1;
3329 pool
->literals
[entry
] = inst
.reloc
.exp
;
3330 pool
->literals
[entry
].X_md
= 4;
3334 /* PR ld/12974: Record the location of the first source line to reference
3335 this entry in the literal pool. If it turns out during linking that the
3336 symbol does not exist we will be able to give an accurate line number for
3337 the (first use of the) missing reference. */
3338 if (debug_type
== DEBUG_DWARF2
)
3339 dwarf2_where (pool
->locs
+ entry
);
3341 pool
->next_free_entry
+= 1;
3343 else if (padding_slot_p
)
3345 pool
->literals
[entry
] = inst
.reloc
.exp
;
3346 pool
->literals
[entry
].X_md
= nbytes
;
3349 inst
.reloc
.exp
.X_op
= O_symbol
;
3350 inst
.reloc
.exp
.X_add_number
= pool_size
;
3351 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3357 tc_start_label_without_colon (void)
3359 bfd_boolean ret
= TRUE
;
3361 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3363 const char *label
= input_line_pointer
;
3365 while (!is_end_of_line
[(int) label
[-1]])
3370 as_bad (_("Invalid label '%s'"), label
);
3374 asmfunc_debug (label
);
3376 asmfunc_state
= WAITING_ENDASMFUNC
;
3382 /* Can't use symbol_new here, so have to create a symbol and then at
3383 a later date assign it a value. Thats what these functions do. */
3386 symbol_locate (symbolS
* symbolP
,
3387 const char * name
, /* It is copied, the caller can modify. */
3388 segT segment
, /* Segment identifier (SEG_<something>). */
3389 valueT valu
, /* Symbol value. */
3390 fragS
* frag
) /* Associated fragment. */
3393 char * preserved_copy_of_name
;
3395 name_length
= strlen (name
) + 1; /* +1 for \0. */
3396 obstack_grow (¬es
, name
, name_length
);
3397 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3399 #ifdef tc_canonicalize_symbol_name
3400 preserved_copy_of_name
=
3401 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3404 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3406 S_SET_SEGMENT (symbolP
, segment
);
3407 S_SET_VALUE (symbolP
, valu
);
3408 symbol_clear_list_pointers (symbolP
);
3410 symbol_set_frag (symbolP
, frag
);
3412 /* Link to end of symbol chain. */
3414 extern int symbol_table_frozen
;
3416 if (symbol_table_frozen
)
3420 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3422 obj_symbol_new_hook (symbolP
);
3424 #ifdef tc_symbol_new_hook
3425 tc_symbol_new_hook (symbolP
);
3429 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3430 #endif /* DEBUG_SYMS */
3434 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3437 literal_pool
* pool
;
3440 pool
= find_literal_pool ();
3442 || pool
->symbol
== NULL
3443 || pool
->next_free_entry
== 0)
3446 /* Align pool as you have word accesses.
3447 Only make a frag if we have to. */
3449 frag_align (pool
->alignment
, 0, 0);
3451 record_alignment (now_seg
, 2);
3454 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3455 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3457 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3459 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3460 (valueT
) frag_now_fix (), frag_now
);
3461 symbol_table_insert (pool
->symbol
);
3463 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3465 #if defined OBJ_COFF || defined OBJ_ELF
3466 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3469 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3472 if (debug_type
== DEBUG_DWARF2
)
3473 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3475 /* First output the expression in the instruction to the pool. */
3476 emit_expr (&(pool
->literals
[entry
]),
3477 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3480 /* Mark the pool as empty. */
3481 pool
->next_free_entry
= 0;
3482 pool
->symbol
= NULL
;
3486 /* Forward declarations for functions below, in the MD interface
3488 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3489 static valueT
create_unwind_entry (int);
3490 static void start_unwind_section (const segT
, int);
3491 static void add_unwind_opcode (valueT
, int);
3492 static void flush_pending_unwind (void);
3494 /* Directives: Data. */
3497 s_arm_elf_cons (int nbytes
)
3501 #ifdef md_flush_pending_output
3502 md_flush_pending_output ();
3505 if (is_it_end_of_statement ())
3507 demand_empty_rest_of_line ();
3511 #ifdef md_cons_align
3512 md_cons_align (nbytes
);
3515 mapping_state (MAP_DATA
);
3519 char *base
= input_line_pointer
;
3523 if (exp
.X_op
!= O_symbol
)
3524 emit_expr (&exp
, (unsigned int) nbytes
);
3527 char *before_reloc
= input_line_pointer
;
3528 reloc
= parse_reloc (&input_line_pointer
);
3531 as_bad (_("unrecognized relocation suffix"));
3532 ignore_rest_of_line ();
3535 else if (reloc
== BFD_RELOC_UNUSED
)
3536 emit_expr (&exp
, (unsigned int) nbytes
);
3539 reloc_howto_type
*howto
= (reloc_howto_type
*)
3540 bfd_reloc_type_lookup (stdoutput
,
3541 (bfd_reloc_code_real_type
) reloc
);
3542 int size
= bfd_get_reloc_size (howto
);
3544 if (reloc
== BFD_RELOC_ARM_PLT32
)
3546 as_bad (_("(plt) is only valid on branch targets"));
3547 reloc
= BFD_RELOC_UNUSED
;
3552 as_bad (_("%s relocations do not fit in %d bytes"),
3553 howto
->name
, nbytes
);
3556 /* We've parsed an expression stopping at O_symbol.
3557 But there may be more expression left now that we
3558 have parsed the relocation marker. Parse it again.
3559 XXX Surely there is a cleaner way to do this. */
3560 char *p
= input_line_pointer
;
3562 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3564 memcpy (save_buf
, base
, input_line_pointer
- base
);
3565 memmove (base
+ (input_line_pointer
- before_reloc
),
3566 base
, before_reloc
- base
);
3568 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3570 memcpy (base
, save_buf
, p
- base
);
3572 offset
= nbytes
- size
;
3573 p
= frag_more (nbytes
);
3574 memset (p
, 0, nbytes
);
3575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3576 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3582 while (*input_line_pointer
++ == ',');
3584 /* Put terminator back into stream. */
3585 input_line_pointer
--;
3586 demand_empty_rest_of_line ();
3589 /* Emit an expression containing a 32-bit thumb instruction.
3590 Implementation based on put_thumb32_insn. */
3593 emit_thumb32_expr (expressionS
* exp
)
3595 expressionS exp_high
= *exp
;
3597 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3598 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3599 exp
->X_add_number
&= 0xffff;
3600 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3603 /* Guess the instruction size based on the opcode. */
3606 thumb_insn_size (int opcode
)
3608 if ((unsigned int) opcode
< 0xe800u
)
3610 else if ((unsigned int) opcode
>= 0xe8000000u
)
3617 emit_insn (expressionS
*exp
, int nbytes
)
3621 if (exp
->X_op
== O_constant
)
3626 size
= thumb_insn_size (exp
->X_add_number
);
3630 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3632 as_bad (_(".inst.n operand too big. "\
3633 "Use .inst.w instead"));
3638 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3639 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3641 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3643 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3644 emit_thumb32_expr (exp
);
3646 emit_expr (exp
, (unsigned int) size
);
3648 it_fsm_post_encode ();
3652 as_bad (_("cannot determine Thumb instruction size. " \
3653 "Use .inst.n/.inst.w instead"));
3656 as_bad (_("constant expression required"));
3661 /* Like s_arm_elf_cons but do not use md_cons_align and
3662 set the mapping state to MAP_ARM/MAP_THUMB. */
3665 s_arm_elf_inst (int nbytes
)
3667 if (is_it_end_of_statement ())
3669 demand_empty_rest_of_line ();
3673 /* Calling mapping_state () here will not change ARM/THUMB,
3674 but will ensure not to be in DATA state. */
3677 mapping_state (MAP_THUMB
);
3682 as_bad (_("width suffixes are invalid in ARM mode"));
3683 ignore_rest_of_line ();
3689 mapping_state (MAP_ARM
);
3698 if (! emit_insn (& exp
, nbytes
))
3700 ignore_rest_of_line ();
3704 while (*input_line_pointer
++ == ',');
3706 /* Put terminator back into stream. */
3707 input_line_pointer
--;
3708 demand_empty_rest_of_line ();
3711 /* Parse a .rel31 directive. */
3714 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3721 if (*input_line_pointer
== '1')
3722 highbit
= 0x80000000;
3723 else if (*input_line_pointer
!= '0')
3724 as_bad (_("expected 0 or 1"));
3726 input_line_pointer
++;
3727 if (*input_line_pointer
!= ',')
3728 as_bad (_("missing comma"));
3729 input_line_pointer
++;
3731 #ifdef md_flush_pending_output
3732 md_flush_pending_output ();
3735 #ifdef md_cons_align
3739 mapping_state (MAP_DATA
);
3744 md_number_to_chars (p
, highbit
, 4);
3745 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3746 BFD_RELOC_ARM_PREL31
);
3748 demand_empty_rest_of_line ();
3751 /* Directives: AEABI stack-unwind tables. */
3753 /* Parse an unwind_fnstart directive. Simply records the current location. */
3756 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3758 demand_empty_rest_of_line ();
3759 if (unwind
.proc_start
)
3761 as_bad (_("duplicate .fnstart directive"));
3765 /* Mark the start of the function. */
3766 unwind
.proc_start
= expr_build_dot ();
3768 /* Reset the rest of the unwind info. */
3769 unwind
.opcode_count
= 0;
3770 unwind
.table_entry
= NULL
;
3771 unwind
.personality_routine
= NULL
;
3772 unwind
.personality_index
= -1;
3773 unwind
.frame_size
= 0;
3774 unwind
.fp_offset
= 0;
3775 unwind
.fp_reg
= REG_SP
;
3777 unwind
.sp_restored
= 0;
3781 /* Parse a handlerdata directive. Creates the exception handling table entry
3782 for the function. */
3785 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3787 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3789 as_bad (MISSING_FNSTART
);
3791 if (unwind
.table_entry
)
3792 as_bad (_("duplicate .handlerdata directive"));
3794 create_unwind_entry (1);
3797 /* Parse an unwind_fnend directive. Generates the index table entry. */
3800 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3805 unsigned int marked_pr_dependency
;
3807 demand_empty_rest_of_line ();
3809 if (!unwind
.proc_start
)
3811 as_bad (_(".fnend directive without .fnstart"));
3815 /* Add eh table entry. */
3816 if (unwind
.table_entry
== NULL
)
3817 val
= create_unwind_entry (0);
3821 /* Add index table entry. This is two words. */
3822 start_unwind_section (unwind
.saved_seg
, 1);
3823 frag_align (2, 0, 0);
3824 record_alignment (now_seg
, 2);
3826 ptr
= frag_more (8);
3828 where
= frag_now_fix () - 8;
3830 /* Self relative offset of the function start. */
3831 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3832 BFD_RELOC_ARM_PREL31
);
3834 /* Indicate dependency on EHABI-defined personality routines to the
3835 linker, if it hasn't been done already. */
3836 marked_pr_dependency
3837 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3838 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3839 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3841 static const char *const name
[] =
3843 "__aeabi_unwind_cpp_pr0",
3844 "__aeabi_unwind_cpp_pr1",
3845 "__aeabi_unwind_cpp_pr2"
3847 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3848 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3849 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3850 |= 1 << unwind
.personality_index
;
3854 /* Inline exception table entry. */
3855 md_number_to_chars (ptr
+ 4, val
, 4);
3857 /* Self relative offset of the table entry. */
3858 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3859 BFD_RELOC_ARM_PREL31
);
3861 /* Restore the original section. */
3862 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3864 unwind
.proc_start
= NULL
;
3868 /* Parse an unwind_cantunwind directive. */
3871 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3873 demand_empty_rest_of_line ();
3874 if (!unwind
.proc_start
)
3875 as_bad (MISSING_FNSTART
);
3877 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3878 as_bad (_("personality routine specified for cantunwind frame"));
3880 unwind
.personality_index
= -2;
3884 /* Parse a personalityindex directive. */
3887 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3895 as_bad (_("duplicate .personalityindex directive"));
3899 if (exp
.X_op
!= O_constant
3900 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3902 as_bad (_("bad personality routine number"));
3903 ignore_rest_of_line ();
3907 unwind
.personality_index
= exp
.X_add_number
;
3909 demand_empty_rest_of_line ();
3913 /* Parse a personality directive. */
3916 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("duplicate .personality directive"));
3926 c
= get_symbol_name (& name
);
3927 p
= input_line_pointer
;
3929 ++ input_line_pointer
;
3930 unwind
.personality_routine
= symbol_find_or_make (name
);
3932 demand_empty_rest_of_line ();
3936 /* Parse a directive saving core registers. */
3939 s_arm_unwind_save_core (void)
3945 range
= parse_reg_list (&input_line_pointer
);
3948 as_bad (_("expected register list"));
3949 ignore_rest_of_line ();
3953 demand_empty_rest_of_line ();
3955 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3956 into .unwind_save {..., sp...}. We aren't bothered about the value of
3957 ip because it is clobbered by calls. */
3958 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3959 && (range
& 0x3000) == 0x1000)
3961 unwind
.opcode_count
--;
3962 unwind
.sp_restored
= 0;
3963 range
= (range
| 0x2000) & ~0x1000;
3964 unwind
.pending_offset
= 0;
3970 /* See if we can use the short opcodes. These pop a block of up to 8
3971 registers starting with r4, plus maybe r14. */
3972 for (n
= 0; n
< 8; n
++)
3974 /* Break at the first non-saved register. */
3975 if ((range
& (1 << (n
+ 4))) == 0)
3978 /* See if there are any other bits set. */
3979 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3981 /* Use the long form. */
3982 op
= 0x8000 | ((range
>> 4) & 0xfff);
3983 add_unwind_opcode (op
, 2);
3987 /* Use the short form. */
3989 op
= 0xa8; /* Pop r14. */
3991 op
= 0xa0; /* Do not pop r14. */
3993 add_unwind_opcode (op
, 1);
4000 op
= 0xb100 | (range
& 0xf);
4001 add_unwind_opcode (op
, 2);
4004 /* Record the number of bytes pushed. */
4005 for (n
= 0; n
< 16; n
++)
4007 if (range
& (1 << n
))
4008 unwind
.frame_size
+= 4;
4013 /* Parse a directive saving FPA registers. */
4016 s_arm_unwind_save_fpa (int reg
)
4022 /* Get Number of registers to transfer. */
4023 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4026 exp
.X_op
= O_illegal
;
4028 if (exp
.X_op
!= O_constant
)
4030 as_bad (_("expected , <constant>"));
4031 ignore_rest_of_line ();
4035 num_regs
= exp
.X_add_number
;
4037 if (num_regs
< 1 || num_regs
> 4)
4039 as_bad (_("number of registers must be in the range [1:4]"));
4040 ignore_rest_of_line ();
4044 demand_empty_rest_of_line ();
4049 op
= 0xb4 | (num_regs
- 1);
4050 add_unwind_opcode (op
, 1);
4055 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4056 add_unwind_opcode (op
, 2);
4058 unwind
.frame_size
+= num_regs
* 12;
4062 /* Parse a directive saving VFP registers for ARMv6 and above. */
4065 s_arm_unwind_save_vfp_armv6 (void)
4070 int num_vfpv3_regs
= 0;
4071 int num_regs_below_16
;
4073 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4076 as_bad (_("expected register list"));
4077 ignore_rest_of_line ();
4081 demand_empty_rest_of_line ();
4083 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4084 than FSTMX/FLDMX-style ones). */
4086 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4088 num_vfpv3_regs
= count
;
4089 else if (start
+ count
> 16)
4090 num_vfpv3_regs
= start
+ count
- 16;
4092 if (num_vfpv3_regs
> 0)
4094 int start_offset
= start
> 16 ? start
- 16 : 0;
4095 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4096 add_unwind_opcode (op
, 2);
4099 /* Generate opcode for registers numbered in the range 0 .. 15. */
4100 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4101 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4102 if (num_regs_below_16
> 0)
4104 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4105 add_unwind_opcode (op
, 2);
4108 unwind
.frame_size
+= count
* 8;
4112 /* Parse a directive saving VFP registers for pre-ARMv6. */
4115 s_arm_unwind_save_vfp (void)
4121 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4124 as_bad (_("expected register list"));
4125 ignore_rest_of_line ();
4129 demand_empty_rest_of_line ();
4134 op
= 0xb8 | (count
- 1);
4135 add_unwind_opcode (op
, 1);
4140 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4141 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8 + 4;
4147 /* Parse a directive saving iWMMXt data registers. */
4150 s_arm_unwind_save_mmxwr (void)
4158 if (*input_line_pointer
== '{')
4159 input_line_pointer
++;
4163 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4167 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4172 as_tsktsk (_("register list not in ascending order"));
4175 if (*input_line_pointer
== '-')
4177 input_line_pointer
++;
4178 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4181 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4184 else if (reg
>= hi_reg
)
4186 as_bad (_("bad register range"));
4189 for (; reg
< hi_reg
; reg
++)
4193 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4195 skip_past_char (&input_line_pointer
, '}');
4197 demand_empty_rest_of_line ();
4199 /* Generate any deferred opcodes because we're going to be looking at
4201 flush_pending_unwind ();
4203 for (i
= 0; i
< 16; i
++)
4205 if (mask
& (1 << i
))
4206 unwind
.frame_size
+= 8;
4209 /* Attempt to combine with a previous opcode. We do this because gcc
4210 likes to output separate unwind directives for a single block of
4212 if (unwind
.opcode_count
> 0)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4215 if ((i
& 0xf8) == 0xc0)
4218 /* Only merge if the blocks are contiguous. */
4221 if ((mask
& 0xfe00) == (1 << 9))
4223 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4224 unwind
.opcode_count
--;
4227 else if (i
== 6 && unwind
.opcode_count
>= 2)
4229 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4233 op
= 0xffff << (reg
- 1);
4235 && ((mask
& op
) == (1u << (reg
- 1))))
4237 op
= (1 << (reg
+ i
+ 1)) - 1;
4238 op
&= ~((1 << reg
) - 1);
4240 unwind
.opcode_count
-= 2;
4247 /* We want to generate opcodes in the order the registers have been
4248 saved, ie. descending order. */
4249 for (reg
= 15; reg
>= -1; reg
--)
4251 /* Save registers in blocks. */
4253 || !(mask
& (1 << reg
)))
4255 /* We found an unsaved reg. Generate opcodes to save the
4262 op
= 0xc0 | (hi_reg
- 10);
4263 add_unwind_opcode (op
, 1);
4268 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4269 add_unwind_opcode (op
, 2);
4278 ignore_rest_of_line ();
4282 s_arm_unwind_save_mmxwcg (void)
4289 if (*input_line_pointer
== '{')
4290 input_line_pointer
++;
4292 skip_whitespace (input_line_pointer
);
4296 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4306 as_tsktsk (_("register list not in ascending order"));
4309 if (*input_line_pointer
== '-')
4311 input_line_pointer
++;
4312 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4318 else if (reg
>= hi_reg
)
4320 as_bad (_("bad register range"));
4323 for (; reg
< hi_reg
; reg
++)
4327 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4329 skip_past_char (&input_line_pointer
, '}');
4331 demand_empty_rest_of_line ();
4333 /* Generate any deferred opcodes because we're going to be looking at
4335 flush_pending_unwind ();
4337 for (reg
= 0; reg
< 16; reg
++)
4339 if (mask
& (1 << reg
))
4340 unwind
.frame_size
+= 4;
4343 add_unwind_opcode (op
, 2);
4346 ignore_rest_of_line ();
4350 /* Parse an unwind_save directive.
4351 If the argument is non-zero, this is a .vsave directive. */
4354 s_arm_unwind_save (int arch_v6
)
4357 struct reg_entry
*reg
;
4358 bfd_boolean had_brace
= FALSE
;
4360 if (!unwind
.proc_start
)
4361 as_bad (MISSING_FNSTART
);
4363 /* Figure out what sort of save we have. */
4364 peek
= input_line_pointer
;
4372 reg
= arm_reg_parse_multi (&peek
);
4376 as_bad (_("register expected"));
4377 ignore_rest_of_line ();
4386 as_bad (_("FPA .unwind_save does not take a register list"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
= peek
;
4391 s_arm_unwind_save_fpa (reg
->number
);
4395 s_arm_unwind_save_core ();
4400 s_arm_unwind_save_vfp_armv6 ();
4402 s_arm_unwind_save_vfp ();
4405 case REG_TYPE_MMXWR
:
4406 s_arm_unwind_save_mmxwr ();
4409 case REG_TYPE_MMXWCG
:
4410 s_arm_unwind_save_mmxwcg ();
4414 as_bad (_(".unwind_save does not support this kind of register"));
4415 ignore_rest_of_line ();
4420 /* Parse an unwind_movsp directive. */
4423 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4429 if (!unwind
.proc_start
)
4430 as_bad (MISSING_FNSTART
);
4432 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4435 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4436 ignore_rest_of_line ();
4440 /* Optional constant. */
4441 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4443 if (immediate_for_directive (&offset
) == FAIL
)
4449 demand_empty_rest_of_line ();
4451 if (reg
== REG_SP
|| reg
== REG_PC
)
4453 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4457 if (unwind
.fp_reg
!= REG_SP
)
4458 as_bad (_("unexpected .unwind_movsp directive"));
4460 /* Generate opcode to restore the value. */
4462 add_unwind_opcode (op
, 1);
4464 /* Record the information for later. */
4465 unwind
.fp_reg
= reg
;
4466 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4467 unwind
.sp_restored
= 1;
4470 /* Parse an unwind_pad directive. */
4473 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4477 if (!unwind
.proc_start
)
4478 as_bad (MISSING_FNSTART
);
4480 if (immediate_for_directive (&offset
) == FAIL
)
4485 as_bad (_("stack increment must be multiple of 4"));
4486 ignore_rest_of_line ();
4490 /* Don't generate any opcodes, just record the details for later. */
4491 unwind
.frame_size
+= offset
;
4492 unwind
.pending_offset
+= offset
;
4494 demand_empty_rest_of_line ();
4497 /* Parse an unwind_setfp directive. */
4500 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4506 if (!unwind
.proc_start
)
4507 as_bad (MISSING_FNSTART
);
4509 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4513 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4517 as_bad (_("expected <reg>, <reg>"));
4518 ignore_rest_of_line ();
4522 /* Optional constant. */
4523 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4525 if (immediate_for_directive (&offset
) == FAIL
)
4531 demand_empty_rest_of_line ();
4533 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4535 as_bad (_("register must be either sp or set by a previous"
4536 "unwind_movsp directive"));
4540 /* Don't generate any opcodes, just record the information for later. */
4541 unwind
.fp_reg
= fp_reg
;
4543 if (sp_reg
== REG_SP
)
4544 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4546 unwind
.fp_offset
-= offset
;
4549 /* Parse an unwind_raw directive. */
4552 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4555 /* This is an arbitrary limit. */
4556 unsigned char op
[16];
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4563 if (exp
.X_op
== O_constant
4564 && skip_past_comma (&input_line_pointer
) != FAIL
)
4566 unwind
.frame_size
+= exp
.X_add_number
;
4570 exp
.X_op
= O_illegal
;
4572 if (exp
.X_op
!= O_constant
)
4574 as_bad (_("expected <offset>, <opcode>"));
4575 ignore_rest_of_line ();
4581 /* Parse the opcode. */
4586 as_bad (_("unwind opcode too long"));
4587 ignore_rest_of_line ();
4589 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4591 as_bad (_("invalid unwind opcode"));
4592 ignore_rest_of_line ();
4595 op
[count
++] = exp
.X_add_number
;
4597 /* Parse the next byte. */
4598 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4604 /* Add the opcode bytes in reverse order. */
4606 add_unwind_opcode (op
[count
], 1);
4608 demand_empty_rest_of_line ();
4612 /* Parse a .eabi_attribute directive. */
4615 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4617 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4619 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4620 attributes_set_explicitly
[tag
] = 1;
4623 /* Emit a tls fix for the symbol. */
4626 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4630 #ifdef md_flush_pending_output
4631 md_flush_pending_output ();
4634 #ifdef md_cons_align
4638 /* Since we're just labelling the code, there's no need to define a
4641 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4642 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4643 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4644 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4646 #endif /* OBJ_ELF */
4648 static void s_arm_arch (int);
4649 static void s_arm_object_arch (int);
4650 static void s_arm_cpu (int);
4651 static void s_arm_fpu (int);
4652 static void s_arm_arch_extension (int);
4657 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4664 if (exp
.X_op
== O_symbol
)
4665 exp
.X_op
= O_secrel
;
4667 emit_expr (&exp
, 4);
4669 while (*input_line_pointer
++ == ',');
4671 input_line_pointer
--;
4672 demand_empty_rest_of_line ();
4676 /* This table describes all the machine specific pseudo-ops the assembler
4677 has to support. The fields are:
4678 pseudo-op name without dot
4679 function to call to execute this pseudo-op
4680 Integer arg to pass to the function. */
4682 const pseudo_typeS md_pseudo_table
[] =
4684 /* Never called because '.req' does not start a line. */
4685 { "req", s_req
, 0 },
4686 /* Following two are likewise never called. */
4689 { "unreq", s_unreq
, 0 },
4690 { "bss", s_bss
, 0 },
4691 { "align", s_align_ptwo
, 2 },
4692 { "arm", s_arm
, 0 },
4693 { "thumb", s_thumb
, 0 },
4694 { "code", s_code
, 0 },
4695 { "force_thumb", s_force_thumb
, 0 },
4696 { "thumb_func", s_thumb_func
, 0 },
4697 { "thumb_set", s_thumb_set
, 0 },
4698 { "even", s_even
, 0 },
4699 { "ltorg", s_ltorg
, 0 },
4700 { "pool", s_ltorg
, 0 },
4701 { "syntax", s_syntax
, 0 },
4702 { "cpu", s_arm_cpu
, 0 },
4703 { "arch", s_arm_arch
, 0 },
4704 { "object_arch", s_arm_object_arch
, 0 },
4705 { "fpu", s_arm_fpu
, 0 },
4706 { "arch_extension", s_arm_arch_extension
, 0 },
4708 { "word", s_arm_elf_cons
, 4 },
4709 { "long", s_arm_elf_cons
, 4 },
4710 { "inst.n", s_arm_elf_inst
, 2 },
4711 { "inst.w", s_arm_elf_inst
, 4 },
4712 { "inst", s_arm_elf_inst
, 0 },
4713 { "rel31", s_arm_rel31
, 0 },
4714 { "fnstart", s_arm_unwind_fnstart
, 0 },
4715 { "fnend", s_arm_unwind_fnend
, 0 },
4716 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4717 { "personality", s_arm_unwind_personality
, 0 },
4718 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4719 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4720 { "save", s_arm_unwind_save
, 0 },
4721 { "vsave", s_arm_unwind_save
, 1 },
4722 { "movsp", s_arm_unwind_movsp
, 0 },
4723 { "pad", s_arm_unwind_pad
, 0 },
4724 { "setfp", s_arm_unwind_setfp
, 0 },
4725 { "unwind_raw", s_arm_unwind_raw
, 0 },
4726 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4727 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4731 /* These are used for dwarf. */
4735 /* These are used for dwarf2. */
4736 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4737 { "loc", dwarf2_directive_loc
, 0 },
4738 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4740 { "extend", float_cons
, 'x' },
4741 { "ldouble", float_cons
, 'x' },
4742 { "packed", float_cons
, 'p' },
4744 {"secrel32", pe_directive_secrel
, 0},
4747 /* These are for compatibility with CodeComposer Studio. */
4748 {"ref", s_ccs_ref
, 0},
4749 {"def", s_ccs_def
, 0},
4750 {"asmfunc", s_ccs_asmfunc
, 0},
4751 {"endasmfunc", s_ccs_endasmfunc
, 0},
4756 /* Parser functions used exclusively in instruction operands. */
4758 /* Generic immediate-value read function for use in insn parsing.
4759 STR points to the beginning of the immediate (the leading #);
4760 VAL receives the value; if the value is outside [MIN, MAX]
4761 issue an error. PREFIX_OPT is true if the immediate prefix is
4765 parse_immediate (char **str
, int *val
, int min
, int max
,
4766 bfd_boolean prefix_opt
)
4769 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4770 if (exp
.X_op
!= O_constant
)
4772 inst
.error
= _("constant expression required");
4776 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4778 inst
.error
= _("immediate value out of range");
4782 *val
= exp
.X_add_number
;
4786 /* Less-generic immediate-value read function with the possibility of loading a
4787 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4788 instructions. Puts the result directly in inst.operands[i]. */
4791 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4792 bfd_boolean allow_symbol_p
)
4795 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4798 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4800 if (exp_p
->X_op
== O_constant
)
4802 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4803 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4804 O_constant. We have to be careful not to break compilation for
4805 32-bit X_add_number, though. */
4806 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4808 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4809 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4811 inst
.operands
[i
].regisimm
= 1;
4814 else if (exp_p
->X_op
== O_big
4815 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4817 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4819 /* Bignums have their least significant bits in
4820 generic_bignum[0]. Make sure we put 32 bits in imm and
4821 32 bits in reg, in a (hopefully) portable way. */
4822 gas_assert (parts
!= 0);
4824 /* Make sure that the number is not too big.
4825 PR 11972: Bignums can now be sign-extended to the
4826 size of a .octa so check that the out of range bits
4827 are all zero or all one. */
4828 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4830 LITTLENUM_TYPE m
= -1;
4832 if (generic_bignum
[parts
* 2] != 0
4833 && generic_bignum
[parts
* 2] != m
)
4836 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4837 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4841 inst
.operands
[i
].imm
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].reg
= 0;
4846 for (j
= 0; j
< parts
; j
++, idx
++)
4847 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4848 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4849 inst
.operands
[i
].regisimm
= 1;
4851 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4859 /* Returns the pseudo-register number of an FPA immediate constant,
4860 or FAIL if there isn't a valid constant here. */
4863 parse_fpa_immediate (char ** str
)
4865 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4871 /* First try and match exact strings, this is to guarantee
4872 that some formats will work even for cross assembly. */
4874 for (i
= 0; fp_const
[i
]; i
++)
4876 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4880 *str
+= strlen (fp_const
[i
]);
4881 if (is_end_of_line
[(unsigned char) **str
])
4887 /* Just because we didn't get a match doesn't mean that the constant
4888 isn't valid, just that it is in a format that we don't
4889 automatically recognize. Try parsing it with the standard
4890 expression routines. */
4892 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4894 /* Look for a raw floating point number. */
4895 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4896 && is_end_of_line
[(unsigned char) *save_in
])
4898 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4900 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4902 if (words
[j
] != fp_values
[i
][j
])
4906 if (j
== MAX_LITTLENUMS
)
4914 /* Try and parse a more complex expression, this will probably fail
4915 unless the code uses a floating point prefix (eg "0f"). */
4916 save_in
= input_line_pointer
;
4917 input_line_pointer
= *str
;
4918 if (expression (&exp
) == absolute_section
4919 && exp
.X_op
== O_big
4920 && exp
.X_add_number
< 0)
4922 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4924 #define X_PRECISION 5
4925 #define E_PRECISION 15L
4926 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4930 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4932 if (words
[j
] != fp_values
[i
][j
])
4936 if (j
== MAX_LITTLENUMS
)
4938 *str
= input_line_pointer
;
4939 input_line_pointer
= save_in
;
4946 *str
= input_line_pointer
;
4947 input_line_pointer
= save_in
;
4948 inst
.error
= _("invalid FPA immediate expression");
4952 /* Returns 1 if a number has "quarter-precision" float format
4953 0baBbbbbbc defgh000 00000000 00000000. */
4956 is_quarter_float (unsigned imm
)
4958 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4959 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4963 /* Detect the presence of a floating point or integer zero constant,
4967 parse_ifimm_zero (char **in
)
4971 if (!is_immediate_prefix (**in
))
4976 /* Accept #0x0 as a synonym for #0. */
4977 if (strncmp (*in
, "0x", 2) == 0)
4980 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4985 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4986 &generic_floating_point_number
);
4989 && generic_floating_point_number
.sign
== '+'
4990 && (generic_floating_point_number
.low
4991 > generic_floating_point_number
.leader
))
4997 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4998 0baBbbbbbc defgh000 00000000 00000000.
4999 The zero and minus-zero cases need special handling, since they can't be
5000 encoded in the "quarter-precision" float format, but can nonetheless be
5001 loaded as integer constants. */
5004 parse_qfloat_immediate (char **ccp
, int *immed
)
5008 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5009 int found_fpchar
= 0;
5011 skip_past_char (&str
, '#');
5013 /* We must not accidentally parse an integer as a floating-point number. Make
5014 sure that the value we parse is not an integer by checking for special
5015 characters '.' or 'e'.
5016 FIXME: This is a horrible hack, but doing better is tricky because type
5017 information isn't in a very usable state at parse time. */
5019 skip_whitespace (fpnum
);
5021 if (strncmp (fpnum
, "0x", 2) == 0)
5025 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5026 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5036 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5038 unsigned fpword
= 0;
5041 /* Our FP word must be 32 bits (single-precision FP). */
5042 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5044 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5048 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5061 /* Shift operands. */
5064 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5067 struct asm_shift_name
5070 enum shift_kind kind
;
5073 /* Third argument to parse_shift. */
5074 enum parse_shift_mode
5076 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5077 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5078 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5079 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5080 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5083 /* Parse a <shift> specifier on an ARM data processing instruction.
5084 This has three forms:
5086 (LSL|LSR|ASL|ASR|ROR) Rs
5087 (LSL|LSR|ASL|ASR|ROR) #imm
5090 Note that ASL is assimilated to LSL in the instruction encoding, and
5091 RRX to ROR #0 (which cannot be written as such). */
5094 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5096 const struct asm_shift_name
*shift_name
;
5097 enum shift_kind shift
;
5102 for (p
= *str
; ISALPHA (*p
); p
++)
5107 inst
.error
= _("shift expression expected");
5111 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5114 if (shift_name
== NULL
)
5116 inst
.error
= _("shift expression expected");
5120 shift
= shift_name
->kind
;
5124 case NO_SHIFT_RESTRICT
:
5125 case SHIFT_IMMEDIATE
: break;
5127 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5128 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5130 inst
.error
= _("'LSL' or 'ASR' required");
5135 case SHIFT_LSL_IMMEDIATE
:
5136 if (shift
!= SHIFT_LSL
)
5138 inst
.error
= _("'LSL' required");
5143 case SHIFT_ASR_IMMEDIATE
:
5144 if (shift
!= SHIFT_ASR
)
5146 inst
.error
= _("'ASR' required");
5154 if (shift
!= SHIFT_RRX
)
5156 /* Whitespace can appear here if the next thing is a bare digit. */
5157 skip_whitespace (p
);
5159 if (mode
== NO_SHIFT_RESTRICT
5160 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5162 inst
.operands
[i
].imm
= reg
;
5163 inst
.operands
[i
].immisreg
= 1;
5165 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5168 inst
.operands
[i
].shift_kind
= shift
;
5169 inst
.operands
[i
].shifted
= 1;
5174 /* Parse a <shifter_operand> for an ARM data processing instruction:
5177 #<immediate>, <rotate>
5181 where <shift> is defined by parse_shift above, and <rotate> is a
5182 multiple of 2 between 0 and 30. Validation of immediate operands
5183 is deferred to md_apply_fix. */
5186 parse_shifter_operand (char **str
, int i
)
5191 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5193 inst
.operands
[i
].reg
= value
;
5194 inst
.operands
[i
].isreg
= 1;
5196 /* parse_shift will override this if appropriate */
5197 inst
.reloc
.exp
.X_op
= O_constant
;
5198 inst
.reloc
.exp
.X_add_number
= 0;
5200 if (skip_past_comma (str
) == FAIL
)
5203 /* Shift operation on register. */
5204 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5207 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5210 if (skip_past_comma (str
) == SUCCESS
)
5212 /* #x, y -- ie explicit rotation by Y. */
5213 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5216 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5218 inst
.error
= _("constant expression expected");
5222 value
= exp
.X_add_number
;
5223 if (value
< 0 || value
> 30 || value
% 2 != 0)
5225 inst
.error
= _("invalid rotation");
5228 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5230 inst
.error
= _("invalid constant");
5234 /* Encode as specified. */
5235 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5239 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5240 inst
.reloc
.pc_rel
= 0;
5244 /* Group relocation information. Each entry in the table contains the
5245 textual name of the relocation as may appear in assembler source
5246 and must end with a colon.
5247 Along with this textual name are the relocation codes to be used if
5248 the corresponding instruction is an ALU instruction (ADD or SUB only),
5249 an LDR, an LDRS, or an LDC. */
5251 struct group_reloc_table_entry
5262 /* Varieties of non-ALU group relocation. */
5269 static struct group_reloc_table_entry group_reloc_table
[] =
5270 { /* Program counter relative: */
5272 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5277 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5278 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5279 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5280 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5282 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5287 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5288 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5289 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5290 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5292 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5293 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5296 /* Section base relative */
5298 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5303 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5304 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5305 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5306 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5308 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5313 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5314 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5315 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5316 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5318 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5319 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5320 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5321 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5322 /* Absolute thumb alu relocations. */
5324 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5329 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5334 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5339 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5344 /* Given the address of a pointer pointing to the textual name of a group
5345 relocation as may appear in assembler source, attempt to find its details
5346 in group_reloc_table. The pointer will be updated to the character after
5347 the trailing colon. On failure, FAIL will be returned; SUCCESS
5348 otherwise. On success, *entry will be updated to point at the relevant
5349 group_reloc_table entry. */
5352 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5355 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5357 int length
= strlen (group_reloc_table
[i
].name
);
5359 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5360 && (*str
)[length
] == ':')
5362 *out
= &group_reloc_table
[i
];
5363 *str
+= (length
+ 1);
5371 /* Parse a <shifter_operand> for an ARM data processing instruction
5372 (as for parse_shifter_operand) where group relocations are allowed:
5375 #<immediate>, <rotate>
5376 #:<group_reloc>:<expression>
5380 where <group_reloc> is one of the strings defined in group_reloc_table.
5381 The hashes are optional.
5383 Everything else is as for parse_shifter_operand. */
5385 static parse_operand_result
5386 parse_shifter_operand_group_reloc (char **str
, int i
)
5388 /* Determine if we have the sequence of characters #: or just :
5389 coming next. If we do, then we check for a group relocation.
5390 If we don't, punt the whole lot to parse_shifter_operand. */
5392 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5393 || (*str
)[0] == ':')
5395 struct group_reloc_table_entry
*entry
;
5397 if ((*str
)[0] == '#')
5402 /* Try to parse a group relocation. Anything else is an error. */
5403 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5405 inst
.error
= _("unknown group relocation");
5406 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5409 /* We now have the group relocation table entry corresponding to
5410 the name in the assembler source. Next, we parse the expression. */
5411 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5412 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5414 /* Record the relocation type (always the ALU variant here). */
5415 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5416 gas_assert (inst
.reloc
.type
!= 0);
5418 return PARSE_OPERAND_SUCCESS
;
5421 return parse_shifter_operand (str
, i
) == SUCCESS
5422 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5424 /* Never reached. */
5427 /* Parse a Neon alignment expression. Information is written to
5428 inst.operands[i]. We assume the initial ':' has been skipped.
5430 align .imm = align << 8, .immisalign=1, .preind=0 */
5431 static parse_operand_result
5432 parse_neon_alignment (char **str
, int i
)
5437 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5439 if (exp
.X_op
!= O_constant
)
5441 inst
.error
= _("alignment must be constant");
5442 return PARSE_OPERAND_FAIL
;
5445 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5446 inst
.operands
[i
].immisalign
= 1;
5447 /* Alignments are not pre-indexes. */
5448 inst
.operands
[i
].preind
= 0;
5451 return PARSE_OPERAND_SUCCESS
;
5454 /* Parse all forms of an ARM address expression. Information is written
5455 to inst.operands[i] and/or inst.reloc.
5457 Preindexed addressing (.preind=1):
5459 [Rn, #offset] .reg=Rn .reloc.exp=offset
5460 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5461 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5462 .shift_kind=shift .reloc.exp=shift_imm
5464 These three may have a trailing ! which causes .writeback to be set also.
5466 Postindexed addressing (.postind=1, .writeback=1):
5468 [Rn], #offset .reg=Rn .reloc.exp=offset
5469 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5470 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5471 .shift_kind=shift .reloc.exp=shift_imm
5473 Unindexed addressing (.preind=0, .postind=0):
5475 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5479 [Rn]{!} shorthand for [Rn,#0]{!}
5480 =immediate .isreg=0 .reloc.exp=immediate
5481 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5483 It is the caller's responsibility to check for addressing modes not
5484 supported by the instruction, and to set inst.reloc.type. */
5486 static parse_operand_result
5487 parse_address_main (char **str
, int i
, int group_relocations
,
5488 group_reloc_type group_type
)
5493 if (skip_past_char (&p
, '[') == FAIL
)
5495 if (skip_past_char (&p
, '=') == FAIL
)
5497 /* Bare address - translate to PC-relative offset. */
5498 inst
.reloc
.pc_rel
= 1;
5499 inst
.operands
[i
].reg
= REG_PC
;
5500 inst
.operands
[i
].isreg
= 1;
5501 inst
.operands
[i
].preind
= 1;
5503 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5504 return PARSE_OPERAND_FAIL
;
5506 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5507 /*allow_symbol_p=*/TRUE
))
5508 return PARSE_OPERAND_FAIL
;
5511 return PARSE_OPERAND_SUCCESS
;
5514 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5515 skip_whitespace (p
);
5517 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5519 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5520 return PARSE_OPERAND_FAIL
;
5522 inst
.operands
[i
].reg
= reg
;
5523 inst
.operands
[i
].isreg
= 1;
5525 if (skip_past_comma (&p
) == SUCCESS
)
5527 inst
.operands
[i
].preind
= 1;
5530 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5532 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5534 inst
.operands
[i
].imm
= reg
;
5535 inst
.operands
[i
].immisreg
= 1;
5537 if (skip_past_comma (&p
) == SUCCESS
)
5538 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5539 return PARSE_OPERAND_FAIL
;
5541 else if (skip_past_char (&p
, ':') == SUCCESS
)
5543 /* FIXME: '@' should be used here, but it's filtered out by generic
5544 code before we get to see it here. This may be subject to
5546 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5548 if (result
!= PARSE_OPERAND_SUCCESS
)
5553 if (inst
.operands
[i
].negative
)
5555 inst
.operands
[i
].negative
= 0;
5559 if (group_relocations
5560 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5562 struct group_reloc_table_entry
*entry
;
5564 /* Skip over the #: or : sequence. */
5570 /* Try to parse a group relocation. Anything else is an
5572 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5574 inst
.error
= _("unknown group relocation");
5575 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5578 /* We now have the group relocation table entry corresponding to
5579 the name in the assembler source. Next, we parse the
5581 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5582 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5584 /* Record the relocation type. */
5588 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5596 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5603 if (inst
.reloc
.type
== 0)
5605 inst
.error
= _("this group relocation is not allowed on this instruction");
5606 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5612 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5613 return PARSE_OPERAND_FAIL
;
5614 /* If the offset is 0, find out if it's a +0 or -0. */
5615 if (inst
.reloc
.exp
.X_op
== O_constant
5616 && inst
.reloc
.exp
.X_add_number
== 0)
5618 skip_whitespace (q
);
5622 skip_whitespace (q
);
5625 inst
.operands
[i
].negative
= 1;
5630 else if (skip_past_char (&p
, ':') == SUCCESS
)
5632 /* FIXME: '@' should be used here, but it's filtered out by generic code
5633 before we get to see it here. This may be subject to change. */
5634 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5636 if (result
!= PARSE_OPERAND_SUCCESS
)
5640 if (skip_past_char (&p
, ']') == FAIL
)
5642 inst
.error
= _("']' expected");
5643 return PARSE_OPERAND_FAIL
;
5646 if (skip_past_char (&p
, '!') == SUCCESS
)
5647 inst
.operands
[i
].writeback
= 1;
5649 else if (skip_past_comma (&p
) == SUCCESS
)
5651 if (skip_past_char (&p
, '{') == SUCCESS
)
5653 /* [Rn], {expr} - unindexed, with option */
5654 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5655 0, 255, TRUE
) == FAIL
)
5656 return PARSE_OPERAND_FAIL
;
5658 if (skip_past_char (&p
, '}') == FAIL
)
5660 inst
.error
= _("'}' expected at end of 'option' field");
5661 return PARSE_OPERAND_FAIL
;
5663 if (inst
.operands
[i
].preind
)
5665 inst
.error
= _("cannot combine index with option");
5666 return PARSE_OPERAND_FAIL
;
5669 return PARSE_OPERAND_SUCCESS
;
5673 inst
.operands
[i
].postind
= 1;
5674 inst
.operands
[i
].writeback
= 1;
5676 if (inst
.operands
[i
].preind
)
5678 inst
.error
= _("cannot combine pre- and post-indexing");
5679 return PARSE_OPERAND_FAIL
;
5683 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5685 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5687 /* We might be using the immediate for alignment already. If we
5688 are, OR the register number into the low-order bits. */
5689 if (inst
.operands
[i
].immisalign
)
5690 inst
.operands
[i
].imm
|= reg
;
5692 inst
.operands
[i
].imm
= reg
;
5693 inst
.operands
[i
].immisreg
= 1;
5695 if (skip_past_comma (&p
) == SUCCESS
)
5696 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5697 return PARSE_OPERAND_FAIL
;
5702 if (inst
.operands
[i
].negative
)
5704 inst
.operands
[i
].negative
= 0;
5707 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5708 return PARSE_OPERAND_FAIL
;
5709 /* If the offset is 0, find out if it's a +0 or -0. */
5710 if (inst
.reloc
.exp
.X_op
== O_constant
5711 && inst
.reloc
.exp
.X_add_number
== 0)
5713 skip_whitespace (q
);
5717 skip_whitespace (q
);
5720 inst
.operands
[i
].negative
= 1;
5726 /* If at this point neither .preind nor .postind is set, we have a
5727 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5728 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5730 inst
.operands
[i
].preind
= 1;
5731 inst
.reloc
.exp
.X_op
= O_constant
;
5732 inst
.reloc
.exp
.X_add_number
= 0;
5735 return PARSE_OPERAND_SUCCESS
;
5739 parse_address (char **str
, int i
)
5741 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5745 static parse_operand_result
5746 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5748 return parse_address_main (str
, i
, 1, type
);
5751 /* Parse an operand for a MOVW or MOVT instruction. */
5753 parse_half (char **str
)
5758 skip_past_char (&p
, '#');
5759 if (strncasecmp (p
, ":lower16:", 9) == 0)
5760 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5761 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5762 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5764 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5767 skip_whitespace (p
);
5770 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5773 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5775 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5777 inst
.error
= _("constant expression expected");
5780 if (inst
.reloc
.exp
.X_add_number
< 0
5781 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5783 inst
.error
= _("immediate value out of range");
5791 /* Miscellaneous. */
5793 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5794 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5796 parse_psr (char **str
, bfd_boolean lhs
)
5799 unsigned long psr_field
;
5800 const struct asm_psr
*psr
;
5802 bfd_boolean is_apsr
= FALSE
;
5803 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5805 /* PR gas/12698: If the user has specified -march=all then m_profile will
5806 be TRUE, but we want to ignore it in this case as we are building for any
5807 CPU type, including non-m variants. */
5808 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5811 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5812 feature for ease of use and backwards compatibility. */
5814 if (strncasecmp (p
, "SPSR", 4) == 0)
5817 goto unsupported_psr
;
5819 psr_field
= SPSR_BIT
;
5821 else if (strncasecmp (p
, "CPSR", 4) == 0)
5824 goto unsupported_psr
;
5828 else if (strncasecmp (p
, "APSR", 4) == 0)
5830 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5831 and ARMv7-R architecture CPUs. */
5840 while (ISALNUM (*p
) || *p
== '_');
5842 if (strncasecmp (start
, "iapsr", 5) == 0
5843 || strncasecmp (start
, "eapsr", 5) == 0
5844 || strncasecmp (start
, "xpsr", 4) == 0
5845 || strncasecmp (start
, "psr", 3) == 0)
5846 p
= start
+ strcspn (start
, "rR") + 1;
5848 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5854 /* If APSR is being written, a bitfield may be specified. Note that
5855 APSR itself is handled above. */
5856 if (psr
->field
<= 3)
5858 psr_field
= psr
->field
;
5864 /* M-profile MSR instructions have the mask field set to "10", except
5865 *PSR variants which modify APSR, which may use a different mask (and
5866 have been handled already). Do that by setting the PSR_f field
5868 return psr
->field
| (lhs
? PSR_f
: 0);
5871 goto unsupported_psr
;
5877 /* A suffix follows. */
5883 while (ISALNUM (*p
) || *p
== '_');
5887 /* APSR uses a notation for bits, rather than fields. */
5888 unsigned int nzcvq_bits
= 0;
5889 unsigned int g_bit
= 0;
5892 for (bit
= start
; bit
!= p
; bit
++)
5894 switch (TOLOWER (*bit
))
5897 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5901 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5913 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5917 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5921 inst
.error
= _("unexpected bit specified after APSR");
5926 if (nzcvq_bits
== 0x1f)
5931 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5933 inst
.error
= _("selected processor does not "
5934 "support DSP extension");
5941 if ((nzcvq_bits
& 0x20) != 0
5942 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5943 || (g_bit
& 0x2) != 0)
5945 inst
.error
= _("bad bitmask specified after APSR");
5951 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5956 psr_field
|= psr
->field
;
5962 goto error
; /* Garbage after "[CS]PSR". */
5964 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5965 is deprecated, but allow it anyway. */
5969 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5972 else if (!m_profile
)
5973 /* These bits are never right for M-profile devices: don't set them
5974 (only code paths which read/write APSR reach here). */
5975 psr_field
|= (PSR_c
| PSR_f
);
5981 inst
.error
= _("selected processor does not support requested special "
5982 "purpose register");
5986 inst
.error
= _("flag for {c}psr instruction expected");
5990 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5991 value suitable for splatting into the AIF field of the instruction. */
5994 parse_cps_flags (char **str
)
6003 case '\0': case ',':
6006 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6007 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6008 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6011 inst
.error
= _("unrecognized CPS flag");
6016 if (saw_a_flag
== 0)
6018 inst
.error
= _("missing CPS flags");
6026 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6027 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6030 parse_endian_specifier (char **str
)
6035 if (strncasecmp (s
, "BE", 2))
6037 else if (strncasecmp (s
, "LE", 2))
6041 inst
.error
= _("valid endian specifiers are be or le");
6045 if (ISALNUM (s
[2]) || s
[2] == '_')
6047 inst
.error
= _("valid endian specifiers are be or le");
6052 return little_endian
;
6055 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6056 value suitable for poking into the rotate field of an sxt or sxta
6057 instruction, or FAIL on error. */
6060 parse_ror (char **str
)
6065 if (strncasecmp (s
, "ROR", 3) == 0)
6069 inst
.error
= _("missing rotation field after comma");
6073 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6078 case 0: *str
= s
; return 0x0;
6079 case 8: *str
= s
; return 0x1;
6080 case 16: *str
= s
; return 0x2;
6081 case 24: *str
= s
; return 0x3;
6084 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6089 /* Parse a conditional code (from conds[] below). The value returned is in the
6090 range 0 .. 14, or FAIL. */
6092 parse_cond (char **str
)
6095 const struct asm_cond
*c
;
6097 /* Condition codes are always 2 characters, so matching up to
6098 3 characters is sufficient. */
6103 while (ISALPHA (*q
) && n
< 3)
6105 cond
[n
] = TOLOWER (*q
);
6110 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6113 inst
.error
= _("condition required");
6121 /* Record a use of the given feature. */
6123 record_feature_use (const arm_feature_set
*feature
)
6126 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6128 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6131 /* If the given feature available in the selected CPU, mark it as used.
6132 Returns TRUE iff feature is available. */
6134 mark_feature_used (const arm_feature_set
*feature
)
6136 /* Ensure the option is valid on the current architecture. */
6137 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6140 /* Add the appropriate architecture feature for the barrier option used.
6142 record_feature_use (feature
);
6147 /* Parse an option for a barrier instruction. Returns the encoding for the
6150 parse_barrier (char **str
)
6153 const struct asm_barrier_opt
*o
;
6156 while (ISALPHA (*q
))
6159 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6164 if (!mark_feature_used (&o
->arch
))
6171 /* Parse the operands of a table branch instruction. Similar to a memory
6174 parse_tb (char **str
)
6179 if (skip_past_char (&p
, '[') == FAIL
)
6181 inst
.error
= _("'[' expected");
6185 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6187 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6190 inst
.operands
[0].reg
= reg
;
6192 if (skip_past_comma (&p
) == FAIL
)
6194 inst
.error
= _("',' expected");
6198 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6200 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6203 inst
.operands
[0].imm
= reg
;
6205 if (skip_past_comma (&p
) == SUCCESS
)
6207 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6209 if (inst
.reloc
.exp
.X_add_number
!= 1)
6211 inst
.error
= _("invalid shift");
6214 inst
.operands
[0].shifted
= 1;
6217 if (skip_past_char (&p
, ']') == FAIL
)
6219 inst
.error
= _("']' expected");
6226 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6227 information on the types the operands can take and how they are encoded.
6228 Up to four operands may be read; this function handles setting the
6229 ".present" field for each read operand itself.
6230 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6231 else returns FAIL. */
6234 parse_neon_mov (char **str
, int *which_operand
)
6236 int i
= *which_operand
, val
;
6237 enum arm_reg_type rtype
;
6239 struct neon_type_el optype
;
6241 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6243 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6244 inst
.operands
[i
].reg
= val
;
6245 inst
.operands
[i
].isscalar
= 1;
6246 inst
.operands
[i
].vectype
= optype
;
6247 inst
.operands
[i
++].present
= 1;
6249 if (skip_past_comma (&ptr
) == FAIL
)
6252 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6255 inst
.operands
[i
].reg
= val
;
6256 inst
.operands
[i
].isreg
= 1;
6257 inst
.operands
[i
].present
= 1;
6259 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6262 /* Cases 0, 1, 2, 3, 5 (D only). */
6263 if (skip_past_comma (&ptr
) == FAIL
)
6266 inst
.operands
[i
].reg
= val
;
6267 inst
.operands
[i
].isreg
= 1;
6268 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6269 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6270 inst
.operands
[i
].isvec
= 1;
6271 inst
.operands
[i
].vectype
= optype
;
6272 inst
.operands
[i
++].present
= 1;
6274 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6276 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6277 Case 13: VMOV <Sd>, <Rm> */
6278 inst
.operands
[i
].reg
= val
;
6279 inst
.operands
[i
].isreg
= 1;
6280 inst
.operands
[i
].present
= 1;
6282 if (rtype
== REG_TYPE_NQ
)
6284 first_error (_("can't use Neon quad register here"));
6287 else if (rtype
!= REG_TYPE_VFS
)
6290 if (skip_past_comma (&ptr
) == FAIL
)
6292 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6294 inst
.operands
[i
].reg
= val
;
6295 inst
.operands
[i
].isreg
= 1;
6296 inst
.operands
[i
].present
= 1;
6299 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6302 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6303 Case 1: VMOV<c><q> <Dd>, <Dm>
6304 Case 8: VMOV.F32 <Sd>, <Sm>
6305 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6307 inst
.operands
[i
].reg
= val
;
6308 inst
.operands
[i
].isreg
= 1;
6309 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6310 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6311 inst
.operands
[i
].isvec
= 1;
6312 inst
.operands
[i
].vectype
= optype
;
6313 inst
.operands
[i
].present
= 1;
6315 if (skip_past_comma (&ptr
) == SUCCESS
)
6320 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6323 inst
.operands
[i
].reg
= val
;
6324 inst
.operands
[i
].isreg
= 1;
6325 inst
.operands
[i
++].present
= 1;
6327 if (skip_past_comma (&ptr
) == FAIL
)
6330 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
].present
= 1;
6338 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6339 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6340 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6341 Case 10: VMOV.F32 <Sd>, #<imm>
6342 Case 11: VMOV.F64 <Dd>, #<imm> */
6343 inst
.operands
[i
].immisfloat
= 1;
6344 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6346 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6347 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6351 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6355 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6358 inst
.operands
[i
].reg
= val
;
6359 inst
.operands
[i
].isreg
= 1;
6360 inst
.operands
[i
++].present
= 1;
6362 if (skip_past_comma (&ptr
) == FAIL
)
6365 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6367 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6368 inst
.operands
[i
].reg
= val
;
6369 inst
.operands
[i
].isscalar
= 1;
6370 inst
.operands
[i
].present
= 1;
6371 inst
.operands
[i
].vectype
= optype
;
6373 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6375 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6376 inst
.operands
[i
].reg
= val
;
6377 inst
.operands
[i
].isreg
= 1;
6378 inst
.operands
[i
++].present
= 1;
6380 if (skip_past_comma (&ptr
) == FAIL
)
6383 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6386 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6390 inst
.operands
[i
].reg
= val
;
6391 inst
.operands
[i
].isreg
= 1;
6392 inst
.operands
[i
].isvec
= 1;
6393 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6394 inst
.operands
[i
].vectype
= optype
;
6395 inst
.operands
[i
].present
= 1;
6397 if (rtype
== REG_TYPE_VFS
)
6401 if (skip_past_comma (&ptr
) == FAIL
)
6403 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6406 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6409 inst
.operands
[i
].reg
= val
;
6410 inst
.operands
[i
].isreg
= 1;
6411 inst
.operands
[i
].isvec
= 1;
6412 inst
.operands
[i
].issingle
= 1;
6413 inst
.operands
[i
].vectype
= optype
;
6414 inst
.operands
[i
].present
= 1;
6417 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6421 inst
.operands
[i
].reg
= val
;
6422 inst
.operands
[i
].isreg
= 1;
6423 inst
.operands
[i
].isvec
= 1;
6424 inst
.operands
[i
].issingle
= 1;
6425 inst
.operands
[i
].vectype
= optype
;
6426 inst
.operands
[i
].present
= 1;
6431 first_error (_("parse error"));
6435 /* Successfully parsed the operands. Update args. */
6441 first_error (_("expected comma"));
6445 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6449 /* Use this macro when the operand constraints are different
6450 for ARM and THUMB (e.g. ldrd). */
6451 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6452 ((arm_operand) | ((thumb_operand) << 16))
6454 /* Matcher codes for parse_operands. */
6455 enum operand_parse_code
6457 OP_stop
, /* end of line */
6459 OP_RR
, /* ARM register */
6460 OP_RRnpc
, /* ARM register, not r15 */
6461 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6462 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6463 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6464 optional trailing ! */
6465 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6466 OP_RCP
, /* Coprocessor number */
6467 OP_RCN
, /* Coprocessor register */
6468 OP_RF
, /* FPA register */
6469 OP_RVS
, /* VFP single precision register */
6470 OP_RVD
, /* VFP double precision register (0..15) */
6471 OP_RND
, /* Neon double precision register (0..31) */
6472 OP_RNQ
, /* Neon quad precision register */
6473 OP_RVSD
, /* VFP single or double precision register */
6474 OP_RNDQ
, /* Neon double or quad precision register */
6475 OP_RNSDQ
, /* Neon single, double or quad precision register */
6476 OP_RNSC
, /* Neon scalar D[X] */
6477 OP_RVC
, /* VFP control register */
6478 OP_RMF
, /* Maverick F register */
6479 OP_RMD
, /* Maverick D register */
6480 OP_RMFX
, /* Maverick FX register */
6481 OP_RMDX
, /* Maverick DX register */
6482 OP_RMAX
, /* Maverick AX register */
6483 OP_RMDS
, /* Maverick DSPSC register */
6484 OP_RIWR
, /* iWMMXt wR register */
6485 OP_RIWC
, /* iWMMXt wC register */
6486 OP_RIWG
, /* iWMMXt wCG register */
6487 OP_RXA
, /* XScale accumulator register */
6489 OP_REGLST
, /* ARM register list */
6490 OP_VRSLST
, /* VFP single-precision register list */
6491 OP_VRDLST
, /* VFP double-precision register list */
6492 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6493 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6494 OP_NSTRLST
, /* Neon element/structure list */
6496 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6497 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6498 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6499 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6500 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6501 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6502 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6503 OP_VMOV
, /* Neon VMOV operands. */
6504 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6505 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6506 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6508 OP_I0
, /* immediate zero */
6509 OP_I7
, /* immediate value 0 .. 7 */
6510 OP_I15
, /* 0 .. 15 */
6511 OP_I16
, /* 1 .. 16 */
6512 OP_I16z
, /* 0 .. 16 */
6513 OP_I31
, /* 0 .. 31 */
6514 OP_I31w
, /* 0 .. 31, optional trailing ! */
6515 OP_I32
, /* 1 .. 32 */
6516 OP_I32z
, /* 0 .. 32 */
6517 OP_I63
, /* 0 .. 63 */
6518 OP_I63s
, /* -64 .. 63 */
6519 OP_I64
, /* 1 .. 64 */
6520 OP_I64z
, /* 0 .. 64 */
6521 OP_I255
, /* 0 .. 255 */
6523 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6524 OP_I7b
, /* 0 .. 7 */
6525 OP_I15b
, /* 0 .. 15 */
6526 OP_I31b
, /* 0 .. 31 */
6528 OP_SH
, /* shifter operand */
6529 OP_SHG
, /* shifter operand with possible group relocation */
6530 OP_ADDR
, /* Memory address expression (any mode) */
6531 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6532 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6533 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6534 OP_EXP
, /* arbitrary expression */
6535 OP_EXPi
, /* same, with optional immediate prefix */
6536 OP_EXPr
, /* same, with optional relocation suffix */
6537 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6538 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6539 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6541 OP_CPSF
, /* CPS flags */
6542 OP_ENDI
, /* Endianness specifier */
6543 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6544 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6545 OP_COND
, /* conditional code */
6546 OP_TB
, /* Table branch. */
6548 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6550 OP_RRnpc_I0
, /* ARM register or literal 0 */
6551 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6552 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6553 OP_RF_IF
, /* FPA register or immediate */
6554 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6555 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6557 /* Optional operands. */
6558 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6559 OP_oI31b
, /* 0 .. 31 */
6560 OP_oI32b
, /* 1 .. 32 */
6561 OP_oI32z
, /* 0 .. 32 */
6562 OP_oIffffb
, /* 0 .. 65535 */
6563 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6565 OP_oRR
, /* ARM register */
6566 OP_oRRnpc
, /* ARM register, not the PC */
6567 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6568 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6569 OP_oRND
, /* Optional Neon double precision register */
6570 OP_oRNQ
, /* Optional Neon quad precision register */
6571 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6572 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6573 OP_oSHll
, /* LSL immediate */
6574 OP_oSHar
, /* ASR immediate */
6575 OP_oSHllar
, /* LSL or ASR immediate */
6576 OP_oROR
, /* ROR 0/8/16/24 */
6577 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6579 /* Some pre-defined mixed (ARM/THUMB) operands. */
6580 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6581 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6582 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6584 OP_FIRST_OPTIONAL
= OP_oI7b
6587 /* Generic instruction operand parser. This does no encoding and no
6588 semantic validation; it merely squirrels values away in the inst
6589 structure. Returns SUCCESS or FAIL depending on whether the
6590 specified grammar matched. */
6592 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6594 unsigned const int *upat
= pattern
;
6595 char *backtrack_pos
= 0;
6596 const char *backtrack_error
= 0;
6597 int i
, val
= 0, backtrack_index
= 0;
6598 enum arm_reg_type rtype
;
6599 parse_operand_result result
;
6600 unsigned int op_parse_code
;
6602 #define po_char_or_fail(chr) \
6605 if (skip_past_char (&str, chr) == FAIL) \
6610 #define po_reg_or_fail(regtype) \
6613 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6614 & inst.operands[i].vectype); \
6617 first_error (_(reg_expected_msgs[regtype])); \
6620 inst.operands[i].reg = val; \
6621 inst.operands[i].isreg = 1; \
6622 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6623 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6624 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6625 || rtype == REG_TYPE_VFD \
6626 || rtype == REG_TYPE_NQ); \
6630 #define po_reg_or_goto(regtype, label) \
6633 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6634 & inst.operands[i].vectype); \
6638 inst.operands[i].reg = val; \
6639 inst.operands[i].isreg = 1; \
6640 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6641 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6642 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6643 || rtype == REG_TYPE_VFD \
6644 || rtype == REG_TYPE_NQ); \
6648 #define po_imm_or_fail(min, max, popt) \
6651 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6653 inst.operands[i].imm = val; \
6657 #define po_scalar_or_goto(elsz, label) \
6660 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6663 inst.operands[i].reg = val; \
6664 inst.operands[i].isscalar = 1; \
6668 #define po_misc_or_fail(expr) \
6676 #define po_misc_or_fail_no_backtrack(expr) \
6680 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6681 backtrack_pos = 0; \
6682 if (result != PARSE_OPERAND_SUCCESS) \
6687 #define po_barrier_or_imm(str) \
6690 val = parse_barrier (&str); \
6691 if (val == FAIL && ! ISALPHA (*str)) \
6694 /* ISB can only take SY as an option. */ \
6695 || ((inst.instruction & 0xf0) == 0x60 \
6698 inst.error = _("invalid barrier type"); \
6699 backtrack_pos = 0; \
6705 skip_whitespace (str
);
6707 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6709 op_parse_code
= upat
[i
];
6710 if (op_parse_code
>= 1<<16)
6711 op_parse_code
= thumb
? (op_parse_code
>> 16)
6712 : (op_parse_code
& ((1<<16)-1));
6714 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6716 /* Remember where we are in case we need to backtrack. */
6717 gas_assert (!backtrack_pos
);
6718 backtrack_pos
= str
;
6719 backtrack_error
= inst
.error
;
6720 backtrack_index
= i
;
6723 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6724 po_char_or_fail (',');
6726 switch (op_parse_code
)
6734 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6735 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6736 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6737 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6738 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6739 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6741 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6743 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6745 /* Also accept generic coprocessor regs for unknown registers. */
6747 po_reg_or_fail (REG_TYPE_CN
);
6749 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6750 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6751 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6752 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6753 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6754 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6755 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6756 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6757 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6758 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6760 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6762 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6763 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6765 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6767 /* Neon scalar. Using an element size of 8 means that some invalid
6768 scalars are accepted here, so deal with those in later code. */
6769 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6773 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6776 po_imm_or_fail (0, 0, TRUE
);
6781 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6786 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6789 if (parse_ifimm_zero (&str
))
6790 inst
.operands
[i
].imm
= 0;
6794 = _("only floating point zero is allowed as immediate value");
6802 po_scalar_or_goto (8, try_rr
);
6805 po_reg_or_fail (REG_TYPE_RN
);
6811 po_scalar_or_goto (8, try_nsdq
);
6814 po_reg_or_fail (REG_TYPE_NSDQ
);
6820 po_scalar_or_goto (8, try_ndq
);
6823 po_reg_or_fail (REG_TYPE_NDQ
);
6829 po_scalar_or_goto (8, try_vfd
);
6832 po_reg_or_fail (REG_TYPE_VFD
);
6837 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6838 not careful then bad things might happen. */
6839 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6844 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6847 /* There's a possibility of getting a 64-bit immediate here, so
6848 we need special handling. */
6849 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6852 inst
.error
= _("immediate value is out of range");
6860 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6863 po_imm_or_fail (0, 63, TRUE
);
6868 po_char_or_fail ('[');
6869 po_reg_or_fail (REG_TYPE_RN
);
6870 po_char_or_fail (']');
6876 po_reg_or_fail (REG_TYPE_RN
);
6877 if (skip_past_char (&str
, '!') == SUCCESS
)
6878 inst
.operands
[i
].writeback
= 1;
6882 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6883 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6884 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6885 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6886 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6887 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6888 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6889 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6890 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6891 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6892 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6893 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6895 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6897 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6898 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6900 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6901 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6902 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6903 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6905 /* Immediate variants */
6907 po_char_or_fail ('{');
6908 po_imm_or_fail (0, 255, TRUE
);
6909 po_char_or_fail ('}');
6913 /* The expression parser chokes on a trailing !, so we have
6914 to find it first and zap it. */
6917 while (*s
&& *s
!= ',')
6922 inst
.operands
[i
].writeback
= 1;
6924 po_imm_or_fail (0, 31, TRUE
);
6932 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6937 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6942 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6944 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6946 val
= parse_reloc (&str
);
6949 inst
.error
= _("unrecognized relocation suffix");
6952 else if (val
!= BFD_RELOC_UNUSED
)
6954 inst
.operands
[i
].imm
= val
;
6955 inst
.operands
[i
].hasreloc
= 1;
6960 /* Operand for MOVW or MOVT. */
6962 po_misc_or_fail (parse_half (&str
));
6965 /* Register or expression. */
6966 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6967 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6969 /* Register or immediate. */
6970 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6971 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6973 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6975 if (!is_immediate_prefix (*str
))
6978 val
= parse_fpa_immediate (&str
);
6981 /* FPA immediates are encoded as registers 8-15.
6982 parse_fpa_immediate has already applied the offset. */
6983 inst
.operands
[i
].reg
= val
;
6984 inst
.operands
[i
].isreg
= 1;
6987 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6988 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6990 /* Two kinds of register. */
6993 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6995 || (rege
->type
!= REG_TYPE_MMXWR
6996 && rege
->type
!= REG_TYPE_MMXWC
6997 && rege
->type
!= REG_TYPE_MMXWCG
))
6999 inst
.error
= _("iWMMXt data or control register expected");
7002 inst
.operands
[i
].reg
= rege
->number
;
7003 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7009 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7011 || (rege
->type
!= REG_TYPE_MMXWC
7012 && rege
->type
!= REG_TYPE_MMXWCG
))
7014 inst
.error
= _("iWMMXt control register expected");
7017 inst
.operands
[i
].reg
= rege
->number
;
7018 inst
.operands
[i
].isreg
= 1;
7023 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7024 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7025 case OP_oROR
: val
= parse_ror (&str
); break;
7026 case OP_COND
: val
= parse_cond (&str
); break;
7027 case OP_oBARRIER_I15
:
7028 po_barrier_or_imm (str
); break;
7030 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7036 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7037 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7039 inst
.error
= _("Banked registers are not available with this "
7045 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7049 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7052 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7054 if (strncasecmp (str
, "APSR_", 5) == 0)
7061 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7062 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7063 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7064 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7065 default: found
= 16;
7069 inst
.operands
[i
].isvec
= 1;
7070 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7071 inst
.operands
[i
].reg
= REG_PC
;
7078 po_misc_or_fail (parse_tb (&str
));
7081 /* Register lists. */
7083 val
= parse_reg_list (&str
);
7086 inst
.operands
[i
].writeback
= 1;
7092 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7096 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7100 /* Allow Q registers too. */
7101 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7106 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7108 inst
.operands
[i
].issingle
= 1;
7113 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7118 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7119 &inst
.operands
[i
].vectype
);
7122 /* Addressing modes */
7124 po_misc_or_fail (parse_address (&str
, i
));
7128 po_misc_or_fail_no_backtrack (
7129 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7133 po_misc_or_fail_no_backtrack (
7134 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7138 po_misc_or_fail_no_backtrack (
7139 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7143 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7147 po_misc_or_fail_no_backtrack (
7148 parse_shifter_operand_group_reloc (&str
, i
));
7152 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7156 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7160 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7164 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7167 /* Various value-based sanity checks and shared operations. We
7168 do not signal immediate failures for the register constraints;
7169 this allows a syntax error to take precedence. */
7170 switch (op_parse_code
)
7178 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7179 inst
.error
= BAD_PC
;
7184 if (inst
.operands
[i
].isreg
)
7186 if (inst
.operands
[i
].reg
== REG_PC
)
7187 inst
.error
= BAD_PC
;
7188 else if (inst
.operands
[i
].reg
== REG_SP
)
7189 inst
.error
= BAD_SP
;
7194 if (inst
.operands
[i
].isreg
7195 && inst
.operands
[i
].reg
== REG_PC
7196 && (inst
.operands
[i
].writeback
|| thumb
))
7197 inst
.error
= BAD_PC
;
7206 case OP_oBARRIER_I15
:
7215 inst
.operands
[i
].imm
= val
;
7222 /* If we get here, this operand was successfully parsed. */
7223 inst
.operands
[i
].present
= 1;
7227 inst
.error
= BAD_ARGS
;
7232 /* The parse routine should already have set inst.error, but set a
7233 default here just in case. */
7235 inst
.error
= _("syntax error");
7239 /* Do not backtrack over a trailing optional argument that
7240 absorbed some text. We will only fail again, with the
7241 'garbage following instruction' error message, which is
7242 probably less helpful than the current one. */
7243 if (backtrack_index
== i
&& backtrack_pos
!= str
7244 && upat
[i
+1] == OP_stop
)
7247 inst
.error
= _("syntax error");
7251 /* Try again, skipping the optional argument at backtrack_pos. */
7252 str
= backtrack_pos
;
7253 inst
.error
= backtrack_error
;
7254 inst
.operands
[backtrack_index
].present
= 0;
7255 i
= backtrack_index
;
7259 /* Check that we have parsed all the arguments. */
7260 if (*str
!= '\0' && !inst
.error
)
7261 inst
.error
= _("garbage following instruction");
7263 return inst
.error
? FAIL
: SUCCESS
;
7266 #undef po_char_or_fail
7267 #undef po_reg_or_fail
7268 #undef po_reg_or_goto
7269 #undef po_imm_or_fail
7270 #undef po_scalar_or_fail
7271 #undef po_barrier_or_imm
7273 /* Shorthand macro for instruction encoding functions issuing errors. */
7274 #define constraint(expr, err) \
7285 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7286 instructions are unpredictable if these registers are used. This
7287 is the BadReg predicate in ARM's Thumb-2 documentation. */
7288 #define reject_bad_reg(reg) \
7290 if (reg == REG_SP || reg == REG_PC) \
7292 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7297 /* If REG is R13 (the stack pointer), warn that its use is
7299 #define warn_deprecated_sp(reg) \
7301 if (warn_on_deprecated && reg == REG_SP) \
7302 as_tsktsk (_("use of r13 is deprecated")); \
7305 /* Functions for operand encoding. ARM, then Thumb. */
7307 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7309 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7311 The only binary encoding difference is the Coprocessor number. Coprocessor
7312 9 is used for half-precision calculations or conversions. The format of the
7313 instruction is the same as the equivalent Coprocessor 10 instruction that
7314 exists for Single-Precision operation. */
7317 do_scalar_fp16_v82_encode (void)
7319 if (inst
.cond
!= COND_ALWAYS
)
7320 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7321 " the behaviour is UNPREDICTABLE"));
7322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7325 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7326 mark_feature_used (&arm_ext_fp16
);
7329 /* If VAL can be encoded in the immediate field of an ARM instruction,
7330 return the encoded form. Otherwise, return FAIL. */
7333 encode_arm_immediate (unsigned int val
)
7340 for (i
= 2; i
< 32; i
+= 2)
7341 if ((a
= rotate_left (val
, i
)) <= 0xff)
7342 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7347 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7348 return the encoded form. Otherwise, return FAIL. */
7350 encode_thumb32_immediate (unsigned int val
)
7357 for (i
= 1; i
<= 24; i
++)
7360 if ((val
& ~(0xff << i
)) == 0)
7361 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7365 if (val
== ((a
<< 16) | a
))
7367 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7371 if (val
== ((a
<< 16) | a
))
7372 return 0x200 | (a
>> 8);
7376 /* Encode a VFP SP or DP register number into inst.instruction. */
7379 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7381 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7384 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7387 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7390 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7395 first_error (_("D register out of range for selected VFP version"));
7403 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7407 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7411 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7415 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7419 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7423 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7431 /* Encode a <shift> in an ARM-format instruction. The immediate,
7432 if any, is handled by md_apply_fix. */
7434 encode_arm_shift (int i
)
7436 /* register-shifted register. */
7437 if (inst
.operands
[i
].immisreg
)
7440 for (index
= 0; index
<= i
; ++index
)
7442 /* Check the operand only when it's presented. In pre-UAL syntax,
7443 if the destination register is the same as the first operand, two
7444 register form of the instruction can be used. */
7445 if (inst
.operands
[index
].present
&& inst
.operands
[index
].isreg
7446 && inst
.operands
[index
].reg
== REG_PC
)
7447 as_warn (UNPRED_REG ("r15"));
7450 if (inst
.operands
[i
].imm
== REG_PC
)
7451 as_warn (UNPRED_REG ("r15"));
7454 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7455 inst
.instruction
|= SHIFT_ROR
<< 5;
7458 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7459 if (inst
.operands
[i
].immisreg
)
7461 inst
.instruction
|= SHIFT_BY_REG
;
7462 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7465 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7470 encode_arm_shifter_operand (int i
)
7472 if (inst
.operands
[i
].isreg
)
7474 inst
.instruction
|= inst
.operands
[i
].reg
;
7475 encode_arm_shift (i
);
7479 inst
.instruction
|= INST_IMMEDIATE
;
7480 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7481 inst
.instruction
|= inst
.operands
[i
].imm
;
7485 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7487 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7490 Generate an error if the operand is not a register. */
7491 constraint (!inst
.operands
[i
].isreg
,
7492 _("Instruction does not support =N addresses"));
7494 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7496 if (inst
.operands
[i
].preind
)
7500 inst
.error
= _("instruction does not accept preindexed addressing");
7503 inst
.instruction
|= PRE_INDEX
;
7504 if (inst
.operands
[i
].writeback
)
7505 inst
.instruction
|= WRITE_BACK
;
7508 else if (inst
.operands
[i
].postind
)
7510 gas_assert (inst
.operands
[i
].writeback
);
7512 inst
.instruction
|= WRITE_BACK
;
7514 else /* unindexed - only for coprocessor */
7516 inst
.error
= _("instruction does not accept unindexed addressing");
7520 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7521 && (((inst
.instruction
& 0x000f0000) >> 16)
7522 == ((inst
.instruction
& 0x0000f000) >> 12)))
7523 as_warn ((inst
.instruction
& LOAD_BIT
)
7524 ? _("destination register same as write-back base")
7525 : _("source register same as write-back base"));
7528 /* inst.operands[i] was set up by parse_address. Encode it into an
7529 ARM-format mode 2 load or store instruction. If is_t is true,
7530 reject forms that cannot be used with a T instruction (i.e. not
7533 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7535 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7537 encode_arm_addr_mode_common (i
, is_t
);
7539 if (inst
.operands
[i
].immisreg
)
7541 constraint ((inst
.operands
[i
].imm
== REG_PC
7542 || (is_pc
&& inst
.operands
[i
].writeback
)),
7544 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7545 inst
.instruction
|= inst
.operands
[i
].imm
;
7546 if (!inst
.operands
[i
].negative
)
7547 inst
.instruction
|= INDEX_UP
;
7548 if (inst
.operands
[i
].shifted
)
7550 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7551 inst
.instruction
|= SHIFT_ROR
<< 5;
7554 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7555 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7559 else /* immediate offset in inst.reloc */
7561 if (is_pc
&& !inst
.reloc
.pc_rel
)
7563 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7565 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7566 cannot use PC in addressing.
7567 PC cannot be used in writeback addressing, either. */
7568 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7571 /* Use of PC in str is deprecated for ARMv7. */
7572 if (warn_on_deprecated
7574 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7575 as_tsktsk (_("use of PC in this instruction is deprecated"));
7578 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7580 /* Prefer + for zero encoded value. */
7581 if (!inst
.operands
[i
].negative
)
7582 inst
.instruction
|= INDEX_UP
;
7583 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7588 /* inst.operands[i] was set up by parse_address. Encode it into an
7589 ARM-format mode 3 load or store instruction. Reject forms that
7590 cannot be used with such instructions. If is_t is true, reject
7591 forms that cannot be used with a T instruction (i.e. not
7594 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7596 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7598 inst
.error
= _("instruction does not accept scaled register index");
7602 encode_arm_addr_mode_common (i
, is_t
);
7604 if (inst
.operands
[i
].immisreg
)
7606 constraint ((inst
.operands
[i
].imm
== REG_PC
7607 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7609 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7611 inst
.instruction
|= inst
.operands
[i
].imm
;
7612 if (!inst
.operands
[i
].negative
)
7613 inst
.instruction
|= INDEX_UP
;
7615 else /* immediate offset in inst.reloc */
7617 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7618 && inst
.operands
[i
].writeback
),
7620 inst
.instruction
|= HWOFFSET_IMM
;
7621 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7623 /* Prefer + for zero encoded value. */
7624 if (!inst
.operands
[i
].negative
)
7625 inst
.instruction
|= INDEX_UP
;
7627 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7632 /* Write immediate bits [7:0] to the following locations:
7634 |28/24|23 19|18 16|15 4|3 0|
7635 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7637 This function is used by VMOV/VMVN/VORR/VBIC. */
7640 neon_write_immbits (unsigned immbits
)
7642 inst
.instruction
|= immbits
& 0xf;
7643 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7644 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7647 /* Invert low-order SIZE bits of XHI:XLO. */
7650 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7652 unsigned immlo
= xlo
? *xlo
: 0;
7653 unsigned immhi
= xhi
? *xhi
: 0;
7658 immlo
= (~immlo
) & 0xff;
7662 immlo
= (~immlo
) & 0xffff;
7666 immhi
= (~immhi
) & 0xffffffff;
7670 immlo
= (~immlo
) & 0xffffffff;
7684 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7688 neon_bits_same_in_bytes (unsigned imm
)
7690 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7691 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7692 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7693 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7696 /* For immediate of above form, return 0bABCD. */
7699 neon_squash_bits (unsigned imm
)
7701 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7702 | ((imm
& 0x01000000) >> 21);
7705 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7708 neon_qfloat_bits (unsigned imm
)
7710 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7713 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7714 the instruction. *OP is passed as the initial value of the op field, and
7715 may be set to a different value depending on the constant (i.e.
7716 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7717 MVN). If the immediate looks like a repeated pattern then also
7718 try smaller element sizes. */
7721 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7722 unsigned *immbits
, int *op
, int size
,
7723 enum neon_el_type type
)
7725 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7727 if (type
== NT_float
&& !float_p
)
7730 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7732 if (size
!= 32 || *op
== 1)
7734 *immbits
= neon_qfloat_bits (immlo
);
7740 if (neon_bits_same_in_bytes (immhi
)
7741 && neon_bits_same_in_bytes (immlo
))
7745 *immbits
= (neon_squash_bits (immhi
) << 4)
7746 | neon_squash_bits (immlo
);
7757 if (immlo
== (immlo
& 0x000000ff))
7762 else if (immlo
== (immlo
& 0x0000ff00))
7764 *immbits
= immlo
>> 8;
7767 else if (immlo
== (immlo
& 0x00ff0000))
7769 *immbits
= immlo
>> 16;
7772 else if (immlo
== (immlo
& 0xff000000))
7774 *immbits
= immlo
>> 24;
7777 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7779 *immbits
= (immlo
>> 8) & 0xff;
7782 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7784 *immbits
= (immlo
>> 16) & 0xff;
7788 if ((immlo
& 0xffff) != (immlo
>> 16))
7795 if (immlo
== (immlo
& 0x000000ff))
7800 else if (immlo
== (immlo
& 0x0000ff00))
7802 *immbits
= immlo
>> 8;
7806 if ((immlo
& 0xff) != (immlo
>> 8))
7811 if (immlo
== (immlo
& 0x000000ff))
7813 /* Don't allow MVN with 8-bit immediate. */
7823 #if defined BFD_HOST_64_BIT
7824 /* Returns TRUE if double precision value V may be cast
7825 to single precision without loss of accuracy. */
7828 is_double_a_single (bfd_int64_t v
)
7830 int exp
= (int)((v
>> 52) & 0x7FF);
7831 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7833 return (exp
== 0 || exp
== 0x7FF
7834 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7835 && (mantissa
& 0x1FFFFFFFl
) == 0;
7838 /* Returns a double precision value casted to single precision
7839 (ignoring the least significant bits in exponent and mantissa). */
7842 double_to_single (bfd_int64_t v
)
7844 int sign
= (int) ((v
>> 63) & 1l);
7845 int exp
= (int) ((v
>> 52) & 0x7FF);
7846 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7852 exp
= exp
- 1023 + 127;
7861 /* No denormalized numbers. */
7867 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7869 #endif /* BFD_HOST_64_BIT */
7878 static void do_vfp_nsyn_opcode (const char *);
7880 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7881 Determine whether it can be performed with a move instruction; if
7882 it can, convert inst.instruction to that move instruction and
7883 return TRUE; if it can't, convert inst.instruction to a literal-pool
7884 load and return FALSE. If this is not a valid thing to do in the
7885 current context, set inst.error and return TRUE.
7887 inst.operands[i] describes the destination register. */
7890 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7893 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7894 bfd_boolean arm_p
= (t
== CONST_ARM
);
7897 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7901 if ((inst
.instruction
& tbit
) == 0)
7903 inst
.error
= _("invalid pseudo operation");
7907 if (inst
.reloc
.exp
.X_op
!= O_constant
7908 && inst
.reloc
.exp
.X_op
!= O_symbol
7909 && inst
.reloc
.exp
.X_op
!= O_big
)
7911 inst
.error
= _("constant expression expected");
7915 if (inst
.reloc
.exp
.X_op
== O_constant
7916 || inst
.reloc
.exp
.X_op
== O_big
)
7918 #if defined BFD_HOST_64_BIT
7923 if (inst
.reloc
.exp
.X_op
== O_big
)
7925 LITTLENUM_TYPE w
[X_PRECISION
];
7928 if (inst
.reloc
.exp
.X_add_number
== -1)
7930 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7932 /* FIXME: Should we check words w[2..5] ? */
7937 #if defined BFD_HOST_64_BIT
7939 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7940 << LITTLENUM_NUMBER_OF_BITS
)
7941 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7942 << LITTLENUM_NUMBER_OF_BITS
)
7943 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7944 << LITTLENUM_NUMBER_OF_BITS
)
7945 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7947 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7948 | (l
[0] & LITTLENUM_MASK
);
7952 v
= inst
.reloc
.exp
.X_add_number
;
7954 if (!inst
.operands
[i
].issingle
)
7958 /* This can be encoded only for a low register. */
7959 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7961 /* This can be done with a mov(1) instruction. */
7962 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7963 inst
.instruction
|= v
;
7967 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7968 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7970 /* Check if on thumb2 it can be done with a mov.w, mvn or
7971 movw instruction. */
7972 unsigned int newimm
;
7973 bfd_boolean isNegated
;
7975 newimm
= encode_thumb32_immediate (v
);
7976 if (newimm
!= (unsigned int) FAIL
)
7980 newimm
= encode_thumb32_immediate (~v
);
7981 if (newimm
!= (unsigned int) FAIL
)
7985 /* The number can be loaded with a mov.w or mvn
7987 if (newimm
!= (unsigned int) FAIL
7988 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7990 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7991 | (inst
.operands
[i
].reg
<< 8));
7992 /* Change to MOVN. */
7993 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7994 inst
.instruction
|= (newimm
& 0x800) << 15;
7995 inst
.instruction
|= (newimm
& 0x700) << 4;
7996 inst
.instruction
|= (newimm
& 0x0ff);
7999 /* The number can be loaded with a movw instruction. */
8000 else if ((v
& ~0xFFFF) == 0
8001 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8003 int imm
= v
& 0xFFFF;
8005 inst
.instruction
= 0xf2400000; /* MOVW. */
8006 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8007 inst
.instruction
|= (imm
& 0xf000) << 4;
8008 inst
.instruction
|= (imm
& 0x0800) << 15;
8009 inst
.instruction
|= (imm
& 0x0700) << 4;
8010 inst
.instruction
|= (imm
& 0x00ff);
8017 int value
= encode_arm_immediate (v
);
8021 /* This can be done with a mov instruction. */
8022 inst
.instruction
&= LITERAL_MASK
;
8023 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8024 inst
.instruction
|= value
& 0xfff;
8028 value
= encode_arm_immediate (~ v
);
8031 /* This can be done with a mvn instruction. */
8032 inst
.instruction
&= LITERAL_MASK
;
8033 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8034 inst
.instruction
|= value
& 0xfff;
8038 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8041 unsigned immbits
= 0;
8042 unsigned immlo
= inst
.operands
[1].imm
;
8043 unsigned immhi
= inst
.operands
[1].regisimm
8044 ? inst
.operands
[1].reg
8045 : inst
.reloc
.exp
.X_unsigned
8047 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8048 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8049 &op
, 64, NT_invtype
);
8053 neon_invert_size (&immlo
, &immhi
, 64);
8055 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8056 &op
, 64, NT_invtype
);
8061 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8067 /* Fill other bits in vmov encoding for both thumb and arm. */
8069 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8071 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8072 neon_write_immbits (immbits
);
8080 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8081 if (inst
.operands
[i
].issingle
8082 && is_quarter_float (inst
.operands
[1].imm
)
8083 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8085 inst
.operands
[1].imm
=
8086 neon_qfloat_bits (v
);
8087 do_vfp_nsyn_opcode ("fconsts");
8091 /* If our host does not support a 64-bit type then we cannot perform
8092 the following optimization. This mean that there will be a
8093 discrepancy between the output produced by an assembler built for
8094 a 32-bit-only host and the output produced from a 64-bit host, but
8095 this cannot be helped. */
8096 #if defined BFD_HOST_64_BIT
8097 else if (!inst
.operands
[1].issingle
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8100 if (is_double_a_single (v
)
8101 && is_quarter_float (double_to_single (v
)))
8103 inst
.operands
[1].imm
=
8104 neon_qfloat_bits (double_to_single (v
));
8105 do_vfp_nsyn_opcode ("fconstd");
8113 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8114 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8117 inst
.operands
[1].reg
= REG_PC
;
8118 inst
.operands
[1].isreg
= 1;
8119 inst
.operands
[1].preind
= 1;
8120 inst
.reloc
.pc_rel
= 1;
8121 inst
.reloc
.type
= (thumb_p
8122 ? BFD_RELOC_ARM_THUMB_OFFSET
8124 ? BFD_RELOC_ARM_HWLITERAL
8125 : BFD_RELOC_ARM_LITERAL
));
8129 /* inst.operands[i] was set up by parse_address. Encode it into an
8130 ARM-format instruction. Reject all forms which cannot be encoded
8131 into a coprocessor load/store instruction. If wb_ok is false,
8132 reject use of writeback; if unind_ok is false, reject use of
8133 unindexed addressing. If reloc_override is not 0, use it instead
8134 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8135 (in which case it is preserved). */
8138 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8140 if (!inst
.operands
[i
].isreg
)
8143 if (! inst
.operands
[0].isvec
)
8145 inst
.error
= _("invalid co-processor operand");
8148 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8152 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8154 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8156 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8158 gas_assert (!inst
.operands
[i
].writeback
);
8161 inst
.error
= _("instruction does not support unindexed addressing");
8164 inst
.instruction
|= inst
.operands
[i
].imm
;
8165 inst
.instruction
|= INDEX_UP
;
8169 if (inst
.operands
[i
].preind
)
8170 inst
.instruction
|= PRE_INDEX
;
8172 if (inst
.operands
[i
].writeback
)
8174 if (inst
.operands
[i
].reg
== REG_PC
)
8176 inst
.error
= _("pc may not be used with write-back");
8181 inst
.error
= _("instruction does not support writeback");
8184 inst
.instruction
|= WRITE_BACK
;
8188 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8189 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8190 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8191 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8194 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8196 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8199 /* Prefer + for zero encoded value. */
8200 if (!inst
.operands
[i
].negative
)
8201 inst
.instruction
|= INDEX_UP
;
8206 /* Functions for instruction encoding, sorted by sub-architecture.
8207 First some generics; their names are taken from the conventional
8208 bit positions for register arguments in ARM format instructions. */
8218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8224 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8231 inst
.instruction
|= inst
.operands
[1].reg
;
8237 inst
.instruction
|= inst
.operands
[0].reg
;
8238 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8251 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8252 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8258 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8263 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8265 if (ARM_CPU_IS_ANY (cpu_variant
))
8267 as_tsktsk ("%s", msg
);
8270 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8282 unsigned Rn
= inst
.operands
[2].reg
;
8283 /* Enforce restrictions on SWP instruction. */
8284 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8286 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8287 _("Rn must not overlap other operands"));
8289 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8291 if (!check_obsolete (&arm_ext_v8
,
8292 _("swp{b} use is obsoleted for ARMv8 and later"))
8293 && warn_on_deprecated
8294 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8295 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8298 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8299 inst
.instruction
|= inst
.operands
[1].reg
;
8300 inst
.instruction
|= Rn
<< 16;
8306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8308 inst
.instruction
|= inst
.operands
[2].reg
;
8314 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8315 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8316 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8317 || inst
.reloc
.exp
.X_add_number
!= 0),
8319 inst
.instruction
|= inst
.operands
[0].reg
;
8320 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8327 inst
.instruction
|= inst
.operands
[0].imm
;
8333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8334 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8337 /* ARM instructions, in alphabetical order by function name (except
8338 that wrapper functions appear immediately after the function they
8341 /* This is a pseudo-op of the form "adr rd, label" to be converted
8342 into a relative address of the form "add rd, pc, #label-.-8". */
8347 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8349 /* Frag hacking will turn this into a sub instruction if the offset turns
8350 out to be negative. */
8351 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8352 inst
.reloc
.pc_rel
= 1;
8353 inst
.reloc
.exp
.X_add_number
-= 8;
8356 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8357 into a relative address of the form:
8358 add rd, pc, #low(label-.-8)"
8359 add rd, rd, #high(label-.-8)" */
8364 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8366 /* Frag hacking will turn this into a sub instruction if the offset turns
8367 out to be negative. */
8368 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8369 inst
.reloc
.pc_rel
= 1;
8370 inst
.size
= INSN_SIZE
* 2;
8371 inst
.reloc
.exp
.X_add_number
-= 8;
8377 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8378 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8380 if (!inst
.operands
[1].present
)
8381 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8383 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8384 encode_arm_shifter_operand (2);
8390 if (inst
.operands
[0].present
)
8391 inst
.instruction
|= inst
.operands
[0].imm
;
8393 inst
.instruction
|= 0xf;
8399 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8400 constraint (msb
> 32, _("bit-field extends past end of register"));
8401 /* The instruction encoding stores the LSB and MSB,
8402 not the LSB and width. */
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8404 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8405 inst
.instruction
|= (msb
- 1) << 16;
8413 /* #0 in second position is alternative syntax for bfc, which is
8414 the same instruction but with REG_PC in the Rm field. */
8415 if (!inst
.operands
[1].isreg
)
8416 inst
.operands
[1].reg
= REG_PC
;
8418 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8419 constraint (msb
> 32, _("bit-field extends past end of register"));
8420 /* The instruction encoding stores the LSB and MSB,
8421 not the LSB and width. */
8422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8423 inst
.instruction
|= inst
.operands
[1].reg
;
8424 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8425 inst
.instruction
|= (msb
- 1) << 16;
8431 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8432 _("bit-field extends past end of register"));
8433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8434 inst
.instruction
|= inst
.operands
[1].reg
;
8435 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8436 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8439 /* ARM V5 breakpoint instruction (argument parse)
8440 BKPT <16 bit unsigned immediate>
8441 Instruction is not conditional.
8442 The bit pattern given in insns[] has the COND_ALWAYS condition,
8443 and it is an error if the caller tried to override that. */
8448 /* Top 12 of 16 bits to bits 19:8. */
8449 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8451 /* Bottom 4 of 16 bits to bits 3:0. */
8452 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8456 encode_branch (int default_reloc
)
8458 if (inst
.operands
[0].hasreloc
)
8460 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8461 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8462 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8463 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8464 ? BFD_RELOC_ARM_PLT32
8465 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8468 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8469 inst
.reloc
.pc_rel
= 1;
8476 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8477 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8480 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8487 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8489 if (inst
.cond
== COND_ALWAYS
)
8490 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8492 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8496 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8499 /* ARM V5 branch-link-exchange instruction (argument parse)
8500 BLX <target_addr> ie BLX(1)
8501 BLX{<condition>} <Rm> ie BLX(2)
8502 Unfortunately, there are two different opcodes for this mnemonic.
8503 So, the insns[].value is not used, and the code here zaps values
8504 into inst.instruction.
8505 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8510 if (inst
.operands
[0].isreg
)
8512 /* Arg is a register; the opcode provided by insns[] is correct.
8513 It is not illegal to do "blx pc", just useless. */
8514 if (inst
.operands
[0].reg
== REG_PC
)
8515 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8517 inst
.instruction
|= inst
.operands
[0].reg
;
8521 /* Arg is an address; this instruction cannot be executed
8522 conditionally, and the opcode must be adjusted.
8523 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8524 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8525 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8526 inst
.instruction
= 0xfa000000;
8527 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8534 bfd_boolean want_reloc
;
8536 if (inst
.operands
[0].reg
== REG_PC
)
8537 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8539 inst
.instruction
|= inst
.operands
[0].reg
;
8540 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8541 it is for ARMv4t or earlier. */
8542 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8543 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8547 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8552 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8556 /* ARM v5TEJ. Jump to Jazelle code. */
8561 if (inst
.operands
[0].reg
== REG_PC
)
8562 as_tsktsk (_("use of r15 in bxj is not really useful"));
8564 inst
.instruction
|= inst
.operands
[0].reg
;
8567 /* Co-processor data operation:
8568 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8569 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8574 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8575 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8576 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[4].reg
;
8578 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8584 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8585 encode_arm_shifter_operand (1);
8588 /* Transfer between coprocessor and ARM registers.
8589 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8594 No special properties. */
8596 struct deprecated_coproc_regs_s
8603 arm_feature_set deprecated
;
8604 arm_feature_set obsoleted
;
8605 const char *dep_msg
;
8606 const char *obs_msg
;
8609 #define DEPR_ACCESS_V8 \
8610 N_("This coprocessor register access is deprecated in ARMv8")
8612 /* Table of all deprecated coprocessor registers. */
8613 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8615 {15, 0, 7, 10, 5, /* CP15DMB. */
8616 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8617 DEPR_ACCESS_V8
, NULL
},
8618 {15, 0, 7, 10, 4, /* CP15DSB. */
8619 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8620 DEPR_ACCESS_V8
, NULL
},
8621 {15, 0, 7, 5, 4, /* CP15ISB. */
8622 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8623 DEPR_ACCESS_V8
, NULL
},
8624 {14, 6, 1, 0, 0, /* TEEHBR. */
8625 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8626 DEPR_ACCESS_V8
, NULL
},
8627 {14, 6, 0, 0, 0, /* TEECR. */
8628 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8629 DEPR_ACCESS_V8
, NULL
},
8632 #undef DEPR_ACCESS_V8
8634 static const size_t deprecated_coproc_reg_count
=
8635 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8643 Rd
= inst
.operands
[2].reg
;
8646 if (inst
.instruction
== 0xee000010
8647 || inst
.instruction
== 0xfe000010)
8649 reject_bad_reg (Rd
);
8652 constraint (Rd
== REG_SP
, BAD_SP
);
8657 if (inst
.instruction
== 0xe000010)
8658 constraint (Rd
== REG_PC
, BAD_PC
);
8661 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8663 const struct deprecated_coproc_regs_s
*r
=
8664 deprecated_coproc_regs
+ i
;
8666 if (inst
.operands
[0].reg
== r
->cp
8667 && inst
.operands
[1].imm
== r
->opc1
8668 && inst
.operands
[3].reg
== r
->crn
8669 && inst
.operands
[4].reg
== r
->crm
8670 && inst
.operands
[5].imm
== r
->opc2
)
8672 if (! ARM_CPU_IS_ANY (cpu_variant
)
8673 && warn_on_deprecated
8674 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8675 as_tsktsk ("%s", r
->dep_msg
);
8679 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8680 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8681 inst
.instruction
|= Rd
<< 12;
8682 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8683 inst
.instruction
|= inst
.operands
[4].reg
;
8684 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8687 /* Transfer between coprocessor register and pair of ARM registers.
8688 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8693 Two XScale instructions are special cases of these:
8695 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8696 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8698 Result unpredictable if Rd or Rn is R15. */
8705 Rd
= inst
.operands
[2].reg
;
8706 Rn
= inst
.operands
[3].reg
;
8710 reject_bad_reg (Rd
);
8711 reject_bad_reg (Rn
);
8715 constraint (Rd
== REG_PC
, BAD_PC
);
8716 constraint (Rn
== REG_PC
, BAD_PC
);
8719 /* Only check the MRRC{2} variants. */
8720 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8722 /* If Rd == Rn, error that the operation is
8723 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8724 constraint (Rd
== Rn
, BAD_OVERLAP
);
8727 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8728 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8729 inst
.instruction
|= Rd
<< 12;
8730 inst
.instruction
|= Rn
<< 16;
8731 inst
.instruction
|= inst
.operands
[4].reg
;
8737 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8738 if (inst
.operands
[1].present
)
8740 inst
.instruction
|= CPSI_MMOD
;
8741 inst
.instruction
|= inst
.operands
[1].imm
;
8748 inst
.instruction
|= inst
.operands
[0].imm
;
8754 unsigned Rd
, Rn
, Rm
;
8756 Rd
= inst
.operands
[0].reg
;
8757 Rn
= (inst
.operands
[1].present
8758 ? inst
.operands
[1].reg
: Rd
);
8759 Rm
= inst
.operands
[2].reg
;
8761 constraint ((Rd
== REG_PC
), BAD_PC
);
8762 constraint ((Rn
== REG_PC
), BAD_PC
);
8763 constraint ((Rm
== REG_PC
), BAD_PC
);
8765 inst
.instruction
|= Rd
<< 16;
8766 inst
.instruction
|= Rn
<< 0;
8767 inst
.instruction
|= Rm
<< 8;
8773 /* There is no IT instruction in ARM mode. We
8774 process it to do the validation as if in
8775 thumb mode, just in case the code gets
8776 assembled for thumb using the unified syntax. */
8781 set_it_insn_type (IT_INSN
);
8782 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8783 now_it
.cc
= inst
.operands
[0].imm
;
8787 /* If there is only one register in the register list,
8788 then return its register number. Otherwise return -1. */
8790 only_one_reg_in_list (int range
)
8792 int i
= ffs (range
) - 1;
8793 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8797 encode_ldmstm(int from_push_pop_mnem
)
8799 int base_reg
= inst
.operands
[0].reg
;
8800 int range
= inst
.operands
[1].imm
;
8803 inst
.instruction
|= base_reg
<< 16;
8804 inst
.instruction
|= range
;
8806 if (inst
.operands
[1].writeback
)
8807 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8809 if (inst
.operands
[0].writeback
)
8811 inst
.instruction
|= WRITE_BACK
;
8812 /* Check for unpredictable uses of writeback. */
8813 if (inst
.instruction
& LOAD_BIT
)
8815 /* Not allowed in LDM type 2. */
8816 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8817 && ((range
& (1 << REG_PC
)) == 0))
8818 as_warn (_("writeback of base register is UNPREDICTABLE"));
8819 /* Only allowed if base reg not in list for other types. */
8820 else if (range
& (1 << base_reg
))
8821 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8825 /* Not allowed for type 2. */
8826 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8827 as_warn (_("writeback of base register is UNPREDICTABLE"));
8828 /* Only allowed if base reg not in list, or first in list. */
8829 else if ((range
& (1 << base_reg
))
8830 && (range
& ((1 << base_reg
) - 1)))
8831 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8835 /* If PUSH/POP has only one register, then use the A2 encoding. */
8836 one_reg
= only_one_reg_in_list (range
);
8837 if (from_push_pop_mnem
&& one_reg
>= 0)
8839 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8841 inst
.instruction
&= A_COND_MASK
;
8842 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8843 inst
.instruction
|= one_reg
<< 12;
8850 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8853 /* ARMv5TE load-consecutive (argument parse)
8862 constraint (inst
.operands
[0].reg
% 2 != 0,
8863 _("first transfer register must be even"));
8864 constraint (inst
.operands
[1].present
8865 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8866 _("can only transfer two consecutive registers"));
8867 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8868 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8870 if (!inst
.operands
[1].present
)
8871 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8873 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8874 register and the first register written; we have to diagnose
8875 overlap between the base and the second register written here. */
8877 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8878 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8879 as_warn (_("base register written back, and overlaps "
8880 "second transfer register"));
8882 if (!(inst
.instruction
& V4_STR_BIT
))
8884 /* For an index-register load, the index register must not overlap the
8885 destination (even if not write-back). */
8886 if (inst
.operands
[2].immisreg
8887 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8888 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8889 as_warn (_("index register overlaps transfer register"));
8891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8892 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8898 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8899 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8900 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8901 || inst
.operands
[1].negative
8902 /* This can arise if the programmer has written
8904 or if they have mistakenly used a register name as the last
8907 It is very difficult to distinguish between these two cases
8908 because "rX" might actually be a label. ie the register
8909 name has been occluded by a symbol of the same name. So we
8910 just generate a general 'bad addressing mode' type error
8911 message and leave it up to the programmer to discover the
8912 true cause and fix their mistake. */
8913 || (inst
.operands
[1].reg
== REG_PC
),
8916 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8917 || inst
.reloc
.exp
.X_add_number
!= 0,
8918 _("offset must be zero in ARM encoding"));
8920 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8924 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8930 constraint (inst
.operands
[0].reg
% 2 != 0,
8931 _("even register required"));
8932 constraint (inst
.operands
[1].present
8933 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8934 _("can only load two consecutive registers"));
8935 /* If op 1 were present and equal to PC, this function wouldn't
8936 have been called in the first place. */
8937 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8940 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8943 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8944 which is not a multiple of four is UNPREDICTABLE. */
8946 check_ldr_r15_aligned (void)
8948 constraint (!(inst
.operands
[1].immisreg
)
8949 && (inst
.operands
[0].reg
== REG_PC
8950 && inst
.operands
[1].reg
== REG_PC
8951 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8952 _("ldr to register 15 must be 4-byte alligned"));
8958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8959 if (!inst
.operands
[1].isreg
)
8960 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8962 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8963 check_ldr_r15_aligned ();
8969 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8971 if (inst
.operands
[1].preind
)
8973 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8974 || inst
.reloc
.exp
.X_add_number
!= 0,
8975 _("this instruction requires a post-indexed address"));
8977 inst
.operands
[1].preind
= 0;
8978 inst
.operands
[1].postind
= 1;
8979 inst
.operands
[1].writeback
= 1;
8981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8982 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8985 /* Halfword and signed-byte load/store operations. */
8990 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 if (!inst
.operands
[1].isreg
)
8993 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8995 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9001 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9003 if (inst
.operands
[1].preind
)
9005 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9006 || inst
.reloc
.exp
.X_add_number
!= 0,
9007 _("this instruction requires a post-indexed address"));
9009 inst
.operands
[1].preind
= 0;
9010 inst
.operands
[1].postind
= 1;
9011 inst
.operands
[1].writeback
= 1;
9013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9014 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9017 /* Co-processor register load/store.
9018 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9022 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9024 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9030 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9031 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9032 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9033 && !(inst
.instruction
& 0x00400000))
9034 as_tsktsk (_("Rd and Rm should be different in mla"));
9036 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9037 inst
.instruction
|= inst
.operands
[1].reg
;
9038 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9039 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9045 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9046 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9049 encode_arm_shifter_operand (1);
9052 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9059 top
= (inst
.instruction
& 0x00400000) != 0;
9060 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9061 _(":lower16: not allowed this instruction"));
9062 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9063 _(":upper16: not allowed instruction"));
9064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9065 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9067 imm
= inst
.reloc
.exp
.X_add_number
;
9068 /* The value is in two pieces: 0:11, 16:19. */
9069 inst
.instruction
|= (imm
& 0x00000fff);
9070 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9075 do_vfp_nsyn_mrs (void)
9077 if (inst
.operands
[0].isvec
)
9079 if (inst
.operands
[1].reg
!= 1)
9080 first_error (_("operand 1 must be FPSCR"));
9081 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9082 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9083 do_vfp_nsyn_opcode ("fmstat");
9085 else if (inst
.operands
[1].isvec
)
9086 do_vfp_nsyn_opcode ("fmrx");
9094 do_vfp_nsyn_msr (void)
9096 if (inst
.operands
[0].isvec
)
9097 do_vfp_nsyn_opcode ("fmxr");
9107 unsigned Rt
= inst
.operands
[0].reg
;
9109 if (thumb_mode
&& Rt
== REG_SP
)
9111 inst
.error
= BAD_SP
;
9115 /* APSR_ sets isvec. All other refs to PC are illegal. */
9116 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9118 inst
.error
= BAD_PC
;
9122 /* If we get through parsing the register name, we just insert the number
9123 generated into the instruction without further validation. */
9124 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9125 inst
.instruction
|= (Rt
<< 12);
9131 unsigned Rt
= inst
.operands
[1].reg
;
9134 reject_bad_reg (Rt
);
9135 else if (Rt
== REG_PC
)
9137 inst
.error
= BAD_PC
;
9141 /* If we get through parsing the register name, we just insert the number
9142 generated into the instruction without further validation. */
9143 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9144 inst
.instruction
|= (Rt
<< 12);
9152 if (do_vfp_nsyn_mrs () == SUCCESS
)
9155 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9158 if (inst
.operands
[1].isreg
)
9160 br
= inst
.operands
[1].reg
;
9161 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9162 as_bad (_("bad register for mrs"));
9166 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9167 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9169 _("'APSR', 'CPSR' or 'SPSR' expected"));
9170 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9173 inst
.instruction
|= br
;
9176 /* Two possible forms:
9177 "{C|S}PSR_<field>, Rm",
9178 "{C|S}PSR_f, #expression". */
9183 if (do_vfp_nsyn_msr () == SUCCESS
)
9186 inst
.instruction
|= inst
.operands
[0].imm
;
9187 if (inst
.operands
[1].isreg
)
9188 inst
.instruction
|= inst
.operands
[1].reg
;
9191 inst
.instruction
|= INST_IMMEDIATE
;
9192 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9193 inst
.reloc
.pc_rel
= 0;
9200 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9202 if (!inst
.operands
[2].present
)
9203 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9204 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9205 inst
.instruction
|= inst
.operands
[1].reg
;
9206 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9208 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9209 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9210 as_tsktsk (_("Rd and Rm should be different in mul"));
9213 /* Long Multiply Parser
9214 UMULL RdLo, RdHi, Rm, Rs
9215 SMULL RdLo, RdHi, Rm, Rs
9216 UMLAL RdLo, RdHi, Rm, Rs
9217 SMLAL RdLo, RdHi, Rm, Rs. */
9222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9223 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9224 inst
.instruction
|= inst
.operands
[2].reg
;
9225 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9227 /* rdhi and rdlo must be different. */
9228 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9229 as_tsktsk (_("rdhi and rdlo must be different"));
9231 /* rdhi, rdlo and rm must all be different before armv6. */
9232 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9233 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9234 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9235 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9241 if (inst
.operands
[0].present
9242 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9244 /* Architectural NOP hints are CPSR sets with no bits selected. */
9245 inst
.instruction
&= 0xf0000000;
9246 inst
.instruction
|= 0x0320f000;
9247 if (inst
.operands
[0].present
)
9248 inst
.instruction
|= inst
.operands
[0].imm
;
9252 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9253 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9254 Condition defaults to COND_ALWAYS.
9255 Error if Rd, Rn or Rm are R15. */
9260 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9261 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9262 inst
.instruction
|= inst
.operands
[2].reg
;
9263 if (inst
.operands
[3].present
)
9264 encode_arm_shift (3);
9267 /* ARM V6 PKHTB (Argument Parse). */
9272 if (!inst
.operands
[3].present
)
9274 /* If the shift specifier is omitted, turn the instruction
9275 into pkhbt rd, rm, rn. */
9276 inst
.instruction
&= 0xfff00010;
9277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9278 inst
.instruction
|= inst
.operands
[1].reg
;
9279 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9284 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9285 inst
.instruction
|= inst
.operands
[2].reg
;
9286 encode_arm_shift (3);
9290 /* ARMv5TE: Preload-Cache
9291 MP Extensions: Preload for write
9295 Syntactically, like LDR with B=1, W=0, L=1. */
9300 constraint (!inst
.operands
[0].isreg
,
9301 _("'[' expected after PLD mnemonic"));
9302 constraint (inst
.operands
[0].postind
,
9303 _("post-indexed expression used in preload instruction"));
9304 constraint (inst
.operands
[0].writeback
,
9305 _("writeback used in preload instruction"));
9306 constraint (!inst
.operands
[0].preind
,
9307 _("unindexed addressing used in preload instruction"));
9308 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9311 /* ARMv7: PLI <addr_mode> */
9315 constraint (!inst
.operands
[0].isreg
,
9316 _("'[' expected after PLI mnemonic"));
9317 constraint (inst
.operands
[0].postind
,
9318 _("post-indexed expression used in preload instruction"));
9319 constraint (inst
.operands
[0].writeback
,
9320 _("writeback used in preload instruction"));
9321 constraint (!inst
.operands
[0].preind
,
9322 _("unindexed addressing used in preload instruction"));
9323 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9324 inst
.instruction
&= ~PRE_INDEX
;
9330 constraint (inst
.operands
[0].writeback
,
9331 _("push/pop do not support {reglist}^"));
9332 inst
.operands
[1] = inst
.operands
[0];
9333 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9334 inst
.operands
[0].isreg
= 1;
9335 inst
.operands
[0].writeback
= 1;
9336 inst
.operands
[0].reg
= REG_SP
;
9337 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9340 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9341 word at the specified address and the following word
9343 Unconditionally executed.
9344 Error if Rn is R15. */
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9350 if (inst
.operands
[0].writeback
)
9351 inst
.instruction
|= WRITE_BACK
;
9354 /* ARM V6 ssat (argument parse). */
9359 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9360 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9361 inst
.instruction
|= inst
.operands
[2].reg
;
9363 if (inst
.operands
[3].present
)
9364 encode_arm_shift (3);
9367 /* ARM V6 usat (argument parse). */
9372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9373 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9374 inst
.instruction
|= inst
.operands
[2].reg
;
9376 if (inst
.operands
[3].present
)
9377 encode_arm_shift (3);
9380 /* ARM V6 ssat16 (argument parse). */
9385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9386 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9387 inst
.instruction
|= inst
.operands
[2].reg
;
9393 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9394 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9395 inst
.instruction
|= inst
.operands
[2].reg
;
9398 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9399 preserving the other bits.
9401 setend <endian_specifier>, where <endian_specifier> is either
9407 if (warn_on_deprecated
9408 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9409 as_tsktsk (_("setend use is deprecated for ARMv8"));
9411 if (inst
.operands
[0].imm
)
9412 inst
.instruction
|= 0x200;
9418 unsigned int Rm
= (inst
.operands
[1].present
9419 ? inst
.operands
[1].reg
9420 : inst
.operands
[0].reg
);
9422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9423 inst
.instruction
|= Rm
;
9424 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9426 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9427 inst
.instruction
|= SHIFT_BY_REG
;
9428 /* PR 12854: Error on extraneous shifts. */
9429 constraint (inst
.operands
[2].shifted
,
9430 _("extraneous shift as part of operand to shift insn"));
9433 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9439 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9440 inst
.reloc
.pc_rel
= 0;
9446 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9447 inst
.reloc
.pc_rel
= 0;
9453 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9454 inst
.reloc
.pc_rel
= 0;
9460 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9461 _("selected processor does not support SETPAN instruction"));
9463 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9469 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9470 _("selected processor does not support SETPAN instruction"));
9472 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9475 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9476 SMLAxy{cond} Rd,Rm,Rs,Rn
9477 SMLAWy{cond} Rd,Rm,Rs,Rn
9478 Error if any register is R15. */
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9484 inst
.instruction
|= inst
.operands
[1].reg
;
9485 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9486 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9489 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9490 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9491 Error if any register is R15.
9492 Warning if Rdlo == Rdhi. */
9497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9498 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9499 inst
.instruction
|= inst
.operands
[2].reg
;
9500 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9502 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9503 as_tsktsk (_("rdhi and rdlo must be different"));
9506 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9507 SMULxy{cond} Rd,Rm,Rs
9508 Error if any register is R15. */
9513 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9514 inst
.instruction
|= inst
.operands
[1].reg
;
9515 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9518 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9519 the same for both ARM and Thumb-2. */
9526 if (inst
.operands
[0].present
)
9528 reg
= inst
.operands
[0].reg
;
9529 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9534 inst
.instruction
|= reg
<< 16;
9535 inst
.instruction
|= inst
.operands
[1].imm
;
9536 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9537 inst
.instruction
|= WRITE_BACK
;
9540 /* ARM V6 strex (argument parse). */
9545 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9546 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9547 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9548 || inst
.operands
[2].negative
9549 /* See comment in do_ldrex(). */
9550 || (inst
.operands
[2].reg
== REG_PC
),
9553 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9554 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9556 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9557 || inst
.reloc
.exp
.X_add_number
!= 0,
9558 _("offset must be zero in ARM encoding"));
9560 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9561 inst
.instruction
|= inst
.operands
[1].reg
;
9562 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9563 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9569 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9570 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9571 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9572 || inst
.operands
[2].negative
,
9575 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9576 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9584 constraint (inst
.operands
[1].reg
% 2 != 0,
9585 _("even register required"));
9586 constraint (inst
.operands
[2].present
9587 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9588 _("can only store two consecutive registers"));
9589 /* If op 2 were present and equal to PC, this function wouldn't
9590 have been called in the first place. */
9591 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9593 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9594 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9595 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9598 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9599 inst
.instruction
|= inst
.operands
[1].reg
;
9600 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9607 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9608 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9616 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9617 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9622 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9623 extends it to 32-bits, and adds the result to a value in another
9624 register. You can specify a rotation by 0, 8, 16, or 24 bits
9625 before extracting the 16-bit value.
9626 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9627 Condition defaults to COND_ALWAYS.
9628 Error if any register uses R15. */
9633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9634 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9635 inst
.instruction
|= inst
.operands
[2].reg
;
9636 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9641 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9642 Condition defaults to COND_ALWAYS.
9643 Error if any register uses R15. */
9648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9649 inst
.instruction
|= inst
.operands
[1].reg
;
9650 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9653 /* VFP instructions. In a logical order: SP variant first, monad
9654 before dyad, arithmetic then move then load/store. */
9657 do_vfp_sp_monadic (void)
9659 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9660 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9664 do_vfp_sp_dyadic (void)
9666 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9667 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9668 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9672 do_vfp_sp_compare_z (void)
9674 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9678 do_vfp_dp_sp_cvt (void)
9680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9681 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9685 do_vfp_sp_dp_cvt (void)
9687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9692 do_vfp_reg_from_sp (void)
9694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9695 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9699 do_vfp_reg2_from_sp2 (void)
9701 constraint (inst
.operands
[2].imm
!= 2,
9702 _("only two consecutive VFP SP registers allowed here"));
9703 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9704 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9705 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9709 do_vfp_sp_from_reg (void)
9711 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9712 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9716 do_vfp_sp2_from_reg2 (void)
9718 constraint (inst
.operands
[0].imm
!= 2,
9719 _("only two consecutive VFP SP registers allowed here"));
9720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9721 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9722 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9726 do_vfp_sp_ldst (void)
9728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9729 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9733 do_vfp_dp_ldst (void)
9735 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9736 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9741 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9743 if (inst
.operands
[0].writeback
)
9744 inst
.instruction
|= WRITE_BACK
;
9746 constraint (ldstm_type
!= VFP_LDSTMIA
,
9747 _("this addressing mode requires base-register writeback"));
9748 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9749 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9750 inst
.instruction
|= inst
.operands
[1].imm
;
9754 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9758 if (inst
.operands
[0].writeback
)
9759 inst
.instruction
|= WRITE_BACK
;
9761 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9762 _("this addressing mode requires base-register writeback"));
9764 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9765 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9767 count
= inst
.operands
[1].imm
<< 1;
9768 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9771 inst
.instruction
|= count
;
9775 do_vfp_sp_ldstmia (void)
9777 vfp_sp_ldstm (VFP_LDSTMIA
);
9781 do_vfp_sp_ldstmdb (void)
9783 vfp_sp_ldstm (VFP_LDSTMDB
);
9787 do_vfp_dp_ldstmia (void)
9789 vfp_dp_ldstm (VFP_LDSTMIA
);
9793 do_vfp_dp_ldstmdb (void)
9795 vfp_dp_ldstm (VFP_LDSTMDB
);
9799 do_vfp_xp_ldstmia (void)
9801 vfp_dp_ldstm (VFP_LDSTMIAX
);
9805 do_vfp_xp_ldstmdb (void)
9807 vfp_dp_ldstm (VFP_LDSTMDBX
);
9811 do_vfp_dp_rd_rm (void)
9813 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9814 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9818 do_vfp_dp_rn_rd (void)
9820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9821 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9825 do_vfp_dp_rd_rn (void)
9827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9828 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9832 do_vfp_dp_rd_rn_rm (void)
9834 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9835 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9836 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9842 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9846 do_vfp_dp_rm_rd_rn (void)
9848 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9849 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9850 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9853 /* VFPv3 instructions. */
9855 do_vfp_sp_const (void)
9857 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9858 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9859 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9863 do_vfp_dp_const (void)
9865 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9866 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9867 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9871 vfp_conv (int srcsize
)
9873 int immbits
= srcsize
- inst
.operands
[1].imm
;
9875 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9877 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9878 i.e. immbits must be in range 0 - 16. */
9879 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9882 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9884 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9885 i.e. immbits must be in range 0 - 31. */
9886 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9890 inst
.instruction
|= (immbits
& 1) << 5;
9891 inst
.instruction
|= (immbits
>> 1);
9895 do_vfp_sp_conv_16 (void)
9897 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9902 do_vfp_dp_conv_16 (void)
9904 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9909 do_vfp_sp_conv_32 (void)
9911 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9916 do_vfp_dp_conv_32 (void)
9918 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9922 /* FPA instructions. Also in a logical order. */
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9928 inst
.instruction
|= inst
.operands
[1].reg
;
9932 do_fpa_ldmstm (void)
9934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9935 switch (inst
.operands
[1].imm
)
9937 case 1: inst
.instruction
|= CP_T_X
; break;
9938 case 2: inst
.instruction
|= CP_T_Y
; break;
9939 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9944 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9946 /* The instruction specified "ea" or "fd", so we can only accept
9947 [Rn]{!}. The instruction does not really support stacking or
9948 unstacking, so we have to emulate these by setting appropriate
9949 bits and offsets. */
9950 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9951 || inst
.reloc
.exp
.X_add_number
!= 0,
9952 _("this instruction does not support indexing"));
9954 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9955 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9957 if (!(inst
.instruction
& INDEX_UP
))
9958 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9960 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9962 inst
.operands
[2].preind
= 0;
9963 inst
.operands
[2].postind
= 1;
9967 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9970 /* iWMMXt instructions: strictly in alphabetical order. */
9973 do_iwmmxt_tandorc (void)
9975 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9979 do_iwmmxt_textrc (void)
9981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9982 inst
.instruction
|= inst
.operands
[1].imm
;
9986 do_iwmmxt_textrm (void)
9988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9989 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[2].imm
;
9994 do_iwmmxt_tinsr (void)
9996 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9997 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9998 inst
.instruction
|= inst
.operands
[2].imm
;
10002 do_iwmmxt_tmia (void)
10004 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10005 inst
.instruction
|= inst
.operands
[1].reg
;
10006 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10010 do_iwmmxt_waligni (void)
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10013 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10014 inst
.instruction
|= inst
.operands
[2].reg
;
10015 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10019 do_iwmmxt_wmerge (void)
10021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10023 inst
.instruction
|= inst
.operands
[2].reg
;
10024 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10028 do_iwmmxt_wmov (void)
10030 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10032 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10033 inst
.instruction
|= inst
.operands
[1].reg
;
10037 do_iwmmxt_wldstbh (void)
10040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10042 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10044 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10045 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10049 do_iwmmxt_wldstw (void)
10051 /* RIWR_RIWC clears .isreg for a control register. */
10052 if (!inst
.operands
[0].isreg
)
10054 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10055 inst
.instruction
|= 0xf0000000;
10058 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10059 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10063 do_iwmmxt_wldstd (void)
10065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10066 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10067 && inst
.operands
[1].immisreg
)
10069 inst
.instruction
&= ~0x1a000ff;
10070 inst
.instruction
|= (0xfU
<< 28);
10071 if (inst
.operands
[1].preind
)
10072 inst
.instruction
|= PRE_INDEX
;
10073 if (!inst
.operands
[1].negative
)
10074 inst
.instruction
|= INDEX_UP
;
10075 if (inst
.operands
[1].writeback
)
10076 inst
.instruction
|= WRITE_BACK
;
10077 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10078 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10079 inst
.instruction
|= inst
.operands
[1].imm
;
10082 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10086 do_iwmmxt_wshufh (void)
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10089 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10090 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10091 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10095 do_iwmmxt_wzero (void)
10097 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10098 inst
.instruction
|= inst
.operands
[0].reg
;
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10104 do_iwmmxt_wrwrwr_or_imm5 (void)
10106 if (inst
.operands
[2].isreg
)
10109 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10110 _("immediate operand requires iWMMXt2"));
10112 if (inst
.operands
[2].imm
== 0)
10114 switch ((inst
.instruction
>> 20) & 0xf)
10120 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10121 inst
.operands
[2].imm
= 16;
10122 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10128 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10129 inst
.operands
[2].imm
= 32;
10130 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10137 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10139 wrn
= (inst
.instruction
>> 16) & 0xf;
10140 inst
.instruction
&= 0xff0fff0f;
10141 inst
.instruction
|= wrn
;
10142 /* Bail out here; the instruction is now assembled. */
10147 /* Map 32 -> 0, etc. */
10148 inst
.operands
[2].imm
&= 0x1f;
10149 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10153 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10154 operations first, then control, shift, and load/store. */
10156 /* Insns like "foo X,Y,Z". */
10159 do_mav_triple (void)
10161 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10162 inst
.instruction
|= inst
.operands
[1].reg
;
10163 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10166 /* Insns like "foo W,X,Y,Z".
10167 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10173 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10174 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10175 inst
.instruction
|= inst
.operands
[3].reg
;
10178 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10180 do_mav_dspsc (void)
10182 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10185 /* Maverick shift immediate instructions.
10186 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10187 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10190 do_mav_shift (void)
10192 int imm
= inst
.operands
[2].imm
;
10194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10195 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10197 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10198 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10199 Bit 4 should be 0. */
10200 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10202 inst
.instruction
|= imm
;
10205 /* XScale instructions. Also sorted arithmetic before move. */
10207 /* Xscale multiply-accumulate (argument parse)
10210 MIAxycc acc0,Rm,Rs. */
10215 inst
.instruction
|= inst
.operands
[1].reg
;
10216 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10219 /* Xscale move-accumulator-register (argument parse)
10221 MARcc acc0,RdLo,RdHi. */
10226 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10227 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10230 /* Xscale move-register-accumulator (argument parse)
10232 MRAcc RdLo,RdHi,acc0. */
10237 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10239 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10242 /* Encoding functions relevant only to Thumb. */
10244 /* inst.operands[i] is a shifted-register operand; encode
10245 it into inst.instruction in the format used by Thumb32. */
10248 encode_thumb32_shifted_operand (int i
)
10250 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10251 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10253 constraint (inst
.operands
[i
].immisreg
,
10254 _("shift by register not allowed in thumb mode"));
10255 inst
.instruction
|= inst
.operands
[i
].reg
;
10256 if (shift
== SHIFT_RRX
)
10257 inst
.instruction
|= SHIFT_ROR
<< 4;
10260 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10261 _("expression too complex"));
10263 constraint (value
> 32
10264 || (value
== 32 && (shift
== SHIFT_LSL
10265 || shift
== SHIFT_ROR
)),
10266 _("shift expression is too large"));
10270 else if (value
== 32)
10273 inst
.instruction
|= shift
<< 4;
10274 inst
.instruction
|= (value
& 0x1c) << 10;
10275 inst
.instruction
|= (value
& 0x03) << 6;
10280 /* inst.operands[i] was set up by parse_address. Encode it into a
10281 Thumb32 format load or store instruction. Reject forms that cannot
10282 be used with such instructions. If is_t is true, reject forms that
10283 cannot be used with a T instruction; if is_d is true, reject forms
10284 that cannot be used with a D instruction. If it is a store insn,
10285 reject PC in Rn. */
10288 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10290 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10292 constraint (!inst
.operands
[i
].isreg
,
10293 _("Instruction does not support =N addresses"));
10295 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10296 if (inst
.operands
[i
].immisreg
)
10298 constraint (is_pc
, BAD_PC_ADDRESSING
);
10299 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10300 constraint (inst
.operands
[i
].negative
,
10301 _("Thumb does not support negative register indexing"));
10302 constraint (inst
.operands
[i
].postind
,
10303 _("Thumb does not support register post-indexing"));
10304 constraint (inst
.operands
[i
].writeback
,
10305 _("Thumb does not support register indexing with writeback"));
10306 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10307 _("Thumb supports only LSL in shifted register indexing"));
10309 inst
.instruction
|= inst
.operands
[i
].imm
;
10310 if (inst
.operands
[i
].shifted
)
10312 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10313 _("expression too complex"));
10314 constraint (inst
.reloc
.exp
.X_add_number
< 0
10315 || inst
.reloc
.exp
.X_add_number
> 3,
10316 _("shift out of range"));
10317 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10319 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10321 else if (inst
.operands
[i
].preind
)
10323 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10324 constraint (is_t
&& inst
.operands
[i
].writeback
,
10325 _("cannot use writeback with this instruction"));
10326 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10327 BAD_PC_ADDRESSING
);
10331 inst
.instruction
|= 0x01000000;
10332 if (inst
.operands
[i
].writeback
)
10333 inst
.instruction
|= 0x00200000;
10337 inst
.instruction
|= 0x00000c00;
10338 if (inst
.operands
[i
].writeback
)
10339 inst
.instruction
|= 0x00000100;
10341 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10343 else if (inst
.operands
[i
].postind
)
10345 gas_assert (inst
.operands
[i
].writeback
);
10346 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10347 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10350 inst
.instruction
|= 0x00200000;
10352 inst
.instruction
|= 0x00000900;
10353 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10355 else /* unindexed - only for coprocessor */
10356 inst
.error
= _("instruction does not accept unindexed addressing");
10359 /* Table of Thumb instructions which exist in both 16- and 32-bit
10360 encodings (the latter only in post-V6T2 cores). The index is the
10361 value used in the insns table below. When there is more than one
10362 possible 16-bit encoding for the instruction, this table always
10364 Also contains several pseudo-instructions used during relaxation. */
10365 #define T16_32_TAB \
10366 X(_adc, 4140, eb400000), \
10367 X(_adcs, 4140, eb500000), \
10368 X(_add, 1c00, eb000000), \
10369 X(_adds, 1c00, eb100000), \
10370 X(_addi, 0000, f1000000), \
10371 X(_addis, 0000, f1100000), \
10372 X(_add_pc,000f, f20f0000), \
10373 X(_add_sp,000d, f10d0000), \
10374 X(_adr, 000f, f20f0000), \
10375 X(_and, 4000, ea000000), \
10376 X(_ands, 4000, ea100000), \
10377 X(_asr, 1000, fa40f000), \
10378 X(_asrs, 1000, fa50f000), \
10379 X(_b, e000, f000b000), \
10380 X(_bcond, d000, f0008000), \
10381 X(_bic, 4380, ea200000), \
10382 X(_bics, 4380, ea300000), \
10383 X(_cmn, 42c0, eb100f00), \
10384 X(_cmp, 2800, ebb00f00), \
10385 X(_cpsie, b660, f3af8400), \
10386 X(_cpsid, b670, f3af8600), \
10387 X(_cpy, 4600, ea4f0000), \
10388 X(_dec_sp,80dd, f1ad0d00), \
10389 X(_eor, 4040, ea800000), \
10390 X(_eors, 4040, ea900000), \
10391 X(_inc_sp,00dd, f10d0d00), \
10392 X(_ldmia, c800, e8900000), \
10393 X(_ldr, 6800, f8500000), \
10394 X(_ldrb, 7800, f8100000), \
10395 X(_ldrh, 8800, f8300000), \
10396 X(_ldrsb, 5600, f9100000), \
10397 X(_ldrsh, 5e00, f9300000), \
10398 X(_ldr_pc,4800, f85f0000), \
10399 X(_ldr_pc2,4800, f85f0000), \
10400 X(_ldr_sp,9800, f85d0000), \
10401 X(_lsl, 0000, fa00f000), \
10402 X(_lsls, 0000, fa10f000), \
10403 X(_lsr, 0800, fa20f000), \
10404 X(_lsrs, 0800, fa30f000), \
10405 X(_mov, 2000, ea4f0000), \
10406 X(_movs, 2000, ea5f0000), \
10407 X(_mul, 4340, fb00f000), \
10408 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10409 X(_mvn, 43c0, ea6f0000), \
10410 X(_mvns, 43c0, ea7f0000), \
10411 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10412 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10413 X(_orr, 4300, ea400000), \
10414 X(_orrs, 4300, ea500000), \
10415 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10416 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10417 X(_rev, ba00, fa90f080), \
10418 X(_rev16, ba40, fa90f090), \
10419 X(_revsh, bac0, fa90f0b0), \
10420 X(_ror, 41c0, fa60f000), \
10421 X(_rors, 41c0, fa70f000), \
10422 X(_sbc, 4180, eb600000), \
10423 X(_sbcs, 4180, eb700000), \
10424 X(_stmia, c000, e8800000), \
10425 X(_str, 6000, f8400000), \
10426 X(_strb, 7000, f8000000), \
10427 X(_strh, 8000, f8200000), \
10428 X(_str_sp,9000, f84d0000), \
10429 X(_sub, 1e00, eba00000), \
10430 X(_subs, 1e00, ebb00000), \
10431 X(_subi, 8000, f1a00000), \
10432 X(_subis, 8000, f1b00000), \
10433 X(_sxtb, b240, fa4ff080), \
10434 X(_sxth, b200, fa0ff080), \
10435 X(_tst, 4200, ea100f00), \
10436 X(_uxtb, b2c0, fa5ff080), \
10437 X(_uxth, b280, fa1ff080), \
10438 X(_nop, bf00, f3af8000), \
10439 X(_yield, bf10, f3af8001), \
10440 X(_wfe, bf20, f3af8002), \
10441 X(_wfi, bf30, f3af8003), \
10442 X(_sev, bf40, f3af8004), \
10443 X(_sevl, bf50, f3af8005), \
10444 X(_udf, de00, f7f0a000)
10446 /* To catch errors in encoding functions, the codes are all offset by
10447 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10448 as 16-bit instructions. */
10449 #define X(a,b,c) T_MNEM##a
10450 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10453 #define X(a,b,c) 0x##b
10454 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10455 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10458 #define X(a,b,c) 0x##c
10459 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10460 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10461 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10465 /* Thumb instruction encoders, in alphabetical order. */
10467 /* ADDW or SUBW. */
10470 do_t_add_sub_w (void)
10474 Rd
= inst
.operands
[0].reg
;
10475 Rn
= inst
.operands
[1].reg
;
10477 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10478 is the SP-{plus,minus}-immediate form of the instruction. */
10480 constraint (Rd
== REG_PC
, BAD_PC
);
10482 reject_bad_reg (Rd
);
10484 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10485 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10488 /* Parse an add or subtract instruction. We get here with inst.instruction
10489 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10492 do_t_add_sub (void)
10496 Rd
= inst
.operands
[0].reg
;
10497 Rs
= (inst
.operands
[1].present
10498 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10499 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10502 set_it_insn_type_last ();
10504 if (unified_syntax
)
10507 bfd_boolean narrow
;
10510 flags
= (inst
.instruction
== T_MNEM_adds
10511 || inst
.instruction
== T_MNEM_subs
);
10513 narrow
= !in_it_block ();
10515 narrow
= in_it_block ();
10516 if (!inst
.operands
[2].isreg
)
10520 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10522 add
= (inst
.instruction
== T_MNEM_add
10523 || inst
.instruction
== T_MNEM_adds
);
10525 if (inst
.size_req
!= 4)
10527 /* Attempt to use a narrow opcode, with relaxation if
10529 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10530 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10531 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10532 opcode
= T_MNEM_add_sp
;
10533 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10534 opcode
= T_MNEM_add_pc
;
10535 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10538 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10540 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10544 inst
.instruction
= THUMB_OP16(opcode
);
10545 inst
.instruction
|= (Rd
<< 4) | Rs
;
10546 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10547 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10549 if (inst
.size_req
== 2)
10550 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10552 inst
.relax
= opcode
;
10556 constraint (inst
.size_req
== 2, BAD_HIREG
);
10558 if (inst
.size_req
== 4
10559 || (inst
.size_req
!= 2 && !opcode
))
10561 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10562 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10563 THUMB1_RELOC_ONLY
);
10566 constraint (add
, BAD_PC
);
10567 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10568 _("only SUBS PC, LR, #const allowed"));
10569 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10570 _("expression too complex"));
10571 constraint (inst
.reloc
.exp
.X_add_number
< 0
10572 || inst
.reloc
.exp
.X_add_number
> 0xff,
10573 _("immediate value out of range"));
10574 inst
.instruction
= T2_SUBS_PC_LR
10575 | inst
.reloc
.exp
.X_add_number
;
10576 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10579 else if (Rs
== REG_PC
)
10581 /* Always use addw/subw. */
10582 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10583 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10587 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10588 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10591 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10593 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10595 inst
.instruction
|= Rd
<< 8;
10596 inst
.instruction
|= Rs
<< 16;
10601 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10602 unsigned int shift
= inst
.operands
[2].shift_kind
;
10604 Rn
= inst
.operands
[2].reg
;
10605 /* See if we can do this with a 16-bit instruction. */
10606 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10608 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10613 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10614 || inst
.instruction
== T_MNEM_add
)
10616 : T_OPCODE_SUB_R3
);
10617 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10621 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10623 /* Thumb-1 cores (except v6-M) require at least one high
10624 register in a narrow non flag setting add. */
10625 if (Rd
> 7 || Rn
> 7
10626 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10627 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10634 inst
.instruction
= T_OPCODE_ADD_HI
;
10635 inst
.instruction
|= (Rd
& 8) << 4;
10636 inst
.instruction
|= (Rd
& 7);
10637 inst
.instruction
|= Rn
<< 3;
10643 constraint (Rd
== REG_PC
, BAD_PC
);
10644 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10645 constraint (Rs
== REG_PC
, BAD_PC
);
10646 reject_bad_reg (Rn
);
10648 /* If we get here, it can't be done in 16 bits. */
10649 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10650 _("shift must be constant"));
10651 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10652 inst
.instruction
|= Rd
<< 8;
10653 inst
.instruction
|= Rs
<< 16;
10654 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10655 _("shift value over 3 not allowed in thumb mode"));
10656 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10657 _("only LSL shift allowed in thumb mode"));
10658 encode_thumb32_shifted_operand (2);
10663 constraint (inst
.instruction
== T_MNEM_adds
10664 || inst
.instruction
== T_MNEM_subs
,
10667 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10669 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10670 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10673 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10674 ? 0x0000 : 0x8000);
10675 inst
.instruction
|= (Rd
<< 4) | Rs
;
10676 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10680 Rn
= inst
.operands
[2].reg
;
10681 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10683 /* We now have Rd, Rs, and Rn set to registers. */
10684 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10686 /* Can't do this for SUB. */
10687 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10688 inst
.instruction
= T_OPCODE_ADD_HI
;
10689 inst
.instruction
|= (Rd
& 8) << 4;
10690 inst
.instruction
|= (Rd
& 7);
10692 inst
.instruction
|= Rn
<< 3;
10694 inst
.instruction
|= Rs
<< 3;
10696 constraint (1, _("dest must overlap one source register"));
10700 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10701 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10702 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10712 Rd
= inst
.operands
[0].reg
;
10713 reject_bad_reg (Rd
);
10715 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10717 /* Defer to section relaxation. */
10718 inst
.relax
= inst
.instruction
;
10719 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10720 inst
.instruction
|= Rd
<< 4;
10722 else if (unified_syntax
&& inst
.size_req
!= 2)
10724 /* Generate a 32-bit opcode. */
10725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10726 inst
.instruction
|= Rd
<< 8;
10727 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10728 inst
.reloc
.pc_rel
= 1;
10732 /* Generate a 16-bit opcode. */
10733 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10734 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10735 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10736 inst
.reloc
.pc_rel
= 1;
10738 inst
.instruction
|= Rd
<< 4;
10742 /* Arithmetic instructions for which there is just one 16-bit
10743 instruction encoding, and it allows only two low registers.
10744 For maximal compatibility with ARM syntax, we allow three register
10745 operands even when Thumb-32 instructions are not available, as long
10746 as the first two are identical. For instance, both "sbc r0,r1" and
10747 "sbc r0,r0,r1" are allowed. */
10753 Rd
= inst
.operands
[0].reg
;
10754 Rs
= (inst
.operands
[1].present
10755 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10756 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10757 Rn
= inst
.operands
[2].reg
;
10759 reject_bad_reg (Rd
);
10760 reject_bad_reg (Rs
);
10761 if (inst
.operands
[2].isreg
)
10762 reject_bad_reg (Rn
);
10764 if (unified_syntax
)
10766 if (!inst
.operands
[2].isreg
)
10768 /* For an immediate, we always generate a 32-bit opcode;
10769 section relaxation will shrink it later if possible. */
10770 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10771 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10772 inst
.instruction
|= Rd
<< 8;
10773 inst
.instruction
|= Rs
<< 16;
10774 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10778 bfd_boolean narrow
;
10780 /* See if we can do this with a 16-bit instruction. */
10781 if (THUMB_SETS_FLAGS (inst
.instruction
))
10782 narrow
= !in_it_block ();
10784 narrow
= in_it_block ();
10786 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10788 if (inst
.operands
[2].shifted
)
10790 if (inst
.size_req
== 4)
10796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10797 inst
.instruction
|= Rd
;
10798 inst
.instruction
|= Rn
<< 3;
10802 /* If we get here, it can't be done in 16 bits. */
10803 constraint (inst
.operands
[2].shifted
10804 && inst
.operands
[2].immisreg
,
10805 _("shift must be constant"));
10806 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10807 inst
.instruction
|= Rd
<< 8;
10808 inst
.instruction
|= Rs
<< 16;
10809 encode_thumb32_shifted_operand (2);
10814 /* On its face this is a lie - the instruction does set the
10815 flags. However, the only supported mnemonic in this mode
10816 says it doesn't. */
10817 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10819 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10820 _("unshifted register required"));
10821 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10822 constraint (Rd
!= Rs
,
10823 _("dest and source1 must be the same register"));
10825 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10826 inst
.instruction
|= Rd
;
10827 inst
.instruction
|= Rn
<< 3;
10831 /* Similarly, but for instructions where the arithmetic operation is
10832 commutative, so we can allow either of them to be different from
10833 the destination operand in a 16-bit instruction. For instance, all
10834 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10841 Rd
= inst
.operands
[0].reg
;
10842 Rs
= (inst
.operands
[1].present
10843 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10844 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10845 Rn
= inst
.operands
[2].reg
;
10847 reject_bad_reg (Rd
);
10848 reject_bad_reg (Rs
);
10849 if (inst
.operands
[2].isreg
)
10850 reject_bad_reg (Rn
);
10852 if (unified_syntax
)
10854 if (!inst
.operands
[2].isreg
)
10856 /* For an immediate, we always generate a 32-bit opcode;
10857 section relaxation will shrink it later if possible. */
10858 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10859 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10860 inst
.instruction
|= Rd
<< 8;
10861 inst
.instruction
|= Rs
<< 16;
10862 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10866 bfd_boolean narrow
;
10868 /* See if we can do this with a 16-bit instruction. */
10869 if (THUMB_SETS_FLAGS (inst
.instruction
))
10870 narrow
= !in_it_block ();
10872 narrow
= in_it_block ();
10874 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10876 if (inst
.operands
[2].shifted
)
10878 if (inst
.size_req
== 4)
10885 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10886 inst
.instruction
|= Rd
;
10887 inst
.instruction
|= Rn
<< 3;
10892 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10893 inst
.instruction
|= Rd
;
10894 inst
.instruction
|= Rs
<< 3;
10899 /* If we get here, it can't be done in 16 bits. */
10900 constraint (inst
.operands
[2].shifted
10901 && inst
.operands
[2].immisreg
,
10902 _("shift must be constant"));
10903 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10904 inst
.instruction
|= Rd
<< 8;
10905 inst
.instruction
|= Rs
<< 16;
10906 encode_thumb32_shifted_operand (2);
10911 /* On its face this is a lie - the instruction does set the
10912 flags. However, the only supported mnemonic in this mode
10913 says it doesn't. */
10914 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10916 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10917 _("unshifted register required"));
10918 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10920 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10921 inst
.instruction
|= Rd
;
10924 inst
.instruction
|= Rn
<< 3;
10926 inst
.instruction
|= Rs
<< 3;
10928 constraint (1, _("dest must overlap one source register"));
10936 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10937 constraint (msb
> 32, _("bit-field extends past end of register"));
10938 /* The instruction encoding stores the LSB and MSB,
10939 not the LSB and width. */
10940 Rd
= inst
.operands
[0].reg
;
10941 reject_bad_reg (Rd
);
10942 inst
.instruction
|= Rd
<< 8;
10943 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10944 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10945 inst
.instruction
|= msb
- 1;
10954 Rd
= inst
.operands
[0].reg
;
10955 reject_bad_reg (Rd
);
10957 /* #0 in second position is alternative syntax for bfc, which is
10958 the same instruction but with REG_PC in the Rm field. */
10959 if (!inst
.operands
[1].isreg
)
10963 Rn
= inst
.operands
[1].reg
;
10964 reject_bad_reg (Rn
);
10967 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10968 constraint (msb
> 32, _("bit-field extends past end of register"));
10969 /* The instruction encoding stores the LSB and MSB,
10970 not the LSB and width. */
10971 inst
.instruction
|= Rd
<< 8;
10972 inst
.instruction
|= Rn
<< 16;
10973 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10974 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10975 inst
.instruction
|= msb
- 1;
10983 Rd
= inst
.operands
[0].reg
;
10984 Rn
= inst
.operands
[1].reg
;
10986 reject_bad_reg (Rd
);
10987 reject_bad_reg (Rn
);
10989 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10990 _("bit-field extends past end of register"));
10991 inst
.instruction
|= Rd
<< 8;
10992 inst
.instruction
|= Rn
<< 16;
10993 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10994 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10995 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10998 /* ARM V5 Thumb BLX (argument parse)
10999 BLX <target_addr> which is BLX(1)
11000 BLX <Rm> which is BLX(2)
11001 Unfortunately, there are two different opcodes for this mnemonic.
11002 So, the insns[].value is not used, and the code here zaps values
11003 into inst.instruction.
11005 ??? How to take advantage of the additional two bits of displacement
11006 available in Thumb32 mode? Need new relocation? */
11011 set_it_insn_type_last ();
11013 if (inst
.operands
[0].isreg
)
11015 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11016 /* We have a register, so this is BLX(2). */
11017 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11021 /* No register. This must be BLX(1). */
11022 inst
.instruction
= 0xf000e800;
11023 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11032 bfd_reloc_code_real_type reloc
;
11035 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11037 if (in_it_block ())
11039 /* Conditional branches inside IT blocks are encoded as unconditional
11041 cond
= COND_ALWAYS
;
11046 if (cond
!= COND_ALWAYS
)
11047 opcode
= T_MNEM_bcond
;
11049 opcode
= inst
.instruction
;
11052 && (inst
.size_req
== 4
11053 || (inst
.size_req
!= 2
11054 && (inst
.operands
[0].hasreloc
11055 || inst
.reloc
.exp
.X_op
== O_constant
))))
11057 inst
.instruction
= THUMB_OP32(opcode
);
11058 if (cond
== COND_ALWAYS
)
11059 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11063 _("selected architecture does not support "
11064 "wide conditional branch instruction"));
11066 gas_assert (cond
!= 0xF);
11067 inst
.instruction
|= cond
<< 22;
11068 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11073 inst
.instruction
= THUMB_OP16(opcode
);
11074 if (cond
== COND_ALWAYS
)
11075 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11078 inst
.instruction
|= cond
<< 8;
11079 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11081 /* Allow section relaxation. */
11082 if (unified_syntax
&& inst
.size_req
!= 2)
11083 inst
.relax
= opcode
;
11085 inst
.reloc
.type
= reloc
;
11086 inst
.reloc
.pc_rel
= 1;
11089 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11090 between the two is the maximum immediate allowed - which is passed in
11093 do_t_bkpt_hlt1 (int range
)
11095 constraint (inst
.cond
!= COND_ALWAYS
,
11096 _("instruction is always unconditional"));
11097 if (inst
.operands
[0].present
)
11099 constraint (inst
.operands
[0].imm
> range
,
11100 _("immediate value out of range"));
11101 inst
.instruction
|= inst
.operands
[0].imm
;
11104 set_it_insn_type (NEUTRAL_IT_INSN
);
11110 do_t_bkpt_hlt1 (63);
11116 do_t_bkpt_hlt1 (255);
11120 do_t_branch23 (void)
11122 set_it_insn_type_last ();
11123 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11125 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11126 this file. We used to simply ignore the PLT reloc type here --
11127 the branch encoding is now needed to deal with TLSCALL relocs.
11128 So if we see a PLT reloc now, put it back to how it used to be to
11129 keep the preexisting behaviour. */
11130 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11131 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11133 #if defined(OBJ_COFF)
11134 /* If the destination of the branch is a defined symbol which does not have
11135 the THUMB_FUNC attribute, then we must be calling a function which has
11136 the (interfacearm) attribute. We look for the Thumb entry point to that
11137 function and change the branch to refer to that function instead. */
11138 if ( inst
.reloc
.exp
.X_op
== O_symbol
11139 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11140 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11141 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11142 inst
.reloc
.exp
.X_add_symbol
=
11143 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11150 set_it_insn_type_last ();
11151 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11152 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11153 should cause the alignment to be checked once it is known. This is
11154 because BX PC only works if the instruction is word aligned. */
11162 set_it_insn_type_last ();
11163 Rm
= inst
.operands
[0].reg
;
11164 reject_bad_reg (Rm
);
11165 inst
.instruction
|= Rm
<< 16;
11174 Rd
= inst
.operands
[0].reg
;
11175 Rm
= inst
.operands
[1].reg
;
11177 reject_bad_reg (Rd
);
11178 reject_bad_reg (Rm
);
11180 inst
.instruction
|= Rd
<< 8;
11181 inst
.instruction
|= Rm
<< 16;
11182 inst
.instruction
|= Rm
;
11188 set_it_insn_type (OUTSIDE_IT_INSN
);
11189 inst
.instruction
|= inst
.operands
[0].imm
;
11195 set_it_insn_type (OUTSIDE_IT_INSN
);
11197 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11198 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11200 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11201 inst
.instruction
= 0xf3af8000;
11202 inst
.instruction
|= imod
<< 9;
11203 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11204 if (inst
.operands
[1].present
)
11205 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11209 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11210 && (inst
.operands
[0].imm
& 4),
11211 _("selected processor does not support 'A' form "
11212 "of this instruction"));
11213 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11214 _("Thumb does not support the 2-argument "
11215 "form of this instruction"));
11216 inst
.instruction
|= inst
.operands
[0].imm
;
11220 /* THUMB CPY instruction (argument parse). */
11225 if (inst
.size_req
== 4)
11227 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11228 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11229 inst
.instruction
|= inst
.operands
[1].reg
;
11233 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11234 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11235 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11242 set_it_insn_type (OUTSIDE_IT_INSN
);
11243 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11244 inst
.instruction
|= inst
.operands
[0].reg
;
11245 inst
.reloc
.pc_rel
= 1;
11246 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11252 inst
.instruction
|= inst
.operands
[0].imm
;
11258 unsigned Rd
, Rn
, Rm
;
11260 Rd
= inst
.operands
[0].reg
;
11261 Rn
= (inst
.operands
[1].present
11262 ? inst
.operands
[1].reg
: Rd
);
11263 Rm
= inst
.operands
[2].reg
;
11265 reject_bad_reg (Rd
);
11266 reject_bad_reg (Rn
);
11267 reject_bad_reg (Rm
);
11269 inst
.instruction
|= Rd
<< 8;
11270 inst
.instruction
|= Rn
<< 16;
11271 inst
.instruction
|= Rm
;
11277 if (unified_syntax
&& inst
.size_req
== 4)
11278 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11280 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11286 unsigned int cond
= inst
.operands
[0].imm
;
11288 set_it_insn_type (IT_INSN
);
11289 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11291 now_it
.warn_deprecated
= FALSE
;
11293 /* If the condition is a negative condition, invert the mask. */
11294 if ((cond
& 0x1) == 0x0)
11296 unsigned int mask
= inst
.instruction
& 0x000f;
11298 if ((mask
& 0x7) == 0)
11300 /* No conversion needed. */
11301 now_it
.block_length
= 1;
11303 else if ((mask
& 0x3) == 0)
11306 now_it
.block_length
= 2;
11308 else if ((mask
& 0x1) == 0)
11311 now_it
.block_length
= 3;
11316 now_it
.block_length
= 4;
11319 inst
.instruction
&= 0xfff0;
11320 inst
.instruction
|= mask
;
11323 inst
.instruction
|= cond
<< 4;
11326 /* Helper function used for both push/pop and ldm/stm. */
11328 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11332 load
= (inst
.instruction
& (1 << 20)) != 0;
11334 if (mask
& (1 << 13))
11335 inst
.error
= _("SP not allowed in register list");
11337 if ((mask
& (1 << base
)) != 0
11339 inst
.error
= _("having the base register in the register list when "
11340 "using write back is UNPREDICTABLE");
11344 if (mask
& (1 << 15))
11346 if (mask
& (1 << 14))
11347 inst
.error
= _("LR and PC should not both be in register list");
11349 set_it_insn_type_last ();
11354 if (mask
& (1 << 15))
11355 inst
.error
= _("PC not allowed in register list");
11358 if ((mask
& (mask
- 1)) == 0)
11360 /* Single register transfers implemented as str/ldr. */
11363 if (inst
.instruction
& (1 << 23))
11364 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11366 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11370 if (inst
.instruction
& (1 << 23))
11371 inst
.instruction
= 0x00800000; /* ia -> [base] */
11373 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11376 inst
.instruction
|= 0xf8400000;
11378 inst
.instruction
|= 0x00100000;
11380 mask
= ffs (mask
) - 1;
11383 else if (writeback
)
11384 inst
.instruction
|= WRITE_BACK
;
11386 inst
.instruction
|= mask
;
11387 inst
.instruction
|= base
<< 16;
11393 /* This really doesn't seem worth it. */
11394 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11395 _("expression too complex"));
11396 constraint (inst
.operands
[1].writeback
,
11397 _("Thumb load/store multiple does not support {reglist}^"));
11399 if (unified_syntax
)
11401 bfd_boolean narrow
;
11405 /* See if we can use a 16-bit instruction. */
11406 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11407 && inst
.size_req
!= 4
11408 && !(inst
.operands
[1].imm
& ~0xff))
11410 mask
= 1 << inst
.operands
[0].reg
;
11412 if (inst
.operands
[0].reg
<= 7)
11414 if (inst
.instruction
== T_MNEM_stmia
11415 ? inst
.operands
[0].writeback
11416 : (inst
.operands
[0].writeback
11417 == !(inst
.operands
[1].imm
& mask
)))
11419 if (inst
.instruction
== T_MNEM_stmia
11420 && (inst
.operands
[1].imm
& mask
)
11421 && (inst
.operands
[1].imm
& (mask
- 1)))
11422 as_warn (_("value stored for r%d is UNKNOWN"),
11423 inst
.operands
[0].reg
);
11425 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11426 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11427 inst
.instruction
|= inst
.operands
[1].imm
;
11430 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11432 /* This means 1 register in reg list one of 3 situations:
11433 1. Instruction is stmia, but without writeback.
11434 2. lmdia without writeback, but with Rn not in
11436 3. ldmia with writeback, but with Rn in reglist.
11437 Case 3 is UNPREDICTABLE behaviour, so we handle
11438 case 1 and 2 which can be converted into a 16-bit
11439 str or ldr. The SP cases are handled below. */
11440 unsigned long opcode
;
11441 /* First, record an error for Case 3. */
11442 if (inst
.operands
[1].imm
& mask
11443 && inst
.operands
[0].writeback
)
11445 _("having the base register in the register list when "
11446 "using write back is UNPREDICTABLE");
11448 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11450 inst
.instruction
= THUMB_OP16 (opcode
);
11451 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11452 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11456 else if (inst
.operands
[0] .reg
== REG_SP
)
11458 if (inst
.operands
[0].writeback
)
11461 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11462 ? T_MNEM_push
: T_MNEM_pop
);
11463 inst
.instruction
|= inst
.operands
[1].imm
;
11466 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11469 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11470 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11471 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11479 if (inst
.instruction
< 0xffff)
11480 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11482 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11483 inst
.operands
[0].writeback
);
11488 constraint (inst
.operands
[0].reg
> 7
11489 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11490 constraint (inst
.instruction
!= T_MNEM_ldmia
11491 && inst
.instruction
!= T_MNEM_stmia
,
11492 _("Thumb-2 instruction only valid in unified syntax"));
11493 if (inst
.instruction
== T_MNEM_stmia
)
11495 if (!inst
.operands
[0].writeback
)
11496 as_warn (_("this instruction will write back the base register"));
11497 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11498 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11499 as_warn (_("value stored for r%d is UNKNOWN"),
11500 inst
.operands
[0].reg
);
11504 if (!inst
.operands
[0].writeback
11505 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11506 as_warn (_("this instruction will write back the base register"));
11507 else if (inst
.operands
[0].writeback
11508 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11509 as_warn (_("this instruction will not write back the base register"));
11512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11513 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11514 inst
.instruction
|= inst
.operands
[1].imm
;
11521 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11522 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11523 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11524 || inst
.operands
[1].negative
,
11527 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11530 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11531 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11537 if (!inst
.operands
[1].present
)
11539 constraint (inst
.operands
[0].reg
== REG_LR
,
11540 _("r14 not allowed as first register "
11541 "when second register is omitted"));
11542 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11544 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11548 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11549 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11555 unsigned long opcode
;
11558 if (inst
.operands
[0].isreg
11559 && !inst
.operands
[0].preind
11560 && inst
.operands
[0].reg
== REG_PC
)
11561 set_it_insn_type_last ();
11563 opcode
= inst
.instruction
;
11564 if (unified_syntax
)
11566 if (!inst
.operands
[1].isreg
)
11568 if (opcode
<= 0xffff)
11569 inst
.instruction
= THUMB_OP32 (opcode
);
11570 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11573 if (inst
.operands
[1].isreg
11574 && !inst
.operands
[1].writeback
11575 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11576 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11577 && opcode
<= 0xffff
11578 && inst
.size_req
!= 4)
11580 /* Insn may have a 16-bit form. */
11581 Rn
= inst
.operands
[1].reg
;
11582 if (inst
.operands
[1].immisreg
)
11584 inst
.instruction
= THUMB_OP16 (opcode
);
11586 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11588 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11589 reject_bad_reg (inst
.operands
[1].imm
);
11591 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11592 && opcode
!= T_MNEM_ldrsb
)
11593 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11594 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11601 if (inst
.reloc
.pc_rel
)
11602 opcode
= T_MNEM_ldr_pc2
;
11604 opcode
= T_MNEM_ldr_pc
;
11608 if (opcode
== T_MNEM_ldr
)
11609 opcode
= T_MNEM_ldr_sp
;
11611 opcode
= T_MNEM_str_sp
;
11613 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11617 inst
.instruction
= inst
.operands
[0].reg
;
11618 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11620 inst
.instruction
|= THUMB_OP16 (opcode
);
11621 if (inst
.size_req
== 2)
11622 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11624 inst
.relax
= opcode
;
11628 /* Definitely a 32-bit variant. */
11630 /* Warning for Erratum 752419. */
11631 if (opcode
== T_MNEM_ldr
11632 && inst
.operands
[0].reg
== REG_SP
11633 && inst
.operands
[1].writeback
== 1
11634 && !inst
.operands
[1].immisreg
)
11636 if (no_cpu_selected ()
11637 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11638 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11639 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11640 as_warn (_("This instruction may be unpredictable "
11641 "if executed on M-profile cores "
11642 "with interrupts enabled."));
11645 /* Do some validations regarding addressing modes. */
11646 if (inst
.operands
[1].immisreg
)
11647 reject_bad_reg (inst
.operands
[1].imm
);
11649 constraint (inst
.operands
[1].writeback
== 1
11650 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11653 inst
.instruction
= THUMB_OP32 (opcode
);
11654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11655 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11656 check_ldr_r15_aligned ();
11660 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11662 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11664 /* Only [Rn,Rm] is acceptable. */
11665 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11666 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11667 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11668 || inst
.operands
[1].negative
,
11669 _("Thumb does not support this addressing mode"));
11670 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11675 if (!inst
.operands
[1].isreg
)
11676 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11679 constraint (!inst
.operands
[1].preind
11680 || inst
.operands
[1].shifted
11681 || inst
.operands
[1].writeback
,
11682 _("Thumb does not support this addressing mode"));
11683 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11685 constraint (inst
.instruction
& 0x0600,
11686 _("byte or halfword not valid for base register"));
11687 constraint (inst
.operands
[1].reg
== REG_PC
11688 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11689 _("r15 based store not allowed"));
11690 constraint (inst
.operands
[1].immisreg
,
11691 _("invalid base register for register offset"));
11693 if (inst
.operands
[1].reg
== REG_PC
)
11694 inst
.instruction
= T_OPCODE_LDR_PC
;
11695 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11696 inst
.instruction
= T_OPCODE_LDR_SP
;
11698 inst
.instruction
= T_OPCODE_STR_SP
;
11700 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11701 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11705 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11706 if (!inst
.operands
[1].immisreg
)
11708 /* Immediate offset. */
11709 inst
.instruction
|= inst
.operands
[0].reg
;
11710 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11711 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11715 /* Register offset. */
11716 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11717 constraint (inst
.operands
[1].negative
,
11718 _("Thumb does not support this addressing mode"));
11721 switch (inst
.instruction
)
11723 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11724 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11725 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11726 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11727 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11728 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11729 case 0x5600 /* ldrsb */:
11730 case 0x5e00 /* ldrsh */: break;
11734 inst
.instruction
|= inst
.operands
[0].reg
;
11735 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11736 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11742 if (!inst
.operands
[1].present
)
11744 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11745 constraint (inst
.operands
[0].reg
== REG_LR
,
11746 _("r14 not allowed here"));
11747 constraint (inst
.operands
[0].reg
== REG_R12
,
11748 _("r12 not allowed here"));
11751 if (inst
.operands
[2].writeback
11752 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11753 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11754 as_warn (_("base register written back, and overlaps "
11755 "one of transfer registers"));
11757 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11758 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11759 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11765 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11766 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11772 unsigned Rd
, Rn
, Rm
, Ra
;
11774 Rd
= inst
.operands
[0].reg
;
11775 Rn
= inst
.operands
[1].reg
;
11776 Rm
= inst
.operands
[2].reg
;
11777 Ra
= inst
.operands
[3].reg
;
11779 reject_bad_reg (Rd
);
11780 reject_bad_reg (Rn
);
11781 reject_bad_reg (Rm
);
11782 reject_bad_reg (Ra
);
11784 inst
.instruction
|= Rd
<< 8;
11785 inst
.instruction
|= Rn
<< 16;
11786 inst
.instruction
|= Rm
;
11787 inst
.instruction
|= Ra
<< 12;
11793 unsigned RdLo
, RdHi
, Rn
, Rm
;
11795 RdLo
= inst
.operands
[0].reg
;
11796 RdHi
= inst
.operands
[1].reg
;
11797 Rn
= inst
.operands
[2].reg
;
11798 Rm
= inst
.operands
[3].reg
;
11800 reject_bad_reg (RdLo
);
11801 reject_bad_reg (RdHi
);
11802 reject_bad_reg (Rn
);
11803 reject_bad_reg (Rm
);
11805 inst
.instruction
|= RdLo
<< 12;
11806 inst
.instruction
|= RdHi
<< 8;
11807 inst
.instruction
|= Rn
<< 16;
11808 inst
.instruction
|= Rm
;
11812 do_t_mov_cmp (void)
11816 Rn
= inst
.operands
[0].reg
;
11817 Rm
= inst
.operands
[1].reg
;
11820 set_it_insn_type_last ();
11822 if (unified_syntax
)
11824 int r0off
= (inst
.instruction
== T_MNEM_mov
11825 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11826 unsigned long opcode
;
11827 bfd_boolean narrow
;
11828 bfd_boolean low_regs
;
11830 low_regs
= (Rn
<= 7 && Rm
<= 7);
11831 opcode
= inst
.instruction
;
11832 if (in_it_block ())
11833 narrow
= opcode
!= T_MNEM_movs
;
11835 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11836 if (inst
.size_req
== 4
11837 || inst
.operands
[1].shifted
)
11840 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11841 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11842 && !inst
.operands
[1].shifted
11846 inst
.instruction
= T2_SUBS_PC_LR
;
11850 if (opcode
== T_MNEM_cmp
)
11852 constraint (Rn
== REG_PC
, BAD_PC
);
11855 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11857 warn_deprecated_sp (Rm
);
11858 /* R15 was documented as a valid choice for Rm in ARMv6,
11859 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11860 tools reject R15, so we do too. */
11861 constraint (Rm
== REG_PC
, BAD_PC
);
11864 reject_bad_reg (Rm
);
11866 else if (opcode
== T_MNEM_mov
11867 || opcode
== T_MNEM_movs
)
11869 if (inst
.operands
[1].isreg
)
11871 if (opcode
== T_MNEM_movs
)
11873 reject_bad_reg (Rn
);
11874 reject_bad_reg (Rm
);
11878 /* This is mov.n. */
11879 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11880 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11882 as_tsktsk (_("Use of r%u as a source register is "
11883 "deprecated when r%u is the destination "
11884 "register."), Rm
, Rn
);
11889 /* This is mov.w. */
11890 constraint (Rn
== REG_PC
, BAD_PC
);
11891 constraint (Rm
== REG_PC
, BAD_PC
);
11892 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11896 reject_bad_reg (Rn
);
11899 if (!inst
.operands
[1].isreg
)
11901 /* Immediate operand. */
11902 if (!in_it_block () && opcode
== T_MNEM_mov
)
11904 if (low_regs
&& narrow
)
11906 inst
.instruction
= THUMB_OP16 (opcode
);
11907 inst
.instruction
|= Rn
<< 8;
11908 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11909 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11911 if (inst
.size_req
== 2)
11912 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11914 inst
.relax
= opcode
;
11919 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11920 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11921 THUMB1_RELOC_ONLY
);
11923 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11924 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11925 inst
.instruction
|= Rn
<< r0off
;
11926 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11929 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11930 && (inst
.instruction
== T_MNEM_mov
11931 || inst
.instruction
== T_MNEM_movs
))
11933 /* Register shifts are encoded as separate shift instructions. */
11934 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11936 if (in_it_block ())
11941 if (inst
.size_req
== 4)
11944 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11950 switch (inst
.operands
[1].shift_kind
)
11953 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11956 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11959 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11962 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11968 inst
.instruction
= opcode
;
11971 inst
.instruction
|= Rn
;
11972 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11977 inst
.instruction
|= CONDS_BIT
;
11979 inst
.instruction
|= Rn
<< 8;
11980 inst
.instruction
|= Rm
<< 16;
11981 inst
.instruction
|= inst
.operands
[1].imm
;
11986 /* Some mov with immediate shift have narrow variants.
11987 Register shifts are handled above. */
11988 if (low_regs
&& inst
.operands
[1].shifted
11989 && (inst
.instruction
== T_MNEM_mov
11990 || inst
.instruction
== T_MNEM_movs
))
11992 if (in_it_block ())
11993 narrow
= (inst
.instruction
== T_MNEM_mov
);
11995 narrow
= (inst
.instruction
== T_MNEM_movs
);
12000 switch (inst
.operands
[1].shift_kind
)
12002 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12003 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12004 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12005 default: narrow
= FALSE
; break;
12011 inst
.instruction
|= Rn
;
12012 inst
.instruction
|= Rm
<< 3;
12013 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12017 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12018 inst
.instruction
|= Rn
<< r0off
;
12019 encode_thumb32_shifted_operand (1);
12023 switch (inst
.instruction
)
12026 /* In v4t or v5t a move of two lowregs produces unpredictable
12027 results. Don't allow this. */
12030 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12031 "MOV Rd, Rs with two low registers is not "
12032 "permitted on this architecture");
12033 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12037 inst
.instruction
= T_OPCODE_MOV_HR
;
12038 inst
.instruction
|= (Rn
& 0x8) << 4;
12039 inst
.instruction
|= (Rn
& 0x7);
12040 inst
.instruction
|= Rm
<< 3;
12044 /* We know we have low registers at this point.
12045 Generate LSLS Rd, Rs, #0. */
12046 inst
.instruction
= T_OPCODE_LSL_I
;
12047 inst
.instruction
|= Rn
;
12048 inst
.instruction
|= Rm
<< 3;
12054 inst
.instruction
= T_OPCODE_CMP_LR
;
12055 inst
.instruction
|= Rn
;
12056 inst
.instruction
|= Rm
<< 3;
12060 inst
.instruction
= T_OPCODE_CMP_HR
;
12061 inst
.instruction
|= (Rn
& 0x8) << 4;
12062 inst
.instruction
|= (Rn
& 0x7);
12063 inst
.instruction
|= Rm
<< 3;
12070 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12072 /* PR 10443: Do not silently ignore shifted operands. */
12073 constraint (inst
.operands
[1].shifted
,
12074 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12076 if (inst
.operands
[1].isreg
)
12078 if (Rn
< 8 && Rm
< 8)
12080 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12081 since a MOV instruction produces unpredictable results. */
12082 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12083 inst
.instruction
= T_OPCODE_ADD_I3
;
12085 inst
.instruction
= T_OPCODE_CMP_LR
;
12087 inst
.instruction
|= Rn
;
12088 inst
.instruction
|= Rm
<< 3;
12092 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12093 inst
.instruction
= T_OPCODE_MOV_HR
;
12095 inst
.instruction
= T_OPCODE_CMP_HR
;
12101 constraint (Rn
> 7,
12102 _("only lo regs allowed with immediate"));
12103 inst
.instruction
|= Rn
<< 8;
12104 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12115 top
= (inst
.instruction
& 0x00800000) != 0;
12116 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12118 constraint (top
, _(":lower16: not allowed this instruction"));
12119 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12121 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12123 constraint (!top
, _(":upper16: not allowed this instruction"));
12124 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12127 Rd
= inst
.operands
[0].reg
;
12128 reject_bad_reg (Rd
);
12130 inst
.instruction
|= Rd
<< 8;
12131 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12133 imm
= inst
.reloc
.exp
.X_add_number
;
12134 inst
.instruction
|= (imm
& 0xf000) << 4;
12135 inst
.instruction
|= (imm
& 0x0800) << 15;
12136 inst
.instruction
|= (imm
& 0x0700) << 4;
12137 inst
.instruction
|= (imm
& 0x00ff);
12142 do_t_mvn_tst (void)
12146 Rn
= inst
.operands
[0].reg
;
12147 Rm
= inst
.operands
[1].reg
;
12149 if (inst
.instruction
== T_MNEM_cmp
12150 || inst
.instruction
== T_MNEM_cmn
)
12151 constraint (Rn
== REG_PC
, BAD_PC
);
12153 reject_bad_reg (Rn
);
12154 reject_bad_reg (Rm
);
12156 if (unified_syntax
)
12158 int r0off
= (inst
.instruction
== T_MNEM_mvn
12159 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12160 bfd_boolean narrow
;
12162 if (inst
.size_req
== 4
12163 || inst
.instruction
> 0xffff
12164 || inst
.operands
[1].shifted
12165 || Rn
> 7 || Rm
> 7)
12167 else if (inst
.instruction
== T_MNEM_cmn
12168 || inst
.instruction
== T_MNEM_tst
)
12170 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12171 narrow
= !in_it_block ();
12173 narrow
= in_it_block ();
12175 if (!inst
.operands
[1].isreg
)
12177 /* For an immediate, we always generate a 32-bit opcode;
12178 section relaxation will shrink it later if possible. */
12179 if (inst
.instruction
< 0xffff)
12180 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12181 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12182 inst
.instruction
|= Rn
<< r0off
;
12183 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12187 /* See if we can do this with a 16-bit instruction. */
12190 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12191 inst
.instruction
|= Rn
;
12192 inst
.instruction
|= Rm
<< 3;
12196 constraint (inst
.operands
[1].shifted
12197 && inst
.operands
[1].immisreg
,
12198 _("shift must be constant"));
12199 if (inst
.instruction
< 0xffff)
12200 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12201 inst
.instruction
|= Rn
<< r0off
;
12202 encode_thumb32_shifted_operand (1);
12208 constraint (inst
.instruction
> 0xffff
12209 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12210 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12211 _("unshifted register required"));
12212 constraint (Rn
> 7 || Rm
> 7,
12215 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12216 inst
.instruction
|= Rn
;
12217 inst
.instruction
|= Rm
<< 3;
12226 if (do_vfp_nsyn_mrs () == SUCCESS
)
12229 Rd
= inst
.operands
[0].reg
;
12230 reject_bad_reg (Rd
);
12231 inst
.instruction
|= Rd
<< 8;
12233 if (inst
.operands
[1].isreg
)
12235 unsigned br
= inst
.operands
[1].reg
;
12236 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12237 as_bad (_("bad register for mrs"));
12239 inst
.instruction
|= br
& (0xf << 16);
12240 inst
.instruction
|= (br
& 0x300) >> 4;
12241 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12245 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12247 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12249 /* PR gas/12698: The constraint is only applied for m_profile.
12250 If the user has specified -march=all, we want to ignore it as
12251 we are building for any CPU type, including non-m variants. */
12252 bfd_boolean m_profile
=
12253 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12254 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12255 "not support requested special purpose register"));
12258 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12260 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12261 _("'APSR', 'CPSR' or 'SPSR' expected"));
12263 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12264 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12265 inst
.instruction
|= 0xf0000;
12275 if (do_vfp_nsyn_msr () == SUCCESS
)
12278 constraint (!inst
.operands
[1].isreg
,
12279 _("Thumb encoding does not support an immediate here"));
12281 if (inst
.operands
[0].isreg
)
12282 flags
= (int)(inst
.operands
[0].reg
);
12284 flags
= inst
.operands
[0].imm
;
12286 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12288 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12290 /* PR gas/12698: The constraint is only applied for m_profile.
12291 If the user has specified -march=all, we want to ignore it as
12292 we are building for any CPU type, including non-m variants. */
12293 bfd_boolean m_profile
=
12294 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12295 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12296 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12297 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12298 && bits
!= PSR_f
)) && m_profile
,
12299 _("selected processor does not support requested special "
12300 "purpose register"));
12303 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12304 "requested special purpose register"));
12306 Rn
= inst
.operands
[1].reg
;
12307 reject_bad_reg (Rn
);
12309 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12310 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12311 inst
.instruction
|= (flags
& 0x300) >> 4;
12312 inst
.instruction
|= (flags
& 0xff);
12313 inst
.instruction
|= Rn
<< 16;
12319 bfd_boolean narrow
;
12320 unsigned Rd
, Rn
, Rm
;
12322 if (!inst
.operands
[2].present
)
12323 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12325 Rd
= inst
.operands
[0].reg
;
12326 Rn
= inst
.operands
[1].reg
;
12327 Rm
= inst
.operands
[2].reg
;
12329 if (unified_syntax
)
12331 if (inst
.size_req
== 4
12337 else if (inst
.instruction
== T_MNEM_muls
)
12338 narrow
= !in_it_block ();
12340 narrow
= in_it_block ();
12344 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12345 constraint (Rn
> 7 || Rm
> 7,
12352 /* 16-bit MULS/Conditional MUL. */
12353 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12354 inst
.instruction
|= Rd
;
12357 inst
.instruction
|= Rm
<< 3;
12359 inst
.instruction
|= Rn
<< 3;
12361 constraint (1, _("dest must overlap one source register"));
12365 constraint (inst
.instruction
!= T_MNEM_mul
,
12366 _("Thumb-2 MUL must not set flags"));
12368 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12369 inst
.instruction
|= Rd
<< 8;
12370 inst
.instruction
|= Rn
<< 16;
12371 inst
.instruction
|= Rm
<< 0;
12373 reject_bad_reg (Rd
);
12374 reject_bad_reg (Rn
);
12375 reject_bad_reg (Rm
);
12382 unsigned RdLo
, RdHi
, Rn
, Rm
;
12384 RdLo
= inst
.operands
[0].reg
;
12385 RdHi
= inst
.operands
[1].reg
;
12386 Rn
= inst
.operands
[2].reg
;
12387 Rm
= inst
.operands
[3].reg
;
12389 reject_bad_reg (RdLo
);
12390 reject_bad_reg (RdHi
);
12391 reject_bad_reg (Rn
);
12392 reject_bad_reg (Rm
);
12394 inst
.instruction
|= RdLo
<< 12;
12395 inst
.instruction
|= RdHi
<< 8;
12396 inst
.instruction
|= Rn
<< 16;
12397 inst
.instruction
|= Rm
;
12400 as_tsktsk (_("rdhi and rdlo must be different"));
12406 set_it_insn_type (NEUTRAL_IT_INSN
);
12408 if (unified_syntax
)
12410 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12412 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12413 inst
.instruction
|= inst
.operands
[0].imm
;
12417 /* PR9722: Check for Thumb2 availability before
12418 generating a thumb2 nop instruction. */
12419 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12421 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12422 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12425 inst
.instruction
= 0x46c0;
12430 constraint (inst
.operands
[0].present
,
12431 _("Thumb does not support NOP with hints"));
12432 inst
.instruction
= 0x46c0;
12439 if (unified_syntax
)
12441 bfd_boolean narrow
;
12443 if (THUMB_SETS_FLAGS (inst
.instruction
))
12444 narrow
= !in_it_block ();
12446 narrow
= in_it_block ();
12447 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12449 if (inst
.size_req
== 4)
12454 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12455 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12456 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12460 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12461 inst
.instruction
|= inst
.operands
[0].reg
;
12462 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12467 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12469 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12472 inst
.instruction
|= inst
.operands
[0].reg
;
12473 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12482 Rd
= inst
.operands
[0].reg
;
12483 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12485 reject_bad_reg (Rd
);
12486 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12487 reject_bad_reg (Rn
);
12489 inst
.instruction
|= Rd
<< 8;
12490 inst
.instruction
|= Rn
<< 16;
12492 if (!inst
.operands
[2].isreg
)
12494 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12495 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12501 Rm
= inst
.operands
[2].reg
;
12502 reject_bad_reg (Rm
);
12504 constraint (inst
.operands
[2].shifted
12505 && inst
.operands
[2].immisreg
,
12506 _("shift must be constant"));
12507 encode_thumb32_shifted_operand (2);
12514 unsigned Rd
, Rn
, Rm
;
12516 Rd
= inst
.operands
[0].reg
;
12517 Rn
= inst
.operands
[1].reg
;
12518 Rm
= inst
.operands
[2].reg
;
12520 reject_bad_reg (Rd
);
12521 reject_bad_reg (Rn
);
12522 reject_bad_reg (Rm
);
12524 inst
.instruction
|= Rd
<< 8;
12525 inst
.instruction
|= Rn
<< 16;
12526 inst
.instruction
|= Rm
;
12527 if (inst
.operands
[3].present
)
12529 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12530 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12531 _("expression too complex"));
12532 inst
.instruction
|= (val
& 0x1c) << 10;
12533 inst
.instruction
|= (val
& 0x03) << 6;
12540 if (!inst
.operands
[3].present
)
12544 inst
.instruction
&= ~0x00000020;
12546 /* PR 10168. Swap the Rm and Rn registers. */
12547 Rtmp
= inst
.operands
[1].reg
;
12548 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12549 inst
.operands
[2].reg
= Rtmp
;
12557 if (inst
.operands
[0].immisreg
)
12558 reject_bad_reg (inst
.operands
[0].imm
);
12560 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12564 do_t_push_pop (void)
12568 constraint (inst
.operands
[0].writeback
,
12569 _("push/pop do not support {reglist}^"));
12570 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12571 _("expression too complex"));
12573 mask
= inst
.operands
[0].imm
;
12574 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12575 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12576 else if (inst
.size_req
!= 4
12577 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12578 ? REG_LR
: REG_PC
)))
12580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12581 inst
.instruction
|= THUMB_PP_PC_LR
;
12582 inst
.instruction
|= mask
& 0xff;
12584 else if (unified_syntax
)
12586 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12587 encode_thumb2_ldmstm (13, mask
, TRUE
);
12591 inst
.error
= _("invalid register list to push/pop instruction");
12601 Rd
= inst
.operands
[0].reg
;
12602 Rm
= inst
.operands
[1].reg
;
12604 reject_bad_reg (Rd
);
12605 reject_bad_reg (Rm
);
12607 inst
.instruction
|= Rd
<< 8;
12608 inst
.instruction
|= Rm
<< 16;
12609 inst
.instruction
|= Rm
;
12617 Rd
= inst
.operands
[0].reg
;
12618 Rm
= inst
.operands
[1].reg
;
12620 reject_bad_reg (Rd
);
12621 reject_bad_reg (Rm
);
12623 if (Rd
<= 7 && Rm
<= 7
12624 && inst
.size_req
!= 4)
12626 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12627 inst
.instruction
|= Rd
;
12628 inst
.instruction
|= Rm
<< 3;
12630 else if (unified_syntax
)
12632 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12633 inst
.instruction
|= Rd
<< 8;
12634 inst
.instruction
|= Rm
<< 16;
12635 inst
.instruction
|= Rm
;
12638 inst
.error
= BAD_HIREG
;
12646 Rd
= inst
.operands
[0].reg
;
12647 Rm
= inst
.operands
[1].reg
;
12649 reject_bad_reg (Rd
);
12650 reject_bad_reg (Rm
);
12652 inst
.instruction
|= Rd
<< 8;
12653 inst
.instruction
|= Rm
;
12661 Rd
= inst
.operands
[0].reg
;
12662 Rs
= (inst
.operands
[1].present
12663 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12664 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12666 reject_bad_reg (Rd
);
12667 reject_bad_reg (Rs
);
12668 if (inst
.operands
[2].isreg
)
12669 reject_bad_reg (inst
.operands
[2].reg
);
12671 inst
.instruction
|= Rd
<< 8;
12672 inst
.instruction
|= Rs
<< 16;
12673 if (!inst
.operands
[2].isreg
)
12675 bfd_boolean narrow
;
12677 if ((inst
.instruction
& 0x00100000) != 0)
12678 narrow
= !in_it_block ();
12680 narrow
= in_it_block ();
12682 if (Rd
> 7 || Rs
> 7)
12685 if (inst
.size_req
== 4 || !unified_syntax
)
12688 if (inst
.reloc
.exp
.X_op
!= O_constant
12689 || inst
.reloc
.exp
.X_add_number
!= 0)
12692 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12693 relaxation, but it doesn't seem worth the hassle. */
12696 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12697 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12698 inst
.instruction
|= Rs
<< 3;
12699 inst
.instruction
|= Rd
;
12703 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12704 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12708 encode_thumb32_shifted_operand (2);
12714 if (warn_on_deprecated
12715 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12716 as_tsktsk (_("setend use is deprecated for ARMv8"));
12718 set_it_insn_type (OUTSIDE_IT_INSN
);
12719 if (inst
.operands
[0].imm
)
12720 inst
.instruction
|= 0x8;
12726 if (!inst
.operands
[1].present
)
12727 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12729 if (unified_syntax
)
12731 bfd_boolean narrow
;
12734 switch (inst
.instruction
)
12737 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12739 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12741 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12743 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12747 if (THUMB_SETS_FLAGS (inst
.instruction
))
12748 narrow
= !in_it_block ();
12750 narrow
= in_it_block ();
12751 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12753 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12755 if (inst
.operands
[2].isreg
12756 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12757 || inst
.operands
[2].reg
> 7))
12759 if (inst
.size_req
== 4)
12762 reject_bad_reg (inst
.operands
[0].reg
);
12763 reject_bad_reg (inst
.operands
[1].reg
);
12767 if (inst
.operands
[2].isreg
)
12769 reject_bad_reg (inst
.operands
[2].reg
);
12770 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12771 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12772 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12773 inst
.instruction
|= inst
.operands
[2].reg
;
12775 /* PR 12854: Error on extraneous shifts. */
12776 constraint (inst
.operands
[2].shifted
,
12777 _("extraneous shift as part of operand to shift insn"));
12781 inst
.operands
[1].shifted
= 1;
12782 inst
.operands
[1].shift_kind
= shift_kind
;
12783 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12784 ? T_MNEM_movs
: T_MNEM_mov
);
12785 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12786 encode_thumb32_shifted_operand (1);
12787 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12788 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12793 if (inst
.operands
[2].isreg
)
12795 switch (shift_kind
)
12797 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12798 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12799 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12800 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12804 inst
.instruction
|= inst
.operands
[0].reg
;
12805 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12807 /* PR 12854: Error on extraneous shifts. */
12808 constraint (inst
.operands
[2].shifted
,
12809 _("extraneous shift as part of operand to shift insn"));
12813 switch (shift_kind
)
12815 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12816 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12817 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12820 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12821 inst
.instruction
|= inst
.operands
[0].reg
;
12822 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12828 constraint (inst
.operands
[0].reg
> 7
12829 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12830 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12832 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12834 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12835 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12836 _("source1 and dest must be same register"));
12838 switch (inst
.instruction
)
12840 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12841 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12842 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12843 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12847 inst
.instruction
|= inst
.operands
[0].reg
;
12848 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12850 /* PR 12854: Error on extraneous shifts. */
12851 constraint (inst
.operands
[2].shifted
,
12852 _("extraneous shift as part of operand to shift insn"));
12856 switch (inst
.instruction
)
12858 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12859 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12860 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12861 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12864 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12865 inst
.instruction
|= inst
.operands
[0].reg
;
12866 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12874 unsigned Rd
, Rn
, Rm
;
12876 Rd
= inst
.operands
[0].reg
;
12877 Rn
= inst
.operands
[1].reg
;
12878 Rm
= inst
.operands
[2].reg
;
12880 reject_bad_reg (Rd
);
12881 reject_bad_reg (Rn
);
12882 reject_bad_reg (Rm
);
12884 inst
.instruction
|= Rd
<< 8;
12885 inst
.instruction
|= Rn
<< 16;
12886 inst
.instruction
|= Rm
;
12892 unsigned Rd
, Rn
, Rm
;
12894 Rd
= inst
.operands
[0].reg
;
12895 Rm
= inst
.operands
[1].reg
;
12896 Rn
= inst
.operands
[2].reg
;
12898 reject_bad_reg (Rd
);
12899 reject_bad_reg (Rn
);
12900 reject_bad_reg (Rm
);
12902 inst
.instruction
|= Rd
<< 8;
12903 inst
.instruction
|= Rn
<< 16;
12904 inst
.instruction
|= Rm
;
12910 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12911 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12912 _("SMC is not permitted on this architecture"));
12913 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12914 _("expression too complex"));
12915 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12916 inst
.instruction
|= (value
& 0xf000) >> 12;
12917 inst
.instruction
|= (value
& 0x0ff0);
12918 inst
.instruction
|= (value
& 0x000f) << 16;
12919 /* PR gas/15623: SMC instructions must be last in an IT block. */
12920 set_it_insn_type_last ();
12926 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12928 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12929 inst
.instruction
|= (value
& 0x0fff);
12930 inst
.instruction
|= (value
& 0xf000) << 4;
12934 do_t_ssat_usat (int bias
)
12938 Rd
= inst
.operands
[0].reg
;
12939 Rn
= inst
.operands
[2].reg
;
12941 reject_bad_reg (Rd
);
12942 reject_bad_reg (Rn
);
12944 inst
.instruction
|= Rd
<< 8;
12945 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12946 inst
.instruction
|= Rn
<< 16;
12948 if (inst
.operands
[3].present
)
12950 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12952 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12954 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12955 _("expression too complex"));
12957 if (shift_amount
!= 0)
12959 constraint (shift_amount
> 31,
12960 _("shift expression is too large"));
12962 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12963 inst
.instruction
|= 0x00200000; /* sh bit. */
12965 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12966 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12974 do_t_ssat_usat (1);
12982 Rd
= inst
.operands
[0].reg
;
12983 Rn
= inst
.operands
[2].reg
;
12985 reject_bad_reg (Rd
);
12986 reject_bad_reg (Rn
);
12988 inst
.instruction
|= Rd
<< 8;
12989 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12990 inst
.instruction
|= Rn
<< 16;
12996 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12997 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12998 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12999 || inst
.operands
[2].negative
,
13002 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13004 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13005 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13006 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13007 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13013 if (!inst
.operands
[2].present
)
13014 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13016 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13017 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13018 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13021 inst
.instruction
|= inst
.operands
[0].reg
;
13022 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13023 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13024 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13030 unsigned Rd
, Rn
, Rm
;
13032 Rd
= inst
.operands
[0].reg
;
13033 Rn
= inst
.operands
[1].reg
;
13034 Rm
= inst
.operands
[2].reg
;
13036 reject_bad_reg (Rd
);
13037 reject_bad_reg (Rn
);
13038 reject_bad_reg (Rm
);
13040 inst
.instruction
|= Rd
<< 8;
13041 inst
.instruction
|= Rn
<< 16;
13042 inst
.instruction
|= Rm
;
13043 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13051 Rd
= inst
.operands
[0].reg
;
13052 Rm
= inst
.operands
[1].reg
;
13054 reject_bad_reg (Rd
);
13055 reject_bad_reg (Rm
);
13057 if (inst
.instruction
<= 0xffff
13058 && inst
.size_req
!= 4
13059 && Rd
<= 7 && Rm
<= 7
13060 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13062 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13063 inst
.instruction
|= Rd
;
13064 inst
.instruction
|= Rm
<< 3;
13066 else if (unified_syntax
)
13068 if (inst
.instruction
<= 0xffff)
13069 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13070 inst
.instruction
|= Rd
<< 8;
13071 inst
.instruction
|= Rm
;
13072 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13076 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13077 _("Thumb encoding does not support rotation"));
13078 constraint (1, BAD_HIREG
);
13085 /* We have to do the following check manually as ARM_EXT_OS only applies
13087 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13089 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13090 /* This only applies to the v6m however, not later architectures. */
13091 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13092 as_bad (_("SVC is not permitted on this architecture"));
13093 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13096 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13105 half
= (inst
.instruction
& 0x10) != 0;
13106 set_it_insn_type_last ();
13107 constraint (inst
.operands
[0].immisreg
,
13108 _("instruction requires register index"));
13110 Rn
= inst
.operands
[0].reg
;
13111 Rm
= inst
.operands
[0].imm
;
13113 constraint (Rn
== REG_SP
, BAD_SP
);
13114 reject_bad_reg (Rm
);
13116 constraint (!half
&& inst
.operands
[0].shifted
,
13117 _("instruction does not allow shifted index"));
13118 inst
.instruction
|= (Rn
<< 16) | Rm
;
13124 if (!inst
.operands
[0].present
)
13125 inst
.operands
[0].imm
= 0;
13127 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13129 constraint (inst
.size_req
== 2,
13130 _("immediate value out of range"));
13131 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13132 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13133 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13137 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13138 inst
.instruction
|= inst
.operands
[0].imm
;
13141 set_it_insn_type (NEUTRAL_IT_INSN
);
13148 do_t_ssat_usat (0);
13156 Rd
= inst
.operands
[0].reg
;
13157 Rn
= inst
.operands
[2].reg
;
13159 reject_bad_reg (Rd
);
13160 reject_bad_reg (Rn
);
13162 inst
.instruction
|= Rd
<< 8;
13163 inst
.instruction
|= inst
.operands
[1].imm
;
13164 inst
.instruction
|= Rn
<< 16;
13167 /* Neon instruction encoder helpers. */
13169 /* Encodings for the different types for various Neon opcodes. */
13171 /* An "invalid" code for the following tables. */
13174 struct neon_tab_entry
13177 unsigned float_or_poly
;
13178 unsigned scalar_or_imm
;
13181 /* Map overloaded Neon opcodes to their respective encodings. */
13182 #define NEON_ENC_TAB \
13183 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13184 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13185 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13186 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13187 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13188 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13189 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13190 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13191 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13192 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13193 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13194 /* Register variants of the following two instructions are encoded as
13195 vcge / vcgt with the operands reversed. */ \
13196 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13197 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13198 X(vfma, N_INV, 0x0000c10, N_INV), \
13199 X(vfms, N_INV, 0x0200c10, N_INV), \
13200 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13201 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13202 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13203 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13204 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13205 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13206 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13207 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13208 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13209 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13210 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13211 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13212 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13213 X(vshl, 0x0000400, N_INV, 0x0800510), \
13214 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13215 X(vand, 0x0000110, N_INV, 0x0800030), \
13216 X(vbic, 0x0100110, N_INV, 0x0800030), \
13217 X(veor, 0x1000110, N_INV, N_INV), \
13218 X(vorn, 0x0300110, N_INV, 0x0800010), \
13219 X(vorr, 0x0200110, N_INV, 0x0800010), \
13220 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13221 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13222 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13223 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13224 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13225 X(vst1, 0x0000000, 0x0800000, N_INV), \
13226 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13227 X(vst2, 0x0000100, 0x0800100, N_INV), \
13228 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13229 X(vst3, 0x0000200, 0x0800200, N_INV), \
13230 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13231 X(vst4, 0x0000300, 0x0800300, N_INV), \
13232 X(vmovn, 0x1b20200, N_INV, N_INV), \
13233 X(vtrn, 0x1b20080, N_INV, N_INV), \
13234 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13235 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13236 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13237 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13238 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13239 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13240 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13241 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13242 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13243 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13244 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13245 X(vseleq, 0xe000a00, N_INV, N_INV), \
13246 X(vselvs, 0xe100a00, N_INV, N_INV), \
13247 X(vselge, 0xe200a00, N_INV, N_INV), \
13248 X(vselgt, 0xe300a00, N_INV, N_INV), \
13249 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13250 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13251 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13252 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13253 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13254 X(aes, 0x3b00300, N_INV, N_INV), \
13255 X(sha3op, 0x2000c00, N_INV, N_INV), \
13256 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13257 X(sha2op, 0x3ba0380, N_INV, N_INV)
13261 #define X(OPC,I,F,S) N_MNEM_##OPC
13266 static const struct neon_tab_entry neon_enc_tab
[] =
13268 #define X(OPC,I,F,S) { (I), (F), (S) }
13273 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13274 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13275 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13276 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13277 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13278 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13279 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13280 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13281 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13282 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13283 #define NEON_ENC_SINGLE_(X) \
13284 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13285 #define NEON_ENC_DOUBLE_(X) \
13286 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13287 #define NEON_ENC_FPV8_(X) \
13288 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13290 #define NEON_ENCODE(type, inst) \
13293 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13294 inst.is_neon = 1; \
13298 #define check_neon_suffixes \
13301 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13303 as_bad (_("invalid neon suffix for non neon instruction")); \
13309 /* Define shapes for instruction operands. The following mnemonic characters
13310 are used in this table:
13312 F - VFP S<n> register
13313 D - Neon D<n> register
13314 Q - Neon Q<n> register
13318 L - D<n> register list
13320 This table is used to generate various data:
13321 - enumerations of the form NS_DDR to be used as arguments to
13323 - a table classifying shapes into single, double, quad, mixed.
13324 - a table used to drive neon_select_shape. */
13326 #define NEON_SHAPE_DEF \
13327 X(3, (D, D, D), DOUBLE), \
13328 X(3, (Q, Q, Q), QUAD), \
13329 X(3, (D, D, I), DOUBLE), \
13330 X(3, (Q, Q, I), QUAD), \
13331 X(3, (D, D, S), DOUBLE), \
13332 X(3, (Q, Q, S), QUAD), \
13333 X(2, (D, D), DOUBLE), \
13334 X(2, (Q, Q), QUAD), \
13335 X(2, (D, S), DOUBLE), \
13336 X(2, (Q, S), QUAD), \
13337 X(2, (D, R), DOUBLE), \
13338 X(2, (Q, R), QUAD), \
13339 X(2, (D, I), DOUBLE), \
13340 X(2, (Q, I), QUAD), \
13341 X(3, (D, L, D), DOUBLE), \
13342 X(2, (D, Q), MIXED), \
13343 X(2, (Q, D), MIXED), \
13344 X(3, (D, Q, I), MIXED), \
13345 X(3, (Q, D, I), MIXED), \
13346 X(3, (Q, D, D), MIXED), \
13347 X(3, (D, Q, Q), MIXED), \
13348 X(3, (Q, Q, D), MIXED), \
13349 X(3, (Q, D, S), MIXED), \
13350 X(3, (D, Q, S), MIXED), \
13351 X(4, (D, D, D, I), DOUBLE), \
13352 X(4, (Q, Q, Q, I), QUAD), \
13353 X(4, (D, D, S, I), DOUBLE), \
13354 X(4, (Q, Q, S, I), QUAD), \
13355 X(2, (F, F), SINGLE), \
13356 X(3, (F, F, F), SINGLE), \
13357 X(2, (F, I), SINGLE), \
13358 X(2, (F, D), MIXED), \
13359 X(2, (D, F), MIXED), \
13360 X(3, (F, F, I), MIXED), \
13361 X(4, (R, R, F, F), SINGLE), \
13362 X(4, (F, F, R, R), SINGLE), \
13363 X(3, (D, R, R), DOUBLE), \
13364 X(3, (R, R, D), DOUBLE), \
13365 X(2, (S, R), SINGLE), \
13366 X(2, (R, S), SINGLE), \
13367 X(2, (F, R), SINGLE), \
13368 X(2, (R, F), SINGLE), \
13369 /* Half float shape supported so far. */\
13370 X (2, (H, D), MIXED), \
13371 X (2, (D, H), MIXED), \
13372 X (2, (H, F), MIXED), \
13373 X (2, (F, H), MIXED), \
13374 X (2, (H, H), HALF), \
13375 X (2, (H, R), HALF), \
13376 X (2, (R, H), HALF), \
13377 X (2, (H, I), HALF), \
13378 X (3, (H, H, H), HALF), \
13379 X (3, (H, F, I), MIXED), \
13380 X (3, (F, H, I), MIXED)
13382 #define S2(A,B) NS_##A##B
13383 #define S3(A,B,C) NS_##A##B##C
13384 #define S4(A,B,C,D) NS_##A##B##C##D
13386 #define X(N, L, C) S##N L
13399 enum neon_shape_class
13408 #define X(N, L, C) SC_##C
13410 static enum neon_shape_class neon_shape_class
[] =
13429 /* Register widths of above. */
13430 static unsigned neon_shape_el_size
[] =
13442 struct neon_shape_info
13445 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13448 #define S2(A,B) { SE_##A, SE_##B }
13449 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13450 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13452 #define X(N, L, C) { N, S##N L }
13454 static struct neon_shape_info neon_shape_tab
[] =
13464 /* Bit masks used in type checking given instructions.
13465 'N_EQK' means the type must be the same as (or based on in some way) the key
13466 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13467 set, various other bits can be set as well in order to modify the meaning of
13468 the type constraint. */
13470 enum neon_type_mask
13494 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13495 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13496 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13497 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13498 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13499 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13500 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13501 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13502 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13503 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13504 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13506 N_MAX_NONSPECIAL
= N_P64
13509 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13511 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13512 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13513 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13514 #define N_S_32 (N_S8 | N_S16 | N_S32)
13515 #define N_F_16_32 (N_F16 | N_F32)
13516 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13517 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13518 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13519 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13521 /* Pass this as the first type argument to neon_check_type to ignore types
13523 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13525 /* Select a "shape" for the current instruction (describing register types or
13526 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13527 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13528 function of operand parsing, so this function doesn't need to be called.
13529 Shapes should be listed in order of decreasing length. */
13531 static enum neon_shape
13532 neon_select_shape (enum neon_shape shape
, ...)
13535 enum neon_shape first_shape
= shape
;
13537 /* Fix missing optional operands. FIXME: we don't know at this point how
13538 many arguments we should have, so this makes the assumption that we have
13539 > 1. This is true of all current Neon opcodes, I think, but may not be
13540 true in the future. */
13541 if (!inst
.operands
[1].present
)
13542 inst
.operands
[1] = inst
.operands
[0];
13544 va_start (ap
, shape
);
13546 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13551 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13553 if (!inst
.operands
[j
].present
)
13559 switch (neon_shape_tab
[shape
].el
[j
])
13561 /* If a .f16, .16, .u16, .s16 type specifier is given over
13562 a VFP single precision register operand, it's essentially
13563 means only half of the register is used.
13565 If the type specifier is given after the mnemonics, the
13566 information is stored in inst.vectype. If the type specifier
13567 is given after register operand, the information is stored
13568 in inst.operands[].vectype.
13570 When there is only one type specifier, and all the register
13571 operands are the same type of hardware register, the type
13572 specifier applies to all register operands.
13574 If no type specifier is given, the shape is inferred from
13575 operand information.
13578 vadd.f16 s0, s1, s2: NS_HHH
13579 vabs.f16 s0, s1: NS_HH
13580 vmov.f16 s0, r1: NS_HR
13581 vmov.f16 r0, s1: NS_RH
13582 vcvt.f16 r0, s1: NS_RH
13583 vcvt.f16.s32 s2, s2, #29: NS_HFI
13584 vcvt.f16.s32 s2, s2: NS_HF
13587 if (!(inst
.operands
[j
].isreg
13588 && inst
.operands
[j
].isvec
13589 && inst
.operands
[j
].issingle
13590 && !inst
.operands
[j
].isquad
13591 && ((inst
.vectype
.elems
== 1
13592 && inst
.vectype
.el
[0].size
== 16)
13593 || (inst
.vectype
.elems
> 1
13594 && inst
.vectype
.el
[j
].size
== 16)
13595 || (inst
.vectype
.elems
== 0
13596 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13597 && inst
.operands
[j
].vectype
.size
== 16))))
13602 if (!(inst
.operands
[j
].isreg
13603 && inst
.operands
[j
].isvec
13604 && inst
.operands
[j
].issingle
13605 && !inst
.operands
[j
].isquad
13606 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13607 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13608 || (inst
.vectype
.elems
== 0
13609 && (inst
.operands
[j
].vectype
.size
== 32
13610 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13615 if (!(inst
.operands
[j
].isreg
13616 && inst
.operands
[j
].isvec
13617 && !inst
.operands
[j
].isquad
13618 && !inst
.operands
[j
].issingle
))
13623 if (!(inst
.operands
[j
].isreg
13624 && !inst
.operands
[j
].isvec
))
13629 if (!(inst
.operands
[j
].isreg
13630 && inst
.operands
[j
].isvec
13631 && inst
.operands
[j
].isquad
13632 && !inst
.operands
[j
].issingle
))
13637 if (!(!inst
.operands
[j
].isreg
13638 && !inst
.operands
[j
].isscalar
))
13643 if (!(!inst
.operands
[j
].isreg
13644 && inst
.operands
[j
].isscalar
))
13654 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13655 /* We've matched all the entries in the shape table, and we don't
13656 have any left over operands which have not been matched. */
13662 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13663 first_error (_("invalid instruction shape"));
13668 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13669 means the Q bit should be set). */
13672 neon_quad (enum neon_shape shape
)
13674 return neon_shape_class
[shape
] == SC_QUAD
;
13678 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13681 /* Allow modification to be made to types which are constrained to be
13682 based on the key element, based on bits set alongside N_EQK. */
13683 if ((typebits
& N_EQK
) != 0)
13685 if ((typebits
& N_HLF
) != 0)
13687 else if ((typebits
& N_DBL
) != 0)
13689 if ((typebits
& N_SGN
) != 0)
13690 *g_type
= NT_signed
;
13691 else if ((typebits
& N_UNS
) != 0)
13692 *g_type
= NT_unsigned
;
13693 else if ((typebits
& N_INT
) != 0)
13694 *g_type
= NT_integer
;
13695 else if ((typebits
& N_FLT
) != 0)
13696 *g_type
= NT_float
;
13697 else if ((typebits
& N_SIZ
) != 0)
13698 *g_type
= NT_untyped
;
13702 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13703 operand type, i.e. the single type specified in a Neon instruction when it
13704 is the only one given. */
13706 static struct neon_type_el
13707 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13709 struct neon_type_el dest
= *key
;
13711 gas_assert ((thisarg
& N_EQK
) != 0);
13713 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13718 /* Convert Neon type and size into compact bitmask representation. */
13720 static enum neon_type_mask
13721 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13728 case 8: return N_8
;
13729 case 16: return N_16
;
13730 case 32: return N_32
;
13731 case 64: return N_64
;
13739 case 8: return N_I8
;
13740 case 16: return N_I16
;
13741 case 32: return N_I32
;
13742 case 64: return N_I64
;
13750 case 16: return N_F16
;
13751 case 32: return N_F32
;
13752 case 64: return N_F64
;
13760 case 8: return N_P8
;
13761 case 16: return N_P16
;
13762 case 64: return N_P64
;
13770 case 8: return N_S8
;
13771 case 16: return N_S16
;
13772 case 32: return N_S32
;
13773 case 64: return N_S64
;
13781 case 8: return N_U8
;
13782 case 16: return N_U16
;
13783 case 32: return N_U32
;
13784 case 64: return N_U64
;
13795 /* Convert compact Neon bitmask type representation to a type and size. Only
13796 handles the case where a single bit is set in the mask. */
13799 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13800 enum neon_type_mask mask
)
13802 if ((mask
& N_EQK
) != 0)
13805 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13807 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13809 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13811 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13816 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13818 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13819 *type
= NT_unsigned
;
13820 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13821 *type
= NT_integer
;
13822 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13823 *type
= NT_untyped
;
13824 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13826 else if ((mask
& (N_F_ALL
)) != 0)
13834 /* Modify a bitmask of allowed types. This is only needed for type
13838 modify_types_allowed (unsigned allowed
, unsigned mods
)
13841 enum neon_el_type type
;
13847 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13849 if (el_type_of_type_chk (&type
, &size
,
13850 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13852 neon_modify_type_size (mods
, &type
, &size
);
13853 destmask
|= type_chk_of_el_type (type
, size
);
13860 /* Check type and return type classification.
13861 The manual states (paraphrase): If one datatype is given, it indicates the
13863 - the second operand, if there is one
13864 - the operand, if there is no second operand
13865 - the result, if there are no operands.
13866 This isn't quite good enough though, so we use a concept of a "key" datatype
13867 which is set on a per-instruction basis, which is the one which matters when
13868 only one data type is written.
13869 Note: this function has side-effects (e.g. filling in missing operands). All
13870 Neon instructions should call it before performing bit encoding. */
13872 static struct neon_type_el
13873 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13876 unsigned i
, pass
, key_el
= 0;
13877 unsigned types
[NEON_MAX_TYPE_ELS
];
13878 enum neon_el_type k_type
= NT_invtype
;
13879 unsigned k_size
= -1u;
13880 struct neon_type_el badtype
= {NT_invtype
, -1};
13881 unsigned key_allowed
= 0;
13883 /* Optional registers in Neon instructions are always (not) in operand 1.
13884 Fill in the missing operand here, if it was omitted. */
13885 if (els
> 1 && !inst
.operands
[1].present
)
13886 inst
.operands
[1] = inst
.operands
[0];
13888 /* Suck up all the varargs. */
13890 for (i
= 0; i
< els
; i
++)
13892 unsigned thisarg
= va_arg (ap
, unsigned);
13893 if (thisarg
== N_IGNORE_TYPE
)
13898 types
[i
] = thisarg
;
13899 if ((thisarg
& N_KEY
) != 0)
13904 if (inst
.vectype
.elems
> 0)
13905 for (i
= 0; i
< els
; i
++)
13906 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13908 first_error (_("types specified in both the mnemonic and operands"));
13912 /* Duplicate inst.vectype elements here as necessary.
13913 FIXME: No idea if this is exactly the same as the ARM assembler,
13914 particularly when an insn takes one register and one non-register
13916 if (inst
.vectype
.elems
== 1 && els
> 1)
13919 inst
.vectype
.elems
= els
;
13920 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13921 for (j
= 0; j
< els
; j
++)
13923 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13926 else if (inst
.vectype
.elems
== 0 && els
> 0)
13929 /* No types were given after the mnemonic, so look for types specified
13930 after each operand. We allow some flexibility here; as long as the
13931 "key" operand has a type, we can infer the others. */
13932 for (j
= 0; j
< els
; j
++)
13933 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13934 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13936 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13938 for (j
= 0; j
< els
; j
++)
13939 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13940 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13945 first_error (_("operand types can't be inferred"));
13949 else if (inst
.vectype
.elems
!= els
)
13951 first_error (_("type specifier has the wrong number of parts"));
13955 for (pass
= 0; pass
< 2; pass
++)
13957 for (i
= 0; i
< els
; i
++)
13959 unsigned thisarg
= types
[i
];
13960 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13961 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13962 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13963 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13965 /* Decay more-specific signed & unsigned types to sign-insensitive
13966 integer types if sign-specific variants are unavailable. */
13967 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13968 && (types_allowed
& N_SU_ALL
) == 0)
13969 g_type
= NT_integer
;
13971 /* If only untyped args are allowed, decay any more specific types to
13972 them. Some instructions only care about signs for some element
13973 sizes, so handle that properly. */
13974 if (((types_allowed
& N_UNT
) == 0)
13975 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13976 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13977 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13978 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13979 g_type
= NT_untyped
;
13983 if ((thisarg
& N_KEY
) != 0)
13987 key_allowed
= thisarg
& ~N_KEY
;
13989 /* Check architecture constraint on FP16 extension. */
13991 && k_type
== NT_float
13992 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13994 inst
.error
= _(BAD_FP16
);
14001 if ((thisarg
& N_VFP
) != 0)
14003 enum neon_shape_el regshape
;
14004 unsigned regwidth
, match
;
14006 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14009 first_error (_("invalid instruction shape"));
14012 regshape
= neon_shape_tab
[ns
].el
[i
];
14013 regwidth
= neon_shape_el_size
[regshape
];
14015 /* In VFP mode, operands must match register widths. If we
14016 have a key operand, use its width, else use the width of
14017 the current operand. */
14023 /* FP16 will use a single precision register. */
14024 if (regwidth
== 32 && match
== 16)
14026 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14030 inst
.error
= _(BAD_FP16
);
14035 if (regwidth
!= match
)
14037 first_error (_("operand size must match register width"));
14042 if ((thisarg
& N_EQK
) == 0)
14044 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14046 if ((given_type
& types_allowed
) == 0)
14048 first_error (_("bad type in Neon instruction"));
14054 enum neon_el_type mod_k_type
= k_type
;
14055 unsigned mod_k_size
= k_size
;
14056 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14057 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14059 first_error (_("inconsistent types in Neon instruction"));
14067 return inst
.vectype
.el
[key_el
];
14070 /* Neon-style VFP instruction forwarding. */
14072 /* Thumb VFP instructions have 0xE in the condition field. */
14075 do_vfp_cond_or_thumb (void)
14080 inst
.instruction
|= 0xe0000000;
14082 inst
.instruction
|= inst
.cond
<< 28;
14085 /* Look up and encode a simple mnemonic, for use as a helper function for the
14086 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14087 etc. It is assumed that operand parsing has already been done, and that the
14088 operands are in the form expected by the given opcode (this isn't necessarily
14089 the same as the form in which they were parsed, hence some massaging must
14090 take place before this function is called).
14091 Checks current arch version against that in the looked-up opcode. */
14094 do_vfp_nsyn_opcode (const char *opname
)
14096 const struct asm_opcode
*opcode
;
14098 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14103 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14104 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14111 inst
.instruction
= opcode
->tvalue
;
14112 opcode
->tencode ();
14116 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14117 opcode
->aencode ();
14122 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14124 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14126 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14129 do_vfp_nsyn_opcode ("fadds");
14131 do_vfp_nsyn_opcode ("fsubs");
14133 /* ARMv8.2 fp16 instruction. */
14135 do_scalar_fp16_v82_encode ();
14140 do_vfp_nsyn_opcode ("faddd");
14142 do_vfp_nsyn_opcode ("fsubd");
14146 /* Check operand types to see if this is a VFP instruction, and if so call
14150 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14152 enum neon_shape rs
;
14153 struct neon_type_el et
;
14158 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14159 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14163 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14164 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14165 N_F_ALL
| N_KEY
| N_VFP
);
14172 if (et
.type
!= NT_invtype
)
14183 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14185 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14187 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14190 do_vfp_nsyn_opcode ("fmacs");
14192 do_vfp_nsyn_opcode ("fnmacs");
14194 /* ARMv8.2 fp16 instruction. */
14196 do_scalar_fp16_v82_encode ();
14201 do_vfp_nsyn_opcode ("fmacd");
14203 do_vfp_nsyn_opcode ("fnmacd");
14208 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14210 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14212 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14215 do_vfp_nsyn_opcode ("ffmas");
14217 do_vfp_nsyn_opcode ("ffnmas");
14219 /* ARMv8.2 fp16 instruction. */
14221 do_scalar_fp16_v82_encode ();
14226 do_vfp_nsyn_opcode ("ffmad");
14228 do_vfp_nsyn_opcode ("ffnmad");
14233 do_vfp_nsyn_mul (enum neon_shape rs
)
14235 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14237 do_vfp_nsyn_opcode ("fmuls");
14239 /* ARMv8.2 fp16 instruction. */
14241 do_scalar_fp16_v82_encode ();
14244 do_vfp_nsyn_opcode ("fmuld");
14248 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14250 int is_neg
= (inst
.instruction
& 0x80) != 0;
14251 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14253 if (rs
== NS_FF
|| rs
== NS_HH
)
14256 do_vfp_nsyn_opcode ("fnegs");
14258 do_vfp_nsyn_opcode ("fabss");
14260 /* ARMv8.2 fp16 instruction. */
14262 do_scalar_fp16_v82_encode ();
14267 do_vfp_nsyn_opcode ("fnegd");
14269 do_vfp_nsyn_opcode ("fabsd");
14273 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14274 insns belong to Neon, and are handled elsewhere. */
14277 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14279 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14283 do_vfp_nsyn_opcode ("fldmdbs");
14285 do_vfp_nsyn_opcode ("fldmias");
14290 do_vfp_nsyn_opcode ("fstmdbs");
14292 do_vfp_nsyn_opcode ("fstmias");
14297 do_vfp_nsyn_sqrt (void)
14299 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14300 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14302 if (rs
== NS_FF
|| rs
== NS_HH
)
14304 do_vfp_nsyn_opcode ("fsqrts");
14306 /* ARMv8.2 fp16 instruction. */
14308 do_scalar_fp16_v82_encode ();
14311 do_vfp_nsyn_opcode ("fsqrtd");
14315 do_vfp_nsyn_div (void)
14317 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14318 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14319 N_F_ALL
| N_KEY
| N_VFP
);
14321 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14323 do_vfp_nsyn_opcode ("fdivs");
14325 /* ARMv8.2 fp16 instruction. */
14327 do_scalar_fp16_v82_encode ();
14330 do_vfp_nsyn_opcode ("fdivd");
14334 do_vfp_nsyn_nmul (void)
14336 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14337 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14338 N_F_ALL
| N_KEY
| N_VFP
);
14340 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14342 NEON_ENCODE (SINGLE
, inst
);
14343 do_vfp_sp_dyadic ();
14345 /* ARMv8.2 fp16 instruction. */
14347 do_scalar_fp16_v82_encode ();
14351 NEON_ENCODE (DOUBLE
, inst
);
14352 do_vfp_dp_rd_rn_rm ();
14354 do_vfp_cond_or_thumb ();
14359 do_vfp_nsyn_cmp (void)
14361 enum neon_shape rs
;
14362 if (inst
.operands
[1].isreg
)
14364 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14365 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14367 if (rs
== NS_FF
|| rs
== NS_HH
)
14369 NEON_ENCODE (SINGLE
, inst
);
14370 do_vfp_sp_monadic ();
14374 NEON_ENCODE (DOUBLE
, inst
);
14375 do_vfp_dp_rd_rm ();
14380 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14381 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14383 switch (inst
.instruction
& 0x0fffffff)
14386 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14389 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14395 if (rs
== NS_FI
|| rs
== NS_HI
)
14397 NEON_ENCODE (SINGLE
, inst
);
14398 do_vfp_sp_compare_z ();
14402 NEON_ENCODE (DOUBLE
, inst
);
14406 do_vfp_cond_or_thumb ();
14408 /* ARMv8.2 fp16 instruction. */
14409 if (rs
== NS_HI
|| rs
== NS_HH
)
14410 do_scalar_fp16_v82_encode ();
14414 nsyn_insert_sp (void)
14416 inst
.operands
[1] = inst
.operands
[0];
14417 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14418 inst
.operands
[0].reg
= REG_SP
;
14419 inst
.operands
[0].isreg
= 1;
14420 inst
.operands
[0].writeback
= 1;
14421 inst
.operands
[0].present
= 1;
14425 do_vfp_nsyn_push (void)
14429 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14430 _("register list must contain at least 1 and at most 16 "
14433 if (inst
.operands
[1].issingle
)
14434 do_vfp_nsyn_opcode ("fstmdbs");
14436 do_vfp_nsyn_opcode ("fstmdbd");
14440 do_vfp_nsyn_pop (void)
14444 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14445 _("register list must contain at least 1 and at most 16 "
14448 if (inst
.operands
[1].issingle
)
14449 do_vfp_nsyn_opcode ("fldmias");
14451 do_vfp_nsyn_opcode ("fldmiad");
14454 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14455 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14458 neon_dp_fixup (struct arm_it
* insn
)
14460 unsigned int i
= insn
->instruction
;
14465 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14476 insn
->instruction
= i
;
14479 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14483 neon_logbits (unsigned x
)
14485 return ffs (x
) - 4;
14488 #define LOW4(R) ((R) & 0xf)
14489 #define HI1(R) (((R) >> 4) & 1)
14491 /* Encode insns with bit pattern:
14493 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14494 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14496 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14497 different meaning for some instruction. */
14500 neon_three_same (int isquad
, int ubit
, int size
)
14502 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14503 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14504 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14505 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14506 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14507 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14508 inst
.instruction
|= (isquad
!= 0) << 6;
14509 inst
.instruction
|= (ubit
!= 0) << 24;
14511 inst
.instruction
|= neon_logbits (size
) << 20;
14513 neon_dp_fixup (&inst
);
14516 /* Encode instructions of the form:
14518 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14519 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14521 Don't write size if SIZE == -1. */
14524 neon_two_same (int qbit
, int ubit
, int size
)
14526 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14527 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14528 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14529 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14530 inst
.instruction
|= (qbit
!= 0) << 6;
14531 inst
.instruction
|= (ubit
!= 0) << 24;
14534 inst
.instruction
|= neon_logbits (size
) << 18;
14536 neon_dp_fixup (&inst
);
14539 /* Neon instruction encoders, in approximate order of appearance. */
14542 do_neon_dyadic_i_su (void)
14544 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14545 struct neon_type_el et
= neon_check_type (3, rs
,
14546 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14547 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14551 do_neon_dyadic_i64_su (void)
14553 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14554 struct neon_type_el et
= neon_check_type (3, rs
,
14555 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14556 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14560 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14563 unsigned size
= et
.size
>> 3;
14564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14568 inst
.instruction
|= (isquad
!= 0) << 6;
14569 inst
.instruction
|= immbits
<< 16;
14570 inst
.instruction
|= (size
>> 3) << 7;
14571 inst
.instruction
|= (size
& 0x7) << 19;
14573 inst
.instruction
|= (uval
!= 0) << 24;
14575 neon_dp_fixup (&inst
);
14579 do_neon_shl_imm (void)
14581 if (!inst
.operands
[2].isreg
)
14583 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14584 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14585 int imm
= inst
.operands
[2].imm
;
14587 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14588 _("immediate out of range for shift"));
14589 NEON_ENCODE (IMMED
, inst
);
14590 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14594 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14595 struct neon_type_el et
= neon_check_type (3, rs
,
14596 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14599 /* VSHL/VQSHL 3-register variants have syntax such as:
14601 whereas other 3-register operations encoded by neon_three_same have
14604 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14606 tmp
= inst
.operands
[2].reg
;
14607 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14608 inst
.operands
[1].reg
= tmp
;
14609 NEON_ENCODE (INTEGER
, inst
);
14610 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14615 do_neon_qshl_imm (void)
14617 if (!inst
.operands
[2].isreg
)
14619 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14620 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14621 int imm
= inst
.operands
[2].imm
;
14623 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14624 _("immediate out of range for shift"));
14625 NEON_ENCODE (IMMED
, inst
);
14626 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14630 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14631 struct neon_type_el et
= neon_check_type (3, rs
,
14632 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14635 /* See note in do_neon_shl_imm. */
14636 tmp
= inst
.operands
[2].reg
;
14637 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14638 inst
.operands
[1].reg
= tmp
;
14639 NEON_ENCODE (INTEGER
, inst
);
14640 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14645 do_neon_rshl (void)
14647 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14648 struct neon_type_el et
= neon_check_type (3, rs
,
14649 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14652 tmp
= inst
.operands
[2].reg
;
14653 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14654 inst
.operands
[1].reg
= tmp
;
14655 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14659 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14661 /* Handle .I8 pseudo-instructions. */
14664 /* Unfortunately, this will make everything apart from zero out-of-range.
14665 FIXME is this the intended semantics? There doesn't seem much point in
14666 accepting .I8 if so. */
14667 immediate
|= immediate
<< 8;
14673 if (immediate
== (immediate
& 0x000000ff))
14675 *immbits
= immediate
;
14678 else if (immediate
== (immediate
& 0x0000ff00))
14680 *immbits
= immediate
>> 8;
14683 else if (immediate
== (immediate
& 0x00ff0000))
14685 *immbits
= immediate
>> 16;
14688 else if (immediate
== (immediate
& 0xff000000))
14690 *immbits
= immediate
>> 24;
14693 if ((immediate
& 0xffff) != (immediate
>> 16))
14694 goto bad_immediate
;
14695 immediate
&= 0xffff;
14698 if (immediate
== (immediate
& 0x000000ff))
14700 *immbits
= immediate
;
14703 else if (immediate
== (immediate
& 0x0000ff00))
14705 *immbits
= immediate
>> 8;
14710 first_error (_("immediate value out of range"));
14715 do_neon_logic (void)
14717 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14719 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14720 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14721 /* U bit and size field were set as part of the bitmask. */
14722 NEON_ENCODE (INTEGER
, inst
);
14723 neon_three_same (neon_quad (rs
), 0, -1);
14727 const int three_ops_form
= (inst
.operands
[2].present
14728 && !inst
.operands
[2].isreg
);
14729 const int immoperand
= (three_ops_form
? 2 : 1);
14730 enum neon_shape rs
= (three_ops_form
14731 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14732 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14733 struct neon_type_el et
= neon_check_type (2, rs
,
14734 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14735 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14739 if (et
.type
== NT_invtype
)
14742 if (three_ops_form
)
14743 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14744 _("first and second operands shall be the same register"));
14746 NEON_ENCODE (IMMED
, inst
);
14748 immbits
= inst
.operands
[immoperand
].imm
;
14751 /* .i64 is a pseudo-op, so the immediate must be a repeating
14753 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14754 inst
.operands
[immoperand
].reg
: 0))
14756 /* Set immbits to an invalid constant. */
14757 immbits
= 0xdeadbeef;
14764 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14768 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14772 /* Pseudo-instruction for VBIC. */
14773 neon_invert_size (&immbits
, 0, et
.size
);
14774 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14778 /* Pseudo-instruction for VORR. */
14779 neon_invert_size (&immbits
, 0, et
.size
);
14780 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14790 inst
.instruction
|= neon_quad (rs
) << 6;
14791 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14792 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14793 inst
.instruction
|= cmode
<< 8;
14794 neon_write_immbits (immbits
);
14796 neon_dp_fixup (&inst
);
14801 do_neon_bitfield (void)
14803 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14804 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14805 neon_three_same (neon_quad (rs
), 0, -1);
14809 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14812 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14813 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14815 if (et
.type
== NT_float
)
14817 NEON_ENCODE (FLOAT
, inst
);
14818 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14822 NEON_ENCODE (INTEGER
, inst
);
14823 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14828 do_neon_dyadic_if_su (void)
14830 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14834 do_neon_dyadic_if_su_d (void)
14836 /* This version only allow D registers, but that constraint is enforced during
14837 operand parsing so we don't need to do anything extra here. */
14838 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14842 do_neon_dyadic_if_i_d (void)
14844 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14845 affected if we specify unsigned args. */
14846 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14849 enum vfp_or_neon_is_neon_bits
14852 NEON_CHECK_ARCH
= 2,
14853 NEON_CHECK_ARCH8
= 4
14856 /* Call this function if an instruction which may have belonged to the VFP or
14857 Neon instruction sets, but turned out to be a Neon instruction (due to the
14858 operand types involved, etc.). We have to check and/or fix-up a couple of
14861 - Make sure the user hasn't attempted to make a Neon instruction
14863 - Alter the value in the condition code field if necessary.
14864 - Make sure that the arch supports Neon instructions.
14866 Which of these operations take place depends on bits from enum
14867 vfp_or_neon_is_neon_bits.
14869 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14870 current instruction's condition is COND_ALWAYS, the condition field is
14871 changed to inst.uncond_value. This is necessary because instructions shared
14872 between VFP and Neon may be conditional for the VFP variants only, and the
14873 unconditional Neon version must have, e.g., 0xF in the condition field. */
14876 vfp_or_neon_is_neon (unsigned check
)
14878 /* Conditions are always legal in Thumb mode (IT blocks). */
14879 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14881 if (inst
.cond
!= COND_ALWAYS
)
14883 first_error (_(BAD_COND
));
14886 if (inst
.uncond_value
!= -1)
14887 inst
.instruction
|= inst
.uncond_value
<< 28;
14890 if ((check
& NEON_CHECK_ARCH
)
14891 && !mark_feature_used (&fpu_neon_ext_v1
))
14893 first_error (_(BAD_FPU
));
14897 if ((check
& NEON_CHECK_ARCH8
)
14898 && !mark_feature_used (&fpu_neon_ext_armv8
))
14900 first_error (_(BAD_FPU
));
14908 do_neon_addsub_if_i (void)
14910 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14913 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14916 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14917 affected if we specify unsigned args. */
14918 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14921 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14923 V<op> A,B (A is operand 0, B is operand 2)
14928 so handle that case specially. */
14931 neon_exchange_operands (void)
14933 if (inst
.operands
[1].present
)
14935 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14937 /* Swap operands[1] and operands[2]. */
14938 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14939 inst
.operands
[1] = inst
.operands
[2];
14940 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14945 inst
.operands
[1] = inst
.operands
[2];
14946 inst
.operands
[2] = inst
.operands
[0];
14951 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14953 if (inst
.operands
[2].isreg
)
14956 neon_exchange_operands ();
14957 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14961 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14962 struct neon_type_el et
= neon_check_type (2, rs
,
14963 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14965 NEON_ENCODE (IMMED
, inst
);
14966 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14967 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14968 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14969 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14970 inst
.instruction
|= neon_quad (rs
) << 6;
14971 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14972 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14974 neon_dp_fixup (&inst
);
14981 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14985 do_neon_cmp_inv (void)
14987 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14993 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14996 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14997 scalars, which are encoded in 5 bits, M : Rm.
14998 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14999 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15003 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15005 unsigned regno
= NEON_SCALAR_REG (scalar
);
15006 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15011 if (regno
> 7 || elno
> 3)
15013 return regno
| (elno
<< 3);
15016 if (regno
> 15 || elno
> 1)
15018 return regno
| (elno
<< 4);
15022 first_error (_("scalar out of range for multiply instruction"));
15028 /* Encode multiply / multiply-accumulate scalar instructions. */
15031 neon_mul_mac (struct neon_type_el et
, int ubit
)
15035 /* Give a more helpful error message if we have an invalid type. */
15036 if (et
.type
== NT_invtype
)
15039 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15040 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15041 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15042 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15044 inst
.instruction
|= LOW4 (scalar
);
15045 inst
.instruction
|= HI1 (scalar
) << 5;
15046 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15047 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15048 inst
.instruction
|= (ubit
!= 0) << 24;
15050 neon_dp_fixup (&inst
);
15054 do_neon_mac_maybe_scalar (void)
15056 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15059 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15062 if (inst
.operands
[2].isscalar
)
15064 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15065 struct neon_type_el et
= neon_check_type (3, rs
,
15066 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15067 NEON_ENCODE (SCALAR
, inst
);
15068 neon_mul_mac (et
, neon_quad (rs
));
15072 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15073 affected if we specify unsigned args. */
15074 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15079 do_neon_fmac (void)
15081 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15084 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15087 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15093 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15094 struct neon_type_el et
= neon_check_type (3, rs
,
15095 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15096 neon_three_same (neon_quad (rs
), 0, et
.size
);
15099 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15100 same types as the MAC equivalents. The polynomial type for this instruction
15101 is encoded the same as the integer type. */
15106 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15109 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15112 if (inst
.operands
[2].isscalar
)
15113 do_neon_mac_maybe_scalar ();
15115 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15119 do_neon_qdmulh (void)
15121 if (inst
.operands
[2].isscalar
)
15123 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15124 struct neon_type_el et
= neon_check_type (3, rs
,
15125 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15126 NEON_ENCODE (SCALAR
, inst
);
15127 neon_mul_mac (et
, neon_quad (rs
));
15131 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15132 struct neon_type_el et
= neon_check_type (3, rs
,
15133 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15134 NEON_ENCODE (INTEGER
, inst
);
15135 /* The U bit (rounding) comes from bit mask. */
15136 neon_three_same (neon_quad (rs
), 0, et
.size
);
15141 do_neon_qrdmlah (void)
15143 /* Check we're on the correct architecture. */
15144 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15146 _("instruction form not available on this architecture.");
15147 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15149 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15150 record_feature_use (&fpu_neon_ext_v8_1
);
15153 if (inst
.operands
[2].isscalar
)
15155 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15156 struct neon_type_el et
= neon_check_type (3, rs
,
15157 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15158 NEON_ENCODE (SCALAR
, inst
);
15159 neon_mul_mac (et
, neon_quad (rs
));
15163 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15164 struct neon_type_el et
= neon_check_type (3, rs
,
15165 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15166 NEON_ENCODE (INTEGER
, inst
);
15167 /* The U bit (rounding) comes from bit mask. */
15168 neon_three_same (neon_quad (rs
), 0, et
.size
);
15173 do_neon_fcmp_absolute (void)
15175 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15176 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15177 N_F_16_32
| N_KEY
);
15178 /* Size field comes from bit mask. */
15179 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15183 do_neon_fcmp_absolute_inv (void)
15185 neon_exchange_operands ();
15186 do_neon_fcmp_absolute ();
15190 do_neon_step (void)
15192 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15193 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15194 N_F_16_32
| N_KEY
);
15195 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15199 do_neon_abs_neg (void)
15201 enum neon_shape rs
;
15202 struct neon_type_el et
;
15204 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15207 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15210 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15211 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15213 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15214 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15215 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15216 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15217 inst
.instruction
|= neon_quad (rs
) << 6;
15218 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15219 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15221 neon_dp_fixup (&inst
);
15227 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15228 struct neon_type_el et
= neon_check_type (2, rs
,
15229 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15230 int imm
= inst
.operands
[2].imm
;
15231 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15232 _("immediate out of range for insert"));
15233 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15239 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15240 struct neon_type_el et
= neon_check_type (2, rs
,
15241 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15242 int imm
= inst
.operands
[2].imm
;
15243 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15244 _("immediate out of range for insert"));
15245 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15249 do_neon_qshlu_imm (void)
15251 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15252 struct neon_type_el et
= neon_check_type (2, rs
,
15253 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15254 int imm
= inst
.operands
[2].imm
;
15255 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15256 _("immediate out of range for shift"));
15257 /* Only encodes the 'U present' variant of the instruction.
15258 In this case, signed types have OP (bit 8) set to 0.
15259 Unsigned types have OP set to 1. */
15260 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15261 /* The rest of the bits are the same as other immediate shifts. */
15262 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15266 do_neon_qmovn (void)
15268 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15269 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15270 /* Saturating move where operands can be signed or unsigned, and the
15271 destination has the same signedness. */
15272 NEON_ENCODE (INTEGER
, inst
);
15273 if (et
.type
== NT_unsigned
)
15274 inst
.instruction
|= 0xc0;
15276 inst
.instruction
|= 0x80;
15277 neon_two_same (0, 1, et
.size
/ 2);
15281 do_neon_qmovun (void)
15283 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15284 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15285 /* Saturating move with unsigned results. Operands must be signed. */
15286 NEON_ENCODE (INTEGER
, inst
);
15287 neon_two_same (0, 1, et
.size
/ 2);
15291 do_neon_rshift_sat_narrow (void)
15293 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15294 or unsigned. If operands are unsigned, results must also be unsigned. */
15295 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15296 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15297 int imm
= inst
.operands
[2].imm
;
15298 /* This gets the bounds check, size encoding and immediate bits calculation
15302 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15303 VQMOVN.I<size> <Dd>, <Qm>. */
15306 inst
.operands
[2].present
= 0;
15307 inst
.instruction
= N_MNEM_vqmovn
;
15312 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15313 _("immediate out of range"));
15314 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15318 do_neon_rshift_sat_narrow_u (void)
15320 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15321 or unsigned. If operands are unsigned, results must also be unsigned. */
15322 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15323 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15324 int imm
= inst
.operands
[2].imm
;
15325 /* This gets the bounds check, size encoding and immediate bits calculation
15329 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15330 VQMOVUN.I<size> <Dd>, <Qm>. */
15333 inst
.operands
[2].present
= 0;
15334 inst
.instruction
= N_MNEM_vqmovun
;
15339 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15340 _("immediate out of range"));
15341 /* FIXME: The manual is kind of unclear about what value U should have in
15342 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15344 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15348 do_neon_movn (void)
15350 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15351 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15352 NEON_ENCODE (INTEGER
, inst
);
15353 neon_two_same (0, 1, et
.size
/ 2);
15357 do_neon_rshift_narrow (void)
15359 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15360 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15361 int imm
= inst
.operands
[2].imm
;
15362 /* This gets the bounds check, size encoding and immediate bits calculation
15366 /* If immediate is zero then we are a pseudo-instruction for
15367 VMOVN.I<size> <Dd>, <Qm> */
15370 inst
.operands
[2].present
= 0;
15371 inst
.instruction
= N_MNEM_vmovn
;
15376 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15377 _("immediate out of range for narrowing operation"));
15378 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15382 do_neon_shll (void)
15384 /* FIXME: Type checking when lengthening. */
15385 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15386 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15387 unsigned imm
= inst
.operands
[2].imm
;
15389 if (imm
== et
.size
)
15391 /* Maximum shift variant. */
15392 NEON_ENCODE (INTEGER
, inst
);
15393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15395 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15396 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15397 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15399 neon_dp_fixup (&inst
);
15403 /* A more-specific type check for non-max versions. */
15404 et
= neon_check_type (2, NS_QDI
,
15405 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15406 NEON_ENCODE (IMMED
, inst
);
15407 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15411 /* Check the various types for the VCVT instruction, and return which version
15412 the current instruction is. */
15414 #define CVT_FLAVOUR_VAR \
15415 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15416 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15417 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15418 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15419 /* Half-precision conversions. */ \
15420 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15421 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15422 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15423 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15424 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15425 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15426 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15427 Compared with single/double precision variants, only the co-processor \
15428 field is different, so the encoding flow is reused here. */ \
15429 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15430 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15431 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15432 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15433 /* VFP instructions. */ \
15434 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15435 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15436 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15437 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15438 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15439 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15440 /* VFP instructions with bitshift. */ \
15441 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15442 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15443 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15444 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15445 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15446 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15447 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15448 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15450 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15451 neon_cvt_flavour_##C,
15453 /* The different types of conversions we can do. */
15454 enum neon_cvt_flavour
15457 neon_cvt_flavour_invalid
,
15458 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15463 static enum neon_cvt_flavour
15464 get_neon_cvt_flavour (enum neon_shape rs
)
15466 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15467 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15468 if (et.type != NT_invtype) \
15470 inst.error = NULL; \
15471 return (neon_cvt_flavour_##C); \
15474 struct neon_type_el et
;
15475 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15476 || rs
== NS_FF
) ? N_VFP
: 0;
15477 /* The instruction versions which take an immediate take one register
15478 argument, which is extended to the width of the full register. Thus the
15479 "source" and "destination" registers must have the same width. Hack that
15480 here by making the size equal to the key (wider, in this case) operand. */
15481 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15485 return neon_cvt_flavour_invalid
;
15500 /* Neon-syntax VFP conversions. */
15503 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15505 const char *opname
= 0;
15507 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15508 || rs
== NS_FHI
|| rs
== NS_HFI
)
15510 /* Conversions with immediate bitshift. */
15511 const char *enc
[] =
15513 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15519 if (flavour
< (int) ARRAY_SIZE (enc
))
15521 opname
= enc
[flavour
];
15522 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15523 _("operands 0 and 1 must be the same register"));
15524 inst
.operands
[1] = inst
.operands
[2];
15525 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15530 /* Conversions without bitshift. */
15531 const char *enc
[] =
15533 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15539 if (flavour
< (int) ARRAY_SIZE (enc
))
15540 opname
= enc
[flavour
];
15544 do_vfp_nsyn_opcode (opname
);
15546 /* ARMv8.2 fp16 VCVT instruction. */
15547 if (flavour
== neon_cvt_flavour_s32_f16
15548 || flavour
== neon_cvt_flavour_u32_f16
15549 || flavour
== neon_cvt_flavour_f16_u32
15550 || flavour
== neon_cvt_flavour_f16_s32
)
15551 do_scalar_fp16_v82_encode ();
15555 do_vfp_nsyn_cvtz (void)
15557 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15558 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15559 const char *enc
[] =
15561 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15567 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15568 do_vfp_nsyn_opcode (enc
[flavour
]);
15572 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15573 enum neon_cvt_mode mode
)
15578 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15579 D register operands. */
15580 if (flavour
== neon_cvt_flavour_s32_f64
15581 || flavour
== neon_cvt_flavour_u32_f64
)
15582 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15585 if (flavour
== neon_cvt_flavour_s32_f16
15586 || flavour
== neon_cvt_flavour_u32_f16
)
15587 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15590 set_it_insn_type (OUTSIDE_IT_INSN
);
15594 case neon_cvt_flavour_s32_f64
:
15598 case neon_cvt_flavour_s32_f32
:
15602 case neon_cvt_flavour_s32_f16
:
15606 case neon_cvt_flavour_u32_f64
:
15610 case neon_cvt_flavour_u32_f32
:
15614 case neon_cvt_flavour_u32_f16
:
15619 first_error (_("invalid instruction shape"));
15625 case neon_cvt_mode_a
: rm
= 0; break;
15626 case neon_cvt_mode_n
: rm
= 1; break;
15627 case neon_cvt_mode_p
: rm
= 2; break;
15628 case neon_cvt_mode_m
: rm
= 3; break;
15629 default: first_error (_("invalid rounding mode")); return;
15632 NEON_ENCODE (FPV8
, inst
);
15633 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15634 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15635 inst
.instruction
|= sz
<< 8;
15637 /* ARMv8.2 fp16 VCVT instruction. */
15638 if (flavour
== neon_cvt_flavour_s32_f16
15639 ||flavour
== neon_cvt_flavour_u32_f16
)
15640 do_scalar_fp16_v82_encode ();
15641 inst
.instruction
|= op
<< 7;
15642 inst
.instruction
|= rm
<< 16;
15643 inst
.instruction
|= 0xf0000000;
15644 inst
.is_neon
= TRUE
;
15648 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15650 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15651 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15652 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15654 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15656 if (flavour
== neon_cvt_flavour_invalid
)
15659 /* PR11109: Handle round-to-zero for VCVT conversions. */
15660 if (mode
== neon_cvt_mode_z
15661 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15662 && (flavour
== neon_cvt_flavour_s16_f16
15663 || flavour
== neon_cvt_flavour_u16_f16
15664 || flavour
== neon_cvt_flavour_s32_f32
15665 || flavour
== neon_cvt_flavour_u32_f32
15666 || flavour
== neon_cvt_flavour_s32_f64
15667 || flavour
== neon_cvt_flavour_u32_f64
)
15668 && (rs
== NS_FD
|| rs
== NS_FF
))
15670 do_vfp_nsyn_cvtz ();
15674 /* ARMv8.2 fp16 VCVT conversions. */
15675 if (mode
== neon_cvt_mode_z
15676 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15677 && (flavour
== neon_cvt_flavour_s32_f16
15678 || flavour
== neon_cvt_flavour_u32_f16
)
15681 do_vfp_nsyn_cvtz ();
15682 do_scalar_fp16_v82_encode ();
15686 /* VFP rather than Neon conversions. */
15687 if (flavour
>= neon_cvt_flavour_first_fp
)
15689 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15690 do_vfp_nsyn_cvt (rs
, flavour
);
15692 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15703 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15704 0x0000100, 0x1000100, 0x0, 0x1000000};
15706 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15709 /* Fixed-point conversion with #0 immediate is encoded as an
15710 integer conversion. */
15711 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15713 NEON_ENCODE (IMMED
, inst
);
15714 if (flavour
!= neon_cvt_flavour_invalid
)
15715 inst
.instruction
|= enctab
[flavour
];
15716 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15717 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15719 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15720 inst
.instruction
|= neon_quad (rs
) << 6;
15721 inst
.instruction
|= 1 << 21;
15722 if (flavour
< neon_cvt_flavour_s16_f16
)
15724 inst
.instruction
|= 1 << 21;
15725 immbits
= 32 - inst
.operands
[2].imm
;
15726 inst
.instruction
|= immbits
<< 16;
15730 inst
.instruction
|= 3 << 20;
15731 immbits
= 16 - inst
.operands
[2].imm
;
15732 inst
.instruction
|= immbits
<< 16;
15733 inst
.instruction
&= ~(1 << 9);
15736 neon_dp_fixup (&inst
);
15742 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15744 NEON_ENCODE (FLOAT
, inst
);
15745 set_it_insn_type (OUTSIDE_IT_INSN
);
15747 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15750 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15751 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15752 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15753 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15754 inst
.instruction
|= neon_quad (rs
) << 6;
15755 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15756 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15757 inst
.instruction
|= mode
<< 8;
15758 if (flavour
== neon_cvt_flavour_u16_f16
15759 || flavour
== neon_cvt_flavour_s16_f16
)
15760 /* Mask off the original size bits and reencode them. */
15761 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15764 inst
.instruction
|= 0xfc000000;
15766 inst
.instruction
|= 0xf0000000;
15772 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15773 0x100, 0x180, 0x0, 0x080};
15775 NEON_ENCODE (INTEGER
, inst
);
15777 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15780 if (flavour
!= neon_cvt_flavour_invalid
)
15781 inst
.instruction
|= enctab
[flavour
];
15783 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15784 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15785 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15786 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15787 inst
.instruction
|= neon_quad (rs
) << 6;
15788 if (flavour
>= neon_cvt_flavour_s16_f16
15789 && flavour
<= neon_cvt_flavour_f16_u16
)
15790 /* Half precision. */
15791 inst
.instruction
|= 1 << 18;
15793 inst
.instruction
|= 2 << 18;
15795 neon_dp_fixup (&inst
);
15800 /* Half-precision conversions for Advanced SIMD -- neon. */
15805 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15807 as_bad (_("operand size must match register width"));
15812 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15814 as_bad (_("operand size must match register width"));
15819 inst
.instruction
= 0x3b60600;
15821 inst
.instruction
= 0x3b60700;
15823 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15824 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15825 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15826 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15827 neon_dp_fixup (&inst
);
15831 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15832 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15833 do_vfp_nsyn_cvt (rs
, flavour
);
15835 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15840 do_neon_cvtr (void)
15842 do_neon_cvt_1 (neon_cvt_mode_x
);
15848 do_neon_cvt_1 (neon_cvt_mode_z
);
15852 do_neon_cvta (void)
15854 do_neon_cvt_1 (neon_cvt_mode_a
);
15858 do_neon_cvtn (void)
15860 do_neon_cvt_1 (neon_cvt_mode_n
);
15864 do_neon_cvtp (void)
15866 do_neon_cvt_1 (neon_cvt_mode_p
);
15870 do_neon_cvtm (void)
15872 do_neon_cvt_1 (neon_cvt_mode_m
);
15876 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15879 mark_feature_used (&fpu_vfp_ext_armv8
);
15881 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15882 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15883 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15884 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15885 inst
.instruction
|= to
? 0x10000 : 0;
15886 inst
.instruction
|= t
? 0x80 : 0;
15887 inst
.instruction
|= is_double
? 0x100 : 0;
15888 do_vfp_cond_or_thumb ();
15892 do_neon_cvttb_1 (bfd_boolean t
)
15894 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15895 NS_DF
, NS_DH
, NS_NULL
);
15899 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15902 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15904 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15907 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15909 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15911 /* The VCVTB and VCVTT instructions with D-register operands
15912 don't work for SP only targets. */
15913 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15917 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15919 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15921 /* The VCVTB and VCVTT instructions with D-register operands
15922 don't work for SP only targets. */
15923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15927 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15934 do_neon_cvtb (void)
15936 do_neon_cvttb_1 (FALSE
);
15941 do_neon_cvtt (void)
15943 do_neon_cvttb_1 (TRUE
);
15947 neon_move_immediate (void)
15949 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15950 struct neon_type_el et
= neon_check_type (2, rs
,
15951 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15952 unsigned immlo
, immhi
= 0, immbits
;
15953 int op
, cmode
, float_p
;
15955 constraint (et
.type
== NT_invtype
,
15956 _("operand size must be specified for immediate VMOV"));
15958 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15959 op
= (inst
.instruction
& (1 << 5)) != 0;
15961 immlo
= inst
.operands
[1].imm
;
15962 if (inst
.operands
[1].regisimm
)
15963 immhi
= inst
.operands
[1].reg
;
15965 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15966 _("immediate has bits set outside the operand size"));
15968 float_p
= inst
.operands
[1].immisfloat
;
15970 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15971 et
.size
, et
.type
)) == FAIL
)
15973 /* Invert relevant bits only. */
15974 neon_invert_size (&immlo
, &immhi
, et
.size
);
15975 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15976 with one or the other; those cases are caught by
15977 neon_cmode_for_move_imm. */
15979 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15980 &op
, et
.size
, et
.type
)) == FAIL
)
15982 first_error (_("immediate out of range"));
15987 inst
.instruction
&= ~(1 << 5);
15988 inst
.instruction
|= op
<< 5;
15990 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15991 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15992 inst
.instruction
|= neon_quad (rs
) << 6;
15993 inst
.instruction
|= cmode
<< 8;
15995 neon_write_immbits (immbits
);
16001 if (inst
.operands
[1].isreg
)
16003 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16005 NEON_ENCODE (INTEGER
, inst
);
16006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16007 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16008 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16009 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16010 inst
.instruction
|= neon_quad (rs
) << 6;
16014 NEON_ENCODE (IMMED
, inst
);
16015 neon_move_immediate ();
16018 neon_dp_fixup (&inst
);
16021 /* Encode instructions of form:
16023 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16024 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16027 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16030 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16033 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16034 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16035 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16036 inst
.instruction
|= neon_logbits (size
) << 20;
16038 neon_dp_fixup (&inst
);
16042 do_neon_dyadic_long (void)
16044 /* FIXME: Type checking for lengthening op. */
16045 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16046 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16047 neon_mixed_length (et
, et
.size
);
16051 do_neon_abal (void)
16053 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16054 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16055 neon_mixed_length (et
, et
.size
);
16059 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16061 if (inst
.operands
[2].isscalar
)
16063 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16064 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16065 NEON_ENCODE (SCALAR
, inst
);
16066 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16070 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16071 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16072 NEON_ENCODE (INTEGER
, inst
);
16073 neon_mixed_length (et
, et
.size
);
16078 do_neon_mac_maybe_scalar_long (void)
16080 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16084 do_neon_dyadic_wide (void)
16086 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16087 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16088 neon_mixed_length (et
, et
.size
);
16092 do_neon_dyadic_narrow (void)
16094 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16095 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16096 /* Operand sign is unimportant, and the U bit is part of the opcode,
16097 so force the operand type to integer. */
16098 et
.type
= NT_integer
;
16099 neon_mixed_length (et
, et
.size
/ 2);
16103 do_neon_mul_sat_scalar_long (void)
16105 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16109 do_neon_vmull (void)
16111 if (inst
.operands
[2].isscalar
)
16112 do_neon_mac_maybe_scalar_long ();
16115 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16116 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16118 if (et
.type
== NT_poly
)
16119 NEON_ENCODE (POLY
, inst
);
16121 NEON_ENCODE (INTEGER
, inst
);
16123 /* For polynomial encoding the U bit must be zero, and the size must
16124 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16125 obviously, as 0b10). */
16128 /* Check we're on the correct architecture. */
16129 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16131 _("Instruction form not available on this architecture.");
16136 neon_mixed_length (et
, et
.size
);
16143 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16144 struct neon_type_el et
= neon_check_type (3, rs
,
16145 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16146 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16148 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16149 _("shift out of range"));
16150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16154 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16155 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16156 inst
.instruction
|= neon_quad (rs
) << 6;
16157 inst
.instruction
|= imm
<< 8;
16159 neon_dp_fixup (&inst
);
16165 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16166 struct neon_type_el et
= neon_check_type (2, rs
,
16167 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16168 unsigned op
= (inst
.instruction
>> 7) & 3;
16169 /* N (width of reversed regions) is encoded as part of the bitmask. We
16170 extract it here to check the elements to be reversed are smaller.
16171 Otherwise we'd get a reserved instruction. */
16172 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16173 gas_assert (elsize
!= 0);
16174 constraint (et
.size
>= elsize
,
16175 _("elements must be smaller than reversal region"));
16176 neon_two_same (neon_quad (rs
), 1, et
.size
);
16182 if (inst
.operands
[1].isscalar
)
16184 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16185 struct neon_type_el et
= neon_check_type (2, rs
,
16186 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16187 unsigned sizebits
= et
.size
>> 3;
16188 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16189 int logsize
= neon_logbits (et
.size
);
16190 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16192 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16195 NEON_ENCODE (SCALAR
, inst
);
16196 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16197 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16198 inst
.instruction
|= LOW4 (dm
);
16199 inst
.instruction
|= HI1 (dm
) << 5;
16200 inst
.instruction
|= neon_quad (rs
) << 6;
16201 inst
.instruction
|= x
<< 17;
16202 inst
.instruction
|= sizebits
<< 16;
16204 neon_dp_fixup (&inst
);
16208 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16209 struct neon_type_el et
= neon_check_type (2, rs
,
16210 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16211 /* Duplicate ARM register to lanes of vector. */
16212 NEON_ENCODE (ARMREG
, inst
);
16215 case 8: inst
.instruction
|= 0x400000; break;
16216 case 16: inst
.instruction
|= 0x000020; break;
16217 case 32: inst
.instruction
|= 0x000000; break;
16220 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16221 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16222 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16223 inst
.instruction
|= neon_quad (rs
) << 21;
16224 /* The encoding for this instruction is identical for the ARM and Thumb
16225 variants, except for the condition field. */
16226 do_vfp_cond_or_thumb ();
16230 /* VMOV has particularly many variations. It can be one of:
16231 0. VMOV<c><q> <Qd>, <Qm>
16232 1. VMOV<c><q> <Dd>, <Dm>
16233 (Register operations, which are VORR with Rm = Rn.)
16234 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16235 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16237 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16238 (ARM register to scalar.)
16239 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16240 (Two ARM registers to vector.)
16241 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16242 (Scalar to ARM register.)
16243 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16244 (Vector to two ARM registers.)
16245 8. VMOV.F32 <Sd>, <Sm>
16246 9. VMOV.F64 <Dd>, <Dm>
16247 (VFP register moves.)
16248 10. VMOV.F32 <Sd>, #imm
16249 11. VMOV.F64 <Dd>, #imm
16250 (VFP float immediate load.)
16251 12. VMOV <Rd>, <Sm>
16252 (VFP single to ARM reg.)
16253 13. VMOV <Sd>, <Rm>
16254 (ARM reg to VFP single.)
16255 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16256 (Two ARM regs to two VFP singles.)
16257 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16258 (Two VFP singles to two ARM regs.)
16260 These cases can be disambiguated using neon_select_shape, except cases 1/9
16261 and 3/11 which depend on the operand type too.
16263 All the encoded bits are hardcoded by this function.
16265 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16266 Cases 5, 7 may be used with VFPv2 and above.
16268 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16269 can specify a type where it doesn't make sense to, and is ignored). */
16274 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16275 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16276 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16277 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16278 struct neon_type_el et
;
16279 const char *ldconst
= 0;
16283 case NS_DD
: /* case 1/9. */
16284 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16285 /* It is not an error here if no type is given. */
16287 if (et
.type
== NT_float
&& et
.size
== 64)
16289 do_vfp_nsyn_opcode ("fcpyd");
16292 /* fall through. */
16294 case NS_QQ
: /* case 0/1. */
16296 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16298 /* The architecture manual I have doesn't explicitly state which
16299 value the U bit should have for register->register moves, but
16300 the equivalent VORR instruction has U = 0, so do that. */
16301 inst
.instruction
= 0x0200110;
16302 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16303 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16304 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16305 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16306 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16307 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16308 inst
.instruction
|= neon_quad (rs
) << 6;
16310 neon_dp_fixup (&inst
);
16314 case NS_DI
: /* case 3/11. */
16315 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16317 if (et
.type
== NT_float
&& et
.size
== 64)
16319 /* case 11 (fconstd). */
16320 ldconst
= "fconstd";
16321 goto encode_fconstd
;
16323 /* fall through. */
16325 case NS_QI
: /* case 2/3. */
16326 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16328 inst
.instruction
= 0x0800010;
16329 neon_move_immediate ();
16330 neon_dp_fixup (&inst
);
16333 case NS_SR
: /* case 4. */
16335 unsigned bcdebits
= 0;
16337 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16338 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16340 /* .<size> is optional here, defaulting to .32. */
16341 if (inst
.vectype
.elems
== 0
16342 && inst
.operands
[0].vectype
.type
== NT_invtype
16343 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16345 inst
.vectype
.el
[0].type
= NT_untyped
;
16346 inst
.vectype
.el
[0].size
= 32;
16347 inst
.vectype
.elems
= 1;
16350 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16351 logsize
= neon_logbits (et
.size
);
16353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16356 && et
.size
!= 32, _(BAD_FPU
));
16357 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16358 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16362 case 8: bcdebits
= 0x8; break;
16363 case 16: bcdebits
= 0x1; break;
16364 case 32: bcdebits
= 0x0; break;
16368 bcdebits
|= x
<< logsize
;
16370 inst
.instruction
= 0xe000b10;
16371 do_vfp_cond_or_thumb ();
16372 inst
.instruction
|= LOW4 (dn
) << 16;
16373 inst
.instruction
|= HI1 (dn
) << 7;
16374 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16375 inst
.instruction
|= (bcdebits
& 3) << 5;
16376 inst
.instruction
|= (bcdebits
>> 2) << 21;
16380 case NS_DRR
: /* case 5 (fmdrr). */
16381 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16384 inst
.instruction
= 0xc400b10;
16385 do_vfp_cond_or_thumb ();
16386 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16387 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16388 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16389 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16392 case NS_RS
: /* case 6. */
16395 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16396 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16397 unsigned abcdebits
= 0;
16399 /* .<dt> is optional here, defaulting to .32. */
16400 if (inst
.vectype
.elems
== 0
16401 && inst
.operands
[0].vectype
.type
== NT_invtype
16402 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16404 inst
.vectype
.el
[0].type
= NT_untyped
;
16405 inst
.vectype
.el
[0].size
= 32;
16406 inst
.vectype
.elems
= 1;
16409 et
= neon_check_type (2, NS_NULL
,
16410 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16411 logsize
= neon_logbits (et
.size
);
16413 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16415 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16416 && et
.size
!= 32, _(BAD_FPU
));
16417 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16418 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16422 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16423 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16424 case 32: abcdebits
= 0x00; break;
16428 abcdebits
|= x
<< logsize
;
16429 inst
.instruction
= 0xe100b10;
16430 do_vfp_cond_or_thumb ();
16431 inst
.instruction
|= LOW4 (dn
) << 16;
16432 inst
.instruction
|= HI1 (dn
) << 7;
16433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16434 inst
.instruction
|= (abcdebits
& 3) << 5;
16435 inst
.instruction
|= (abcdebits
>> 2) << 21;
16439 case NS_RRD
: /* case 7 (fmrrd). */
16440 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16443 inst
.instruction
= 0xc500b10;
16444 do_vfp_cond_or_thumb ();
16445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16446 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16447 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16448 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16451 case NS_FF
: /* case 8 (fcpys). */
16452 do_vfp_nsyn_opcode ("fcpys");
16456 case NS_FI
: /* case 10 (fconsts). */
16457 ldconst
= "fconsts";
16459 if (is_quarter_float (inst
.operands
[1].imm
))
16461 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16462 do_vfp_nsyn_opcode (ldconst
);
16464 /* ARMv8.2 fp16 vmov.f16 instruction. */
16466 do_scalar_fp16_v82_encode ();
16469 first_error (_("immediate out of range"));
16473 case NS_RF
: /* case 12 (fmrs). */
16474 do_vfp_nsyn_opcode ("fmrs");
16475 /* ARMv8.2 fp16 vmov.f16 instruction. */
16477 do_scalar_fp16_v82_encode ();
16481 case NS_FR
: /* case 13 (fmsr). */
16482 do_vfp_nsyn_opcode ("fmsr");
16483 /* ARMv8.2 fp16 vmov.f16 instruction. */
16485 do_scalar_fp16_v82_encode ();
16488 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16489 (one of which is a list), but we have parsed four. Do some fiddling to
16490 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16492 case NS_RRFF
: /* case 14 (fmrrs). */
16493 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16494 _("VFP registers must be adjacent"));
16495 inst
.operands
[2].imm
= 2;
16496 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16497 do_vfp_nsyn_opcode ("fmrrs");
16500 case NS_FFRR
: /* case 15 (fmsrr). */
16501 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16502 _("VFP registers must be adjacent"));
16503 inst
.operands
[1] = inst
.operands
[2];
16504 inst
.operands
[2] = inst
.operands
[3];
16505 inst
.operands
[0].imm
= 2;
16506 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16507 do_vfp_nsyn_opcode ("fmsrr");
16511 /* neon_select_shape has determined that the instruction
16512 shape is wrong and has already set the error message. */
16521 do_neon_rshift_round_imm (void)
16523 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16524 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16525 int imm
= inst
.operands
[2].imm
;
16527 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16530 inst
.operands
[2].present
= 0;
16535 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16536 _("immediate out of range for shift"));
16537 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16542 do_neon_movhf (void)
16544 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16545 constraint (rs
!= NS_HH
, _("invalid suffix"));
16547 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16550 do_vfp_sp_monadic ();
16553 inst
.instruction
|= 0xf0000000;
16557 do_neon_movl (void)
16559 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16560 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16561 unsigned sizebits
= et
.size
>> 3;
16562 inst
.instruction
|= sizebits
<< 19;
16563 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16569 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16570 struct neon_type_el et
= neon_check_type (2, rs
,
16571 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16572 NEON_ENCODE (INTEGER
, inst
);
16573 neon_two_same (neon_quad (rs
), 1, et
.size
);
16577 do_neon_zip_uzp (void)
16579 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16580 struct neon_type_el et
= neon_check_type (2, rs
,
16581 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16582 if (rs
== NS_DD
&& et
.size
== 32)
16584 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16585 inst
.instruction
= N_MNEM_vtrn
;
16589 neon_two_same (neon_quad (rs
), 1, et
.size
);
16593 do_neon_sat_abs_neg (void)
16595 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16596 struct neon_type_el et
= neon_check_type (2, rs
,
16597 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16598 neon_two_same (neon_quad (rs
), 1, et
.size
);
16602 do_neon_pair_long (void)
16604 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16605 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16606 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16607 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16608 neon_two_same (neon_quad (rs
), 1, et
.size
);
16612 do_neon_recip_est (void)
16614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16615 struct neon_type_el et
= neon_check_type (2, rs
,
16616 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16617 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16618 neon_two_same (neon_quad (rs
), 1, et
.size
);
16624 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16625 struct neon_type_el et
= neon_check_type (2, rs
,
16626 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16627 neon_two_same (neon_quad (rs
), 1, et
.size
);
16633 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16634 struct neon_type_el et
= neon_check_type (2, rs
,
16635 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16636 neon_two_same (neon_quad (rs
), 1, et
.size
);
16642 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16643 struct neon_type_el et
= neon_check_type (2, rs
,
16644 N_EQK
| N_INT
, N_8
| N_KEY
);
16645 neon_two_same (neon_quad (rs
), 1, et
.size
);
16651 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16652 neon_two_same (neon_quad (rs
), 1, -1);
16656 do_neon_tbl_tbx (void)
16658 unsigned listlenbits
;
16659 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16661 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16663 first_error (_("bad list length for table lookup"));
16667 listlenbits
= inst
.operands
[1].imm
- 1;
16668 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16669 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16670 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16671 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16672 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16673 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16674 inst
.instruction
|= listlenbits
<< 8;
16676 neon_dp_fixup (&inst
);
16680 do_neon_ldm_stm (void)
16682 /* P, U and L bits are part of bitmask. */
16683 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16684 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16686 if (inst
.operands
[1].issingle
)
16688 do_vfp_nsyn_ldm_stm (is_dbmode
);
16692 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16693 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16695 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16696 _("register list must contain at least 1 and at most 16 "
16699 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16700 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16701 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16702 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16704 inst
.instruction
|= offsetbits
;
16706 do_vfp_cond_or_thumb ();
16710 do_neon_ldr_str (void)
16712 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16714 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16715 And is UNPREDICTABLE in thumb mode. */
16717 && inst
.operands
[1].reg
== REG_PC
16718 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16721 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16722 else if (warn_on_deprecated
)
16723 as_tsktsk (_("Use of PC here is deprecated"));
16726 if (inst
.operands
[0].issingle
)
16729 do_vfp_nsyn_opcode ("flds");
16731 do_vfp_nsyn_opcode ("fsts");
16733 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16734 if (inst
.vectype
.el
[0].size
== 16)
16735 do_scalar_fp16_v82_encode ();
16740 do_vfp_nsyn_opcode ("fldd");
16742 do_vfp_nsyn_opcode ("fstd");
16746 /* "interleave" version also handles non-interleaving register VLD1/VST1
16750 do_neon_ld_st_interleave (void)
16752 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16753 N_8
| N_16
| N_32
| N_64
);
16754 unsigned alignbits
= 0;
16756 /* The bits in this table go:
16757 0: register stride of one (0) or two (1)
16758 1,2: register list length, minus one (1, 2, 3, 4).
16759 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16760 We use -1 for invalid entries. */
16761 const int typetable
[] =
16763 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16764 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16765 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16766 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16770 if (et
.type
== NT_invtype
)
16773 if (inst
.operands
[1].immisalign
)
16774 switch (inst
.operands
[1].imm
>> 8)
16776 case 64: alignbits
= 1; break;
16778 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16779 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16780 goto bad_alignment
;
16784 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16785 goto bad_alignment
;
16790 first_error (_("bad alignment"));
16794 inst
.instruction
|= alignbits
<< 4;
16795 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16797 /* Bits [4:6] of the immediate in a list specifier encode register stride
16798 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16799 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16800 up the right value for "type" in a table based on this value and the given
16801 list style, then stick it back. */
16802 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16803 | (((inst
.instruction
>> 8) & 3) << 3);
16805 typebits
= typetable
[idx
];
16807 constraint (typebits
== -1, _("bad list type for instruction"));
16808 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16809 _("bad element type for instruction"));
16811 inst
.instruction
&= ~0xf00;
16812 inst
.instruction
|= typebits
<< 8;
16815 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16816 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16817 otherwise. The variable arguments are a list of pairs of legal (size, align)
16818 values, terminated with -1. */
16821 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16824 int result
= FAIL
, thissize
, thisalign
;
16826 if (!inst
.operands
[1].immisalign
)
16832 va_start (ap
, do_alignment
);
16836 thissize
= va_arg (ap
, int);
16837 if (thissize
== -1)
16839 thisalign
= va_arg (ap
, int);
16841 if (size
== thissize
&& align
== thisalign
)
16844 while (result
!= SUCCESS
);
16848 if (result
== SUCCESS
)
16851 first_error (_("unsupported alignment for instruction"));
16857 do_neon_ld_st_lane (void)
16859 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16860 int align_good
, do_alignment
= 0;
16861 int logsize
= neon_logbits (et
.size
);
16862 int align
= inst
.operands
[1].imm
>> 8;
16863 int n
= (inst
.instruction
>> 8) & 3;
16864 int max_el
= 64 / et
.size
;
16866 if (et
.type
== NT_invtype
)
16869 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16870 _("bad list length"));
16871 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16872 _("scalar index out of range"));
16873 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16875 _("stride of 2 unavailable when element size is 8"));
16879 case 0: /* VLD1 / VST1. */
16880 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16882 if (align_good
== FAIL
)
16886 unsigned alignbits
= 0;
16889 case 16: alignbits
= 0x1; break;
16890 case 32: alignbits
= 0x3; break;
16893 inst
.instruction
|= alignbits
<< 4;
16897 case 1: /* VLD2 / VST2. */
16898 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16899 16, 32, 32, 64, -1);
16900 if (align_good
== FAIL
)
16903 inst
.instruction
|= 1 << 4;
16906 case 2: /* VLD3 / VST3. */
16907 constraint (inst
.operands
[1].immisalign
,
16908 _("can't use alignment with this instruction"));
16911 case 3: /* VLD4 / VST4. */
16912 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16913 16, 64, 32, 64, 32, 128, -1);
16914 if (align_good
== FAIL
)
16918 unsigned alignbits
= 0;
16921 case 8: alignbits
= 0x1; break;
16922 case 16: alignbits
= 0x1; break;
16923 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16926 inst
.instruction
|= alignbits
<< 4;
16933 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16934 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16935 inst
.instruction
|= 1 << (4 + logsize
);
16937 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16938 inst
.instruction
|= logsize
<< 10;
16941 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16944 do_neon_ld_dup (void)
16946 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16947 int align_good
, do_alignment
= 0;
16949 if (et
.type
== NT_invtype
)
16952 switch ((inst
.instruction
>> 8) & 3)
16954 case 0: /* VLD1. */
16955 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16956 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16957 &do_alignment
, 16, 16, 32, 32, -1);
16958 if (align_good
== FAIL
)
16960 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16963 case 2: inst
.instruction
|= 1 << 5; break;
16964 default: first_error (_("bad list length")); return;
16966 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16969 case 1: /* VLD2. */
16970 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16971 &do_alignment
, 8, 16, 16, 32, 32, 64,
16973 if (align_good
== FAIL
)
16975 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16976 _("bad list length"));
16977 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16978 inst
.instruction
|= 1 << 5;
16979 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16982 case 2: /* VLD3. */
16983 constraint (inst
.operands
[1].immisalign
,
16984 _("can't use alignment with this instruction"));
16985 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16986 _("bad list length"));
16987 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16988 inst
.instruction
|= 1 << 5;
16989 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16992 case 3: /* VLD4. */
16994 int align
= inst
.operands
[1].imm
>> 8;
16995 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16996 16, 64, 32, 64, 32, 128, -1);
16997 if (align_good
== FAIL
)
16999 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17000 _("bad list length"));
17001 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17002 inst
.instruction
|= 1 << 5;
17003 if (et
.size
== 32 && align
== 128)
17004 inst
.instruction
|= 0x3 << 6;
17006 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17013 inst
.instruction
|= do_alignment
<< 4;
17016 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17017 apart from bits [11:4]. */
17020 do_neon_ldx_stx (void)
17022 if (inst
.operands
[1].isreg
)
17023 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17025 switch (NEON_LANE (inst
.operands
[0].imm
))
17027 case NEON_INTERLEAVE_LANES
:
17028 NEON_ENCODE (INTERLV
, inst
);
17029 do_neon_ld_st_interleave ();
17032 case NEON_ALL_LANES
:
17033 NEON_ENCODE (DUP
, inst
);
17034 if (inst
.instruction
== N_INV
)
17036 first_error ("only loads support such operands");
17043 NEON_ENCODE (LANE
, inst
);
17044 do_neon_ld_st_lane ();
17047 /* L bit comes from bit mask. */
17048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17049 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17052 if (inst
.operands
[1].postind
)
17054 int postreg
= inst
.operands
[1].imm
& 0xf;
17055 constraint (!inst
.operands
[1].immisreg
,
17056 _("post-index must be a register"));
17057 constraint (postreg
== 0xd || postreg
== 0xf,
17058 _("bad register for post-index"));
17059 inst
.instruction
|= postreg
;
17063 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17064 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17065 || inst
.reloc
.exp
.X_add_number
!= 0,
17068 if (inst
.operands
[1].writeback
)
17070 inst
.instruction
|= 0xd;
17073 inst
.instruction
|= 0xf;
17077 inst
.instruction
|= 0xf9000000;
17079 inst
.instruction
|= 0xf4000000;
17084 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17086 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17087 D register operands. */
17088 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17089 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17092 NEON_ENCODE (FPV8
, inst
);
17094 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17096 do_vfp_sp_dyadic ();
17098 /* ARMv8.2 fp16 instruction. */
17100 do_scalar_fp16_v82_encode ();
17103 do_vfp_dp_rd_rn_rm ();
17106 inst
.instruction
|= 0x100;
17108 inst
.instruction
|= 0xf0000000;
17114 set_it_insn_type (OUTSIDE_IT_INSN
);
17116 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17117 first_error (_("invalid instruction shape"));
17123 set_it_insn_type (OUTSIDE_IT_INSN
);
17125 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17128 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17131 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17135 do_vrint_1 (enum neon_cvt_mode mode
)
17137 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17138 struct neon_type_el et
;
17143 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17144 D register operands. */
17145 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17146 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17149 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17151 if (et
.type
!= NT_invtype
)
17153 /* VFP encodings. */
17154 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17155 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17156 set_it_insn_type (OUTSIDE_IT_INSN
);
17158 NEON_ENCODE (FPV8
, inst
);
17159 if (rs
== NS_FF
|| rs
== NS_HH
)
17160 do_vfp_sp_monadic ();
17162 do_vfp_dp_rd_rm ();
17166 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17167 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17168 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17169 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17170 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17171 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17172 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17176 inst
.instruction
|= (rs
== NS_DD
) << 8;
17177 do_vfp_cond_or_thumb ();
17179 /* ARMv8.2 fp16 vrint instruction. */
17181 do_scalar_fp16_v82_encode ();
17185 /* Neon encodings (or something broken...). */
17187 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17189 if (et
.type
== NT_invtype
)
17192 set_it_insn_type (OUTSIDE_IT_INSN
);
17193 NEON_ENCODE (FLOAT
, inst
);
17195 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17198 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17199 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17200 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17201 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17202 inst
.instruction
|= neon_quad (rs
) << 6;
17203 /* Mask off the original size bits and reencode them. */
17204 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17205 | neon_logbits (et
.size
) << 18);
17209 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17210 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17211 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17212 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17213 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17214 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17215 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17220 inst
.instruction
|= 0xfc000000;
17222 inst
.instruction
|= 0xf0000000;
17229 do_vrint_1 (neon_cvt_mode_x
);
17235 do_vrint_1 (neon_cvt_mode_z
);
17241 do_vrint_1 (neon_cvt_mode_r
);
17247 do_vrint_1 (neon_cvt_mode_a
);
17253 do_vrint_1 (neon_cvt_mode_n
);
17259 do_vrint_1 (neon_cvt_mode_p
);
17265 do_vrint_1 (neon_cvt_mode_m
);
17269 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17271 unsigned regno
= NEON_SCALAR_REG (opnd
);
17272 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17274 if (elsize
== 16 && elno
< 2 && regno
< 16)
17275 return regno
| (elno
<< 4);
17276 else if (elsize
== 32 && elno
== 0)
17279 first_error (_("scalar out of range"));
17286 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17288 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17289 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17290 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17291 _("immediate out of range"));
17293 if (inst
.operands
[2].isscalar
)
17295 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17296 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17297 N_KEY
| N_F16
| N_F32
).size
;
17298 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17300 inst
.instruction
= 0xfe000800;
17301 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17302 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17303 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17304 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17305 inst
.instruction
|= LOW4 (m
);
17306 inst
.instruction
|= HI1 (m
) << 5;
17307 inst
.instruction
|= neon_quad (rs
) << 6;
17308 inst
.instruction
|= rot
<< 20;
17309 inst
.instruction
|= (size
== 32) << 23;
17313 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17314 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17315 N_KEY
| N_F16
| N_F32
).size
;
17316 neon_three_same (neon_quad (rs
), 0, -1);
17317 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17318 inst
.instruction
|= 0xfc200800;
17319 inst
.instruction
|= rot
<< 23;
17320 inst
.instruction
|= (size
== 32) << 20;
17327 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17329 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17330 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17331 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17332 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17333 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17334 N_KEY
| N_F16
| N_F32
).size
;
17335 neon_three_same (neon_quad (rs
), 0, -1);
17336 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17337 inst
.instruction
|= 0xfc800800;
17338 inst
.instruction
|= (rot
== 270) << 24;
17339 inst
.instruction
|= (size
== 32) << 20;
17342 /* Crypto v1 instructions. */
17344 do_crypto_2op_1 (unsigned elttype
, int op
)
17346 set_it_insn_type (OUTSIDE_IT_INSN
);
17348 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17354 NEON_ENCODE (INTEGER
, inst
);
17355 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17356 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17357 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17358 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17360 inst
.instruction
|= op
<< 6;
17363 inst
.instruction
|= 0xfc000000;
17365 inst
.instruction
|= 0xf0000000;
17369 do_crypto_3op_1 (int u
, int op
)
17371 set_it_insn_type (OUTSIDE_IT_INSN
);
17373 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17374 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17379 NEON_ENCODE (INTEGER
, inst
);
17380 neon_three_same (1, u
, 8 << op
);
17386 do_crypto_2op_1 (N_8
, 0);
17392 do_crypto_2op_1 (N_8
, 1);
17398 do_crypto_2op_1 (N_8
, 2);
17404 do_crypto_2op_1 (N_8
, 3);
17410 do_crypto_3op_1 (0, 0);
17416 do_crypto_3op_1 (0, 1);
17422 do_crypto_3op_1 (0, 2);
17428 do_crypto_3op_1 (0, 3);
17434 do_crypto_3op_1 (1, 0);
17440 do_crypto_3op_1 (1, 1);
17444 do_sha256su1 (void)
17446 do_crypto_3op_1 (1, 2);
17452 do_crypto_2op_1 (N_32
, -1);
17458 do_crypto_2op_1 (N_32
, 0);
17462 do_sha256su0 (void)
17464 do_crypto_2op_1 (N_32
, 1);
17468 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17470 unsigned int Rd
= inst
.operands
[0].reg
;
17471 unsigned int Rn
= inst
.operands
[1].reg
;
17472 unsigned int Rm
= inst
.operands
[2].reg
;
17474 set_it_insn_type (OUTSIDE_IT_INSN
);
17475 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17476 inst
.instruction
|= LOW4 (Rn
) << 16;
17477 inst
.instruction
|= LOW4 (Rm
);
17478 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17479 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17481 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17482 as_warn (UNPRED_REG ("r15"));
17483 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17484 as_warn (UNPRED_REG ("r13"));
17526 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17528 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17529 do_vfp_sp_dp_cvt ();
17530 do_vfp_cond_or_thumb ();
17534 /* Overall per-instruction processing. */
17536 /* We need to be able to fix up arbitrary expressions in some statements.
17537 This is so that we can handle symbols that are an arbitrary distance from
17538 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17539 which returns part of an address in a form which will be valid for
17540 a data instruction. We do this by pushing the expression into a symbol
17541 in the expr_section, and creating a fix for that. */
17544 fix_new_arm (fragS
* frag
,
17558 /* Create an absolute valued symbol, so we have something to
17559 refer to in the object file. Unfortunately for us, gas's
17560 generic expression parsing will already have folded out
17561 any use of .set foo/.type foo %function that may have
17562 been used to set type information of the target location,
17563 that's being specified symbolically. We have to presume
17564 the user knows what they are doing. */
17568 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17570 symbol
= symbol_find_or_make (name
);
17571 S_SET_SEGMENT (symbol
, absolute_section
);
17572 symbol_set_frag (symbol
, &zero_address_frag
);
17573 S_SET_VALUE (symbol
, exp
->X_add_number
);
17574 exp
->X_op
= O_symbol
;
17575 exp
->X_add_symbol
= symbol
;
17576 exp
->X_add_number
= 0;
17582 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17583 (enum bfd_reloc_code_real
) reloc
);
17587 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17588 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17592 /* Mark whether the fix is to a THUMB instruction, or an ARM
17594 new_fix
->tc_fix_data
= thumb_mode
;
17597 /* Create a frg for an instruction requiring relaxation. */
17599 output_relax_insn (void)
17605 /* The size of the instruction is unknown, so tie the debug info to the
17606 start of the instruction. */
17607 dwarf2_emit_insn (0);
17609 switch (inst
.reloc
.exp
.X_op
)
17612 sym
= inst
.reloc
.exp
.X_add_symbol
;
17613 offset
= inst
.reloc
.exp
.X_add_number
;
17617 offset
= inst
.reloc
.exp
.X_add_number
;
17620 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17624 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17625 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17626 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17629 /* Write a 32-bit thumb instruction to buf. */
17631 put_thumb32_insn (char * buf
, unsigned long insn
)
17633 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17634 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17638 output_inst (const char * str
)
17644 as_bad ("%s -- `%s'", inst
.error
, str
);
17649 output_relax_insn ();
17652 if (inst
.size
== 0)
17655 to
= frag_more (inst
.size
);
17656 /* PR 9814: Record the thumb mode into the current frag so that we know
17657 what type of NOP padding to use, if necessary. We override any previous
17658 setting so that if the mode has changed then the NOPS that we use will
17659 match the encoding of the last instruction in the frag. */
17660 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17662 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17664 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17665 put_thumb32_insn (to
, inst
.instruction
);
17667 else if (inst
.size
> INSN_SIZE
)
17669 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17670 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17671 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17674 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17676 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17677 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17678 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17681 dwarf2_emit_insn (inst
.size
);
17685 output_it_inst (int cond
, int mask
, char * to
)
17687 unsigned long instruction
= 0xbf00;
17690 instruction
|= mask
;
17691 instruction
|= cond
<< 4;
17695 to
= frag_more (2);
17697 dwarf2_emit_insn (2);
17701 md_number_to_chars (to
, instruction
, 2);
17706 /* Tag values used in struct asm_opcode's tag field. */
17709 OT_unconditional
, /* Instruction cannot be conditionalized.
17710 The ARM condition field is still 0xE. */
17711 OT_unconditionalF
, /* Instruction cannot be conditionalized
17712 and carries 0xF in its ARM condition field. */
17713 OT_csuffix
, /* Instruction takes a conditional suffix. */
17714 OT_csuffixF
, /* Some forms of the instruction take a conditional
17715 suffix, others place 0xF where the condition field
17717 OT_cinfix3
, /* Instruction takes a conditional infix,
17718 beginning at character index 3. (In
17719 unified mode, it becomes a suffix.) */
17720 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17721 tsts, cmps, cmns, and teqs. */
17722 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17723 character index 3, even in unified mode. Used for
17724 legacy instructions where suffix and infix forms
17725 may be ambiguous. */
17726 OT_csuf_or_in3
, /* Instruction takes either a conditional
17727 suffix or an infix at character index 3. */
17728 OT_odd_infix_unc
, /* This is the unconditional variant of an
17729 instruction that takes a conditional infix
17730 at an unusual position. In unified mode,
17731 this variant will accept a suffix. */
17732 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17733 are the conditional variants of instructions that
17734 take conditional infixes in unusual positions.
17735 The infix appears at character index
17736 (tag - OT_odd_infix_0). These are not accepted
17737 in unified mode. */
17740 /* Subroutine of md_assemble, responsible for looking up the primary
17741 opcode from the mnemonic the user wrote. STR points to the
17742 beginning of the mnemonic.
17744 This is not simply a hash table lookup, because of conditional
17745 variants. Most instructions have conditional variants, which are
17746 expressed with a _conditional affix_ to the mnemonic. If we were
17747 to encode each conditional variant as a literal string in the opcode
17748 table, it would have approximately 20,000 entries.
17750 Most mnemonics take this affix as a suffix, and in unified syntax,
17751 'most' is upgraded to 'all'. However, in the divided syntax, some
17752 instructions take the affix as an infix, notably the s-variants of
17753 the arithmetic instructions. Of those instructions, all but six
17754 have the infix appear after the third character of the mnemonic.
17756 Accordingly, the algorithm for looking up primary opcodes given
17759 1. Look up the identifier in the opcode table.
17760 If we find a match, go to step U.
17762 2. Look up the last two characters of the identifier in the
17763 conditions table. If we find a match, look up the first N-2
17764 characters of the identifier in the opcode table. If we
17765 find a match, go to step CE.
17767 3. Look up the fourth and fifth characters of the identifier in
17768 the conditions table. If we find a match, extract those
17769 characters from the identifier, and look up the remaining
17770 characters in the opcode table. If we find a match, go
17775 U. Examine the tag field of the opcode structure, in case this is
17776 one of the six instructions with its conditional infix in an
17777 unusual place. If it is, the tag tells us where to find the
17778 infix; look it up in the conditions table and set inst.cond
17779 accordingly. Otherwise, this is an unconditional instruction.
17780 Again set inst.cond accordingly. Return the opcode structure.
17782 CE. Examine the tag field to make sure this is an instruction that
17783 should receive a conditional suffix. If it is not, fail.
17784 Otherwise, set inst.cond from the suffix we already looked up,
17785 and return the opcode structure.
17787 CM. Examine the tag field to make sure this is an instruction that
17788 should receive a conditional infix after the third character.
17789 If it is not, fail. Otherwise, undo the edits to the current
17790 line of input and proceed as for case CE. */
17792 static const struct asm_opcode
*
17793 opcode_lookup (char **str
)
17797 const struct asm_opcode
*opcode
;
17798 const struct asm_cond
*cond
;
17801 /* Scan up to the end of the mnemonic, which must end in white space,
17802 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17803 for (base
= end
= *str
; *end
!= '\0'; end
++)
17804 if (*end
== ' ' || *end
== '.')
17810 /* Handle a possible width suffix and/or Neon type suffix. */
17815 /* The .w and .n suffixes are only valid if the unified syntax is in
17817 if (unified_syntax
&& end
[1] == 'w')
17819 else if (unified_syntax
&& end
[1] == 'n')
17824 inst
.vectype
.elems
= 0;
17826 *str
= end
+ offset
;
17828 if (end
[offset
] == '.')
17830 /* See if we have a Neon type suffix (possible in either unified or
17831 non-unified ARM syntax mode). */
17832 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17835 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17841 /* Look for unaffixed or special-case affixed mnemonic. */
17842 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17847 if (opcode
->tag
< OT_odd_infix_0
)
17849 inst
.cond
= COND_ALWAYS
;
17853 if (warn_on_deprecated
&& unified_syntax
)
17854 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17855 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17856 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17859 inst
.cond
= cond
->value
;
17863 /* Cannot have a conditional suffix on a mnemonic of less than two
17865 if (end
- base
< 3)
17868 /* Look for suffixed mnemonic. */
17870 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17871 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17873 if (opcode
&& cond
)
17876 switch (opcode
->tag
)
17878 case OT_cinfix3_legacy
:
17879 /* Ignore conditional suffixes matched on infix only mnemonics. */
17883 case OT_cinfix3_deprecated
:
17884 case OT_odd_infix_unc
:
17885 if (!unified_syntax
)
17887 /* Fall through. */
17891 case OT_csuf_or_in3
:
17892 inst
.cond
= cond
->value
;
17895 case OT_unconditional
:
17896 case OT_unconditionalF
:
17898 inst
.cond
= cond
->value
;
17901 /* Delayed diagnostic. */
17902 inst
.error
= BAD_COND
;
17903 inst
.cond
= COND_ALWAYS
;
17912 /* Cannot have a usual-position infix on a mnemonic of less than
17913 six characters (five would be a suffix). */
17914 if (end
- base
< 6)
17917 /* Look for infixed mnemonic in the usual position. */
17919 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17923 memcpy (save
, affix
, 2);
17924 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17925 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17927 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17928 memcpy (affix
, save
, 2);
17931 && (opcode
->tag
== OT_cinfix3
17932 || opcode
->tag
== OT_cinfix3_deprecated
17933 || opcode
->tag
== OT_csuf_or_in3
17934 || opcode
->tag
== OT_cinfix3_legacy
))
17937 if (warn_on_deprecated
&& unified_syntax
17938 && (opcode
->tag
== OT_cinfix3
17939 || opcode
->tag
== OT_cinfix3_deprecated
))
17940 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17942 inst
.cond
= cond
->value
;
17949 /* This function generates an initial IT instruction, leaving its block
17950 virtually open for the new instructions. Eventually,
17951 the mask will be updated by now_it_add_mask () each time
17952 a new instruction needs to be included in the IT block.
17953 Finally, the block is closed with close_automatic_it_block ().
17954 The block closure can be requested either from md_assemble (),
17955 a tencode (), or due to a label hook. */
17958 new_automatic_it_block (int cond
)
17960 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17961 now_it
.mask
= 0x18;
17963 now_it
.block_length
= 1;
17964 mapping_state (MAP_THUMB
);
17965 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17966 now_it
.warn_deprecated
= FALSE
;
17967 now_it
.insn_cond
= TRUE
;
17970 /* Close an automatic IT block.
17971 See comments in new_automatic_it_block (). */
17974 close_automatic_it_block (void)
17976 now_it
.mask
= 0x10;
17977 now_it
.block_length
= 0;
17980 /* Update the mask of the current automatically-generated IT
17981 instruction. See comments in new_automatic_it_block (). */
17984 now_it_add_mask (int cond
)
17986 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17987 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17988 | ((bitvalue) << (nbit)))
17989 const int resulting_bit
= (cond
& 1);
17991 now_it
.mask
&= 0xf;
17992 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17994 (5 - now_it
.block_length
));
17995 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17997 ((5 - now_it
.block_length
) - 1) );
17998 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18001 #undef SET_BIT_VALUE
18004 /* The IT blocks handling machinery is accessed through the these functions:
18005 it_fsm_pre_encode () from md_assemble ()
18006 set_it_insn_type () optional, from the tencode functions
18007 set_it_insn_type_last () ditto
18008 in_it_block () ditto
18009 it_fsm_post_encode () from md_assemble ()
18010 force_automatic_it_block_close () from label habdling functions
18013 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18014 initializing the IT insn type with a generic initial value depending
18015 on the inst.condition.
18016 2) During the tencode function, two things may happen:
18017 a) The tencode function overrides the IT insn type by
18018 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18019 b) The tencode function queries the IT block state by
18020 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18022 Both set_it_insn_type and in_it_block run the internal FSM state
18023 handling function (handle_it_state), because: a) setting the IT insn
18024 type may incur in an invalid state (exiting the function),
18025 and b) querying the state requires the FSM to be updated.
18026 Specifically we want to avoid creating an IT block for conditional
18027 branches, so it_fsm_pre_encode is actually a guess and we can't
18028 determine whether an IT block is required until the tencode () routine
18029 has decided what type of instruction this actually it.
18030 Because of this, if set_it_insn_type and in_it_block have to be used,
18031 set_it_insn_type has to be called first.
18033 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18034 determines the insn IT type depending on the inst.cond code.
18035 When a tencode () routine encodes an instruction that can be
18036 either outside an IT block, or, in the case of being inside, has to be
18037 the last one, set_it_insn_type_last () will determine the proper
18038 IT instruction type based on the inst.cond code. Otherwise,
18039 set_it_insn_type can be called for overriding that logic or
18040 for covering other cases.
18042 Calling handle_it_state () may not transition the IT block state to
18043 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18044 still queried. Instead, if the FSM determines that the state should
18045 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18046 after the tencode () function: that's what it_fsm_post_encode () does.
18048 Since in_it_block () calls the state handling function to get an
18049 updated state, an error may occur (due to invalid insns combination).
18050 In that case, inst.error is set.
18051 Therefore, inst.error has to be checked after the execution of
18052 the tencode () routine.
18054 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18055 any pending state change (if any) that didn't take place in
18056 handle_it_state () as explained above. */
18059 it_fsm_pre_encode (void)
18061 if (inst
.cond
!= COND_ALWAYS
)
18062 inst
.it_insn_type
= INSIDE_IT_INSN
;
18064 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18066 now_it
.state_handled
= 0;
18069 /* IT state FSM handling function. */
18072 handle_it_state (void)
18074 now_it
.state_handled
= 1;
18075 now_it
.insn_cond
= FALSE
;
18077 switch (now_it
.state
)
18079 case OUTSIDE_IT_BLOCK
:
18080 switch (inst
.it_insn_type
)
18082 case OUTSIDE_IT_INSN
:
18085 case INSIDE_IT_INSN
:
18086 case INSIDE_IT_LAST_INSN
:
18087 if (thumb_mode
== 0)
18090 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18091 as_tsktsk (_("Warning: conditional outside an IT block"\
18096 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18097 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18099 /* Automatically generate the IT instruction. */
18100 new_automatic_it_block (inst
.cond
);
18101 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18102 close_automatic_it_block ();
18106 inst
.error
= BAD_OUT_IT
;
18112 case IF_INSIDE_IT_LAST_INSN
:
18113 case NEUTRAL_IT_INSN
:
18117 now_it
.state
= MANUAL_IT_BLOCK
;
18118 now_it
.block_length
= 0;
18123 case AUTOMATIC_IT_BLOCK
:
18124 /* Three things may happen now:
18125 a) We should increment current it block size;
18126 b) We should close current it block (closing insn or 4 insns);
18127 c) We should close current it block and start a new one (due
18128 to incompatible conditions or
18129 4 insns-length block reached). */
18131 switch (inst
.it_insn_type
)
18133 case OUTSIDE_IT_INSN
:
18134 /* The closure of the block shall happen immediately,
18135 so any in_it_block () call reports the block as closed. */
18136 force_automatic_it_block_close ();
18139 case INSIDE_IT_INSN
:
18140 case INSIDE_IT_LAST_INSN
:
18141 case IF_INSIDE_IT_LAST_INSN
:
18142 now_it
.block_length
++;
18144 if (now_it
.block_length
> 4
18145 || !now_it_compatible (inst
.cond
))
18147 force_automatic_it_block_close ();
18148 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18149 new_automatic_it_block (inst
.cond
);
18153 now_it
.insn_cond
= TRUE
;
18154 now_it_add_mask (inst
.cond
);
18157 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18158 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18159 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18160 close_automatic_it_block ();
18163 case NEUTRAL_IT_INSN
:
18164 now_it
.block_length
++;
18165 now_it
.insn_cond
= TRUE
;
18167 if (now_it
.block_length
> 4)
18168 force_automatic_it_block_close ();
18170 now_it_add_mask (now_it
.cc
& 1);
18174 close_automatic_it_block ();
18175 now_it
.state
= MANUAL_IT_BLOCK
;
18180 case MANUAL_IT_BLOCK
:
18182 /* Check conditional suffixes. */
18183 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18186 now_it
.mask
&= 0x1f;
18187 is_last
= (now_it
.mask
== 0x10);
18188 now_it
.insn_cond
= TRUE
;
18190 switch (inst
.it_insn_type
)
18192 case OUTSIDE_IT_INSN
:
18193 inst
.error
= BAD_NOT_IT
;
18196 case INSIDE_IT_INSN
:
18197 if (cond
!= inst
.cond
)
18199 inst
.error
= BAD_IT_COND
;
18204 case INSIDE_IT_LAST_INSN
:
18205 case IF_INSIDE_IT_LAST_INSN
:
18206 if (cond
!= inst
.cond
)
18208 inst
.error
= BAD_IT_COND
;
18213 inst
.error
= BAD_BRANCH
;
18218 case NEUTRAL_IT_INSN
:
18219 /* The BKPT instruction is unconditional even in an IT block. */
18223 inst
.error
= BAD_IT_IT
;
18233 struct depr_insn_mask
18235 unsigned long pattern
;
18236 unsigned long mask
;
18237 const char* description
;
18240 /* List of 16-bit instruction patterns deprecated in an IT block in
18242 static const struct depr_insn_mask depr_it_insns
[] = {
18243 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18244 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18245 { 0xa000, 0xb800, N_("ADR") },
18246 { 0x4800, 0xf800, N_("Literal loads") },
18247 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18248 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18249 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18250 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18251 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18256 it_fsm_post_encode (void)
18260 if (!now_it
.state_handled
)
18261 handle_it_state ();
18263 if (now_it
.insn_cond
18264 && !now_it
.warn_deprecated
18265 && warn_on_deprecated
18266 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18268 if (inst
.instruction
>= 0x10000)
18270 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18271 "deprecated in ARMv8"));
18272 now_it
.warn_deprecated
= TRUE
;
18276 const struct depr_insn_mask
*p
= depr_it_insns
;
18278 while (p
->mask
!= 0)
18280 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18282 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18283 "of the following class are deprecated in ARMv8: "
18284 "%s"), p
->description
);
18285 now_it
.warn_deprecated
= TRUE
;
18293 if (now_it
.block_length
> 1)
18295 as_tsktsk (_("IT blocks containing more than one conditional "
18296 "instruction are deprecated in ARMv8"));
18297 now_it
.warn_deprecated
= TRUE
;
18301 is_last
= (now_it
.mask
== 0x10);
18304 now_it
.state
= OUTSIDE_IT_BLOCK
;
18310 force_automatic_it_block_close (void)
18312 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18314 close_automatic_it_block ();
18315 now_it
.state
= OUTSIDE_IT_BLOCK
;
18323 if (!now_it
.state_handled
)
18324 handle_it_state ();
18326 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18329 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18330 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18331 here, hence the "known" in the function name. */
18334 known_t32_only_insn (const struct asm_opcode
*opcode
)
18336 /* Original Thumb-1 wide instruction. */
18337 if (opcode
->tencode
== do_t_blx
18338 || opcode
->tencode
== do_t_branch23
18339 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18340 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18343 /* Wide-only instruction added to ARMv8-M Baseline. */
18344 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18345 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18346 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18347 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18353 /* Whether wide instruction variant can be used if available for a valid OPCODE
18357 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18359 if (known_t32_only_insn (opcode
))
18362 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18363 of variant T3 of B.W is checked in do_t_branch. */
18364 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18365 && opcode
->tencode
== do_t_branch
)
18368 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18369 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18370 && opcode
->tencode
== do_t_mov_cmp
18371 /* Make sure CMP instruction is not affected. */
18372 && opcode
->aencode
== do_mov
)
18375 /* Wide instruction variants of all instructions with narrow *and* wide
18376 variants become available with ARMv6t2. Other opcodes are either
18377 narrow-only or wide-only and are thus available if OPCODE is valid. */
18378 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18381 /* OPCODE with narrow only instruction variant or wide variant not
18387 md_assemble (char *str
)
18390 const struct asm_opcode
* opcode
;
18392 /* Align the previous label if needed. */
18393 if (last_label_seen
!= NULL
)
18395 symbol_set_frag (last_label_seen
, frag_now
);
18396 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18397 S_SET_SEGMENT (last_label_seen
, now_seg
);
18400 memset (&inst
, '\0', sizeof (inst
));
18401 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18403 opcode
= opcode_lookup (&p
);
18406 /* It wasn't an instruction, but it might be a register alias of
18407 the form alias .req reg, or a Neon .dn/.qn directive. */
18408 if (! create_register_alias (str
, p
)
18409 && ! create_neon_reg_alias (str
, p
))
18410 as_bad (_("bad instruction `%s'"), str
);
18415 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18416 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18418 /* The value which unconditional instructions should have in place of the
18419 condition field. */
18420 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18424 arm_feature_set variant
;
18426 variant
= cpu_variant
;
18427 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18428 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18429 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18430 /* Check that this instruction is supported for this CPU. */
18431 if (!opcode
->tvariant
18432 || (thumb_mode
== 1
18433 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18435 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18438 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18439 && opcode
->tencode
!= do_t_branch
)
18441 as_bad (_("Thumb does not support conditional execution"));
18445 /* Two things are addressed here:
18446 1) Implicit require narrow instructions on Thumb-1.
18447 This avoids relaxation accidentally introducing Thumb-2
18449 2) Reject wide instructions in non Thumb-2 cores.
18451 Only instructions with narrow and wide variants need to be handled
18452 but selecting all non wide-only instructions is easier. */
18453 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18454 && !t32_insn_ok (variant
, opcode
))
18456 if (inst
.size_req
== 0)
18458 else if (inst
.size_req
== 4)
18460 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18461 as_bad (_("selected processor does not support 32bit wide "
18462 "variant of instruction `%s'"), str
);
18464 as_bad (_("selected processor does not support `%s' in "
18465 "Thumb-2 mode"), str
);
18470 inst
.instruction
= opcode
->tvalue
;
18472 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18474 /* Prepare the it_insn_type for those encodings that don't set
18476 it_fsm_pre_encode ();
18478 opcode
->tencode ();
18480 it_fsm_post_encode ();
18483 if (!(inst
.error
|| inst
.relax
))
18485 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18486 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18487 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18489 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18494 /* Something has gone badly wrong if we try to relax a fixed size
18496 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18498 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18499 *opcode
->tvariant
);
18500 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18501 set those bits when Thumb-2 32-bit instructions are seen. The impact
18502 of relaxable instructions will be considered later after we finish all
18504 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18505 variant
= arm_arch_none
;
18507 variant
= cpu_variant
;
18508 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18509 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18512 check_neon_suffixes
;
18516 mapping_state (MAP_THUMB
);
18519 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18523 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18524 is_bx
= (opcode
->aencode
== do_bx
);
18526 /* Check that this instruction is supported for this CPU. */
18527 if (!(is_bx
&& fix_v4bx
)
18528 && !(opcode
->avariant
&&
18529 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18531 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18536 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18540 inst
.instruction
= opcode
->avalue
;
18541 if (opcode
->tag
== OT_unconditionalF
)
18542 inst
.instruction
|= 0xFU
<< 28;
18544 inst
.instruction
|= inst
.cond
<< 28;
18545 inst
.size
= INSN_SIZE
;
18546 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18548 it_fsm_pre_encode ();
18549 opcode
->aencode ();
18550 it_fsm_post_encode ();
18552 /* Arm mode bx is marked as both v4T and v5 because it's still required
18553 on a hypothetical non-thumb v5 core. */
18555 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18557 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18558 *opcode
->avariant
);
18560 check_neon_suffixes
;
18564 mapping_state (MAP_ARM
);
18569 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18577 check_it_blocks_finished (void)
18582 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18583 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18584 == MANUAL_IT_BLOCK
)
18586 as_warn (_("section '%s' finished with an open IT block."),
18590 if (now_it
.state
== MANUAL_IT_BLOCK
)
18591 as_warn (_("file finished with an open IT block."));
18595 /* Various frobbings of labels and their addresses. */
18598 arm_start_line_hook (void)
18600 last_label_seen
= NULL
;
18604 arm_frob_label (symbolS
* sym
)
18606 last_label_seen
= sym
;
18608 ARM_SET_THUMB (sym
, thumb_mode
);
18610 #if defined OBJ_COFF || defined OBJ_ELF
18611 ARM_SET_INTERWORK (sym
, support_interwork
);
18614 force_automatic_it_block_close ();
18616 /* Note - do not allow local symbols (.Lxxx) to be labelled
18617 as Thumb functions. This is because these labels, whilst
18618 they exist inside Thumb code, are not the entry points for
18619 possible ARM->Thumb calls. Also, these labels can be used
18620 as part of a computed goto or switch statement. eg gcc
18621 can generate code that looks like this:
18623 ldr r2, [pc, .Laaa]
18633 The first instruction loads the address of the jump table.
18634 The second instruction converts a table index into a byte offset.
18635 The third instruction gets the jump address out of the table.
18636 The fourth instruction performs the jump.
18638 If the address stored at .Laaa is that of a symbol which has the
18639 Thumb_Func bit set, then the linker will arrange for this address
18640 to have the bottom bit set, which in turn would mean that the
18641 address computation performed by the third instruction would end
18642 up with the bottom bit set. Since the ARM is capable of unaligned
18643 word loads, the instruction would then load the incorrect address
18644 out of the jump table, and chaos would ensue. */
18645 if (label_is_thumb_function_name
18646 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18647 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18649 /* When the address of a Thumb function is taken the bottom
18650 bit of that address should be set. This will allow
18651 interworking between Arm and Thumb functions to work
18654 THUMB_SET_FUNC (sym
, 1);
18656 label_is_thumb_function_name
= FALSE
;
18659 dwarf2_emit_label (sym
);
18663 arm_data_in_code (void)
18665 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18667 *input_line_pointer
= '/';
18668 input_line_pointer
+= 5;
18669 *input_line_pointer
= 0;
18677 arm_canonicalize_symbol_name (char * name
)
18681 if (thumb_mode
&& (len
= strlen (name
)) > 5
18682 && streq (name
+ len
- 5, "/data"))
18683 *(name
+ len
- 5) = 0;
18688 /* Table of all register names defined by default. The user can
18689 define additional names with .req. Note that all register names
18690 should appear in both upper and lowercase variants. Some registers
18691 also have mixed-case names. */
18693 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18694 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18695 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18696 #define REGSET(p,t) \
18697 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18698 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18699 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18700 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18701 #define REGSETH(p,t) \
18702 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18703 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18704 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18705 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18706 #define REGSET2(p,t) \
18707 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18708 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18709 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18710 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18711 #define SPLRBANK(base,bank,t) \
18712 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18713 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18714 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18715 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18716 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18717 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18719 static const struct reg_entry reg_names
[] =
18721 /* ARM integer registers. */
18722 REGSET(r
, RN
), REGSET(R
, RN
),
18724 /* ATPCS synonyms. */
18725 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18726 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18727 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18729 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18730 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18731 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18733 /* Well-known aliases. */
18734 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18735 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18737 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18738 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18740 /* Coprocessor numbers. */
18741 REGSET(p
, CP
), REGSET(P
, CP
),
18743 /* Coprocessor register numbers. The "cr" variants are for backward
18745 REGSET(c
, CN
), REGSET(C
, CN
),
18746 REGSET(cr
, CN
), REGSET(CR
, CN
),
18748 /* ARM banked registers. */
18749 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18750 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18751 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18752 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18753 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18754 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18755 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18757 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18758 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18759 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18760 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18761 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18762 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18763 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18764 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18766 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18767 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18768 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18769 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18770 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18771 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18772 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18773 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18774 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18776 /* FPA registers. */
18777 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18778 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18780 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18781 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18783 /* VFP SP registers. */
18784 REGSET(s
,VFS
), REGSET(S
,VFS
),
18785 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18787 /* VFP DP Registers. */
18788 REGSET(d
,VFD
), REGSET(D
,VFD
),
18789 /* Extra Neon DP registers. */
18790 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18792 /* Neon QP registers. */
18793 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18795 /* VFP control registers. */
18796 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18797 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18798 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18799 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18800 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18801 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18803 /* Maverick DSP coprocessor registers. */
18804 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18805 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18807 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18808 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18809 REGDEF(dspsc
,0,DSPSC
),
18811 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18812 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18813 REGDEF(DSPSC
,0,DSPSC
),
18815 /* iWMMXt data registers - p0, c0-15. */
18816 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18818 /* iWMMXt control registers - p1, c0-3. */
18819 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18820 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18821 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18822 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18824 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18825 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18826 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18827 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18828 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18830 /* XScale accumulator registers. */
18831 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18837 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18838 within psr_required_here. */
18839 static const struct asm_psr psrs
[] =
18841 /* Backward compatibility notation. Note that "all" is no longer
18842 truly all possible PSR bits. */
18843 {"all", PSR_c
| PSR_f
},
18847 /* Individual flags. */
18853 /* Combinations of flags. */
18854 {"fs", PSR_f
| PSR_s
},
18855 {"fx", PSR_f
| PSR_x
},
18856 {"fc", PSR_f
| PSR_c
},
18857 {"sf", PSR_s
| PSR_f
},
18858 {"sx", PSR_s
| PSR_x
},
18859 {"sc", PSR_s
| PSR_c
},
18860 {"xf", PSR_x
| PSR_f
},
18861 {"xs", PSR_x
| PSR_s
},
18862 {"xc", PSR_x
| PSR_c
},
18863 {"cf", PSR_c
| PSR_f
},
18864 {"cs", PSR_c
| PSR_s
},
18865 {"cx", PSR_c
| PSR_x
},
18866 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18867 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18868 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18869 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18870 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18871 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18872 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18873 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18874 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18875 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18876 {"scf", PSR_s
| PSR_c
| PSR_f
},
18877 {"scx", PSR_s
| PSR_c
| PSR_x
},
18878 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18879 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18880 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18881 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18882 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18883 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18884 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18885 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18886 {"csf", PSR_c
| PSR_s
| PSR_f
},
18887 {"csx", PSR_c
| PSR_s
| PSR_x
},
18888 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18889 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18890 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18891 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18892 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18893 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18894 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18895 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18896 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18897 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18898 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18899 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18900 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18901 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18902 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18903 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18904 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18905 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18906 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18907 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18908 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18909 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18910 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18911 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18912 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18913 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18916 /* Table of V7M psr names. */
18917 static const struct asm_psr v7m_psrs
[] =
18919 {"apsr", 0x0 }, {"APSR", 0x0 },
18920 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18921 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18922 {"psr", 0x3 }, {"PSR", 0x3 },
18923 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18924 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18925 {"epsr", 0x6 }, {"EPSR", 0x6 },
18926 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18927 {"msp", 0x8 }, {"MSP", 0x8 },
18928 {"psp", 0x9 }, {"PSP", 0x9 },
18929 {"msplim", 0xa }, {"MSPLIM", 0xa },
18930 {"psplim", 0xb }, {"PSPLIM", 0xb },
18931 {"primask", 0x10}, {"PRIMASK", 0x10},
18932 {"basepri", 0x11}, {"BASEPRI", 0x11},
18933 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18934 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18935 {"control", 0x14}, {"CONTROL", 0x14},
18936 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18937 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18938 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18939 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18940 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18941 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18942 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18943 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18944 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18947 /* Table of all shift-in-operand names. */
18948 static const struct asm_shift_name shift_names
[] =
18950 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18951 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18952 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18953 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18954 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18955 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18958 /* Table of all explicit relocation names. */
18960 static struct reloc_entry reloc_names
[] =
18962 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18963 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18964 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18965 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18966 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18967 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18968 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18969 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18970 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18971 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18972 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18973 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18974 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18975 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18976 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18977 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18978 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18979 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18983 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18984 static const struct asm_cond conds
[] =
18988 {"cs", 0x2}, {"hs", 0x2},
18989 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19003 #define UL_BARRIER(L,U,CODE,FEAT) \
19004 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19005 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19007 static struct asm_barrier_opt barrier_opt_names
[] =
19009 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19010 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19011 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19012 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19013 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19014 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19015 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19016 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19017 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19018 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19019 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19020 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19021 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19022 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19023 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19024 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19029 /* Table of ARM-format instructions. */
19031 /* Macros for gluing together operand strings. N.B. In all cases
19032 other than OPS0, the trailing OP_stop comes from default
19033 zero-initialization of the unspecified elements of the array. */
19034 #define OPS0() { OP_stop, }
19035 #define OPS1(a) { OP_##a, }
19036 #define OPS2(a,b) { OP_##a,OP_##b, }
19037 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19038 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19039 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19040 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19042 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19043 This is useful when mixing operands for ARM and THUMB, i.e. using the
19044 MIX_ARM_THUMB_OPERANDS macro.
19045 In order to use these macros, prefix the number of operands with _
19047 #define OPS_1(a) { a, }
19048 #define OPS_2(a,b) { a,b, }
19049 #define OPS_3(a,b,c) { a,b,c, }
19050 #define OPS_4(a,b,c,d) { a,b,c,d, }
19051 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19052 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19054 /* These macros abstract out the exact format of the mnemonic table and
19055 save some repeated characters. */
19057 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19058 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19059 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19060 THUMB_VARIANT, do_##ae, do_##te }
19062 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19063 a T_MNEM_xyz enumerator. */
19064 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19065 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19066 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19067 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19069 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19070 infix after the third character. */
19071 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19072 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19073 THUMB_VARIANT, do_##ae, do_##te }
19074 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19075 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19076 THUMB_VARIANT, do_##ae, do_##te }
19077 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19078 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19079 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19080 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19081 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19082 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19083 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19084 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19086 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19087 field is still 0xE. Many of the Thumb variants can be executed
19088 conditionally, so this is checked separately. */
19089 #define TUE(mnem, op, top, nops, ops, ae, te) \
19090 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19091 THUMB_VARIANT, do_##ae, do_##te }
19093 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19094 Used by mnemonics that have very minimal differences in the encoding for
19095 ARM and Thumb variants and can be handled in a common function. */
19096 #define TUEc(mnem, op, top, nops, ops, en) \
19097 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19098 THUMB_VARIANT, do_##en, do_##en }
19100 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19101 condition code field. */
19102 #define TUF(mnem, op, top, nops, ops, ae, te) \
19103 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19104 THUMB_VARIANT, do_##ae, do_##te }
19106 /* ARM-only variants of all the above. */
19107 #define CE(mnem, op, nops, ops, ae) \
19108 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19110 #define C3(mnem, op, nops, ops, ae) \
19111 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19113 /* Legacy mnemonics that always have conditional infix after the third
19115 #define CL(mnem, op, nops, ops, ae) \
19116 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19117 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19119 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19120 #define cCE(mnem, op, nops, ops, ae) \
19121 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19123 /* Legacy coprocessor instructions where conditional infix and conditional
19124 suffix are ambiguous. For consistency this includes all FPA instructions,
19125 not just the potentially ambiguous ones. */
19126 #define cCL(mnem, op, nops, ops, ae) \
19127 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19128 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19130 /* Coprocessor, takes either a suffix or a position-3 infix
19131 (for an FPA corner case). */
19132 #define C3E(mnem, op, nops, ops, ae) \
19133 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19134 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19136 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19137 { m1 #m2 m3, OPS##nops ops, \
19138 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19139 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19141 #define CM(m1, m2, op, nops, ops, ae) \
19142 xCM_ (m1, , m2, op, nops, ops, ae), \
19143 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19144 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19145 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19146 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19147 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19148 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19149 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19150 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19151 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19152 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19153 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19154 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19155 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19156 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19157 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19158 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19159 xCM_ (m1, le, m2, op, nops, ops, ae), \
19160 xCM_ (m1, al, m2, op, nops, ops, ae)
19162 #define UE(mnem, op, nops, ops, ae) \
19163 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19165 #define UF(mnem, op, nops, ops, ae) \
19166 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19168 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19169 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19170 use the same encoding function for each. */
19171 #define NUF(mnem, op, nops, ops, enc) \
19172 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19173 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19175 /* Neon data processing, version which indirects through neon_enc_tab for
19176 the various overloaded versions of opcodes. */
19177 #define nUF(mnem, op, nops, ops, enc) \
19178 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19179 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19181 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19183 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19184 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19185 THUMB_VARIANT, do_##enc, do_##enc }
19187 #define NCE(mnem, op, nops, ops, enc) \
19188 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19190 #define NCEF(mnem, op, nops, ops, enc) \
19191 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19193 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19194 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19195 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19196 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19198 #define nCE(mnem, op, nops, ops, enc) \
19199 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19201 #define nCEF(mnem, op, nops, ops, enc) \
19202 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19206 static const struct asm_opcode insns
[] =
19208 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19209 #define THUMB_VARIANT & arm_ext_v4t
19210 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19211 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19212 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19213 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19214 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19215 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19216 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19217 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19218 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19219 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19220 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19221 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19222 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19223 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19224 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19225 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19227 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19228 for setting PSR flag bits. They are obsolete in V6 and do not
19229 have Thumb equivalents. */
19230 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19231 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19232 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19233 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19234 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19235 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19236 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19237 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19238 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19240 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19241 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19242 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19243 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19245 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19246 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19247 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19249 OP_ADDRGLDR
),ldst
, t_ldst
),
19250 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19252 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19253 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19254 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19255 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19256 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19257 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19259 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19260 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19261 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19262 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19265 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19266 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19267 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19268 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19270 /* Thumb-compatibility pseudo ops. */
19271 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19272 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19273 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19274 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19275 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19276 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19277 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19278 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19279 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19280 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19281 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19282 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19284 /* These may simplify to neg. */
19285 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19286 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19288 #undef THUMB_VARIANT
19289 #define THUMB_VARIANT & arm_ext_v6
19291 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19293 /* V1 instructions with no Thumb analogue prior to V6T2. */
19294 #undef THUMB_VARIANT
19295 #define THUMB_VARIANT & arm_ext_v6t2
19297 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19298 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19299 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19301 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19302 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19303 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19304 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19306 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19307 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19309 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19310 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19312 /* V1 instructions with no Thumb analogue at all. */
19313 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19314 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19316 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19317 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19318 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19319 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19320 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19321 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19322 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19323 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19326 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19327 #undef THUMB_VARIANT
19328 #define THUMB_VARIANT & arm_ext_v4t
19330 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19331 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19333 #undef THUMB_VARIANT
19334 #define THUMB_VARIANT & arm_ext_v6t2
19336 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19337 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19339 /* Generic coprocessor instructions. */
19340 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19341 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19342 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19343 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19344 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19345 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19346 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19349 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19351 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19352 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19355 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19356 #undef THUMB_VARIANT
19357 #define THUMB_VARIANT & arm_ext_msr
19359 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19360 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19363 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19364 #undef THUMB_VARIANT
19365 #define THUMB_VARIANT & arm_ext_v6t2
19367 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19368 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19369 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19370 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19371 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19372 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19373 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19374 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19377 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19378 #undef THUMB_VARIANT
19379 #define THUMB_VARIANT & arm_ext_v4t
19381 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19382 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19383 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19384 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19385 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19386 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19389 #define ARM_VARIANT & arm_ext_v4t_5
19391 /* ARM Architecture 4T. */
19392 /* Note: bx (and blx) are required on V5, even if the processor does
19393 not support Thumb. */
19394 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19397 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19398 #undef THUMB_VARIANT
19399 #define THUMB_VARIANT & arm_ext_v5t
19401 /* Note: blx has 2 variants; the .value coded here is for
19402 BLX(2). Only this variant has conditional execution. */
19403 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19404 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19406 #undef THUMB_VARIANT
19407 #define THUMB_VARIANT & arm_ext_v6t2
19409 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19410 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19411 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19412 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19413 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19414 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19415 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19416 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19419 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19420 #undef THUMB_VARIANT
19421 #define THUMB_VARIANT & arm_ext_v5exp
19423 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19424 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19425 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19426 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19428 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19429 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19431 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19432 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19433 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19434 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19436 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19437 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19438 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19439 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19441 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19442 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19444 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19445 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19446 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19447 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19450 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19451 #undef THUMB_VARIANT
19452 #define THUMB_VARIANT & arm_ext_v6t2
19454 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19455 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19457 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19458 ADDRGLDRS
), ldrd
, t_ldstd
),
19460 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19461 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19464 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19466 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19469 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19470 #undef THUMB_VARIANT
19471 #define THUMB_VARIANT & arm_ext_v6
19473 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19474 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19475 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19476 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19477 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19478 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19479 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19480 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19481 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19482 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19484 #undef THUMB_VARIANT
19485 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19487 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19488 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19490 #undef THUMB_VARIANT
19491 #define THUMB_VARIANT & arm_ext_v6t2
19493 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19494 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19496 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19497 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19499 /* ARM V6 not included in V7M. */
19500 #undef THUMB_VARIANT
19501 #define THUMB_VARIANT & arm_ext_v6_notm
19502 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19503 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19504 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19505 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19506 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19507 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19508 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19509 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19510 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19511 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19512 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19513 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19514 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19515 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19516 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19517 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19518 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19519 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19520 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19522 /* ARM V6 not included in V7M (eg. integer SIMD). */
19523 #undef THUMB_VARIANT
19524 #define THUMB_VARIANT & arm_ext_v6_dsp
19525 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19526 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19527 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19528 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19529 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19530 /* Old name for QASX. */
19531 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19532 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19533 /* Old name for QSAX. */
19534 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19535 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19536 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19537 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19538 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19539 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19540 /* Old name for SASX. */
19541 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19542 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19543 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19544 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19545 /* Old name for SHASX. */
19546 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19547 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19548 /* Old name for SHSAX. */
19549 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19550 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19551 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19552 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19553 /* Old name for SSAX. */
19554 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19555 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19556 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19557 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19558 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19559 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19560 /* Old name for UASX. */
19561 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19562 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19563 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19564 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19565 /* Old name for UHASX. */
19566 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19567 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 /* Old name for UHSAX. */
19569 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19570 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19571 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19572 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19573 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19574 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 /* Old name for UQASX. */
19576 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19577 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19578 /* Old name for UQSAX. */
19579 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19580 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19582 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19583 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 /* Old name for USAX. */
19585 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19586 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19587 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19588 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19589 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19590 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19591 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19592 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19593 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19594 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19595 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19596 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19597 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19598 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19599 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19600 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19601 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19602 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19603 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19604 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19605 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19606 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19607 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19608 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19609 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19610 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19611 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19612 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19613 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19614 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19615 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19616 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19617 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19618 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19621 #define ARM_VARIANT & arm_ext_v6k
19622 #undef THUMB_VARIANT
19623 #define THUMB_VARIANT & arm_ext_v6k
19625 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19626 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19627 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19628 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19630 #undef THUMB_VARIANT
19631 #define THUMB_VARIANT & arm_ext_v6_notm
19632 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19634 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19635 RRnpcb
), strexd
, t_strexd
),
19637 #undef THUMB_VARIANT
19638 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19639 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19641 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19643 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19645 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19647 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19650 #define ARM_VARIANT & arm_ext_sec
19651 #undef THUMB_VARIANT
19652 #define THUMB_VARIANT & arm_ext_sec
19654 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19657 #define ARM_VARIANT & arm_ext_virt
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & arm_ext_virt
19661 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19662 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19665 #define ARM_VARIANT & arm_ext_pan
19666 #undef THUMB_VARIANT
19667 #define THUMB_VARIANT & arm_ext_pan
19669 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19672 #define ARM_VARIANT & arm_ext_v6t2
19673 #undef THUMB_VARIANT
19674 #define THUMB_VARIANT & arm_ext_v6t2
19676 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19677 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19678 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19679 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19681 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19682 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19684 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19685 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19686 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19687 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19689 #undef THUMB_VARIANT
19690 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19691 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19692 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19694 /* Thumb-only instructions. */
19696 #define ARM_VARIANT NULL
19697 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19698 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19700 /* ARM does not really have an IT instruction, so always allow it.
19701 The opcode is copied from Thumb in order to allow warnings in
19702 -mimplicit-it=[never | arm] modes. */
19704 #define ARM_VARIANT & arm_ext_v1
19705 #undef THUMB_VARIANT
19706 #define THUMB_VARIANT & arm_ext_v6t2
19708 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19709 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19710 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19711 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19712 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19713 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19714 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19715 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19716 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19717 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19718 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19719 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19720 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19721 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19722 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19723 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19724 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19725 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19727 /* Thumb2 only instructions. */
19729 #define ARM_VARIANT NULL
19731 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19732 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19733 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19734 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19735 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19736 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19738 /* Hardware division instructions. */
19740 #define ARM_VARIANT & arm_ext_adiv
19741 #undef THUMB_VARIANT
19742 #define THUMB_VARIANT & arm_ext_div
19744 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19745 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19747 /* ARM V6M/V7 instructions. */
19749 #define ARM_VARIANT & arm_ext_barrier
19750 #undef THUMB_VARIANT
19751 #define THUMB_VARIANT & arm_ext_barrier
19753 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19754 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19755 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19757 /* ARM V7 instructions. */
19759 #define ARM_VARIANT & arm_ext_v7
19760 #undef THUMB_VARIANT
19761 #define THUMB_VARIANT & arm_ext_v7
19763 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19764 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19767 #define ARM_VARIANT & arm_ext_mp
19768 #undef THUMB_VARIANT
19769 #define THUMB_VARIANT & arm_ext_mp
19771 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19773 /* AArchv8 instructions. */
19775 #define ARM_VARIANT & arm_ext_v8
19777 /* Instructions shared between armv8-a and armv8-m. */
19778 #undef THUMB_VARIANT
19779 #define THUMB_VARIANT & arm_ext_atomics
19781 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19782 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19783 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19784 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19785 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19786 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19787 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19788 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19789 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19790 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19792 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19794 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19796 #undef THUMB_VARIANT
19797 #define THUMB_VARIANT & arm_ext_v8
19799 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19800 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19801 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19803 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19805 /* ARMv8 T32 only. */
19807 #define ARM_VARIANT NULL
19808 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19809 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19810 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19812 /* FP for ARMv8. */
19814 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19815 #undef THUMB_VARIANT
19816 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19818 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19819 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19820 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19821 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19822 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19823 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19824 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19825 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19826 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19827 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19828 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19829 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19830 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19831 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19832 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19833 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19834 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19836 /* Crypto v1 extensions. */
19838 #define ARM_VARIANT & fpu_crypto_ext_armv8
19839 #undef THUMB_VARIANT
19840 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19842 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19843 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19844 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19845 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19846 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19847 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19848 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19849 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19850 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19851 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19852 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19853 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19854 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19855 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19858 #define ARM_VARIANT & crc_ext_armv8
19859 #undef THUMB_VARIANT
19860 #define THUMB_VARIANT & crc_ext_armv8
19861 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19862 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19863 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19864 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19865 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19866 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19868 /* ARMv8.2 RAS extension. */
19870 #define ARM_VARIANT & arm_ext_ras
19871 #undef THUMB_VARIANT
19872 #define THUMB_VARIANT & arm_ext_ras
19873 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19876 #define ARM_VARIANT & arm_ext_v8_3
19877 #undef THUMB_VARIANT
19878 #define THUMB_VARIANT & arm_ext_v8_3
19879 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19880 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19881 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19884 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19885 #undef THUMB_VARIANT
19886 #define THUMB_VARIANT NULL
19888 cCE("wfs", e200110
, 1, (RR
), rd
),
19889 cCE("rfs", e300110
, 1, (RR
), rd
),
19890 cCE("wfc", e400110
, 1, (RR
), rd
),
19891 cCE("rfc", e500110
, 1, (RR
), rd
),
19893 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19894 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19895 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19896 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19898 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19899 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19900 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19901 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19903 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19997 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20010 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20023 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20036 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20049 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20062 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20075 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20088 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20101 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20121 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20127 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20128 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20130 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20134 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20140 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20141 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20166 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20179 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20192 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20205 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20206 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20208 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20211 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20218 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20219 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20221 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20224 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20231 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20232 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20244 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20257 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20270 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20281 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20282 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20283 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20285 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20286 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20287 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20288 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20289 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20290 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20291 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20292 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20293 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20294 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20295 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20296 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20298 /* The implementation of the FIX instruction is broken on some
20299 assemblers, in that it accepts a precision specifier as well as a
20300 rounding specifier, despite the fact that this is meaningless.
20301 To be more compatible, we accept it as well, though of course it
20302 does not set any bits. */
20303 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20304 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20305 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20306 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20307 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20308 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20309 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20310 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20311 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20312 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20313 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20314 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20315 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20317 /* Instructions that were new with the real FPA, call them V2. */
20319 #define ARM_VARIANT & fpu_fpa_ext_v2
20321 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20322 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20323 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20324 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20325 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20326 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20329 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20331 /* Moves and type conversions. */
20332 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20333 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20334 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20335 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20336 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20337 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20338 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20339 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20340 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20341 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20342 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20343 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20344 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20345 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20347 /* Memory operations. */
20348 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20349 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20350 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20351 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20352 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20353 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20354 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20355 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20356 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20357 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20358 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20359 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20360 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20361 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20362 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20363 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20364 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20365 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20367 /* Monadic operations. */
20368 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20369 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20370 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20372 /* Dyadic operations. */
20373 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20374 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20375 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20376 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20377 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20378 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20379 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20380 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20381 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20384 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20385 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20386 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20387 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20389 /* Double precision load/store are still present on single precision
20390 implementations. */
20391 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20392 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20393 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20394 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20395 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20396 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20397 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20398 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20399 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20400 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20403 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20405 /* Moves and type conversions. */
20406 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20407 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20408 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20409 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20410 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20411 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20412 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20413 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20414 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20415 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20416 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20417 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20418 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20420 /* Monadic operations. */
20421 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20422 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20423 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20425 /* Dyadic operations. */
20426 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20427 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20428 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20429 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20430 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20431 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20432 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20433 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20434 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20437 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20438 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20439 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20440 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20443 #define ARM_VARIANT & fpu_vfp_ext_v2
20445 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20446 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20447 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20448 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20450 /* Instructions which may belong to either the Neon or VFP instruction sets.
20451 Individual encoder functions perform additional architecture checks. */
20453 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20454 #undef THUMB_VARIANT
20455 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20457 /* These mnemonics are unique to VFP. */
20458 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20459 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20460 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20461 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20462 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20463 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20464 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20465 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20466 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20467 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20469 /* Mnemonics shared by Neon and VFP. */
20470 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20471 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20472 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20474 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20475 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20477 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20478 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20480 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20481 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20482 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20483 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20484 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20485 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20486 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20487 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20489 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20490 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20491 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20492 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20495 /* NOTE: All VMOV encoding is special-cased! */
20496 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20497 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20500 #define ARM_VARIANT & arm_ext_fp16
20501 #undef THUMB_VARIANT
20502 #define THUMB_VARIANT & arm_ext_fp16
20503 /* New instructions added from v8.2, allowing the extraction and insertion of
20504 the upper 16 bits of a 32-bit vector register. */
20505 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20506 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20508 #undef THUMB_VARIANT
20509 #define THUMB_VARIANT & fpu_neon_ext_v1
20511 #define ARM_VARIANT & fpu_neon_ext_v1
20513 /* Data processing with three registers of the same length. */
20514 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20515 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20516 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20517 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20518 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20519 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20520 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20521 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20522 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20523 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20524 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20525 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20526 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20527 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20528 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20529 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20530 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20531 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20532 /* If not immediate, fall back to neon_dyadic_i64_su.
20533 shl_imm should accept I8 I16 I32 I64,
20534 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20535 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20536 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20537 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20538 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20539 /* Logic ops, types optional & ignored. */
20540 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20541 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20542 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20543 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20544 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20545 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20546 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20547 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20548 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20549 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20550 /* Bitfield ops, untyped. */
20551 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20552 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20553 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20554 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20555 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20556 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20557 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20558 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20559 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20560 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20561 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20562 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20563 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20564 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20565 back to neon_dyadic_if_su. */
20566 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20567 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20568 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20569 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20570 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20571 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20572 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20573 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20574 /* Comparison. Type I8 I16 I32 F32. */
20575 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20576 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20577 /* As above, D registers only. */
20578 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20579 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20580 /* Int and float variants, signedness unimportant. */
20581 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20582 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20583 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20584 /* Add/sub take types I8 I16 I32 I64 F32. */
20585 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20586 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20587 /* vtst takes sizes 8, 16, 32. */
20588 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20589 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20590 /* VMUL takes I8 I16 I32 F32 P8. */
20591 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20592 /* VQD{R}MULH takes S16 S32. */
20593 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20594 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20595 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20596 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20597 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20598 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20599 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20600 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20601 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20602 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20603 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20604 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20605 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20606 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20607 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20608 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20609 /* ARM v8.1 extension. */
20610 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20611 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20612 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20613 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20615 /* Two address, int/float. Types S8 S16 S32 F32. */
20616 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20617 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20619 /* Data processing with two registers and a shift amount. */
20620 /* Right shifts, and variants with rounding.
20621 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20622 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20623 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20624 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20625 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20626 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20627 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20628 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20629 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20630 /* Shift and insert. Sizes accepted 8 16 32 64. */
20631 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20632 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20633 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20634 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20635 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20636 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20637 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20638 /* Right shift immediate, saturating & narrowing, with rounding variants.
20639 Types accepted S16 S32 S64 U16 U32 U64. */
20640 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20641 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20642 /* As above, unsigned. Types accepted S16 S32 S64. */
20643 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20644 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20645 /* Right shift narrowing. Types accepted I16 I32 I64. */
20646 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20647 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20648 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20649 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20650 /* CVT with optional immediate for fixed-point variant. */
20651 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20653 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20654 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20656 /* Data processing, three registers of different lengths. */
20657 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20658 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20659 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20660 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20661 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20662 /* If not scalar, fall back to neon_dyadic_long.
20663 Vector types as above, scalar types S16 S32 U16 U32. */
20664 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20665 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20666 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20667 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20668 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20669 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20670 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20671 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20672 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20673 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20674 /* Saturating doubling multiplies. Types S16 S32. */
20675 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20676 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20677 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20678 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20679 S16 S32 U16 U32. */
20680 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20682 /* Extract. Size 8. */
20683 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20684 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20686 /* Two registers, miscellaneous. */
20687 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20688 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20689 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20690 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20691 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20692 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20693 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20694 /* Vector replicate. Sizes 8 16 32. */
20695 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20696 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20697 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20698 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20699 /* VMOVN. Types I16 I32 I64. */
20700 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20701 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20702 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20703 /* VQMOVUN. Types S16 S32 S64. */
20704 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20705 /* VZIP / VUZP. Sizes 8 16 32. */
20706 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20707 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20708 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20709 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20710 /* VQABS / VQNEG. Types S8 S16 S32. */
20711 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20712 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20713 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20714 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20715 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20716 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20717 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20718 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20719 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20720 /* Reciprocal estimates. Types U32 F16 F32. */
20721 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20722 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20723 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20724 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20725 /* VCLS. Types S8 S16 S32. */
20726 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20727 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20728 /* VCLZ. Types I8 I16 I32. */
20729 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20730 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20731 /* VCNT. Size 8. */
20732 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20733 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20734 /* Two address, untyped. */
20735 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20736 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20737 /* VTRN. Sizes 8 16 32. */
20738 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20739 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20741 /* Table lookup. Size 8. */
20742 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20743 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20745 #undef THUMB_VARIANT
20746 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20748 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20750 /* Neon element/structure load/store. */
20751 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20752 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20753 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20754 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20755 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20756 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20757 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20758 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20760 #undef THUMB_VARIANT
20761 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20763 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20764 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20765 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20766 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20767 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20768 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20769 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20770 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20771 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20772 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20774 #undef THUMB_VARIANT
20775 #define THUMB_VARIANT & fpu_vfp_ext_v3
20777 #define ARM_VARIANT & fpu_vfp_ext_v3
20779 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20780 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20781 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20782 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20783 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20784 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20785 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20786 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20787 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20790 #define ARM_VARIANT & fpu_vfp_ext_fma
20791 #undef THUMB_VARIANT
20792 #define THUMB_VARIANT & fpu_vfp_ext_fma
20793 /* Mnemonics shared by Neon and VFP. These are included in the
20794 VFP FMA variant; NEON and VFP FMA always includes the NEON
20795 FMA instructions. */
20796 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20797 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20798 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20799 the v form should always be used. */
20800 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20801 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20802 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20803 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20804 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20805 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20807 #undef THUMB_VARIANT
20809 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20811 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20812 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20813 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20814 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20815 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20816 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20817 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20818 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20821 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20823 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20824 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20825 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20826 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20827 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20828 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20829 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20830 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20831 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20832 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20833 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20834 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20835 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20836 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20837 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20838 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20839 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20840 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20841 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20842 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20843 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20844 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20845 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20846 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20847 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20848 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20849 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20850 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20851 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20852 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20853 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20854 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20855 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20856 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20857 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20858 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20859 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20860 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20870 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20890 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20891 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20892 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20893 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20912 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20924 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20925 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20926 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20927 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20928 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20929 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20930 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20931 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20932 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20933 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20934 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20935 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20936 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20937 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20938 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20939 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20940 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20941 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20942 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20943 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20944 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20945 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20946 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20947 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20948 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20949 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20950 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20951 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20952 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20953 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20954 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20955 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20956 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20957 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20958 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20959 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20960 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20961 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20962 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20963 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20964 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20965 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20966 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20967 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20968 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20969 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20970 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20971 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20972 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20973 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20974 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20975 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20976 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20977 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20978 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20979 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20980 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20981 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20982 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20983 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20984 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20987 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20989 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20990 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20991 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20992 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20993 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20994 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20995 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20996 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20997 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20998 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20999 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21002 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21003 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21004 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21006 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21007 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21008 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21009 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21010 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21011 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21012 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21013 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21014 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21021 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21022 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21023 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21024 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21025 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21026 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21027 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21050 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21051 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21052 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21053 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21054 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21055 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21056 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21057 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21058 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21059 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21060 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21061 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21062 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21063 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21064 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21065 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21066 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21067 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21068 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21069 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21070 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21071 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21072 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21073 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21074 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21075 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21076 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21077 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21078 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21079 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21080 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21081 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21082 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21083 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21084 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21085 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21086 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21087 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21088 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21089 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21090 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21091 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21092 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21093 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21094 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21095 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21096 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21097 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21098 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21099 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21100 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21101 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21102 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21103 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21104 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21105 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21106 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21107 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21108 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21109 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21110 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21111 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21112 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21113 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21114 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21115 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21116 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21117 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21118 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21119 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21120 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21121 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21122 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21123 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21124 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21125 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21127 /* ARMv8-M instructions. */
21129 #define ARM_VARIANT NULL
21130 #undef THUMB_VARIANT
21131 #define THUMB_VARIANT & arm_ext_v8m
21132 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21133 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21134 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21135 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21136 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21137 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21138 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21140 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21141 instructions behave as nop if no VFP is present. */
21142 #undef THUMB_VARIANT
21143 #define THUMB_VARIANT & arm_ext_v8m_main
21144 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21145 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21148 #undef THUMB_VARIANT
21174 /* MD interface: bits in the object file. */
21176 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21177 for use in the a.out file, and stores them in the array pointed to by buf.
21178 This knows about the endian-ness of the target machine and does
21179 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21180 2 (short) and 4 (long) Floating numbers are put out as a series of
21181 LITTLENUMS (shorts, here at least). */
21184 md_number_to_chars (char * buf
, valueT val
, int n
)
21186 if (target_big_endian
)
21187 number_to_chars_bigendian (buf
, val
, n
);
21189 number_to_chars_littleendian (buf
, val
, n
);
21193 md_chars_to_number (char * buf
, int n
)
21196 unsigned char * where
= (unsigned char *) buf
;
21198 if (target_big_endian
)
21203 result
|= (*where
++ & 255);
21211 result
|= (where
[n
] & 255);
21218 /* MD interface: Sections. */
21220 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21221 that an rs_machine_dependent frag may reach. */
21224 arm_frag_max_var (fragS
*fragp
)
21226 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21227 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21229 Note that we generate relaxable instructions even for cases that don't
21230 really need it, like an immediate that's a trivial constant. So we're
21231 overestimating the instruction size for some of those cases. Rather
21232 than putting more intelligence here, it would probably be better to
21233 avoid generating a relaxation frag in the first place when it can be
21234 determined up front that a short instruction will suffice. */
21236 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21240 /* Estimate the size of a frag before relaxing. Assume everything fits in
21244 md_estimate_size_before_relax (fragS
* fragp
,
21245 segT segtype ATTRIBUTE_UNUSED
)
21251 /* Convert a machine dependent frag. */
21254 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21256 unsigned long insn
;
21257 unsigned long old_op
;
21265 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21267 old_op
= bfd_get_16(abfd
, buf
);
21268 if (fragp
->fr_symbol
)
21270 exp
.X_op
= O_symbol
;
21271 exp
.X_add_symbol
= fragp
->fr_symbol
;
21275 exp
.X_op
= O_constant
;
21277 exp
.X_add_number
= fragp
->fr_offset
;
21278 opcode
= fragp
->fr_subtype
;
21281 case T_MNEM_ldr_pc
:
21282 case T_MNEM_ldr_pc2
:
21283 case T_MNEM_ldr_sp
:
21284 case T_MNEM_str_sp
:
21291 if (fragp
->fr_var
== 4)
21293 insn
= THUMB_OP32 (opcode
);
21294 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21296 insn
|= (old_op
& 0x700) << 4;
21300 insn
|= (old_op
& 7) << 12;
21301 insn
|= (old_op
& 0x38) << 13;
21303 insn
|= 0x00000c00;
21304 put_thumb32_insn (buf
, insn
);
21305 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21309 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21311 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21314 if (fragp
->fr_var
== 4)
21316 insn
= THUMB_OP32 (opcode
);
21317 insn
|= (old_op
& 0xf0) << 4;
21318 put_thumb32_insn (buf
, insn
);
21319 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21323 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21324 exp
.X_add_number
-= 4;
21332 if (fragp
->fr_var
== 4)
21334 int r0off
= (opcode
== T_MNEM_mov
21335 || opcode
== T_MNEM_movs
) ? 0 : 8;
21336 insn
= THUMB_OP32 (opcode
);
21337 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21338 insn
|= (old_op
& 0x700) << r0off
;
21339 put_thumb32_insn (buf
, insn
);
21340 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21344 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21349 if (fragp
->fr_var
== 4)
21351 insn
= THUMB_OP32(opcode
);
21352 put_thumb32_insn (buf
, insn
);
21353 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21356 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21360 if (fragp
->fr_var
== 4)
21362 insn
= THUMB_OP32(opcode
);
21363 insn
|= (old_op
& 0xf00) << 14;
21364 put_thumb32_insn (buf
, insn
);
21365 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21368 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21371 case T_MNEM_add_sp
:
21372 case T_MNEM_add_pc
:
21373 case T_MNEM_inc_sp
:
21374 case T_MNEM_dec_sp
:
21375 if (fragp
->fr_var
== 4)
21377 /* ??? Choose between add and addw. */
21378 insn
= THUMB_OP32 (opcode
);
21379 insn
|= (old_op
& 0xf0) << 4;
21380 put_thumb32_insn (buf
, insn
);
21381 if (opcode
== T_MNEM_add_pc
)
21382 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21384 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21387 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21395 if (fragp
->fr_var
== 4)
21397 insn
= THUMB_OP32 (opcode
);
21398 insn
|= (old_op
& 0xf0) << 4;
21399 insn
|= (old_op
& 0xf) << 16;
21400 put_thumb32_insn (buf
, insn
);
21401 if (insn
& (1 << 20))
21402 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21404 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21407 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21413 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21414 (enum bfd_reloc_code_real
) reloc_type
);
21415 fixp
->fx_file
= fragp
->fr_file
;
21416 fixp
->fx_line
= fragp
->fr_line
;
21417 fragp
->fr_fix
+= fragp
->fr_var
;
21419 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21420 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21421 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21422 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21425 /* Return the size of a relaxable immediate operand instruction.
21426 SHIFT and SIZE specify the form of the allowable immediate. */
21428 relax_immediate (fragS
*fragp
, int size
, int shift
)
21434 /* ??? Should be able to do better than this. */
21435 if (fragp
->fr_symbol
)
21438 low
= (1 << shift
) - 1;
21439 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21440 offset
= fragp
->fr_offset
;
21441 /* Force misaligned offsets to 32-bit variant. */
21444 if (offset
& ~mask
)
21449 /* Get the address of a symbol during relaxation. */
21451 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21457 sym
= fragp
->fr_symbol
;
21458 sym_frag
= symbol_get_frag (sym
);
21459 know (S_GET_SEGMENT (sym
) != absolute_section
21460 || sym_frag
== &zero_address_frag
);
21461 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21463 /* If frag has yet to be reached on this pass, assume it will
21464 move by STRETCH just as we did. If this is not so, it will
21465 be because some frag between grows, and that will force
21469 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21473 /* Adjust stretch for any alignment frag. Note that if have
21474 been expanding the earlier code, the symbol may be
21475 defined in what appears to be an earlier frag. FIXME:
21476 This doesn't handle the fr_subtype field, which specifies
21477 a maximum number of bytes to skip when doing an
21479 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21481 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21484 stretch
= - ((- stretch
)
21485 & ~ ((1 << (int) f
->fr_offset
) - 1));
21487 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21499 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21502 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21507 /* Assume worst case for symbols not known to be in the same section. */
21508 if (fragp
->fr_symbol
== NULL
21509 || !S_IS_DEFINED (fragp
->fr_symbol
)
21510 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21511 || S_IS_WEAK (fragp
->fr_symbol
))
21514 val
= relaxed_symbol_addr (fragp
, stretch
);
21515 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21516 addr
= (addr
+ 4) & ~3;
21517 /* Force misaligned targets to 32-bit variant. */
21521 if (val
< 0 || val
> 1020)
21526 /* Return the size of a relaxable add/sub immediate instruction. */
21528 relax_addsub (fragS
*fragp
, asection
*sec
)
21533 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21534 op
= bfd_get_16(sec
->owner
, buf
);
21535 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21536 return relax_immediate (fragp
, 8, 0);
21538 return relax_immediate (fragp
, 3, 0);
21541 /* Return TRUE iff the definition of symbol S could be pre-empted
21542 (overridden) at link or load time. */
21544 symbol_preemptible (symbolS
*s
)
21546 /* Weak symbols can always be pre-empted. */
21550 /* Non-global symbols cannot be pre-empted. */
21551 if (! S_IS_EXTERNAL (s
))
21555 /* In ELF, a global symbol can be marked protected, or private. In that
21556 case it can't be pre-empted (other definitions in the same link unit
21557 would violate the ODR). */
21558 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21562 /* Other global symbols might be pre-empted. */
21566 /* Return the size of a relaxable branch instruction. BITS is the
21567 size of the offset field in the narrow instruction. */
21570 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21576 /* Assume worst case for symbols not known to be in the same section. */
21577 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21578 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21579 || S_IS_WEAK (fragp
->fr_symbol
))
21583 /* A branch to a function in ARM state will require interworking. */
21584 if (S_IS_DEFINED (fragp
->fr_symbol
)
21585 && ARM_IS_FUNC (fragp
->fr_symbol
))
21589 if (symbol_preemptible (fragp
->fr_symbol
))
21592 val
= relaxed_symbol_addr (fragp
, stretch
);
21593 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21596 /* Offset is a signed value *2 */
21598 if (val
>= limit
|| val
< -limit
)
21604 /* Relax a machine dependent frag. This returns the amount by which
21605 the current size of the frag should change. */
21608 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21613 oldsize
= fragp
->fr_var
;
21614 switch (fragp
->fr_subtype
)
21616 case T_MNEM_ldr_pc2
:
21617 newsize
= relax_adr (fragp
, sec
, stretch
);
21619 case T_MNEM_ldr_pc
:
21620 case T_MNEM_ldr_sp
:
21621 case T_MNEM_str_sp
:
21622 newsize
= relax_immediate (fragp
, 8, 2);
21626 newsize
= relax_immediate (fragp
, 5, 2);
21630 newsize
= relax_immediate (fragp
, 5, 1);
21634 newsize
= relax_immediate (fragp
, 5, 0);
21637 newsize
= relax_adr (fragp
, sec
, stretch
);
21643 newsize
= relax_immediate (fragp
, 8, 0);
21646 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21649 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21651 case T_MNEM_add_sp
:
21652 case T_MNEM_add_pc
:
21653 newsize
= relax_immediate (fragp
, 8, 2);
21655 case T_MNEM_inc_sp
:
21656 case T_MNEM_dec_sp
:
21657 newsize
= relax_immediate (fragp
, 7, 2);
21663 newsize
= relax_addsub (fragp
, sec
);
21669 fragp
->fr_var
= newsize
;
21670 /* Freeze wide instructions that are at or before the same location as
21671 in the previous pass. This avoids infinite loops.
21672 Don't freeze them unconditionally because targets may be artificially
21673 misaligned by the expansion of preceding frags. */
21674 if (stretch
<= 0 && newsize
> 2)
21676 md_convert_frag (sec
->owner
, sec
, fragp
);
21680 return newsize
- oldsize
;
21683 /* Round up a section size to the appropriate boundary. */
21686 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21689 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21690 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21692 /* For a.out, force the section size to be aligned. If we don't do
21693 this, BFD will align it for us, but it will not write out the
21694 final bytes of the section. This may be a bug in BFD, but it is
21695 easier to fix it here since that is how the other a.out targets
21699 align
= bfd_get_section_alignment (stdoutput
, segment
);
21700 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21707 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21708 of an rs_align_code fragment. */
21711 arm_handle_align (fragS
* fragP
)
21713 static unsigned char const arm_noop
[2][2][4] =
21716 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21717 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21720 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21721 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21724 static unsigned char const thumb_noop
[2][2][2] =
21727 {0xc0, 0x46}, /* LE */
21728 {0x46, 0xc0}, /* BE */
21731 {0x00, 0xbf}, /* LE */
21732 {0xbf, 0x00} /* BE */
21735 static unsigned char const wide_thumb_noop
[2][4] =
21736 { /* Wide Thumb-2 */
21737 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21738 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21741 unsigned bytes
, fix
, noop_size
;
21743 const unsigned char * noop
;
21744 const unsigned char *narrow_noop
= NULL
;
21749 if (fragP
->fr_type
!= rs_align_code
)
21752 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21753 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21756 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21757 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21759 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21761 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21763 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21764 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21766 narrow_noop
= thumb_noop
[1][target_big_endian
];
21767 noop
= wide_thumb_noop
[target_big_endian
];
21770 noop
= thumb_noop
[0][target_big_endian
];
21778 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21779 ? selected_cpu
: arm_arch_none
,
21781 [target_big_endian
];
21788 fragP
->fr_var
= noop_size
;
21790 if (bytes
& (noop_size
- 1))
21792 fix
= bytes
& (noop_size
- 1);
21794 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21796 memset (p
, 0, fix
);
21803 if (bytes
& noop_size
)
21805 /* Insert a narrow noop. */
21806 memcpy (p
, narrow_noop
, noop_size
);
21808 bytes
-= noop_size
;
21812 /* Use wide noops for the remainder */
21816 while (bytes
>= noop_size
)
21818 memcpy (p
, noop
, noop_size
);
21820 bytes
-= noop_size
;
21824 fragP
->fr_fix
+= fix
;
21827 /* Called from md_do_align. Used to create an alignment
21828 frag in a code section. */
21831 arm_frag_align_code (int n
, int max
)
21835 /* We assume that there will never be a requirement
21836 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21837 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21842 _("alignments greater than %d bytes not supported in .text sections."),
21843 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21844 as_fatal ("%s", err_msg
);
21847 p
= frag_var (rs_align_code
,
21848 MAX_MEM_FOR_RS_ALIGN_CODE
,
21850 (relax_substateT
) max
,
21857 /* Perform target specific initialisation of a frag.
21858 Note - despite the name this initialisation is not done when the frag
21859 is created, but only when its type is assigned. A frag can be created
21860 and used a long time before its type is set, so beware of assuming that
21861 this initialisationis performed first. */
21865 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21867 /* Record whether this frag is in an ARM or a THUMB area. */
21868 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21871 #else /* OBJ_ELF is defined. */
21873 arm_init_frag (fragS
* fragP
, int max_chars
)
21875 int frag_thumb_mode
;
21877 /* If the current ARM vs THUMB mode has not already
21878 been recorded into this frag then do so now. */
21879 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21880 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21882 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21884 /* Record a mapping symbol for alignment frags. We will delete this
21885 later if the alignment ends up empty. */
21886 switch (fragP
->fr_type
)
21889 case rs_align_test
:
21891 mapping_state_2 (MAP_DATA
, max_chars
);
21893 case rs_align_code
:
21894 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21901 /* When we change sections we need to issue a new mapping symbol. */
21904 arm_elf_change_section (void)
21906 /* Link an unlinked unwind index table section to the .text section. */
21907 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21908 && elf_linked_to_section (now_seg
) == NULL
)
21909 elf_linked_to_section (now_seg
) = text_section
;
21913 arm_elf_section_type (const char * str
, size_t len
)
21915 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21916 return SHT_ARM_EXIDX
;
21921 /* Code to deal with unwinding tables. */
21923 static void add_unwind_adjustsp (offsetT
);
21925 /* Generate any deferred unwind frame offset. */
21928 flush_pending_unwind (void)
21932 offset
= unwind
.pending_offset
;
21933 unwind
.pending_offset
= 0;
21935 add_unwind_adjustsp (offset
);
21938 /* Add an opcode to this list for this function. Two-byte opcodes should
21939 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21943 add_unwind_opcode (valueT op
, int length
)
21945 /* Add any deferred stack adjustment. */
21946 if (unwind
.pending_offset
)
21947 flush_pending_unwind ();
21949 unwind
.sp_restored
= 0;
21951 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21953 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21954 if (unwind
.opcodes
)
21955 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21956 unwind
.opcode_alloc
);
21958 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21963 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21965 unwind
.opcode_count
++;
21969 /* Add unwind opcodes to adjust the stack pointer. */
21972 add_unwind_adjustsp (offsetT offset
)
21976 if (offset
> 0x200)
21978 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21983 /* Long form: 0xb2, uleb128. */
21984 /* This might not fit in a word so add the individual bytes,
21985 remembering the list is built in reverse order. */
21986 o
= (valueT
) ((offset
- 0x204) >> 2);
21988 add_unwind_opcode (0, 1);
21990 /* Calculate the uleb128 encoding of the offset. */
21994 bytes
[n
] = o
& 0x7f;
22000 /* Add the insn. */
22002 add_unwind_opcode (bytes
[n
- 1], 1);
22003 add_unwind_opcode (0xb2, 1);
22005 else if (offset
> 0x100)
22007 /* Two short opcodes. */
22008 add_unwind_opcode (0x3f, 1);
22009 op
= (offset
- 0x104) >> 2;
22010 add_unwind_opcode (op
, 1);
22012 else if (offset
> 0)
22014 /* Short opcode. */
22015 op
= (offset
- 4) >> 2;
22016 add_unwind_opcode (op
, 1);
22018 else if (offset
< 0)
22021 while (offset
> 0x100)
22023 add_unwind_opcode (0x7f, 1);
22026 op
= ((offset
- 4) >> 2) | 0x40;
22027 add_unwind_opcode (op
, 1);
22031 /* Finish the list of unwind opcodes for this function. */
22033 finish_unwind_opcodes (void)
22037 if (unwind
.fp_used
)
22039 /* Adjust sp as necessary. */
22040 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22041 flush_pending_unwind ();
22043 /* After restoring sp from the frame pointer. */
22044 op
= 0x90 | unwind
.fp_reg
;
22045 add_unwind_opcode (op
, 1);
22048 flush_pending_unwind ();
22052 /* Start an exception table entry. If idx is nonzero this is an index table
22056 start_unwind_section (const segT text_seg
, int idx
)
22058 const char * text_name
;
22059 const char * prefix
;
22060 const char * prefix_once
;
22061 const char * group_name
;
22069 prefix
= ELF_STRING_ARM_unwind
;
22070 prefix_once
= ELF_STRING_ARM_unwind_once
;
22071 type
= SHT_ARM_EXIDX
;
22075 prefix
= ELF_STRING_ARM_unwind_info
;
22076 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22077 type
= SHT_PROGBITS
;
22080 text_name
= segment_name (text_seg
);
22081 if (streq (text_name
, ".text"))
22084 if (strncmp (text_name
, ".gnu.linkonce.t.",
22085 strlen (".gnu.linkonce.t.")) == 0)
22087 prefix
= prefix_once
;
22088 text_name
+= strlen (".gnu.linkonce.t.");
22091 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22097 /* Handle COMDAT group. */
22098 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22100 group_name
= elf_group_name (text_seg
);
22101 if (group_name
== NULL
)
22103 as_bad (_("Group section `%s' has no group signature"),
22104 segment_name (text_seg
));
22105 ignore_rest_of_line ();
22108 flags
|= SHF_GROUP
;
22112 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
22114 /* Set the section link for index tables. */
22116 elf_linked_to_section (now_seg
) = text_seg
;
22120 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22121 personality routine data. Returns zero, or the index table value for
22122 an inline entry. */
22125 create_unwind_entry (int have_data
)
22130 /* The current word of data. */
22132 /* The number of bytes left in this word. */
22135 finish_unwind_opcodes ();
22137 /* Remember the current text section. */
22138 unwind
.saved_seg
= now_seg
;
22139 unwind
.saved_subseg
= now_subseg
;
22141 start_unwind_section (now_seg
, 0);
22143 if (unwind
.personality_routine
== NULL
)
22145 if (unwind
.personality_index
== -2)
22148 as_bad (_("handlerdata in cantunwind frame"));
22149 return 1; /* EXIDX_CANTUNWIND. */
22152 /* Use a default personality routine if none is specified. */
22153 if (unwind
.personality_index
== -1)
22155 if (unwind
.opcode_count
> 3)
22156 unwind
.personality_index
= 1;
22158 unwind
.personality_index
= 0;
22161 /* Space for the personality routine entry. */
22162 if (unwind
.personality_index
== 0)
22164 if (unwind
.opcode_count
> 3)
22165 as_bad (_("too many unwind opcodes for personality routine 0"));
22169 /* All the data is inline in the index table. */
22172 while (unwind
.opcode_count
> 0)
22174 unwind
.opcode_count
--;
22175 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22179 /* Pad with "finish" opcodes. */
22181 data
= (data
<< 8) | 0xb0;
22188 /* We get two opcodes "free" in the first word. */
22189 size
= unwind
.opcode_count
- 2;
22193 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22194 if (unwind
.personality_index
!= -1)
22196 as_bad (_("attempt to recreate an unwind entry"));
22200 /* An extra byte is required for the opcode count. */
22201 size
= unwind
.opcode_count
+ 1;
22204 size
= (size
+ 3) >> 2;
22206 as_bad (_("too many unwind opcodes"));
22208 frag_align (2, 0, 0);
22209 record_alignment (now_seg
, 2);
22210 unwind
.table_entry
= expr_build_dot ();
22212 /* Allocate the table entry. */
22213 ptr
= frag_more ((size
<< 2) + 4);
22214 /* PR 13449: Zero the table entries in case some of them are not used. */
22215 memset (ptr
, 0, (size
<< 2) + 4);
22216 where
= frag_now_fix () - ((size
<< 2) + 4);
22218 switch (unwind
.personality_index
)
22221 /* ??? Should this be a PLT generating relocation? */
22222 /* Custom personality routine. */
22223 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22224 BFD_RELOC_ARM_PREL31
);
22229 /* Set the first byte to the number of additional words. */
22230 data
= size
> 0 ? size
- 1 : 0;
22234 /* ABI defined personality routines. */
22236 /* Three opcodes bytes are packed into the first word. */
22243 /* The size and first two opcode bytes go in the first word. */
22244 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22249 /* Should never happen. */
22253 /* Pack the opcodes into words (MSB first), reversing the list at the same
22255 while (unwind
.opcode_count
> 0)
22259 md_number_to_chars (ptr
, data
, 4);
22264 unwind
.opcode_count
--;
22266 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22269 /* Finish off the last word. */
22272 /* Pad with "finish" opcodes. */
22274 data
= (data
<< 8) | 0xb0;
22276 md_number_to_chars (ptr
, data
, 4);
22281 /* Add an empty descriptor if there is no user-specified data. */
22282 ptr
= frag_more (4);
22283 md_number_to_chars (ptr
, 0, 4);
22290 /* Initialize the DWARF-2 unwind information for this procedure. */
22293 tc_arm_frame_initial_instructions (void)
22295 cfi_add_CFA_def_cfa (REG_SP
, 0);
22297 #endif /* OBJ_ELF */
22299 /* Convert REGNAME to a DWARF-2 register number. */
22302 tc_arm_regname_to_dw2regnum (char *regname
)
22304 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22308 /* PR 16694: Allow VFP registers as well. */
22309 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22313 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22322 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22326 exp
.X_op
= O_secrel
;
22327 exp
.X_add_symbol
= symbol
;
22328 exp
.X_add_number
= 0;
22329 emit_expr (&exp
, size
);
22333 /* MD interface: Symbol and relocation handling. */
22335 /* Return the address within the segment that a PC-relative fixup is
22336 relative to. For ARM, PC-relative fixups applied to instructions
22337 are generally relative to the location of the fixup plus 8 bytes.
22338 Thumb branches are offset by 4, and Thumb loads relative to PC
22339 require special handling. */
22342 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22344 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22346 /* If this is pc-relative and we are going to emit a relocation
22347 then we just want to put out any pipeline compensation that the linker
22348 will need. Otherwise we want to use the calculated base.
22349 For WinCE we skip the bias for externals as well, since this
22350 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22352 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22353 || (arm_force_relocation (fixP
)
22355 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22361 switch (fixP
->fx_r_type
)
22363 /* PC relative addressing on the Thumb is slightly odd as the
22364 bottom two bits of the PC are forced to zero for the
22365 calculation. This happens *after* application of the
22366 pipeline offset. However, Thumb adrl already adjusts for
22367 this, so we need not do it again. */
22368 case BFD_RELOC_ARM_THUMB_ADD
:
22371 case BFD_RELOC_ARM_THUMB_OFFSET
:
22372 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22373 case BFD_RELOC_ARM_T32_ADD_PC12
:
22374 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22375 return (base
+ 4) & ~3;
22377 /* Thumb branches are simply offset by +4. */
22378 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22379 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22380 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22381 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22382 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22385 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22387 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22388 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22389 && ARM_IS_FUNC (fixP
->fx_addsy
)
22390 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22391 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22394 /* BLX is like branches above, but forces the low two bits of PC to
22396 case BFD_RELOC_THUMB_PCREL_BLX
:
22398 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22399 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22400 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22401 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22402 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22403 return (base
+ 4) & ~3;
22405 /* ARM mode branches are offset by +8. However, the Windows CE
22406 loader expects the relocation not to take this into account. */
22407 case BFD_RELOC_ARM_PCREL_BLX
:
22409 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22410 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22411 && ARM_IS_FUNC (fixP
->fx_addsy
)
22412 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22413 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22416 case BFD_RELOC_ARM_PCREL_CALL
:
22418 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22419 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22420 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22421 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22422 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22425 case BFD_RELOC_ARM_PCREL_BRANCH
:
22426 case BFD_RELOC_ARM_PCREL_JUMP
:
22427 case BFD_RELOC_ARM_PLT32
:
22429 /* When handling fixups immediately, because we have already
22430 discovered the value of a symbol, or the address of the frag involved
22431 we must account for the offset by +8, as the OS loader will never see the reloc.
22432 see fixup_segment() in write.c
22433 The S_IS_EXTERNAL test handles the case of global symbols.
22434 Those need the calculated base, not just the pipe compensation the linker will need. */
22436 && fixP
->fx_addsy
!= NULL
22437 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22438 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22446 /* ARM mode loads relative to PC are also offset by +8. Unlike
22447 branches, the Windows CE loader *does* expect the relocation
22448 to take this into account. */
22449 case BFD_RELOC_ARM_OFFSET_IMM
:
22450 case BFD_RELOC_ARM_OFFSET_IMM8
:
22451 case BFD_RELOC_ARM_HWLITERAL
:
22452 case BFD_RELOC_ARM_LITERAL
:
22453 case BFD_RELOC_ARM_CP_OFF_IMM
:
22457 /* Other PC-relative relocations are un-offset. */
22463 static bfd_boolean flag_warn_syms
= TRUE
;
22466 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22468 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22469 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22470 does mean that the resulting code might be very confusing to the reader.
22471 Also this warning can be triggered if the user omits an operand before
22472 an immediate address, eg:
22476 GAS treats this as an assignment of the value of the symbol foo to a
22477 symbol LDR, and so (without this code) it will not issue any kind of
22478 warning or error message.
22480 Note - ARM instructions are case-insensitive but the strings in the hash
22481 table are all stored in lower case, so we must first ensure that name is
22483 if (flag_warn_syms
&& arm_ops_hsh
)
22485 char * nbuf
= strdup (name
);
22488 for (p
= nbuf
; *p
; p
++)
22490 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22492 static struct hash_control
* already_warned
= NULL
;
22494 if (already_warned
== NULL
)
22495 already_warned
= hash_new ();
22496 /* Only warn about the symbol once. To keep the code
22497 simple we let hash_insert do the lookup for us. */
22498 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22499 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22508 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22509 Otherwise we have no need to default values of symbols. */
22512 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22515 if (name
[0] == '_' && name
[1] == 'G'
22516 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22520 if (symbol_find (name
))
22521 as_bad (_("GOT already in the symbol table"));
22523 GOT_symbol
= symbol_new (name
, undefined_section
,
22524 (valueT
) 0, & zero_address_frag
);
22534 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22535 computed as two separate immediate values, added together. We
22536 already know that this value cannot be computed by just one ARM
22539 static unsigned int
22540 validate_immediate_twopart (unsigned int val
,
22541 unsigned int * highpart
)
22546 for (i
= 0; i
< 32; i
+= 2)
22547 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22553 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22555 else if (a
& 0xff0000)
22557 if (a
& 0xff000000)
22559 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22563 gas_assert (a
& 0xff000000);
22564 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22567 return (a
& 0xff) | (i
<< 7);
22574 validate_offset_imm (unsigned int val
, int hwse
)
22576 if ((hwse
&& val
> 255) || val
> 4095)
22581 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22582 negative immediate constant by altering the instruction. A bit of
22587 by inverting the second operand, and
22590 by negating the second operand. */
22593 negate_data_op (unsigned long * instruction
,
22594 unsigned long value
)
22597 unsigned long negated
, inverted
;
22599 negated
= encode_arm_immediate (-value
);
22600 inverted
= encode_arm_immediate (~value
);
22602 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22605 /* First negates. */
22606 case OPCODE_SUB
: /* ADD <-> SUB */
22607 new_inst
= OPCODE_ADD
;
22612 new_inst
= OPCODE_SUB
;
22616 case OPCODE_CMP
: /* CMP <-> CMN */
22617 new_inst
= OPCODE_CMN
;
22622 new_inst
= OPCODE_CMP
;
22626 /* Now Inverted ops. */
22627 case OPCODE_MOV
: /* MOV <-> MVN */
22628 new_inst
= OPCODE_MVN
;
22633 new_inst
= OPCODE_MOV
;
22637 case OPCODE_AND
: /* AND <-> BIC */
22638 new_inst
= OPCODE_BIC
;
22643 new_inst
= OPCODE_AND
;
22647 case OPCODE_ADC
: /* ADC <-> SBC */
22648 new_inst
= OPCODE_SBC
;
22653 new_inst
= OPCODE_ADC
;
22657 /* We cannot do anything. */
22662 if (value
== (unsigned) FAIL
)
22665 *instruction
&= OPCODE_MASK
;
22666 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22670 /* Like negate_data_op, but for Thumb-2. */
22672 static unsigned int
22673 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22677 unsigned int negated
, inverted
;
22679 negated
= encode_thumb32_immediate (-value
);
22680 inverted
= encode_thumb32_immediate (~value
);
22682 rd
= (*instruction
>> 8) & 0xf;
22683 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22686 /* ADD <-> SUB. Includes CMP <-> CMN. */
22687 case T2_OPCODE_SUB
:
22688 new_inst
= T2_OPCODE_ADD
;
22692 case T2_OPCODE_ADD
:
22693 new_inst
= T2_OPCODE_SUB
;
22697 /* ORR <-> ORN. Includes MOV <-> MVN. */
22698 case T2_OPCODE_ORR
:
22699 new_inst
= T2_OPCODE_ORN
;
22703 case T2_OPCODE_ORN
:
22704 new_inst
= T2_OPCODE_ORR
;
22708 /* AND <-> BIC. TST has no inverted equivalent. */
22709 case T2_OPCODE_AND
:
22710 new_inst
= T2_OPCODE_BIC
;
22717 case T2_OPCODE_BIC
:
22718 new_inst
= T2_OPCODE_AND
;
22723 case T2_OPCODE_ADC
:
22724 new_inst
= T2_OPCODE_SBC
;
22728 case T2_OPCODE_SBC
:
22729 new_inst
= T2_OPCODE_ADC
;
22733 /* We cannot do anything. */
22738 if (value
== (unsigned int)FAIL
)
22741 *instruction
&= T2_OPCODE_MASK
;
22742 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22746 /* Read a 32-bit thumb instruction from buf. */
22747 static unsigned long
22748 get_thumb32_insn (char * buf
)
22750 unsigned long insn
;
22751 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22752 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22758 /* We usually want to set the low bit on the address of thumb function
22759 symbols. In particular .word foo - . should have the low bit set.
22760 Generic code tries to fold the difference of two symbols to
22761 a constant. Prevent this and force a relocation when the first symbols
22762 is a thumb function. */
22765 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22767 if (op
== O_subtract
22768 && l
->X_op
== O_symbol
22769 && r
->X_op
== O_symbol
22770 && THUMB_IS_FUNC (l
->X_add_symbol
))
22772 l
->X_op
= O_subtract
;
22773 l
->X_op_symbol
= r
->X_add_symbol
;
22774 l
->X_add_number
-= r
->X_add_number
;
22778 /* Process as normal. */
22782 /* Encode Thumb2 unconditional branches and calls. The encoding
22783 for the 2 are identical for the immediate values. */
22786 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22788 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22791 addressT S
, I1
, I2
, lo
, hi
;
22793 S
= (value
>> 24) & 0x01;
22794 I1
= (value
>> 23) & 0x01;
22795 I2
= (value
>> 22) & 0x01;
22796 hi
= (value
>> 12) & 0x3ff;
22797 lo
= (value
>> 1) & 0x7ff;
22798 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22799 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22800 newval
|= (S
<< 10) | hi
;
22801 newval2
&= ~T2I1I2MASK
;
22802 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22803 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22804 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22808 md_apply_fix (fixS
* fixP
,
22812 offsetT value
= * valP
;
22814 unsigned int newimm
;
22815 unsigned long temp
;
22817 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22819 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22821 /* Note whether this will delete the relocation. */
22823 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22826 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22827 consistency with the behaviour on 32-bit hosts. Remember value
22829 value
&= 0xffffffff;
22830 value
^= 0x80000000;
22831 value
-= 0x80000000;
22834 fixP
->fx_addnumber
= value
;
22836 /* Same treatment for fixP->fx_offset. */
22837 fixP
->fx_offset
&= 0xffffffff;
22838 fixP
->fx_offset
^= 0x80000000;
22839 fixP
->fx_offset
-= 0x80000000;
22841 switch (fixP
->fx_r_type
)
22843 case BFD_RELOC_NONE
:
22844 /* This will need to go in the object file. */
22848 case BFD_RELOC_ARM_IMMEDIATE
:
22849 /* We claim that this fixup has been processed here,
22850 even if in fact we generate an error because we do
22851 not have a reloc for it, so tc_gen_reloc will reject it. */
22854 if (fixP
->fx_addsy
)
22856 const char *msg
= 0;
22858 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22859 msg
= _("undefined symbol %s used as an immediate value");
22860 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22861 msg
= _("symbol %s is in a different section");
22862 else if (S_IS_WEAK (fixP
->fx_addsy
))
22863 msg
= _("symbol %s is weak and may be overridden later");
22867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22868 msg
, S_GET_NAME (fixP
->fx_addsy
));
22873 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22875 /* If the offset is negative, we should use encoding A2 for ADR. */
22876 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22877 newimm
= negate_data_op (&temp
, value
);
22880 newimm
= encode_arm_immediate (value
);
22882 /* If the instruction will fail, see if we can fix things up by
22883 changing the opcode. */
22884 if (newimm
== (unsigned int) FAIL
)
22885 newimm
= negate_data_op (&temp
, value
);
22886 /* MOV accepts both ARM modified immediate (A1 encoding) and
22887 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22888 When disassembling, MOV is preferred when there is no encoding
22890 if (newimm
== (unsigned int) FAIL
22891 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22892 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22893 && !((temp
>> SBIT_SHIFT
) & 0x1)
22894 && value
>= 0 && value
<= 0xffff)
22896 /* Clear bits[23:20] to change encoding from A1 to A2. */
22897 temp
&= 0xff0fffff;
22898 /* Encoding high 4bits imm. Code below will encode the remaining
22900 temp
|= (value
& 0x0000f000) << 4;
22901 newimm
= value
& 0x00000fff;
22905 if (newimm
== (unsigned int) FAIL
)
22907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22908 _("invalid constant (%lx) after fixup"),
22909 (unsigned long) value
);
22913 newimm
|= (temp
& 0xfffff000);
22914 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22917 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22919 unsigned int highpart
= 0;
22920 unsigned int newinsn
= 0xe1a00000; /* nop. */
22922 if (fixP
->fx_addsy
)
22924 const char *msg
= 0;
22926 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22927 msg
= _("undefined symbol %s used as an immediate value");
22928 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22929 msg
= _("symbol %s is in a different section");
22930 else if (S_IS_WEAK (fixP
->fx_addsy
))
22931 msg
= _("symbol %s is weak and may be overridden later");
22935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22936 msg
, S_GET_NAME (fixP
->fx_addsy
));
22941 newimm
= encode_arm_immediate (value
);
22942 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22944 /* If the instruction will fail, see if we can fix things up by
22945 changing the opcode. */
22946 if (newimm
== (unsigned int) FAIL
22947 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22949 /* No ? OK - try using two ADD instructions to generate
22951 newimm
= validate_immediate_twopart (value
, & highpart
);
22953 /* Yes - then make sure that the second instruction is
22955 if (newimm
!= (unsigned int) FAIL
)
22957 /* Still No ? Try using a negated value. */
22958 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22959 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22960 /* Otherwise - give up. */
22963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22964 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22969 /* Replace the first operand in the 2nd instruction (which
22970 is the PC) with the destination register. We have
22971 already added in the PC in the first instruction and we
22972 do not want to do it again. */
22973 newinsn
&= ~ 0xf0000;
22974 newinsn
|= ((newinsn
& 0x0f000) << 4);
22977 newimm
|= (temp
& 0xfffff000);
22978 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22980 highpart
|= (newinsn
& 0xfffff000);
22981 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22985 case BFD_RELOC_ARM_OFFSET_IMM
:
22986 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22988 /* Fall through. */
22990 case BFD_RELOC_ARM_LITERAL
:
22996 if (validate_offset_imm (value
, 0) == FAIL
)
22998 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23000 _("invalid literal constant: pool needs to be closer"));
23002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23003 _("bad immediate value for offset (%ld)"),
23008 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23010 newval
&= 0xfffff000;
23013 newval
&= 0xff7ff000;
23014 newval
|= value
| (sign
? INDEX_UP
: 0);
23016 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23019 case BFD_RELOC_ARM_OFFSET_IMM8
:
23020 case BFD_RELOC_ARM_HWLITERAL
:
23026 if (validate_offset_imm (value
, 1) == FAIL
)
23028 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23029 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23030 _("invalid literal constant: pool needs to be closer"));
23032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23033 _("bad immediate value for 8-bit offset (%ld)"),
23038 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23040 newval
&= 0xfffff0f0;
23043 newval
&= 0xff7ff0f0;
23044 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23046 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23049 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23050 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23052 _("bad immediate value for offset (%ld)"), (long) value
);
23055 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23057 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23060 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23061 /* This is a complicated relocation used for all varieties of Thumb32
23062 load/store instruction with immediate offset:
23064 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23065 *4, optional writeback(W)
23066 (doubleword load/store)
23068 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23069 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23070 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23071 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23072 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23074 Uppercase letters indicate bits that are already encoded at
23075 this point. Lowercase letters are our problem. For the
23076 second block of instructions, the secondary opcode nybble
23077 (bits 8..11) is present, and bit 23 is zero, even if this is
23078 a PC-relative operation. */
23079 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23081 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23083 if ((newval
& 0xf0000000) == 0xe0000000)
23085 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23087 newval
|= (1 << 23);
23090 if (value
% 4 != 0)
23092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23093 _("offset not a multiple of 4"));
23099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23100 _("offset out of range"));
23105 else if ((newval
& 0x000f0000) == 0x000f0000)
23107 /* PC-relative, 12-bit offset. */
23109 newval
|= (1 << 23);
23114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23115 _("offset out of range"));
23120 else if ((newval
& 0x00000100) == 0x00000100)
23122 /* Writeback: 8-bit, +/- offset. */
23124 newval
|= (1 << 9);
23129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23130 _("offset out of range"));
23135 else if ((newval
& 0x00000f00) == 0x00000e00)
23137 /* T-instruction: positive 8-bit offset. */
23138 if (value
< 0 || value
> 0xff)
23140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23141 _("offset out of range"));
23149 /* Positive 12-bit or negative 8-bit offset. */
23153 newval
|= (1 << 23);
23163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23164 _("offset out of range"));
23171 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23172 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23175 case BFD_RELOC_ARM_SHIFT_IMM
:
23176 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23177 if (((unsigned long) value
) > 32
23179 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23182 _("shift expression is too large"));
23187 /* Shifts of zero must be done as lsl. */
23189 else if (value
== 32)
23191 newval
&= 0xfffff07f;
23192 newval
|= (value
& 0x1f) << 7;
23193 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23196 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23197 case BFD_RELOC_ARM_T32_ADD_IMM
:
23198 case BFD_RELOC_ARM_T32_IMM12
:
23199 case BFD_RELOC_ARM_T32_ADD_PC12
:
23200 /* We claim that this fixup has been processed here,
23201 even if in fact we generate an error because we do
23202 not have a reloc for it, so tc_gen_reloc will reject it. */
23206 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23209 _("undefined symbol %s used as an immediate value"),
23210 S_GET_NAME (fixP
->fx_addsy
));
23214 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23216 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23219 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23220 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23221 Thumb2 modified immediate encoding (T2). */
23222 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23223 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23225 newimm
= encode_thumb32_immediate (value
);
23226 if (newimm
== (unsigned int) FAIL
)
23227 newimm
= thumb32_negate_data_op (&newval
, value
);
23229 if (newimm
== (unsigned int) FAIL
)
23231 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23233 /* Turn add/sum into addw/subw. */
23234 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23235 newval
= (newval
& 0xfeffffff) | 0x02000000;
23236 /* No flat 12-bit imm encoding for addsw/subsw. */
23237 if ((newval
& 0x00100000) == 0)
23239 /* 12 bit immediate for addw/subw. */
23243 newval
^= 0x00a00000;
23246 newimm
= (unsigned int) FAIL
;
23253 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23254 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23255 disassembling, MOV is preferred when there is no encoding
23257 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23258 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23259 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23260 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23261 && value
>= 0 && value
<=0xffff)
23263 /* Toggle bit[25] to change encoding from T2 to T3. */
23265 /* Clear bits[19:16]. */
23266 newval
&= 0xfff0ffff;
23267 /* Encoding high 4bits imm. Code below will encode the
23268 remaining low 12bits. */
23269 newval
|= (value
& 0x0000f000) << 4;
23270 newimm
= value
& 0x00000fff;
23275 if (newimm
== (unsigned int)FAIL
)
23277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23278 _("invalid constant (%lx) after fixup"),
23279 (unsigned long) value
);
23283 newval
|= (newimm
& 0x800) << 15;
23284 newval
|= (newimm
& 0x700) << 4;
23285 newval
|= (newimm
& 0x0ff);
23287 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23288 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23291 case BFD_RELOC_ARM_SMC
:
23292 if (((unsigned long) value
) > 0xffff)
23293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23294 _("invalid smc expression"));
23295 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23296 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23297 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23300 case BFD_RELOC_ARM_HVC
:
23301 if (((unsigned long) value
) > 0xffff)
23302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23303 _("invalid hvc expression"));
23304 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23305 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23306 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23309 case BFD_RELOC_ARM_SWI
:
23310 if (fixP
->tc_fix_data
!= 0)
23312 if (((unsigned long) value
) > 0xff)
23313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23314 _("invalid swi expression"));
23315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23317 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23321 if (((unsigned long) value
) > 0x00ffffff)
23322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23323 _("invalid swi expression"));
23324 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23326 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23330 case BFD_RELOC_ARM_MULTI
:
23331 if (((unsigned long) value
) > 0xffff)
23332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23333 _("invalid expression in load/store multiple"));
23334 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23335 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23339 case BFD_RELOC_ARM_PCREL_CALL
:
23341 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23343 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23344 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23345 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23346 /* Flip the bl to blx. This is a simple flip
23347 bit here because we generate PCREL_CALL for
23348 unconditional bls. */
23350 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23351 newval
= newval
| 0x10000000;
23352 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23358 goto arm_branch_common
;
23360 case BFD_RELOC_ARM_PCREL_JUMP
:
23361 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23363 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23364 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23365 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23367 /* This would map to a bl<cond>, b<cond>,
23368 b<always> to a Thumb function. We
23369 need to force a relocation for this particular
23371 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23374 /* Fall through. */
23376 case BFD_RELOC_ARM_PLT32
:
23378 case BFD_RELOC_ARM_PCREL_BRANCH
:
23380 goto arm_branch_common
;
23382 case BFD_RELOC_ARM_PCREL_BLX
:
23385 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23387 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23388 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23389 && ARM_IS_FUNC (fixP
->fx_addsy
))
23391 /* Flip the blx to a bl and warn. */
23392 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23393 newval
= 0xeb000000;
23394 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23395 _("blx to '%s' an ARM ISA state function changed to bl"),
23397 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23403 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23404 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23408 /* We are going to store value (shifted right by two) in the
23409 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23410 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23411 also be be clear. */
23413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23414 _("misaligned branch destination"));
23415 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23416 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23419 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23421 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23422 newval
|= (value
>> 2) & 0x00ffffff;
23423 /* Set the H bit on BLX instructions. */
23427 newval
|= 0x01000000;
23429 newval
&= ~0x01000000;
23431 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23435 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23436 /* CBZ can only branch forward. */
23438 /* Attempts to use CBZ to branch to the next instruction
23439 (which, strictly speaking, are prohibited) will be turned into
23442 FIXME: It may be better to remove the instruction completely and
23443 perform relaxation. */
23446 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23447 newval
= 0xbf00; /* NOP encoding T1 */
23448 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23455 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23458 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23459 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23464 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23465 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23468 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23470 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23471 newval
|= (value
& 0x1ff) >> 1;
23472 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23476 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23477 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23480 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23482 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23483 newval
|= (value
& 0xfff) >> 1;
23484 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23488 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23490 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23491 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23492 && ARM_IS_FUNC (fixP
->fx_addsy
)
23493 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23495 /* Force a relocation for a branch 20 bits wide. */
23498 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23500 _("conditional branch out of range"));
23502 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23505 addressT S
, J1
, J2
, lo
, hi
;
23507 S
= (value
& 0x00100000) >> 20;
23508 J2
= (value
& 0x00080000) >> 19;
23509 J1
= (value
& 0x00040000) >> 18;
23510 hi
= (value
& 0x0003f000) >> 12;
23511 lo
= (value
& 0x00000ffe) >> 1;
23513 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23514 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23515 newval
|= (S
<< 10) | hi
;
23516 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23517 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23518 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23522 case BFD_RELOC_THUMB_PCREL_BLX
:
23523 /* If there is a blx from a thumb state function to
23524 another thumb function flip this to a bl and warn
23528 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23529 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23530 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23532 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23533 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23536 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23537 newval
= newval
| 0x1000;
23538 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23539 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23544 goto thumb_bl_common
;
23546 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23547 /* A bl from Thumb state ISA to an internal ARM state function
23548 is converted to a blx. */
23550 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23551 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23552 && ARM_IS_FUNC (fixP
->fx_addsy
)
23553 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23555 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23556 newval
= newval
& ~0x1000;
23557 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23558 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23564 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23565 /* For a BLX instruction, make sure that the relocation is rounded up
23566 to a word boundary. This follows the semantics of the instruction
23567 which specifies that bit 1 of the target address will come from bit
23568 1 of the base address. */
23569 value
= (value
+ 3) & ~ 3;
23572 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23573 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23574 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23577 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23579 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23581 else if ((value
& ~0x1ffffff)
23582 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23583 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23584 _("Thumb2 branch out of range"));
23587 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23588 encode_thumb2_b_bl_offset (buf
, value
);
23592 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23593 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23596 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23597 encode_thumb2_b_bl_offset (buf
, value
);
23602 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23608 md_number_to_chars (buf
, value
, 2);
23612 case BFD_RELOC_ARM_TLS_CALL
:
23613 case BFD_RELOC_ARM_THM_TLS_CALL
:
23614 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23615 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23616 case BFD_RELOC_ARM_TLS_GOTDESC
:
23617 case BFD_RELOC_ARM_TLS_GD32
:
23618 case BFD_RELOC_ARM_TLS_LE32
:
23619 case BFD_RELOC_ARM_TLS_IE32
:
23620 case BFD_RELOC_ARM_TLS_LDM32
:
23621 case BFD_RELOC_ARM_TLS_LDO32
:
23622 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23625 case BFD_RELOC_ARM_GOT32
:
23626 case BFD_RELOC_ARM_GOTOFF
:
23629 case BFD_RELOC_ARM_GOT_PREL
:
23630 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23631 md_number_to_chars (buf
, value
, 4);
23634 case BFD_RELOC_ARM_TARGET2
:
23635 /* TARGET2 is not partial-inplace, so we need to write the
23636 addend here for REL targets, because it won't be written out
23637 during reloc processing later. */
23638 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23639 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23643 case BFD_RELOC_RVA
:
23645 case BFD_RELOC_ARM_TARGET1
:
23646 case BFD_RELOC_ARM_ROSEGREL32
:
23647 case BFD_RELOC_ARM_SBREL32
:
23648 case BFD_RELOC_32_PCREL
:
23650 case BFD_RELOC_32_SECREL
:
23652 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23654 /* For WinCE we only do this for pcrel fixups. */
23655 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23657 md_number_to_chars (buf
, value
, 4);
23661 case BFD_RELOC_ARM_PREL31
:
23662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23664 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23665 if ((value
^ (value
>> 1)) & 0x40000000)
23667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23668 _("rel31 relocation overflow"));
23670 newval
|= value
& 0x7fffffff;
23671 md_number_to_chars (buf
, newval
, 4);
23676 case BFD_RELOC_ARM_CP_OFF_IMM
:
23677 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23678 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23679 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23681 newval
= get_thumb32_insn (buf
);
23682 if ((newval
& 0x0f200f00) == 0x0d000900)
23684 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23685 has permitted values that are multiples of 2, in the range 0
23687 if (value
< -510 || value
> 510 || (value
& 1))
23688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23689 _("co-processor offset out of range"));
23691 else if (value
< -1023 || value
> 1023 || (value
& 3))
23692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23693 _("co-processor offset out of range"));
23698 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23699 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23700 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23702 newval
= get_thumb32_insn (buf
);
23704 newval
&= 0xffffff00;
23707 newval
&= 0xff7fff00;
23708 if ((newval
& 0x0f200f00) == 0x0d000900)
23710 /* This is a fp16 vstr/vldr.
23712 It requires the immediate offset in the instruction is shifted
23713 left by 1 to be a half-word offset.
23715 Here, left shift by 1 first, and later right shift by 2
23716 should get the right offset. */
23719 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23721 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23722 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23723 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23725 put_thumb32_insn (buf
, newval
);
23728 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23729 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23730 if (value
< -255 || value
> 255)
23731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23732 _("co-processor offset out of range"));
23734 goto cp_off_common
;
23736 case BFD_RELOC_ARM_THUMB_OFFSET
:
23737 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23738 /* Exactly what ranges, and where the offset is inserted depends
23739 on the type of instruction, we can establish this from the
23741 switch (newval
>> 12)
23743 case 4: /* PC load. */
23744 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23745 forced to zero for these loads; md_pcrel_from has already
23746 compensated for this. */
23748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23749 _("invalid offset, target not word aligned (0x%08lX)"),
23750 (((unsigned long) fixP
->fx_frag
->fr_address
23751 + (unsigned long) fixP
->fx_where
) & ~3)
23752 + (unsigned long) value
);
23754 if (value
& ~0x3fc)
23755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23756 _("invalid offset, value too big (0x%08lX)"),
23759 newval
|= value
>> 2;
23762 case 9: /* SP load/store. */
23763 if (value
& ~0x3fc)
23764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23765 _("invalid offset, value too big (0x%08lX)"),
23767 newval
|= value
>> 2;
23770 case 6: /* Word load/store. */
23772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23773 _("invalid offset, value too big (0x%08lX)"),
23775 newval
|= value
<< 4; /* 6 - 2. */
23778 case 7: /* Byte load/store. */
23780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23781 _("invalid offset, value too big (0x%08lX)"),
23783 newval
|= value
<< 6;
23786 case 8: /* Halfword load/store. */
23788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23789 _("invalid offset, value too big (0x%08lX)"),
23791 newval
|= value
<< 5; /* 6 - 1. */
23795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23796 "Unable to process relocation for thumb opcode: %lx",
23797 (unsigned long) newval
);
23800 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23803 case BFD_RELOC_ARM_THUMB_ADD
:
23804 /* This is a complicated relocation, since we use it for all of
23805 the following immediate relocations:
23809 9bit ADD/SUB SP word-aligned
23810 10bit ADD PC/SP word-aligned
23812 The type of instruction being processed is encoded in the
23819 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23821 int rd
= (newval
>> 4) & 0xf;
23822 int rs
= newval
& 0xf;
23823 int subtract
= !!(newval
& 0x8000);
23825 /* Check for HI regs, only very restricted cases allowed:
23826 Adjusting SP, and using PC or SP to get an address. */
23827 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23828 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23830 _("invalid Hi register with immediate"));
23832 /* If value is negative, choose the opposite instruction. */
23836 subtract
= !subtract
;
23838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23839 _("immediate value out of range"));
23844 if (value
& ~0x1fc)
23845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23846 _("invalid immediate for stack address calculation"));
23847 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23848 newval
|= value
>> 2;
23850 else if (rs
== REG_PC
|| rs
== REG_SP
)
23852 /* PR gas/18541. If the addition is for a defined symbol
23853 within range of an ADR instruction then accept it. */
23856 && fixP
->fx_addsy
!= NULL
)
23860 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23861 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23862 || S_IS_WEAK (fixP
->fx_addsy
))
23864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23865 _("address calculation needs a strongly defined nearby symbol"));
23869 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23871 /* Round up to the next 4-byte boundary. */
23876 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23881 _("symbol too far away"));
23891 if (subtract
|| value
& ~0x3fc)
23892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23893 _("invalid immediate for address calculation (value = 0x%08lX)"),
23894 (unsigned long) (subtract
? - value
: value
));
23895 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23897 newval
|= value
>> 2;
23902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23903 _("immediate value out of range"));
23904 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23905 newval
|= (rd
<< 8) | value
;
23910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23911 _("immediate value out of range"));
23912 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23913 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23916 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23919 case BFD_RELOC_ARM_THUMB_IMM
:
23920 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23921 if (value
< 0 || value
> 255)
23922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23923 _("invalid immediate: %ld is out of range"),
23926 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23929 case BFD_RELOC_ARM_THUMB_SHIFT
:
23930 /* 5bit shift value (0..32). LSL cannot take 32. */
23931 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23932 temp
= newval
& 0xf800;
23933 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23935 _("invalid shift value: %ld"), (long) value
);
23936 /* Shifts of zero must be encoded as LSL. */
23938 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23939 /* Shifts of 32 are encoded as zero. */
23940 else if (value
== 32)
23942 newval
|= value
<< 6;
23943 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23946 case BFD_RELOC_VTABLE_INHERIT
:
23947 case BFD_RELOC_VTABLE_ENTRY
:
23951 case BFD_RELOC_ARM_MOVW
:
23952 case BFD_RELOC_ARM_MOVT
:
23953 case BFD_RELOC_ARM_THUMB_MOVW
:
23954 case BFD_RELOC_ARM_THUMB_MOVT
:
23955 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23957 /* REL format relocations are limited to a 16-bit addend. */
23958 if (!fixP
->fx_done
)
23960 if (value
< -0x8000 || value
> 0x7fff)
23961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23962 _("offset out of range"));
23964 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23965 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23970 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23971 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23973 newval
= get_thumb32_insn (buf
);
23974 newval
&= 0xfbf08f00;
23975 newval
|= (value
& 0xf000) << 4;
23976 newval
|= (value
& 0x0800) << 15;
23977 newval
|= (value
& 0x0700) << 4;
23978 newval
|= (value
& 0x00ff);
23979 put_thumb32_insn (buf
, newval
);
23983 newval
= md_chars_to_number (buf
, 4);
23984 newval
&= 0xfff0f000;
23985 newval
|= value
& 0x0fff;
23986 newval
|= (value
& 0xf000) << 4;
23987 md_number_to_chars (buf
, newval
, 4);
23992 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23993 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23994 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23995 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23996 gas_assert (!fixP
->fx_done
);
23999 bfd_boolean is_mov
;
24000 bfd_vma encoded_addend
= value
;
24002 /* Check that addend can be encoded in instruction. */
24003 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24005 _("the offset 0x%08lX is not representable"),
24006 (unsigned long) encoded_addend
);
24008 /* Extract the instruction. */
24009 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24010 is_mov
= (insn
& 0xf800) == 0x2000;
24015 if (!seg
->use_rela_p
)
24016 insn
|= encoded_addend
;
24022 /* Extract the instruction. */
24023 /* Encoding is the following
24028 /* The following conditions must be true :
24033 rd
= (insn
>> 4) & 0xf;
24035 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24037 _("Unable to process relocation for thumb opcode: %lx"),
24038 (unsigned long) insn
);
24040 /* Encode as ADD immediate8 thumb 1 code. */
24041 insn
= 0x3000 | (rd
<< 8);
24043 /* Place the encoded addend into the first 8 bits of the
24045 if (!seg
->use_rela_p
)
24046 insn
|= encoded_addend
;
24049 /* Update the instruction. */
24050 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24054 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24055 case BFD_RELOC_ARM_ALU_PC_G0
:
24056 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24057 case BFD_RELOC_ARM_ALU_PC_G1
:
24058 case BFD_RELOC_ARM_ALU_PC_G2
:
24059 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24060 case BFD_RELOC_ARM_ALU_SB_G0
:
24061 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24062 case BFD_RELOC_ARM_ALU_SB_G1
:
24063 case BFD_RELOC_ARM_ALU_SB_G2
:
24064 gas_assert (!fixP
->fx_done
);
24065 if (!seg
->use_rela_p
)
24068 bfd_vma encoded_addend
;
24069 bfd_vma addend_abs
= abs (value
);
24071 /* Check that the absolute value of the addend can be
24072 expressed as an 8-bit constant plus a rotation. */
24073 encoded_addend
= encode_arm_immediate (addend_abs
);
24074 if (encoded_addend
== (unsigned int) FAIL
)
24075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24076 _("the offset 0x%08lX is not representable"),
24077 (unsigned long) addend_abs
);
24079 /* Extract the instruction. */
24080 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24082 /* If the addend is positive, use an ADD instruction.
24083 Otherwise use a SUB. Take care not to destroy the S bit. */
24084 insn
&= 0xff1fffff;
24090 /* Place the encoded addend into the first 12 bits of the
24092 insn
&= 0xfffff000;
24093 insn
|= encoded_addend
;
24095 /* Update the instruction. */
24096 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24100 case BFD_RELOC_ARM_LDR_PC_G0
:
24101 case BFD_RELOC_ARM_LDR_PC_G1
:
24102 case BFD_RELOC_ARM_LDR_PC_G2
:
24103 case BFD_RELOC_ARM_LDR_SB_G0
:
24104 case BFD_RELOC_ARM_LDR_SB_G1
:
24105 case BFD_RELOC_ARM_LDR_SB_G2
:
24106 gas_assert (!fixP
->fx_done
);
24107 if (!seg
->use_rela_p
)
24110 bfd_vma addend_abs
= abs (value
);
24112 /* Check that the absolute value of the addend can be
24113 encoded in 12 bits. */
24114 if (addend_abs
>= 0x1000)
24115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24116 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24117 (unsigned long) addend_abs
);
24119 /* Extract the instruction. */
24120 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24122 /* If the addend is negative, clear bit 23 of the instruction.
24123 Otherwise set it. */
24125 insn
&= ~(1 << 23);
24129 /* Place the absolute value of the addend into the first 12 bits
24130 of the instruction. */
24131 insn
&= 0xfffff000;
24132 insn
|= addend_abs
;
24134 /* Update the instruction. */
24135 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24139 case BFD_RELOC_ARM_LDRS_PC_G0
:
24140 case BFD_RELOC_ARM_LDRS_PC_G1
:
24141 case BFD_RELOC_ARM_LDRS_PC_G2
:
24142 case BFD_RELOC_ARM_LDRS_SB_G0
:
24143 case BFD_RELOC_ARM_LDRS_SB_G1
:
24144 case BFD_RELOC_ARM_LDRS_SB_G2
:
24145 gas_assert (!fixP
->fx_done
);
24146 if (!seg
->use_rela_p
)
24149 bfd_vma addend_abs
= abs (value
);
24151 /* Check that the absolute value of the addend can be
24152 encoded in 8 bits. */
24153 if (addend_abs
>= 0x100)
24154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24155 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24156 (unsigned long) addend_abs
);
24158 /* Extract the instruction. */
24159 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24161 /* If the addend is negative, clear bit 23 of the instruction.
24162 Otherwise set it. */
24164 insn
&= ~(1 << 23);
24168 /* Place the first four bits of the absolute value of the addend
24169 into the first 4 bits of the instruction, and the remaining
24170 four into bits 8 .. 11. */
24171 insn
&= 0xfffff0f0;
24172 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24174 /* Update the instruction. */
24175 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24179 case BFD_RELOC_ARM_LDC_PC_G0
:
24180 case BFD_RELOC_ARM_LDC_PC_G1
:
24181 case BFD_RELOC_ARM_LDC_PC_G2
:
24182 case BFD_RELOC_ARM_LDC_SB_G0
:
24183 case BFD_RELOC_ARM_LDC_SB_G1
:
24184 case BFD_RELOC_ARM_LDC_SB_G2
:
24185 gas_assert (!fixP
->fx_done
);
24186 if (!seg
->use_rela_p
)
24189 bfd_vma addend_abs
= abs (value
);
24191 /* Check that the absolute value of the addend is a multiple of
24192 four and, when divided by four, fits in 8 bits. */
24193 if (addend_abs
& 0x3)
24194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24195 _("bad offset 0x%08lX (must be word-aligned)"),
24196 (unsigned long) addend_abs
);
24198 if ((addend_abs
>> 2) > 0xff)
24199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24200 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24201 (unsigned long) addend_abs
);
24203 /* Extract the instruction. */
24204 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24206 /* If the addend is negative, clear bit 23 of the instruction.
24207 Otherwise set it. */
24209 insn
&= ~(1 << 23);
24213 /* Place the addend (divided by four) into the first eight
24214 bits of the instruction. */
24215 insn
&= 0xfffffff0;
24216 insn
|= addend_abs
>> 2;
24218 /* Update the instruction. */
24219 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24223 case BFD_RELOC_ARM_V4BX
:
24224 /* This will need to go in the object file. */
24228 case BFD_RELOC_UNUSED
:
24230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24231 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24235 /* Translate internal representation of relocation info to BFD target
24239 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24242 bfd_reloc_code_real_type code
;
24244 reloc
= XNEW (arelent
);
24246 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24247 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24248 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24250 if (fixp
->fx_pcrel
)
24252 if (section
->use_rela_p
)
24253 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24255 fixp
->fx_offset
= reloc
->address
;
24257 reloc
->addend
= fixp
->fx_offset
;
24259 switch (fixp
->fx_r_type
)
24262 if (fixp
->fx_pcrel
)
24264 code
= BFD_RELOC_8_PCREL
;
24267 /* Fall through. */
24270 if (fixp
->fx_pcrel
)
24272 code
= BFD_RELOC_16_PCREL
;
24275 /* Fall through. */
24278 if (fixp
->fx_pcrel
)
24280 code
= BFD_RELOC_32_PCREL
;
24283 /* Fall through. */
24285 case BFD_RELOC_ARM_MOVW
:
24286 if (fixp
->fx_pcrel
)
24288 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24291 /* Fall through. */
24293 case BFD_RELOC_ARM_MOVT
:
24294 if (fixp
->fx_pcrel
)
24296 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24299 /* Fall through. */
24301 case BFD_RELOC_ARM_THUMB_MOVW
:
24302 if (fixp
->fx_pcrel
)
24304 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24307 /* Fall through. */
24309 case BFD_RELOC_ARM_THUMB_MOVT
:
24310 if (fixp
->fx_pcrel
)
24312 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24315 /* Fall through. */
24317 case BFD_RELOC_NONE
:
24318 case BFD_RELOC_ARM_PCREL_BRANCH
:
24319 case BFD_RELOC_ARM_PCREL_BLX
:
24320 case BFD_RELOC_RVA
:
24321 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24322 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24323 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24324 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24325 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24326 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24327 case BFD_RELOC_VTABLE_ENTRY
:
24328 case BFD_RELOC_VTABLE_INHERIT
:
24330 case BFD_RELOC_32_SECREL
:
24332 code
= fixp
->fx_r_type
;
24335 case BFD_RELOC_THUMB_PCREL_BLX
:
24337 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24338 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24341 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24344 case BFD_RELOC_ARM_LITERAL
:
24345 case BFD_RELOC_ARM_HWLITERAL
:
24346 /* If this is called then the a literal has
24347 been referenced across a section boundary. */
24348 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24349 _("literal referenced across section boundary"));
24353 case BFD_RELOC_ARM_TLS_CALL
:
24354 case BFD_RELOC_ARM_THM_TLS_CALL
:
24355 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24356 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24357 case BFD_RELOC_ARM_GOT32
:
24358 case BFD_RELOC_ARM_GOTOFF
:
24359 case BFD_RELOC_ARM_GOT_PREL
:
24360 case BFD_RELOC_ARM_PLT32
:
24361 case BFD_RELOC_ARM_TARGET1
:
24362 case BFD_RELOC_ARM_ROSEGREL32
:
24363 case BFD_RELOC_ARM_SBREL32
:
24364 case BFD_RELOC_ARM_PREL31
:
24365 case BFD_RELOC_ARM_TARGET2
:
24366 case BFD_RELOC_ARM_TLS_LDO32
:
24367 case BFD_RELOC_ARM_PCREL_CALL
:
24368 case BFD_RELOC_ARM_PCREL_JUMP
:
24369 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24370 case BFD_RELOC_ARM_ALU_PC_G0
:
24371 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24372 case BFD_RELOC_ARM_ALU_PC_G1
:
24373 case BFD_RELOC_ARM_ALU_PC_G2
:
24374 case BFD_RELOC_ARM_LDR_PC_G0
:
24375 case BFD_RELOC_ARM_LDR_PC_G1
:
24376 case BFD_RELOC_ARM_LDR_PC_G2
:
24377 case BFD_RELOC_ARM_LDRS_PC_G0
:
24378 case BFD_RELOC_ARM_LDRS_PC_G1
:
24379 case BFD_RELOC_ARM_LDRS_PC_G2
:
24380 case BFD_RELOC_ARM_LDC_PC_G0
:
24381 case BFD_RELOC_ARM_LDC_PC_G1
:
24382 case BFD_RELOC_ARM_LDC_PC_G2
:
24383 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24384 case BFD_RELOC_ARM_ALU_SB_G0
:
24385 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24386 case BFD_RELOC_ARM_ALU_SB_G1
:
24387 case BFD_RELOC_ARM_ALU_SB_G2
:
24388 case BFD_RELOC_ARM_LDR_SB_G0
:
24389 case BFD_RELOC_ARM_LDR_SB_G1
:
24390 case BFD_RELOC_ARM_LDR_SB_G2
:
24391 case BFD_RELOC_ARM_LDRS_SB_G0
:
24392 case BFD_RELOC_ARM_LDRS_SB_G1
:
24393 case BFD_RELOC_ARM_LDRS_SB_G2
:
24394 case BFD_RELOC_ARM_LDC_SB_G0
:
24395 case BFD_RELOC_ARM_LDC_SB_G1
:
24396 case BFD_RELOC_ARM_LDC_SB_G2
:
24397 case BFD_RELOC_ARM_V4BX
:
24398 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24399 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24400 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24401 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24402 code
= fixp
->fx_r_type
;
24405 case BFD_RELOC_ARM_TLS_GOTDESC
:
24406 case BFD_RELOC_ARM_TLS_GD32
:
24407 case BFD_RELOC_ARM_TLS_LE32
:
24408 case BFD_RELOC_ARM_TLS_IE32
:
24409 case BFD_RELOC_ARM_TLS_LDM32
:
24410 /* BFD will include the symbol's address in the addend.
24411 But we don't want that, so subtract it out again here. */
24412 if (!S_IS_COMMON (fixp
->fx_addsy
))
24413 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24414 code
= fixp
->fx_r_type
;
24418 case BFD_RELOC_ARM_IMMEDIATE
:
24419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24420 _("internal relocation (type: IMMEDIATE) not fixed up"));
24423 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24424 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24425 _("ADRL used for a symbol not defined in the same file"));
24428 case BFD_RELOC_ARM_OFFSET_IMM
:
24429 if (section
->use_rela_p
)
24431 code
= fixp
->fx_r_type
;
24435 if (fixp
->fx_addsy
!= NULL
24436 && !S_IS_DEFINED (fixp
->fx_addsy
)
24437 && S_IS_LOCAL (fixp
->fx_addsy
))
24439 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24440 _("undefined local label `%s'"),
24441 S_GET_NAME (fixp
->fx_addsy
));
24445 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24446 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24453 switch (fixp
->fx_r_type
)
24455 case BFD_RELOC_NONE
: type
= "NONE"; break;
24456 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24457 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24458 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24459 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24460 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24461 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24462 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24463 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24464 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24465 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24466 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24467 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24468 default: type
= _("<unknown>"); break;
24470 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24471 _("cannot represent %s relocation in this object file format"),
24478 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24480 && fixp
->fx_addsy
== GOT_symbol
)
24482 code
= BFD_RELOC_ARM_GOTPC
;
24483 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24487 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24489 if (reloc
->howto
== NULL
)
24491 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24492 _("cannot represent %s relocation in this object file format"),
24493 bfd_get_reloc_code_name (code
));
24497 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24498 vtable entry to be used in the relocation's section offset. */
24499 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24500 reloc
->address
= fixp
->fx_offset
;
24505 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24508 cons_fix_new_arm (fragS
* frag
,
24512 bfd_reloc_code_real_type reloc
)
24517 FIXME: @@ Should look at CPU word size. */
24521 reloc
= BFD_RELOC_8
;
24524 reloc
= BFD_RELOC_16
;
24528 reloc
= BFD_RELOC_32
;
24531 reloc
= BFD_RELOC_64
;
24536 if (exp
->X_op
== O_secrel
)
24538 exp
->X_op
= O_symbol
;
24539 reloc
= BFD_RELOC_32_SECREL
;
24543 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24546 #if defined (OBJ_COFF)
24548 arm_validate_fix (fixS
* fixP
)
24550 /* If the destination of the branch is a defined symbol which does not have
24551 the THUMB_FUNC attribute, then we must be calling a function which has
24552 the (interfacearm) attribute. We look for the Thumb entry point to that
24553 function and change the branch to refer to that function instead. */
24554 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24555 && fixP
->fx_addsy
!= NULL
24556 && S_IS_DEFINED (fixP
->fx_addsy
)
24557 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24559 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24566 arm_force_relocation (struct fix
* fixp
)
24568 #if defined (OBJ_COFF) && defined (TE_PE)
24569 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24573 /* In case we have a call or a branch to a function in ARM ISA mode from
24574 a thumb function or vice-versa force the relocation. These relocations
24575 are cleared off for some cores that might have blx and simple transformations
24579 switch (fixp
->fx_r_type
)
24581 case BFD_RELOC_ARM_PCREL_JUMP
:
24582 case BFD_RELOC_ARM_PCREL_CALL
:
24583 case BFD_RELOC_THUMB_PCREL_BLX
:
24584 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24588 case BFD_RELOC_ARM_PCREL_BLX
:
24589 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24590 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24591 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24592 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24601 /* Resolve these relocations even if the symbol is extern or weak.
24602 Technically this is probably wrong due to symbol preemption.
24603 In practice these relocations do not have enough range to be useful
24604 at dynamic link time, and some code (e.g. in the Linux kernel)
24605 expects these references to be resolved. */
24606 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24607 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24608 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24609 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24610 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24611 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24612 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24613 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24614 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24615 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24616 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24617 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24618 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24619 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24622 /* Always leave these relocations for the linker. */
24623 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24624 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24625 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24628 /* Always generate relocations against function symbols. */
24629 if (fixp
->fx_r_type
== BFD_RELOC_32
24631 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24634 return generic_force_reloc (fixp
);
24637 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24638 /* Relocations against function names must be left unadjusted,
24639 so that the linker can use this information to generate interworking
24640 stubs. The MIPS version of this function
24641 also prevents relocations that are mips-16 specific, but I do not
24642 know why it does this.
24645 There is one other problem that ought to be addressed here, but
24646 which currently is not: Taking the address of a label (rather
24647 than a function) and then later jumping to that address. Such
24648 addresses also ought to have their bottom bit set (assuming that
24649 they reside in Thumb code), but at the moment they will not. */
24652 arm_fix_adjustable (fixS
* fixP
)
24654 if (fixP
->fx_addsy
== NULL
)
24657 /* Preserve relocations against symbols with function type. */
24658 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24661 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24662 && fixP
->fx_subsy
== NULL
)
24665 /* We need the symbol name for the VTABLE entries. */
24666 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24667 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24670 /* Don't allow symbols to be discarded on GOT related relocs. */
24671 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24672 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24673 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24674 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24675 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24676 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24677 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24678 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24679 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24680 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24681 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24682 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24683 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24684 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24687 /* Similarly for group relocations. */
24688 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24689 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24690 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24693 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24694 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24695 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24696 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24697 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24698 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24699 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24700 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24701 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24704 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24705 offsets, so keep these symbols. */
24706 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24707 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24712 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24716 elf32_arm_target_format (void)
24719 return (target_big_endian
24720 ? "elf32-bigarm-symbian"
24721 : "elf32-littlearm-symbian");
24722 #elif defined (TE_VXWORKS)
24723 return (target_big_endian
24724 ? "elf32-bigarm-vxworks"
24725 : "elf32-littlearm-vxworks");
24726 #elif defined (TE_NACL)
24727 return (target_big_endian
24728 ? "elf32-bigarm-nacl"
24729 : "elf32-littlearm-nacl");
24731 if (target_big_endian
)
24732 return "elf32-bigarm";
24734 return "elf32-littlearm";
24739 armelf_frob_symbol (symbolS
* symp
,
24742 elf_frob_symbol (symp
, puntp
);
24746 /* MD interface: Finalization. */
24751 literal_pool
* pool
;
24753 /* Ensure that all the IT blocks are properly closed. */
24754 check_it_blocks_finished ();
24756 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24758 /* Put it at the end of the relevant section. */
24759 subseg_set (pool
->section
, pool
->sub_section
);
24761 arm_elf_change_section ();
24768 /* Remove any excess mapping symbols generated for alignment frags in
24769 SEC. We may have created a mapping symbol before a zero byte
24770 alignment; remove it if there's a mapping symbol after the
24773 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24774 void *dummy ATTRIBUTE_UNUSED
)
24776 segment_info_type
*seginfo
= seg_info (sec
);
24779 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24782 for (fragp
= seginfo
->frchainP
->frch_root
;
24784 fragp
= fragp
->fr_next
)
24786 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24787 fragS
*next
= fragp
->fr_next
;
24789 /* Variable-sized frags have been converted to fixed size by
24790 this point. But if this was variable-sized to start with,
24791 there will be a fixed-size frag after it. So don't handle
24793 if (sym
== NULL
|| next
== NULL
)
24796 if (S_GET_VALUE (sym
) < next
->fr_address
)
24797 /* Not at the end of this frag. */
24799 know (S_GET_VALUE (sym
) == next
->fr_address
);
24803 if (next
->tc_frag_data
.first_map
!= NULL
)
24805 /* Next frag starts with a mapping symbol. Discard this
24807 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24811 if (next
->fr_next
== NULL
)
24813 /* This mapping symbol is at the end of the section. Discard
24815 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24816 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24820 /* As long as we have empty frags without any mapping symbols,
24822 /* If the next frag is non-empty and does not start with a
24823 mapping symbol, then this mapping symbol is required. */
24824 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24827 next
= next
->fr_next
;
24829 while (next
!= NULL
);
24834 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24838 arm_adjust_symtab (void)
24843 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24845 if (ARM_IS_THUMB (sym
))
24847 if (THUMB_IS_FUNC (sym
))
24849 /* Mark the symbol as a Thumb function. */
24850 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24851 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24852 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24854 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24855 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24857 as_bad (_("%s: unexpected function type: %d"),
24858 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24860 else switch (S_GET_STORAGE_CLASS (sym
))
24863 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24866 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24869 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24877 if (ARM_IS_INTERWORK (sym
))
24878 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24885 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24887 if (ARM_IS_THUMB (sym
))
24889 elf_symbol_type
* elf_sym
;
24891 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24892 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24894 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24895 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24897 /* If it's a .thumb_func, declare it as so,
24898 otherwise tag label as .code 16. */
24899 if (THUMB_IS_FUNC (sym
))
24900 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24901 ST_BRANCH_TO_THUMB
);
24902 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24903 elf_sym
->internal_elf_sym
.st_info
=
24904 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24909 /* Remove any overlapping mapping symbols generated by alignment frags. */
24910 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24911 /* Now do generic ELF adjustments. */
24912 elf_adjust_symtab ();
24916 /* MD interface: Initialization. */
24919 set_constant_flonums (void)
24923 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24924 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24928 /* Auto-select Thumb mode if it's the only available instruction set for the
24929 given architecture. */
24932 autoselect_thumb_from_cpu_variant (void)
24934 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24935 opcode_select (16);
24944 if ( (arm_ops_hsh
= hash_new ()) == NULL
24945 || (arm_cond_hsh
= hash_new ()) == NULL
24946 || (arm_shift_hsh
= hash_new ()) == NULL
24947 || (arm_psr_hsh
= hash_new ()) == NULL
24948 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24949 || (arm_reg_hsh
= hash_new ()) == NULL
24950 || (arm_reloc_hsh
= hash_new ()) == NULL
24951 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24952 as_fatal (_("virtual memory exhausted"));
24954 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24955 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24956 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24957 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24958 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24959 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24960 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24961 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24962 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24963 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24964 (void *) (v7m_psrs
+ i
));
24965 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24966 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24968 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24970 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24971 (void *) (barrier_opt_names
+ i
));
24973 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24975 struct reloc_entry
* entry
= reloc_names
+ i
;
24977 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24978 /* This makes encode_branch() use the EABI versions of this relocation. */
24979 entry
->reloc
= BFD_RELOC_UNUSED
;
24981 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24985 set_constant_flonums ();
24987 /* Set the cpu variant based on the command-line options. We prefer
24988 -mcpu= over -march= if both are set (as for GCC); and we prefer
24989 -mfpu= over any other way of setting the floating point unit.
24990 Use of legacy options with new options are faulted. */
24993 if (mcpu_cpu_opt
|| march_cpu_opt
)
24994 as_bad (_("use of old and new-style options to set CPU type"));
24996 mcpu_cpu_opt
= legacy_cpu
;
24998 else if (!mcpu_cpu_opt
)
24999 mcpu_cpu_opt
= march_cpu_opt
;
25004 as_bad (_("use of old and new-style options to set FPU type"));
25006 mfpu_opt
= legacy_fpu
;
25008 else if (!mfpu_opt
)
25010 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25011 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25012 /* Some environments specify a default FPU. If they don't, infer it
25013 from the processor. */
25015 mfpu_opt
= mcpu_fpu_opt
;
25017 mfpu_opt
= march_fpu_opt
;
25019 mfpu_opt
= &fpu_default
;
25025 if (mcpu_cpu_opt
!= NULL
)
25026 mfpu_opt
= &fpu_default
;
25027 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25028 mfpu_opt
= &fpu_arch_vfp_v2
;
25030 mfpu_opt
= &fpu_arch_fpa
;
25036 mcpu_cpu_opt
= &cpu_default
;
25037 selected_cpu
= cpu_default
;
25039 else if (no_cpu_selected ())
25040 selected_cpu
= cpu_default
;
25043 selected_cpu
= *mcpu_cpu_opt
;
25045 mcpu_cpu_opt
= &arm_arch_any
;
25048 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25050 autoselect_thumb_from_cpu_variant ();
25052 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25054 #if defined OBJ_COFF || defined OBJ_ELF
25056 unsigned int flags
= 0;
25058 #if defined OBJ_ELF
25059 flags
= meabi_flags
;
25061 switch (meabi_flags
)
25063 case EF_ARM_EABI_UNKNOWN
:
25065 /* Set the flags in the private structure. */
25066 if (uses_apcs_26
) flags
|= F_APCS26
;
25067 if (support_interwork
) flags
|= F_INTERWORK
;
25068 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25069 if (pic_code
) flags
|= F_PIC
;
25070 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25071 flags
|= F_SOFT_FLOAT
;
25073 switch (mfloat_abi_opt
)
25075 case ARM_FLOAT_ABI_SOFT
:
25076 case ARM_FLOAT_ABI_SOFTFP
:
25077 flags
|= F_SOFT_FLOAT
;
25080 case ARM_FLOAT_ABI_HARD
:
25081 if (flags
& F_SOFT_FLOAT
)
25082 as_bad (_("hard-float conflicts with specified fpu"));
25086 /* Using pure-endian doubles (even if soft-float). */
25087 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25088 flags
|= F_VFP_FLOAT
;
25090 #if defined OBJ_ELF
25091 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25092 flags
|= EF_ARM_MAVERICK_FLOAT
;
25095 case EF_ARM_EABI_VER4
:
25096 case EF_ARM_EABI_VER5
:
25097 /* No additional flags to set. */
25104 bfd_set_private_flags (stdoutput
, flags
);
25106 /* We have run out flags in the COFF header to encode the
25107 status of ATPCS support, so instead we create a dummy,
25108 empty, debug section called .arm.atpcs. */
25113 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25117 bfd_set_section_flags
25118 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25119 bfd_set_section_size (stdoutput
, sec
, 0);
25120 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25126 /* Record the CPU type as well. */
25127 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25128 mach
= bfd_mach_arm_iWMMXt2
;
25129 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25130 mach
= bfd_mach_arm_iWMMXt
;
25131 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25132 mach
= bfd_mach_arm_XScale
;
25133 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25134 mach
= bfd_mach_arm_ep9312
;
25135 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25136 mach
= bfd_mach_arm_5TE
;
25137 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25139 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25140 mach
= bfd_mach_arm_5T
;
25142 mach
= bfd_mach_arm_5
;
25144 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25146 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25147 mach
= bfd_mach_arm_4T
;
25149 mach
= bfd_mach_arm_4
;
25151 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25152 mach
= bfd_mach_arm_3M
;
25153 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25154 mach
= bfd_mach_arm_3
;
25155 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25156 mach
= bfd_mach_arm_2a
;
25157 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25158 mach
= bfd_mach_arm_2
;
25160 mach
= bfd_mach_arm_unknown
;
25162 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25165 /* Command line processing. */
25168 Invocation line includes a switch not recognized by the base assembler.
25169 See if it's a processor-specific option.
25171 This routine is somewhat complicated by the need for backwards
25172 compatibility (since older releases of gcc can't be changed).
25173 The new options try to make the interface as compatible as
25176 New options (supported) are:
25178 -mcpu=<cpu name> Assemble for selected processor
25179 -march=<architecture name> Assemble for selected architecture
25180 -mfpu=<fpu architecture> Assemble for selected FPU.
25181 -EB/-mbig-endian Big-endian
25182 -EL/-mlittle-endian Little-endian
25183 -k Generate PIC code
25184 -mthumb Start in Thumb mode
25185 -mthumb-interwork Code supports ARM/Thumb interworking
25187 -m[no-]warn-deprecated Warn about deprecated features
25188 -m[no-]warn-syms Warn when symbols match instructions
25190 For now we will also provide support for:
25192 -mapcs-32 32-bit Program counter
25193 -mapcs-26 26-bit Program counter
25194 -macps-float Floats passed in FP registers
25195 -mapcs-reentrant Reentrant code
25197 (sometime these will probably be replaced with -mapcs=<list of options>
25198 and -matpcs=<list of options>)
25200 The remaining options are only supported for back-wards compatibility.
25201 Cpu variants, the arm part is optional:
25202 -m[arm]1 Currently not supported.
25203 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25204 -m[arm]3 Arm 3 processor
25205 -m[arm]6[xx], Arm 6 processors
25206 -m[arm]7[xx][t][[d]m] Arm 7 processors
25207 -m[arm]8[10] Arm 8 processors
25208 -m[arm]9[20][tdmi] Arm 9 processors
25209 -mstrongarm[110[0]] StrongARM processors
25210 -mxscale XScale processors
25211 -m[arm]v[2345[t[e]]] Arm architectures
25212 -mall All (except the ARM1)
25214 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25215 -mfpe-old (No float load/store multiples)
25216 -mvfpxd VFP Single precision
25218 -mno-fpu Disable all floating point instructions
25220 The following CPU names are recognized:
25221 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25222 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25223 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25224 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25225 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25226 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25227 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25231 const char * md_shortopts
= "m:k";
25233 #ifdef ARM_BI_ENDIAN
25234 #define OPTION_EB (OPTION_MD_BASE + 0)
25235 #define OPTION_EL (OPTION_MD_BASE + 1)
25237 #if TARGET_BYTES_BIG_ENDIAN
25238 #define OPTION_EB (OPTION_MD_BASE + 0)
25240 #define OPTION_EL (OPTION_MD_BASE + 1)
25243 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25245 struct option md_longopts
[] =
25248 {"EB", no_argument
, NULL
, OPTION_EB
},
25251 {"EL", no_argument
, NULL
, OPTION_EL
},
25253 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25254 {NULL
, no_argument
, NULL
, 0}
25258 size_t md_longopts_size
= sizeof (md_longopts
);
25260 struct arm_option_table
25262 const char *option
; /* Option name to match. */
25263 const char *help
; /* Help information. */
25264 int *var
; /* Variable to change. */
25265 int value
; /* What to change it to. */
25266 const char *deprecated
; /* If non-null, print this message. */
25269 struct arm_option_table arm_opts
[] =
25271 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25272 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25273 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25274 &support_interwork
, 1, NULL
},
25275 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25276 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25277 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25279 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25280 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25281 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25282 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25285 /* These are recognized by the assembler, but have no affect on code. */
25286 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25287 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25289 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25290 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25291 &warn_on_deprecated
, 0, NULL
},
25292 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25293 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25294 {NULL
, NULL
, NULL
, 0, NULL
}
25297 struct arm_legacy_option_table
25299 const char *option
; /* Option name to match. */
25300 const arm_feature_set
**var
; /* Variable to change. */
25301 const arm_feature_set value
; /* What to change it to. */
25302 const char *deprecated
; /* If non-null, print this message. */
25305 const struct arm_legacy_option_table arm_legacy_opts
[] =
25307 /* DON'T add any new processors to this list -- we want the whole list
25308 to go away... Add them to the processors table instead. */
25309 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25310 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25311 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25312 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25313 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25314 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25315 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25316 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25317 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25318 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25319 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25320 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25321 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25322 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25323 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25324 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25325 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25326 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25327 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25328 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25329 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25330 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25331 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25332 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25333 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25334 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25335 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25336 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25337 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25338 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25339 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25340 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25341 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25342 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25343 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25344 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25345 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25346 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25347 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25348 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25349 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25350 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25351 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25352 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25353 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25354 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25355 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25356 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25357 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25358 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25359 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25360 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25361 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25362 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25363 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25364 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25365 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25366 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25367 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25368 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25369 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25370 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25371 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25372 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25373 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25374 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25375 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25376 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25377 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25378 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25379 N_("use -mcpu=strongarm110")},
25380 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25381 N_("use -mcpu=strongarm1100")},
25382 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25383 N_("use -mcpu=strongarm1110")},
25384 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25385 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25386 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25388 /* Architecture variants -- don't add any more to this list either. */
25389 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25390 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25391 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25392 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25393 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25394 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25395 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25396 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25397 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25398 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25399 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25400 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25401 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25402 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25403 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25404 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25405 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25406 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25408 /* Floating point variants -- don't add any more to this list either. */
25409 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25410 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25411 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25412 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25413 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25415 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25418 struct arm_cpu_option_table
25422 const arm_feature_set value
;
25423 /* For some CPUs we assume an FPU unless the user explicitly sets
25425 const arm_feature_set default_fpu
;
25426 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25428 const char *canonical_name
;
25431 /* This list should, at a minimum, contain all the cpu names
25432 recognized by GCC. */
25433 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25434 static const struct arm_cpu_option_table arm_cpus
[] =
25436 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25437 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25438 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25439 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25440 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25441 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25442 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25443 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25444 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25445 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25446 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25447 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25448 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25449 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25450 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25451 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25452 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25453 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25454 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25455 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25456 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25457 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25458 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25459 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25460 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25461 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25462 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25463 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25464 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25465 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25466 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25467 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25468 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25469 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25470 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25471 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25472 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25473 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25474 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25475 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25476 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25477 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25478 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25479 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25480 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25481 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25482 /* For V5 or later processors we default to using VFP; but the user
25483 should really set the FPU type explicitly. */
25484 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25485 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25486 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25487 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25488 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25489 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25490 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25491 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25492 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25493 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25494 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25495 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25496 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25497 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25498 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25499 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25500 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25501 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25502 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25503 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25505 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25506 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25507 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25508 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25509 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25510 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25511 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25512 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25513 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25515 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25516 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25517 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25518 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25519 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25520 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25521 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25522 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25523 FPU_NONE
, "Cortex-A5"),
25524 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25526 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25527 ARM_FEATURE_COPROC (FPU_VFP_V3
25528 | FPU_NEON_EXT_V1
),
25530 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25531 ARM_FEATURE_COPROC (FPU_VFP_V3
25532 | FPU_NEON_EXT_V1
),
25534 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25536 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25538 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25540 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25542 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25544 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25546 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25548 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25550 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25552 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25553 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25555 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25556 FPU_NONE
, "Cortex-R5"),
25557 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25558 FPU_ARCH_VFP_V3D16
,
25560 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25561 FPU_ARCH_VFP_V3D16
,
25563 ARM_CPU_OPT ("cortex-m33", ARM_ARCH_V8M_MAIN_DSP
,
25564 FPU_NONE
, "Cortex-M33"),
25565 ARM_CPU_OPT ("cortex-m23", ARM_ARCH_V8M_BASE
,
25566 FPU_NONE
, "Cortex-M23"),
25567 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25568 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25569 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25570 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25571 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25572 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25573 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25576 ARM_CPU_OPT ("falkor", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25579 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25583 /* ??? XSCALE is really an architecture. */
25584 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25585 /* ??? iwmmxt is not a processor. */
25586 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25587 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25588 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25590 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25591 FPU_ARCH_MAVERICK
, "ARM920T"),
25592 /* Marvell processors. */
25593 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25595 ARM_EXT2_V6T2_V8M
),
25596 FPU_ARCH_VFP_V3D16
, NULL
),
25597 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25599 ARM_EXT2_V6T2_V8M
),
25600 FPU_ARCH_NEON_VFP_V4
, NULL
),
25601 /* APM X-Gene family. */
25602 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25604 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25607 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25611 struct arm_arch_option_table
25615 const arm_feature_set value
;
25616 const arm_feature_set default_fpu
;
25619 /* This list should, at a minimum, contain all the architecture names
25620 recognized by GCC. */
25621 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25622 static const struct arm_arch_option_table arm_archs
[] =
25624 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25625 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25626 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25627 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25628 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25629 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25630 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25631 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25632 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25633 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25634 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25635 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25636 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25637 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25638 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25639 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25640 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25641 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25642 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25643 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25644 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25645 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25646 kept to preserve existing behaviour. */
25647 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25648 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25649 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25650 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25651 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25652 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25653 kept to preserve existing behaviour. */
25654 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25655 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25656 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25657 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25658 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25659 /* The official spelling of the ARMv7 profile variants is the dashed form.
25660 Accept the non-dashed form for compatibility with old toolchains. */
25661 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25662 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25663 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25664 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25665 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25666 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25667 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25668 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25669 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25670 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25671 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25672 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25673 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25674 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25675 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25676 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25677 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25678 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25680 #undef ARM_ARCH_OPT
25682 /* ISA extensions in the co-processor and main instruction set space. */
25683 struct arm_option_extension_value_table
25687 const arm_feature_set merge_value
;
25688 const arm_feature_set clear_value
;
25689 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25690 indicates that an extension is available for all architectures while
25691 ARM_ANY marks an empty entry. */
25692 const arm_feature_set allowed_archs
[2];
25695 /* The following table must be in alphabetical order with a NULL last entry.
25697 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25698 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25699 static const struct arm_option_extension_value_table arm_extensions
[] =
25701 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25702 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25703 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25704 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25705 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25706 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25707 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25708 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25709 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25710 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25711 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25712 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25714 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25715 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25716 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25717 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25718 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25719 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25720 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25721 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25722 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25723 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25724 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25725 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25726 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25727 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25728 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25729 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25730 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25731 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25732 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25733 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25734 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25735 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25736 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25737 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25738 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25739 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25740 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25741 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25742 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25743 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25744 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25745 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25746 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25747 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25749 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25750 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25751 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25752 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25753 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25757 /* ISA floating-point and Advanced SIMD extensions. */
25758 struct arm_option_fpu_value_table
25761 const arm_feature_set value
;
25764 /* This list should, at a minimum, contain all the fpu names
25765 recognized by GCC. */
25766 static const struct arm_option_fpu_value_table arm_fpus
[] =
25768 {"softfpa", FPU_NONE
},
25769 {"fpe", FPU_ARCH_FPE
},
25770 {"fpe2", FPU_ARCH_FPE
},
25771 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25772 {"fpa", FPU_ARCH_FPA
},
25773 {"fpa10", FPU_ARCH_FPA
},
25774 {"fpa11", FPU_ARCH_FPA
},
25775 {"arm7500fe", FPU_ARCH_FPA
},
25776 {"softvfp", FPU_ARCH_VFP
},
25777 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25778 {"vfp", FPU_ARCH_VFP_V2
},
25779 {"vfp9", FPU_ARCH_VFP_V2
},
25780 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25781 {"vfp10", FPU_ARCH_VFP_V2
},
25782 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25783 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25784 {"vfpv2", FPU_ARCH_VFP_V2
},
25785 {"vfpv3", FPU_ARCH_VFP_V3
},
25786 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25787 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25788 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25789 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25790 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25791 {"arm1020t", FPU_ARCH_VFP_V1
},
25792 {"arm1020e", FPU_ARCH_VFP_V2
},
25793 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25794 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25795 {"maverick", FPU_ARCH_MAVERICK
},
25796 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25797 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25798 {"vfpv4", FPU_ARCH_VFP_V4
},
25799 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25800 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25801 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25802 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25803 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25804 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25805 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25806 {"crypto-neon-fp-armv8",
25807 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25808 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25809 {"crypto-neon-fp-armv8.1",
25810 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25811 {NULL
, ARM_ARCH_NONE
}
25814 struct arm_option_value_table
25820 static const struct arm_option_value_table arm_float_abis
[] =
25822 {"hard", ARM_FLOAT_ABI_HARD
},
25823 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25824 {"soft", ARM_FLOAT_ABI_SOFT
},
25829 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25830 static const struct arm_option_value_table arm_eabis
[] =
25832 {"gnu", EF_ARM_EABI_UNKNOWN
},
25833 {"4", EF_ARM_EABI_VER4
},
25834 {"5", EF_ARM_EABI_VER5
},
25839 struct arm_long_option_table
25841 const char * option
; /* Substring to match. */
25842 const char * help
; /* Help information. */
25843 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25844 const char * deprecated
; /* If non-null, print this message. */
25848 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25850 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25852 /* We insist on extensions being specified in alphabetical order, and with
25853 extensions being added before being removed. We achieve this by having
25854 the global ARM_EXTENSIONS table in alphabetical order, and using the
25855 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25856 or removing it (0) and only allowing it to change in the order
25858 const struct arm_option_extension_value_table
* opt
= NULL
;
25859 const arm_feature_set arm_any
= ARM_ANY
;
25860 int adding_value
= -1;
25862 /* Copy the feature set, so that we can modify it. */
25863 *ext_set
= **opt_p
;
25866 while (str
!= NULL
&& *str
!= 0)
25873 as_bad (_("invalid architectural extension"));
25878 ext
= strchr (str
, '+');
25883 len
= strlen (str
);
25885 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25887 if (adding_value
!= 0)
25890 opt
= arm_extensions
;
25898 if (adding_value
== -1)
25901 opt
= arm_extensions
;
25903 else if (adding_value
!= 1)
25905 as_bad (_("must specify extensions to add before specifying "
25906 "those to remove"));
25913 as_bad (_("missing architectural extension"));
25917 gas_assert (adding_value
!= -1);
25918 gas_assert (opt
!= NULL
);
25920 /* Scan over the options table trying to find an exact match. */
25921 for (; opt
->name
!= NULL
; opt
++)
25922 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25924 int i
, nb_allowed_archs
=
25925 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25926 /* Check we can apply the extension to this architecture. */
25927 for (i
= 0; i
< nb_allowed_archs
; i
++)
25930 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25932 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25935 if (i
== nb_allowed_archs
)
25937 as_bad (_("extension does not apply to the base architecture"));
25941 /* Add or remove the extension. */
25943 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25945 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25950 if (opt
->name
== NULL
)
25952 /* Did we fail to find an extension because it wasn't specified in
25953 alphabetical order, or because it does not exist? */
25955 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25956 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25959 if (opt
->name
== NULL
)
25960 as_bad (_("unknown architectural extension `%s'"), str
);
25962 as_bad (_("architectural extensions must be specified in "
25963 "alphabetical order"));
25969 /* We should skip the extension we've just matched the next time
25981 arm_parse_cpu (const char *str
)
25983 const struct arm_cpu_option_table
*opt
;
25984 const char *ext
= strchr (str
, '+');
25990 len
= strlen (str
);
25994 as_bad (_("missing cpu name `%s'"), str
);
25998 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25999 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26001 mcpu_cpu_opt
= &opt
->value
;
26002 mcpu_fpu_opt
= &opt
->default_fpu
;
26003 if (opt
->canonical_name
)
26005 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26006 strcpy (selected_cpu_name
, opt
->canonical_name
);
26012 if (len
>= sizeof selected_cpu_name
)
26013 len
= (sizeof selected_cpu_name
) - 1;
26015 for (i
= 0; i
< len
; i
++)
26016 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26017 selected_cpu_name
[i
] = 0;
26021 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
26026 as_bad (_("unknown cpu `%s'"), str
);
26031 arm_parse_arch (const char *str
)
26033 const struct arm_arch_option_table
*opt
;
26034 const char *ext
= strchr (str
, '+');
26040 len
= strlen (str
);
26044 as_bad (_("missing architecture name `%s'"), str
);
26048 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26049 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26051 march_cpu_opt
= &opt
->value
;
26052 march_fpu_opt
= &opt
->default_fpu
;
26053 strcpy (selected_cpu_name
, opt
->name
);
26056 return arm_parse_extension (ext
, &march_cpu_opt
);
26061 as_bad (_("unknown architecture `%s'\n"), str
);
26066 arm_parse_fpu (const char * str
)
26068 const struct arm_option_fpu_value_table
* opt
;
26070 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26071 if (streq (opt
->name
, str
))
26073 mfpu_opt
= &opt
->value
;
26077 as_bad (_("unknown floating point format `%s'\n"), str
);
26082 arm_parse_float_abi (const char * str
)
26084 const struct arm_option_value_table
* opt
;
26086 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26087 if (streq (opt
->name
, str
))
26089 mfloat_abi_opt
= opt
->value
;
26093 as_bad (_("unknown floating point abi `%s'\n"), str
);
26099 arm_parse_eabi (const char * str
)
26101 const struct arm_option_value_table
*opt
;
26103 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26104 if (streq (opt
->name
, str
))
26106 meabi_flags
= opt
->value
;
26109 as_bad (_("unknown EABI `%s'\n"), str
);
26115 arm_parse_it_mode (const char * str
)
26117 bfd_boolean ret
= TRUE
;
26119 if (streq ("arm", str
))
26120 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26121 else if (streq ("thumb", str
))
26122 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26123 else if (streq ("always", str
))
26124 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26125 else if (streq ("never", str
))
26126 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26129 as_bad (_("unknown implicit IT mode `%s', should be "\
26130 "arm, thumb, always, or never."), str
);
26138 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26140 codecomposer_syntax
= TRUE
;
26141 arm_comment_chars
[0] = ';';
26142 arm_line_separator_chars
[0] = 0;
26146 struct arm_long_option_table arm_long_opts
[] =
26148 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26149 arm_parse_cpu
, NULL
},
26150 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26151 arm_parse_arch
, NULL
},
26152 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26153 arm_parse_fpu
, NULL
},
26154 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26155 arm_parse_float_abi
, NULL
},
26157 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26158 arm_parse_eabi
, NULL
},
26160 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26161 arm_parse_it_mode
, NULL
},
26162 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26163 arm_ccs_mode
, NULL
},
26164 {NULL
, NULL
, 0, NULL
}
26168 md_parse_option (int c
, const char * arg
)
26170 struct arm_option_table
*opt
;
26171 const struct arm_legacy_option_table
*fopt
;
26172 struct arm_long_option_table
*lopt
;
26178 target_big_endian
= 1;
26184 target_big_endian
= 0;
26188 case OPTION_FIX_V4BX
:
26193 /* Listing option. Just ignore these, we don't support additional
26198 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26200 if (c
== opt
->option
[0]
26201 && ((arg
== NULL
&& opt
->option
[1] == 0)
26202 || streq (arg
, opt
->option
+ 1)))
26204 /* If the option is deprecated, tell the user. */
26205 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26206 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26207 arg
? arg
: "", _(opt
->deprecated
));
26209 if (opt
->var
!= NULL
)
26210 *opt
->var
= opt
->value
;
26216 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26218 if (c
== fopt
->option
[0]
26219 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26220 || streq (arg
, fopt
->option
+ 1)))
26222 /* If the option is deprecated, tell the user. */
26223 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26224 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26225 arg
? arg
: "", _(fopt
->deprecated
));
26227 if (fopt
->var
!= NULL
)
26228 *fopt
->var
= &fopt
->value
;
26234 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26236 /* These options are expected to have an argument. */
26237 if (c
== lopt
->option
[0]
26239 && strncmp (arg
, lopt
->option
+ 1,
26240 strlen (lopt
->option
+ 1)) == 0)
26242 /* If the option is deprecated, tell the user. */
26243 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26244 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26245 _(lopt
->deprecated
));
26247 /* Call the sup-option parser. */
26248 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26259 md_show_usage (FILE * fp
)
26261 struct arm_option_table
*opt
;
26262 struct arm_long_option_table
*lopt
;
26264 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26266 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26267 if (opt
->help
!= NULL
)
26268 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26270 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26271 if (lopt
->help
!= NULL
)
26272 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26276 -EB assemble code for a big-endian cpu\n"));
26281 -EL assemble code for a little-endian cpu\n"));
26285 --fix-v4bx Allow BX in ARMv4 code\n"));
26293 arm_feature_set flags
;
26294 } cpu_arch_ver_table
;
26296 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26297 must be sorted least features first but some reordering is needed, eg. for
26298 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26299 static const cpu_arch_ver_table cpu_arch_ver
[] =
26305 {4, ARM_ARCH_V5TE
},
26306 {5, ARM_ARCH_V5TEJ
},
26310 {11, ARM_ARCH_V6M
},
26311 {12, ARM_ARCH_V6SM
},
26312 {8, ARM_ARCH_V6T2
},
26313 {10, ARM_ARCH_V7VE
},
26314 {10, ARM_ARCH_V7R
},
26315 {10, ARM_ARCH_V7M
},
26316 {14, ARM_ARCH_V8A
},
26317 {16, ARM_ARCH_V8M_BASE
},
26318 {17, ARM_ARCH_V8M_MAIN
},
26322 /* Set an attribute if it has not already been set by the user. */
26324 aeabi_set_attribute_int (int tag
, int value
)
26327 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26328 || !attributes_set_explicitly
[tag
])
26329 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26333 aeabi_set_attribute_string (int tag
, const char *value
)
26336 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26337 || !attributes_set_explicitly
[tag
])
26338 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26341 /* Set the public EABI object attributes. */
26343 aeabi_set_public_attributes (void)
26348 int fp16_optional
= 0;
26349 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26350 arm_feature_set flags
;
26351 arm_feature_set tmp
;
26352 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26353 const cpu_arch_ver_table
*p
;
26355 /* Choose the architecture based on the capabilities of the requested cpu
26356 (if any) and/or the instructions actually used. */
26357 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26358 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26359 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26361 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26362 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26364 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26365 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26367 selected_cpu
= flags
;
26369 /* Allow the user to override the reported architecture. */
26372 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26373 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26376 /* We need to make sure that the attributes do not identify us as v6S-M
26377 when the only v6S-M feature in use is the Operating System Extensions. */
26378 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26379 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26380 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26384 for (p
= cpu_arch_ver
; p
->val
; p
++)
26386 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26389 arm_arch
= p
->flags
;
26390 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26394 /* The table lookup above finds the last architecture to contribute
26395 a new feature. Unfortunately, Tag13 is a subset of the union of
26396 v6T2 and v7-M, so it is never seen as contributing a new feature.
26397 We can not search for the last entry which is entirely used,
26398 because if no CPU is specified we build up only those flags
26399 actually used. Perhaps we should separate out the specified
26400 and implicit cases. Avoid taking this path for -march=all by
26401 checking for contradictory v7-A / v7-M features. */
26402 if (arch
== TAG_CPU_ARCH_V7
26403 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26404 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26405 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26407 arch
= TAG_CPU_ARCH_V7E_M
;
26408 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26411 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26412 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26414 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26415 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26418 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26419 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26420 ARMv8-M, -march=all must be detected as ARMv8-A. */
26421 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26422 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26424 arch
= TAG_CPU_ARCH_V8
;
26425 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26428 /* Tag_CPU_name. */
26429 if (selected_cpu_name
[0])
26433 q
= selected_cpu_name
;
26434 if (strncmp (q
, "armv", 4) == 0)
26439 for (i
= 0; q
[i
]; i
++)
26440 q
[i
] = TOUPPER (q
[i
]);
26442 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26445 /* Tag_CPU_arch. */
26446 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26448 /* Tag_CPU_arch_profile. */
26449 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26450 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26451 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26452 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26454 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26456 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26461 if (profile
!= '\0')
26462 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26464 /* Tag_DSP_extension. */
26465 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26467 arm_feature_set ext
;
26469 /* DSP instructions not in architecture. */
26470 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26471 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26472 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26475 /* Tag_ARM_ISA_use. */
26476 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26478 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26480 /* Tag_THUMB_ISA_use. */
26481 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26486 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26487 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26489 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26493 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26496 /* Tag_VFP_arch. */
26497 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26498 aeabi_set_attribute_int (Tag_VFP_arch
,
26499 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26501 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26502 aeabi_set_attribute_int (Tag_VFP_arch
,
26503 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26505 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26508 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26510 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26512 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26515 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26516 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26517 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26518 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26519 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26521 /* Tag_ABI_HardFP_use. */
26522 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26523 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26524 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26526 /* Tag_WMMX_arch. */
26527 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26528 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26529 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26530 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26532 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26533 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26534 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26535 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26536 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26537 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26539 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26541 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26545 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26550 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26551 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26552 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26556 We set Tag_DIV_use to two when integer divide instructions have been used
26557 in ARM state, or when Thumb integer divide instructions have been used,
26558 but we have no architecture profile set, nor have we any ARM instructions.
26560 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26561 by the base architecture.
26563 For new architectures we will have to check these tests. */
26564 gas_assert (arch
<= TAG_CPU_ARCH_V8
26565 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26566 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26567 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26568 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26569 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26570 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26571 || (profile
== '\0'
26572 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26573 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26574 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26576 /* Tag_MP_extension_use. */
26577 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26578 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26580 /* Tag Virtualization_use. */
26581 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26583 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26586 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26589 /* Add the default contents for the .ARM.attributes section. */
26593 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26596 aeabi_set_public_attributes ();
26598 #endif /* OBJ_ELF */
26601 /* Parse a .cpu directive. */
26604 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26606 const struct arm_cpu_option_table
*opt
;
26610 name
= input_line_pointer
;
26611 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26612 input_line_pointer
++;
26613 saved_char
= *input_line_pointer
;
26614 *input_line_pointer
= 0;
26616 /* Skip the first "all" entry. */
26617 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26618 if (streq (opt
->name
, name
))
26620 mcpu_cpu_opt
= &opt
->value
;
26621 selected_cpu
= opt
->value
;
26622 if (opt
->canonical_name
)
26623 strcpy (selected_cpu_name
, opt
->canonical_name
);
26627 for (i
= 0; opt
->name
[i
]; i
++)
26628 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26630 selected_cpu_name
[i
] = 0;
26632 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26633 *input_line_pointer
= saved_char
;
26634 demand_empty_rest_of_line ();
26637 as_bad (_("unknown cpu `%s'"), name
);
26638 *input_line_pointer
= saved_char
;
26639 ignore_rest_of_line ();
26643 /* Parse a .arch directive. */
26646 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26648 const struct arm_arch_option_table
*opt
;
26652 name
= input_line_pointer
;
26653 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26654 input_line_pointer
++;
26655 saved_char
= *input_line_pointer
;
26656 *input_line_pointer
= 0;
26658 /* Skip the first "all" entry. */
26659 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26660 if (streq (opt
->name
, name
))
26662 mcpu_cpu_opt
= &opt
->value
;
26663 selected_cpu
= opt
->value
;
26664 strcpy (selected_cpu_name
, opt
->name
);
26665 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26666 *input_line_pointer
= saved_char
;
26667 demand_empty_rest_of_line ();
26671 as_bad (_("unknown architecture `%s'\n"), name
);
26672 *input_line_pointer
= saved_char
;
26673 ignore_rest_of_line ();
26677 /* Parse a .object_arch directive. */
26680 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26682 const struct arm_arch_option_table
*opt
;
26686 name
= input_line_pointer
;
26687 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26688 input_line_pointer
++;
26689 saved_char
= *input_line_pointer
;
26690 *input_line_pointer
= 0;
26692 /* Skip the first "all" entry. */
26693 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26694 if (streq (opt
->name
, name
))
26696 object_arch
= &opt
->value
;
26697 *input_line_pointer
= saved_char
;
26698 demand_empty_rest_of_line ();
26702 as_bad (_("unknown architecture `%s'\n"), name
);
26703 *input_line_pointer
= saved_char
;
26704 ignore_rest_of_line ();
26707 /* Parse a .arch_extension directive. */
26710 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26712 const struct arm_option_extension_value_table
*opt
;
26713 const arm_feature_set arm_any
= ARM_ANY
;
26716 int adding_value
= 1;
26718 name
= input_line_pointer
;
26719 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26720 input_line_pointer
++;
26721 saved_char
= *input_line_pointer
;
26722 *input_line_pointer
= 0;
26724 if (strlen (name
) >= 2
26725 && strncmp (name
, "no", 2) == 0)
26731 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26732 if (streq (opt
->name
, name
))
26734 int i
, nb_allowed_archs
=
26735 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26736 for (i
= 0; i
< nb_allowed_archs
; i
++)
26739 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26741 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26745 if (i
== nb_allowed_archs
)
26747 as_bad (_("architectural extension `%s' is not allowed for the "
26748 "current base architecture"), name
);
26753 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26756 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26758 mcpu_cpu_opt
= &selected_cpu
;
26759 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26760 *input_line_pointer
= saved_char
;
26761 demand_empty_rest_of_line ();
26765 if (opt
->name
== NULL
)
26766 as_bad (_("unknown architecture extension `%s'\n"), name
);
26768 *input_line_pointer
= saved_char
;
26769 ignore_rest_of_line ();
26772 /* Parse a .fpu directive. */
26775 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26777 const struct arm_option_fpu_value_table
*opt
;
26781 name
= input_line_pointer
;
26782 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26783 input_line_pointer
++;
26784 saved_char
= *input_line_pointer
;
26785 *input_line_pointer
= 0;
26787 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26788 if (streq (opt
->name
, name
))
26790 mfpu_opt
= &opt
->value
;
26791 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26792 *input_line_pointer
= saved_char
;
26793 demand_empty_rest_of_line ();
26797 as_bad (_("unknown floating point format `%s'\n"), name
);
26798 *input_line_pointer
= saved_char
;
26799 ignore_rest_of_line ();
26802 /* Copy symbol information. */
26805 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26807 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26811 /* Given a symbolic attribute NAME, return the proper integer value.
26812 Returns -1 if the attribute is not known. */
26815 arm_convert_symbolic_attribute (const char *name
)
26817 static const struct
26822 attribute_table
[] =
26824 /* When you modify this table you should
26825 also modify the list in doc/c-arm.texi. */
26826 #define T(tag) {#tag, tag}
26827 T (Tag_CPU_raw_name
),
26830 T (Tag_CPU_arch_profile
),
26831 T (Tag_ARM_ISA_use
),
26832 T (Tag_THUMB_ISA_use
),
26836 T (Tag_Advanced_SIMD_arch
),
26837 T (Tag_PCS_config
),
26838 T (Tag_ABI_PCS_R9_use
),
26839 T (Tag_ABI_PCS_RW_data
),
26840 T (Tag_ABI_PCS_RO_data
),
26841 T (Tag_ABI_PCS_GOT_use
),
26842 T (Tag_ABI_PCS_wchar_t
),
26843 T (Tag_ABI_FP_rounding
),
26844 T (Tag_ABI_FP_denormal
),
26845 T (Tag_ABI_FP_exceptions
),
26846 T (Tag_ABI_FP_user_exceptions
),
26847 T (Tag_ABI_FP_number_model
),
26848 T (Tag_ABI_align_needed
),
26849 T (Tag_ABI_align8_needed
),
26850 T (Tag_ABI_align_preserved
),
26851 T (Tag_ABI_align8_preserved
),
26852 T (Tag_ABI_enum_size
),
26853 T (Tag_ABI_HardFP_use
),
26854 T (Tag_ABI_VFP_args
),
26855 T (Tag_ABI_WMMX_args
),
26856 T (Tag_ABI_optimization_goals
),
26857 T (Tag_ABI_FP_optimization_goals
),
26858 T (Tag_compatibility
),
26859 T (Tag_CPU_unaligned_access
),
26860 T (Tag_FP_HP_extension
),
26861 T (Tag_VFP_HP_extension
),
26862 T (Tag_ABI_FP_16bit_format
),
26863 T (Tag_MPextension_use
),
26865 T (Tag_nodefaults
),
26866 T (Tag_also_compatible_with
),
26867 T (Tag_conformance
),
26869 T (Tag_Virtualization_use
),
26870 T (Tag_DSP_extension
),
26871 /* We deliberately do not include Tag_MPextension_use_legacy. */
26879 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26880 if (streq (name
, attribute_table
[i
].name
))
26881 return attribute_table
[i
].tag
;
26887 /* Apply sym value for relocations only in the case that they are for
26888 local symbols in the same segment as the fixup and you have the
26889 respective architectural feature for blx and simple switches. */
26891 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26894 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26895 /* PR 17444: If the local symbol is in a different section then a reloc
26896 will always be generated for it, so applying the symbol value now
26897 will result in a double offset being stored in the relocation. */
26898 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26901 switch (fixP
->fx_r_type
)
26903 case BFD_RELOC_ARM_PCREL_BLX
:
26904 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26905 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26909 case BFD_RELOC_ARM_PCREL_CALL
:
26910 case BFD_RELOC_THUMB_PCREL_BLX
:
26911 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26922 #endif /* OBJ_ELF */