1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
146 static int fix_v4bx
= FALSE
;
148 /* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
151 static const arm_feature_set
*legacy_cpu
= NULL
;
152 static const arm_feature_set
*legacy_fpu
= NULL
;
154 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
155 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
156 static const arm_feature_set
*march_cpu_opt
= NULL
;
157 static const arm_feature_set
*march_fpu_opt
= NULL
;
158 static const arm_feature_set
*mfpu_opt
= NULL
;
159 static const arm_feature_set
*object_arch
= NULL
;
161 /* Constants for known architecture features. */
162 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
163 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
164 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
165 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
166 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
167 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
168 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
169 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
170 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
173 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
176 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
179 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
180 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
181 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
182 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
183 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v4t_5
=
185 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
186 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
187 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
188 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
189 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
190 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
191 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
192 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
193 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
194 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
195 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
196 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
197 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
198 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
199 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
221 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
222 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
223 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
225 static int mfloat_abi_opt
= -1;
226 /* Record user cpu selection for object attributes. */
227 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
228 /* Must be long enough to hold any of the names in arm_cpus. */
229 static char selected_cpu_name
[16];
232 static int meabi_flags
= EABI_DEFAULT
;
234 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
240 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
245 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
246 symbolS
* GOT_symbol
;
249 /* 0: assemble for ARM,
250 1: assemble for Thumb,
251 2: assemble for Thumb even though target CPU does not support thumb
253 static int thumb_mode
= 0;
255 /* If unified_syntax is true, we are processing the new unified
256 ARM/Thumb syntax. Important differences from the old ARM mode:
258 - Immediate operands do not require a # prefix.
259 - Conditional affixes always appear at the end of the
260 instruction. (For backward compatibility, those instructions
261 that formerly had them in the middle, continue to accept them
263 - The IT instruction may appear, and if it does is validated
264 against subsequent conditional affixes. It does not generate
267 Important differences from the old Thumb mode:
269 - Immediate operands do not require a # prefix.
270 - Most of the V6T2 instructions are only available in unified mode.
271 - The .N and .W suffixes are recognized and honored (it is an error
272 if they cannot be honored).
273 - All instructions set the flags if and only if they have an 's' affix.
274 - Conditional affixes may be used. They are validated against
275 preceding IT instructions. Unlike ARM mode, you cannot use a
276 conditional affix except in the scope of an IT instruction. */
278 static bfd_boolean unified_syntax
= FALSE
;
293 enum neon_el_type type
;
297 #define NEON_MAX_TYPE_ELS 4
301 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
308 unsigned long instruction
;
312 /* "uncond_value" is set to the value in place of the conditional field in
313 unconditional versions of the instruction, or -1 if nothing is
316 struct neon_type vectype
;
317 /* Set to the opcode if the instruction needs relaxation.
318 Zero if the instruction is not relaxed. */
322 bfd_reloc_code_real_type type
;
331 struct neon_type_el vectype
;
332 unsigned present
: 1; /* Operand present. */
333 unsigned isreg
: 1; /* Operand was a register. */
334 unsigned immisreg
: 1; /* .imm field is a second register. */
335 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
336 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
337 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
338 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
339 instructions. This allows us to disambiguate ARM <-> vector insns. */
340 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
341 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
342 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
343 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
344 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
345 unsigned writeback
: 1; /* Operand has trailing ! */
346 unsigned preind
: 1; /* Preindexed address. */
347 unsigned postind
: 1; /* Postindexed address. */
348 unsigned negative
: 1; /* Index register was negated. */
349 unsigned shifted
: 1; /* Shift applied to operation. */
350 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
354 static struct arm_it inst
;
356 #define NUM_FLOAT_VALS 8
358 const char * fp_const
[] =
360 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
363 /* Number of littlenums required to hold an extended precision number. */
364 #define MAX_LITTLENUMS 6
366 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
376 #define CP_T_X 0x00008000
377 #define CP_T_Y 0x00400000
379 #define CONDS_BIT 0x00100000
380 #define LOAD_BIT 0x00100000
382 #define DOUBLE_LOAD_FLAG 0x00000001
386 const char * template;
390 #define COND_ALWAYS 0xE
394 const char *template;
398 struct asm_barrier_opt
400 const char *template;
404 /* The bit that distinguishes CPSR and SPSR. */
405 #define SPSR_BIT (1 << 22)
407 /* The individual PSR flag bits. */
408 #define PSR_c (1 << 16)
409 #define PSR_x (1 << 17)
410 #define PSR_s (1 << 18)
411 #define PSR_f (1 << 19)
416 bfd_reloc_code_real_type reloc
;
421 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
422 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
427 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
430 /* Bits for DEFINED field in neon_typed_alias. */
431 #define NTA_HASTYPE 1
432 #define NTA_HASINDEX 2
434 struct neon_typed_alias
436 unsigned char defined
;
438 struct neon_type_el eltype
;
441 /* ARM register categories. This includes coprocessor numbers and various
442 architecture extensions' registers. */
468 /* Structure for a hash table entry for a register.
469 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
470 information which states whether a vector type or index is specified (for a
471 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
475 unsigned char number
;
477 unsigned char builtin
;
478 struct neon_typed_alias
*neon
;
481 /* Diagnostics used when we don't get a register of the expected type. */
482 const char *const reg_expected_msgs
[] =
484 N_("ARM register expected"),
485 N_("bad or missing co-processor number"),
486 N_("co-processor register expected"),
487 N_("FPA register expected"),
488 N_("VFP single precision register expected"),
489 N_("VFP/Neon double precision register expected"),
490 N_("Neon quad precision register expected"),
491 N_("VFP single or double precision register expected"),
492 N_("Neon double or quad precision register expected"),
493 N_("VFP single, double or Neon quad precision register expected"),
494 N_("VFP system register expected"),
495 N_("Maverick MVF register expected"),
496 N_("Maverick MVD register expected"),
497 N_("Maverick MVFX register expected"),
498 N_("Maverick MVDX register expected"),
499 N_("Maverick MVAX register expected"),
500 N_("Maverick DSPSC register expected"),
501 N_("iWMMXt data register expected"),
502 N_("iWMMXt control register expected"),
503 N_("iWMMXt scalar register expected"),
504 N_("XScale accumulator register expected"),
507 /* Some well known registers that we refer to directly elsewhere. */
512 /* ARM instructions take 4bytes in the object file, Thumb instructions
518 /* Basic string to match. */
519 const char *template;
521 /* Parameters to instruction. */
522 unsigned char operands
[8];
524 /* Conditional tag - see opcode_lookup. */
525 unsigned int tag
: 4;
527 /* Basic instruction code. */
528 unsigned int avalue
: 28;
530 /* Thumb-format instruction code. */
533 /* Which architecture variant provides this instruction. */
534 const arm_feature_set
*avariant
;
535 const arm_feature_set
*tvariant
;
537 /* Function to call to encode instruction in ARM format. */
538 void (* aencode
) (void);
540 /* Function to call to encode instruction in Thumb format. */
541 void (* tencode
) (void);
544 /* Defines for various bits that we will want to toggle. */
545 #define INST_IMMEDIATE 0x02000000
546 #define OFFSET_REG 0x02000000
547 #define HWOFFSET_IMM 0x00400000
548 #define SHIFT_BY_REG 0x00000010
549 #define PRE_INDEX 0x01000000
550 #define INDEX_UP 0x00800000
551 #define WRITE_BACK 0x00200000
552 #define LDM_TYPE_2_OR_3 0x00400000
553 #define CPSI_MMOD 0x00020000
555 #define LITERAL_MASK 0xf000f000
556 #define OPCODE_MASK 0xfe1fffff
557 #define V4_STR_BIT 0x00000020
559 #define T2_SUBS_PC_LR 0xf3de8f00
561 #define DATA_OP_SHIFT 21
563 #define T2_OPCODE_MASK 0xfe1fffff
564 #define T2_DATA_OP_SHIFT 21
566 /* Codes to distinguish the arithmetic instructions. */
577 #define OPCODE_CMP 10
578 #define OPCODE_CMN 11
579 #define OPCODE_ORR 12
580 #define OPCODE_MOV 13
581 #define OPCODE_BIC 14
582 #define OPCODE_MVN 15
584 #define T2_OPCODE_AND 0
585 #define T2_OPCODE_BIC 1
586 #define T2_OPCODE_ORR 2
587 #define T2_OPCODE_ORN 3
588 #define T2_OPCODE_EOR 4
589 #define T2_OPCODE_ADD 8
590 #define T2_OPCODE_ADC 10
591 #define T2_OPCODE_SBC 11
592 #define T2_OPCODE_SUB 13
593 #define T2_OPCODE_RSB 14
595 #define T_OPCODE_MUL 0x4340
596 #define T_OPCODE_TST 0x4200
597 #define T_OPCODE_CMN 0x42c0
598 #define T_OPCODE_NEG 0x4240
599 #define T_OPCODE_MVN 0x43c0
601 #define T_OPCODE_ADD_R3 0x1800
602 #define T_OPCODE_SUB_R3 0x1a00
603 #define T_OPCODE_ADD_HI 0x4400
604 #define T_OPCODE_ADD_ST 0xb000
605 #define T_OPCODE_SUB_ST 0xb080
606 #define T_OPCODE_ADD_SP 0xa800
607 #define T_OPCODE_ADD_PC 0xa000
608 #define T_OPCODE_ADD_I8 0x3000
609 #define T_OPCODE_SUB_I8 0x3800
610 #define T_OPCODE_ADD_I3 0x1c00
611 #define T_OPCODE_SUB_I3 0x1e00
613 #define T_OPCODE_ASR_R 0x4100
614 #define T_OPCODE_LSL_R 0x4080
615 #define T_OPCODE_LSR_R 0x40c0
616 #define T_OPCODE_ROR_R 0x41c0
617 #define T_OPCODE_ASR_I 0x1000
618 #define T_OPCODE_LSL_I 0x0000
619 #define T_OPCODE_LSR_I 0x0800
621 #define T_OPCODE_MOV_I8 0x2000
622 #define T_OPCODE_CMP_I8 0x2800
623 #define T_OPCODE_CMP_LR 0x4280
624 #define T_OPCODE_MOV_HR 0x4600
625 #define T_OPCODE_CMP_HR 0x4500
627 #define T_OPCODE_LDR_PC 0x4800
628 #define T_OPCODE_LDR_SP 0x9800
629 #define T_OPCODE_STR_SP 0x9000
630 #define T_OPCODE_LDR_IW 0x6800
631 #define T_OPCODE_STR_IW 0x6000
632 #define T_OPCODE_LDR_IH 0x8800
633 #define T_OPCODE_STR_IH 0x8000
634 #define T_OPCODE_LDR_IB 0x7800
635 #define T_OPCODE_STR_IB 0x7000
636 #define T_OPCODE_LDR_RW 0x5800
637 #define T_OPCODE_STR_RW 0x5000
638 #define T_OPCODE_LDR_RH 0x5a00
639 #define T_OPCODE_STR_RH 0x5200
640 #define T_OPCODE_LDR_RB 0x5c00
641 #define T_OPCODE_STR_RB 0x5400
643 #define T_OPCODE_PUSH 0xb400
644 #define T_OPCODE_POP 0xbc00
646 #define T_OPCODE_BRANCH 0xe000
648 #define THUMB_SIZE 2 /* Size of thumb instruction. */
649 #define THUMB_PP_PC_LR 0x0100
650 #define THUMB_LOAD_BIT 0x0800
651 #define THUMB2_LOAD_BIT 0x00100000
653 #define BAD_ARGS _("bad arguments to instruction")
654 #define BAD_PC _("r15 not allowed here")
655 #define BAD_COND _("instruction cannot be conditional")
656 #define BAD_OVERLAP _("registers may not be the same")
657 #define BAD_HIREG _("lo register required")
658 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
659 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
660 #define BAD_BRANCH _("branch must be last instruction in IT block")
661 #define BAD_NOT_IT _("instruction not allowed in IT block")
662 #define BAD_FPU _("selected FPU does not support instruction")
664 static struct hash_control
*arm_ops_hsh
;
665 static struct hash_control
*arm_cond_hsh
;
666 static struct hash_control
*arm_shift_hsh
;
667 static struct hash_control
*arm_psr_hsh
;
668 static struct hash_control
*arm_v7m_psr_hsh
;
669 static struct hash_control
*arm_reg_hsh
;
670 static struct hash_control
*arm_reloc_hsh
;
671 static struct hash_control
*arm_barrier_opt_hsh
;
673 /* Stuff needed to resolve the label ambiguity
682 symbolS
* last_label_seen
;
683 static int label_is_thumb_function_name
= FALSE
;
685 /* Literal pool structure. Held on a per-section
686 and per-sub-section basis. */
688 #define MAX_LITERAL_POOL_SIZE 1024
689 typedef struct literal_pool
691 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
692 unsigned int next_free_entry
;
697 struct literal_pool
* next
;
700 /* Pointer to a linked list of literal pools. */
701 literal_pool
* list_of_pools
= NULL
;
703 /* State variables for IT block handling. */
704 static bfd_boolean current_it_mask
= 0;
705 static int current_cc
;
709 /* This array holds the chars that always start a comment. If the
710 pre-processor is disabled, these aren't very useful. */
711 const char comment_chars
[] = "@";
713 /* This array holds the chars that only start a comment at the beginning of
714 a line. If the line seems to have the form '# 123 filename'
715 .line and .file directives will appear in the pre-processed output. */
716 /* Note that input_file.c hand checks for '#' at the beginning of the
717 first line of the input file. This is because the compiler outputs
718 #NO_APP at the beginning of its output. */
719 /* Also note that comments like this one will always work. */
720 const char line_comment_chars
[] = "#";
722 const char line_separator_chars
[] = ";";
724 /* Chars that can be used to separate mant
725 from exp in floating point numbers. */
726 const char EXP_CHARS
[] = "eE";
728 /* Chars that mean this number is a floating point constant. */
732 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
734 /* Prefix characters that indicate the start of an immediate
736 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
738 /* Separator character handling. */
740 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
743 skip_past_char (char ** str
, char c
)
753 #define skip_past_comma(str) skip_past_char (str, ',')
755 /* Arithmetic expressions (possibly involving symbols). */
757 /* Return TRUE if anything in the expression is a bignum. */
760 walk_no_bignums (symbolS
* sp
)
762 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
765 if (symbol_get_value_expression (sp
)->X_add_symbol
)
767 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
768 || (symbol_get_value_expression (sp
)->X_op_symbol
769 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
775 static int in_my_get_expression
= 0;
777 /* Third argument to my_get_expression. */
778 #define GE_NO_PREFIX 0
779 #define GE_IMM_PREFIX 1
780 #define GE_OPT_PREFIX 2
781 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
782 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
783 #define GE_OPT_PREFIX_BIG 3
786 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
791 /* In unified syntax, all prefixes are optional. */
793 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
798 case GE_NO_PREFIX
: break;
800 if (!is_immediate_prefix (**str
))
802 inst
.error
= _("immediate expression requires a # prefix");
808 case GE_OPT_PREFIX_BIG
:
809 if (is_immediate_prefix (**str
))
815 memset (ep
, 0, sizeof (expressionS
));
817 save_in
= input_line_pointer
;
818 input_line_pointer
= *str
;
819 in_my_get_expression
= 1;
820 seg
= expression (ep
);
821 in_my_get_expression
= 0;
823 if (ep
->X_op
== O_illegal
)
825 /* We found a bad expression in md_operand(). */
826 *str
= input_line_pointer
;
827 input_line_pointer
= save_in
;
828 if (inst
.error
== NULL
)
829 inst
.error
= _("bad expression");
834 if (seg
!= absolute_section
835 && seg
!= text_section
836 && seg
!= data_section
837 && seg
!= bss_section
838 && seg
!= undefined_section
)
840 inst
.error
= _("bad segment");
841 *str
= input_line_pointer
;
842 input_line_pointer
= save_in
;
847 /* Get rid of any bignums now, so that we don't generate an error for which
848 we can't establish a line number later on. Big numbers are never valid
849 in instructions, which is where this routine is always called. */
850 if (prefix_mode
!= GE_OPT_PREFIX_BIG
851 && (ep
->X_op
== O_big
853 && (walk_no_bignums (ep
->X_add_symbol
)
855 && walk_no_bignums (ep
->X_op_symbol
))))))
857 inst
.error
= _("invalid constant");
858 *str
= input_line_pointer
;
859 input_line_pointer
= save_in
;
863 *str
= input_line_pointer
;
864 input_line_pointer
= save_in
;
868 /* Turn a string in input_line_pointer into a floating point constant
869 of type TYPE, and store the appropriate bytes in *LITP. The number
870 of LITTLENUMS emitted is stored in *SIZEP. An error message is
871 returned, or NULL on OK.
873 Note that fp constants aren't represent in the normal way on the ARM.
874 In big endian mode, things are as expected. However, in little endian
875 mode fp constants are big-endian word-wise, and little-endian byte-wise
876 within the words. For example, (double) 1.1 in big endian mode is
877 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
878 the byte sequence 99 99 f1 3f 9a 99 99 99.
880 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
883 md_atof (int type
, char * litP
, int * sizeP
)
886 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
918 return _("Unrecognized or unsupported floating point constant");
921 t
= atof_ieee (input_line_pointer
, type
, words
);
923 input_line_pointer
= t
;
924 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
926 if (target_big_endian
)
928 for (i
= 0; i
< prec
; i
++)
930 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
931 litP
+= sizeof (LITTLENUM_TYPE
);
936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
937 for (i
= prec
- 1; i
>= 0; i
--)
939 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
940 litP
+= sizeof (LITTLENUM_TYPE
);
943 /* For a 4 byte float the order of elements in `words' is 1 0.
944 For an 8 byte float the order is 1 0 3 2. */
945 for (i
= 0; i
< prec
; i
+= 2)
947 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
948 sizeof (LITTLENUM_TYPE
));
949 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
950 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
951 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
958 /* We handle all bad expressions here, so that we can report the faulty
959 instruction in the error message. */
961 md_operand (expressionS
* expr
)
963 if (in_my_get_expression
)
964 expr
->X_op
= O_illegal
;
967 /* Immediate values. */
969 /* Generic immediate-value read function for use in directives.
970 Accepts anything that 'expression' can fold to a constant.
971 *val receives the number. */
974 immediate_for_directive (int *val
)
977 exp
.X_op
= O_illegal
;
979 if (is_immediate_prefix (*input_line_pointer
))
981 input_line_pointer
++;
985 if (exp
.X_op
!= O_constant
)
987 as_bad (_("expected #constant"));
988 ignore_rest_of_line ();
991 *val
= exp
.X_add_number
;
996 /* Register parsing. */
998 /* Generic register parser. CCP points to what should be the
999 beginning of a register name. If it is indeed a valid register
1000 name, advance CCP over it and return the reg_entry structure;
1001 otherwise return NULL. Does not issue diagnostics. */
1003 static struct reg_entry
*
1004 arm_reg_parse_multi (char **ccp
)
1008 struct reg_entry
*reg
;
1010 #ifdef REGISTER_PREFIX
1011 if (*start
!= REGISTER_PREFIX
)
1015 #ifdef OPTIONAL_REGISTER_PREFIX
1016 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1021 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1026 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1028 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1038 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1039 enum arm_reg_type type
)
1041 /* Alternative syntaxes are accepted for a few register classes. */
1048 /* Generic coprocessor register names are allowed for these. */
1049 if (reg
&& reg
->type
== REG_TYPE_CN
)
1054 /* For backward compatibility, a bare number is valid here. */
1056 unsigned long processor
= strtoul (start
, ccp
, 10);
1057 if (*ccp
!= start
&& processor
<= 15)
1061 case REG_TYPE_MMXWC
:
1062 /* WC includes WCG. ??? I'm not sure this is true for all
1063 instructions that take WC registers. */
1064 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1075 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1076 return value is the register number or FAIL. */
1079 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1082 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1085 /* Do not allow a scalar (reg+index) to parse as a register. */
1086 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1089 if (reg
&& reg
->type
== type
)
1092 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1099 /* Parse a Neon type specifier. *STR should point at the leading '.'
1100 character. Does no verification at this stage that the type fits the opcode
1107 Can all be legally parsed by this function.
1109 Fills in neon_type struct pointer with parsed information, and updates STR
1110 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1111 type, FAIL if not. */
1114 parse_neon_type (struct neon_type
*type
, char **str
)
1121 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1123 enum neon_el_type thistype
= NT_untyped
;
1124 unsigned thissize
= -1u;
1131 /* Just a size without an explicit type. */
1135 switch (TOLOWER (*ptr
))
1137 case 'i': thistype
= NT_integer
; break;
1138 case 'f': thistype
= NT_float
; break;
1139 case 'p': thistype
= NT_poly
; break;
1140 case 's': thistype
= NT_signed
; break;
1141 case 'u': thistype
= NT_unsigned
; break;
1143 thistype
= NT_float
;
1148 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1154 /* .f is an abbreviation for .f32. */
1155 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1160 thissize
= strtoul (ptr
, &ptr
, 10);
1162 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1165 as_bad (_("bad size %d in type specifier"), thissize
);
1173 type
->el
[type
->elems
].type
= thistype
;
1174 type
->el
[type
->elems
].size
= thissize
;
1179 /* Empty/missing type is not a successful parse. */
1180 if (type
->elems
== 0)
1188 /* Errors may be set multiple times during parsing or bit encoding
1189 (particularly in the Neon bits), but usually the earliest error which is set
1190 will be the most meaningful. Avoid overwriting it with later (cascading)
1191 errors by calling this function. */
1194 first_error (const char *err
)
1200 /* Parse a single type, e.g. ".s32", leading period included. */
1202 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1205 struct neon_type optype
;
1209 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1211 if (optype
.elems
== 1)
1212 *vectype
= optype
.el
[0];
1215 first_error (_("only one type should be specified for operand"));
1221 first_error (_("vector type expected"));
1233 /* Special meanings for indices (which have a range of 0-7), which will fit into
1236 #define NEON_ALL_LANES 15
1237 #define NEON_INTERLEAVE_LANES 14
1239 /* Parse either a register or a scalar, with an optional type. Return the
1240 register number, and optionally fill in the actual type of the register
1241 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1242 type/index information in *TYPEINFO. */
1245 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1246 enum arm_reg_type
*rtype
,
1247 struct neon_typed_alias
*typeinfo
)
1250 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1251 struct neon_typed_alias atype
;
1252 struct neon_type_el parsetype
;
1256 atype
.eltype
.type
= NT_invtype
;
1257 atype
.eltype
.size
= -1;
1259 /* Try alternate syntax for some types of register. Note these are mutually
1260 exclusive with the Neon syntax extensions. */
1263 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1271 /* Undo polymorphism when a set of register types may be accepted. */
1272 if ((type
== REG_TYPE_NDQ
1273 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1274 || (type
== REG_TYPE_VFSD
1275 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1276 || (type
== REG_TYPE_NSDQ
1277 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1278 || reg
->type
== REG_TYPE_NQ
))
1279 || (type
== REG_TYPE_MMXWC
1280 && (reg
->type
== REG_TYPE_MMXWCG
)))
1283 if (type
!= reg
->type
)
1289 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1291 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1293 first_error (_("can't redefine type for operand"));
1296 atype
.defined
|= NTA_HASTYPE
;
1297 atype
.eltype
= parsetype
;
1300 if (skip_past_char (&str
, '[') == SUCCESS
)
1302 if (type
!= REG_TYPE_VFD
)
1304 first_error (_("only D registers may be indexed"));
1308 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1310 first_error (_("can't change index for operand"));
1314 atype
.defined
|= NTA_HASINDEX
;
1316 if (skip_past_char (&str
, ']') == SUCCESS
)
1317 atype
.index
= NEON_ALL_LANES
;
1322 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1324 if (exp
.X_op
!= O_constant
)
1326 first_error (_("constant expression required"));
1330 if (skip_past_char (&str
, ']') == FAIL
)
1333 atype
.index
= exp
.X_add_number
;
1348 /* Like arm_reg_parse, but allow allow the following extra features:
1349 - If RTYPE is non-zero, return the (possibly restricted) type of the
1350 register (e.g. Neon double or quad reg when either has been requested).
1351 - If this is a Neon vector type with additional type information, fill
1352 in the struct pointed to by VECTYPE (if non-NULL).
1353 This function will fault on encountering a scalar. */
1356 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1357 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1359 struct neon_typed_alias atype
;
1361 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1366 /* Do not allow a scalar (reg+index) to parse as a register. */
1367 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1369 first_error (_("register operand expected, but got scalar"));
1374 *vectype
= atype
.eltype
;
1381 #define NEON_SCALAR_REG(X) ((X) >> 4)
1382 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1384 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1385 have enough information to be able to do a good job bounds-checking. So, we
1386 just do easy checks here, and do further checks later. */
1389 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1393 struct neon_typed_alias atype
;
1395 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1397 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1400 if (atype
.index
== NEON_ALL_LANES
)
1402 first_error (_("scalar must have an index"));
1405 else if (atype
.index
>= 64 / elsize
)
1407 first_error (_("scalar index out of range"));
1412 *type
= atype
.eltype
;
1416 return reg
* 16 + atype
.index
;
1419 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1421 parse_reg_list (char ** strp
)
1423 char * str
= * strp
;
1427 /* We come back here if we get ranges concatenated by '+' or '|'. */
1442 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1444 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1454 first_error (_("bad range in register list"));
1458 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1460 if (range
& (1 << i
))
1462 (_("Warning: duplicated register (r%d) in register list"),
1470 if (range
& (1 << reg
))
1471 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1473 else if (reg
<= cur_reg
)
1474 as_tsktsk (_("Warning: register range not in ascending order"));
1479 while (skip_past_comma (&str
) != FAIL
1480 || (in_range
= 1, *str
++ == '-'));
1485 first_error (_("missing `}'"));
1493 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1496 if (expr
.X_op
== O_constant
)
1498 if (expr
.X_add_number
1499 != (expr
.X_add_number
& 0x0000ffff))
1501 inst
.error
= _("invalid register mask");
1505 if ((range
& expr
.X_add_number
) != 0)
1507 int regno
= range
& expr
.X_add_number
;
1510 regno
= (1 << regno
) - 1;
1512 (_("Warning: duplicated register (r%d) in register list"),
1516 range
|= expr
.X_add_number
;
1520 if (inst
.reloc
.type
!= 0)
1522 inst
.error
= _("expression too complex");
1526 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1527 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1528 inst
.reloc
.pc_rel
= 0;
1532 if (*str
== '|' || *str
== '+')
1538 while (another_range
);
1544 /* Types of registers in a list. */
1553 /* Parse a VFP register list. If the string is invalid return FAIL.
1554 Otherwise return the number of registers, and set PBASE to the first
1555 register. Parses registers of type ETYPE.
1556 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1557 - Q registers can be used to specify pairs of D registers
1558 - { } can be omitted from around a singleton register list
1559 FIXME: This is not implemented, as it would require backtracking in
1562 This could be done (the meaning isn't really ambiguous), but doesn't
1563 fit in well with the current parsing framework.
1564 - 32 D registers may be used (also true for VFPv3).
1565 FIXME: Types are ignored in these register lists, which is probably a
1569 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1574 enum arm_reg_type regtype
= 0;
1578 unsigned long mask
= 0;
1583 inst
.error
= _("expecting {");
1592 regtype
= REG_TYPE_VFS
;
1597 regtype
= REG_TYPE_VFD
;
1600 case REGLIST_NEON_D
:
1601 regtype
= REG_TYPE_NDQ
;
1605 if (etype
!= REGLIST_VFP_S
)
1607 /* VFPv3 allows 32 D registers. */
1608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1612 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1615 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1622 base_reg
= max_regs
;
1626 int setmask
= 1, addregs
= 1;
1628 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1630 if (new_base
== FAIL
)
1632 first_error (_(reg_expected_msgs
[regtype
]));
1636 if (new_base
>= max_regs
)
1638 first_error (_("register out of range in list"));
1642 /* Note: a value of 2 * n is returned for the register Q<n>. */
1643 if (regtype
== REG_TYPE_NQ
)
1649 if (new_base
< base_reg
)
1650 base_reg
= new_base
;
1652 if (mask
& (setmask
<< new_base
))
1654 first_error (_("invalid register list"));
1658 if ((mask
>> new_base
) != 0 && ! warned
)
1660 as_tsktsk (_("register list not in ascending order"));
1664 mask
|= setmask
<< new_base
;
1667 if (*str
== '-') /* We have the start of a range expression */
1673 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1676 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1680 if (high_range
>= max_regs
)
1682 first_error (_("register out of range in list"));
1686 if (regtype
== REG_TYPE_NQ
)
1687 high_range
= high_range
+ 1;
1689 if (high_range
<= new_base
)
1691 inst
.error
= _("register range not in ascending order");
1695 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1697 if (mask
& (setmask
<< new_base
))
1699 inst
.error
= _("invalid register list");
1703 mask
|= setmask
<< new_base
;
1708 while (skip_past_comma (&str
) != FAIL
);
1712 /* Sanity check -- should have raised a parse error above. */
1713 if (count
== 0 || count
> max_regs
)
1718 /* Final test -- the registers must be consecutive. */
1720 for (i
= 0; i
< count
; i
++)
1722 if ((mask
& (1u << i
)) == 0)
1724 inst
.error
= _("non-contiguous register range");
1734 /* True if two alias types are the same. */
1737 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1745 if (a
->defined
!= b
->defined
)
1748 if ((a
->defined
& NTA_HASTYPE
) != 0
1749 && (a
->eltype
.type
!= b
->eltype
.type
1750 || a
->eltype
.size
!= b
->eltype
.size
))
1753 if ((a
->defined
& NTA_HASINDEX
) != 0
1754 && (a
->index
!= b
->index
))
1760 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1761 The base register is put in *PBASE.
1762 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1764 The register stride (minus one) is put in bit 4 of the return value.
1765 Bits [6:5] encode the list length (minus one).
1766 The type of the list elements is put in *ELTYPE, if non-NULL. */
1768 #define NEON_LANE(X) ((X) & 0xf)
1769 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1770 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1773 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1774 struct neon_type_el
*eltype
)
1781 int leading_brace
= 0;
1782 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1784 const char *const incr_error
= "register stride must be 1 or 2";
1785 const char *const type_error
= "mismatched element/structure types in list";
1786 struct neon_typed_alias firsttype
;
1788 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1793 struct neon_typed_alias atype
;
1794 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1798 first_error (_(reg_expected_msgs
[rtype
]));
1805 if (rtype
== REG_TYPE_NQ
)
1812 else if (reg_incr
== -1)
1814 reg_incr
= getreg
- base_reg
;
1815 if (reg_incr
< 1 || reg_incr
> 2)
1817 first_error (_(incr_error
));
1821 else if (getreg
!= base_reg
+ reg_incr
* count
)
1823 first_error (_(incr_error
));
1827 if (!neon_alias_types_same (&atype
, &firsttype
))
1829 first_error (_(type_error
));
1833 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1837 struct neon_typed_alias htype
;
1838 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1840 lane
= NEON_INTERLEAVE_LANES
;
1841 else if (lane
!= NEON_INTERLEAVE_LANES
)
1843 first_error (_(type_error
));
1848 else if (reg_incr
!= 1)
1850 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1854 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1857 first_error (_(reg_expected_msgs
[rtype
]));
1860 if (!neon_alias_types_same (&htype
, &firsttype
))
1862 first_error (_(type_error
));
1865 count
+= hireg
+ dregs
- getreg
;
1869 /* If we're using Q registers, we can't use [] or [n] syntax. */
1870 if (rtype
== REG_TYPE_NQ
)
1876 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1880 else if (lane
!= atype
.index
)
1882 first_error (_(type_error
));
1886 else if (lane
== -1)
1887 lane
= NEON_INTERLEAVE_LANES
;
1888 else if (lane
!= NEON_INTERLEAVE_LANES
)
1890 first_error (_(type_error
));
1895 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1897 /* No lane set by [x]. We must be interleaving structures. */
1899 lane
= NEON_INTERLEAVE_LANES
;
1902 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1903 || (count
> 1 && reg_incr
== -1))
1905 first_error (_("error parsing element/structure list"));
1909 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1911 first_error (_("expected }"));
1919 *eltype
= firsttype
.eltype
;
1924 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1927 /* Parse an explicit relocation suffix on an expression. This is
1928 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1929 arm_reloc_hsh contains no entries, so this function can only
1930 succeed if there is no () after the word. Returns -1 on error,
1931 BFD_RELOC_UNUSED if there wasn't any suffix. */
1933 parse_reloc (char **str
)
1935 struct reloc_entry
*r
;
1939 return BFD_RELOC_UNUSED
;
1944 while (*q
&& *q
!= ')' && *q
!= ',')
1949 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1956 /* Directives: register aliases. */
1958 static struct reg_entry
*
1959 insert_reg_alias (char *str
, int number
, int type
)
1961 struct reg_entry
*new;
1964 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1967 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1969 /* Only warn about a redefinition if it's not defined as the
1971 else if (new->number
!= number
|| new->type
!= type
)
1972 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1977 name
= xstrdup (str
);
1978 new = xmalloc (sizeof (struct reg_entry
));
1981 new->number
= number
;
1983 new->builtin
= FALSE
;
1986 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1993 insert_neon_reg_alias (char *str
, int number
, int type
,
1994 struct neon_typed_alias
*atype
)
1996 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2000 first_error (_("attempt to redefine typed alias"));
2006 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2007 *reg
->neon
= *atype
;
2011 /* Look for the .req directive. This is of the form:
2013 new_register_name .req existing_register_name
2015 If we find one, or if it looks sufficiently like one that we want to
2016 handle any error here, return TRUE. Otherwise return FALSE. */
2019 create_register_alias (char * newname
, char *p
)
2021 struct reg_entry
*old
;
2022 char *oldname
, *nbuf
;
2025 /* The input scrubber ensures that whitespace after the mnemonic is
2026 collapsed to single spaces. */
2028 if (strncmp (oldname
, " .req ", 6) != 0)
2032 if (*oldname
== '\0')
2035 old
= hash_find (arm_reg_hsh
, oldname
);
2038 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2042 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2043 the desired alias name, and p points to its end. If not, then
2044 the desired alias name is in the global original_case_string. */
2045 #ifdef TC_CASE_SENSITIVE
2048 newname
= original_case_string
;
2049 nlen
= strlen (newname
);
2052 nbuf
= alloca (nlen
+ 1);
2053 memcpy (nbuf
, newname
, nlen
);
2056 /* Create aliases under the new name as stated; an all-lowercase
2057 version of the new name; and an all-uppercase version of the new
2059 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2061 for (p
= nbuf
; *p
; p
++)
2064 if (strncmp (nbuf
, newname
, nlen
))
2066 /* If this attempt to create an additional alias fails, do not bother
2067 trying to create the all-lower case alias. We will fail and issue
2068 a second, duplicate error message. This situation arises when the
2069 programmer does something like:
2072 The second .req creates the "Foo" alias but then fails to create
2073 the artificial FOO alias because it has already been created by the
2075 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2079 for (p
= nbuf
; *p
; p
++)
2082 if (strncmp (nbuf
, newname
, nlen
))
2083 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2089 /* Create a Neon typed/indexed register alias using directives, e.g.:
2094 These typed registers can be used instead of the types specified after the
2095 Neon mnemonic, so long as all operands given have types. Types can also be
2096 specified directly, e.g.:
2097 vadd d0.s32, d1.s32, d2.s32 */
2100 create_neon_reg_alias (char *newname
, char *p
)
2102 enum arm_reg_type basetype
;
2103 struct reg_entry
*basereg
;
2104 struct reg_entry mybasereg
;
2105 struct neon_type ntype
;
2106 struct neon_typed_alias typeinfo
;
2107 char *namebuf
, *nameend
;
2110 typeinfo
.defined
= 0;
2111 typeinfo
.eltype
.type
= NT_invtype
;
2112 typeinfo
.eltype
.size
= -1;
2113 typeinfo
.index
= -1;
2117 if (strncmp (p
, " .dn ", 5) == 0)
2118 basetype
= REG_TYPE_VFD
;
2119 else if (strncmp (p
, " .qn ", 5) == 0)
2120 basetype
= REG_TYPE_NQ
;
2129 basereg
= arm_reg_parse_multi (&p
);
2131 if (basereg
&& basereg
->type
!= basetype
)
2133 as_bad (_("bad type for register"));
2137 if (basereg
== NULL
)
2140 /* Try parsing as an integer. */
2141 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2142 if (exp
.X_op
!= O_constant
)
2144 as_bad (_("expression must be constant"));
2147 basereg
= &mybasereg
;
2148 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2154 typeinfo
= *basereg
->neon
;
2156 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2158 /* We got a type. */
2159 if (typeinfo
.defined
& NTA_HASTYPE
)
2161 as_bad (_("can't redefine the type of a register alias"));
2165 typeinfo
.defined
|= NTA_HASTYPE
;
2166 if (ntype
.elems
!= 1)
2168 as_bad (_("you must specify a single type only"));
2171 typeinfo
.eltype
= ntype
.el
[0];
2174 if (skip_past_char (&p
, '[') == SUCCESS
)
2177 /* We got a scalar index. */
2179 if (typeinfo
.defined
& NTA_HASINDEX
)
2181 as_bad (_("can't redefine the index of a scalar alias"));
2185 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2187 if (exp
.X_op
!= O_constant
)
2189 as_bad (_("scalar index must be constant"));
2193 typeinfo
.defined
|= NTA_HASINDEX
;
2194 typeinfo
.index
= exp
.X_add_number
;
2196 if (skip_past_char (&p
, ']') == FAIL
)
2198 as_bad (_("expecting ]"));
2203 namelen
= nameend
- newname
;
2204 namebuf
= alloca (namelen
+ 1);
2205 strncpy (namebuf
, newname
, namelen
);
2206 namebuf
[namelen
] = '\0';
2208 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2209 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2211 /* Insert name in all uppercase. */
2212 for (p
= namebuf
; *p
; p
++)
2215 if (strncmp (namebuf
, newname
, namelen
))
2216 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2217 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2219 /* Insert name in all lowercase. */
2220 for (p
= namebuf
; *p
; p
++)
2223 if (strncmp (namebuf
, newname
, namelen
))
2224 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2225 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2230 /* Should never be called, as .req goes between the alias and the
2231 register name, not at the beginning of the line. */
2233 s_req (int a ATTRIBUTE_UNUSED
)
2235 as_bad (_("invalid syntax for .req directive"));
2239 s_dn (int a ATTRIBUTE_UNUSED
)
2241 as_bad (_("invalid syntax for .dn directive"));
2245 s_qn (int a ATTRIBUTE_UNUSED
)
2247 as_bad (_("invalid syntax for .qn directive"));
2250 /* The .unreq directive deletes an alias which was previously defined
2251 by .req. For example:
2257 s_unreq (int a ATTRIBUTE_UNUSED
)
2262 name
= input_line_pointer
;
2264 while (*input_line_pointer
!= 0
2265 && *input_line_pointer
!= ' '
2266 && *input_line_pointer
!= '\n')
2267 ++input_line_pointer
;
2269 saved_char
= *input_line_pointer
;
2270 *input_line_pointer
= 0;
2273 as_bad (_("invalid syntax for .unreq directive"));
2276 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2279 as_bad (_("unknown register alias '%s'"), name
);
2280 else if (reg
->builtin
)
2281 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2288 hash_delete (arm_reg_hsh
, name
);
2289 free ((char *) reg
->name
);
2294 /* Also locate the all upper case and all lower case versions.
2295 Do not complain if we cannot find one or the other as it
2296 was probably deleted above. */
2298 nbuf
= strdup (name
);
2299 for (p
= nbuf
; *p
; p
++)
2301 reg
= hash_find (arm_reg_hsh
, nbuf
);
2304 hash_delete (arm_reg_hsh
, nbuf
);
2305 free ((char *) reg
->name
);
2311 for (p
= nbuf
; *p
; p
++)
2313 reg
= hash_find (arm_reg_hsh
, nbuf
);
2316 hash_delete (arm_reg_hsh
, nbuf
);
2317 free ((char *) reg
->name
);
2327 *input_line_pointer
= saved_char
;
2328 demand_empty_rest_of_line ();
2331 /* Directives: Instruction set selection. */
2334 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2335 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2336 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2337 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2339 static enum mstate mapstate
= MAP_UNDEFINED
;
2342 mapping_state (enum mstate state
)
2345 const char * symname
;
2348 if (mapstate
== state
)
2349 /* The mapping symbol has already been emitted.
2350 There is nothing else to do. */
2359 type
= BSF_NO_FLAGS
;
2363 type
= BSF_NO_FLAGS
;
2367 type
= BSF_NO_FLAGS
;
2375 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2377 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2378 symbol_table_insert (symbolP
);
2379 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2384 THUMB_SET_FUNC (symbolP
, 0);
2385 ARM_SET_THUMB (symbolP
, 0);
2386 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2390 THUMB_SET_FUNC (symbolP
, 1);
2391 ARM_SET_THUMB (symbolP
, 1);
2392 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2401 #define mapping_state(x) /* nothing */
2404 /* Find the real, Thumb encoded start of a Thumb function. */
2407 find_real_start (symbolS
* symbolP
)
2410 const char * name
= S_GET_NAME (symbolP
);
2411 symbolS
* new_target
;
2413 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2414 #define STUB_NAME ".real_start_of"
2419 /* The compiler may generate BL instructions to local labels because
2420 it needs to perform a branch to a far away location. These labels
2421 do not have a corresponding ".real_start_of" label. We check
2422 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2423 the ".real_start_of" convention for nonlocal branches. */
2424 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2427 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2428 new_target
= symbol_find (real_start
);
2430 if (new_target
== NULL
)
2432 as_warn (_("Failed to find real start of function: %s\n"), name
);
2433 new_target
= symbolP
;
2440 opcode_select (int width
)
2447 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2448 as_bad (_("selected processor does not support THUMB opcodes"));
2451 /* No need to force the alignment, since we will have been
2452 coming from ARM mode, which is word-aligned. */
2453 record_alignment (now_seg
, 1);
2455 mapping_state (MAP_THUMB
);
2461 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2462 as_bad (_("selected processor does not support ARM opcodes"));
2467 frag_align (2, 0, 0);
2469 record_alignment (now_seg
, 1);
2471 mapping_state (MAP_ARM
);
2475 as_bad (_("invalid instruction size selected (%d)"), width
);
2480 s_arm (int ignore ATTRIBUTE_UNUSED
)
2483 demand_empty_rest_of_line ();
2487 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2490 demand_empty_rest_of_line ();
2494 s_code (int unused ATTRIBUTE_UNUSED
)
2498 temp
= get_absolute_expression ();
2503 opcode_select (temp
);
2507 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2512 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2514 /* If we are not already in thumb mode go into it, EVEN if
2515 the target processor does not support thumb instructions.
2516 This is used by gcc/config/arm/lib1funcs.asm for example
2517 to compile interworking support functions even if the
2518 target processor should not support interworking. */
2522 record_alignment (now_seg
, 1);
2525 demand_empty_rest_of_line ();
2529 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2533 /* The following label is the name/address of the start of a Thumb function.
2534 We need to know this for the interworking support. */
2535 label_is_thumb_function_name
= TRUE
;
2538 /* Perform a .set directive, but also mark the alias as
2539 being a thumb function. */
2542 s_thumb_set (int equiv
)
2544 /* XXX the following is a duplicate of the code for s_set() in read.c
2545 We cannot just call that code as we need to get at the symbol that
2552 /* Especial apologies for the random logic:
2553 This just grew, and could be parsed much more simply!
2555 name
= input_line_pointer
;
2556 delim
= get_symbol_end ();
2557 end_name
= input_line_pointer
;
2560 if (*input_line_pointer
!= ',')
2563 as_bad (_("expected comma after name \"%s\""), name
);
2565 ignore_rest_of_line ();
2569 input_line_pointer
++;
2572 if (name
[0] == '.' && name
[1] == '\0')
2574 /* XXX - this should not happen to .thumb_set. */
2578 if ((symbolP
= symbol_find (name
)) == NULL
2579 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2582 /* When doing symbol listings, play games with dummy fragments living
2583 outside the normal fragment chain to record the file and line info
2585 if (listing
& LISTING_SYMBOLS
)
2587 extern struct list_info_struct
* listing_tail
;
2588 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2590 memset (dummy_frag
, 0, sizeof (fragS
));
2591 dummy_frag
->fr_type
= rs_fill
;
2592 dummy_frag
->line
= listing_tail
;
2593 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2594 dummy_frag
->fr_symbol
= symbolP
;
2598 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2601 /* "set" symbols are local unless otherwise specified. */
2602 SF_SET_LOCAL (symbolP
);
2603 #endif /* OBJ_COFF */
2604 } /* Make a new symbol. */
2606 symbol_table_insert (symbolP
);
2611 && S_IS_DEFINED (symbolP
)
2612 && S_GET_SEGMENT (symbolP
) != reg_section
)
2613 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2615 pseudo_set (symbolP
);
2617 demand_empty_rest_of_line ();
2619 /* XXX Now we come to the Thumb specific bit of code. */
2621 THUMB_SET_FUNC (symbolP
, 1);
2622 ARM_SET_THUMB (symbolP
, 1);
2623 #if defined OBJ_ELF || defined OBJ_COFF
2624 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2628 /* Directives: Mode selection. */
2630 /* .syntax [unified|divided] - choose the new unified syntax
2631 (same for Arm and Thumb encoding, modulo slight differences in what
2632 can be represented) or the old divergent syntax for each mode. */
2634 s_syntax (int unused ATTRIBUTE_UNUSED
)
2638 name
= input_line_pointer
;
2639 delim
= get_symbol_end ();
2641 if (!strcasecmp (name
, "unified"))
2642 unified_syntax
= TRUE
;
2643 else if (!strcasecmp (name
, "divided"))
2644 unified_syntax
= FALSE
;
2647 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2650 *input_line_pointer
= delim
;
2651 demand_empty_rest_of_line ();
2654 /* Directives: sectioning and alignment. */
2656 /* Same as s_align_ptwo but align 0 => align 2. */
2659 s_align (int unused ATTRIBUTE_UNUSED
)
2664 long max_alignment
= 15;
2666 temp
= get_absolute_expression ();
2667 if (temp
> max_alignment
)
2668 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2671 as_bad (_("alignment negative. 0 assumed."));
2675 if (*input_line_pointer
== ',')
2677 input_line_pointer
++;
2678 temp_fill
= get_absolute_expression ();
2690 /* Only make a frag if we HAVE to. */
2691 if (temp
&& !need_pass_2
)
2693 if (!fill_p
&& subseg_text_p (now_seg
))
2694 frag_align_code (temp
, 0);
2696 frag_align (temp
, (int) temp_fill
, 0);
2698 demand_empty_rest_of_line ();
2700 record_alignment (now_seg
, temp
);
2704 s_bss (int ignore ATTRIBUTE_UNUSED
)
2706 /* We don't support putting frags in the BSS segment, we fake it by
2707 marking in_bss, then looking at s_skip for clues. */
2708 subseg_set (bss_section
, 0);
2709 demand_empty_rest_of_line ();
2710 mapping_state (MAP_DATA
);
2714 s_even (int ignore ATTRIBUTE_UNUSED
)
2716 /* Never make frag if expect extra pass. */
2718 frag_align (1, 0, 0);
2720 record_alignment (now_seg
, 1);
2722 demand_empty_rest_of_line ();
2725 /* Directives: Literal pools. */
2727 static literal_pool
*
2728 find_literal_pool (void)
2730 literal_pool
* pool
;
2732 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2734 if (pool
->section
== now_seg
2735 && pool
->sub_section
== now_subseg
)
2742 static literal_pool
*
2743 find_or_make_literal_pool (void)
2745 /* Next literal pool ID number. */
2746 static unsigned int latest_pool_num
= 1;
2747 literal_pool
* pool
;
2749 pool
= find_literal_pool ();
2753 /* Create a new pool. */
2754 pool
= xmalloc (sizeof (* pool
));
2758 pool
->next_free_entry
= 0;
2759 pool
->section
= now_seg
;
2760 pool
->sub_section
= now_subseg
;
2761 pool
->next
= list_of_pools
;
2762 pool
->symbol
= NULL
;
2764 /* Add it to the list. */
2765 list_of_pools
= pool
;
2768 /* New pools, and emptied pools, will have a NULL symbol. */
2769 if (pool
->symbol
== NULL
)
2771 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2772 (valueT
) 0, &zero_address_frag
);
2773 pool
->id
= latest_pool_num
++;
2780 /* Add the literal in the global 'inst'
2781 structure to the relevant literal pool. */
2784 add_to_lit_pool (void)
2786 literal_pool
* pool
;
2789 pool
= find_or_make_literal_pool ();
2791 /* Check if this literal value is already in the pool. */
2792 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2794 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2795 && (inst
.reloc
.exp
.X_op
== O_constant
)
2796 && (pool
->literals
[entry
].X_add_number
2797 == inst
.reloc
.exp
.X_add_number
)
2798 && (pool
->literals
[entry
].X_unsigned
2799 == inst
.reloc
.exp
.X_unsigned
))
2802 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2803 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2804 && (pool
->literals
[entry
].X_add_number
2805 == inst
.reloc
.exp
.X_add_number
)
2806 && (pool
->literals
[entry
].X_add_symbol
2807 == inst
.reloc
.exp
.X_add_symbol
)
2808 && (pool
->literals
[entry
].X_op_symbol
2809 == inst
.reloc
.exp
.X_op_symbol
))
2813 /* Do we need to create a new entry? */
2814 if (entry
== pool
->next_free_entry
)
2816 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2818 inst
.error
= _("literal pool overflow");
2822 pool
->literals
[entry
] = inst
.reloc
.exp
;
2823 pool
->next_free_entry
+= 1;
2826 inst
.reloc
.exp
.X_op
= O_symbol
;
2827 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2828 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2833 /* Can't use symbol_new here, so have to create a symbol and then at
2834 a later date assign it a value. Thats what these functions do. */
2837 symbol_locate (symbolS
* symbolP
,
2838 const char * name
, /* It is copied, the caller can modify. */
2839 segT segment
, /* Segment identifier (SEG_<something>). */
2840 valueT valu
, /* Symbol value. */
2841 fragS
* frag
) /* Associated fragment. */
2843 unsigned int name_length
;
2844 char * preserved_copy_of_name
;
2846 name_length
= strlen (name
) + 1; /* +1 for \0. */
2847 obstack_grow (¬es
, name
, name_length
);
2848 preserved_copy_of_name
= obstack_finish (¬es
);
2850 #ifdef tc_canonicalize_symbol_name
2851 preserved_copy_of_name
=
2852 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2855 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2857 S_SET_SEGMENT (symbolP
, segment
);
2858 S_SET_VALUE (symbolP
, valu
);
2859 symbol_clear_list_pointers (symbolP
);
2861 symbol_set_frag (symbolP
, frag
);
2863 /* Link to end of symbol chain. */
2865 extern int symbol_table_frozen
;
2867 if (symbol_table_frozen
)
2871 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2873 obj_symbol_new_hook (symbolP
);
2875 #ifdef tc_symbol_new_hook
2876 tc_symbol_new_hook (symbolP
);
2880 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2881 #endif /* DEBUG_SYMS */
2886 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2889 literal_pool
* pool
;
2892 pool
= find_literal_pool ();
2894 || pool
->symbol
== NULL
2895 || pool
->next_free_entry
== 0)
2898 mapping_state (MAP_DATA
);
2900 /* Align pool as you have word accesses.
2901 Only make a frag if we have to. */
2903 frag_align (2, 0, 0);
2905 record_alignment (now_seg
, 2);
2907 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2909 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2910 (valueT
) frag_now_fix (), frag_now
);
2911 symbol_table_insert (pool
->symbol
);
2913 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2915 #if defined OBJ_COFF || defined OBJ_ELF
2916 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2919 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2920 /* First output the expression in the instruction to the pool. */
2921 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2923 /* Mark the pool as empty. */
2924 pool
->next_free_entry
= 0;
2925 pool
->symbol
= NULL
;
2929 /* Forward declarations for functions below, in the MD interface
2931 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2932 static valueT
create_unwind_entry (int);
2933 static void start_unwind_section (const segT
, int);
2934 static void add_unwind_opcode (valueT
, int);
2935 static void flush_pending_unwind (void);
2937 /* Directives: Data. */
2940 s_arm_elf_cons (int nbytes
)
2944 #ifdef md_flush_pending_output
2945 md_flush_pending_output ();
2948 if (is_it_end_of_statement ())
2950 demand_empty_rest_of_line ();
2954 #ifdef md_cons_align
2955 md_cons_align (nbytes
);
2958 mapping_state (MAP_DATA
);
2962 char *base
= input_line_pointer
;
2966 if (exp
.X_op
!= O_symbol
)
2967 emit_expr (&exp
, (unsigned int) nbytes
);
2970 char *before_reloc
= input_line_pointer
;
2971 reloc
= parse_reloc (&input_line_pointer
);
2974 as_bad (_("unrecognized relocation suffix"));
2975 ignore_rest_of_line ();
2978 else if (reloc
== BFD_RELOC_UNUSED
)
2979 emit_expr (&exp
, (unsigned int) nbytes
);
2982 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2983 int size
= bfd_get_reloc_size (howto
);
2985 if (reloc
== BFD_RELOC_ARM_PLT32
)
2987 as_bad (_("(plt) is only valid on branch targets"));
2988 reloc
= BFD_RELOC_UNUSED
;
2993 as_bad (_("%s relocations do not fit in %d bytes"),
2994 howto
->name
, nbytes
);
2997 /* We've parsed an expression stopping at O_symbol.
2998 But there may be more expression left now that we
2999 have parsed the relocation marker. Parse it again.
3000 XXX Surely there is a cleaner way to do this. */
3001 char *p
= input_line_pointer
;
3003 char *save_buf
= alloca (input_line_pointer
- base
);
3004 memcpy (save_buf
, base
, input_line_pointer
- base
);
3005 memmove (base
+ (input_line_pointer
- before_reloc
),
3006 base
, before_reloc
- base
);
3008 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3010 memcpy (base
, save_buf
, p
- base
);
3012 offset
= nbytes
- size
;
3013 p
= frag_more ((int) nbytes
);
3014 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3015 size
, &exp
, 0, reloc
);
3020 while (*input_line_pointer
++ == ',');
3022 /* Put terminator back into stream. */
3023 input_line_pointer
--;
3024 demand_empty_rest_of_line ();
3028 /* Parse a .rel31 directive. */
3031 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3038 if (*input_line_pointer
== '1')
3039 highbit
= 0x80000000;
3040 else if (*input_line_pointer
!= '0')
3041 as_bad (_("expected 0 or 1"));
3043 input_line_pointer
++;
3044 if (*input_line_pointer
!= ',')
3045 as_bad (_("missing comma"));
3046 input_line_pointer
++;
3048 #ifdef md_flush_pending_output
3049 md_flush_pending_output ();
3052 #ifdef md_cons_align
3056 mapping_state (MAP_DATA
);
3061 md_number_to_chars (p
, highbit
, 4);
3062 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3063 BFD_RELOC_ARM_PREL31
);
3065 demand_empty_rest_of_line ();
3068 /* Directives: AEABI stack-unwind tables. */
3070 /* Parse an unwind_fnstart directive. Simply records the current location. */
3073 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3075 demand_empty_rest_of_line ();
3076 /* Mark the start of the function. */
3077 unwind
.proc_start
= expr_build_dot ();
3079 /* Reset the rest of the unwind info. */
3080 unwind
.opcode_count
= 0;
3081 unwind
.table_entry
= NULL
;
3082 unwind
.personality_routine
= NULL
;
3083 unwind
.personality_index
= -1;
3084 unwind
.frame_size
= 0;
3085 unwind
.fp_offset
= 0;
3088 unwind
.sp_restored
= 0;
3092 /* Parse a handlerdata directive. Creates the exception handling table entry
3093 for the function. */
3096 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.table_entry
)
3100 as_bad (_("duplicate .handlerdata directive"));
3102 create_unwind_entry (1);
3105 /* Parse an unwind_fnend directive. Generates the index table entry. */
3108 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3114 demand_empty_rest_of_line ();
3116 /* Add eh table entry. */
3117 if (unwind
.table_entry
== NULL
)
3118 val
= create_unwind_entry (0);
3122 /* Add index table entry. This is two words. */
3123 start_unwind_section (unwind
.saved_seg
, 1);
3124 frag_align (2, 0, 0);
3125 record_alignment (now_seg
, 2);
3127 ptr
= frag_more (8);
3128 where
= frag_now_fix () - 8;
3130 /* Self relative offset of the function start. */
3131 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3132 BFD_RELOC_ARM_PREL31
);
3134 /* Indicate dependency on EHABI-defined personality routines to the
3135 linker, if it hasn't been done already. */
3136 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3137 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3139 static const char *const name
[] =
3141 "__aeabi_unwind_cpp_pr0",
3142 "__aeabi_unwind_cpp_pr1",
3143 "__aeabi_unwind_cpp_pr2"
3145 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3146 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3147 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3148 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3149 = marked_pr_dependency
;
3153 /* Inline exception table entry. */
3154 md_number_to_chars (ptr
+ 4, val
, 4);
3156 /* Self relative offset of the table entry. */
3157 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3158 BFD_RELOC_ARM_PREL31
);
3160 /* Restore the original section. */
3161 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3165 /* Parse an unwind_cantunwind directive. */
3168 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3170 demand_empty_rest_of_line ();
3171 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3172 as_bad (_("personality routine specified for cantunwind frame"));
3174 unwind
.personality_index
= -2;
3178 /* Parse a personalityindex directive. */
3181 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3185 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3186 as_bad (_("duplicate .personalityindex directive"));
3190 if (exp
.X_op
!= O_constant
3191 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3193 as_bad (_("bad personality routine number"));
3194 ignore_rest_of_line ();
3198 unwind
.personality_index
= exp
.X_add_number
;
3200 demand_empty_rest_of_line ();
3204 /* Parse a personality directive. */
3207 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3211 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3212 as_bad (_("duplicate .personality directive"));
3214 name
= input_line_pointer
;
3215 c
= get_symbol_end ();
3216 p
= input_line_pointer
;
3217 unwind
.personality_routine
= symbol_find_or_make (name
);
3219 demand_empty_rest_of_line ();
3223 /* Parse a directive saving core registers. */
3226 s_arm_unwind_save_core (void)
3232 range
= parse_reg_list (&input_line_pointer
);
3235 as_bad (_("expected register list"));
3236 ignore_rest_of_line ();
3240 demand_empty_rest_of_line ();
3242 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3243 into .unwind_save {..., sp...}. We aren't bothered about the value of
3244 ip because it is clobbered by calls. */
3245 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3246 && (range
& 0x3000) == 0x1000)
3248 unwind
.opcode_count
--;
3249 unwind
.sp_restored
= 0;
3250 range
= (range
| 0x2000) & ~0x1000;
3251 unwind
.pending_offset
= 0;
3257 /* See if we can use the short opcodes. These pop a block of up to 8
3258 registers starting with r4, plus maybe r14. */
3259 for (n
= 0; n
< 8; n
++)
3261 /* Break at the first non-saved register. */
3262 if ((range
& (1 << (n
+ 4))) == 0)
3265 /* See if there are any other bits set. */
3266 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3268 /* Use the long form. */
3269 op
= 0x8000 | ((range
>> 4) & 0xfff);
3270 add_unwind_opcode (op
, 2);
3274 /* Use the short form. */
3276 op
= 0xa8; /* Pop r14. */
3278 op
= 0xa0; /* Do not pop r14. */
3280 add_unwind_opcode (op
, 1);
3287 op
= 0xb100 | (range
& 0xf);
3288 add_unwind_opcode (op
, 2);
3291 /* Record the number of bytes pushed. */
3292 for (n
= 0; n
< 16; n
++)
3294 if (range
& (1 << n
))
3295 unwind
.frame_size
+= 4;
3300 /* Parse a directive saving FPA registers. */
3303 s_arm_unwind_save_fpa (int reg
)
3309 /* Get Number of registers to transfer. */
3310 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3313 exp
.X_op
= O_illegal
;
3315 if (exp
.X_op
!= O_constant
)
3317 as_bad (_("expected , <constant>"));
3318 ignore_rest_of_line ();
3322 num_regs
= exp
.X_add_number
;
3324 if (num_regs
< 1 || num_regs
> 4)
3326 as_bad (_("number of registers must be in the range [1:4]"));
3327 ignore_rest_of_line ();
3331 demand_empty_rest_of_line ();
3336 op
= 0xb4 | (num_regs
- 1);
3337 add_unwind_opcode (op
, 1);
3342 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3343 add_unwind_opcode (op
, 2);
3345 unwind
.frame_size
+= num_regs
* 12;
3349 /* Parse a directive saving VFP registers for ARMv6 and above. */
3352 s_arm_unwind_save_vfp_armv6 (void)
3357 int num_vfpv3_regs
= 0;
3358 int num_regs_below_16
;
3360 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3363 as_bad (_("expected register list"));
3364 ignore_rest_of_line ();
3368 demand_empty_rest_of_line ();
3370 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3371 than FSTMX/FLDMX-style ones). */
3373 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3375 num_vfpv3_regs
= count
;
3376 else if (start
+ count
> 16)
3377 num_vfpv3_regs
= start
+ count
- 16;
3379 if (num_vfpv3_regs
> 0)
3381 int start_offset
= start
> 16 ? start
- 16 : 0;
3382 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3383 add_unwind_opcode (op
, 2);
3386 /* Generate opcode for registers numbered in the range 0 .. 15. */
3387 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3388 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3389 if (num_regs_below_16
> 0)
3391 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3392 add_unwind_opcode (op
, 2);
3395 unwind
.frame_size
+= count
* 8;
3399 /* Parse a directive saving VFP registers for pre-ARMv6. */
3402 s_arm_unwind_save_vfp (void)
3408 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3411 as_bad (_("expected register list"));
3412 ignore_rest_of_line ();
3416 demand_empty_rest_of_line ();
3421 op
= 0xb8 | (count
- 1);
3422 add_unwind_opcode (op
, 1);
3427 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3428 add_unwind_opcode (op
, 2);
3430 unwind
.frame_size
+= count
* 8 + 4;
3434 /* Parse a directive saving iWMMXt data registers. */
3437 s_arm_unwind_save_mmxwr (void)
3445 if (*input_line_pointer
== '{')
3446 input_line_pointer
++;
3450 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3454 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3459 as_tsktsk (_("register list not in ascending order"));
3462 if (*input_line_pointer
== '-')
3464 input_line_pointer
++;
3465 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3468 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3471 else if (reg
>= hi_reg
)
3473 as_bad (_("bad register range"));
3476 for (; reg
< hi_reg
; reg
++)
3480 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3482 if (*input_line_pointer
== '}')
3483 input_line_pointer
++;
3485 demand_empty_rest_of_line ();
3487 /* Generate any deferred opcodes because we're going to be looking at
3489 flush_pending_unwind ();
3491 for (i
= 0; i
< 16; i
++)
3493 if (mask
& (1 << i
))
3494 unwind
.frame_size
+= 8;
3497 /* Attempt to combine with a previous opcode. We do this because gcc
3498 likes to output separate unwind directives for a single block of
3500 if (unwind
.opcode_count
> 0)
3502 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3503 if ((i
& 0xf8) == 0xc0)
3506 /* Only merge if the blocks are contiguous. */
3509 if ((mask
& 0xfe00) == (1 << 9))
3511 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3512 unwind
.opcode_count
--;
3515 else if (i
== 6 && unwind
.opcode_count
>= 2)
3517 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3521 op
= 0xffff << (reg
- 1);
3523 && ((mask
& op
) == (1u << (reg
- 1))))
3525 op
= (1 << (reg
+ i
+ 1)) - 1;
3526 op
&= ~((1 << reg
) - 1);
3528 unwind
.opcode_count
-= 2;
3535 /* We want to generate opcodes in the order the registers have been
3536 saved, ie. descending order. */
3537 for (reg
= 15; reg
>= -1; reg
--)
3539 /* Save registers in blocks. */
3541 || !(mask
& (1 << reg
)))
3543 /* We found an unsaved reg. Generate opcodes to save the
3550 op
= 0xc0 | (hi_reg
- 10);
3551 add_unwind_opcode (op
, 1);
3556 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3557 add_unwind_opcode (op
, 2);
3566 ignore_rest_of_line ();
3570 s_arm_unwind_save_mmxwcg (void)
3577 if (*input_line_pointer
== '{')
3578 input_line_pointer
++;
3582 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3586 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3592 as_tsktsk (_("register list not in ascending order"));
3595 if (*input_line_pointer
== '-')
3597 input_line_pointer
++;
3598 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3601 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3604 else if (reg
>= hi_reg
)
3606 as_bad (_("bad register range"));
3609 for (; reg
< hi_reg
; reg
++)
3613 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3615 if (*input_line_pointer
== '}')
3616 input_line_pointer
++;
3618 demand_empty_rest_of_line ();
3620 /* Generate any deferred opcodes because we're going to be looking at
3622 flush_pending_unwind ();
3624 for (reg
= 0; reg
< 16; reg
++)
3626 if (mask
& (1 << reg
))
3627 unwind
.frame_size
+= 4;
3630 add_unwind_opcode (op
, 2);
3633 ignore_rest_of_line ();
3637 /* Parse an unwind_save directive.
3638 If the argument is non-zero, this is a .vsave directive. */
3641 s_arm_unwind_save (int arch_v6
)
3644 struct reg_entry
*reg
;
3645 bfd_boolean had_brace
= FALSE
;
3647 /* Figure out what sort of save we have. */
3648 peek
= input_line_pointer
;
3656 reg
= arm_reg_parse_multi (&peek
);
3660 as_bad (_("register expected"));
3661 ignore_rest_of_line ();
3670 as_bad (_("FPA .unwind_save does not take a register list"));
3671 ignore_rest_of_line ();
3674 input_line_pointer
= peek
;
3675 s_arm_unwind_save_fpa (reg
->number
);
3678 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3681 s_arm_unwind_save_vfp_armv6 ();
3683 s_arm_unwind_save_vfp ();
3685 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3686 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3689 as_bad (_(".unwind_save does not support this kind of register"));
3690 ignore_rest_of_line ();
3695 /* Parse an unwind_movsp directive. */
3698 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3704 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3707 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3708 ignore_rest_of_line ();
3712 /* Optional constant. */
3713 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3715 if (immediate_for_directive (&offset
) == FAIL
)
3721 demand_empty_rest_of_line ();
3723 if (reg
== REG_SP
|| reg
== REG_PC
)
3725 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3729 if (unwind
.fp_reg
!= REG_SP
)
3730 as_bad (_("unexpected .unwind_movsp directive"));
3732 /* Generate opcode to restore the value. */
3734 add_unwind_opcode (op
, 1);
3736 /* Record the information for later. */
3737 unwind
.fp_reg
= reg
;
3738 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3739 unwind
.sp_restored
= 1;
3742 /* Parse an unwind_pad directive. */
3745 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3749 if (immediate_for_directive (&offset
) == FAIL
)
3754 as_bad (_("stack increment must be multiple of 4"));
3755 ignore_rest_of_line ();
3759 /* Don't generate any opcodes, just record the details for later. */
3760 unwind
.frame_size
+= offset
;
3761 unwind
.pending_offset
+= offset
;
3763 demand_empty_rest_of_line ();
3766 /* Parse an unwind_setfp directive. */
3769 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3775 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3776 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3779 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3781 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3783 as_bad (_("expected <reg>, <reg>"));
3784 ignore_rest_of_line ();
3788 /* Optional constant. */
3789 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3791 if (immediate_for_directive (&offset
) == FAIL
)
3797 demand_empty_rest_of_line ();
3799 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3801 as_bad (_("register must be either sp or set by a previous"
3802 "unwind_movsp directive"));
3806 /* Don't generate any opcodes, just record the information for later. */
3807 unwind
.fp_reg
= fp_reg
;
3810 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3812 unwind
.fp_offset
-= offset
;
3815 /* Parse an unwind_raw directive. */
3818 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3821 /* This is an arbitrary limit. */
3822 unsigned char op
[16];
3826 if (exp
.X_op
== O_constant
3827 && skip_past_comma (&input_line_pointer
) != FAIL
)
3829 unwind
.frame_size
+= exp
.X_add_number
;
3833 exp
.X_op
= O_illegal
;
3835 if (exp
.X_op
!= O_constant
)
3837 as_bad (_("expected <offset>, <opcode>"));
3838 ignore_rest_of_line ();
3844 /* Parse the opcode. */
3849 as_bad (_("unwind opcode too long"));
3850 ignore_rest_of_line ();
3852 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3854 as_bad (_("invalid unwind opcode"));
3855 ignore_rest_of_line ();
3858 op
[count
++] = exp
.X_add_number
;
3860 /* Parse the next byte. */
3861 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3867 /* Add the opcode bytes in reverse order. */
3869 add_unwind_opcode (op
[count
], 1);
3871 demand_empty_rest_of_line ();
3875 /* Parse a .eabi_attribute directive. */
3878 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3880 s_vendor_attribute (OBJ_ATTR_PROC
);
3882 #endif /* OBJ_ELF */
3884 static void s_arm_arch (int);
3885 static void s_arm_object_arch (int);
3886 static void s_arm_cpu (int);
3887 static void s_arm_fpu (int);
3892 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3899 if (exp
.X_op
== O_symbol
)
3900 exp
.X_op
= O_secrel
;
3902 emit_expr (&exp
, 4);
3904 while (*input_line_pointer
++ == ',');
3906 input_line_pointer
--;
3907 demand_empty_rest_of_line ();
3911 /* This table describes all the machine specific pseudo-ops the assembler
3912 has to support. The fields are:
3913 pseudo-op name without dot
3914 function to call to execute this pseudo-op
3915 Integer arg to pass to the function. */
3917 const pseudo_typeS md_pseudo_table
[] =
3919 /* Never called because '.req' does not start a line. */
3920 { "req", s_req
, 0 },
3921 /* Following two are likewise never called. */
3924 { "unreq", s_unreq
, 0 },
3925 { "bss", s_bss
, 0 },
3926 { "align", s_align
, 0 },
3927 { "arm", s_arm
, 0 },
3928 { "thumb", s_thumb
, 0 },
3929 { "code", s_code
, 0 },
3930 { "force_thumb", s_force_thumb
, 0 },
3931 { "thumb_func", s_thumb_func
, 0 },
3932 { "thumb_set", s_thumb_set
, 0 },
3933 { "even", s_even
, 0 },
3934 { "ltorg", s_ltorg
, 0 },
3935 { "pool", s_ltorg
, 0 },
3936 { "syntax", s_syntax
, 0 },
3937 { "cpu", s_arm_cpu
, 0 },
3938 { "arch", s_arm_arch
, 0 },
3939 { "object_arch", s_arm_object_arch
, 0 },
3940 { "fpu", s_arm_fpu
, 0 },
3942 { "word", s_arm_elf_cons
, 4 },
3943 { "long", s_arm_elf_cons
, 4 },
3944 { "rel31", s_arm_rel31
, 0 },
3945 { "fnstart", s_arm_unwind_fnstart
, 0 },
3946 { "fnend", s_arm_unwind_fnend
, 0 },
3947 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3948 { "personality", s_arm_unwind_personality
, 0 },
3949 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3950 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3951 { "save", s_arm_unwind_save
, 0 },
3952 { "vsave", s_arm_unwind_save
, 1 },
3953 { "movsp", s_arm_unwind_movsp
, 0 },
3954 { "pad", s_arm_unwind_pad
, 0 },
3955 { "setfp", s_arm_unwind_setfp
, 0 },
3956 { "unwind_raw", s_arm_unwind_raw
, 0 },
3957 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3961 /* These are used for dwarf. */
3965 /* These are used for dwarf2. */
3966 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3967 { "loc", dwarf2_directive_loc
, 0 },
3968 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3970 { "extend", float_cons
, 'x' },
3971 { "ldouble", float_cons
, 'x' },
3972 { "packed", float_cons
, 'p' },
3974 {"secrel32", pe_directive_secrel
, 0},
3979 /* Parser functions used exclusively in instruction operands. */
3981 /* Generic immediate-value read function for use in insn parsing.
3982 STR points to the beginning of the immediate (the leading #);
3983 VAL receives the value; if the value is outside [MIN, MAX]
3984 issue an error. PREFIX_OPT is true if the immediate prefix is
3988 parse_immediate (char **str
, int *val
, int min
, int max
,
3989 bfd_boolean prefix_opt
)
3992 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3993 if (exp
.X_op
!= O_constant
)
3995 inst
.error
= _("constant expression required");
3999 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4001 inst
.error
= _("immediate value out of range");
4005 *val
= exp
.X_add_number
;
4009 /* Less-generic immediate-value read function with the possibility of loading a
4010 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4011 instructions. Puts the result directly in inst.operands[i]. */
4014 parse_big_immediate (char **str
, int i
)
4019 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4021 if (exp
.X_op
== O_constant
)
4023 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4024 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4025 O_constant. We have to be careful not to break compilation for
4026 32-bit X_add_number, though. */
4027 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4029 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4030 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4031 inst
.operands
[i
].regisimm
= 1;
4034 else if (exp
.X_op
== O_big
4035 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4036 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4038 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4039 /* Bignums have their least significant bits in
4040 generic_bignum[0]. Make sure we put 32 bits in imm and
4041 32 bits in reg, in a (hopefully) portable way. */
4042 assert (parts
!= 0);
4043 inst
.operands
[i
].imm
= 0;
4044 for (j
= 0; j
< parts
; j
++, idx
++)
4045 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4046 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4047 inst
.operands
[i
].reg
= 0;
4048 for (j
= 0; j
< parts
; j
++, idx
++)
4049 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4050 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4051 inst
.operands
[i
].regisimm
= 1;
4061 /* Returns the pseudo-register number of an FPA immediate constant,
4062 or FAIL if there isn't a valid constant here. */
4065 parse_fpa_immediate (char ** str
)
4067 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4073 /* First try and match exact strings, this is to guarantee
4074 that some formats will work even for cross assembly. */
4076 for (i
= 0; fp_const
[i
]; i
++)
4078 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4082 *str
+= strlen (fp_const
[i
]);
4083 if (is_end_of_line
[(unsigned char) **str
])
4089 /* Just because we didn't get a match doesn't mean that the constant
4090 isn't valid, just that it is in a format that we don't
4091 automatically recognize. Try parsing it with the standard
4092 expression routines. */
4094 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4096 /* Look for a raw floating point number. */
4097 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4098 && is_end_of_line
[(unsigned char) *save_in
])
4100 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4102 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4104 if (words
[j
] != fp_values
[i
][j
])
4108 if (j
== MAX_LITTLENUMS
)
4116 /* Try and parse a more complex expression, this will probably fail
4117 unless the code uses a floating point prefix (eg "0f"). */
4118 save_in
= input_line_pointer
;
4119 input_line_pointer
= *str
;
4120 if (expression (&exp
) == absolute_section
4121 && exp
.X_op
== O_big
4122 && exp
.X_add_number
< 0)
4124 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4126 if (gen_to_words (words
, 5, (long) 15) == 0)
4128 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4130 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4132 if (words
[j
] != fp_values
[i
][j
])
4136 if (j
== MAX_LITTLENUMS
)
4138 *str
= input_line_pointer
;
4139 input_line_pointer
= save_in
;
4146 *str
= input_line_pointer
;
4147 input_line_pointer
= save_in
;
4148 inst
.error
= _("invalid FPA immediate expression");
4152 /* Returns 1 if a number has "quarter-precision" float format
4153 0baBbbbbbc defgh000 00000000 00000000. */
4156 is_quarter_float (unsigned imm
)
4158 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4159 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4162 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4163 0baBbbbbbc defgh000 00000000 00000000.
4164 The zero and minus-zero cases need special handling, since they can't be
4165 encoded in the "quarter-precision" float format, but can nonetheless be
4166 loaded as integer constants. */
4169 parse_qfloat_immediate (char **ccp
, int *immed
)
4173 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4174 int found_fpchar
= 0;
4176 skip_past_char (&str
, '#');
4178 /* We must not accidentally parse an integer as a floating-point number. Make
4179 sure that the value we parse is not an integer by checking for special
4180 characters '.' or 'e'.
4181 FIXME: This is a horrible hack, but doing better is tricky because type
4182 information isn't in a very usable state at parse time. */
4184 skip_whitespace (fpnum
);
4186 if (strncmp (fpnum
, "0x", 2) == 0)
4190 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4191 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4201 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4203 unsigned fpword
= 0;
4206 /* Our FP word must be 32 bits (single-precision FP). */
4207 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4209 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4213 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4226 /* Shift operands. */
4229 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4232 struct asm_shift_name
4235 enum shift_kind kind
;
4238 /* Third argument to parse_shift. */
4239 enum parse_shift_mode
4241 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4242 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4243 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4244 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4245 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4248 /* Parse a <shift> specifier on an ARM data processing instruction.
4249 This has three forms:
4251 (LSL|LSR|ASL|ASR|ROR) Rs
4252 (LSL|LSR|ASL|ASR|ROR) #imm
4255 Note that ASL is assimilated to LSL in the instruction encoding, and
4256 RRX to ROR #0 (which cannot be written as such). */
4259 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4261 const struct asm_shift_name
*shift_name
;
4262 enum shift_kind shift
;
4267 for (p
= *str
; ISALPHA (*p
); p
++)
4272 inst
.error
= _("shift expression expected");
4276 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4278 if (shift_name
== NULL
)
4280 inst
.error
= _("shift expression expected");
4284 shift
= shift_name
->kind
;
4288 case NO_SHIFT_RESTRICT
:
4289 case SHIFT_IMMEDIATE
: break;
4291 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4292 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4294 inst
.error
= _("'LSL' or 'ASR' required");
4299 case SHIFT_LSL_IMMEDIATE
:
4300 if (shift
!= SHIFT_LSL
)
4302 inst
.error
= _("'LSL' required");
4307 case SHIFT_ASR_IMMEDIATE
:
4308 if (shift
!= SHIFT_ASR
)
4310 inst
.error
= _("'ASR' required");
4318 if (shift
!= SHIFT_RRX
)
4320 /* Whitespace can appear here if the next thing is a bare digit. */
4321 skip_whitespace (p
);
4323 if (mode
== NO_SHIFT_RESTRICT
4324 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4326 inst
.operands
[i
].imm
= reg
;
4327 inst
.operands
[i
].immisreg
= 1;
4329 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4332 inst
.operands
[i
].shift_kind
= shift
;
4333 inst
.operands
[i
].shifted
= 1;
4338 /* Parse a <shifter_operand> for an ARM data processing instruction:
4341 #<immediate>, <rotate>
4345 where <shift> is defined by parse_shift above, and <rotate> is a
4346 multiple of 2 between 0 and 30. Validation of immediate operands
4347 is deferred to md_apply_fix. */
4350 parse_shifter_operand (char **str
, int i
)
4355 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4357 inst
.operands
[i
].reg
= value
;
4358 inst
.operands
[i
].isreg
= 1;
4360 /* parse_shift will override this if appropriate */
4361 inst
.reloc
.exp
.X_op
= O_constant
;
4362 inst
.reloc
.exp
.X_add_number
= 0;
4364 if (skip_past_comma (str
) == FAIL
)
4367 /* Shift operation on register. */
4368 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4371 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4374 if (skip_past_comma (str
) == SUCCESS
)
4376 /* #x, y -- ie explicit rotation by Y. */
4377 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4380 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4382 inst
.error
= _("constant expression expected");
4386 value
= expr
.X_add_number
;
4387 if (value
< 0 || value
> 30 || value
% 2 != 0)
4389 inst
.error
= _("invalid rotation");
4392 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4394 inst
.error
= _("invalid constant");
4398 /* Convert to decoded value. md_apply_fix will put it back. */
4399 inst
.reloc
.exp
.X_add_number
4400 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4401 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4404 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4405 inst
.reloc
.pc_rel
= 0;
4409 /* Group relocation information. Each entry in the table contains the
4410 textual name of the relocation as may appear in assembler source
4411 and must end with a colon.
4412 Along with this textual name are the relocation codes to be used if
4413 the corresponding instruction is an ALU instruction (ADD or SUB only),
4414 an LDR, an LDRS, or an LDC. */
4416 struct group_reloc_table_entry
4427 /* Varieties of non-ALU group relocation. */
4434 static struct group_reloc_table_entry group_reloc_table
[] =
4435 { /* Program counter relative: */
4437 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4442 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4443 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4444 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4445 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4447 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4452 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4453 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4454 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4455 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4457 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4458 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4459 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4460 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4461 /* Section base relative */
4463 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4468 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4469 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4470 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4471 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4473 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4478 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4479 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4480 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4481 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4483 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4484 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4485 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4486 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4488 /* Given the address of a pointer pointing to the textual name of a group
4489 relocation as may appear in assembler source, attempt to find its details
4490 in group_reloc_table. The pointer will be updated to the character after
4491 the trailing colon. On failure, FAIL will be returned; SUCCESS
4492 otherwise. On success, *entry will be updated to point at the relevant
4493 group_reloc_table entry. */
4496 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4499 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4501 int length
= strlen (group_reloc_table
[i
].name
);
4503 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4504 && (*str
)[length
] == ':')
4506 *out
= &group_reloc_table
[i
];
4507 *str
+= (length
+ 1);
4515 /* Parse a <shifter_operand> for an ARM data processing instruction
4516 (as for parse_shifter_operand) where group relocations are allowed:
4519 #<immediate>, <rotate>
4520 #:<group_reloc>:<expression>
4524 where <group_reloc> is one of the strings defined in group_reloc_table.
4525 The hashes are optional.
4527 Everything else is as for parse_shifter_operand. */
4529 static parse_operand_result
4530 parse_shifter_operand_group_reloc (char **str
, int i
)
4532 /* Determine if we have the sequence of characters #: or just :
4533 coming next. If we do, then we check for a group relocation.
4534 If we don't, punt the whole lot to parse_shifter_operand. */
4536 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4537 || (*str
)[0] == ':')
4539 struct group_reloc_table_entry
*entry
;
4541 if ((*str
)[0] == '#')
4546 /* Try to parse a group relocation. Anything else is an error. */
4547 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4549 inst
.error
= _("unknown group relocation");
4550 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4553 /* We now have the group relocation table entry corresponding to
4554 the name in the assembler source. Next, we parse the expression. */
4555 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4556 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4558 /* Record the relocation type (always the ALU variant here). */
4559 inst
.reloc
.type
= entry
->alu_code
;
4560 assert (inst
.reloc
.type
!= 0);
4562 return PARSE_OPERAND_SUCCESS
;
4565 return parse_shifter_operand (str
, i
) == SUCCESS
4566 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4568 /* Never reached. */
4571 /* Parse all forms of an ARM address expression. Information is written
4572 to inst.operands[i] and/or inst.reloc.
4574 Preindexed addressing (.preind=1):
4576 [Rn, #offset] .reg=Rn .reloc.exp=offset
4577 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4578 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4579 .shift_kind=shift .reloc.exp=shift_imm
4581 These three may have a trailing ! which causes .writeback to be set also.
4583 Postindexed addressing (.postind=1, .writeback=1):
4585 [Rn], #offset .reg=Rn .reloc.exp=offset
4586 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4587 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4588 .shift_kind=shift .reloc.exp=shift_imm
4590 Unindexed addressing (.preind=0, .postind=0):
4592 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4596 [Rn]{!} shorthand for [Rn,#0]{!}
4597 =immediate .isreg=0 .reloc.exp=immediate
4598 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4600 It is the caller's responsibility to check for addressing modes not
4601 supported by the instruction, and to set inst.reloc.type. */
4603 static parse_operand_result
4604 parse_address_main (char **str
, int i
, int group_relocations
,
4605 group_reloc_type group_type
)
4610 if (skip_past_char (&p
, '[') == FAIL
)
4612 if (skip_past_char (&p
, '=') == FAIL
)
4614 /* bare address - translate to PC-relative offset */
4615 inst
.reloc
.pc_rel
= 1;
4616 inst
.operands
[i
].reg
= REG_PC
;
4617 inst
.operands
[i
].isreg
= 1;
4618 inst
.operands
[i
].preind
= 1;
4620 /* else a load-constant pseudo op, no special treatment needed here */
4622 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4623 return PARSE_OPERAND_FAIL
;
4626 return PARSE_OPERAND_SUCCESS
;
4629 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4631 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4632 return PARSE_OPERAND_FAIL
;
4634 inst
.operands
[i
].reg
= reg
;
4635 inst
.operands
[i
].isreg
= 1;
4637 if (skip_past_comma (&p
) == SUCCESS
)
4639 inst
.operands
[i
].preind
= 1;
4642 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4644 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4646 inst
.operands
[i
].imm
= reg
;
4647 inst
.operands
[i
].immisreg
= 1;
4649 if (skip_past_comma (&p
) == SUCCESS
)
4650 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4651 return PARSE_OPERAND_FAIL
;
4653 else if (skip_past_char (&p
, ':') == SUCCESS
)
4655 /* FIXME: '@' should be used here, but it's filtered out by generic
4656 code before we get to see it here. This may be subject to
4659 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4660 if (exp
.X_op
!= O_constant
)
4662 inst
.error
= _("alignment must be constant");
4663 return PARSE_OPERAND_FAIL
;
4665 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4666 inst
.operands
[i
].immisalign
= 1;
4667 /* Alignments are not pre-indexes. */
4668 inst
.operands
[i
].preind
= 0;
4672 if (inst
.operands
[i
].negative
)
4674 inst
.operands
[i
].negative
= 0;
4678 if (group_relocations
4679 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4681 struct group_reloc_table_entry
*entry
;
4683 /* Skip over the #: or : sequence. */
4689 /* Try to parse a group relocation. Anything else is an
4691 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4693 inst
.error
= _("unknown group relocation");
4694 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4697 /* We now have the group relocation table entry corresponding to
4698 the name in the assembler source. Next, we parse the
4700 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4701 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4703 /* Record the relocation type. */
4707 inst
.reloc
.type
= entry
->ldr_code
;
4711 inst
.reloc
.type
= entry
->ldrs_code
;
4715 inst
.reloc
.type
= entry
->ldc_code
;
4722 if (inst
.reloc
.type
== 0)
4724 inst
.error
= _("this group relocation is not allowed on this instruction");
4725 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4729 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4730 return PARSE_OPERAND_FAIL
;
4734 if (skip_past_char (&p
, ']') == FAIL
)
4736 inst
.error
= _("']' expected");
4737 return PARSE_OPERAND_FAIL
;
4740 if (skip_past_char (&p
, '!') == SUCCESS
)
4741 inst
.operands
[i
].writeback
= 1;
4743 else if (skip_past_comma (&p
) == SUCCESS
)
4745 if (skip_past_char (&p
, '{') == SUCCESS
)
4747 /* [Rn], {expr} - unindexed, with option */
4748 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4749 0, 255, TRUE
) == FAIL
)
4750 return PARSE_OPERAND_FAIL
;
4752 if (skip_past_char (&p
, '}') == FAIL
)
4754 inst
.error
= _("'}' expected at end of 'option' field");
4755 return PARSE_OPERAND_FAIL
;
4757 if (inst
.operands
[i
].preind
)
4759 inst
.error
= _("cannot combine index with option");
4760 return PARSE_OPERAND_FAIL
;
4763 return PARSE_OPERAND_SUCCESS
;
4767 inst
.operands
[i
].postind
= 1;
4768 inst
.operands
[i
].writeback
= 1;
4770 if (inst
.operands
[i
].preind
)
4772 inst
.error
= _("cannot combine pre- and post-indexing");
4773 return PARSE_OPERAND_FAIL
;
4777 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4779 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4781 /* We might be using the immediate for alignment already. If we
4782 are, OR the register number into the low-order bits. */
4783 if (inst
.operands
[i
].immisalign
)
4784 inst
.operands
[i
].imm
|= reg
;
4786 inst
.operands
[i
].imm
= reg
;
4787 inst
.operands
[i
].immisreg
= 1;
4789 if (skip_past_comma (&p
) == SUCCESS
)
4790 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4791 return PARSE_OPERAND_FAIL
;
4795 if (inst
.operands
[i
].negative
)
4797 inst
.operands
[i
].negative
= 0;
4800 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4801 return PARSE_OPERAND_FAIL
;
4806 /* If at this point neither .preind nor .postind is set, we have a
4807 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4808 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4810 inst
.operands
[i
].preind
= 1;
4811 inst
.reloc
.exp
.X_op
= O_constant
;
4812 inst
.reloc
.exp
.X_add_number
= 0;
4815 return PARSE_OPERAND_SUCCESS
;
4819 parse_address (char **str
, int i
)
4821 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4825 static parse_operand_result
4826 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4828 return parse_address_main (str
, i
, 1, type
);
4831 /* Parse an operand for a MOVW or MOVT instruction. */
4833 parse_half (char **str
)
4838 skip_past_char (&p
, '#');
4839 if (strncasecmp (p
, ":lower16:", 9) == 0)
4840 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4841 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4842 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4844 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4847 skip_whitespace (p
);
4850 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4853 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4855 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4857 inst
.error
= _("constant expression expected");
4860 if (inst
.reloc
.exp
.X_add_number
< 0
4861 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4863 inst
.error
= _("immediate value out of range");
4871 /* Miscellaneous. */
4873 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4874 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4876 parse_psr (char **str
)
4879 unsigned long psr_field
;
4880 const struct asm_psr
*psr
;
4883 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4884 feature for ease of use and backwards compatibility. */
4886 if (strncasecmp (p
, "SPSR", 4) == 0)
4887 psr_field
= SPSR_BIT
;
4888 else if (strncasecmp (p
, "CPSR", 4) == 0)
4895 while (ISALNUM (*p
) || *p
== '_');
4897 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4908 /* A suffix follows. */
4914 while (ISALNUM (*p
) || *p
== '_');
4916 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4920 psr_field
|= psr
->field
;
4925 goto error
; /* Garbage after "[CS]PSR". */
4927 psr_field
|= (PSR_c
| PSR_f
);
4933 inst
.error
= _("flag for {c}psr instruction expected");
4937 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4938 value suitable for splatting into the AIF field of the instruction. */
4941 parse_cps_flags (char **str
)
4950 case '\0': case ',':
4953 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4954 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4955 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4958 inst
.error
= _("unrecognized CPS flag");
4963 if (saw_a_flag
== 0)
4965 inst
.error
= _("missing CPS flags");
4973 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4974 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4977 parse_endian_specifier (char **str
)
4982 if (strncasecmp (s
, "BE", 2))
4984 else if (strncasecmp (s
, "LE", 2))
4988 inst
.error
= _("valid endian specifiers are be or le");
4992 if (ISALNUM (s
[2]) || s
[2] == '_')
4994 inst
.error
= _("valid endian specifiers are be or le");
4999 return little_endian
;
5002 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5003 value suitable for poking into the rotate field of an sxt or sxta
5004 instruction, or FAIL on error. */
5007 parse_ror (char **str
)
5012 if (strncasecmp (s
, "ROR", 3) == 0)
5016 inst
.error
= _("missing rotation field after comma");
5020 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5025 case 0: *str
= s
; return 0x0;
5026 case 8: *str
= s
; return 0x1;
5027 case 16: *str
= s
; return 0x2;
5028 case 24: *str
= s
; return 0x3;
5031 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5036 /* Parse a conditional code (from conds[] below). The value returned is in the
5037 range 0 .. 14, or FAIL. */
5039 parse_cond (char **str
)
5042 const struct asm_cond
*c
;
5045 while (ISALPHA (*q
))
5048 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5051 inst
.error
= _("condition required");
5059 /* Parse an option for a barrier instruction. Returns the encoding for the
5062 parse_barrier (char **str
)
5065 const struct asm_barrier_opt
*o
;
5068 while (ISALPHA (*q
))
5071 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5079 /* Parse the operands of a table branch instruction. Similar to a memory
5082 parse_tb (char **str
)
5087 if (skip_past_char (&p
, '[') == FAIL
)
5089 inst
.error
= _("'[' expected");
5093 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5095 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5098 inst
.operands
[0].reg
= reg
;
5100 if (skip_past_comma (&p
) == FAIL
)
5102 inst
.error
= _("',' expected");
5106 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5108 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5111 inst
.operands
[0].imm
= reg
;
5113 if (skip_past_comma (&p
) == SUCCESS
)
5115 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5117 if (inst
.reloc
.exp
.X_add_number
!= 1)
5119 inst
.error
= _("invalid shift");
5122 inst
.operands
[0].shifted
= 1;
5125 if (skip_past_char (&p
, ']') == FAIL
)
5127 inst
.error
= _("']' expected");
5134 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5135 information on the types the operands can take and how they are encoded.
5136 Up to four operands may be read; this function handles setting the
5137 ".present" field for each read operand itself.
5138 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5139 else returns FAIL. */
5142 parse_neon_mov (char **str
, int *which_operand
)
5144 int i
= *which_operand
, val
;
5145 enum arm_reg_type rtype
;
5147 struct neon_type_el optype
;
5149 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5151 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5152 inst
.operands
[i
].reg
= val
;
5153 inst
.operands
[i
].isscalar
= 1;
5154 inst
.operands
[i
].vectype
= optype
;
5155 inst
.operands
[i
++].present
= 1;
5157 if (skip_past_comma (&ptr
) == FAIL
)
5160 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5163 inst
.operands
[i
].reg
= val
;
5164 inst
.operands
[i
].isreg
= 1;
5165 inst
.operands
[i
].present
= 1;
5167 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5170 /* Cases 0, 1, 2, 3, 5 (D only). */
5171 if (skip_past_comma (&ptr
) == FAIL
)
5174 inst
.operands
[i
].reg
= val
;
5175 inst
.operands
[i
].isreg
= 1;
5176 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5177 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5178 inst
.operands
[i
].isvec
= 1;
5179 inst
.operands
[i
].vectype
= optype
;
5180 inst
.operands
[i
++].present
= 1;
5182 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5184 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5185 Case 13: VMOV <Sd>, <Rm> */
5186 inst
.operands
[i
].reg
= val
;
5187 inst
.operands
[i
].isreg
= 1;
5188 inst
.operands
[i
].present
= 1;
5190 if (rtype
== REG_TYPE_NQ
)
5192 first_error (_("can't use Neon quad register here"));
5195 else if (rtype
!= REG_TYPE_VFS
)
5198 if (skip_past_comma (&ptr
) == FAIL
)
5200 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5202 inst
.operands
[i
].reg
= val
;
5203 inst
.operands
[i
].isreg
= 1;
5204 inst
.operands
[i
].present
= 1;
5207 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5208 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5209 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5210 Case 10: VMOV.F32 <Sd>, #<imm>
5211 Case 11: VMOV.F64 <Dd>, #<imm> */
5212 inst
.operands
[i
].immisfloat
= 1;
5213 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5214 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5215 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5217 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5220 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5221 Case 1: VMOV<c><q> <Dd>, <Dm>
5222 Case 8: VMOV.F32 <Sd>, <Sm>
5223 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5225 inst
.operands
[i
].reg
= val
;
5226 inst
.operands
[i
].isreg
= 1;
5227 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5228 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5229 inst
.operands
[i
].isvec
= 1;
5230 inst
.operands
[i
].vectype
= optype
;
5231 inst
.operands
[i
].present
= 1;
5233 if (skip_past_comma (&ptr
) == SUCCESS
)
5238 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5241 inst
.operands
[i
].reg
= val
;
5242 inst
.operands
[i
].isreg
= 1;
5243 inst
.operands
[i
++].present
= 1;
5245 if (skip_past_comma (&ptr
) == FAIL
)
5248 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5251 inst
.operands
[i
].reg
= val
;
5252 inst
.operands
[i
].isreg
= 1;
5253 inst
.operands
[i
++].present
= 1;
5258 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5262 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5265 inst
.operands
[i
].reg
= val
;
5266 inst
.operands
[i
].isreg
= 1;
5267 inst
.operands
[i
++].present
= 1;
5269 if (skip_past_comma (&ptr
) == FAIL
)
5272 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5274 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5275 inst
.operands
[i
].reg
= val
;
5276 inst
.operands
[i
].isscalar
= 1;
5277 inst
.operands
[i
].present
= 1;
5278 inst
.operands
[i
].vectype
= optype
;
5280 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5282 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5283 inst
.operands
[i
].reg
= val
;
5284 inst
.operands
[i
].isreg
= 1;
5285 inst
.operands
[i
++].present
= 1;
5287 if (skip_past_comma (&ptr
) == FAIL
)
5290 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5293 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5297 inst
.operands
[i
].reg
= val
;
5298 inst
.operands
[i
].isreg
= 1;
5299 inst
.operands
[i
].isvec
= 1;
5300 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5301 inst
.operands
[i
].vectype
= optype
;
5302 inst
.operands
[i
].present
= 1;
5304 if (rtype
== REG_TYPE_VFS
)
5308 if (skip_past_comma (&ptr
) == FAIL
)
5310 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5313 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5316 inst
.operands
[i
].reg
= val
;
5317 inst
.operands
[i
].isreg
= 1;
5318 inst
.operands
[i
].isvec
= 1;
5319 inst
.operands
[i
].issingle
= 1;
5320 inst
.operands
[i
].vectype
= optype
;
5321 inst
.operands
[i
].present
= 1;
5324 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5328 inst
.operands
[i
].reg
= val
;
5329 inst
.operands
[i
].isreg
= 1;
5330 inst
.operands
[i
].isvec
= 1;
5331 inst
.operands
[i
].issingle
= 1;
5332 inst
.operands
[i
].vectype
= optype
;
5333 inst
.operands
[i
++].present
= 1;
5338 first_error (_("parse error"));
5342 /* Successfully parsed the operands. Update args. */
5348 first_error (_("expected comma"));
5352 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5356 /* Matcher codes for parse_operands. */
5357 enum operand_parse_code
5359 OP_stop
, /* end of line */
5361 OP_RR
, /* ARM register */
5362 OP_RRnpc
, /* ARM register, not r15 */
5363 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5364 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5365 OP_RCP
, /* Coprocessor number */
5366 OP_RCN
, /* Coprocessor register */
5367 OP_RF
, /* FPA register */
5368 OP_RVS
, /* VFP single precision register */
5369 OP_RVD
, /* VFP double precision register (0..15) */
5370 OP_RND
, /* Neon double precision register (0..31) */
5371 OP_RNQ
, /* Neon quad precision register */
5372 OP_RVSD
, /* VFP single or double precision register */
5373 OP_RNDQ
, /* Neon double or quad precision register */
5374 OP_RNSDQ
, /* Neon single, double or quad precision register */
5375 OP_RNSC
, /* Neon scalar D[X] */
5376 OP_RVC
, /* VFP control register */
5377 OP_RMF
, /* Maverick F register */
5378 OP_RMD
, /* Maverick D register */
5379 OP_RMFX
, /* Maverick FX register */
5380 OP_RMDX
, /* Maverick DX register */
5381 OP_RMAX
, /* Maverick AX register */
5382 OP_RMDS
, /* Maverick DSPSC register */
5383 OP_RIWR
, /* iWMMXt wR register */
5384 OP_RIWC
, /* iWMMXt wC register */
5385 OP_RIWG
, /* iWMMXt wCG register */
5386 OP_RXA
, /* XScale accumulator register */
5388 OP_REGLST
, /* ARM register list */
5389 OP_VRSLST
, /* VFP single-precision register list */
5390 OP_VRDLST
, /* VFP double-precision register list */
5391 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5392 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5393 OP_NSTRLST
, /* Neon element/structure list */
5395 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5396 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5397 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5398 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5399 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5400 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5401 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5402 OP_VMOV
, /* Neon VMOV operands. */
5403 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5404 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5405 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5407 OP_I0
, /* immediate zero */
5408 OP_I7
, /* immediate value 0 .. 7 */
5409 OP_I15
, /* 0 .. 15 */
5410 OP_I16
, /* 1 .. 16 */
5411 OP_I16z
, /* 0 .. 16 */
5412 OP_I31
, /* 0 .. 31 */
5413 OP_I31w
, /* 0 .. 31, optional trailing ! */
5414 OP_I32
, /* 1 .. 32 */
5415 OP_I32z
, /* 0 .. 32 */
5416 OP_I63
, /* 0 .. 63 */
5417 OP_I63s
, /* -64 .. 63 */
5418 OP_I64
, /* 1 .. 64 */
5419 OP_I64z
, /* 0 .. 64 */
5420 OP_I255
, /* 0 .. 255 */
5422 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5423 OP_I7b
, /* 0 .. 7 */
5424 OP_I15b
, /* 0 .. 15 */
5425 OP_I31b
, /* 0 .. 31 */
5427 OP_SH
, /* shifter operand */
5428 OP_SHG
, /* shifter operand with possible group relocation */
5429 OP_ADDR
, /* Memory address expression (any mode) */
5430 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5431 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5432 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5433 OP_EXP
, /* arbitrary expression */
5434 OP_EXPi
, /* same, with optional immediate prefix */
5435 OP_EXPr
, /* same, with optional relocation suffix */
5436 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5438 OP_CPSF
, /* CPS flags */
5439 OP_ENDI
, /* Endianness specifier */
5440 OP_PSR
, /* CPSR/SPSR mask for msr */
5441 OP_COND
, /* conditional code */
5442 OP_TB
, /* Table branch. */
5444 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5445 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5447 OP_RRnpc_I0
, /* ARM register or literal 0 */
5448 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5449 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5450 OP_RF_IF
, /* FPA register or immediate */
5451 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5452 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5454 /* Optional operands. */
5455 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5456 OP_oI31b
, /* 0 .. 31 */
5457 OP_oI32b
, /* 1 .. 32 */
5458 OP_oIffffb
, /* 0 .. 65535 */
5459 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5461 OP_oRR
, /* ARM register */
5462 OP_oRRnpc
, /* ARM register, not the PC */
5463 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5464 OP_oRND
, /* Optional Neon double precision register */
5465 OP_oRNQ
, /* Optional Neon quad precision register */
5466 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5467 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5468 OP_oSHll
, /* LSL immediate */
5469 OP_oSHar
, /* ASR immediate */
5470 OP_oSHllar
, /* LSL or ASR immediate */
5471 OP_oROR
, /* ROR 0/8/16/24 */
5472 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5474 OP_FIRST_OPTIONAL
= OP_oI7b
5477 /* Generic instruction operand parser. This does no encoding and no
5478 semantic validation; it merely squirrels values away in the inst
5479 structure. Returns SUCCESS or FAIL depending on whether the
5480 specified grammar matched. */
5482 parse_operands (char *str
, const unsigned char *pattern
)
5484 unsigned const char *upat
= pattern
;
5485 char *backtrack_pos
= 0;
5486 const char *backtrack_error
= 0;
5487 int i
, val
, backtrack_index
= 0;
5488 enum arm_reg_type rtype
;
5489 parse_operand_result result
;
5491 #define po_char_or_fail(chr) do { \
5492 if (skip_past_char (&str, chr) == FAIL) \
5496 #define po_reg_or_fail(regtype) do { \
5497 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5498 &inst.operands[i].vectype); \
5501 first_error (_(reg_expected_msgs[regtype])); \
5504 inst.operands[i].reg = val; \
5505 inst.operands[i].isreg = 1; \
5506 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5507 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5508 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5509 || rtype == REG_TYPE_VFD \
5510 || rtype == REG_TYPE_NQ); \
5513 #define po_reg_or_goto(regtype, label) do { \
5514 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5515 &inst.operands[i].vectype); \
5519 inst.operands[i].reg = val; \
5520 inst.operands[i].isreg = 1; \
5521 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5522 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5523 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5524 || rtype == REG_TYPE_VFD \
5525 || rtype == REG_TYPE_NQ); \
5528 #define po_imm_or_fail(min, max, popt) do { \
5529 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5531 inst.operands[i].imm = val; \
5534 #define po_scalar_or_goto(elsz, label) do { \
5535 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5538 inst.operands[i].reg = val; \
5539 inst.operands[i].isscalar = 1; \
5542 #define po_misc_or_fail(expr) do { \
5547 #define po_misc_or_fail_no_backtrack(expr) do { \
5549 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5550 backtrack_pos = 0; \
5551 if (result != PARSE_OPERAND_SUCCESS) \
5555 skip_whitespace (str
);
5557 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5559 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5561 /* Remember where we are in case we need to backtrack. */
5562 assert (!backtrack_pos
);
5563 backtrack_pos
= str
;
5564 backtrack_error
= inst
.error
;
5565 backtrack_index
= i
;
5568 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5569 po_char_or_fail (',');
5577 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5578 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5579 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5580 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5581 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5582 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5584 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5586 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5588 /* Also accept generic coprocessor regs for unknown registers. */
5590 po_reg_or_fail (REG_TYPE_CN
);
5592 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5593 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5594 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5595 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5596 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5597 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5598 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5599 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5600 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5601 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5603 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5605 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5606 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5608 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5610 /* Neon scalar. Using an element size of 8 means that some invalid
5611 scalars are accepted here, so deal with those in later code. */
5612 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5614 /* WARNING: We can expand to two operands here. This has the potential
5615 to totally confuse the backtracking mechanism! It will be OK at
5616 least as long as we don't try to use optional args as well,
5620 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5621 inst
.operands
[i
].present
= 1;
5623 skip_past_comma (&str
);
5624 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5627 /* Optional register operand was omitted. Unfortunately, it's in
5628 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5629 here (this is a bit grotty). */
5630 inst
.operands
[i
] = inst
.operands
[i
-1];
5631 inst
.operands
[i
-1].present
= 0;
5634 /* There's a possibility of getting a 64-bit immediate here, so
5635 we need special handling. */
5636 if (parse_big_immediate (&str
, i
) == FAIL
)
5638 inst
.error
= _("immediate value is out of range");
5646 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5649 po_imm_or_fail (0, 0, TRUE
);
5654 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5659 po_scalar_or_goto (8, try_rr
);
5662 po_reg_or_fail (REG_TYPE_RN
);
5668 po_scalar_or_goto (8, try_nsdq
);
5671 po_reg_or_fail (REG_TYPE_NSDQ
);
5677 po_scalar_or_goto (8, try_ndq
);
5680 po_reg_or_fail (REG_TYPE_NDQ
);
5686 po_scalar_or_goto (8, try_vfd
);
5689 po_reg_or_fail (REG_TYPE_VFD
);
5694 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5695 not careful then bad things might happen. */
5696 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5701 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5704 /* There's a possibility of getting a 64-bit immediate here, so
5705 we need special handling. */
5706 if (parse_big_immediate (&str
, i
) == FAIL
)
5708 inst
.error
= _("immediate value is out of range");
5716 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5719 po_imm_or_fail (0, 63, TRUE
);
5724 po_char_or_fail ('[');
5725 po_reg_or_fail (REG_TYPE_RN
);
5726 po_char_or_fail (']');
5731 po_reg_or_fail (REG_TYPE_RN
);
5732 if (skip_past_char (&str
, '!') == SUCCESS
)
5733 inst
.operands
[i
].writeback
= 1;
5737 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5738 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5739 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5740 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5741 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5742 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5743 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5744 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5745 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5746 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5747 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5748 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5750 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5752 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5753 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5755 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5756 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5757 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5759 /* Immediate variants */
5761 po_char_or_fail ('{');
5762 po_imm_or_fail (0, 255, TRUE
);
5763 po_char_or_fail ('}');
5767 /* The expression parser chokes on a trailing !, so we have
5768 to find it first and zap it. */
5771 while (*s
&& *s
!= ',')
5776 inst
.operands
[i
].writeback
= 1;
5778 po_imm_or_fail (0, 31, TRUE
);
5786 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5791 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5796 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5798 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5800 val
= parse_reloc (&str
);
5803 inst
.error
= _("unrecognized relocation suffix");
5806 else if (val
!= BFD_RELOC_UNUSED
)
5808 inst
.operands
[i
].imm
= val
;
5809 inst
.operands
[i
].hasreloc
= 1;
5814 /* Operand for MOVW or MOVT. */
5816 po_misc_or_fail (parse_half (&str
));
5819 /* Register or expression */
5820 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5821 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5823 /* Register or immediate */
5824 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5825 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5827 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5829 if (!is_immediate_prefix (*str
))
5832 val
= parse_fpa_immediate (&str
);
5835 /* FPA immediates are encoded as registers 8-15.
5836 parse_fpa_immediate has already applied the offset. */
5837 inst
.operands
[i
].reg
= val
;
5838 inst
.operands
[i
].isreg
= 1;
5841 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5842 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5844 /* Two kinds of register */
5847 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5849 || (rege
->type
!= REG_TYPE_MMXWR
5850 && rege
->type
!= REG_TYPE_MMXWC
5851 && rege
->type
!= REG_TYPE_MMXWCG
))
5853 inst
.error
= _("iWMMXt data or control register expected");
5856 inst
.operands
[i
].reg
= rege
->number
;
5857 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5863 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5865 || (rege
->type
!= REG_TYPE_MMXWC
5866 && rege
->type
!= REG_TYPE_MMXWCG
))
5868 inst
.error
= _("iWMMXt control register expected");
5871 inst
.operands
[i
].reg
= rege
->number
;
5872 inst
.operands
[i
].isreg
= 1;
5877 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5878 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5879 case OP_oROR
: val
= parse_ror (&str
); break;
5880 case OP_PSR
: val
= parse_psr (&str
); break;
5881 case OP_COND
: val
= parse_cond (&str
); break;
5882 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5885 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5886 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5889 val
= parse_psr (&str
);
5893 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5896 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5898 if (strncasecmp (str
, "APSR_", 5) == 0)
5905 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5906 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5907 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5908 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5909 default: found
= 16;
5913 inst
.operands
[i
].isvec
= 1;
5920 po_misc_or_fail (parse_tb (&str
));
5923 /* Register lists */
5925 val
= parse_reg_list (&str
);
5928 inst
.operands
[1].writeback
= 1;
5934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5938 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5942 /* Allow Q registers too. */
5943 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5948 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5950 inst
.operands
[i
].issingle
= 1;
5955 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5960 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5961 &inst
.operands
[i
].vectype
);
5964 /* Addressing modes */
5966 po_misc_or_fail (parse_address (&str
, i
));
5970 po_misc_or_fail_no_backtrack (
5971 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5975 po_misc_or_fail_no_backtrack (
5976 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5980 po_misc_or_fail_no_backtrack (
5981 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5985 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5989 po_misc_or_fail_no_backtrack (
5990 parse_shifter_operand_group_reloc (&str
, i
));
5994 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5998 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6002 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6006 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6009 /* Various value-based sanity checks and shared operations. We
6010 do not signal immediate failures for the register constraints;
6011 this allows a syntax error to take precedence. */
6020 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6021 inst
.error
= BAD_PC
;
6039 inst
.operands
[i
].imm
= val
;
6046 /* If we get here, this operand was successfully parsed. */
6047 inst
.operands
[i
].present
= 1;
6051 inst
.error
= BAD_ARGS
;
6056 /* The parse routine should already have set inst.error, but set a
6057 default here just in case. */
6059 inst
.error
= _("syntax error");
6063 /* Do not backtrack over a trailing optional argument that
6064 absorbed some text. We will only fail again, with the
6065 'garbage following instruction' error message, which is
6066 probably less helpful than the current one. */
6067 if (backtrack_index
== i
&& backtrack_pos
!= str
6068 && upat
[i
+1] == OP_stop
)
6071 inst
.error
= _("syntax error");
6075 /* Try again, skipping the optional argument at backtrack_pos. */
6076 str
= backtrack_pos
;
6077 inst
.error
= backtrack_error
;
6078 inst
.operands
[backtrack_index
].present
= 0;
6079 i
= backtrack_index
;
6083 /* Check that we have parsed all the arguments. */
6084 if (*str
!= '\0' && !inst
.error
)
6085 inst
.error
= _("garbage following instruction");
6087 return inst
.error
? FAIL
: SUCCESS
;
6090 #undef po_char_or_fail
6091 #undef po_reg_or_fail
6092 #undef po_reg_or_goto
6093 #undef po_imm_or_fail
6094 #undef po_scalar_or_fail
6096 /* Shorthand macro for instruction encoding functions issuing errors. */
6097 #define constraint(expr, err) do { \
6105 /* Functions for operand encoding. ARM, then Thumb. */
6107 #define rotate_left(v, n) (v << n | v >> (32 - n))
6109 /* If VAL can be encoded in the immediate field of an ARM instruction,
6110 return the encoded form. Otherwise, return FAIL. */
6113 encode_arm_immediate (unsigned int val
)
6117 for (i
= 0; i
< 32; i
+= 2)
6118 if ((a
= rotate_left (val
, i
)) <= 0xff)
6119 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6124 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6125 return the encoded form. Otherwise, return FAIL. */
6127 encode_thumb32_immediate (unsigned int val
)
6134 for (i
= 1; i
<= 24; i
++)
6137 if ((val
& ~(0xff << i
)) == 0)
6138 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6142 if (val
== ((a
<< 16) | a
))
6144 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6148 if (val
== ((a
<< 16) | a
))
6149 return 0x200 | (a
>> 8);
6153 /* Encode a VFP SP or DP register number into inst.instruction. */
6156 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6158 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6161 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6164 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6167 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6172 first_error (_("D register out of range for selected VFP version"));
6180 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6184 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6188 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6192 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6196 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6200 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6208 /* Encode a <shift> in an ARM-format instruction. The immediate,
6209 if any, is handled by md_apply_fix. */
6211 encode_arm_shift (int i
)
6213 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6214 inst
.instruction
|= SHIFT_ROR
<< 5;
6217 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6218 if (inst
.operands
[i
].immisreg
)
6220 inst
.instruction
|= SHIFT_BY_REG
;
6221 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6224 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6229 encode_arm_shifter_operand (int i
)
6231 if (inst
.operands
[i
].isreg
)
6233 inst
.instruction
|= inst
.operands
[i
].reg
;
6234 encode_arm_shift (i
);
6237 inst
.instruction
|= INST_IMMEDIATE
;
6240 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6242 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6244 assert (inst
.operands
[i
].isreg
);
6245 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6247 if (inst
.operands
[i
].preind
)
6251 inst
.error
= _("instruction does not accept preindexed addressing");
6254 inst
.instruction
|= PRE_INDEX
;
6255 if (inst
.operands
[i
].writeback
)
6256 inst
.instruction
|= WRITE_BACK
;
6259 else if (inst
.operands
[i
].postind
)
6261 assert (inst
.operands
[i
].writeback
);
6263 inst
.instruction
|= WRITE_BACK
;
6265 else /* unindexed - only for coprocessor */
6267 inst
.error
= _("instruction does not accept unindexed addressing");
6271 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6272 && (((inst
.instruction
& 0x000f0000) >> 16)
6273 == ((inst
.instruction
& 0x0000f000) >> 12)))
6274 as_warn ((inst
.instruction
& LOAD_BIT
)
6275 ? _("destination register same as write-back base")
6276 : _("source register same as write-back base"));
6279 /* inst.operands[i] was set up by parse_address. Encode it into an
6280 ARM-format mode 2 load or store instruction. If is_t is true,
6281 reject forms that cannot be used with a T instruction (i.e. not
6284 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6286 encode_arm_addr_mode_common (i
, is_t
);
6288 if (inst
.operands
[i
].immisreg
)
6290 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6291 inst
.instruction
|= inst
.operands
[i
].imm
;
6292 if (!inst
.operands
[i
].negative
)
6293 inst
.instruction
|= INDEX_UP
;
6294 if (inst
.operands
[i
].shifted
)
6296 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6297 inst
.instruction
|= SHIFT_ROR
<< 5;
6300 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6301 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6305 else /* immediate offset in inst.reloc */
6307 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6308 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6312 /* inst.operands[i] was set up by parse_address. Encode it into an
6313 ARM-format mode 3 load or store instruction. Reject forms that
6314 cannot be used with such instructions. If is_t is true, reject
6315 forms that cannot be used with a T instruction (i.e. not
6318 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6320 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6322 inst
.error
= _("instruction does not accept scaled register index");
6326 encode_arm_addr_mode_common (i
, is_t
);
6328 if (inst
.operands
[i
].immisreg
)
6330 inst
.instruction
|= inst
.operands
[i
].imm
;
6331 if (!inst
.operands
[i
].negative
)
6332 inst
.instruction
|= INDEX_UP
;
6334 else /* immediate offset in inst.reloc */
6336 inst
.instruction
|= HWOFFSET_IMM
;
6337 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6338 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6342 /* inst.operands[i] was set up by parse_address. Encode it into an
6343 ARM-format instruction. Reject all forms which cannot be encoded
6344 into a coprocessor load/store instruction. If wb_ok is false,
6345 reject use of writeback; if unind_ok is false, reject use of
6346 unindexed addressing. If reloc_override is not 0, use it instead
6347 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6348 (in which case it is preserved). */
6351 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6353 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6355 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6357 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6359 assert (!inst
.operands
[i
].writeback
);
6362 inst
.error
= _("instruction does not support unindexed addressing");
6365 inst
.instruction
|= inst
.operands
[i
].imm
;
6366 inst
.instruction
|= INDEX_UP
;
6370 if (inst
.operands
[i
].preind
)
6371 inst
.instruction
|= PRE_INDEX
;
6373 if (inst
.operands
[i
].writeback
)
6375 if (inst
.operands
[i
].reg
== REG_PC
)
6377 inst
.error
= _("pc may not be used with write-back");
6382 inst
.error
= _("instruction does not support writeback");
6385 inst
.instruction
|= WRITE_BACK
;
6389 inst
.reloc
.type
= reloc_override
;
6390 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6391 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6392 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6395 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6397 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6403 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6404 Determine whether it can be performed with a move instruction; if
6405 it can, convert inst.instruction to that move instruction and
6406 return 1; if it can't, convert inst.instruction to a literal-pool
6407 load and return 0. If this is not a valid thing to do in the
6408 current context, set inst.error and return 1.
6410 inst.operands[i] describes the destination register. */
6413 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6418 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6422 if ((inst
.instruction
& tbit
) == 0)
6424 inst
.error
= _("invalid pseudo operation");
6427 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6429 inst
.error
= _("constant expression expected");
6432 if (inst
.reloc
.exp
.X_op
== O_constant
)
6436 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6438 /* This can be done with a mov(1) instruction. */
6439 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6440 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6446 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6449 /* This can be done with a mov instruction. */
6450 inst
.instruction
&= LITERAL_MASK
;
6451 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6452 inst
.instruction
|= value
& 0xfff;
6456 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6459 /* This can be done with a mvn instruction. */
6460 inst
.instruction
&= LITERAL_MASK
;
6461 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6462 inst
.instruction
|= value
& 0xfff;
6468 if (add_to_lit_pool () == FAIL
)
6470 inst
.error
= _("literal pool insertion failed");
6473 inst
.operands
[1].reg
= REG_PC
;
6474 inst
.operands
[1].isreg
= 1;
6475 inst
.operands
[1].preind
= 1;
6476 inst
.reloc
.pc_rel
= 1;
6477 inst
.reloc
.type
= (thumb_p
6478 ? BFD_RELOC_ARM_THUMB_OFFSET
6480 ? BFD_RELOC_ARM_HWLITERAL
6481 : BFD_RELOC_ARM_LITERAL
));
6485 /* Functions for instruction encoding, sorted by sub-architecture.
6486 First some generics; their names are taken from the conventional
6487 bit positions for register arguments in ARM format instructions. */
6497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6504 inst
.instruction
|= inst
.operands
[1].reg
;
6510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6511 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6517 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6518 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6524 unsigned Rn
= inst
.operands
[2].reg
;
6525 /* Enforce restrictions on SWP instruction. */
6526 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6527 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6528 _("Rn must not overlap other operands"));
6529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6530 inst
.instruction
|= inst
.operands
[1].reg
;
6531 inst
.instruction
|= Rn
<< 16;
6537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6538 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6539 inst
.instruction
|= inst
.operands
[2].reg
;
6545 inst
.instruction
|= inst
.operands
[0].reg
;
6546 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6547 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6553 inst
.instruction
|= inst
.operands
[0].imm
;
6559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6560 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6563 /* ARM instructions, in alphabetical order by function name (except
6564 that wrapper functions appear immediately after the function they
6567 /* This is a pseudo-op of the form "adr rd, label" to be converted
6568 into a relative address of the form "add rd, pc, #label-.-8". */
6573 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6575 /* Frag hacking will turn this into a sub instruction if the offset turns
6576 out to be negative. */
6577 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6578 inst
.reloc
.pc_rel
= 1;
6579 inst
.reloc
.exp
.X_add_number
-= 8;
6582 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6583 into a relative address of the form:
6584 add rd, pc, #low(label-.-8)"
6585 add rd, rd, #high(label-.-8)" */
6590 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6592 /* Frag hacking will turn this into a sub instruction if the offset turns
6593 out to be negative. */
6594 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6595 inst
.reloc
.pc_rel
= 1;
6596 inst
.size
= INSN_SIZE
* 2;
6597 inst
.reloc
.exp
.X_add_number
-= 8;
6603 if (!inst
.operands
[1].present
)
6604 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6607 encode_arm_shifter_operand (2);
6613 if (inst
.operands
[0].present
)
6615 constraint ((inst
.instruction
& 0xf0) != 0x40
6616 && inst
.operands
[0].imm
!= 0xf,
6617 _("bad barrier type"));
6618 inst
.instruction
|= inst
.operands
[0].imm
;
6621 inst
.instruction
|= 0xf;
6627 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6628 constraint (msb
> 32, _("bit-field extends past end of register"));
6629 /* The instruction encoding stores the LSB and MSB,
6630 not the LSB and width. */
6631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6632 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6633 inst
.instruction
|= (msb
- 1) << 16;
6641 /* #0 in second position is alternative syntax for bfc, which is
6642 the same instruction but with REG_PC in the Rm field. */
6643 if (!inst
.operands
[1].isreg
)
6644 inst
.operands
[1].reg
= REG_PC
;
6646 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6647 constraint (msb
> 32, _("bit-field extends past end of register"));
6648 /* The instruction encoding stores the LSB and MSB,
6649 not the LSB and width. */
6650 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6651 inst
.instruction
|= inst
.operands
[1].reg
;
6652 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6653 inst
.instruction
|= (msb
- 1) << 16;
6659 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6660 _("bit-field extends past end of register"));
6661 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6662 inst
.instruction
|= inst
.operands
[1].reg
;
6663 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6664 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6667 /* ARM V5 breakpoint instruction (argument parse)
6668 BKPT <16 bit unsigned immediate>
6669 Instruction is not conditional.
6670 The bit pattern given in insns[] has the COND_ALWAYS condition,
6671 and it is an error if the caller tried to override that. */
6676 /* Top 12 of 16 bits to bits 19:8. */
6677 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6679 /* Bottom 4 of 16 bits to bits 3:0. */
6680 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6684 encode_branch (int default_reloc
)
6686 if (inst
.operands
[0].hasreloc
)
6688 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6689 _("the only suffix valid here is '(plt)'"));
6690 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6694 inst
.reloc
.type
= default_reloc
;
6696 inst
.reloc
.pc_rel
= 1;
6703 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6704 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6707 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6714 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6716 if (inst
.cond
== COND_ALWAYS
)
6717 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6719 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6723 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6726 /* ARM V5 branch-link-exchange instruction (argument parse)
6727 BLX <target_addr> ie BLX(1)
6728 BLX{<condition>} <Rm> ie BLX(2)
6729 Unfortunately, there are two different opcodes for this mnemonic.
6730 So, the insns[].value is not used, and the code here zaps values
6731 into inst.instruction.
6732 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6737 if (inst
.operands
[0].isreg
)
6739 /* Arg is a register; the opcode provided by insns[] is correct.
6740 It is not illegal to do "blx pc", just useless. */
6741 if (inst
.operands
[0].reg
== REG_PC
)
6742 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6744 inst
.instruction
|= inst
.operands
[0].reg
;
6748 /* Arg is an address; this instruction cannot be executed
6749 conditionally, and the opcode must be adjusted. */
6750 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6751 inst
.instruction
= 0xfa000000;
6753 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6754 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6757 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6764 bfd_boolean want_reloc
;
6766 if (inst
.operands
[0].reg
== REG_PC
)
6767 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6769 inst
.instruction
|= inst
.operands
[0].reg
;
6770 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6771 it is for ARMv4t or earlier. */
6772 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6773 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6776 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6780 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6784 /* ARM v5TEJ. Jump to Jazelle code. */
6789 if (inst
.operands
[0].reg
== REG_PC
)
6790 as_tsktsk (_("use of r15 in bxj is not really useful"));
6792 inst
.instruction
|= inst
.operands
[0].reg
;
6795 /* Co-processor data operation:
6796 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6797 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6801 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6802 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6803 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6804 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6805 inst
.instruction
|= inst
.operands
[4].reg
;
6806 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6812 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6813 encode_arm_shifter_operand (1);
6816 /* Transfer between coprocessor and ARM registers.
6817 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6822 No special properties. */
6827 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6828 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6829 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6830 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6831 inst
.instruction
|= inst
.operands
[4].reg
;
6832 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6835 /* Transfer between coprocessor register and pair of ARM registers.
6836 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6841 Two XScale instructions are special cases of these:
6843 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6844 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6846 Result unpredictable if Rd or Rn is R15. */
6851 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6852 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6853 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6854 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6855 inst
.instruction
|= inst
.operands
[4].reg
;
6861 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6862 if (inst
.operands
[1].present
)
6864 inst
.instruction
|= CPSI_MMOD
;
6865 inst
.instruction
|= inst
.operands
[1].imm
;
6872 inst
.instruction
|= inst
.operands
[0].imm
;
6878 /* There is no IT instruction in ARM mode. We
6879 process it but do not generate code for it. */
6886 int base_reg
= inst
.operands
[0].reg
;
6887 int range
= inst
.operands
[1].imm
;
6889 inst
.instruction
|= base_reg
<< 16;
6890 inst
.instruction
|= range
;
6892 if (inst
.operands
[1].writeback
)
6893 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6895 if (inst
.operands
[0].writeback
)
6897 inst
.instruction
|= WRITE_BACK
;
6898 /* Check for unpredictable uses of writeback. */
6899 if (inst
.instruction
& LOAD_BIT
)
6901 /* Not allowed in LDM type 2. */
6902 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6903 && ((range
& (1 << REG_PC
)) == 0))
6904 as_warn (_("writeback of base register is UNPREDICTABLE"));
6905 /* Only allowed if base reg not in list for other types. */
6906 else if (range
& (1 << base_reg
))
6907 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6911 /* Not allowed for type 2. */
6912 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6913 as_warn (_("writeback of base register is UNPREDICTABLE"));
6914 /* Only allowed if base reg not in list, or first in list. */
6915 else if ((range
& (1 << base_reg
))
6916 && (range
& ((1 << base_reg
) - 1)))
6917 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6922 /* ARMv5TE load-consecutive (argument parse)
6931 constraint (inst
.operands
[0].reg
% 2 != 0,
6932 _("first destination register must be even"));
6933 constraint (inst
.operands
[1].present
6934 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6935 _("can only load two consecutive registers"));
6936 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6937 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6939 if (!inst
.operands
[1].present
)
6940 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6942 if (inst
.instruction
& LOAD_BIT
)
6944 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6945 register and the first register written; we have to diagnose
6946 overlap between the base and the second register written here. */
6948 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6949 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6950 as_warn (_("base register written back, and overlaps "
6951 "second destination register"));
6953 /* For an index-register load, the index register must not overlap the
6954 destination (even if not write-back). */
6955 else if (inst
.operands
[2].immisreg
6956 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6957 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6958 as_warn (_("index register overlaps destination register"));
6961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6962 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6968 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6969 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6970 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6971 || inst
.operands
[1].negative
6972 /* This can arise if the programmer has written
6974 or if they have mistakenly used a register name as the last
6977 It is very difficult to distinguish between these two cases
6978 because "rX" might actually be a label. ie the register
6979 name has been occluded by a symbol of the same name. So we
6980 just generate a general 'bad addressing mode' type error
6981 message and leave it up to the programmer to discover the
6982 true cause and fix their mistake. */
6983 || (inst
.operands
[1].reg
== REG_PC
),
6986 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6987 || inst
.reloc
.exp
.X_add_number
!= 0,
6988 _("offset must be zero in ARM encoding"));
6990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6991 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6992 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6998 constraint (inst
.operands
[0].reg
% 2 != 0,
6999 _("even register required"));
7000 constraint (inst
.operands
[1].present
7001 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7002 _("can only load two consecutive registers"));
7003 /* If op 1 were present and equal to PC, this function wouldn't
7004 have been called in the first place. */
7005 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7008 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7015 if (!inst
.operands
[1].isreg
)
7016 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7018 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7024 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7026 if (inst
.operands
[1].preind
)
7028 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7029 || inst
.reloc
.exp
.X_add_number
!= 0,
7030 _("this instruction requires a post-indexed address"));
7032 inst
.operands
[1].preind
= 0;
7033 inst
.operands
[1].postind
= 1;
7034 inst
.operands
[1].writeback
= 1;
7036 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7037 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7040 /* Halfword and signed-byte load/store operations. */
7045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7046 if (!inst
.operands
[1].isreg
)
7047 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7049 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7055 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7057 if (inst
.operands
[1].preind
)
7059 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7060 || inst
.reloc
.exp
.X_add_number
!= 0,
7061 _("this instruction requires a post-indexed address"));
7063 inst
.operands
[1].preind
= 0;
7064 inst
.operands
[1].postind
= 1;
7065 inst
.operands
[1].writeback
= 1;
7067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7068 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7071 /* Co-processor register load/store.
7072 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7076 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7077 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7078 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7084 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7085 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7086 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7087 && !(inst
.instruction
& 0x00400000))
7088 as_tsktsk (_("Rd and Rm should be different in mla"));
7090 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7091 inst
.instruction
|= inst
.operands
[1].reg
;
7092 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7093 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7100 encode_arm_shifter_operand (1);
7103 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7110 top
= (inst
.instruction
& 0x00400000) != 0;
7111 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7112 _(":lower16: not allowed this instruction"));
7113 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7114 _(":upper16: not allowed instruction"));
7115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7116 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7118 imm
= inst
.reloc
.exp
.X_add_number
;
7119 /* The value is in two pieces: 0:11, 16:19. */
7120 inst
.instruction
|= (imm
& 0x00000fff);
7121 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7125 static void do_vfp_nsyn_opcode (const char *);
7128 do_vfp_nsyn_mrs (void)
7130 if (inst
.operands
[0].isvec
)
7132 if (inst
.operands
[1].reg
!= 1)
7133 first_error (_("operand 1 must be FPSCR"));
7134 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7135 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7136 do_vfp_nsyn_opcode ("fmstat");
7138 else if (inst
.operands
[1].isvec
)
7139 do_vfp_nsyn_opcode ("fmrx");
7147 do_vfp_nsyn_msr (void)
7149 if (inst
.operands
[0].isvec
)
7150 do_vfp_nsyn_opcode ("fmxr");
7160 if (do_vfp_nsyn_mrs () == SUCCESS
)
7163 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7164 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7166 _("'CPSR' or 'SPSR' expected"));
7167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7168 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7171 /* Two possible forms:
7172 "{C|S}PSR_<field>, Rm",
7173 "{C|S}PSR_f, #expression". */
7178 if (do_vfp_nsyn_msr () == SUCCESS
)
7181 inst
.instruction
|= inst
.operands
[0].imm
;
7182 if (inst
.operands
[1].isreg
)
7183 inst
.instruction
|= inst
.operands
[1].reg
;
7186 inst
.instruction
|= INST_IMMEDIATE
;
7187 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7188 inst
.reloc
.pc_rel
= 0;
7195 if (!inst
.operands
[2].present
)
7196 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7197 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7198 inst
.instruction
|= inst
.operands
[1].reg
;
7199 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7201 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7202 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7203 as_tsktsk (_("Rd and Rm should be different in mul"));
7206 /* Long Multiply Parser
7207 UMULL RdLo, RdHi, Rm, Rs
7208 SMULL RdLo, RdHi, Rm, Rs
7209 UMLAL RdLo, RdHi, Rm, Rs
7210 SMLAL RdLo, RdHi, Rm, Rs. */
7215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7216 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7217 inst
.instruction
|= inst
.operands
[2].reg
;
7218 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7220 /* rdhi and rdlo must be different. */
7221 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7222 as_tsktsk (_("rdhi and rdlo must be different"));
7224 /* rdhi, rdlo and rm must all be different before armv6. */
7225 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7226 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7227 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7228 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7234 if (inst
.operands
[0].present
)
7236 /* Architectural NOP hints are CPSR sets with no bits selected. */
7237 inst
.instruction
&= 0xf0000000;
7238 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7242 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7243 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7244 Condition defaults to COND_ALWAYS.
7245 Error if Rd, Rn or Rm are R15. */
7250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7252 inst
.instruction
|= inst
.operands
[2].reg
;
7253 if (inst
.operands
[3].present
)
7254 encode_arm_shift (3);
7257 /* ARM V6 PKHTB (Argument Parse). */
7262 if (!inst
.operands
[3].present
)
7264 /* If the shift specifier is omitted, turn the instruction
7265 into pkhbt rd, rm, rn. */
7266 inst
.instruction
&= 0xfff00010;
7267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7268 inst
.instruction
|= inst
.operands
[1].reg
;
7269 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7274 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7275 inst
.instruction
|= inst
.operands
[2].reg
;
7276 encode_arm_shift (3);
7280 /* ARMv5TE: Preload-Cache
7284 Syntactically, like LDR with B=1, W=0, L=1. */
7289 constraint (!inst
.operands
[0].isreg
,
7290 _("'[' expected after PLD mnemonic"));
7291 constraint (inst
.operands
[0].postind
,
7292 _("post-indexed expression used in preload instruction"));
7293 constraint (inst
.operands
[0].writeback
,
7294 _("writeback used in preload instruction"));
7295 constraint (!inst
.operands
[0].preind
,
7296 _("unindexed addressing used in preload instruction"));
7297 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7300 /* ARMv7: PLI <addr_mode> */
7304 constraint (!inst
.operands
[0].isreg
,
7305 _("'[' expected after PLI mnemonic"));
7306 constraint (inst
.operands
[0].postind
,
7307 _("post-indexed expression used in preload instruction"));
7308 constraint (inst
.operands
[0].writeback
,
7309 _("writeback used in preload instruction"));
7310 constraint (!inst
.operands
[0].preind
,
7311 _("unindexed addressing used in preload instruction"));
7312 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7313 inst
.instruction
&= ~PRE_INDEX
;
7319 inst
.operands
[1] = inst
.operands
[0];
7320 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7321 inst
.operands
[0].isreg
= 1;
7322 inst
.operands
[0].writeback
= 1;
7323 inst
.operands
[0].reg
= REG_SP
;
7327 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7328 word at the specified address and the following word
7330 Unconditionally executed.
7331 Error if Rn is R15. */
7336 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7337 if (inst
.operands
[0].writeback
)
7338 inst
.instruction
|= WRITE_BACK
;
7341 /* ARM V6 ssat (argument parse). */
7346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7347 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7348 inst
.instruction
|= inst
.operands
[2].reg
;
7350 if (inst
.operands
[3].present
)
7351 encode_arm_shift (3);
7354 /* ARM V6 usat (argument parse). */
7359 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7360 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7361 inst
.instruction
|= inst
.operands
[2].reg
;
7363 if (inst
.operands
[3].present
)
7364 encode_arm_shift (3);
7367 /* ARM V6 ssat16 (argument parse). */
7372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7373 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7374 inst
.instruction
|= inst
.operands
[2].reg
;
7380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7381 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7382 inst
.instruction
|= inst
.operands
[2].reg
;
7385 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7386 preserving the other bits.
7388 setend <endian_specifier>, where <endian_specifier> is either
7394 if (inst
.operands
[0].imm
)
7395 inst
.instruction
|= 0x200;
7401 unsigned int Rm
= (inst
.operands
[1].present
7402 ? inst
.operands
[1].reg
7403 : inst
.operands
[0].reg
);
7405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7406 inst
.instruction
|= Rm
;
7407 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7409 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7410 inst
.instruction
|= SHIFT_BY_REG
;
7413 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7419 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7420 inst
.reloc
.pc_rel
= 0;
7426 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7427 inst
.reloc
.pc_rel
= 0;
7430 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7431 SMLAxy{cond} Rd,Rm,Rs,Rn
7432 SMLAWy{cond} Rd,Rm,Rs,Rn
7433 Error if any register is R15. */
7438 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7439 inst
.instruction
|= inst
.operands
[1].reg
;
7440 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7441 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7444 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7445 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7446 Error if any register is R15.
7447 Warning if Rdlo == Rdhi. */
7452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7453 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7454 inst
.instruction
|= inst
.operands
[2].reg
;
7455 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7457 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7458 as_tsktsk (_("rdhi and rdlo must be different"));
7461 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7462 SMULxy{cond} Rd,Rm,Rs
7463 Error if any register is R15. */
7468 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7469 inst
.instruction
|= inst
.operands
[1].reg
;
7470 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7473 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7474 the same for both ARM and Thumb-2. */
7481 if (inst
.operands
[0].present
)
7483 reg
= inst
.operands
[0].reg
;
7484 constraint (reg
!= 13, _("SRS base register must be r13"));
7489 inst
.instruction
|= reg
<< 16;
7490 inst
.instruction
|= inst
.operands
[1].imm
;
7491 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7492 inst
.instruction
|= WRITE_BACK
;
7495 /* ARM V6 strex (argument parse). */
7500 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7501 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7502 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7503 || inst
.operands
[2].negative
7504 /* See comment in do_ldrex(). */
7505 || (inst
.operands
[2].reg
== REG_PC
),
7508 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7509 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7511 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7512 || inst
.reloc
.exp
.X_add_number
!= 0,
7513 _("offset must be zero in ARM encoding"));
7515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7516 inst
.instruction
|= inst
.operands
[1].reg
;
7517 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7518 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7524 constraint (inst
.operands
[1].reg
% 2 != 0,
7525 _("even register required"));
7526 constraint (inst
.operands
[2].present
7527 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7528 _("can only store two consecutive registers"));
7529 /* If op 2 were present and equal to PC, this function wouldn't
7530 have been called in the first place. */
7531 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7533 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7534 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7535 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7539 inst
.instruction
|= inst
.operands
[1].reg
;
7540 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7543 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7544 extends it to 32-bits, and adds the result to a value in another
7545 register. You can specify a rotation by 0, 8, 16, or 24 bits
7546 before extracting the 16-bit value.
7547 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7548 Condition defaults to COND_ALWAYS.
7549 Error if any register uses R15. */
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7555 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7556 inst
.instruction
|= inst
.operands
[2].reg
;
7557 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7562 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7563 Condition defaults to COND_ALWAYS.
7564 Error if any register uses R15. */
7569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7570 inst
.instruction
|= inst
.operands
[1].reg
;
7571 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7574 /* VFP instructions. In a logical order: SP variant first, monad
7575 before dyad, arithmetic then move then load/store. */
7578 do_vfp_sp_monadic (void)
7580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7581 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7585 do_vfp_sp_dyadic (void)
7587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7588 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7589 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7593 do_vfp_sp_compare_z (void)
7595 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7599 do_vfp_dp_sp_cvt (void)
7601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7602 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7606 do_vfp_sp_dp_cvt (void)
7608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7609 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7613 do_vfp_reg_from_sp (void)
7615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7616 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7620 do_vfp_reg2_from_sp2 (void)
7622 constraint (inst
.operands
[2].imm
!= 2,
7623 _("only two consecutive VFP SP registers allowed here"));
7624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7625 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7626 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7630 do_vfp_sp_from_reg (void)
7632 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7633 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7637 do_vfp_sp2_from_reg2 (void)
7639 constraint (inst
.operands
[0].imm
!= 2,
7640 _("only two consecutive VFP SP registers allowed here"));
7641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7642 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7643 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7647 do_vfp_sp_ldst (void)
7649 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7650 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7654 do_vfp_dp_ldst (void)
7656 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7657 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7662 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7664 if (inst
.operands
[0].writeback
)
7665 inst
.instruction
|= WRITE_BACK
;
7667 constraint (ldstm_type
!= VFP_LDSTMIA
,
7668 _("this addressing mode requires base-register writeback"));
7669 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7670 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7671 inst
.instruction
|= inst
.operands
[1].imm
;
7675 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7679 if (inst
.operands
[0].writeback
)
7680 inst
.instruction
|= WRITE_BACK
;
7682 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7683 _("this addressing mode requires base-register writeback"));
7685 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7688 count
= inst
.operands
[1].imm
<< 1;
7689 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7692 inst
.instruction
|= count
;
7696 do_vfp_sp_ldstmia (void)
7698 vfp_sp_ldstm (VFP_LDSTMIA
);
7702 do_vfp_sp_ldstmdb (void)
7704 vfp_sp_ldstm (VFP_LDSTMDB
);
7708 do_vfp_dp_ldstmia (void)
7710 vfp_dp_ldstm (VFP_LDSTMIA
);
7714 do_vfp_dp_ldstmdb (void)
7716 vfp_dp_ldstm (VFP_LDSTMDB
);
7720 do_vfp_xp_ldstmia (void)
7722 vfp_dp_ldstm (VFP_LDSTMIAX
);
7726 do_vfp_xp_ldstmdb (void)
7728 vfp_dp_ldstm (VFP_LDSTMDBX
);
7732 do_vfp_dp_rd_rm (void)
7734 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7735 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7739 do_vfp_dp_rn_rd (void)
7741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7742 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7746 do_vfp_dp_rd_rn (void)
7748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7749 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7753 do_vfp_dp_rd_rn_rm (void)
7755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7756 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7757 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7767 do_vfp_dp_rm_rd_rn (void)
7769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7770 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7771 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7774 /* VFPv3 instructions. */
7776 do_vfp_sp_const (void)
7778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7779 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7780 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7784 do_vfp_dp_const (void)
7786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7787 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7788 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7792 vfp_conv (int srcsize
)
7794 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7795 inst
.instruction
|= (immbits
& 1) << 5;
7796 inst
.instruction
|= (immbits
>> 1);
7800 do_vfp_sp_conv_16 (void)
7802 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7807 do_vfp_dp_conv_16 (void)
7809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7814 do_vfp_sp_conv_32 (void)
7816 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7821 do_vfp_dp_conv_32 (void)
7823 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7827 /* FPA instructions. Also in a logical order. */
7832 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7833 inst
.instruction
|= inst
.operands
[1].reg
;
7837 do_fpa_ldmstm (void)
7839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7840 switch (inst
.operands
[1].imm
)
7842 case 1: inst
.instruction
|= CP_T_X
; break;
7843 case 2: inst
.instruction
|= CP_T_Y
; break;
7844 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7849 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7851 /* The instruction specified "ea" or "fd", so we can only accept
7852 [Rn]{!}. The instruction does not really support stacking or
7853 unstacking, so we have to emulate these by setting appropriate
7854 bits and offsets. */
7855 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7856 || inst
.reloc
.exp
.X_add_number
!= 0,
7857 _("this instruction does not support indexing"));
7859 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7860 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7862 if (!(inst
.instruction
& INDEX_UP
))
7863 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7865 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7867 inst
.operands
[2].preind
= 0;
7868 inst
.operands
[2].postind
= 1;
7872 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7875 /* iWMMXt instructions: strictly in alphabetical order. */
7878 do_iwmmxt_tandorc (void)
7880 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7884 do_iwmmxt_textrc (void)
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7887 inst
.instruction
|= inst
.operands
[1].imm
;
7891 do_iwmmxt_textrm (void)
7893 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7894 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7895 inst
.instruction
|= inst
.operands
[2].imm
;
7899 do_iwmmxt_tinsr (void)
7901 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7902 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7903 inst
.instruction
|= inst
.operands
[2].imm
;
7907 do_iwmmxt_tmia (void)
7909 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7910 inst
.instruction
|= inst
.operands
[1].reg
;
7911 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7915 do_iwmmxt_waligni (void)
7917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[2].reg
;
7920 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7924 do_iwmmxt_wmerge (void)
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7928 inst
.instruction
|= inst
.operands
[2].reg
;
7929 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7933 do_iwmmxt_wmov (void)
7935 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7938 inst
.instruction
|= inst
.operands
[1].reg
;
7942 do_iwmmxt_wldstbh (void)
7945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7947 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7949 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7950 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7954 do_iwmmxt_wldstw (void)
7956 /* RIWR_RIWC clears .isreg for a control register. */
7957 if (!inst
.operands
[0].isreg
)
7959 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7960 inst
.instruction
|= 0xf0000000;
7963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7964 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7968 do_iwmmxt_wldstd (void)
7970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7971 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7972 && inst
.operands
[1].immisreg
)
7974 inst
.instruction
&= ~0x1a000ff;
7975 inst
.instruction
|= (0xf << 28);
7976 if (inst
.operands
[1].preind
)
7977 inst
.instruction
|= PRE_INDEX
;
7978 if (!inst
.operands
[1].negative
)
7979 inst
.instruction
|= INDEX_UP
;
7980 if (inst
.operands
[1].writeback
)
7981 inst
.instruction
|= WRITE_BACK
;
7982 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7983 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7984 inst
.instruction
|= inst
.operands
[1].imm
;
7987 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7991 do_iwmmxt_wshufh (void)
7993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7994 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7995 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7996 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8000 do_iwmmxt_wzero (void)
8002 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8003 inst
.instruction
|= inst
.operands
[0].reg
;
8004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8005 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8009 do_iwmmxt_wrwrwr_or_imm5 (void)
8011 if (inst
.operands
[2].isreg
)
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8015 _("immediate operand requires iWMMXt2"));
8017 if (inst
.operands
[2].imm
== 0)
8019 switch ((inst
.instruction
>> 20) & 0xf)
8025 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8026 inst
.operands
[2].imm
= 16;
8027 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8033 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8034 inst
.operands
[2].imm
= 32;
8035 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8042 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8044 wrn
= (inst
.instruction
>> 16) & 0xf;
8045 inst
.instruction
&= 0xff0fff0f;
8046 inst
.instruction
|= wrn
;
8047 /* Bail out here; the instruction is now assembled. */
8052 /* Map 32 -> 0, etc. */
8053 inst
.operands
[2].imm
&= 0x1f;
8054 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8058 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8059 operations first, then control, shift, and load/store. */
8061 /* Insns like "foo X,Y,Z". */
8064 do_mav_triple (void)
8066 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8067 inst
.instruction
|= inst
.operands
[1].reg
;
8068 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8071 /* Insns like "foo W,X,Y,Z".
8072 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8077 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8078 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8079 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8080 inst
.instruction
|= inst
.operands
[3].reg
;
8083 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8087 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8090 /* Maverick shift immediate instructions.
8091 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8092 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8097 int imm
= inst
.operands
[2].imm
;
8099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8100 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8102 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8103 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8104 Bit 4 should be 0. */
8105 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8107 inst
.instruction
|= imm
;
8110 /* XScale instructions. Also sorted arithmetic before move. */
8112 /* Xscale multiply-accumulate (argument parse)
8115 MIAxycc acc0,Rm,Rs. */
8120 inst
.instruction
|= inst
.operands
[1].reg
;
8121 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8124 /* Xscale move-accumulator-register (argument parse)
8126 MARcc acc0,RdLo,RdHi. */
8131 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8132 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8135 /* Xscale move-register-accumulator (argument parse)
8137 MRAcc RdLo,RdHi,acc0. */
8142 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8147 /* Encoding functions relevant only to Thumb. */
8149 /* inst.operands[i] is a shifted-register operand; encode
8150 it into inst.instruction in the format used by Thumb32. */
8153 encode_thumb32_shifted_operand (int i
)
8155 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8156 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8158 constraint (inst
.operands
[i
].immisreg
,
8159 _("shift by register not allowed in thumb mode"));
8160 inst
.instruction
|= inst
.operands
[i
].reg
;
8161 if (shift
== SHIFT_RRX
)
8162 inst
.instruction
|= SHIFT_ROR
<< 4;
8165 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8166 _("expression too complex"));
8168 constraint (value
> 32
8169 || (value
== 32 && (shift
== SHIFT_LSL
8170 || shift
== SHIFT_ROR
)),
8171 _("shift expression is too large"));
8175 else if (value
== 32)
8178 inst
.instruction
|= shift
<< 4;
8179 inst
.instruction
|= (value
& 0x1c) << 10;
8180 inst
.instruction
|= (value
& 0x03) << 6;
8185 /* inst.operands[i] was set up by parse_address. Encode it into a
8186 Thumb32 format load or store instruction. Reject forms that cannot
8187 be used with such instructions. If is_t is true, reject forms that
8188 cannot be used with a T instruction; if is_d is true, reject forms
8189 that cannot be used with a D instruction. */
8192 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8194 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8196 constraint (!inst
.operands
[i
].isreg
,
8197 _("Instruction does not support =N addresses"));
8199 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8200 if (inst
.operands
[i
].immisreg
)
8202 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8203 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8204 constraint (inst
.operands
[i
].negative
,
8205 _("Thumb does not support negative register indexing"));
8206 constraint (inst
.operands
[i
].postind
,
8207 _("Thumb does not support register post-indexing"));
8208 constraint (inst
.operands
[i
].writeback
,
8209 _("Thumb does not support register indexing with writeback"));
8210 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8211 _("Thumb supports only LSL in shifted register indexing"));
8213 inst
.instruction
|= inst
.operands
[i
].imm
;
8214 if (inst
.operands
[i
].shifted
)
8216 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8217 _("expression too complex"));
8218 constraint (inst
.reloc
.exp
.X_add_number
< 0
8219 || inst
.reloc
.exp
.X_add_number
> 3,
8220 _("shift out of range"));
8221 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8223 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8225 else if (inst
.operands
[i
].preind
)
8227 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8228 _("cannot use writeback with PC-relative addressing"));
8229 constraint (is_t
&& inst
.operands
[i
].writeback
,
8230 _("cannot use writeback with this instruction"));
8234 inst
.instruction
|= 0x01000000;
8235 if (inst
.operands
[i
].writeback
)
8236 inst
.instruction
|= 0x00200000;
8240 inst
.instruction
|= 0x00000c00;
8241 if (inst
.operands
[i
].writeback
)
8242 inst
.instruction
|= 0x00000100;
8244 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8246 else if (inst
.operands
[i
].postind
)
8248 assert (inst
.operands
[i
].writeback
);
8249 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8250 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8253 inst
.instruction
|= 0x00200000;
8255 inst
.instruction
|= 0x00000900;
8256 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8258 else /* unindexed - only for coprocessor */
8259 inst
.error
= _("instruction does not accept unindexed addressing");
8262 /* Table of Thumb instructions which exist in both 16- and 32-bit
8263 encodings (the latter only in post-V6T2 cores). The index is the
8264 value used in the insns table below. When there is more than one
8265 possible 16-bit encoding for the instruction, this table always
8267 Also contains several pseudo-instructions used during relaxation. */
8268 #define T16_32_TAB \
8269 X(adc, 4140, eb400000), \
8270 X(adcs, 4140, eb500000), \
8271 X(add, 1c00, eb000000), \
8272 X(adds, 1c00, eb100000), \
8273 X(addi, 0000, f1000000), \
8274 X(addis, 0000, f1100000), \
8275 X(add_pc,000f, f20f0000), \
8276 X(add_sp,000d, f10d0000), \
8277 X(adr, 000f, f20f0000), \
8278 X(and, 4000, ea000000), \
8279 X(ands, 4000, ea100000), \
8280 X(asr, 1000, fa40f000), \
8281 X(asrs, 1000, fa50f000), \
8282 X(b, e000, f000b000), \
8283 X(bcond, d000, f0008000), \
8284 X(bic, 4380, ea200000), \
8285 X(bics, 4380, ea300000), \
8286 X(cmn, 42c0, eb100f00), \
8287 X(cmp, 2800, ebb00f00), \
8288 X(cpsie, b660, f3af8400), \
8289 X(cpsid, b670, f3af8600), \
8290 X(cpy, 4600, ea4f0000), \
8291 X(dec_sp,80dd, f1ad0d00), \
8292 X(eor, 4040, ea800000), \
8293 X(eors, 4040, ea900000), \
8294 X(inc_sp,00dd, f10d0d00), \
8295 X(ldmia, c800, e8900000), \
8296 X(ldr, 6800, f8500000), \
8297 X(ldrb, 7800, f8100000), \
8298 X(ldrh, 8800, f8300000), \
8299 X(ldrsb, 5600, f9100000), \
8300 X(ldrsh, 5e00, f9300000), \
8301 X(ldr_pc,4800, f85f0000), \
8302 X(ldr_pc2,4800, f85f0000), \
8303 X(ldr_sp,9800, f85d0000), \
8304 X(lsl, 0000, fa00f000), \
8305 X(lsls, 0000, fa10f000), \
8306 X(lsr, 0800, fa20f000), \
8307 X(lsrs, 0800, fa30f000), \
8308 X(mov, 2000, ea4f0000), \
8309 X(movs, 2000, ea5f0000), \
8310 X(mul, 4340, fb00f000), \
8311 X(muls, 4340, ffffffff), /* no 32b muls */ \
8312 X(mvn, 43c0, ea6f0000), \
8313 X(mvns, 43c0, ea7f0000), \
8314 X(neg, 4240, f1c00000), /* rsb #0 */ \
8315 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8316 X(orr, 4300, ea400000), \
8317 X(orrs, 4300, ea500000), \
8318 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8319 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8320 X(rev, ba00, fa90f080), \
8321 X(rev16, ba40, fa90f090), \
8322 X(revsh, bac0, fa90f0b0), \
8323 X(ror, 41c0, fa60f000), \
8324 X(rors, 41c0, fa70f000), \
8325 X(sbc, 4180, eb600000), \
8326 X(sbcs, 4180, eb700000), \
8327 X(stmia, c000, e8800000), \
8328 X(str, 6000, f8400000), \
8329 X(strb, 7000, f8000000), \
8330 X(strh, 8000, f8200000), \
8331 X(str_sp,9000, f84d0000), \
8332 X(sub, 1e00, eba00000), \
8333 X(subs, 1e00, ebb00000), \
8334 X(subi, 8000, f1a00000), \
8335 X(subis, 8000, f1b00000), \
8336 X(sxtb, b240, fa4ff080), \
8337 X(sxth, b200, fa0ff080), \
8338 X(tst, 4200, ea100f00), \
8339 X(uxtb, b2c0, fa5ff080), \
8340 X(uxth, b280, fa1ff080), \
8341 X(nop, bf00, f3af8000), \
8342 X(yield, bf10, f3af8001), \
8343 X(wfe, bf20, f3af8002), \
8344 X(wfi, bf30, f3af8003), \
8345 X(sev, bf40, f3af9004), /* typo, 8004? */
8347 /* To catch errors in encoding functions, the codes are all offset by
8348 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8349 as 16-bit instructions. */
8350 #define X(a,b,c) T_MNEM_##a
8351 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8354 #define X(a,b,c) 0x##b
8355 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8356 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8359 #define X(a,b,c) 0x##c
8360 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8361 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8362 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8366 /* Thumb instruction encoders, in alphabetical order. */
8370 do_t_add_sub_w (void)
8374 Rd
= inst
.operands
[0].reg
;
8375 Rn
= inst
.operands
[1].reg
;
8377 constraint (Rd
== 15, _("PC not allowed as destination"));
8378 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8379 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8382 /* Parse an add or subtract instruction. We get here with inst.instruction
8383 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8390 Rd
= inst
.operands
[0].reg
;
8391 Rs
= (inst
.operands
[1].present
8392 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8393 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8401 flags
= (inst
.instruction
== T_MNEM_adds
8402 || inst
.instruction
== T_MNEM_subs
);
8404 narrow
= (current_it_mask
== 0);
8406 narrow
= (current_it_mask
!= 0);
8407 if (!inst
.operands
[2].isreg
)
8411 add
= (inst
.instruction
== T_MNEM_add
8412 || inst
.instruction
== T_MNEM_adds
);
8414 if (inst
.size_req
!= 4)
8416 /* Attempt to use a narrow opcode, with relaxation if
8418 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8419 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8420 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8421 opcode
= T_MNEM_add_sp
;
8422 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8423 opcode
= T_MNEM_add_pc
;
8424 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8427 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8429 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8433 inst
.instruction
= THUMB_OP16(opcode
);
8434 inst
.instruction
|= (Rd
<< 4) | Rs
;
8435 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8436 if (inst
.size_req
!= 2)
8437 inst
.relax
= opcode
;
8440 constraint (inst
.size_req
== 2, BAD_HIREG
);
8442 if (inst
.size_req
== 4
8443 || (inst
.size_req
!= 2 && !opcode
))
8447 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8448 _("only SUBS PC, LR, #const allowed"));
8449 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8450 _("expression too complex"));
8451 constraint (inst
.reloc
.exp
.X_add_number
< 0
8452 || inst
.reloc
.exp
.X_add_number
> 0xff,
8453 _("immediate value out of range"));
8454 inst
.instruction
= T2_SUBS_PC_LR
8455 | inst
.reloc
.exp
.X_add_number
;
8456 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8459 else if (Rs
== REG_PC
)
8461 /* Always use addw/subw. */
8462 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8463 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8467 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8468 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8471 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8473 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8475 inst
.instruction
|= Rd
<< 8;
8476 inst
.instruction
|= Rs
<< 16;
8481 Rn
= inst
.operands
[2].reg
;
8482 /* See if we can do this with a 16-bit instruction. */
8483 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8485 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8490 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8491 || inst
.instruction
== T_MNEM_add
)
8494 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8498 if (inst
.instruction
== T_MNEM_add
)
8502 inst
.instruction
= T_OPCODE_ADD_HI
;
8503 inst
.instruction
|= (Rd
& 8) << 4;
8504 inst
.instruction
|= (Rd
& 7);
8505 inst
.instruction
|= Rn
<< 3;
8508 /* ... because addition is commutative! */
8511 inst
.instruction
= T_OPCODE_ADD_HI
;
8512 inst
.instruction
|= (Rd
& 8) << 4;
8513 inst
.instruction
|= (Rd
& 7);
8514 inst
.instruction
|= Rs
<< 3;
8519 /* If we get here, it can't be done in 16 bits. */
8520 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8521 _("shift must be constant"));
8522 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8523 inst
.instruction
|= Rd
<< 8;
8524 inst
.instruction
|= Rs
<< 16;
8525 encode_thumb32_shifted_operand (2);
8530 constraint (inst
.instruction
== T_MNEM_adds
8531 || inst
.instruction
== T_MNEM_subs
,
8534 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8536 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8537 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8540 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8542 inst
.instruction
|= (Rd
<< 4) | Rs
;
8543 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8547 Rn
= inst
.operands
[2].reg
;
8548 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8550 /* We now have Rd, Rs, and Rn set to registers. */
8551 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8553 /* Can't do this for SUB. */
8554 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8555 inst
.instruction
= T_OPCODE_ADD_HI
;
8556 inst
.instruction
|= (Rd
& 8) << 4;
8557 inst
.instruction
|= (Rd
& 7);
8559 inst
.instruction
|= Rn
<< 3;
8561 inst
.instruction
|= Rs
<< 3;
8563 constraint (1, _("dest must overlap one source register"));
8567 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8568 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8569 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8577 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8579 /* Defer to section relaxation. */
8580 inst
.relax
= inst
.instruction
;
8581 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8582 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8584 else if (unified_syntax
&& inst
.size_req
!= 2)
8586 /* Generate a 32-bit opcode. */
8587 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8588 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8589 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8590 inst
.reloc
.pc_rel
= 1;
8594 /* Generate a 16-bit opcode. */
8595 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8596 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8597 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8598 inst
.reloc
.pc_rel
= 1;
8600 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8604 /* Arithmetic instructions for which there is just one 16-bit
8605 instruction encoding, and it allows only two low registers.
8606 For maximal compatibility with ARM syntax, we allow three register
8607 operands even when Thumb-32 instructions are not available, as long
8608 as the first two are identical. For instance, both "sbc r0,r1" and
8609 "sbc r0,r0,r1" are allowed. */
8615 Rd
= inst
.operands
[0].reg
;
8616 Rs
= (inst
.operands
[1].present
8617 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8618 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8619 Rn
= inst
.operands
[2].reg
;
8623 if (!inst
.operands
[2].isreg
)
8625 /* For an immediate, we always generate a 32-bit opcode;
8626 section relaxation will shrink it later if possible. */
8627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8628 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8629 inst
.instruction
|= Rd
<< 8;
8630 inst
.instruction
|= Rs
<< 16;
8631 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8637 /* See if we can do this with a 16-bit instruction. */
8638 if (THUMB_SETS_FLAGS (inst
.instruction
))
8639 narrow
= current_it_mask
== 0;
8641 narrow
= current_it_mask
!= 0;
8643 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8645 if (inst
.operands
[2].shifted
)
8647 if (inst
.size_req
== 4)
8653 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8654 inst
.instruction
|= Rd
;
8655 inst
.instruction
|= Rn
<< 3;
8659 /* If we get here, it can't be done in 16 bits. */
8660 constraint (inst
.operands
[2].shifted
8661 && inst
.operands
[2].immisreg
,
8662 _("shift must be constant"));
8663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8664 inst
.instruction
|= Rd
<< 8;
8665 inst
.instruction
|= Rs
<< 16;
8666 encode_thumb32_shifted_operand (2);
8671 /* On its face this is a lie - the instruction does set the
8672 flags. However, the only supported mnemonic in this mode
8674 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8676 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8677 _("unshifted register required"));
8678 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8679 constraint (Rd
!= Rs
,
8680 _("dest and source1 must be the same register"));
8682 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8683 inst
.instruction
|= Rd
;
8684 inst
.instruction
|= Rn
<< 3;
8688 /* Similarly, but for instructions where the arithmetic operation is
8689 commutative, so we can allow either of them to be different from
8690 the destination operand in a 16-bit instruction. For instance, all
8691 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8698 Rd
= inst
.operands
[0].reg
;
8699 Rs
= (inst
.operands
[1].present
8700 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8701 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8702 Rn
= inst
.operands
[2].reg
;
8706 if (!inst
.operands
[2].isreg
)
8708 /* For an immediate, we always generate a 32-bit opcode;
8709 section relaxation will shrink it later if possible. */
8710 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8711 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8712 inst
.instruction
|= Rd
<< 8;
8713 inst
.instruction
|= Rs
<< 16;
8714 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8720 /* See if we can do this with a 16-bit instruction. */
8721 if (THUMB_SETS_FLAGS (inst
.instruction
))
8722 narrow
= current_it_mask
== 0;
8724 narrow
= current_it_mask
!= 0;
8726 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8728 if (inst
.operands
[2].shifted
)
8730 if (inst
.size_req
== 4)
8737 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8738 inst
.instruction
|= Rd
;
8739 inst
.instruction
|= Rn
<< 3;
8744 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8745 inst
.instruction
|= Rd
;
8746 inst
.instruction
|= Rs
<< 3;
8751 /* If we get here, it can't be done in 16 bits. */
8752 constraint (inst
.operands
[2].shifted
8753 && inst
.operands
[2].immisreg
,
8754 _("shift must be constant"));
8755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8756 inst
.instruction
|= Rd
<< 8;
8757 inst
.instruction
|= Rs
<< 16;
8758 encode_thumb32_shifted_operand (2);
8763 /* On its face this is a lie - the instruction does set the
8764 flags. However, the only supported mnemonic in this mode
8766 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8768 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8769 _("unshifted register required"));
8770 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8772 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8773 inst
.instruction
|= Rd
;
8776 inst
.instruction
|= Rn
<< 3;
8778 inst
.instruction
|= Rs
<< 3;
8780 constraint (1, _("dest must overlap one source register"));
8787 if (inst
.operands
[0].present
)
8789 constraint ((inst
.instruction
& 0xf0) != 0x40
8790 && inst
.operands
[0].imm
!= 0xf,
8791 _("bad barrier type"));
8792 inst
.instruction
|= inst
.operands
[0].imm
;
8795 inst
.instruction
|= 0xf;
8801 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8802 constraint (msb
> 32, _("bit-field extends past end of register"));
8803 /* The instruction encoding stores the LSB and MSB,
8804 not the LSB and width. */
8805 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8806 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8807 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8808 inst
.instruction
|= msb
- 1;
8816 /* #0 in second position is alternative syntax for bfc, which is
8817 the same instruction but with REG_PC in the Rm field. */
8818 if (!inst
.operands
[1].isreg
)
8819 inst
.operands
[1].reg
= REG_PC
;
8821 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8822 constraint (msb
> 32, _("bit-field extends past end of register"));
8823 /* The instruction encoding stores the LSB and MSB,
8824 not the LSB and width. */
8825 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8826 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8827 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8828 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8829 inst
.instruction
|= msb
- 1;
8835 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8836 _("bit-field extends past end of register"));
8837 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8838 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8839 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8840 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8841 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8844 /* ARM V5 Thumb BLX (argument parse)
8845 BLX <target_addr> which is BLX(1)
8846 BLX <Rm> which is BLX(2)
8847 Unfortunately, there are two different opcodes for this mnemonic.
8848 So, the insns[].value is not used, and the code here zaps values
8849 into inst.instruction.
8851 ??? How to take advantage of the additional two bits of displacement
8852 available in Thumb32 mode? Need new relocation? */
8857 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8858 if (inst
.operands
[0].isreg
)
8859 /* We have a register, so this is BLX(2). */
8860 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8863 /* No register. This must be BLX(1). */
8864 inst
.instruction
= 0xf000e800;
8866 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8867 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8870 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8871 inst
.reloc
.pc_rel
= 1;
8881 if (current_it_mask
)
8883 /* Conditional branches inside IT blocks are encoded as unconditional
8886 /* A branch must be the last instruction in an IT block. */
8887 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8892 if (cond
!= COND_ALWAYS
)
8893 opcode
= T_MNEM_bcond
;
8895 opcode
= inst
.instruction
;
8897 if (unified_syntax
&& inst
.size_req
== 4)
8899 inst
.instruction
= THUMB_OP32(opcode
);
8900 if (cond
== COND_ALWAYS
)
8901 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8904 assert (cond
!= 0xF);
8905 inst
.instruction
|= cond
<< 22;
8906 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8911 inst
.instruction
= THUMB_OP16(opcode
);
8912 if (cond
== COND_ALWAYS
)
8913 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8916 inst
.instruction
|= cond
<< 8;
8917 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8919 /* Allow section relaxation. */
8920 if (unified_syntax
&& inst
.size_req
!= 2)
8921 inst
.relax
= opcode
;
8924 inst
.reloc
.pc_rel
= 1;
8930 constraint (inst
.cond
!= COND_ALWAYS
,
8931 _("instruction is always unconditional"));
8932 if (inst
.operands
[0].present
)
8934 constraint (inst
.operands
[0].imm
> 255,
8935 _("immediate value out of range"));
8936 inst
.instruction
|= inst
.operands
[0].imm
;
8941 do_t_branch23 (void)
8943 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8944 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8945 inst
.reloc
.pc_rel
= 1;
8947 /* If the destination of the branch is a defined symbol which does not have
8948 the THUMB_FUNC attribute, then we must be calling a function which has
8949 the (interfacearm) attribute. We look for the Thumb entry point to that
8950 function and change the branch to refer to that function instead. */
8951 if ( inst
.reloc
.exp
.X_op
== O_symbol
8952 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8953 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8954 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8955 inst
.reloc
.exp
.X_add_symbol
=
8956 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8962 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8963 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8964 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8965 should cause the alignment to be checked once it is known. This is
8966 because BX PC only works if the instruction is word aligned. */
8972 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8973 if (inst
.operands
[0].reg
== REG_PC
)
8974 as_tsktsk (_("use of r15 in bxj is not really useful"));
8976 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8982 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8983 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8984 inst
.instruction
|= inst
.operands
[1].reg
;
8990 constraint (current_it_mask
, BAD_NOT_IT
);
8991 inst
.instruction
|= inst
.operands
[0].imm
;
8997 constraint (current_it_mask
, BAD_NOT_IT
);
8999 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9000 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9002 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9003 inst
.instruction
= 0xf3af8000;
9004 inst
.instruction
|= imod
<< 9;
9005 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9006 if (inst
.operands
[1].present
)
9007 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9012 && (inst
.operands
[0].imm
& 4),
9013 _("selected processor does not support 'A' form "
9014 "of this instruction"));
9015 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9016 _("Thumb does not support the 2-argument "
9017 "form of this instruction"));
9018 inst
.instruction
|= inst
.operands
[0].imm
;
9022 /* THUMB CPY instruction (argument parse). */
9027 if (inst
.size_req
== 4)
9029 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9030 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9031 inst
.instruction
|= inst
.operands
[1].reg
;
9035 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9036 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9037 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9044 constraint (current_it_mask
, BAD_NOT_IT
);
9045 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9046 inst
.instruction
|= inst
.operands
[0].reg
;
9047 inst
.reloc
.pc_rel
= 1;
9048 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9054 inst
.instruction
|= inst
.operands
[0].imm
;
9060 if (!inst
.operands
[1].present
)
9061 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9062 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9063 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9064 inst
.instruction
|= inst
.operands
[2].reg
;
9070 if (unified_syntax
&& inst
.size_req
== 4)
9071 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9073 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9079 unsigned int cond
= inst
.operands
[0].imm
;
9081 constraint (current_it_mask
, BAD_NOT_IT
);
9082 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9085 /* If the condition is a negative condition, invert the mask. */
9086 if ((cond
& 0x1) == 0x0)
9088 unsigned int mask
= inst
.instruction
& 0x000f;
9090 if ((mask
& 0x7) == 0)
9091 /* no conversion needed */;
9092 else if ((mask
& 0x3) == 0)
9094 else if ((mask
& 0x1) == 0)
9099 inst
.instruction
&= 0xfff0;
9100 inst
.instruction
|= mask
;
9103 inst
.instruction
|= cond
<< 4;
9106 /* Helper function used for both push/pop and ldm/stm. */
9108 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9112 load
= (inst
.instruction
& (1 << 20)) != 0;
9114 if (mask
& (1 << 13))
9115 inst
.error
= _("SP not allowed in register list");
9118 if (mask
& (1 << 14)
9119 && mask
& (1 << 15))
9120 inst
.error
= _("LR and PC should not both be in register list");
9122 if ((mask
& (1 << base
)) != 0
9124 as_warn (_("base register should not be in register list "
9125 "when written back"));
9129 if (mask
& (1 << 15))
9130 inst
.error
= _("PC not allowed in register list");
9132 if (mask
& (1 << base
))
9133 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9136 if ((mask
& (mask
- 1)) == 0)
9138 /* Single register transfers implemented as str/ldr. */
9141 if (inst
.instruction
& (1 << 23))
9142 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9144 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9148 if (inst
.instruction
& (1 << 23))
9149 inst
.instruction
= 0x00800000; /* ia -> [base] */
9151 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9154 inst
.instruction
|= 0xf8400000;
9156 inst
.instruction
|= 0x00100000;
9158 mask
= ffs (mask
) - 1;
9162 inst
.instruction
|= WRITE_BACK
;
9164 inst
.instruction
|= mask
;
9165 inst
.instruction
|= base
<< 16;
9171 /* This really doesn't seem worth it. */
9172 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9173 _("expression too complex"));
9174 constraint (inst
.operands
[1].writeback
,
9175 _("Thumb load/store multiple does not support {reglist}^"));
9183 /* See if we can use a 16-bit instruction. */
9184 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9185 && inst
.size_req
!= 4
9186 && !(inst
.operands
[1].imm
& ~0xff))
9188 mask
= 1 << inst
.operands
[0].reg
;
9190 if (inst
.operands
[0].reg
<= 7
9191 && (inst
.instruction
== T_MNEM_stmia
9192 ? inst
.operands
[0].writeback
9193 : (inst
.operands
[0].writeback
9194 == !(inst
.operands
[1].imm
& mask
))))
9196 if (inst
.instruction
== T_MNEM_stmia
9197 && (inst
.operands
[1].imm
& mask
)
9198 && (inst
.operands
[1].imm
& (mask
- 1)))
9199 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9200 inst
.operands
[0].reg
);
9202 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9203 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9204 inst
.instruction
|= inst
.operands
[1].imm
;
9207 else if (inst
.operands
[0] .reg
== REG_SP
9208 && inst
.operands
[0].writeback
)
9210 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9211 ? T_MNEM_push
: T_MNEM_pop
);
9212 inst
.instruction
|= inst
.operands
[1].imm
;
9219 if (inst
.instruction
< 0xffff)
9220 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9222 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9223 inst
.operands
[0].writeback
);
9228 constraint (inst
.operands
[0].reg
> 7
9229 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9230 constraint (inst
.instruction
!= T_MNEM_ldmia
9231 && inst
.instruction
!= T_MNEM_stmia
,
9232 _("Thumb-2 instruction only valid in unified syntax"));
9233 if (inst
.instruction
== T_MNEM_stmia
)
9235 if (!inst
.operands
[0].writeback
)
9236 as_warn (_("this instruction will write back the base register"));
9237 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9238 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9239 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9240 inst
.operands
[0].reg
);
9244 if (!inst
.operands
[0].writeback
9245 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9246 as_warn (_("this instruction will write back the base register"));
9247 else if (inst
.operands
[0].writeback
9248 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9249 as_warn (_("this instruction will not write back the base register"));
9252 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9253 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9254 inst
.instruction
|= inst
.operands
[1].imm
;
9261 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9262 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9263 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9264 || inst
.operands
[1].negative
,
9267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9268 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9269 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9275 if (!inst
.operands
[1].present
)
9277 constraint (inst
.operands
[0].reg
== REG_LR
,
9278 _("r14 not allowed as first register "
9279 "when second register is omitted"));
9280 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9282 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9286 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9287 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9293 unsigned long opcode
;
9296 opcode
= inst
.instruction
;
9299 if (!inst
.operands
[1].isreg
)
9301 if (opcode
<= 0xffff)
9302 inst
.instruction
= THUMB_OP32 (opcode
);
9303 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9306 if (inst
.operands
[1].isreg
9307 && !inst
.operands
[1].writeback
9308 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9309 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9311 && inst
.size_req
!= 4)
9313 /* Insn may have a 16-bit form. */
9314 Rn
= inst
.operands
[1].reg
;
9315 if (inst
.operands
[1].immisreg
)
9317 inst
.instruction
= THUMB_OP16 (opcode
);
9319 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9322 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9323 && opcode
!= T_MNEM_ldrsb
)
9324 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9325 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9332 if (inst
.reloc
.pc_rel
)
9333 opcode
= T_MNEM_ldr_pc2
;
9335 opcode
= T_MNEM_ldr_pc
;
9339 if (opcode
== T_MNEM_ldr
)
9340 opcode
= T_MNEM_ldr_sp
;
9342 opcode
= T_MNEM_str_sp
;
9344 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9348 inst
.instruction
= inst
.operands
[0].reg
;
9349 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9351 inst
.instruction
|= THUMB_OP16 (opcode
);
9352 if (inst
.size_req
== 2)
9353 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9355 inst
.relax
= opcode
;
9359 /* Definitely a 32-bit variant. */
9360 inst
.instruction
= THUMB_OP32 (opcode
);
9361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9362 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9366 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9368 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9370 /* Only [Rn,Rm] is acceptable. */
9371 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9372 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9373 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9374 || inst
.operands
[1].negative
,
9375 _("Thumb does not support this addressing mode"));
9376 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9380 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9381 if (!inst
.operands
[1].isreg
)
9382 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9385 constraint (!inst
.operands
[1].preind
9386 || inst
.operands
[1].shifted
9387 || inst
.operands
[1].writeback
,
9388 _("Thumb does not support this addressing mode"));
9389 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9391 constraint (inst
.instruction
& 0x0600,
9392 _("byte or halfword not valid for base register"));
9393 constraint (inst
.operands
[1].reg
== REG_PC
9394 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9395 _("r15 based store not allowed"));
9396 constraint (inst
.operands
[1].immisreg
,
9397 _("invalid base register for register offset"));
9399 if (inst
.operands
[1].reg
== REG_PC
)
9400 inst
.instruction
= T_OPCODE_LDR_PC
;
9401 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9402 inst
.instruction
= T_OPCODE_LDR_SP
;
9404 inst
.instruction
= T_OPCODE_STR_SP
;
9406 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9407 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9411 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9412 if (!inst
.operands
[1].immisreg
)
9414 /* Immediate offset. */
9415 inst
.instruction
|= inst
.operands
[0].reg
;
9416 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9417 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9421 /* Register offset. */
9422 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9423 constraint (inst
.operands
[1].negative
,
9424 _("Thumb does not support this addressing mode"));
9427 switch (inst
.instruction
)
9429 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9430 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9431 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9432 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9433 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9434 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9435 case 0x5600 /* ldrsb */:
9436 case 0x5e00 /* ldrsh */: break;
9440 inst
.instruction
|= inst
.operands
[0].reg
;
9441 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9442 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9448 if (!inst
.operands
[1].present
)
9450 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9451 constraint (inst
.operands
[0].reg
== REG_LR
,
9452 _("r14 not allowed here"));
9454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9455 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9456 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9463 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9469 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9470 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9471 inst
.instruction
|= inst
.operands
[2].reg
;
9472 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9479 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9480 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9481 inst
.instruction
|= inst
.operands
[3].reg
;
9489 int r0off
= (inst
.instruction
== T_MNEM_mov
9490 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9491 unsigned long opcode
;
9493 bfd_boolean low_regs
;
9495 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9496 opcode
= inst
.instruction
;
9497 if (current_it_mask
)
9498 narrow
= opcode
!= T_MNEM_movs
;
9500 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9501 if (inst
.size_req
== 4
9502 || inst
.operands
[1].shifted
)
9505 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9506 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9507 && !inst
.operands
[1].shifted
9508 && inst
.operands
[0].reg
== REG_PC
9509 && inst
.operands
[1].reg
== REG_LR
)
9511 inst
.instruction
= T2_SUBS_PC_LR
;
9515 if (!inst
.operands
[1].isreg
)
9517 /* Immediate operand. */
9518 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9520 if (low_regs
&& narrow
)
9522 inst
.instruction
= THUMB_OP16 (opcode
);
9523 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9524 if (inst
.size_req
== 2)
9525 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9527 inst
.relax
= opcode
;
9531 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9532 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9533 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9534 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9537 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9538 && (inst
.instruction
== T_MNEM_mov
9539 || inst
.instruction
== T_MNEM_movs
))
9541 /* Register shifts are encoded as separate shift instructions. */
9542 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9544 if (current_it_mask
)
9549 if (inst
.size_req
== 4)
9552 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9555 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9558 switch (inst
.operands
[1].shift_kind
)
9561 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9564 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9567 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9570 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9576 inst
.instruction
= opcode
;
9579 inst
.instruction
|= inst
.operands
[0].reg
;
9580 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9585 inst
.instruction
|= CONDS_BIT
;
9587 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9588 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9589 inst
.instruction
|= inst
.operands
[1].imm
;
9594 /* Some mov with immediate shift have narrow variants.
9595 Register shifts are handled above. */
9596 if (low_regs
&& inst
.operands
[1].shifted
9597 && (inst
.instruction
== T_MNEM_mov
9598 || inst
.instruction
== T_MNEM_movs
))
9600 if (current_it_mask
)
9601 narrow
= (inst
.instruction
== T_MNEM_mov
);
9603 narrow
= (inst
.instruction
== T_MNEM_movs
);
9608 switch (inst
.operands
[1].shift_kind
)
9610 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9611 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9612 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9613 default: narrow
= FALSE
; break;
9619 inst
.instruction
|= inst
.operands
[0].reg
;
9620 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9621 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9625 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9626 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9627 encode_thumb32_shifted_operand (1);
9631 switch (inst
.instruction
)
9634 inst
.instruction
= T_OPCODE_MOV_HR
;
9635 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9636 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9637 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9641 /* We know we have low registers at this point.
9642 Generate ADD Rd, Rs, #0. */
9643 inst
.instruction
= T_OPCODE_ADD_I3
;
9644 inst
.instruction
|= inst
.operands
[0].reg
;
9645 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9651 inst
.instruction
= T_OPCODE_CMP_LR
;
9652 inst
.instruction
|= inst
.operands
[0].reg
;
9653 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9657 inst
.instruction
= T_OPCODE_CMP_HR
;
9658 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9659 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9660 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9668 if (inst
.operands
[1].isreg
)
9670 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9672 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9673 since a MOV instruction produces unpredictable results. */
9674 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9675 inst
.instruction
= T_OPCODE_ADD_I3
;
9677 inst
.instruction
= T_OPCODE_CMP_LR
;
9679 inst
.instruction
|= inst
.operands
[0].reg
;
9680 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9684 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9685 inst
.instruction
= T_OPCODE_MOV_HR
;
9687 inst
.instruction
= T_OPCODE_CMP_HR
;
9693 constraint (inst
.operands
[0].reg
> 7,
9694 _("only lo regs allowed with immediate"));
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9696 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9706 top
= (inst
.instruction
& 0x00800000) != 0;
9707 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9709 constraint (top
, _(":lower16: not allowed this instruction"));
9710 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9712 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9714 constraint (!top
, _(":upper16: not allowed this instruction"));
9715 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9718 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9719 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9721 imm
= inst
.reloc
.exp
.X_add_number
;
9722 inst
.instruction
|= (imm
& 0xf000) << 4;
9723 inst
.instruction
|= (imm
& 0x0800) << 15;
9724 inst
.instruction
|= (imm
& 0x0700) << 4;
9725 inst
.instruction
|= (imm
& 0x00ff);
9734 int r0off
= (inst
.instruction
== T_MNEM_mvn
9735 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9738 if (inst
.size_req
== 4
9739 || inst
.instruction
> 0xffff
9740 || inst
.operands
[1].shifted
9741 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9743 else if (inst
.instruction
== T_MNEM_cmn
)
9745 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9746 narrow
= (current_it_mask
== 0);
9748 narrow
= (current_it_mask
!= 0);
9750 if (!inst
.operands
[1].isreg
)
9752 /* For an immediate, we always generate a 32-bit opcode;
9753 section relaxation will shrink it later if possible. */
9754 if (inst
.instruction
< 0xffff)
9755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9756 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9757 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9758 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9762 /* See if we can do this with a 16-bit instruction. */
9765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9766 inst
.instruction
|= inst
.operands
[0].reg
;
9767 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9771 constraint (inst
.operands
[1].shifted
9772 && inst
.operands
[1].immisreg
,
9773 _("shift must be constant"));
9774 if (inst
.instruction
< 0xffff)
9775 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9776 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9777 encode_thumb32_shifted_operand (1);
9783 constraint (inst
.instruction
> 0xffff
9784 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9785 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9786 _("unshifted register required"));
9787 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9790 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9791 inst
.instruction
|= inst
.operands
[0].reg
;
9792 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9801 if (do_vfp_nsyn_mrs () == SUCCESS
)
9804 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9807 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9808 _("selected processor does not support "
9809 "requested special purpose register"));
9813 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9814 _("selected processor does not support "
9815 "requested special purpose register %x"));
9816 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9817 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9818 _("'CPSR' or 'SPSR' expected"));
9821 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9822 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9823 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9831 if (do_vfp_nsyn_msr () == SUCCESS
)
9834 constraint (!inst
.operands
[1].isreg
,
9835 _("Thumb encoding does not support an immediate here"));
9836 flags
= inst
.operands
[0].imm
;
9839 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9840 _("selected processor does not support "
9841 "requested special purpose register"));
9845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9846 _("selected processor does not support "
9847 "requested special purpose register"));
9850 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9851 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9852 inst
.instruction
|= (flags
& 0xff);
9853 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9859 if (!inst
.operands
[2].present
)
9860 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9862 /* There is no 32-bit MULS and no 16-bit MUL. */
9863 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9865 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9866 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9867 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9868 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9872 constraint (!unified_syntax
9873 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9874 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9877 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9878 inst
.instruction
|= inst
.operands
[0].reg
;
9880 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9881 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9882 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9883 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9885 constraint (1, _("dest must overlap one source register"));
9892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9893 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9894 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9895 inst
.instruction
|= inst
.operands
[3].reg
;
9897 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9898 as_tsktsk (_("rdhi and rdlo must be different"));
9906 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9909 inst
.instruction
|= inst
.operands
[0].imm
;
9913 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9914 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9919 constraint (inst
.operands
[0].present
,
9920 _("Thumb does not support NOP with hints"));
9921 inst
.instruction
= 0x46c0;
9932 if (THUMB_SETS_FLAGS (inst
.instruction
))
9933 narrow
= (current_it_mask
== 0);
9935 narrow
= (current_it_mask
!= 0);
9936 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9938 if (inst
.size_req
== 4)
9943 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9944 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9945 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9949 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9950 inst
.instruction
|= inst
.operands
[0].reg
;
9951 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9956 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9958 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9960 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9961 inst
.instruction
|= inst
.operands
[0].reg
;
9962 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9971 inst
.instruction
|= inst
.operands
[2].reg
;
9972 if (inst
.operands
[3].present
)
9974 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9975 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9976 _("expression too complex"));
9977 inst
.instruction
|= (val
& 0x1c) << 10;
9978 inst
.instruction
|= (val
& 0x03) << 6;
9985 if (!inst
.operands
[3].present
)
9986 inst
.instruction
&= ~0x00000020;
9993 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9997 do_t_push_pop (void)
10001 constraint (inst
.operands
[0].writeback
,
10002 _("push/pop do not support {reglist}^"));
10003 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10004 _("expression too complex"));
10006 mask
= inst
.operands
[0].imm
;
10007 if ((mask
& ~0xff) == 0)
10008 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10009 else if ((inst
.instruction
== T_MNEM_push
10010 && (mask
& ~0xff) == 1 << REG_LR
)
10011 || (inst
.instruction
== T_MNEM_pop
10012 && (mask
& ~0xff) == 1 << REG_PC
))
10014 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10015 inst
.instruction
|= THUMB_PP_PC_LR
;
10016 inst
.instruction
|= mask
& 0xff;
10018 else if (unified_syntax
)
10020 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10021 encode_thumb2_ldmstm (13, mask
, TRUE
);
10025 inst
.error
= _("invalid register list to push/pop instruction");
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10040 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10041 && inst
.size_req
!= 4)
10043 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10044 inst
.instruction
|= inst
.operands
[0].reg
;
10045 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10047 else if (unified_syntax
)
10049 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10050 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10051 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10052 inst
.instruction
|= inst
.operands
[1].reg
;
10055 inst
.error
= BAD_HIREG
;
10063 Rd
= inst
.operands
[0].reg
;
10064 Rs
= (inst
.operands
[1].present
10065 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10066 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10068 inst
.instruction
|= Rd
<< 8;
10069 inst
.instruction
|= Rs
<< 16;
10070 if (!inst
.operands
[2].isreg
)
10072 bfd_boolean narrow
;
10074 if ((inst
.instruction
& 0x00100000) != 0)
10075 narrow
= (current_it_mask
== 0);
10077 narrow
= (current_it_mask
!= 0);
10079 if (Rd
> 7 || Rs
> 7)
10082 if (inst
.size_req
== 4 || !unified_syntax
)
10085 if (inst
.reloc
.exp
.X_op
!= O_constant
10086 || inst
.reloc
.exp
.X_add_number
!= 0)
10089 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10090 relaxation, but it doesn't seem worth the hassle. */
10093 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10094 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10095 inst
.instruction
|= Rs
<< 3;
10096 inst
.instruction
|= Rd
;
10100 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10101 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10105 encode_thumb32_shifted_operand (2);
10111 constraint (current_it_mask
, BAD_NOT_IT
);
10112 if (inst
.operands
[0].imm
)
10113 inst
.instruction
|= 0x8;
10119 if (!inst
.operands
[1].present
)
10120 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10122 if (unified_syntax
)
10124 bfd_boolean narrow
;
10127 switch (inst
.instruction
)
10130 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10132 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10134 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10136 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10140 if (THUMB_SETS_FLAGS (inst
.instruction
))
10141 narrow
= (current_it_mask
== 0);
10143 narrow
= (current_it_mask
!= 0);
10144 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10146 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10148 if (inst
.operands
[2].isreg
10149 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10150 || inst
.operands
[2].reg
> 7))
10152 if (inst
.size_req
== 4)
10157 if (inst
.operands
[2].isreg
)
10159 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10160 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10161 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10162 inst
.instruction
|= inst
.operands
[2].reg
;
10166 inst
.operands
[1].shifted
= 1;
10167 inst
.operands
[1].shift_kind
= shift_kind
;
10168 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10169 ? T_MNEM_movs
: T_MNEM_mov
);
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10171 encode_thumb32_shifted_operand (1);
10172 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10173 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10178 if (inst
.operands
[2].isreg
)
10180 switch (shift_kind
)
10182 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10183 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10184 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10185 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10189 inst
.instruction
|= inst
.operands
[0].reg
;
10190 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10194 switch (shift_kind
)
10196 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10197 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10198 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10201 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10202 inst
.instruction
|= inst
.operands
[0].reg
;
10203 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10209 constraint (inst
.operands
[0].reg
> 7
10210 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10211 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10213 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10215 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10216 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10217 _("source1 and dest must be same register"));
10219 switch (inst
.instruction
)
10221 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10222 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10223 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10224 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10228 inst
.instruction
|= inst
.operands
[0].reg
;
10229 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10233 switch (inst
.instruction
)
10235 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10236 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10237 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10238 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10241 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10242 inst
.instruction
|= inst
.operands
[0].reg
;
10243 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10251 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10252 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10253 inst
.instruction
|= inst
.operands
[2].reg
;
10259 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10260 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10261 _("expression too complex"));
10262 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10263 inst
.instruction
|= (value
& 0xf000) >> 12;
10264 inst
.instruction
|= (value
& 0x0ff0);
10265 inst
.instruction
|= (value
& 0x000f) << 16;
10271 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10272 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10273 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10275 if (inst
.operands
[3].present
)
10277 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10278 _("expression too complex"));
10280 if (inst
.reloc
.exp
.X_add_number
!= 0)
10282 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10283 inst
.instruction
|= 0x00200000; /* sh bit */
10284 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10285 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10287 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10294 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10295 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10296 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10302 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10303 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10304 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10305 || inst
.operands
[2].negative
,
10308 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10309 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10310 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10311 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10317 if (!inst
.operands
[2].present
)
10318 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10320 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10321 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10322 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10323 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10326 inst
.instruction
|= inst
.operands
[0].reg
;
10327 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10328 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10329 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10335 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10337 inst
.instruction
|= inst
.operands
[2].reg
;
10338 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10344 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10345 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10346 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10348 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10349 inst
.instruction
|= inst
.operands
[0].reg
;
10350 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10352 else if (unified_syntax
)
10354 if (inst
.instruction
<= 0xffff)
10355 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10356 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10357 inst
.instruction
|= inst
.operands
[1].reg
;
10358 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10362 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10363 _("Thumb encoding does not support rotation"));
10364 constraint (1, BAD_HIREG
);
10371 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10379 half
= (inst
.instruction
& 0x10) != 0;
10380 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10381 constraint (inst
.operands
[0].immisreg
,
10382 _("instruction requires register index"));
10383 constraint (inst
.operands
[0].imm
== 15,
10384 _("PC is not a valid index register"));
10385 constraint (!half
&& inst
.operands
[0].shifted
,
10386 _("instruction does not allow shifted index"));
10387 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10393 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10394 inst
.instruction
|= inst
.operands
[1].imm
;
10395 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10397 if (inst
.operands
[3].present
)
10399 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10400 _("expression too complex"));
10401 if (inst
.reloc
.exp
.X_add_number
!= 0)
10403 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10404 inst
.instruction
|= 0x00200000; /* sh bit */
10406 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10407 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10409 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10416 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10417 inst
.instruction
|= inst
.operands
[1].imm
;
10418 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10421 /* Neon instruction encoder helpers. */
10423 /* Encodings for the different types for various Neon opcodes. */
10425 /* An "invalid" code for the following tables. */
10428 struct neon_tab_entry
10431 unsigned float_or_poly
;
10432 unsigned scalar_or_imm
;
10435 /* Map overloaded Neon opcodes to their respective encodings. */
10436 #define NEON_ENC_TAB \
10437 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10438 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10439 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10440 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10441 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10442 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10443 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10444 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10445 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10446 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10447 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10448 /* Register variants of the following two instructions are encoded as
10449 vcge / vcgt with the operands reversed. */ \
10450 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10451 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10452 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10453 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10454 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10455 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10456 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10457 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10458 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10459 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10460 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10461 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10462 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10463 X(vshl, 0x0000400, N_INV, 0x0800510), \
10464 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10465 X(vand, 0x0000110, N_INV, 0x0800030), \
10466 X(vbic, 0x0100110, N_INV, 0x0800030), \
10467 X(veor, 0x1000110, N_INV, N_INV), \
10468 X(vorn, 0x0300110, N_INV, 0x0800010), \
10469 X(vorr, 0x0200110, N_INV, 0x0800010), \
10470 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10471 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10472 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10473 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10474 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10475 X(vst1, 0x0000000, 0x0800000, N_INV), \
10476 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10477 X(vst2, 0x0000100, 0x0800100, N_INV), \
10478 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10479 X(vst3, 0x0000200, 0x0800200, N_INV), \
10480 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10481 X(vst4, 0x0000300, 0x0800300, N_INV), \
10482 X(vmovn, 0x1b20200, N_INV, N_INV), \
10483 X(vtrn, 0x1b20080, N_INV, N_INV), \
10484 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10485 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10486 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10487 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10488 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10489 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10490 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10491 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10492 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10496 #define X(OPC,I,F,S) N_MNEM_##OPC
10501 static const struct neon_tab_entry neon_enc_tab
[] =
10503 #define X(OPC,I,F,S) { (I), (F), (S) }
10508 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10509 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10510 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10511 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10512 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10513 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10514 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10515 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10516 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10517 #define NEON_ENC_SINGLE(X) \
10518 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10519 #define NEON_ENC_DOUBLE(X) \
10520 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10522 /* Define shapes for instruction operands. The following mnemonic characters
10523 are used in this table:
10525 F - VFP S<n> register
10526 D - Neon D<n> register
10527 Q - Neon Q<n> register
10531 L - D<n> register list
10533 This table is used to generate various data:
10534 - enumerations of the form NS_DDR to be used as arguments to
10536 - a table classifying shapes into single, double, quad, mixed.
10537 - a table used to drive neon_select_shape. */
10539 #define NEON_SHAPE_DEF \
10540 X(3, (D, D, D), DOUBLE), \
10541 X(3, (Q, Q, Q), QUAD), \
10542 X(3, (D, D, I), DOUBLE), \
10543 X(3, (Q, Q, I), QUAD), \
10544 X(3, (D, D, S), DOUBLE), \
10545 X(3, (Q, Q, S), QUAD), \
10546 X(2, (D, D), DOUBLE), \
10547 X(2, (Q, Q), QUAD), \
10548 X(2, (D, S), DOUBLE), \
10549 X(2, (Q, S), QUAD), \
10550 X(2, (D, R), DOUBLE), \
10551 X(2, (Q, R), QUAD), \
10552 X(2, (D, I), DOUBLE), \
10553 X(2, (Q, I), QUAD), \
10554 X(3, (D, L, D), DOUBLE), \
10555 X(2, (D, Q), MIXED), \
10556 X(2, (Q, D), MIXED), \
10557 X(3, (D, Q, I), MIXED), \
10558 X(3, (Q, D, I), MIXED), \
10559 X(3, (Q, D, D), MIXED), \
10560 X(3, (D, Q, Q), MIXED), \
10561 X(3, (Q, Q, D), MIXED), \
10562 X(3, (Q, D, S), MIXED), \
10563 X(3, (D, Q, S), MIXED), \
10564 X(4, (D, D, D, I), DOUBLE), \
10565 X(4, (Q, Q, Q, I), QUAD), \
10566 X(2, (F, F), SINGLE), \
10567 X(3, (F, F, F), SINGLE), \
10568 X(2, (F, I), SINGLE), \
10569 X(2, (F, D), MIXED), \
10570 X(2, (D, F), MIXED), \
10571 X(3, (F, F, I), MIXED), \
10572 X(4, (R, R, F, F), SINGLE), \
10573 X(4, (F, F, R, R), SINGLE), \
10574 X(3, (D, R, R), DOUBLE), \
10575 X(3, (R, R, D), DOUBLE), \
10576 X(2, (S, R), SINGLE), \
10577 X(2, (R, S), SINGLE), \
10578 X(2, (F, R), SINGLE), \
10579 X(2, (R, F), SINGLE)
10581 #define S2(A,B) NS_##A##B
10582 #define S3(A,B,C) NS_##A##B##C
10583 #define S4(A,B,C,D) NS_##A##B##C##D
10585 #define X(N, L, C) S##N L
10598 enum neon_shape_class
10606 #define X(N, L, C) SC_##C
10608 static enum neon_shape_class neon_shape_class
[] =
10626 /* Register widths of above. */
10627 static unsigned neon_shape_el_size
[] =
10638 struct neon_shape_info
10641 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10644 #define S2(A,B) { SE_##A, SE_##B }
10645 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10646 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10648 #define X(N, L, C) { N, S##N L }
10650 static struct neon_shape_info neon_shape_tab
[] =
10660 /* Bit masks used in type checking given instructions.
10661 'N_EQK' means the type must be the same as (or based on in some way) the key
10662 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10663 set, various other bits can be set as well in order to modify the meaning of
10664 the type constraint. */
10666 enum neon_type_mask
10688 N_KEY
= 0x100000, /* key element (main type specifier). */
10689 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10690 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10691 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10692 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10693 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10694 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10695 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10696 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10697 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10699 N_MAX_NONSPECIAL
= N_F64
10702 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10704 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10705 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10706 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10707 #define N_SUF_32 (N_SU_32 | N_F32)
10708 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10709 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10711 /* Pass this as the first type argument to neon_check_type to ignore types
10713 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10715 /* Select a "shape" for the current instruction (describing register types or
10716 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10717 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10718 function of operand parsing, so this function doesn't need to be called.
10719 Shapes should be listed in order of decreasing length. */
10721 static enum neon_shape
10722 neon_select_shape (enum neon_shape shape
, ...)
10725 enum neon_shape first_shape
= shape
;
10727 /* Fix missing optional operands. FIXME: we don't know at this point how
10728 many arguments we should have, so this makes the assumption that we have
10729 > 1. This is true of all current Neon opcodes, I think, but may not be
10730 true in the future. */
10731 if (!inst
.operands
[1].present
)
10732 inst
.operands
[1] = inst
.operands
[0];
10734 va_start (ap
, shape
);
10736 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10741 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10743 if (!inst
.operands
[j
].present
)
10749 switch (neon_shape_tab
[shape
].el
[j
])
10752 if (!(inst
.operands
[j
].isreg
10753 && inst
.operands
[j
].isvec
10754 && inst
.operands
[j
].issingle
10755 && !inst
.operands
[j
].isquad
))
10760 if (!(inst
.operands
[j
].isreg
10761 && inst
.operands
[j
].isvec
10762 && !inst
.operands
[j
].isquad
10763 && !inst
.operands
[j
].issingle
))
10768 if (!(inst
.operands
[j
].isreg
10769 && !inst
.operands
[j
].isvec
))
10774 if (!(inst
.operands
[j
].isreg
10775 && inst
.operands
[j
].isvec
10776 && inst
.operands
[j
].isquad
10777 && !inst
.operands
[j
].issingle
))
10782 if (!(!inst
.operands
[j
].isreg
10783 && !inst
.operands
[j
].isscalar
))
10788 if (!(!inst
.operands
[j
].isreg
10789 && inst
.operands
[j
].isscalar
))
10803 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10804 first_error (_("invalid instruction shape"));
10809 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10810 means the Q bit should be set). */
10813 neon_quad (enum neon_shape shape
)
10815 return neon_shape_class
[shape
] == SC_QUAD
;
10819 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10822 /* Allow modification to be made to types which are constrained to be
10823 based on the key element, based on bits set alongside N_EQK. */
10824 if ((typebits
& N_EQK
) != 0)
10826 if ((typebits
& N_HLF
) != 0)
10828 else if ((typebits
& N_DBL
) != 0)
10830 if ((typebits
& N_SGN
) != 0)
10831 *g_type
= NT_signed
;
10832 else if ((typebits
& N_UNS
) != 0)
10833 *g_type
= NT_unsigned
;
10834 else if ((typebits
& N_INT
) != 0)
10835 *g_type
= NT_integer
;
10836 else if ((typebits
& N_FLT
) != 0)
10837 *g_type
= NT_float
;
10838 else if ((typebits
& N_SIZ
) != 0)
10839 *g_type
= NT_untyped
;
10843 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10844 operand type, i.e. the single type specified in a Neon instruction when it
10845 is the only one given. */
10847 static struct neon_type_el
10848 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10850 struct neon_type_el dest
= *key
;
10852 assert ((thisarg
& N_EQK
) != 0);
10854 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10859 /* Convert Neon type and size into compact bitmask representation. */
10861 static enum neon_type_mask
10862 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10869 case 8: return N_8
;
10870 case 16: return N_16
;
10871 case 32: return N_32
;
10872 case 64: return N_64
;
10880 case 8: return N_I8
;
10881 case 16: return N_I16
;
10882 case 32: return N_I32
;
10883 case 64: return N_I64
;
10891 case 32: return N_F32
;
10892 case 64: return N_F64
;
10900 case 8: return N_P8
;
10901 case 16: return N_P16
;
10909 case 8: return N_S8
;
10910 case 16: return N_S16
;
10911 case 32: return N_S32
;
10912 case 64: return N_S64
;
10920 case 8: return N_U8
;
10921 case 16: return N_U16
;
10922 case 32: return N_U32
;
10923 case 64: return N_U64
;
10934 /* Convert compact Neon bitmask type representation to a type and size. Only
10935 handles the case where a single bit is set in the mask. */
10938 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10939 enum neon_type_mask mask
)
10941 if ((mask
& N_EQK
) != 0)
10944 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10946 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10948 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10950 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10955 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10957 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10958 *type
= NT_unsigned
;
10959 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10960 *type
= NT_integer
;
10961 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10962 *type
= NT_untyped
;
10963 else if ((mask
& (N_P8
| N_P16
)) != 0)
10965 else if ((mask
& (N_F32
| N_F64
)) != 0)
10973 /* Modify a bitmask of allowed types. This is only needed for type
10977 modify_types_allowed (unsigned allowed
, unsigned mods
)
10980 enum neon_el_type type
;
10986 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10988 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10990 neon_modify_type_size (mods
, &type
, &size
);
10991 destmask
|= type_chk_of_el_type (type
, size
);
10998 /* Check type and return type classification.
10999 The manual states (paraphrase): If one datatype is given, it indicates the
11001 - the second operand, if there is one
11002 - the operand, if there is no second operand
11003 - the result, if there are no operands.
11004 This isn't quite good enough though, so we use a concept of a "key" datatype
11005 which is set on a per-instruction basis, which is the one which matters when
11006 only one data type is written.
11007 Note: this function has side-effects (e.g. filling in missing operands). All
11008 Neon instructions should call it before performing bit encoding. */
11010 static struct neon_type_el
11011 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11014 unsigned i
, pass
, key_el
= 0;
11015 unsigned types
[NEON_MAX_TYPE_ELS
];
11016 enum neon_el_type k_type
= NT_invtype
;
11017 unsigned k_size
= -1u;
11018 struct neon_type_el badtype
= {NT_invtype
, -1};
11019 unsigned key_allowed
= 0;
11021 /* Optional registers in Neon instructions are always (not) in operand 1.
11022 Fill in the missing operand here, if it was omitted. */
11023 if (els
> 1 && !inst
.operands
[1].present
)
11024 inst
.operands
[1] = inst
.operands
[0];
11026 /* Suck up all the varargs. */
11028 for (i
= 0; i
< els
; i
++)
11030 unsigned thisarg
= va_arg (ap
, unsigned);
11031 if (thisarg
== N_IGNORE_TYPE
)
11036 types
[i
] = thisarg
;
11037 if ((thisarg
& N_KEY
) != 0)
11042 if (inst
.vectype
.elems
> 0)
11043 for (i
= 0; i
< els
; i
++)
11044 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11046 first_error (_("types specified in both the mnemonic and operands"));
11050 /* Duplicate inst.vectype elements here as necessary.
11051 FIXME: No idea if this is exactly the same as the ARM assembler,
11052 particularly when an insn takes one register and one non-register
11054 if (inst
.vectype
.elems
== 1 && els
> 1)
11057 inst
.vectype
.elems
= els
;
11058 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11059 for (j
= 0; j
< els
; j
++)
11061 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11064 else if (inst
.vectype
.elems
== 0 && els
> 0)
11067 /* No types were given after the mnemonic, so look for types specified
11068 after each operand. We allow some flexibility here; as long as the
11069 "key" operand has a type, we can infer the others. */
11070 for (j
= 0; j
< els
; j
++)
11071 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11072 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11074 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11076 for (j
= 0; j
< els
; j
++)
11077 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11078 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11083 first_error (_("operand types can't be inferred"));
11087 else if (inst
.vectype
.elems
!= els
)
11089 first_error (_("type specifier has the wrong number of parts"));
11093 for (pass
= 0; pass
< 2; pass
++)
11095 for (i
= 0; i
< els
; i
++)
11097 unsigned thisarg
= types
[i
];
11098 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11099 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11100 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11101 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11103 /* Decay more-specific signed & unsigned types to sign-insensitive
11104 integer types if sign-specific variants are unavailable. */
11105 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11106 && (types_allowed
& N_SU_ALL
) == 0)
11107 g_type
= NT_integer
;
11109 /* If only untyped args are allowed, decay any more specific types to
11110 them. Some instructions only care about signs for some element
11111 sizes, so handle that properly. */
11112 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11113 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11114 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11115 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11116 g_type
= NT_untyped
;
11120 if ((thisarg
& N_KEY
) != 0)
11124 key_allowed
= thisarg
& ~N_KEY
;
11129 if ((thisarg
& N_VFP
) != 0)
11131 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11132 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11134 /* In VFP mode, operands must match register widths. If we
11135 have a key operand, use its width, else use the width of
11136 the current operand. */
11142 if (regwidth
!= match
)
11144 first_error (_("operand size must match register width"));
11149 if ((thisarg
& N_EQK
) == 0)
11151 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11153 if ((given_type
& types_allowed
) == 0)
11155 first_error (_("bad type in Neon instruction"));
11161 enum neon_el_type mod_k_type
= k_type
;
11162 unsigned mod_k_size
= k_size
;
11163 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11164 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11166 first_error (_("inconsistent types in Neon instruction"));
11174 return inst
.vectype
.el
[key_el
];
11177 /* Neon-style VFP instruction forwarding. */
11179 /* Thumb VFP instructions have 0xE in the condition field. */
11182 do_vfp_cond_or_thumb (void)
11185 inst
.instruction
|= 0xe0000000;
11187 inst
.instruction
|= inst
.cond
<< 28;
11190 /* Look up and encode a simple mnemonic, for use as a helper function for the
11191 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11192 etc. It is assumed that operand parsing has already been done, and that the
11193 operands are in the form expected by the given opcode (this isn't necessarily
11194 the same as the form in which they were parsed, hence some massaging must
11195 take place before this function is called).
11196 Checks current arch version against that in the looked-up opcode. */
11199 do_vfp_nsyn_opcode (const char *opname
)
11201 const struct asm_opcode
*opcode
;
11203 opcode
= hash_find (arm_ops_hsh
, opname
);
11208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11209 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11214 inst
.instruction
= opcode
->tvalue
;
11215 opcode
->tencode ();
11219 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11220 opcode
->aencode ();
11225 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11227 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11232 do_vfp_nsyn_opcode ("fadds");
11234 do_vfp_nsyn_opcode ("fsubs");
11239 do_vfp_nsyn_opcode ("faddd");
11241 do_vfp_nsyn_opcode ("fsubd");
11245 /* Check operand types to see if this is a VFP instruction, and if so call
11249 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11251 enum neon_shape rs
;
11252 struct neon_type_el et
;
11257 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11258 et
= neon_check_type (2, rs
,
11259 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11263 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11264 et
= neon_check_type (3, rs
,
11265 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11272 if (et
.type
!= NT_invtype
)
11284 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11286 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11291 do_vfp_nsyn_opcode ("fmacs");
11293 do_vfp_nsyn_opcode ("fmscs");
11298 do_vfp_nsyn_opcode ("fmacd");
11300 do_vfp_nsyn_opcode ("fmscd");
11305 do_vfp_nsyn_mul (enum neon_shape rs
)
11308 do_vfp_nsyn_opcode ("fmuls");
11310 do_vfp_nsyn_opcode ("fmuld");
11314 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11316 int is_neg
= (inst
.instruction
& 0x80) != 0;
11317 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11322 do_vfp_nsyn_opcode ("fnegs");
11324 do_vfp_nsyn_opcode ("fabss");
11329 do_vfp_nsyn_opcode ("fnegd");
11331 do_vfp_nsyn_opcode ("fabsd");
11335 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11336 insns belong to Neon, and are handled elsewhere. */
11339 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11341 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11345 do_vfp_nsyn_opcode ("fldmdbs");
11347 do_vfp_nsyn_opcode ("fldmias");
11352 do_vfp_nsyn_opcode ("fstmdbs");
11354 do_vfp_nsyn_opcode ("fstmias");
11359 do_vfp_nsyn_sqrt (void)
11361 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11362 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11365 do_vfp_nsyn_opcode ("fsqrts");
11367 do_vfp_nsyn_opcode ("fsqrtd");
11371 do_vfp_nsyn_div (void)
11373 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11374 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11375 N_F32
| N_F64
| N_KEY
| N_VFP
);
11378 do_vfp_nsyn_opcode ("fdivs");
11380 do_vfp_nsyn_opcode ("fdivd");
11384 do_vfp_nsyn_nmul (void)
11386 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11387 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11388 N_F32
| N_F64
| N_KEY
| N_VFP
);
11392 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11393 do_vfp_sp_dyadic ();
11397 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11398 do_vfp_dp_rd_rn_rm ();
11400 do_vfp_cond_or_thumb ();
11404 do_vfp_nsyn_cmp (void)
11406 if (inst
.operands
[1].isreg
)
11408 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11409 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11413 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11414 do_vfp_sp_monadic ();
11418 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11419 do_vfp_dp_rd_rm ();
11424 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11425 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11427 switch (inst
.instruction
& 0x0fffffff)
11430 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11433 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11441 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11442 do_vfp_sp_compare_z ();
11446 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11450 do_vfp_cond_or_thumb ();
11454 nsyn_insert_sp (void)
11456 inst
.operands
[1] = inst
.operands
[0];
11457 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11458 inst
.operands
[0].reg
= 13;
11459 inst
.operands
[0].isreg
= 1;
11460 inst
.operands
[0].writeback
= 1;
11461 inst
.operands
[0].present
= 1;
11465 do_vfp_nsyn_push (void)
11468 if (inst
.operands
[1].issingle
)
11469 do_vfp_nsyn_opcode ("fstmdbs");
11471 do_vfp_nsyn_opcode ("fstmdbd");
11475 do_vfp_nsyn_pop (void)
11478 if (inst
.operands
[1].issingle
)
11479 do_vfp_nsyn_opcode ("fldmias");
11481 do_vfp_nsyn_opcode ("fldmiad");
11484 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11485 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11488 neon_dp_fixup (unsigned i
)
11492 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11506 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11510 neon_logbits (unsigned x
)
11512 return ffs (x
) - 4;
11515 #define LOW4(R) ((R) & 0xf)
11516 #define HI1(R) (((R) >> 4) & 1)
11518 /* Encode insns with bit pattern:
11520 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11521 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11523 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11524 different meaning for some instruction. */
11527 neon_three_same (int isquad
, int ubit
, int size
)
11529 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11530 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11531 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11532 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11533 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11534 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11535 inst
.instruction
|= (isquad
!= 0) << 6;
11536 inst
.instruction
|= (ubit
!= 0) << 24;
11538 inst
.instruction
|= neon_logbits (size
) << 20;
11540 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11543 /* Encode instructions of the form:
11545 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11546 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11548 Don't write size if SIZE == -1. */
11551 neon_two_same (int qbit
, int ubit
, int size
)
11553 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11554 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11556 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11557 inst
.instruction
|= (qbit
!= 0) << 6;
11558 inst
.instruction
|= (ubit
!= 0) << 24;
11561 inst
.instruction
|= neon_logbits (size
) << 18;
11563 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11566 /* Neon instruction encoders, in approximate order of appearance. */
11569 do_neon_dyadic_i_su (void)
11571 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11572 struct neon_type_el et
= neon_check_type (3, rs
,
11573 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11574 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11578 do_neon_dyadic_i64_su (void)
11580 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11581 struct neon_type_el et
= neon_check_type (3, rs
,
11582 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11583 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11587 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11590 unsigned size
= et
.size
>> 3;
11591 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11592 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11593 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11594 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11595 inst
.instruction
|= (isquad
!= 0) << 6;
11596 inst
.instruction
|= immbits
<< 16;
11597 inst
.instruction
|= (size
>> 3) << 7;
11598 inst
.instruction
|= (size
& 0x7) << 19;
11600 inst
.instruction
|= (uval
!= 0) << 24;
11602 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11606 do_neon_shl_imm (void)
11608 if (!inst
.operands
[2].isreg
)
11610 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11611 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11612 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11613 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11617 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11618 struct neon_type_el et
= neon_check_type (3, rs
,
11619 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11622 /* VSHL/VQSHL 3-register variants have syntax such as:
11624 whereas other 3-register operations encoded by neon_three_same have
11627 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11629 tmp
= inst
.operands
[2].reg
;
11630 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11631 inst
.operands
[1].reg
= tmp
;
11632 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11633 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11638 do_neon_qshl_imm (void)
11640 if (!inst
.operands
[2].isreg
)
11642 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11643 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11645 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11646 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11647 inst
.operands
[2].imm
);
11651 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11652 struct neon_type_el et
= neon_check_type (3, rs
,
11653 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11656 /* See note in do_neon_shl_imm. */
11657 tmp
= inst
.operands
[2].reg
;
11658 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11659 inst
.operands
[1].reg
= tmp
;
11660 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11661 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11666 do_neon_rshl (void)
11668 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11669 struct neon_type_el et
= neon_check_type (3, rs
,
11670 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11673 tmp
= inst
.operands
[2].reg
;
11674 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11675 inst
.operands
[1].reg
= tmp
;
11676 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11680 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11682 /* Handle .I8 pseudo-instructions. */
11685 /* Unfortunately, this will make everything apart from zero out-of-range.
11686 FIXME is this the intended semantics? There doesn't seem much point in
11687 accepting .I8 if so. */
11688 immediate
|= immediate
<< 8;
11694 if (immediate
== (immediate
& 0x000000ff))
11696 *immbits
= immediate
;
11699 else if (immediate
== (immediate
& 0x0000ff00))
11701 *immbits
= immediate
>> 8;
11704 else if (immediate
== (immediate
& 0x00ff0000))
11706 *immbits
= immediate
>> 16;
11709 else if (immediate
== (immediate
& 0xff000000))
11711 *immbits
= immediate
>> 24;
11714 if ((immediate
& 0xffff) != (immediate
>> 16))
11715 goto bad_immediate
;
11716 immediate
&= 0xffff;
11719 if (immediate
== (immediate
& 0x000000ff))
11721 *immbits
= immediate
;
11724 else if (immediate
== (immediate
& 0x0000ff00))
11726 *immbits
= immediate
>> 8;
11731 first_error (_("immediate value out of range"));
11735 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11739 neon_bits_same_in_bytes (unsigned imm
)
11741 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11742 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11743 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11744 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11747 /* For immediate of above form, return 0bABCD. */
11750 neon_squash_bits (unsigned imm
)
11752 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11753 | ((imm
& 0x01000000) >> 21);
11756 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11759 neon_qfloat_bits (unsigned imm
)
11761 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11764 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11765 the instruction. *OP is passed as the initial value of the op field, and
11766 may be set to a different value depending on the constant (i.e.
11767 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11768 MVN). If the immediate looks like a repeated pattern then also
11769 try smaller element sizes. */
11772 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11773 unsigned *immbits
, int *op
, int size
,
11774 enum neon_el_type type
)
11776 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11778 if (type
== NT_float
&& !float_p
)
11781 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11783 if (size
!= 32 || *op
== 1)
11785 *immbits
= neon_qfloat_bits (immlo
);
11791 if (neon_bits_same_in_bytes (immhi
)
11792 && neon_bits_same_in_bytes (immlo
))
11796 *immbits
= (neon_squash_bits (immhi
) << 4)
11797 | neon_squash_bits (immlo
);
11802 if (immhi
!= immlo
)
11808 if (immlo
== (immlo
& 0x000000ff))
11813 else if (immlo
== (immlo
& 0x0000ff00))
11815 *immbits
= immlo
>> 8;
11818 else if (immlo
== (immlo
& 0x00ff0000))
11820 *immbits
= immlo
>> 16;
11823 else if (immlo
== (immlo
& 0xff000000))
11825 *immbits
= immlo
>> 24;
11828 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11830 *immbits
= (immlo
>> 8) & 0xff;
11833 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11835 *immbits
= (immlo
>> 16) & 0xff;
11839 if ((immlo
& 0xffff) != (immlo
>> 16))
11846 if (immlo
== (immlo
& 0x000000ff))
11851 else if (immlo
== (immlo
& 0x0000ff00))
11853 *immbits
= immlo
>> 8;
11857 if ((immlo
& 0xff) != (immlo
>> 8))
11862 if (immlo
== (immlo
& 0x000000ff))
11864 /* Don't allow MVN with 8-bit immediate. */
11874 /* Write immediate bits [7:0] to the following locations:
11876 |28/24|23 19|18 16|15 4|3 0|
11877 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11879 This function is used by VMOV/VMVN/VORR/VBIC. */
11882 neon_write_immbits (unsigned immbits
)
11884 inst
.instruction
|= immbits
& 0xf;
11885 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11886 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11889 /* Invert low-order SIZE bits of XHI:XLO. */
11892 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11894 unsigned immlo
= xlo
? *xlo
: 0;
11895 unsigned immhi
= xhi
? *xhi
: 0;
11900 immlo
= (~immlo
) & 0xff;
11904 immlo
= (~immlo
) & 0xffff;
11908 immhi
= (~immhi
) & 0xffffffff;
11909 /* fall through. */
11912 immlo
= (~immlo
) & 0xffffffff;
11927 do_neon_logic (void)
11929 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11931 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11932 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11933 /* U bit and size field were set as part of the bitmask. */
11934 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11935 neon_three_same (neon_quad (rs
), 0, -1);
11939 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11940 struct neon_type_el et
= neon_check_type (2, rs
,
11941 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11942 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11946 if (et
.type
== NT_invtype
)
11949 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11951 immbits
= inst
.operands
[1].imm
;
11954 /* .i64 is a pseudo-op, so the immediate must be a repeating
11956 if (immbits
!= (inst
.operands
[1].regisimm
?
11957 inst
.operands
[1].reg
: 0))
11959 /* Set immbits to an invalid constant. */
11960 immbits
= 0xdeadbeef;
11967 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11971 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11975 /* Pseudo-instruction for VBIC. */
11976 neon_invert_size (&immbits
, 0, et
.size
);
11977 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11981 /* Pseudo-instruction for VORR. */
11982 neon_invert_size (&immbits
, 0, et
.size
);
11983 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11993 inst
.instruction
|= neon_quad (rs
) << 6;
11994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11995 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11996 inst
.instruction
|= cmode
<< 8;
11997 neon_write_immbits (immbits
);
11999 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12004 do_neon_bitfield (void)
12006 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12007 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12008 neon_three_same (neon_quad (rs
), 0, -1);
12012 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12015 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12016 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12018 if (et
.type
== NT_float
)
12020 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12021 neon_three_same (neon_quad (rs
), 0, -1);
12025 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12026 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12031 do_neon_dyadic_if_su (void)
12033 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12037 do_neon_dyadic_if_su_d (void)
12039 /* This version only allow D registers, but that constraint is enforced during
12040 operand parsing so we don't need to do anything extra here. */
12041 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12045 do_neon_dyadic_if_i_d (void)
12047 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12048 affected if we specify unsigned args. */
12049 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12052 enum vfp_or_neon_is_neon_bits
12055 NEON_CHECK_ARCH
= 2
12058 /* Call this function if an instruction which may have belonged to the VFP or
12059 Neon instruction sets, but turned out to be a Neon instruction (due to the
12060 operand types involved, etc.). We have to check and/or fix-up a couple of
12063 - Make sure the user hasn't attempted to make a Neon instruction
12065 - Alter the value in the condition code field if necessary.
12066 - Make sure that the arch supports Neon instructions.
12068 Which of these operations take place depends on bits from enum
12069 vfp_or_neon_is_neon_bits.
12071 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12072 current instruction's condition is COND_ALWAYS, the condition field is
12073 changed to inst.uncond_value. This is necessary because instructions shared
12074 between VFP and Neon may be conditional for the VFP variants only, and the
12075 unconditional Neon version must have, e.g., 0xF in the condition field. */
12078 vfp_or_neon_is_neon (unsigned check
)
12080 /* Conditions are always legal in Thumb mode (IT blocks). */
12081 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12083 if (inst
.cond
!= COND_ALWAYS
)
12085 first_error (_(BAD_COND
));
12088 if (inst
.uncond_value
!= -1)
12089 inst
.instruction
|= inst
.uncond_value
<< 28;
12092 if ((check
& NEON_CHECK_ARCH
)
12093 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12095 first_error (_(BAD_FPU
));
12103 do_neon_addsub_if_i (void)
12105 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12108 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12111 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12112 affected if we specify unsigned args. */
12113 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12116 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12118 V<op> A,B (A is operand 0, B is operand 2)
12123 so handle that case specially. */
12126 neon_exchange_operands (void)
12128 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12129 if (inst
.operands
[1].present
)
12131 /* Swap operands[1] and operands[2]. */
12132 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12133 inst
.operands
[1] = inst
.operands
[2];
12134 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12138 inst
.operands
[1] = inst
.operands
[2];
12139 inst
.operands
[2] = inst
.operands
[0];
12144 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12146 if (inst
.operands
[2].isreg
)
12149 neon_exchange_operands ();
12150 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12154 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12155 struct neon_type_el et
= neon_check_type (2, rs
,
12156 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12158 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12159 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12160 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12161 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12162 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12163 inst
.instruction
|= neon_quad (rs
) << 6;
12164 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12165 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12167 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12174 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12178 do_neon_cmp_inv (void)
12180 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12186 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12189 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12190 scalars, which are encoded in 5 bits, M : Rm.
12191 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12192 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12196 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12198 unsigned regno
= NEON_SCALAR_REG (scalar
);
12199 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12204 if (regno
> 7 || elno
> 3)
12206 return regno
| (elno
<< 3);
12209 if (regno
> 15 || elno
> 1)
12211 return regno
| (elno
<< 4);
12215 first_error (_("scalar out of range for multiply instruction"));
12221 /* Encode multiply / multiply-accumulate scalar instructions. */
12224 neon_mul_mac (struct neon_type_el et
, int ubit
)
12228 /* Give a more helpful error message if we have an invalid type. */
12229 if (et
.type
== NT_invtype
)
12232 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12233 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12234 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12236 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12237 inst
.instruction
|= LOW4 (scalar
);
12238 inst
.instruction
|= HI1 (scalar
) << 5;
12239 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12240 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12241 inst
.instruction
|= (ubit
!= 0) << 24;
12243 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12247 do_neon_mac_maybe_scalar (void)
12249 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12252 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12255 if (inst
.operands
[2].isscalar
)
12257 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12258 struct neon_type_el et
= neon_check_type (3, rs
,
12259 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12260 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12261 neon_mul_mac (et
, neon_quad (rs
));
12265 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12266 affected if we specify unsigned args. */
12267 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12274 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12275 struct neon_type_el et
= neon_check_type (3, rs
,
12276 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12277 neon_three_same (neon_quad (rs
), 0, et
.size
);
12280 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12281 same types as the MAC equivalents. The polynomial type for this instruction
12282 is encoded the same as the integer type. */
12287 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12290 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12293 if (inst
.operands
[2].isscalar
)
12294 do_neon_mac_maybe_scalar ();
12296 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12300 do_neon_qdmulh (void)
12302 if (inst
.operands
[2].isscalar
)
12304 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12305 struct neon_type_el et
= neon_check_type (3, rs
,
12306 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12307 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12308 neon_mul_mac (et
, neon_quad (rs
));
12312 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12313 struct neon_type_el et
= neon_check_type (3, rs
,
12314 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12315 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12316 /* The U bit (rounding) comes from bit mask. */
12317 neon_three_same (neon_quad (rs
), 0, et
.size
);
12322 do_neon_fcmp_absolute (void)
12324 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12325 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12326 /* Size field comes from bit mask. */
12327 neon_three_same (neon_quad (rs
), 1, -1);
12331 do_neon_fcmp_absolute_inv (void)
12333 neon_exchange_operands ();
12334 do_neon_fcmp_absolute ();
12338 do_neon_step (void)
12340 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12341 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12342 neon_three_same (neon_quad (rs
), 0, -1);
12346 do_neon_abs_neg (void)
12348 enum neon_shape rs
;
12349 struct neon_type_el et
;
12351 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12354 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12357 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12358 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12360 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12361 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12362 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12363 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12364 inst
.instruction
|= neon_quad (rs
) << 6;
12365 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12366 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12368 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12374 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12375 struct neon_type_el et
= neon_check_type (2, rs
,
12376 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12377 int imm
= inst
.operands
[2].imm
;
12378 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12379 _("immediate out of range for insert"));
12380 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12386 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12387 struct neon_type_el et
= neon_check_type (2, rs
,
12388 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12389 int imm
= inst
.operands
[2].imm
;
12390 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12391 _("immediate out of range for insert"));
12392 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12396 do_neon_qshlu_imm (void)
12398 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12399 struct neon_type_el et
= neon_check_type (2, rs
,
12400 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12401 int imm
= inst
.operands
[2].imm
;
12402 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12403 _("immediate out of range for shift"));
12404 /* Only encodes the 'U present' variant of the instruction.
12405 In this case, signed types have OP (bit 8) set to 0.
12406 Unsigned types have OP set to 1. */
12407 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12408 /* The rest of the bits are the same as other immediate shifts. */
12409 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12413 do_neon_qmovn (void)
12415 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12416 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12417 /* Saturating move where operands can be signed or unsigned, and the
12418 destination has the same signedness. */
12419 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12420 if (et
.type
== NT_unsigned
)
12421 inst
.instruction
|= 0xc0;
12423 inst
.instruction
|= 0x80;
12424 neon_two_same (0, 1, et
.size
/ 2);
12428 do_neon_qmovun (void)
12430 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12431 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12432 /* Saturating move with unsigned results. Operands must be signed. */
12433 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12434 neon_two_same (0, 1, et
.size
/ 2);
12438 do_neon_rshift_sat_narrow (void)
12440 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12441 or unsigned. If operands are unsigned, results must also be unsigned. */
12442 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12443 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12444 int imm
= inst
.operands
[2].imm
;
12445 /* This gets the bounds check, size encoding and immediate bits calculation
12449 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12450 VQMOVN.I<size> <Dd>, <Qm>. */
12453 inst
.operands
[2].present
= 0;
12454 inst
.instruction
= N_MNEM_vqmovn
;
12459 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12460 _("immediate out of range"));
12461 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12465 do_neon_rshift_sat_narrow_u (void)
12467 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12468 or unsigned. If operands are unsigned, results must also be unsigned. */
12469 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12470 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12471 int imm
= inst
.operands
[2].imm
;
12472 /* This gets the bounds check, size encoding and immediate bits calculation
12476 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12477 VQMOVUN.I<size> <Dd>, <Qm>. */
12480 inst
.operands
[2].present
= 0;
12481 inst
.instruction
= N_MNEM_vqmovun
;
12486 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12487 _("immediate out of range"));
12488 /* FIXME: The manual is kind of unclear about what value U should have in
12489 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12491 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12495 do_neon_movn (void)
12497 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12498 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12499 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12500 neon_two_same (0, 1, et
.size
/ 2);
12504 do_neon_rshift_narrow (void)
12506 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12507 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12508 int imm
= inst
.operands
[2].imm
;
12509 /* This gets the bounds check, size encoding and immediate bits calculation
12513 /* If immediate is zero then we are a pseudo-instruction for
12514 VMOVN.I<size> <Dd>, <Qm> */
12517 inst
.operands
[2].present
= 0;
12518 inst
.instruction
= N_MNEM_vmovn
;
12523 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12524 _("immediate out of range for narrowing operation"));
12525 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12529 do_neon_shll (void)
12531 /* FIXME: Type checking when lengthening. */
12532 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12533 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12534 unsigned imm
= inst
.operands
[2].imm
;
12536 if (imm
== et
.size
)
12538 /* Maximum shift variant. */
12539 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12540 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12541 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12542 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12543 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12544 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12546 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12550 /* A more-specific type check for non-max versions. */
12551 et
= neon_check_type (2, NS_QDI
,
12552 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12553 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12554 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12558 /* Check the various types for the VCVT instruction, and return which version
12559 the current instruction is. */
12562 neon_cvt_flavour (enum neon_shape rs
)
12564 #define CVT_VAR(C,X,Y) \
12565 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12566 if (et.type != NT_invtype) \
12568 inst.error = NULL; \
12571 struct neon_type_el et
;
12572 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12573 || rs
== NS_FF
) ? N_VFP
: 0;
12574 /* The instruction versions which take an immediate take one register
12575 argument, which is extended to the width of the full register. Thus the
12576 "source" and "destination" registers must have the same width. Hack that
12577 here by making the size equal to the key (wider, in this case) operand. */
12578 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12580 CVT_VAR (0, N_S32
, N_F32
);
12581 CVT_VAR (1, N_U32
, N_F32
);
12582 CVT_VAR (2, N_F32
, N_S32
);
12583 CVT_VAR (3, N_F32
, N_U32
);
12587 /* VFP instructions. */
12588 CVT_VAR (4, N_F32
, N_F64
);
12589 CVT_VAR (5, N_F64
, N_F32
);
12590 CVT_VAR (6, N_S32
, N_F64
| key
);
12591 CVT_VAR (7, N_U32
, N_F64
| key
);
12592 CVT_VAR (8, N_F64
| key
, N_S32
);
12593 CVT_VAR (9, N_F64
| key
, N_U32
);
12594 /* VFP instructions with bitshift. */
12595 CVT_VAR (10, N_F32
| key
, N_S16
);
12596 CVT_VAR (11, N_F32
| key
, N_U16
);
12597 CVT_VAR (12, N_F64
| key
, N_S16
);
12598 CVT_VAR (13, N_F64
| key
, N_U16
);
12599 CVT_VAR (14, N_S16
, N_F32
| key
);
12600 CVT_VAR (15, N_U16
, N_F32
| key
);
12601 CVT_VAR (16, N_S16
, N_F64
| key
);
12602 CVT_VAR (17, N_U16
, N_F64
| key
);
12608 /* Neon-syntax VFP conversions. */
12611 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12613 const char *opname
= 0;
12615 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12617 /* Conversions with immediate bitshift. */
12618 const char *enc
[] =
12640 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12642 opname
= enc
[flavour
];
12643 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12644 _("operands 0 and 1 must be the same register"));
12645 inst
.operands
[1] = inst
.operands
[2];
12646 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12651 /* Conversions without bitshift. */
12652 const char *enc
[] =
12666 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12667 opname
= enc
[flavour
];
12671 do_vfp_nsyn_opcode (opname
);
12675 do_vfp_nsyn_cvtz (void)
12677 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12678 int flavour
= neon_cvt_flavour (rs
);
12679 const char *enc
[] =
12691 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12692 do_vfp_nsyn_opcode (enc
[flavour
]);
12698 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12699 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12700 int flavour
= neon_cvt_flavour (rs
);
12702 /* VFP rather than Neon conversions. */
12705 do_vfp_nsyn_cvt (rs
, flavour
);
12714 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12717 /* Fixed-point conversion with #0 immediate is encoded as an
12718 integer conversion. */
12719 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12721 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12722 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12723 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12725 inst
.instruction
|= enctab
[flavour
];
12726 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12727 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12729 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12730 inst
.instruction
|= neon_quad (rs
) << 6;
12731 inst
.instruction
|= 1 << 21;
12732 inst
.instruction
|= immbits
<< 16;
12734 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12742 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12744 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12746 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12750 inst
.instruction
|= enctab
[flavour
];
12752 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12753 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12754 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12755 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12756 inst
.instruction
|= neon_quad (rs
) << 6;
12757 inst
.instruction
|= 2 << 18;
12759 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12764 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12765 do_vfp_nsyn_cvt (rs
, flavour
);
12770 neon_move_immediate (void)
12772 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12773 struct neon_type_el et
= neon_check_type (2, rs
,
12774 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12775 unsigned immlo
, immhi
= 0, immbits
;
12776 int op
, cmode
, float_p
;
12778 constraint (et
.type
== NT_invtype
,
12779 _("operand size must be specified for immediate VMOV"));
12781 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12782 op
= (inst
.instruction
& (1 << 5)) != 0;
12784 immlo
= inst
.operands
[1].imm
;
12785 if (inst
.operands
[1].regisimm
)
12786 immhi
= inst
.operands
[1].reg
;
12788 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12789 _("immediate has bits set outside the operand size"));
12791 float_p
= inst
.operands
[1].immisfloat
;
12793 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12794 et
.size
, et
.type
)) == FAIL
)
12796 /* Invert relevant bits only. */
12797 neon_invert_size (&immlo
, &immhi
, et
.size
);
12798 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12799 with one or the other; those cases are caught by
12800 neon_cmode_for_move_imm. */
12802 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12803 &op
, et
.size
, et
.type
)) == FAIL
)
12805 first_error (_("immediate out of range"));
12810 inst
.instruction
&= ~(1 << 5);
12811 inst
.instruction
|= op
<< 5;
12813 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12814 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12815 inst
.instruction
|= neon_quad (rs
) << 6;
12816 inst
.instruction
|= cmode
<< 8;
12818 neon_write_immbits (immbits
);
12824 if (inst
.operands
[1].isreg
)
12826 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12828 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12829 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12830 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12831 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12832 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12833 inst
.instruction
|= neon_quad (rs
) << 6;
12837 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12838 neon_move_immediate ();
12841 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12844 /* Encode instructions of form:
12846 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12847 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12850 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12852 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12853 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12854 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12855 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12856 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12857 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12858 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12859 inst
.instruction
|= neon_logbits (size
) << 20;
12861 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12865 do_neon_dyadic_long (void)
12867 /* FIXME: Type checking for lengthening op. */
12868 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12869 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12870 neon_mixed_length (et
, et
.size
);
12874 do_neon_abal (void)
12876 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12877 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12878 neon_mixed_length (et
, et
.size
);
12882 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12884 if (inst
.operands
[2].isscalar
)
12886 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12887 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12888 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12889 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12893 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12894 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12895 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12896 neon_mixed_length (et
, et
.size
);
12901 do_neon_mac_maybe_scalar_long (void)
12903 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12907 do_neon_dyadic_wide (void)
12909 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12910 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12911 neon_mixed_length (et
, et
.size
);
12915 do_neon_dyadic_narrow (void)
12917 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12918 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12919 /* Operand sign is unimportant, and the U bit is part of the opcode,
12920 so force the operand type to integer. */
12921 et
.type
= NT_integer
;
12922 neon_mixed_length (et
, et
.size
/ 2);
12926 do_neon_mul_sat_scalar_long (void)
12928 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12932 do_neon_vmull (void)
12934 if (inst
.operands
[2].isscalar
)
12935 do_neon_mac_maybe_scalar_long ();
12938 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12939 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12940 if (et
.type
== NT_poly
)
12941 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12943 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12944 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12945 zero. Should be OK as-is. */
12946 neon_mixed_length (et
, et
.size
);
12953 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12954 struct neon_type_el et
= neon_check_type (3, rs
,
12955 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12956 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12957 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12958 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12959 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12960 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12961 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12962 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12963 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12964 inst
.instruction
|= neon_quad (rs
) << 6;
12965 inst
.instruction
|= imm
<< 8;
12967 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12973 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12974 struct neon_type_el et
= neon_check_type (2, rs
,
12975 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12976 unsigned op
= (inst
.instruction
>> 7) & 3;
12977 /* N (width of reversed regions) is encoded as part of the bitmask. We
12978 extract it here to check the elements to be reversed are smaller.
12979 Otherwise we'd get a reserved instruction. */
12980 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12981 assert (elsize
!= 0);
12982 constraint (et
.size
>= elsize
,
12983 _("elements must be smaller than reversal region"));
12984 neon_two_same (neon_quad (rs
), 1, et
.size
);
12990 if (inst
.operands
[1].isscalar
)
12992 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12993 struct neon_type_el et
= neon_check_type (2, rs
,
12994 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12995 unsigned sizebits
= et
.size
>> 3;
12996 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12997 int logsize
= neon_logbits (et
.size
);
12998 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13000 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13003 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13004 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13005 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13006 inst
.instruction
|= LOW4 (dm
);
13007 inst
.instruction
|= HI1 (dm
) << 5;
13008 inst
.instruction
|= neon_quad (rs
) << 6;
13009 inst
.instruction
|= x
<< 17;
13010 inst
.instruction
|= sizebits
<< 16;
13012 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13016 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13017 struct neon_type_el et
= neon_check_type (2, rs
,
13018 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13019 /* Duplicate ARM register to lanes of vector. */
13020 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13023 case 8: inst
.instruction
|= 0x400000; break;
13024 case 16: inst
.instruction
|= 0x000020; break;
13025 case 32: inst
.instruction
|= 0x000000; break;
13028 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13030 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13031 inst
.instruction
|= neon_quad (rs
) << 21;
13032 /* The encoding for this instruction is identical for the ARM and Thumb
13033 variants, except for the condition field. */
13034 do_vfp_cond_or_thumb ();
13038 /* VMOV has particularly many variations. It can be one of:
13039 0. VMOV<c><q> <Qd>, <Qm>
13040 1. VMOV<c><q> <Dd>, <Dm>
13041 (Register operations, which are VORR with Rm = Rn.)
13042 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13043 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13045 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13046 (ARM register to scalar.)
13047 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13048 (Two ARM registers to vector.)
13049 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13050 (Scalar to ARM register.)
13051 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13052 (Vector to two ARM registers.)
13053 8. VMOV.F32 <Sd>, <Sm>
13054 9. VMOV.F64 <Dd>, <Dm>
13055 (VFP register moves.)
13056 10. VMOV.F32 <Sd>, #imm
13057 11. VMOV.F64 <Dd>, #imm
13058 (VFP float immediate load.)
13059 12. VMOV <Rd>, <Sm>
13060 (VFP single to ARM reg.)
13061 13. VMOV <Sd>, <Rm>
13062 (ARM reg to VFP single.)
13063 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13064 (Two ARM regs to two VFP singles.)
13065 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13066 (Two VFP singles to two ARM regs.)
13068 These cases can be disambiguated using neon_select_shape, except cases 1/9
13069 and 3/11 which depend on the operand type too.
13071 All the encoded bits are hardcoded by this function.
13073 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13074 Cases 5, 7 may be used with VFPv2 and above.
13076 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13077 can specify a type where it doesn't make sense to, and is ignored). */
13082 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13083 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13085 struct neon_type_el et
;
13086 const char *ldconst
= 0;
13090 case NS_DD
: /* case 1/9. */
13091 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13092 /* It is not an error here if no type is given. */
13094 if (et
.type
== NT_float
&& et
.size
== 64)
13096 do_vfp_nsyn_opcode ("fcpyd");
13099 /* fall through. */
13101 case NS_QQ
: /* case 0/1. */
13103 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13105 /* The architecture manual I have doesn't explicitly state which
13106 value the U bit should have for register->register moves, but
13107 the equivalent VORR instruction has U = 0, so do that. */
13108 inst
.instruction
= 0x0200110;
13109 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13110 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13111 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13112 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13113 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13114 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13115 inst
.instruction
|= neon_quad (rs
) << 6;
13117 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13121 case NS_DI
: /* case 3/11. */
13122 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13124 if (et
.type
== NT_float
&& et
.size
== 64)
13126 /* case 11 (fconstd). */
13127 ldconst
= "fconstd";
13128 goto encode_fconstd
;
13130 /* fall through. */
13132 case NS_QI
: /* case 2/3. */
13133 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13135 inst
.instruction
= 0x0800010;
13136 neon_move_immediate ();
13137 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13140 case NS_SR
: /* case 4. */
13142 unsigned bcdebits
= 0;
13143 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13144 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13145 int logsize
= neon_logbits (et
.size
);
13146 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13147 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13149 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13152 && et
.size
!= 32, _(BAD_FPU
));
13153 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13154 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13158 case 8: bcdebits
= 0x8; break;
13159 case 16: bcdebits
= 0x1; break;
13160 case 32: bcdebits
= 0x0; break;
13164 bcdebits
|= x
<< logsize
;
13166 inst
.instruction
= 0xe000b10;
13167 do_vfp_cond_or_thumb ();
13168 inst
.instruction
|= LOW4 (dn
) << 16;
13169 inst
.instruction
|= HI1 (dn
) << 7;
13170 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13171 inst
.instruction
|= (bcdebits
& 3) << 5;
13172 inst
.instruction
|= (bcdebits
>> 2) << 21;
13176 case NS_DRR
: /* case 5 (fmdrr). */
13177 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13180 inst
.instruction
= 0xc400b10;
13181 do_vfp_cond_or_thumb ();
13182 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13183 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13184 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13185 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13188 case NS_RS
: /* case 6. */
13190 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13191 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13192 unsigned logsize
= neon_logbits (et
.size
);
13193 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13194 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13195 unsigned abcdebits
= 0;
13197 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13199 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13200 && et
.size
!= 32, _(BAD_FPU
));
13201 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13202 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13206 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13207 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13208 case 32: abcdebits
= 0x00; break;
13212 abcdebits
|= x
<< logsize
;
13213 inst
.instruction
= 0xe100b10;
13214 do_vfp_cond_or_thumb ();
13215 inst
.instruction
|= LOW4 (dn
) << 16;
13216 inst
.instruction
|= HI1 (dn
) << 7;
13217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13218 inst
.instruction
|= (abcdebits
& 3) << 5;
13219 inst
.instruction
|= (abcdebits
>> 2) << 21;
13223 case NS_RRD
: /* case 7 (fmrrd). */
13224 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13227 inst
.instruction
= 0xc500b10;
13228 do_vfp_cond_or_thumb ();
13229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13230 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13231 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13232 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13235 case NS_FF
: /* case 8 (fcpys). */
13236 do_vfp_nsyn_opcode ("fcpys");
13239 case NS_FI
: /* case 10 (fconsts). */
13240 ldconst
= "fconsts";
13242 if (is_quarter_float (inst
.operands
[1].imm
))
13244 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13245 do_vfp_nsyn_opcode (ldconst
);
13248 first_error (_("immediate out of range"));
13251 case NS_RF
: /* case 12 (fmrs). */
13252 do_vfp_nsyn_opcode ("fmrs");
13255 case NS_FR
: /* case 13 (fmsr). */
13256 do_vfp_nsyn_opcode ("fmsr");
13259 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13260 (one of which is a list), but we have parsed four. Do some fiddling to
13261 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13263 case NS_RRFF
: /* case 14 (fmrrs). */
13264 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13265 _("VFP registers must be adjacent"));
13266 inst
.operands
[2].imm
= 2;
13267 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13268 do_vfp_nsyn_opcode ("fmrrs");
13271 case NS_FFRR
: /* case 15 (fmsrr). */
13272 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13273 _("VFP registers must be adjacent"));
13274 inst
.operands
[1] = inst
.operands
[2];
13275 inst
.operands
[2] = inst
.operands
[3];
13276 inst
.operands
[0].imm
= 2;
13277 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13278 do_vfp_nsyn_opcode ("fmsrr");
13287 do_neon_rshift_round_imm (void)
13289 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13290 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13291 int imm
= inst
.operands
[2].imm
;
13293 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13296 inst
.operands
[2].present
= 0;
13301 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13302 _("immediate out of range for shift"));
13303 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13308 do_neon_movl (void)
13310 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13311 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13312 unsigned sizebits
= et
.size
>> 3;
13313 inst
.instruction
|= sizebits
<< 19;
13314 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13320 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13321 struct neon_type_el et
= neon_check_type (2, rs
,
13322 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13323 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13324 neon_two_same (neon_quad (rs
), 1, et
.size
);
13328 do_neon_zip_uzp (void)
13330 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13331 struct neon_type_el et
= neon_check_type (2, rs
,
13332 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13333 if (rs
== NS_DD
&& et
.size
== 32)
13335 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13336 inst
.instruction
= N_MNEM_vtrn
;
13340 neon_two_same (neon_quad (rs
), 1, et
.size
);
13344 do_neon_sat_abs_neg (void)
13346 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13347 struct neon_type_el et
= neon_check_type (2, rs
,
13348 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13349 neon_two_same (neon_quad (rs
), 1, et
.size
);
13353 do_neon_pair_long (void)
13355 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13356 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13357 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13358 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13359 neon_two_same (neon_quad (rs
), 1, et
.size
);
13363 do_neon_recip_est (void)
13365 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13366 struct neon_type_el et
= neon_check_type (2, rs
,
13367 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13368 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13369 neon_two_same (neon_quad (rs
), 1, et
.size
);
13375 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13376 struct neon_type_el et
= neon_check_type (2, rs
,
13377 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13378 neon_two_same (neon_quad (rs
), 1, et
.size
);
13384 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13385 struct neon_type_el et
= neon_check_type (2, rs
,
13386 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13387 neon_two_same (neon_quad (rs
), 1, et
.size
);
13393 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13394 struct neon_type_el et
= neon_check_type (2, rs
,
13395 N_EQK
| N_INT
, N_8
| N_KEY
);
13396 neon_two_same (neon_quad (rs
), 1, et
.size
);
13402 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13403 neon_two_same (neon_quad (rs
), 1, -1);
13407 do_neon_tbl_tbx (void)
13409 unsigned listlenbits
;
13410 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13412 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13414 first_error (_("bad list length for table lookup"));
13418 listlenbits
= inst
.operands
[1].imm
- 1;
13419 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13420 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13421 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13423 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13424 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13425 inst
.instruction
|= listlenbits
<< 8;
13427 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13431 do_neon_ldm_stm (void)
13433 /* P, U and L bits are part of bitmask. */
13434 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13435 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13437 if (inst
.operands
[1].issingle
)
13439 do_vfp_nsyn_ldm_stm (is_dbmode
);
13443 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13444 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13446 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13447 _("register list must contain at least 1 and at most 16 "
13450 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13451 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13452 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13453 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13455 inst
.instruction
|= offsetbits
;
13457 do_vfp_cond_or_thumb ();
13461 do_neon_ldr_str (void)
13463 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13465 if (inst
.operands
[0].issingle
)
13468 do_vfp_nsyn_opcode ("flds");
13470 do_vfp_nsyn_opcode ("fsts");
13475 do_vfp_nsyn_opcode ("fldd");
13477 do_vfp_nsyn_opcode ("fstd");
13481 /* "interleave" version also handles non-interleaving register VLD1/VST1
13485 do_neon_ld_st_interleave (void)
13487 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13488 N_8
| N_16
| N_32
| N_64
);
13489 unsigned alignbits
= 0;
13491 /* The bits in this table go:
13492 0: register stride of one (0) or two (1)
13493 1,2: register list length, minus one (1, 2, 3, 4).
13494 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13495 We use -1 for invalid entries. */
13496 const int typetable
[] =
13498 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13499 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13500 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13501 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13505 if (et
.type
== NT_invtype
)
13508 if (inst
.operands
[1].immisalign
)
13509 switch (inst
.operands
[1].imm
>> 8)
13511 case 64: alignbits
= 1; break;
13513 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13514 goto bad_alignment
;
13518 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13519 goto bad_alignment
;
13524 first_error (_("bad alignment"));
13528 inst
.instruction
|= alignbits
<< 4;
13529 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13531 /* Bits [4:6] of the immediate in a list specifier encode register stride
13532 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13533 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13534 up the right value for "type" in a table based on this value and the given
13535 list style, then stick it back. */
13536 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13537 | (((inst
.instruction
>> 8) & 3) << 3);
13539 typebits
= typetable
[idx
];
13541 constraint (typebits
== -1, _("bad list type for instruction"));
13543 inst
.instruction
&= ~0xf00;
13544 inst
.instruction
|= typebits
<< 8;
13547 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13548 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13549 otherwise. The variable arguments are a list of pairs of legal (size, align)
13550 values, terminated with -1. */
13553 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13556 int result
= FAIL
, thissize
, thisalign
;
13558 if (!inst
.operands
[1].immisalign
)
13564 va_start (ap
, do_align
);
13568 thissize
= va_arg (ap
, int);
13569 if (thissize
== -1)
13571 thisalign
= va_arg (ap
, int);
13573 if (size
== thissize
&& align
== thisalign
)
13576 while (result
!= SUCCESS
);
13580 if (result
== SUCCESS
)
13583 first_error (_("unsupported alignment for instruction"));
13589 do_neon_ld_st_lane (void)
13591 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13592 int align_good
, do_align
= 0;
13593 int logsize
= neon_logbits (et
.size
);
13594 int align
= inst
.operands
[1].imm
>> 8;
13595 int n
= (inst
.instruction
>> 8) & 3;
13596 int max_el
= 64 / et
.size
;
13598 if (et
.type
== NT_invtype
)
13601 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13602 _("bad list length"));
13603 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13604 _("scalar index out of range"));
13605 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13607 _("stride of 2 unavailable when element size is 8"));
13611 case 0: /* VLD1 / VST1. */
13612 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13614 if (align_good
== FAIL
)
13618 unsigned alignbits
= 0;
13621 case 16: alignbits
= 0x1; break;
13622 case 32: alignbits
= 0x3; break;
13625 inst
.instruction
|= alignbits
<< 4;
13629 case 1: /* VLD2 / VST2. */
13630 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13632 if (align_good
== FAIL
)
13635 inst
.instruction
|= 1 << 4;
13638 case 2: /* VLD3 / VST3. */
13639 constraint (inst
.operands
[1].immisalign
,
13640 _("can't use alignment with this instruction"));
13643 case 3: /* VLD4 / VST4. */
13644 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13645 16, 64, 32, 64, 32, 128, -1);
13646 if (align_good
== FAIL
)
13650 unsigned alignbits
= 0;
13653 case 8: alignbits
= 0x1; break;
13654 case 16: alignbits
= 0x1; break;
13655 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13658 inst
.instruction
|= alignbits
<< 4;
13665 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13666 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13667 inst
.instruction
|= 1 << (4 + logsize
);
13669 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13670 inst
.instruction
|= logsize
<< 10;
13673 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13676 do_neon_ld_dup (void)
13678 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13679 int align_good
, do_align
= 0;
13681 if (et
.type
== NT_invtype
)
13684 switch ((inst
.instruction
>> 8) & 3)
13686 case 0: /* VLD1. */
13687 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13688 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13689 &do_align
, 16, 16, 32, 32, -1);
13690 if (align_good
== FAIL
)
13692 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13695 case 2: inst
.instruction
|= 1 << 5; break;
13696 default: first_error (_("bad list length")); return;
13698 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13701 case 1: /* VLD2. */
13702 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13703 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13704 if (align_good
== FAIL
)
13706 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13707 _("bad list length"));
13708 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13709 inst
.instruction
|= 1 << 5;
13710 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13713 case 2: /* VLD3. */
13714 constraint (inst
.operands
[1].immisalign
,
13715 _("can't use alignment with this instruction"));
13716 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13717 _("bad list length"));
13718 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13719 inst
.instruction
|= 1 << 5;
13720 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13723 case 3: /* VLD4. */
13725 int align
= inst
.operands
[1].imm
>> 8;
13726 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13727 16, 64, 32, 64, 32, 128, -1);
13728 if (align_good
== FAIL
)
13730 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13731 _("bad list length"));
13732 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13733 inst
.instruction
|= 1 << 5;
13734 if (et
.size
== 32 && align
== 128)
13735 inst
.instruction
|= 0x3 << 6;
13737 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13744 inst
.instruction
|= do_align
<< 4;
13747 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13748 apart from bits [11:4]. */
13751 do_neon_ldx_stx (void)
13753 switch (NEON_LANE (inst
.operands
[0].imm
))
13755 case NEON_INTERLEAVE_LANES
:
13756 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13757 do_neon_ld_st_interleave ();
13760 case NEON_ALL_LANES
:
13761 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13766 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13767 do_neon_ld_st_lane ();
13770 /* L bit comes from bit mask. */
13771 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13772 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13775 if (inst
.operands
[1].postind
)
13777 int postreg
= inst
.operands
[1].imm
& 0xf;
13778 constraint (!inst
.operands
[1].immisreg
,
13779 _("post-index must be a register"));
13780 constraint (postreg
== 0xd || postreg
== 0xf,
13781 _("bad register for post-index"));
13782 inst
.instruction
|= postreg
;
13784 else if (inst
.operands
[1].writeback
)
13786 inst
.instruction
|= 0xd;
13789 inst
.instruction
|= 0xf;
13792 inst
.instruction
|= 0xf9000000;
13794 inst
.instruction
|= 0xf4000000;
13797 /* Overall per-instruction processing. */
13799 /* We need to be able to fix up arbitrary expressions in some statements.
13800 This is so that we can handle symbols that are an arbitrary distance from
13801 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13802 which returns part of an address in a form which will be valid for
13803 a data instruction. We do this by pushing the expression into a symbol
13804 in the expr_section, and creating a fix for that. */
13807 fix_new_arm (fragS
* frag
,
13822 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13826 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13831 /* Mark whether the fix is to a THUMB instruction, or an ARM
13833 new_fix
->tc_fix_data
= thumb_mode
;
13836 /* Create a frg for an instruction requiring relaxation. */
13838 output_relax_insn (void)
13844 /* The size of the instruction is unknown, so tie the debug info to the
13845 start of the instruction. */
13846 dwarf2_emit_insn (0);
13848 switch (inst
.reloc
.exp
.X_op
)
13851 sym
= inst
.reloc
.exp
.X_add_symbol
;
13852 offset
= inst
.reloc
.exp
.X_add_number
;
13856 offset
= inst
.reloc
.exp
.X_add_number
;
13859 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13863 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13864 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13865 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13868 /* Write a 32-bit thumb instruction to buf. */
13870 put_thumb32_insn (char * buf
, unsigned long insn
)
13872 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13873 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13877 output_inst (const char * str
)
13883 as_bad ("%s -- `%s'", inst
.error
, str
);
13888 output_relax_insn ();
13891 if (inst
.size
== 0)
13894 to
= frag_more (inst
.size
);
13896 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13898 assert (inst
.size
== (2 * THUMB_SIZE
));
13899 put_thumb32_insn (to
, inst
.instruction
);
13901 else if (inst
.size
> INSN_SIZE
)
13903 assert (inst
.size
== (2 * INSN_SIZE
));
13904 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13905 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13908 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13910 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13911 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13912 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13915 dwarf2_emit_insn (inst
.size
);
13918 /* Tag values used in struct asm_opcode's tag field. */
13921 OT_unconditional
, /* Instruction cannot be conditionalized.
13922 The ARM condition field is still 0xE. */
13923 OT_unconditionalF
, /* Instruction cannot be conditionalized
13924 and carries 0xF in its ARM condition field. */
13925 OT_csuffix
, /* Instruction takes a conditional suffix. */
13926 OT_csuffixF
, /* Some forms of the instruction take a conditional
13927 suffix, others place 0xF where the condition field
13929 OT_cinfix3
, /* Instruction takes a conditional infix,
13930 beginning at character index 3. (In
13931 unified mode, it becomes a suffix.) */
13932 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13933 tsts, cmps, cmns, and teqs. */
13934 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13935 character index 3, even in unified mode. Used for
13936 legacy instructions where suffix and infix forms
13937 may be ambiguous. */
13938 OT_csuf_or_in3
, /* Instruction takes either a conditional
13939 suffix or an infix at character index 3. */
13940 OT_odd_infix_unc
, /* This is the unconditional variant of an
13941 instruction that takes a conditional infix
13942 at an unusual position. In unified mode,
13943 this variant will accept a suffix. */
13944 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13945 are the conditional variants of instructions that
13946 take conditional infixes in unusual positions.
13947 The infix appears at character index
13948 (tag - OT_odd_infix_0). These are not accepted
13949 in unified mode. */
13952 /* Subroutine of md_assemble, responsible for looking up the primary
13953 opcode from the mnemonic the user wrote. STR points to the
13954 beginning of the mnemonic.
13956 This is not simply a hash table lookup, because of conditional
13957 variants. Most instructions have conditional variants, which are
13958 expressed with a _conditional affix_ to the mnemonic. If we were
13959 to encode each conditional variant as a literal string in the opcode
13960 table, it would have approximately 20,000 entries.
13962 Most mnemonics take this affix as a suffix, and in unified syntax,
13963 'most' is upgraded to 'all'. However, in the divided syntax, some
13964 instructions take the affix as an infix, notably the s-variants of
13965 the arithmetic instructions. Of those instructions, all but six
13966 have the infix appear after the third character of the mnemonic.
13968 Accordingly, the algorithm for looking up primary opcodes given
13971 1. Look up the identifier in the opcode table.
13972 If we find a match, go to step U.
13974 2. Look up the last two characters of the identifier in the
13975 conditions table. If we find a match, look up the first N-2
13976 characters of the identifier in the opcode table. If we
13977 find a match, go to step CE.
13979 3. Look up the fourth and fifth characters of the identifier in
13980 the conditions table. If we find a match, extract those
13981 characters from the identifier, and look up the remaining
13982 characters in the opcode table. If we find a match, go
13987 U. Examine the tag field of the opcode structure, in case this is
13988 one of the six instructions with its conditional infix in an
13989 unusual place. If it is, the tag tells us where to find the
13990 infix; look it up in the conditions table and set inst.cond
13991 accordingly. Otherwise, this is an unconditional instruction.
13992 Again set inst.cond accordingly. Return the opcode structure.
13994 CE. Examine the tag field to make sure this is an instruction that
13995 should receive a conditional suffix. If it is not, fail.
13996 Otherwise, set inst.cond from the suffix we already looked up,
13997 and return the opcode structure.
13999 CM. Examine the tag field to make sure this is an instruction that
14000 should receive a conditional infix after the third character.
14001 If it is not, fail. Otherwise, undo the edits to the current
14002 line of input and proceed as for case CE. */
14004 static const struct asm_opcode
*
14005 opcode_lookup (char **str
)
14009 const struct asm_opcode
*opcode
;
14010 const struct asm_cond
*cond
;
14012 bfd_boolean neon_supported
;
14014 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14016 /* Scan up to the end of the mnemonic, which must end in white space,
14017 '.' (in unified mode, or for Neon instructions), or end of string. */
14018 for (base
= end
= *str
; *end
!= '\0'; end
++)
14019 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14025 /* Handle a possible width suffix and/or Neon type suffix. */
14030 /* The .w and .n suffixes are only valid if the unified syntax is in
14032 if (unified_syntax
&& end
[1] == 'w')
14034 else if (unified_syntax
&& end
[1] == 'n')
14039 inst
.vectype
.elems
= 0;
14041 *str
= end
+ offset
;
14043 if (end
[offset
] == '.')
14045 /* See if we have a Neon type suffix (possible in either unified or
14046 non-unified ARM syntax mode). */
14047 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14050 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14056 /* Look for unaffixed or special-case affixed mnemonic. */
14057 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14061 if (opcode
->tag
< OT_odd_infix_0
)
14063 inst
.cond
= COND_ALWAYS
;
14067 if (unified_syntax
)
14068 as_warn (_("conditional infixes are deprecated in unified syntax"));
14069 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14070 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14073 inst
.cond
= cond
->value
;
14077 /* Cannot have a conditional suffix on a mnemonic of less than two
14079 if (end
- base
< 3)
14082 /* Look for suffixed mnemonic. */
14084 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14085 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14086 if (opcode
&& cond
)
14089 switch (opcode
->tag
)
14091 case OT_cinfix3_legacy
:
14092 /* Ignore conditional suffixes matched on infix only mnemonics. */
14096 case OT_cinfix3_deprecated
:
14097 case OT_odd_infix_unc
:
14098 if (!unified_syntax
)
14100 /* else fall through */
14104 case OT_csuf_or_in3
:
14105 inst
.cond
= cond
->value
;
14108 case OT_unconditional
:
14109 case OT_unconditionalF
:
14112 inst
.cond
= cond
->value
;
14116 /* delayed diagnostic */
14117 inst
.error
= BAD_COND
;
14118 inst
.cond
= COND_ALWAYS
;
14127 /* Cannot have a usual-position infix on a mnemonic of less than
14128 six characters (five would be a suffix). */
14129 if (end
- base
< 6)
14132 /* Look for infixed mnemonic in the usual position. */
14134 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14138 memcpy (save
, affix
, 2);
14139 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14140 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14141 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14142 memcpy (affix
, save
, 2);
14145 && (opcode
->tag
== OT_cinfix3
14146 || opcode
->tag
== OT_cinfix3_deprecated
14147 || opcode
->tag
== OT_csuf_or_in3
14148 || opcode
->tag
== OT_cinfix3_legacy
))
14152 && (opcode
->tag
== OT_cinfix3
14153 || opcode
->tag
== OT_cinfix3_deprecated
))
14154 as_warn (_("conditional infixes are deprecated in unified syntax"));
14156 inst
.cond
= cond
->value
;
14164 md_assemble (char *str
)
14167 const struct asm_opcode
* opcode
;
14169 /* Align the previous label if needed. */
14170 if (last_label_seen
!= NULL
)
14172 symbol_set_frag (last_label_seen
, frag_now
);
14173 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14174 S_SET_SEGMENT (last_label_seen
, now_seg
);
14177 memset (&inst
, '\0', sizeof (inst
));
14178 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14180 opcode
= opcode_lookup (&p
);
14183 /* It wasn't an instruction, but it might be a register alias of
14184 the form alias .req reg, or a Neon .dn/.qn directive. */
14185 if (!create_register_alias (str
, p
)
14186 && !create_neon_reg_alias (str
, p
))
14187 as_bad (_("bad instruction `%s'"), str
);
14192 if (opcode
->tag
== OT_cinfix3_deprecated
)
14193 as_warn (_("s suffix on comparison instruction is deprecated"));
14195 /* The value which unconditional instructions should have in place of the
14196 condition field. */
14197 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14201 arm_feature_set variant
;
14203 variant
= cpu_variant
;
14204 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14205 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14206 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14207 /* Check that this instruction is supported for this CPU. */
14208 if (!opcode
->tvariant
14209 || (thumb_mode
== 1
14210 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14212 as_bad (_("selected processor does not support `%s'"), str
);
14215 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14216 && opcode
->tencode
!= do_t_branch
)
14218 as_bad (_("Thumb does not support conditional execution"));
14222 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14224 /* Implicit require narrow instructions on Thumb-1. This avoids
14225 relaxation accidentally introducing Thumb-2 instructions. */
14226 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
)
14230 /* Check conditional suffixes. */
14231 if (current_it_mask
)
14234 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14235 current_it_mask
<<= 1;
14236 current_it_mask
&= 0x1f;
14237 /* The BKPT instruction is unconditional even in an IT block. */
14239 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14241 as_bad (_("incorrect condition in IT block"));
14245 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14247 as_bad (_("thumb conditional instruction not in IT block"));
14251 mapping_state (MAP_THUMB
);
14252 inst
.instruction
= opcode
->tvalue
;
14254 if (!parse_operands (p
, opcode
->operands
))
14255 opcode
->tencode ();
14257 /* Clear current_it_mask at the end of an IT block. */
14258 if (current_it_mask
== 0x10)
14259 current_it_mask
= 0;
14261 if (!(inst
.error
|| inst
.relax
))
14263 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14264 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14265 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14267 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14272 /* Something has gone badly wrong if we try to relax a fixed size
14274 assert (inst
.size_req
== 0 || !inst
.relax
);
14276 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14277 *opcode
->tvariant
);
14278 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14279 set those bits when Thumb-2 32-bit instructions are seen. ie.
14280 anything other than bl/blx.
14281 This is overly pessimistic for relaxable instructions. */
14282 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14284 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14287 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14291 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14292 is_bx
= (opcode
->aencode
== do_bx
);
14294 /* Check that this instruction is supported for this CPU. */
14295 if (!(is_bx
&& fix_v4bx
)
14296 && !(opcode
->avariant
&&
14297 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14299 as_bad (_("selected processor does not support `%s'"), str
);
14304 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14308 mapping_state (MAP_ARM
);
14309 inst
.instruction
= opcode
->avalue
;
14310 if (opcode
->tag
== OT_unconditionalF
)
14311 inst
.instruction
|= 0xF << 28;
14313 inst
.instruction
|= inst
.cond
<< 28;
14314 inst
.size
= INSN_SIZE
;
14315 if (!parse_operands (p
, opcode
->operands
))
14316 opcode
->aencode ();
14317 /* Arm mode bx is marked as both v4T and v5 because it's still required
14318 on a hypothetical non-thumb v5 core. */
14320 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14323 *opcode
->avariant
);
14327 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14334 /* Various frobbings of labels and their addresses. */
14337 arm_start_line_hook (void)
14339 last_label_seen
= NULL
;
14343 arm_frob_label (symbolS
* sym
)
14345 last_label_seen
= sym
;
14347 ARM_SET_THUMB (sym
, thumb_mode
);
14349 #if defined OBJ_COFF || defined OBJ_ELF
14350 ARM_SET_INTERWORK (sym
, support_interwork
);
14353 /* Note - do not allow local symbols (.Lxxx) to be labelled
14354 as Thumb functions. This is because these labels, whilst
14355 they exist inside Thumb code, are not the entry points for
14356 possible ARM->Thumb calls. Also, these labels can be used
14357 as part of a computed goto or switch statement. eg gcc
14358 can generate code that looks like this:
14360 ldr r2, [pc, .Laaa]
14370 The first instruction loads the address of the jump table.
14371 The second instruction converts a table index into a byte offset.
14372 The third instruction gets the jump address out of the table.
14373 The fourth instruction performs the jump.
14375 If the address stored at .Laaa is that of a symbol which has the
14376 Thumb_Func bit set, then the linker will arrange for this address
14377 to have the bottom bit set, which in turn would mean that the
14378 address computation performed by the third instruction would end
14379 up with the bottom bit set. Since the ARM is capable of unaligned
14380 word loads, the instruction would then load the incorrect address
14381 out of the jump table, and chaos would ensue. */
14382 if (label_is_thumb_function_name
14383 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14384 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14386 /* When the address of a Thumb function is taken the bottom
14387 bit of that address should be set. This will allow
14388 interworking between Arm and Thumb functions to work
14391 THUMB_SET_FUNC (sym
, 1);
14393 label_is_thumb_function_name
= FALSE
;
14396 dwarf2_emit_label (sym
);
14400 arm_data_in_code (void)
14402 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14404 *input_line_pointer
= '/';
14405 input_line_pointer
+= 5;
14406 *input_line_pointer
= 0;
14414 arm_canonicalize_symbol_name (char * name
)
14418 if (thumb_mode
&& (len
= strlen (name
)) > 5
14419 && streq (name
+ len
- 5, "/data"))
14420 *(name
+ len
- 5) = 0;
14425 /* Table of all register names defined by default. The user can
14426 define additional names with .req. Note that all register names
14427 should appear in both upper and lowercase variants. Some registers
14428 also have mixed-case names. */
14430 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14431 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14432 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14433 #define REGSET(p,t) \
14434 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14435 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14436 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14437 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14438 #define REGSETH(p,t) \
14439 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14440 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14441 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14442 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14443 #define REGSET2(p,t) \
14444 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14445 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14446 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14447 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14449 static const struct reg_entry reg_names
[] =
14451 /* ARM integer registers. */
14452 REGSET(r
, RN
), REGSET(R
, RN
),
14454 /* ATPCS synonyms. */
14455 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14456 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14457 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14459 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14460 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14461 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14463 /* Well-known aliases. */
14464 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14465 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14467 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14468 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14470 /* Coprocessor numbers. */
14471 REGSET(p
, CP
), REGSET(P
, CP
),
14473 /* Coprocessor register numbers. The "cr" variants are for backward
14475 REGSET(c
, CN
), REGSET(C
, CN
),
14476 REGSET(cr
, CN
), REGSET(CR
, CN
),
14478 /* FPA registers. */
14479 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14480 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14482 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14483 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14485 /* VFP SP registers. */
14486 REGSET(s
,VFS
), REGSET(S
,VFS
),
14487 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14489 /* VFP DP Registers. */
14490 REGSET(d
,VFD
), REGSET(D
,VFD
),
14491 /* Extra Neon DP registers. */
14492 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14494 /* Neon QP registers. */
14495 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14497 /* VFP control registers. */
14498 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14499 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14500 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14501 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14502 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14503 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14505 /* Maverick DSP coprocessor registers. */
14506 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14507 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14509 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14510 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14511 REGDEF(dspsc
,0,DSPSC
),
14513 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14514 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14515 REGDEF(DSPSC
,0,DSPSC
),
14517 /* iWMMXt data registers - p0, c0-15. */
14518 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14520 /* iWMMXt control registers - p1, c0-3. */
14521 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14522 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14523 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14524 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14526 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14527 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14528 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14529 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14530 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14532 /* XScale accumulator registers. */
14533 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14539 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14540 within psr_required_here. */
14541 static const struct asm_psr psrs
[] =
14543 /* Backward compatibility notation. Note that "all" is no longer
14544 truly all possible PSR bits. */
14545 {"all", PSR_c
| PSR_f
},
14549 /* Individual flags. */
14554 /* Combinations of flags. */
14555 {"fs", PSR_f
| PSR_s
},
14556 {"fx", PSR_f
| PSR_x
},
14557 {"fc", PSR_f
| PSR_c
},
14558 {"sf", PSR_s
| PSR_f
},
14559 {"sx", PSR_s
| PSR_x
},
14560 {"sc", PSR_s
| PSR_c
},
14561 {"xf", PSR_x
| PSR_f
},
14562 {"xs", PSR_x
| PSR_s
},
14563 {"xc", PSR_x
| PSR_c
},
14564 {"cf", PSR_c
| PSR_f
},
14565 {"cs", PSR_c
| PSR_s
},
14566 {"cx", PSR_c
| PSR_x
},
14567 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14568 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14569 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14570 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14571 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14572 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14573 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14574 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14575 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14576 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14577 {"scf", PSR_s
| PSR_c
| PSR_f
},
14578 {"scx", PSR_s
| PSR_c
| PSR_x
},
14579 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14580 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14581 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14582 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14583 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14584 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14585 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14586 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14587 {"csf", PSR_c
| PSR_s
| PSR_f
},
14588 {"csx", PSR_c
| PSR_s
| PSR_x
},
14589 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14590 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14591 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14592 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14593 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14594 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14595 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14596 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14597 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14598 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14599 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14600 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14601 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14602 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14603 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14604 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14605 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14606 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14607 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14608 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14609 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14610 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14611 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14612 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14613 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14614 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14617 /* Table of V7M psr names. */
14618 static const struct asm_psr v7m_psrs
[] =
14620 {"apsr", 0 }, {"APSR", 0 },
14621 {"iapsr", 1 }, {"IAPSR", 1 },
14622 {"eapsr", 2 }, {"EAPSR", 2 },
14623 {"psr", 3 }, {"PSR", 3 },
14624 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14625 {"ipsr", 5 }, {"IPSR", 5 },
14626 {"epsr", 6 }, {"EPSR", 6 },
14627 {"iepsr", 7 }, {"IEPSR", 7 },
14628 {"msp", 8 }, {"MSP", 8 },
14629 {"psp", 9 }, {"PSP", 9 },
14630 {"primask", 16}, {"PRIMASK", 16},
14631 {"basepri", 17}, {"BASEPRI", 17},
14632 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14633 {"faultmask", 19}, {"FAULTMASK", 19},
14634 {"control", 20}, {"CONTROL", 20}
14637 /* Table of all shift-in-operand names. */
14638 static const struct asm_shift_name shift_names
[] =
14640 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14641 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14642 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14643 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14644 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14645 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14648 /* Table of all explicit relocation names. */
14650 static struct reloc_entry reloc_names
[] =
14652 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14653 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14654 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14655 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14656 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14657 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14658 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14659 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14660 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14661 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14662 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14666 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14667 static const struct asm_cond conds
[] =
14671 {"cs", 0x2}, {"hs", 0x2},
14672 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14686 static struct asm_barrier_opt barrier_opt_names
[] =
14694 /* Table of ARM-format instructions. */
14696 /* Macros for gluing together operand strings. N.B. In all cases
14697 other than OPS0, the trailing OP_stop comes from default
14698 zero-initialization of the unspecified elements of the array. */
14699 #define OPS0() { OP_stop, }
14700 #define OPS1(a) { OP_##a, }
14701 #define OPS2(a,b) { OP_##a,OP_##b, }
14702 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14703 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14704 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14705 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14707 /* These macros abstract out the exact format of the mnemonic table and
14708 save some repeated characters. */
14710 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14711 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14712 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14713 THUMB_VARIANT, do_##ae, do_##te }
14715 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14716 a T_MNEM_xyz enumerator. */
14717 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14718 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14719 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14720 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14722 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14723 infix after the third character. */
14724 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14725 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14726 THUMB_VARIANT, do_##ae, do_##te }
14727 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14728 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14729 THUMB_VARIANT, do_##ae, do_##te }
14730 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14731 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14732 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14733 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14734 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14735 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14736 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14737 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14739 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14740 appear in the condition table. */
14741 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14742 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14743 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14745 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14746 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14747 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14748 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14749 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14750 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14751 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14752 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14753 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14754 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14755 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14756 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14757 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14758 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14759 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14766 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14767 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14768 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14769 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14771 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14772 field is still 0xE. Many of the Thumb variants can be executed
14773 conditionally, so this is checked separately. */
14774 #define TUE(mnem, op, top, nops, ops, ae, te) \
14775 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14776 THUMB_VARIANT, do_##ae, do_##te }
14778 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14779 condition code field. */
14780 #define TUF(mnem, op, top, nops, ops, ae, te) \
14781 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14782 THUMB_VARIANT, do_##ae, do_##te }
14784 /* ARM-only variants of all the above. */
14785 #define CE(mnem, op, nops, ops, ae) \
14786 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14788 #define C3(mnem, op, nops, ops, ae) \
14789 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14791 /* Legacy mnemonics that always have conditional infix after the third
14793 #define CL(mnem, op, nops, ops, ae) \
14794 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14795 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14797 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14798 #define cCE(mnem, op, nops, ops, ae) \
14799 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14801 /* Legacy coprocessor instructions where conditional infix and conditional
14802 suffix are ambiguous. For consistency this includes all FPA instructions,
14803 not just the potentially ambiguous ones. */
14804 #define cCL(mnem, op, nops, ops, ae) \
14805 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14806 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14808 /* Coprocessor, takes either a suffix or a position-3 infix
14809 (for an FPA corner case). */
14810 #define C3E(mnem, op, nops, ops, ae) \
14811 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14812 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14814 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14815 { #m1 #m2 #m3, OPS##nops ops, \
14816 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14817 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14819 #define CM(m1, m2, op, nops, ops, ae) \
14820 xCM_(m1, , m2, op, nops, ops, ae), \
14821 xCM_(m1, eq, m2, op, nops, ops, ae), \
14822 xCM_(m1, ne, m2, op, nops, ops, ae), \
14823 xCM_(m1, cs, m2, op, nops, ops, ae), \
14824 xCM_(m1, hs, m2, op, nops, ops, ae), \
14825 xCM_(m1, cc, m2, op, nops, ops, ae), \
14826 xCM_(m1, ul, m2, op, nops, ops, ae), \
14827 xCM_(m1, lo, m2, op, nops, ops, ae), \
14828 xCM_(m1, mi, m2, op, nops, ops, ae), \
14829 xCM_(m1, pl, m2, op, nops, ops, ae), \
14830 xCM_(m1, vs, m2, op, nops, ops, ae), \
14831 xCM_(m1, vc, m2, op, nops, ops, ae), \
14832 xCM_(m1, hi, m2, op, nops, ops, ae), \
14833 xCM_(m1, ls, m2, op, nops, ops, ae), \
14834 xCM_(m1, ge, m2, op, nops, ops, ae), \
14835 xCM_(m1, lt, m2, op, nops, ops, ae), \
14836 xCM_(m1, gt, m2, op, nops, ops, ae), \
14837 xCM_(m1, le, m2, op, nops, ops, ae), \
14838 xCM_(m1, al, m2, op, nops, ops, ae)
14840 #define UE(mnem, op, nops, ops, ae) \
14841 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14843 #define UF(mnem, op, nops, ops, ae) \
14844 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14846 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14847 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14848 use the same encoding function for each. */
14849 #define NUF(mnem, op, nops, ops, enc) \
14850 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14851 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14853 /* Neon data processing, version which indirects through neon_enc_tab for
14854 the various overloaded versions of opcodes. */
14855 #define nUF(mnem, op, nops, ops, enc) \
14856 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14857 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14859 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14861 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14862 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14863 THUMB_VARIANT, do_##enc, do_##enc }
14865 #define NCE(mnem, op, nops, ops, enc) \
14866 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14868 #define NCEF(mnem, op, nops, ops, enc) \
14869 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14871 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14872 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14873 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14874 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14876 #define nCE(mnem, op, nops, ops, enc) \
14877 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14879 #define nCEF(mnem, op, nops, ops, enc) \
14880 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14884 /* Thumb-only, unconditional. */
14885 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14887 static const struct asm_opcode insns
[] =
14889 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14890 #define THUMB_VARIANT &arm_ext_v4t
14891 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14892 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14893 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14894 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14895 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14896 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14897 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14898 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14899 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14900 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14901 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14902 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14903 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14904 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14905 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14906 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14908 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14909 for setting PSR flag bits. They are obsolete in V6 and do not
14910 have Thumb equivalents. */
14911 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14912 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14913 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14914 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14915 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14916 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14917 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14918 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14919 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14921 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14922 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14923 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14924 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14926 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14927 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14928 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14929 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14931 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14932 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14933 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14934 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14935 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14936 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14938 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14939 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14940 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14941 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14944 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14945 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14946 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14948 /* Thumb-compatibility pseudo ops. */
14949 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14950 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14951 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14952 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14953 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14954 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14955 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14956 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14957 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14958 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14959 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14960 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14962 /* These may simplify to neg. */
14963 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14964 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14966 #undef THUMB_VARIANT
14967 #define THUMB_VARIANT &arm_ext_v6
14968 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14970 /* V1 instructions with no Thumb analogue prior to V6T2. */
14971 #undef THUMB_VARIANT
14972 #define THUMB_VARIANT &arm_ext_v6t2
14973 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14974 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14975 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14977 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14978 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14979 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14980 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14982 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14983 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14985 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14986 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14988 /* V1 instructions with no Thumb analogue at all. */
14989 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14990 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14992 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14993 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14994 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14995 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14996 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14997 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14998 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14999 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15002 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15003 #undef THUMB_VARIANT
15004 #define THUMB_VARIANT &arm_ext_v4t
15005 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15006 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15008 #undef THUMB_VARIANT
15009 #define THUMB_VARIANT &arm_ext_v6t2
15010 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15011 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15013 /* Generic coprocessor instructions. */
15014 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15015 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15016 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15017 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15018 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15019 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15020 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15023 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15024 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15025 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15028 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15029 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15030 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15033 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15034 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15035 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15036 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15037 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15038 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15039 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15040 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15041 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15044 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15045 #undef THUMB_VARIANT
15046 #define THUMB_VARIANT &arm_ext_v4t
15047 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15048 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15049 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15050 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15051 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15052 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15055 #define ARM_VARIANT &arm_ext_v4t_5
15056 /* ARM Architecture 4T. */
15057 /* Note: bx (and blx) are required on V5, even if the processor does
15058 not support Thumb. */
15059 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15062 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15063 #undef THUMB_VARIANT
15064 #define THUMB_VARIANT &arm_ext_v5t
15065 /* Note: blx has 2 variants; the .value coded here is for
15066 BLX(2). Only this variant has conditional execution. */
15067 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15068 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15070 #undef THUMB_VARIANT
15071 #define THUMB_VARIANT &arm_ext_v6t2
15072 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15073 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15074 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15075 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15076 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15077 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15078 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15079 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15082 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15083 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15084 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15085 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15086 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15088 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15089 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15091 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15092 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15093 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15094 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15096 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15097 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15098 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15099 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15101 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15102 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15104 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15105 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15106 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15107 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15110 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15111 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15112 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15113 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15115 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15116 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15119 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15120 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15123 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15124 #undef THUMB_VARIANT
15125 #define THUMB_VARIANT &arm_ext_v6
15126 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15127 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15128 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15129 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15130 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15131 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15132 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15133 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15134 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15135 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15137 #undef THUMB_VARIANT
15138 #define THUMB_VARIANT &arm_ext_v6t2
15139 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15140 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15141 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15142 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15144 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15145 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15147 /* ARM V6 not included in V7M (eg. integer SIMD). */
15148 #undef THUMB_VARIANT
15149 #define THUMB_VARIANT &arm_ext_v6_notm
15150 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15151 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15152 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15153 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15154 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15155 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15156 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15157 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15158 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15159 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15160 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15161 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15162 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15163 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15164 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15166 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15167 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15168 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15169 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15170 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15171 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15172 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15173 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15174 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15175 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15176 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15177 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15178 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15179 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15180 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15181 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15182 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15183 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15184 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15185 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15186 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15187 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15188 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15189 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15190 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15191 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15192 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15193 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15194 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15195 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15196 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15197 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15198 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15199 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15200 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15201 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15202 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15203 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15204 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15205 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15206 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15207 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15208 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15209 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15210 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15211 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15212 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15213 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15214 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15215 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15216 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15217 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15218 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15219 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15220 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15221 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15222 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15223 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15224 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15225 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15226 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15227 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15228 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15229 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15230 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15231 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15232 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15235 #define ARM_VARIANT &arm_ext_v6k
15236 #undef THUMB_VARIANT
15237 #define THUMB_VARIANT &arm_ext_v6k
15238 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15239 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15240 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15241 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15243 #undef THUMB_VARIANT
15244 #define THUMB_VARIANT &arm_ext_v6_notm
15245 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15246 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15248 #undef THUMB_VARIANT
15249 #define THUMB_VARIANT &arm_ext_v6t2
15250 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15251 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15252 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15253 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15254 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15257 #define ARM_VARIANT &arm_ext_v6z
15258 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15261 #define ARM_VARIANT &arm_ext_v6t2
15262 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15263 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15264 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15265 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15267 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15268 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15269 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15270 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15272 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15273 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15274 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15275 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15277 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15278 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15279 /* ARM does not really have an IT instruction, so always allow it. */
15281 #define ARM_VARIANT &arm_ext_v1
15282 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15283 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15284 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15285 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15286 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15287 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15288 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15289 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15290 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15291 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15292 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15293 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15294 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15295 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15296 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15298 /* Thumb2 only instructions. */
15300 #define ARM_VARIANT NULL
15302 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15303 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15304 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15305 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15307 /* Thumb-2 hardware division instructions (R and M profiles only). */
15308 #undef THUMB_VARIANT
15309 #define THUMB_VARIANT &arm_ext_div
15310 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15311 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15313 /* ARM V7 instructions. */
15315 #define ARM_VARIANT &arm_ext_v7
15316 #undef THUMB_VARIANT
15317 #define THUMB_VARIANT &arm_ext_v7
15318 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15319 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15320 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15321 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15322 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15325 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15326 cCE(wfs
, e200110
, 1, (RR
), rd
),
15327 cCE(rfs
, e300110
, 1, (RR
), rd
),
15328 cCE(wfc
, e400110
, 1, (RR
), rd
),
15329 cCE(rfc
, e500110
, 1, (RR
), rd
),
15331 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15332 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15333 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15334 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15336 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15337 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15338 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15339 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15341 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15342 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15343 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15344 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15345 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15346 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15355 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15358 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15359 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15368 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15372 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15381 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15385 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15394 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15396 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15397 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15398 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15407 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15409 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15410 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15411 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15420 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15422 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15423 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15424 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15433 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15435 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15436 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15437 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15446 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15448 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15449 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15450 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15527 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15537 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15539 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15540 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15542 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15550 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15551 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15552 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15553 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15554 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15556 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15557 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15558 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15559 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15560 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15562 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15563 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15564 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15565 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15566 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15567 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15576 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15578 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15579 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15580 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15589 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15591 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15592 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15593 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15602 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15604 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15605 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15606 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15615 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15617 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15618 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15619 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15628 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15630 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15631 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15632 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15641 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15643 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15644 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15645 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15654 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15656 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15657 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15658 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15696 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15706 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15708 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15709 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15711 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15719 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15720 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15721 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15723 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15724 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15725 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15726 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15727 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15728 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15729 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15730 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15731 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15732 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15733 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15734 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15736 /* The implementation of the FIX instruction is broken on some
15737 assemblers, in that it accepts a precision specifier as well as a
15738 rounding specifier, despite the fact that this is meaningless.
15739 To be more compatible, we accept it as well, though of course it
15740 does not set any bits. */
15741 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15742 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15743 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15744 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15745 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15746 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15747 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15748 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15749 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15750 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15751 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15752 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15753 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15755 /* Instructions that were new with the real FPA, call them V2. */
15757 #define ARM_VARIANT &fpu_fpa_ext_v2
15758 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15759 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15760 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15761 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15762 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15763 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15766 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15767 /* Moves and type conversions. */
15768 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15769 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15770 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15771 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15772 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15773 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15774 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15775 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15776 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15777 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15778 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15779 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15781 /* Memory operations. */
15782 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15783 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15784 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15785 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15786 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15787 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15788 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15789 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15790 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15791 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15792 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15793 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15794 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15795 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15796 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15797 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15798 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15799 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15801 /* Monadic operations. */
15802 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15803 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15804 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15806 /* Dyadic operations. */
15807 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15808 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15809 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15810 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15811 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15812 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15813 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15814 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15815 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15818 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15819 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15820 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15821 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15824 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15825 /* Moves and type conversions. */
15826 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15827 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15828 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15829 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15830 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15831 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15832 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15833 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15834 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15835 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15836 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15837 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15838 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15840 /* Memory operations. */
15841 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15842 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15843 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15844 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15845 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15846 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15847 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15848 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15849 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15850 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15852 /* Monadic operations. */
15853 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15854 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15855 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15857 /* Dyadic operations. */
15858 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15859 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15860 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15861 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15862 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15863 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15864 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15865 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15866 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15869 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15870 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15871 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15872 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15875 #define ARM_VARIANT &fpu_vfp_ext_v2
15876 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15877 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15878 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15879 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15881 /* Instructions which may belong to either the Neon or VFP instruction sets.
15882 Individual encoder functions perform additional architecture checks. */
15884 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15885 #undef THUMB_VARIANT
15886 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15887 /* These mnemonics are unique to VFP. */
15888 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15889 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15890 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15891 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15892 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15893 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15894 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15895 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15896 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15897 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15899 /* Mnemonics shared by Neon and VFP. */
15900 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15901 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15902 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15904 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15905 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15907 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15908 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15910 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15911 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15912 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15913 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15914 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15915 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15916 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15917 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15919 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15921 /* NOTE: All VMOV encoding is special-cased! */
15922 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15923 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15925 #undef THUMB_VARIANT
15926 #define THUMB_VARIANT &fpu_neon_ext_v1
15928 #define ARM_VARIANT &fpu_neon_ext_v1
15929 /* Data processing with three registers of the same length. */
15930 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15931 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15932 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15933 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15934 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15935 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15936 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15937 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15938 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15939 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15940 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15941 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15942 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15943 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15944 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15945 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15946 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15947 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15948 /* If not immediate, fall back to neon_dyadic_i64_su.
15949 shl_imm should accept I8 I16 I32 I64,
15950 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15951 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15952 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15953 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15954 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15955 /* Logic ops, types optional & ignored. */
15956 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15957 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15958 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15959 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15960 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15961 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15962 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15963 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15964 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15965 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15966 /* Bitfield ops, untyped. */
15967 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15968 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15969 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15970 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15971 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15972 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15973 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15974 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15975 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15976 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15977 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15978 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15979 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15980 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15981 back to neon_dyadic_if_su. */
15982 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15983 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15984 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15985 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15986 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15987 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15988 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15989 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15990 /* Comparison. Type I8 I16 I32 F32. */
15991 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15992 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15993 /* As above, D registers only. */
15994 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15995 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15996 /* Int and float variants, signedness unimportant. */
15997 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15998 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15999 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16000 /* Add/sub take types I8 I16 I32 I64 F32. */
16001 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16002 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16003 /* vtst takes sizes 8, 16, 32. */
16004 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16005 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16006 /* VMUL takes I8 I16 I32 F32 P8. */
16007 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16008 /* VQD{R}MULH takes S16 S32. */
16009 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16010 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16011 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16012 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16013 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16014 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16015 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16016 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16017 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16018 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16019 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16020 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16021 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16022 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16023 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16024 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16026 /* Two address, int/float. Types S8 S16 S32 F32. */
16027 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16028 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16030 /* Data processing with two registers and a shift amount. */
16031 /* Right shifts, and variants with rounding.
16032 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16033 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16034 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16035 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16036 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16037 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16038 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16039 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16040 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16041 /* Shift and insert. Sizes accepted 8 16 32 64. */
16042 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16043 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16044 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16045 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16046 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16047 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16048 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16049 /* Right shift immediate, saturating & narrowing, with rounding variants.
16050 Types accepted S16 S32 S64 U16 U32 U64. */
16051 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16052 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16053 /* As above, unsigned. Types accepted S16 S32 S64. */
16054 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16055 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16056 /* Right shift narrowing. Types accepted I16 I32 I64. */
16057 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16058 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16059 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16060 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16061 /* CVT with optional immediate for fixed-point variant. */
16062 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16064 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16065 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16067 /* Data processing, three registers of different lengths. */
16068 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16069 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16070 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16071 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16072 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16073 /* If not scalar, fall back to neon_dyadic_long.
16074 Vector types as above, scalar types S16 S32 U16 U32. */
16075 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16076 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16077 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16078 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16079 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16080 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16081 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16082 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16083 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16084 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16085 /* Saturating doubling multiplies. Types S16 S32. */
16086 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16087 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16088 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16089 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16090 S16 S32 U16 U32. */
16091 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16093 /* Extract. Size 8. */
16094 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16095 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16097 /* Two registers, miscellaneous. */
16098 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16099 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16100 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16101 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16102 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16103 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16104 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16105 /* Vector replicate. Sizes 8 16 32. */
16106 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16107 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16108 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16109 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16110 /* VMOVN. Types I16 I32 I64. */
16111 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16112 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16113 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16114 /* VQMOVUN. Types S16 S32 S64. */
16115 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16116 /* VZIP / VUZP. Sizes 8 16 32. */
16117 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16118 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16119 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16120 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16121 /* VQABS / VQNEG. Types S8 S16 S32. */
16122 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16123 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16124 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16125 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16126 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16127 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16128 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16129 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16130 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16131 /* Reciprocal estimates. Types U32 F32. */
16132 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16133 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16134 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16135 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16136 /* VCLS. Types S8 S16 S32. */
16137 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16138 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16139 /* VCLZ. Types I8 I16 I32. */
16140 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16141 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16142 /* VCNT. Size 8. */
16143 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16144 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16145 /* Two address, untyped. */
16146 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16147 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16148 /* VTRN. Sizes 8 16 32. */
16149 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16150 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16152 /* Table lookup. Size 8. */
16153 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16154 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16156 #undef THUMB_VARIANT
16157 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16159 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16160 /* Neon element/structure load/store. */
16161 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16162 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16163 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16164 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16165 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16166 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16167 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16168 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16170 #undef THUMB_VARIANT
16171 #define THUMB_VARIANT &fpu_vfp_ext_v3
16173 #define ARM_VARIANT &fpu_vfp_ext_v3
16174 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16175 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16176 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16177 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16178 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16179 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16180 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16181 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16182 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16183 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16184 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16185 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16186 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16187 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16188 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16189 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16190 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16191 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16193 #undef THUMB_VARIANT
16195 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16196 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16197 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16198 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16199 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16200 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16201 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16202 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16203 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16206 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16207 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16208 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16209 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16210 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16211 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16212 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16213 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16214 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16215 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16216 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16217 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16218 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16219 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16220 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16221 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16222 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16223 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16224 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16225 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16226 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16227 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16228 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16229 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16230 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16231 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16232 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16233 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16234 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16235 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16236 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16237 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16238 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16239 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16240 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16241 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16242 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16243 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16244 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16245 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16246 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16247 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16248 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16249 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16250 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16251 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16252 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16253 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16254 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16255 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16256 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16257 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16259 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16271 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16272 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16274 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16275 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16276 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16277 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16278 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16279 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16280 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16281 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16282 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16284 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16285 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16286 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16287 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16288 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16289 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16290 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16291 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16292 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16293 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16294 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16295 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16296 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16297 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16298 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16299 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16300 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16301 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16302 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16303 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16304 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16305 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16306 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16307 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16308 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16309 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16310 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16311 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16312 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16313 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16314 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16315 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16316 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16317 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16318 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16319 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16320 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16321 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16322 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16323 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16324 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16325 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16326 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16327 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16328 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16329 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16330 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16331 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16332 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16333 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16334 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16335 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16336 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16337 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16338 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16339 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16340 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16341 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16342 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16343 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16344 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16345 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16346 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16347 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16348 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16349 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16350 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16351 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16352 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16353 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16354 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16355 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16356 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16357 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16358 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16359 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16360 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16361 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16362 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16363 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16364 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16366 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16368 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16371 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16372 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16373 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16374 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16375 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16376 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16377 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16378 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16379 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16380 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16388 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16389 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16393 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16410 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16420 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16421 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16422 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16423 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16424 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16425 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16426 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16427 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16431 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16432 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16433 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16434 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16435 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16436 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16437 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16438 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16439 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16440 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16441 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16442 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16443 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16444 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16445 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16446 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16447 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16448 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16449 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16450 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16451 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16452 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16453 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16454 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16455 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16456 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16457 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16458 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16459 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16460 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16461 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16462 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16463 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16464 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16465 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16466 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16467 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16468 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16469 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16470 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16471 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16472 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16473 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16474 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16475 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16476 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16477 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16478 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16479 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16480 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16481 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16482 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16483 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16484 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16485 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16486 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16487 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16488 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16489 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16490 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16491 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16492 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16493 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16494 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16495 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16496 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16497 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16498 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16499 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16500 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16501 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16502 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16503 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16504 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16505 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16506 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16507 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16510 #undef THUMB_VARIANT
16537 /* MD interface: bits in the object file. */
16539 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16540 for use in the a.out file, and stores them in the array pointed to by buf.
16541 This knows about the endian-ness of the target machine and does
16542 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16543 2 (short) and 4 (long) Floating numbers are put out as a series of
16544 LITTLENUMS (shorts, here at least). */
16547 md_number_to_chars (char * buf
, valueT val
, int n
)
16549 if (target_big_endian
)
16550 number_to_chars_bigendian (buf
, val
, n
);
16552 number_to_chars_littleendian (buf
, val
, n
);
16556 md_chars_to_number (char * buf
, int n
)
16559 unsigned char * where
= (unsigned char *) buf
;
16561 if (target_big_endian
)
16566 result
|= (*where
++ & 255);
16574 result
|= (where
[n
] & 255);
16581 /* MD interface: Sections. */
16583 /* Estimate the size of a frag before relaxing. Assume everything fits in
16587 md_estimate_size_before_relax (fragS
* fragp
,
16588 segT segtype ATTRIBUTE_UNUSED
)
16594 /* Convert a machine dependent frag. */
16597 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16599 unsigned long insn
;
16600 unsigned long old_op
;
16608 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16610 old_op
= bfd_get_16(abfd
, buf
);
16611 if (fragp
->fr_symbol
)
16613 exp
.X_op
= O_symbol
;
16614 exp
.X_add_symbol
= fragp
->fr_symbol
;
16618 exp
.X_op
= O_constant
;
16620 exp
.X_add_number
= fragp
->fr_offset
;
16621 opcode
= fragp
->fr_subtype
;
16624 case T_MNEM_ldr_pc
:
16625 case T_MNEM_ldr_pc2
:
16626 case T_MNEM_ldr_sp
:
16627 case T_MNEM_str_sp
:
16634 if (fragp
->fr_var
== 4)
16636 insn
= THUMB_OP32 (opcode
);
16637 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16639 insn
|= (old_op
& 0x700) << 4;
16643 insn
|= (old_op
& 7) << 12;
16644 insn
|= (old_op
& 0x38) << 13;
16646 insn
|= 0x00000c00;
16647 put_thumb32_insn (buf
, insn
);
16648 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16652 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16654 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16657 if (fragp
->fr_var
== 4)
16659 insn
= THUMB_OP32 (opcode
);
16660 insn
|= (old_op
& 0xf0) << 4;
16661 put_thumb32_insn (buf
, insn
);
16662 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16666 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16667 exp
.X_add_number
-= 4;
16675 if (fragp
->fr_var
== 4)
16677 int r0off
= (opcode
== T_MNEM_mov
16678 || opcode
== T_MNEM_movs
) ? 0 : 8;
16679 insn
= THUMB_OP32 (opcode
);
16680 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16681 insn
|= (old_op
& 0x700) << r0off
;
16682 put_thumb32_insn (buf
, insn
);
16683 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16687 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16692 if (fragp
->fr_var
== 4)
16694 insn
= THUMB_OP32(opcode
);
16695 put_thumb32_insn (buf
, insn
);
16696 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16699 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16703 if (fragp
->fr_var
== 4)
16705 insn
= THUMB_OP32(opcode
);
16706 insn
|= (old_op
& 0xf00) << 14;
16707 put_thumb32_insn (buf
, insn
);
16708 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16711 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16714 case T_MNEM_add_sp
:
16715 case T_MNEM_add_pc
:
16716 case T_MNEM_inc_sp
:
16717 case T_MNEM_dec_sp
:
16718 if (fragp
->fr_var
== 4)
16720 /* ??? Choose between add and addw. */
16721 insn
= THUMB_OP32 (opcode
);
16722 insn
|= (old_op
& 0xf0) << 4;
16723 put_thumb32_insn (buf
, insn
);
16724 if (opcode
== T_MNEM_add_pc
)
16725 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16727 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16730 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16738 if (fragp
->fr_var
== 4)
16740 insn
= THUMB_OP32 (opcode
);
16741 insn
|= (old_op
& 0xf0) << 4;
16742 insn
|= (old_op
& 0xf) << 16;
16743 put_thumb32_insn (buf
, insn
);
16744 if (insn
& (1 << 20))
16745 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16747 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16750 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16756 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16758 fixp
->fx_file
= fragp
->fr_file
;
16759 fixp
->fx_line
= fragp
->fr_line
;
16760 fragp
->fr_fix
+= fragp
->fr_var
;
16763 /* Return the size of a relaxable immediate operand instruction.
16764 SHIFT and SIZE specify the form of the allowable immediate. */
16766 relax_immediate (fragS
*fragp
, int size
, int shift
)
16772 /* ??? Should be able to do better than this. */
16773 if (fragp
->fr_symbol
)
16776 low
= (1 << shift
) - 1;
16777 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16778 offset
= fragp
->fr_offset
;
16779 /* Force misaligned offsets to 32-bit variant. */
16782 if (offset
& ~mask
)
16787 /* Get the address of a symbol during relaxation. */
16789 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16795 sym
= fragp
->fr_symbol
;
16796 sym_frag
= symbol_get_frag (sym
);
16797 know (S_GET_SEGMENT (sym
) != absolute_section
16798 || sym_frag
== &zero_address_frag
);
16799 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16801 /* If frag has yet to be reached on this pass, assume it will
16802 move by STRETCH just as we did. If this is not so, it will
16803 be because some frag between grows, and that will force
16807 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16811 /* Adjust stretch for any alignment frag. Note that if have
16812 been expanding the earlier code, the symbol may be
16813 defined in what appears to be an earlier frag. FIXME:
16814 This doesn't handle the fr_subtype field, which specifies
16815 a maximum number of bytes to skip when doing an
16817 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16819 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16822 stretch
= - ((- stretch
)
16823 & ~ ((1 << (int) f
->fr_offset
) - 1));
16825 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16837 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16840 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16845 /* Assume worst case for symbols not known to be in the same section. */
16846 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16847 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16850 val
= relaxed_symbol_addr (fragp
, stretch
);
16851 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16852 addr
= (addr
+ 4) & ~3;
16853 /* Force misaligned targets to 32-bit variant. */
16857 if (val
< 0 || val
> 1020)
16862 /* Return the size of a relaxable add/sub immediate instruction. */
16864 relax_addsub (fragS
*fragp
, asection
*sec
)
16869 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16870 op
= bfd_get_16(sec
->owner
, buf
);
16871 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16872 return relax_immediate (fragp
, 8, 0);
16874 return relax_immediate (fragp
, 3, 0);
16878 /* Return the size of a relaxable branch instruction. BITS is the
16879 size of the offset field in the narrow instruction. */
16882 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16888 /* Assume worst case for symbols not known to be in the same section. */
16889 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16890 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16893 val
= relaxed_symbol_addr (fragp
, stretch
);
16894 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16897 /* Offset is a signed value *2 */
16899 if (val
>= limit
|| val
< -limit
)
16905 /* Relax a machine dependent frag. This returns the amount by which
16906 the current size of the frag should change. */
16909 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16914 oldsize
= fragp
->fr_var
;
16915 switch (fragp
->fr_subtype
)
16917 case T_MNEM_ldr_pc2
:
16918 newsize
= relax_adr (fragp
, sec
, stretch
);
16920 case T_MNEM_ldr_pc
:
16921 case T_MNEM_ldr_sp
:
16922 case T_MNEM_str_sp
:
16923 newsize
= relax_immediate (fragp
, 8, 2);
16927 newsize
= relax_immediate (fragp
, 5, 2);
16931 newsize
= relax_immediate (fragp
, 5, 1);
16935 newsize
= relax_immediate (fragp
, 5, 0);
16938 newsize
= relax_adr (fragp
, sec
, stretch
);
16944 newsize
= relax_immediate (fragp
, 8, 0);
16947 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
16950 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
16952 case T_MNEM_add_sp
:
16953 case T_MNEM_add_pc
:
16954 newsize
= relax_immediate (fragp
, 8, 2);
16956 case T_MNEM_inc_sp
:
16957 case T_MNEM_dec_sp
:
16958 newsize
= relax_immediate (fragp
, 7, 2);
16964 newsize
= relax_addsub (fragp
, sec
);
16970 fragp
->fr_var
= newsize
;
16971 /* Freeze wide instructions that are at or before the same location as
16972 in the previous pass. This avoids infinite loops.
16973 Don't freeze them unconditionally because targets may be artificially
16974 misaligned by the expansion of preceding frags. */
16975 if (stretch
<= 0 && newsize
> 2)
16977 md_convert_frag (sec
->owner
, sec
, fragp
);
16981 return newsize
- oldsize
;
16984 /* Round up a section size to the appropriate boundary. */
16987 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16990 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16991 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16993 /* For a.out, force the section size to be aligned. If we don't do
16994 this, BFD will align it for us, but it will not write out the
16995 final bytes of the section. This may be a bug in BFD, but it is
16996 easier to fix it here since that is how the other a.out targets
17000 align
= bfd_get_section_alignment (stdoutput
, segment
);
17001 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17008 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17009 of an rs_align_code fragment. */
17012 arm_handle_align (fragS
* fragP
)
17014 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17015 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17016 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17017 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17019 int bytes
, fix
, noop_size
;
17023 if (fragP
->fr_type
!= rs_align_code
)
17026 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17027 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17030 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17031 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17033 if (fragP
->tc_frag_data
)
17035 if (target_big_endian
)
17036 noop
= thumb_bigend_noop
;
17039 noop_size
= sizeof (thumb_noop
);
17043 if (target_big_endian
)
17044 noop
= arm_bigend_noop
;
17047 noop_size
= sizeof (arm_noop
);
17050 if (bytes
& (noop_size
- 1))
17052 fix
= bytes
& (noop_size
- 1);
17053 memset (p
, 0, fix
);
17058 while (bytes
>= noop_size
)
17060 memcpy (p
, noop
, noop_size
);
17062 bytes
-= noop_size
;
17066 fragP
->fr_fix
+= fix
;
17067 fragP
->fr_var
= noop_size
;
17070 /* Called from md_do_align. Used to create an alignment
17071 frag in a code section. */
17074 arm_frag_align_code (int n
, int max
)
17078 /* We assume that there will never be a requirement
17079 to support alignments greater than 32 bytes. */
17080 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17081 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17083 p
= frag_var (rs_align_code
,
17084 MAX_MEM_FOR_RS_ALIGN_CODE
,
17086 (relax_substateT
) max
,
17093 /* Perform target specific initialisation of a frag. */
17096 arm_init_frag (fragS
* fragP
)
17098 /* Record whether this frag is in an ARM or a THUMB area. */
17099 fragP
->tc_frag_data
= thumb_mode
;
17103 /* When we change sections we need to issue a new mapping symbol. */
17106 arm_elf_change_section (void)
17109 segment_info_type
*seginfo
;
17111 /* Link an unlinked unwind index table section to the .text section. */
17112 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17113 && elf_linked_to_section (now_seg
) == NULL
)
17114 elf_linked_to_section (now_seg
) = text_section
;
17116 if (!SEG_NORMAL (now_seg
))
17119 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17121 /* We can ignore sections that only contain debug info. */
17122 if ((flags
& SEC_ALLOC
) == 0)
17125 seginfo
= seg_info (now_seg
);
17126 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17127 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17131 arm_elf_section_type (const char * str
, size_t len
)
17133 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17134 return SHT_ARM_EXIDX
;
17139 /* Code to deal with unwinding tables. */
17141 static void add_unwind_adjustsp (offsetT
);
17143 /* Generate any deferred unwind frame offset. */
17146 flush_pending_unwind (void)
17150 offset
= unwind
.pending_offset
;
17151 unwind
.pending_offset
= 0;
17153 add_unwind_adjustsp (offset
);
17156 /* Add an opcode to this list for this function. Two-byte opcodes should
17157 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17161 add_unwind_opcode (valueT op
, int length
)
17163 /* Add any deferred stack adjustment. */
17164 if (unwind
.pending_offset
)
17165 flush_pending_unwind ();
17167 unwind
.sp_restored
= 0;
17169 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17171 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17172 if (unwind
.opcodes
)
17173 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17174 unwind
.opcode_alloc
);
17176 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17181 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17183 unwind
.opcode_count
++;
17187 /* Add unwind opcodes to adjust the stack pointer. */
17190 add_unwind_adjustsp (offsetT offset
)
17194 if (offset
> 0x200)
17196 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17201 /* Long form: 0xb2, uleb128. */
17202 /* This might not fit in a word so add the individual bytes,
17203 remembering the list is built in reverse order. */
17204 o
= (valueT
) ((offset
- 0x204) >> 2);
17206 add_unwind_opcode (0, 1);
17208 /* Calculate the uleb128 encoding of the offset. */
17212 bytes
[n
] = o
& 0x7f;
17218 /* Add the insn. */
17220 add_unwind_opcode (bytes
[n
- 1], 1);
17221 add_unwind_opcode (0xb2, 1);
17223 else if (offset
> 0x100)
17225 /* Two short opcodes. */
17226 add_unwind_opcode (0x3f, 1);
17227 op
= (offset
- 0x104) >> 2;
17228 add_unwind_opcode (op
, 1);
17230 else if (offset
> 0)
17232 /* Short opcode. */
17233 op
= (offset
- 4) >> 2;
17234 add_unwind_opcode (op
, 1);
17236 else if (offset
< 0)
17239 while (offset
> 0x100)
17241 add_unwind_opcode (0x7f, 1);
17244 op
= ((offset
- 4) >> 2) | 0x40;
17245 add_unwind_opcode (op
, 1);
17249 /* Finish the list of unwind opcodes for this function. */
17251 finish_unwind_opcodes (void)
17255 if (unwind
.fp_used
)
17257 /* Adjust sp as necessary. */
17258 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17259 flush_pending_unwind ();
17261 /* After restoring sp from the frame pointer. */
17262 op
= 0x90 | unwind
.fp_reg
;
17263 add_unwind_opcode (op
, 1);
17266 flush_pending_unwind ();
17270 /* Start an exception table entry. If idx is nonzero this is an index table
17274 start_unwind_section (const segT text_seg
, int idx
)
17276 const char * text_name
;
17277 const char * prefix
;
17278 const char * prefix_once
;
17279 const char * group_name
;
17283 size_t sec_name_len
;
17290 prefix
= ELF_STRING_ARM_unwind
;
17291 prefix_once
= ELF_STRING_ARM_unwind_once
;
17292 type
= SHT_ARM_EXIDX
;
17296 prefix
= ELF_STRING_ARM_unwind_info
;
17297 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17298 type
= SHT_PROGBITS
;
17301 text_name
= segment_name (text_seg
);
17302 if (streq (text_name
, ".text"))
17305 if (strncmp (text_name
, ".gnu.linkonce.t.",
17306 strlen (".gnu.linkonce.t.")) == 0)
17308 prefix
= prefix_once
;
17309 text_name
+= strlen (".gnu.linkonce.t.");
17312 prefix_len
= strlen (prefix
);
17313 text_len
= strlen (text_name
);
17314 sec_name_len
= prefix_len
+ text_len
;
17315 sec_name
= xmalloc (sec_name_len
+ 1);
17316 memcpy (sec_name
, prefix
, prefix_len
);
17317 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17318 sec_name
[prefix_len
+ text_len
] = '\0';
17324 /* Handle COMDAT group. */
17325 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17327 group_name
= elf_group_name (text_seg
);
17328 if (group_name
== NULL
)
17330 as_bad (_("Group section `%s' has no group signature"),
17331 segment_name (text_seg
));
17332 ignore_rest_of_line ();
17335 flags
|= SHF_GROUP
;
17339 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17341 /* Set the section link for index tables. */
17343 elf_linked_to_section (now_seg
) = text_seg
;
17347 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17348 personality routine data. Returns zero, or the index table value for
17349 and inline entry. */
17352 create_unwind_entry (int have_data
)
17357 /* The current word of data. */
17359 /* The number of bytes left in this word. */
17362 finish_unwind_opcodes ();
17364 /* Remember the current text section. */
17365 unwind
.saved_seg
= now_seg
;
17366 unwind
.saved_subseg
= now_subseg
;
17368 start_unwind_section (now_seg
, 0);
17370 if (unwind
.personality_routine
== NULL
)
17372 if (unwind
.personality_index
== -2)
17375 as_bad (_("handlerdata in cantunwind frame"));
17376 return 1; /* EXIDX_CANTUNWIND. */
17379 /* Use a default personality routine if none is specified. */
17380 if (unwind
.personality_index
== -1)
17382 if (unwind
.opcode_count
> 3)
17383 unwind
.personality_index
= 1;
17385 unwind
.personality_index
= 0;
17388 /* Space for the personality routine entry. */
17389 if (unwind
.personality_index
== 0)
17391 if (unwind
.opcode_count
> 3)
17392 as_bad (_("too many unwind opcodes for personality routine 0"));
17396 /* All the data is inline in the index table. */
17399 while (unwind
.opcode_count
> 0)
17401 unwind
.opcode_count
--;
17402 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17406 /* Pad with "finish" opcodes. */
17408 data
= (data
<< 8) | 0xb0;
17415 /* We get two opcodes "free" in the first word. */
17416 size
= unwind
.opcode_count
- 2;
17419 /* An extra byte is required for the opcode count. */
17420 size
= unwind
.opcode_count
+ 1;
17422 size
= (size
+ 3) >> 2;
17424 as_bad (_("too many unwind opcodes"));
17426 frag_align (2, 0, 0);
17427 record_alignment (now_seg
, 2);
17428 unwind
.table_entry
= expr_build_dot ();
17430 /* Allocate the table entry. */
17431 ptr
= frag_more ((size
<< 2) + 4);
17432 where
= frag_now_fix () - ((size
<< 2) + 4);
17434 switch (unwind
.personality_index
)
17437 /* ??? Should this be a PLT generating relocation? */
17438 /* Custom personality routine. */
17439 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17440 BFD_RELOC_ARM_PREL31
);
17445 /* Set the first byte to the number of additional words. */
17450 /* ABI defined personality routines. */
17452 /* Three opcodes bytes are packed into the first word. */
17459 /* The size and first two opcode bytes go in the first word. */
17460 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17465 /* Should never happen. */
17469 /* Pack the opcodes into words (MSB first), reversing the list at the same
17471 while (unwind
.opcode_count
> 0)
17475 md_number_to_chars (ptr
, data
, 4);
17480 unwind
.opcode_count
--;
17482 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17485 /* Finish off the last word. */
17488 /* Pad with "finish" opcodes. */
17490 data
= (data
<< 8) | 0xb0;
17492 md_number_to_chars (ptr
, data
, 4);
17497 /* Add an empty descriptor if there is no user-specified data. */
17498 ptr
= frag_more (4);
17499 md_number_to_chars (ptr
, 0, 4);
17506 /* Initialize the DWARF-2 unwind information for this procedure. */
17509 tc_arm_frame_initial_instructions (void)
17511 cfi_add_CFA_def_cfa (REG_SP
, 0);
17513 #endif /* OBJ_ELF */
17515 /* Convert REGNAME to a DWARF-2 register number. */
17518 tc_arm_regname_to_dw2regnum (char *regname
)
17520 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17530 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17534 expr
.X_op
= O_secrel
;
17535 expr
.X_add_symbol
= symbol
;
17536 expr
.X_add_number
= 0;
17537 emit_expr (&expr
, size
);
17541 /* MD interface: Symbol and relocation handling. */
17543 /* Return the address within the segment that a PC-relative fixup is
17544 relative to. For ARM, PC-relative fixups applied to instructions
17545 are generally relative to the location of the fixup plus 8 bytes.
17546 Thumb branches are offset by 4, and Thumb loads relative to PC
17547 require special handling. */
17550 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17552 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17554 /* If this is pc-relative and we are going to emit a relocation
17555 then we just want to put out any pipeline compensation that the linker
17556 will need. Otherwise we want to use the calculated base.
17557 For WinCE we skip the bias for externals as well, since this
17558 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17560 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17561 || (arm_force_relocation (fixP
)
17563 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17568 switch (fixP
->fx_r_type
)
17570 /* PC relative addressing on the Thumb is slightly odd as the
17571 bottom two bits of the PC are forced to zero for the
17572 calculation. This happens *after* application of the
17573 pipeline offset. However, Thumb adrl already adjusts for
17574 this, so we need not do it again. */
17575 case BFD_RELOC_ARM_THUMB_ADD
:
17578 case BFD_RELOC_ARM_THUMB_OFFSET
:
17579 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17580 case BFD_RELOC_ARM_T32_ADD_PC12
:
17581 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17582 return (base
+ 4) & ~3;
17584 /* Thumb branches are simply offset by +4. */
17585 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17586 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17587 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17588 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17589 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17590 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17591 case BFD_RELOC_THUMB_PCREL_BLX
:
17594 /* ARM mode branches are offset by +8. However, the Windows CE
17595 loader expects the relocation not to take this into account. */
17596 case BFD_RELOC_ARM_PCREL_BRANCH
:
17597 case BFD_RELOC_ARM_PCREL_CALL
:
17598 case BFD_RELOC_ARM_PCREL_JUMP
:
17599 case BFD_RELOC_ARM_PCREL_BLX
:
17600 case BFD_RELOC_ARM_PLT32
:
17602 /* When handling fixups immediately, because we have already
17603 discovered the value of a symbol, or the address of the frag involved
17604 we must account for the offset by +8, as the OS loader will never see the reloc.
17605 see fixup_segment() in write.c
17606 The S_IS_EXTERNAL test handles the case of global symbols.
17607 Those need the calculated base, not just the pipe compensation the linker will need. */
17609 && fixP
->fx_addsy
!= NULL
17610 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17611 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17618 /* ARM mode loads relative to PC are also offset by +8. Unlike
17619 branches, the Windows CE loader *does* expect the relocation
17620 to take this into account. */
17621 case BFD_RELOC_ARM_OFFSET_IMM
:
17622 case BFD_RELOC_ARM_OFFSET_IMM8
:
17623 case BFD_RELOC_ARM_HWLITERAL
:
17624 case BFD_RELOC_ARM_LITERAL
:
17625 case BFD_RELOC_ARM_CP_OFF_IMM
:
17629 /* Other PC-relative relocations are un-offset. */
17635 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17636 Otherwise we have no need to default values of symbols. */
17639 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17642 if (name
[0] == '_' && name
[1] == 'G'
17643 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17647 if (symbol_find (name
))
17648 as_bad (_("GOT already in the symbol table"));
17650 GOT_symbol
= symbol_new (name
, undefined_section
,
17651 (valueT
) 0, & zero_address_frag
);
17661 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17662 computed as two separate immediate values, added together. We
17663 already know that this value cannot be computed by just one ARM
17666 static unsigned int
17667 validate_immediate_twopart (unsigned int val
,
17668 unsigned int * highpart
)
17673 for (i
= 0; i
< 32; i
+= 2)
17674 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17680 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17682 else if (a
& 0xff0000)
17684 if (a
& 0xff000000)
17686 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17690 assert (a
& 0xff000000);
17691 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17694 return (a
& 0xff) | (i
<< 7);
17701 validate_offset_imm (unsigned int val
, int hwse
)
17703 if ((hwse
&& val
> 255) || val
> 4095)
17708 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17709 negative immediate constant by altering the instruction. A bit of
17714 by inverting the second operand, and
17717 by negating the second operand. */
17720 negate_data_op (unsigned long * instruction
,
17721 unsigned long value
)
17724 unsigned long negated
, inverted
;
17726 negated
= encode_arm_immediate (-value
);
17727 inverted
= encode_arm_immediate (~value
);
17729 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17732 /* First negates. */
17733 case OPCODE_SUB
: /* ADD <-> SUB */
17734 new_inst
= OPCODE_ADD
;
17739 new_inst
= OPCODE_SUB
;
17743 case OPCODE_CMP
: /* CMP <-> CMN */
17744 new_inst
= OPCODE_CMN
;
17749 new_inst
= OPCODE_CMP
;
17753 /* Now Inverted ops. */
17754 case OPCODE_MOV
: /* MOV <-> MVN */
17755 new_inst
= OPCODE_MVN
;
17760 new_inst
= OPCODE_MOV
;
17764 case OPCODE_AND
: /* AND <-> BIC */
17765 new_inst
= OPCODE_BIC
;
17770 new_inst
= OPCODE_AND
;
17774 case OPCODE_ADC
: /* ADC <-> SBC */
17775 new_inst
= OPCODE_SBC
;
17780 new_inst
= OPCODE_ADC
;
17784 /* We cannot do anything. */
17789 if (value
== (unsigned) FAIL
)
17792 *instruction
&= OPCODE_MASK
;
17793 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17797 /* Like negate_data_op, but for Thumb-2. */
17799 static unsigned int
17800 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17804 unsigned int negated
, inverted
;
17806 negated
= encode_thumb32_immediate (-value
);
17807 inverted
= encode_thumb32_immediate (~value
);
17809 rd
= (*instruction
>> 8) & 0xf;
17810 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17813 /* ADD <-> SUB. Includes CMP <-> CMN. */
17814 case T2_OPCODE_SUB
:
17815 new_inst
= T2_OPCODE_ADD
;
17819 case T2_OPCODE_ADD
:
17820 new_inst
= T2_OPCODE_SUB
;
17824 /* ORR <-> ORN. Includes MOV <-> MVN. */
17825 case T2_OPCODE_ORR
:
17826 new_inst
= T2_OPCODE_ORN
;
17830 case T2_OPCODE_ORN
:
17831 new_inst
= T2_OPCODE_ORR
;
17835 /* AND <-> BIC. TST has no inverted equivalent. */
17836 case T2_OPCODE_AND
:
17837 new_inst
= T2_OPCODE_BIC
;
17844 case T2_OPCODE_BIC
:
17845 new_inst
= T2_OPCODE_AND
;
17850 case T2_OPCODE_ADC
:
17851 new_inst
= T2_OPCODE_SBC
;
17855 case T2_OPCODE_SBC
:
17856 new_inst
= T2_OPCODE_ADC
;
17860 /* We cannot do anything. */
17865 if (value
== (unsigned int)FAIL
)
17868 *instruction
&= T2_OPCODE_MASK
;
17869 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17873 /* Read a 32-bit thumb instruction from buf. */
17874 static unsigned long
17875 get_thumb32_insn (char * buf
)
17877 unsigned long insn
;
17878 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17879 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17885 /* We usually want to set the low bit on the address of thumb function
17886 symbols. In particular .word foo - . should have the low bit set.
17887 Generic code tries to fold the difference of two symbols to
17888 a constant. Prevent this and force a relocation when the first symbols
17889 is a thumb function. */
17891 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17893 if (op
== O_subtract
17894 && l
->X_op
== O_symbol
17895 && r
->X_op
== O_symbol
17896 && THUMB_IS_FUNC (l
->X_add_symbol
))
17898 l
->X_op
= O_subtract
;
17899 l
->X_op_symbol
= r
->X_add_symbol
;
17900 l
->X_add_number
-= r
->X_add_number
;
17903 /* Process as normal. */
17908 md_apply_fix (fixS
* fixP
,
17912 offsetT value
= * valP
;
17914 unsigned int newimm
;
17915 unsigned long temp
;
17917 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17919 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17921 /* Note whether this will delete the relocation. */
17923 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17926 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17927 consistency with the behaviour on 32-bit hosts. Remember value
17929 value
&= 0xffffffff;
17930 value
^= 0x80000000;
17931 value
-= 0x80000000;
17934 fixP
->fx_addnumber
= value
;
17936 /* Same treatment for fixP->fx_offset. */
17937 fixP
->fx_offset
&= 0xffffffff;
17938 fixP
->fx_offset
^= 0x80000000;
17939 fixP
->fx_offset
-= 0x80000000;
17941 switch (fixP
->fx_r_type
)
17943 case BFD_RELOC_NONE
:
17944 /* This will need to go in the object file. */
17948 case BFD_RELOC_ARM_IMMEDIATE
:
17949 /* We claim that this fixup has been processed here,
17950 even if in fact we generate an error because we do
17951 not have a reloc for it, so tc_gen_reloc will reject it. */
17955 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17958 _("undefined symbol %s used as an immediate value"),
17959 S_GET_NAME (fixP
->fx_addsy
));
17963 newimm
= encode_arm_immediate (value
);
17964 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17966 /* If the instruction will fail, see if we can fix things up by
17967 changing the opcode. */
17968 if (newimm
== (unsigned int) FAIL
17969 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17972 _("invalid constant (%lx) after fixup"),
17973 (unsigned long) value
);
17977 newimm
|= (temp
& 0xfffff000);
17978 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17981 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17983 unsigned int highpart
= 0;
17984 unsigned int newinsn
= 0xe1a00000; /* nop. */
17986 newimm
= encode_arm_immediate (value
);
17987 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17989 /* If the instruction will fail, see if we can fix things up by
17990 changing the opcode. */
17991 if (newimm
== (unsigned int) FAIL
17992 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17994 /* No ? OK - try using two ADD instructions to generate
17996 newimm
= validate_immediate_twopart (value
, & highpart
);
17998 /* Yes - then make sure that the second instruction is
18000 if (newimm
!= (unsigned int) FAIL
)
18002 /* Still No ? Try using a negated value. */
18003 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18004 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18005 /* Otherwise - give up. */
18008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18009 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18014 /* Replace the first operand in the 2nd instruction (which
18015 is the PC) with the destination register. We have
18016 already added in the PC in the first instruction and we
18017 do not want to do it again. */
18018 newinsn
&= ~ 0xf0000;
18019 newinsn
|= ((newinsn
& 0x0f000) << 4);
18022 newimm
|= (temp
& 0xfffff000);
18023 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18025 highpart
|= (newinsn
& 0xfffff000);
18026 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18030 case BFD_RELOC_ARM_OFFSET_IMM
:
18031 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18034 case BFD_RELOC_ARM_LITERAL
:
18040 if (validate_offset_imm (value
, 0) == FAIL
)
18042 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18044 _("invalid literal constant: pool needs to be closer"));
18046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18047 _("bad immediate value for offset (%ld)"),
18052 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18053 newval
&= 0xff7ff000;
18054 newval
|= value
| (sign
? INDEX_UP
: 0);
18055 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18058 case BFD_RELOC_ARM_OFFSET_IMM8
:
18059 case BFD_RELOC_ARM_HWLITERAL
:
18065 if (validate_offset_imm (value
, 1) == FAIL
)
18067 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18069 _("invalid literal constant: pool needs to be closer"));
18071 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18076 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18077 newval
&= 0xff7ff0f0;
18078 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18079 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18082 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18083 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18085 _("bad immediate value for offset (%ld)"), (long) value
);
18088 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18090 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18093 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18094 /* This is a complicated relocation used for all varieties of Thumb32
18095 load/store instruction with immediate offset:
18097 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18098 *4, optional writeback(W)
18099 (doubleword load/store)
18101 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18102 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18103 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18104 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18105 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18107 Uppercase letters indicate bits that are already encoded at
18108 this point. Lowercase letters are our problem. For the
18109 second block of instructions, the secondary opcode nybble
18110 (bits 8..11) is present, and bit 23 is zero, even if this is
18111 a PC-relative operation. */
18112 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18114 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18116 if ((newval
& 0xf0000000) == 0xe0000000)
18118 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18120 newval
|= (1 << 23);
18123 if (value
% 4 != 0)
18125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18126 _("offset not a multiple of 4"));
18132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18133 _("offset out of range"));
18138 else if ((newval
& 0x000f0000) == 0x000f0000)
18140 /* PC-relative, 12-bit offset. */
18142 newval
|= (1 << 23);
18147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18148 _("offset out of range"));
18153 else if ((newval
& 0x00000100) == 0x00000100)
18155 /* Writeback: 8-bit, +/- offset. */
18157 newval
|= (1 << 9);
18162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18163 _("offset out of range"));
18168 else if ((newval
& 0x00000f00) == 0x00000e00)
18170 /* T-instruction: positive 8-bit offset. */
18171 if (value
< 0 || value
> 0xff)
18173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18174 _("offset out of range"));
18182 /* Positive 12-bit or negative 8-bit offset. */
18186 newval
|= (1 << 23);
18196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18197 _("offset out of range"));
18204 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18205 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18208 case BFD_RELOC_ARM_SHIFT_IMM
:
18209 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18210 if (((unsigned long) value
) > 32
18212 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18215 _("shift expression is too large"));
18220 /* Shifts of zero must be done as lsl. */
18222 else if (value
== 32)
18224 newval
&= 0xfffff07f;
18225 newval
|= (value
& 0x1f) << 7;
18226 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18229 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18230 case BFD_RELOC_ARM_T32_ADD_IMM
:
18231 case BFD_RELOC_ARM_T32_IMM12
:
18232 case BFD_RELOC_ARM_T32_ADD_PC12
:
18233 /* We claim that this fixup has been processed here,
18234 even if in fact we generate an error because we do
18235 not have a reloc for it, so tc_gen_reloc will reject it. */
18239 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18242 _("undefined symbol %s used as an immediate value"),
18243 S_GET_NAME (fixP
->fx_addsy
));
18247 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18249 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18252 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18253 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18255 newimm
= encode_thumb32_immediate (value
);
18256 if (newimm
== (unsigned int) FAIL
)
18257 newimm
= thumb32_negate_data_op (&newval
, value
);
18259 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18260 && newimm
== (unsigned int) FAIL
)
18262 /* Turn add/sum into addw/subw. */
18263 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18264 newval
= (newval
& 0xfeffffff) | 0x02000000;
18266 /* 12 bit immediate for addw/subw. */
18270 newval
^= 0x00a00000;
18273 newimm
= (unsigned int) FAIL
;
18278 if (newimm
== (unsigned int)FAIL
)
18280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18281 _("invalid constant (%lx) after fixup"),
18282 (unsigned long) value
);
18286 newval
|= (newimm
& 0x800) << 15;
18287 newval
|= (newimm
& 0x700) << 4;
18288 newval
|= (newimm
& 0x0ff);
18290 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18291 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18294 case BFD_RELOC_ARM_SMC
:
18295 if (((unsigned long) value
) > 0xffff)
18296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18297 _("invalid smc expression"));
18298 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18299 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18300 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18303 case BFD_RELOC_ARM_SWI
:
18304 if (fixP
->tc_fix_data
!= 0)
18306 if (((unsigned long) value
) > 0xff)
18307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18308 _("invalid swi expression"));
18309 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18311 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18315 if (((unsigned long) value
) > 0x00ffffff)
18316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18317 _("invalid swi expression"));
18318 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18320 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18324 case BFD_RELOC_ARM_MULTI
:
18325 if (((unsigned long) value
) > 0xffff)
18326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18327 _("invalid expression in load/store multiple"));
18328 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18329 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18333 case BFD_RELOC_ARM_PCREL_CALL
:
18334 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18335 if ((newval
& 0xf0000000) == 0xf0000000)
18339 goto arm_branch_common
;
18341 case BFD_RELOC_ARM_PCREL_JUMP
:
18342 case BFD_RELOC_ARM_PLT32
:
18344 case BFD_RELOC_ARM_PCREL_BRANCH
:
18346 goto arm_branch_common
;
18348 case BFD_RELOC_ARM_PCREL_BLX
:
18351 /* We are going to store value (shifted right by two) in the
18352 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18353 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18354 also be be clear. */
18356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18357 _("misaligned branch destination"));
18358 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18359 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18361 _("branch out of range"));
18363 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18365 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18366 newval
|= (value
>> 2) & 0x00ffffff;
18367 /* Set the H bit on BLX instructions. */
18371 newval
|= 0x01000000;
18373 newval
&= ~0x01000000;
18375 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18379 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18380 /* CBZ can only branch forward. */
18382 /* Attempts to use CBZ to branch to the next instruction
18383 (which, strictly speaking, are prohibited) will be turned into
18386 FIXME: It may be better to remove the instruction completely and
18387 perform relaxation. */
18390 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18391 newval
= 0xbf00; /* NOP encoding T1 */
18392 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18398 _("branch out of range"));
18400 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18402 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18403 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18404 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18409 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18410 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18412 _("branch out of range"));
18414 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18416 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18417 newval
|= (value
& 0x1ff) >> 1;
18418 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18422 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18423 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18425 _("branch out of range"));
18427 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18429 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18430 newval
|= (value
& 0xfff) >> 1;
18431 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18435 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18436 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18438 _("conditional branch out of range"));
18440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18443 addressT S
, J1
, J2
, lo
, hi
;
18445 S
= (value
& 0x00100000) >> 20;
18446 J2
= (value
& 0x00080000) >> 19;
18447 J1
= (value
& 0x00040000) >> 18;
18448 hi
= (value
& 0x0003f000) >> 12;
18449 lo
= (value
& 0x00000ffe) >> 1;
18451 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18452 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18453 newval
|= (S
<< 10) | hi
;
18454 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18455 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18456 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18460 case BFD_RELOC_THUMB_PCREL_BLX
:
18461 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18462 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18464 _("branch out of range"));
18466 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18467 /* For a BLX instruction, make sure that the relocation is rounded up
18468 to a word boundary. This follows the semantics of the instruction
18469 which specifies that bit 1 of the target address will come from bit
18470 1 of the base address. */
18471 value
= (value
+ 1) & ~ 1;
18473 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18477 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18478 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18479 newval
|= (value
& 0x7fffff) >> 12;
18480 newval2
|= (value
& 0xfff) >> 1;
18481 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18482 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18486 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18487 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18489 _("branch out of range"));
18491 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18494 addressT S
, I1
, I2
, lo
, hi
;
18496 S
= (value
& 0x01000000) >> 24;
18497 I1
= (value
& 0x00800000) >> 23;
18498 I2
= (value
& 0x00400000) >> 22;
18499 hi
= (value
& 0x003ff000) >> 12;
18500 lo
= (value
& 0x00000ffe) >> 1;
18505 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18506 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18507 newval
|= (S
<< 10) | hi
;
18508 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18509 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18510 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18515 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18516 md_number_to_chars (buf
, value
, 1);
18520 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18521 md_number_to_chars (buf
, value
, 2);
18525 case BFD_RELOC_ARM_TLS_GD32
:
18526 case BFD_RELOC_ARM_TLS_LE32
:
18527 case BFD_RELOC_ARM_TLS_IE32
:
18528 case BFD_RELOC_ARM_TLS_LDM32
:
18529 case BFD_RELOC_ARM_TLS_LDO32
:
18530 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18533 case BFD_RELOC_ARM_GOT32
:
18534 case BFD_RELOC_ARM_GOTOFF
:
18535 case BFD_RELOC_ARM_TARGET2
:
18536 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18537 md_number_to_chars (buf
, 0, 4);
18541 case BFD_RELOC_RVA
:
18543 case BFD_RELOC_ARM_TARGET1
:
18544 case BFD_RELOC_ARM_ROSEGREL32
:
18545 case BFD_RELOC_ARM_SBREL32
:
18546 case BFD_RELOC_32_PCREL
:
18548 case BFD_RELOC_32_SECREL
:
18550 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18552 /* For WinCE we only do this for pcrel fixups. */
18553 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18555 md_number_to_chars (buf
, value
, 4);
18559 case BFD_RELOC_ARM_PREL31
:
18560 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18562 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18563 if ((value
^ (value
>> 1)) & 0x40000000)
18565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18566 _("rel31 relocation overflow"));
18568 newval
|= value
& 0x7fffffff;
18569 md_number_to_chars (buf
, newval
, 4);
18574 case BFD_RELOC_ARM_CP_OFF_IMM
:
18575 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18576 if (value
< -1023 || value
> 1023 || (value
& 3))
18577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18578 _("co-processor offset out of range"));
18583 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18584 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18585 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18587 newval
= get_thumb32_insn (buf
);
18588 newval
&= 0xff7fff00;
18589 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18590 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18591 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18592 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18594 put_thumb32_insn (buf
, newval
);
18597 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18598 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18599 if (value
< -255 || value
> 255)
18600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18601 _("co-processor offset out of range"));
18603 goto cp_off_common
;
18605 case BFD_RELOC_ARM_THUMB_OFFSET
:
18606 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18607 /* Exactly what ranges, and where the offset is inserted depends
18608 on the type of instruction, we can establish this from the
18610 switch (newval
>> 12)
18612 case 4: /* PC load. */
18613 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18614 forced to zero for these loads; md_pcrel_from has already
18615 compensated for this. */
18617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18618 _("invalid offset, target not word aligned (0x%08lX)"),
18619 (((unsigned long) fixP
->fx_frag
->fr_address
18620 + (unsigned long) fixP
->fx_where
) & ~3)
18621 + (unsigned long) value
);
18623 if (value
& ~0x3fc)
18624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18625 _("invalid offset, value too big (0x%08lX)"),
18628 newval
|= value
>> 2;
18631 case 9: /* SP load/store. */
18632 if (value
& ~0x3fc)
18633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18634 _("invalid offset, value too big (0x%08lX)"),
18636 newval
|= value
>> 2;
18639 case 6: /* Word load/store. */
18641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18642 _("invalid offset, value too big (0x%08lX)"),
18644 newval
|= value
<< 4; /* 6 - 2. */
18647 case 7: /* Byte load/store. */
18649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18650 _("invalid offset, value too big (0x%08lX)"),
18652 newval
|= value
<< 6;
18655 case 8: /* Halfword load/store. */
18657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18658 _("invalid offset, value too big (0x%08lX)"),
18660 newval
|= value
<< 5; /* 6 - 1. */
18664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18665 "Unable to process relocation for thumb opcode: %lx",
18666 (unsigned long) newval
);
18669 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18672 case BFD_RELOC_ARM_THUMB_ADD
:
18673 /* This is a complicated relocation, since we use it for all of
18674 the following immediate relocations:
18678 9bit ADD/SUB SP word-aligned
18679 10bit ADD PC/SP word-aligned
18681 The type of instruction being processed is encoded in the
18688 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18690 int rd
= (newval
>> 4) & 0xf;
18691 int rs
= newval
& 0xf;
18692 int subtract
= !!(newval
& 0x8000);
18694 /* Check for HI regs, only very restricted cases allowed:
18695 Adjusting SP, and using PC or SP to get an address. */
18696 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18697 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18699 _("invalid Hi register with immediate"));
18701 /* If value is negative, choose the opposite instruction. */
18705 subtract
= !subtract
;
18707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18708 _("immediate value out of range"));
18713 if (value
& ~0x1fc)
18714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18715 _("invalid immediate for stack address calculation"));
18716 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18717 newval
|= value
>> 2;
18719 else if (rs
== REG_PC
|| rs
== REG_SP
)
18721 if (subtract
|| value
& ~0x3fc)
18722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18723 _("invalid immediate for address calculation (value = 0x%08lX)"),
18724 (unsigned long) value
);
18725 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18727 newval
|= value
>> 2;
18732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18733 _("immediate value out of range"));
18734 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18735 newval
|= (rd
<< 8) | value
;
18740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18741 _("immediate value out of range"));
18742 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18743 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18746 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18749 case BFD_RELOC_ARM_THUMB_IMM
:
18750 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18751 if (value
< 0 || value
> 255)
18752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18753 _("invalid immediate: %ld is out of range"),
18756 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18759 case BFD_RELOC_ARM_THUMB_SHIFT
:
18760 /* 5bit shift value (0..32). LSL cannot take 32. */
18761 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18762 temp
= newval
& 0xf800;
18763 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18765 _("invalid shift value: %ld"), (long) value
);
18766 /* Shifts of zero must be encoded as LSL. */
18768 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18769 /* Shifts of 32 are encoded as zero. */
18770 else if (value
== 32)
18772 newval
|= value
<< 6;
18773 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18776 case BFD_RELOC_VTABLE_INHERIT
:
18777 case BFD_RELOC_VTABLE_ENTRY
:
18781 case BFD_RELOC_ARM_MOVW
:
18782 case BFD_RELOC_ARM_MOVT
:
18783 case BFD_RELOC_ARM_THUMB_MOVW
:
18784 case BFD_RELOC_ARM_THUMB_MOVT
:
18785 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18787 /* REL format relocations are limited to a 16-bit addend. */
18788 if (!fixP
->fx_done
)
18790 if (value
< -0x1000 || value
> 0xffff)
18791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18792 _("offset out of range"));
18794 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18795 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18800 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18801 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18803 newval
= get_thumb32_insn (buf
);
18804 newval
&= 0xfbf08f00;
18805 newval
|= (value
& 0xf000) << 4;
18806 newval
|= (value
& 0x0800) << 15;
18807 newval
|= (value
& 0x0700) << 4;
18808 newval
|= (value
& 0x00ff);
18809 put_thumb32_insn (buf
, newval
);
18813 newval
= md_chars_to_number (buf
, 4);
18814 newval
&= 0xfff0f000;
18815 newval
|= value
& 0x0fff;
18816 newval
|= (value
& 0xf000) << 4;
18817 md_number_to_chars (buf
, newval
, 4);
18822 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18823 case BFD_RELOC_ARM_ALU_PC_G0
:
18824 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18825 case BFD_RELOC_ARM_ALU_PC_G1
:
18826 case BFD_RELOC_ARM_ALU_PC_G2
:
18827 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18828 case BFD_RELOC_ARM_ALU_SB_G0
:
18829 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18830 case BFD_RELOC_ARM_ALU_SB_G1
:
18831 case BFD_RELOC_ARM_ALU_SB_G2
:
18832 assert (!fixP
->fx_done
);
18833 if (!seg
->use_rela_p
)
18836 bfd_vma encoded_addend
;
18837 bfd_vma addend_abs
= abs (value
);
18839 /* Check that the absolute value of the addend can be
18840 expressed as an 8-bit constant plus a rotation. */
18841 encoded_addend
= encode_arm_immediate (addend_abs
);
18842 if (encoded_addend
== (unsigned int) FAIL
)
18843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18844 _("the offset 0x%08lX is not representable"),
18845 (unsigned long) addend_abs
);
18847 /* Extract the instruction. */
18848 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18850 /* If the addend is positive, use an ADD instruction.
18851 Otherwise use a SUB. Take care not to destroy the S bit. */
18852 insn
&= 0xff1fffff;
18858 /* Place the encoded addend into the first 12 bits of the
18860 insn
&= 0xfffff000;
18861 insn
|= encoded_addend
;
18863 /* Update the instruction. */
18864 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18868 case BFD_RELOC_ARM_LDR_PC_G0
:
18869 case BFD_RELOC_ARM_LDR_PC_G1
:
18870 case BFD_RELOC_ARM_LDR_PC_G2
:
18871 case BFD_RELOC_ARM_LDR_SB_G0
:
18872 case BFD_RELOC_ARM_LDR_SB_G1
:
18873 case BFD_RELOC_ARM_LDR_SB_G2
:
18874 assert (!fixP
->fx_done
);
18875 if (!seg
->use_rela_p
)
18878 bfd_vma addend_abs
= abs (value
);
18880 /* Check that the absolute value of the addend can be
18881 encoded in 12 bits. */
18882 if (addend_abs
>= 0x1000)
18883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18884 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18885 (unsigned long) addend_abs
);
18887 /* Extract the instruction. */
18888 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18890 /* If the addend is negative, clear bit 23 of the instruction.
18891 Otherwise set it. */
18893 insn
&= ~(1 << 23);
18897 /* Place the absolute value of the addend into the first 12 bits
18898 of the instruction. */
18899 insn
&= 0xfffff000;
18900 insn
|= addend_abs
;
18902 /* Update the instruction. */
18903 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18907 case BFD_RELOC_ARM_LDRS_PC_G0
:
18908 case BFD_RELOC_ARM_LDRS_PC_G1
:
18909 case BFD_RELOC_ARM_LDRS_PC_G2
:
18910 case BFD_RELOC_ARM_LDRS_SB_G0
:
18911 case BFD_RELOC_ARM_LDRS_SB_G1
:
18912 case BFD_RELOC_ARM_LDRS_SB_G2
:
18913 assert (!fixP
->fx_done
);
18914 if (!seg
->use_rela_p
)
18917 bfd_vma addend_abs
= abs (value
);
18919 /* Check that the absolute value of the addend can be
18920 encoded in 8 bits. */
18921 if (addend_abs
>= 0x100)
18922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18923 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18924 (unsigned long) addend_abs
);
18926 /* Extract the instruction. */
18927 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18929 /* If the addend is negative, clear bit 23 of the instruction.
18930 Otherwise set it. */
18932 insn
&= ~(1 << 23);
18936 /* Place the first four bits of the absolute value of the addend
18937 into the first 4 bits of the instruction, and the remaining
18938 four into bits 8 .. 11. */
18939 insn
&= 0xfffff0f0;
18940 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18942 /* Update the instruction. */
18943 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18947 case BFD_RELOC_ARM_LDC_PC_G0
:
18948 case BFD_RELOC_ARM_LDC_PC_G1
:
18949 case BFD_RELOC_ARM_LDC_PC_G2
:
18950 case BFD_RELOC_ARM_LDC_SB_G0
:
18951 case BFD_RELOC_ARM_LDC_SB_G1
:
18952 case BFD_RELOC_ARM_LDC_SB_G2
:
18953 assert (!fixP
->fx_done
);
18954 if (!seg
->use_rela_p
)
18957 bfd_vma addend_abs
= abs (value
);
18959 /* Check that the absolute value of the addend is a multiple of
18960 four and, when divided by four, fits in 8 bits. */
18961 if (addend_abs
& 0x3)
18962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18963 _("bad offset 0x%08lX (must be word-aligned)"),
18964 (unsigned long) addend_abs
);
18966 if ((addend_abs
>> 2) > 0xff)
18967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18968 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18969 (unsigned long) addend_abs
);
18971 /* Extract the instruction. */
18972 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18974 /* If the addend is negative, clear bit 23 of the instruction.
18975 Otherwise set it. */
18977 insn
&= ~(1 << 23);
18981 /* Place the addend (divided by four) into the first eight
18982 bits of the instruction. */
18983 insn
&= 0xfffffff0;
18984 insn
|= addend_abs
>> 2;
18986 /* Update the instruction. */
18987 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18991 case BFD_RELOC_ARM_V4BX
:
18992 /* This will need to go in the object file. */
18996 case BFD_RELOC_UNUSED
:
18998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18999 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19003 /* Translate internal representation of relocation info to BFD target
19007 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19010 bfd_reloc_code_real_type code
;
19012 reloc
= xmalloc (sizeof (arelent
));
19014 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19015 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19016 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19018 if (fixp
->fx_pcrel
)
19020 if (section
->use_rela_p
)
19021 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19023 fixp
->fx_offset
= reloc
->address
;
19025 reloc
->addend
= fixp
->fx_offset
;
19027 switch (fixp
->fx_r_type
)
19030 if (fixp
->fx_pcrel
)
19032 code
= BFD_RELOC_8_PCREL
;
19037 if (fixp
->fx_pcrel
)
19039 code
= BFD_RELOC_16_PCREL
;
19044 if (fixp
->fx_pcrel
)
19046 code
= BFD_RELOC_32_PCREL
;
19050 case BFD_RELOC_ARM_MOVW
:
19051 if (fixp
->fx_pcrel
)
19053 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19057 case BFD_RELOC_ARM_MOVT
:
19058 if (fixp
->fx_pcrel
)
19060 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19064 case BFD_RELOC_ARM_THUMB_MOVW
:
19065 if (fixp
->fx_pcrel
)
19067 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19071 case BFD_RELOC_ARM_THUMB_MOVT
:
19072 if (fixp
->fx_pcrel
)
19074 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19078 case BFD_RELOC_NONE
:
19079 case BFD_RELOC_ARM_PCREL_BRANCH
:
19080 case BFD_RELOC_ARM_PCREL_BLX
:
19081 case BFD_RELOC_RVA
:
19082 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19083 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19084 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19085 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19086 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19087 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19088 case BFD_RELOC_THUMB_PCREL_BLX
:
19089 case BFD_RELOC_VTABLE_ENTRY
:
19090 case BFD_RELOC_VTABLE_INHERIT
:
19092 case BFD_RELOC_32_SECREL
:
19094 code
= fixp
->fx_r_type
;
19097 case BFD_RELOC_ARM_LITERAL
:
19098 case BFD_RELOC_ARM_HWLITERAL
:
19099 /* If this is called then the a literal has
19100 been referenced across a section boundary. */
19101 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19102 _("literal referenced across section boundary"));
19106 case BFD_RELOC_ARM_GOT32
:
19107 case BFD_RELOC_ARM_GOTOFF
:
19108 case BFD_RELOC_ARM_PLT32
:
19109 case BFD_RELOC_ARM_TARGET1
:
19110 case BFD_RELOC_ARM_ROSEGREL32
:
19111 case BFD_RELOC_ARM_SBREL32
:
19112 case BFD_RELOC_ARM_PREL31
:
19113 case BFD_RELOC_ARM_TARGET2
:
19114 case BFD_RELOC_ARM_TLS_LE32
:
19115 case BFD_RELOC_ARM_TLS_LDO32
:
19116 case BFD_RELOC_ARM_PCREL_CALL
:
19117 case BFD_RELOC_ARM_PCREL_JUMP
:
19118 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19119 case BFD_RELOC_ARM_ALU_PC_G0
:
19120 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19121 case BFD_RELOC_ARM_ALU_PC_G1
:
19122 case BFD_RELOC_ARM_ALU_PC_G2
:
19123 case BFD_RELOC_ARM_LDR_PC_G0
:
19124 case BFD_RELOC_ARM_LDR_PC_G1
:
19125 case BFD_RELOC_ARM_LDR_PC_G2
:
19126 case BFD_RELOC_ARM_LDRS_PC_G0
:
19127 case BFD_RELOC_ARM_LDRS_PC_G1
:
19128 case BFD_RELOC_ARM_LDRS_PC_G2
:
19129 case BFD_RELOC_ARM_LDC_PC_G0
:
19130 case BFD_RELOC_ARM_LDC_PC_G1
:
19131 case BFD_RELOC_ARM_LDC_PC_G2
:
19132 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19133 case BFD_RELOC_ARM_ALU_SB_G0
:
19134 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19135 case BFD_RELOC_ARM_ALU_SB_G1
:
19136 case BFD_RELOC_ARM_ALU_SB_G2
:
19137 case BFD_RELOC_ARM_LDR_SB_G0
:
19138 case BFD_RELOC_ARM_LDR_SB_G1
:
19139 case BFD_RELOC_ARM_LDR_SB_G2
:
19140 case BFD_RELOC_ARM_LDRS_SB_G0
:
19141 case BFD_RELOC_ARM_LDRS_SB_G1
:
19142 case BFD_RELOC_ARM_LDRS_SB_G2
:
19143 case BFD_RELOC_ARM_LDC_SB_G0
:
19144 case BFD_RELOC_ARM_LDC_SB_G1
:
19145 case BFD_RELOC_ARM_LDC_SB_G2
:
19146 case BFD_RELOC_ARM_V4BX
:
19147 code
= fixp
->fx_r_type
;
19150 case BFD_RELOC_ARM_TLS_GD32
:
19151 case BFD_RELOC_ARM_TLS_IE32
:
19152 case BFD_RELOC_ARM_TLS_LDM32
:
19153 /* BFD will include the symbol's address in the addend.
19154 But we don't want that, so subtract it out again here. */
19155 if (!S_IS_COMMON (fixp
->fx_addsy
))
19156 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19157 code
= fixp
->fx_r_type
;
19161 case BFD_RELOC_ARM_IMMEDIATE
:
19162 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19163 _("internal relocation (type: IMMEDIATE) not fixed up"));
19166 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19167 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19168 _("ADRL used for a symbol not defined in the same file"));
19171 case BFD_RELOC_ARM_OFFSET_IMM
:
19172 if (section
->use_rela_p
)
19174 code
= fixp
->fx_r_type
;
19178 if (fixp
->fx_addsy
!= NULL
19179 && !S_IS_DEFINED (fixp
->fx_addsy
)
19180 && S_IS_LOCAL (fixp
->fx_addsy
))
19182 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19183 _("undefined local label `%s'"),
19184 S_GET_NAME (fixp
->fx_addsy
));
19188 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19189 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19196 switch (fixp
->fx_r_type
)
19198 case BFD_RELOC_NONE
: type
= "NONE"; break;
19199 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19200 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19201 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19202 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19203 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19204 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19205 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19206 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19207 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19208 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19209 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19210 default: type
= _("<unknown>"); break;
19212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19213 _("cannot represent %s relocation in this object file format"),
19220 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19222 && fixp
->fx_addsy
== GOT_symbol
)
19224 code
= BFD_RELOC_ARM_GOTPC
;
19225 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19229 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19231 if (reloc
->howto
== NULL
)
19233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19234 _("cannot represent %s relocation in this object file format"),
19235 bfd_get_reloc_code_name (code
));
19239 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19240 vtable entry to be used in the relocation's section offset. */
19241 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19242 reloc
->address
= fixp
->fx_offset
;
19247 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19250 cons_fix_new_arm (fragS
* frag
,
19255 bfd_reloc_code_real_type type
;
19259 FIXME: @@ Should look at CPU word size. */
19263 type
= BFD_RELOC_8
;
19266 type
= BFD_RELOC_16
;
19270 type
= BFD_RELOC_32
;
19273 type
= BFD_RELOC_64
;
19278 if (exp
->X_op
== O_secrel
)
19280 exp
->X_op
= O_symbol
;
19281 type
= BFD_RELOC_32_SECREL
;
19285 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19288 #if defined OBJ_COFF || defined OBJ_ELF
19290 arm_validate_fix (fixS
* fixP
)
19292 /* If the destination of the branch is a defined symbol which does not have
19293 the THUMB_FUNC attribute, then we must be calling a function which has
19294 the (interfacearm) attribute. We look for the Thumb entry point to that
19295 function and change the branch to refer to that function instead. */
19296 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19297 && fixP
->fx_addsy
!= NULL
19298 && S_IS_DEFINED (fixP
->fx_addsy
)
19299 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19301 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19307 arm_force_relocation (struct fix
* fixp
)
19309 #if defined (OBJ_COFF) && defined (TE_PE)
19310 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19314 /* Resolve these relocations even if the symbol is extern or weak. */
19315 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19316 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19317 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19318 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19319 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19320 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19321 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19324 /* Always leave these relocations for the linker. */
19325 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19326 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19327 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19330 /* Always generate relocations against function symbols. */
19331 if (fixp
->fx_r_type
== BFD_RELOC_32
19333 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19336 return generic_force_reloc (fixp
);
19339 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19340 /* Relocations against function names must be left unadjusted,
19341 so that the linker can use this information to generate interworking
19342 stubs. The MIPS version of this function
19343 also prevents relocations that are mips-16 specific, but I do not
19344 know why it does this.
19347 There is one other problem that ought to be addressed here, but
19348 which currently is not: Taking the address of a label (rather
19349 than a function) and then later jumping to that address. Such
19350 addresses also ought to have their bottom bit set (assuming that
19351 they reside in Thumb code), but at the moment they will not. */
19354 arm_fix_adjustable (fixS
* fixP
)
19356 if (fixP
->fx_addsy
== NULL
)
19359 /* Preserve relocations against symbols with function type. */
19360 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19363 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19364 && fixP
->fx_subsy
== NULL
)
19367 /* We need the symbol name for the VTABLE entries. */
19368 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19369 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19372 /* Don't allow symbols to be discarded on GOT related relocs. */
19373 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19374 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19375 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19376 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19377 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19378 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19379 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19380 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19381 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19384 /* Similarly for group relocations. */
19385 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19386 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19387 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19392 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19397 elf32_arm_target_format (void)
19400 return (target_big_endian
19401 ? "elf32-bigarm-symbian"
19402 : "elf32-littlearm-symbian");
19403 #elif defined (TE_VXWORKS)
19404 return (target_big_endian
19405 ? "elf32-bigarm-vxworks"
19406 : "elf32-littlearm-vxworks");
19408 if (target_big_endian
)
19409 return "elf32-bigarm";
19411 return "elf32-littlearm";
19416 armelf_frob_symbol (symbolS
* symp
,
19419 elf_frob_symbol (symp
, puntp
);
19423 /* MD interface: Finalization. */
19425 /* A good place to do this, although this was probably not intended
19426 for this kind of use. We need to dump the literal pool before
19427 references are made to a null symbol pointer. */
19432 literal_pool
* pool
;
19434 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19436 /* Put it at the end of the relevant section. */
19437 subseg_set (pool
->section
, pool
->sub_section
);
19439 arm_elf_change_section ();
19445 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19449 arm_adjust_symtab (void)
19454 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19456 if (ARM_IS_THUMB (sym
))
19458 if (THUMB_IS_FUNC (sym
))
19460 /* Mark the symbol as a Thumb function. */
19461 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19462 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19463 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19465 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19466 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19468 as_bad (_("%s: unexpected function type: %d"),
19469 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19471 else switch (S_GET_STORAGE_CLASS (sym
))
19474 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19477 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19480 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19488 if (ARM_IS_INTERWORK (sym
))
19489 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19496 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19498 if (ARM_IS_THUMB (sym
))
19500 elf_symbol_type
* elf_sym
;
19502 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19503 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19505 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19506 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19508 /* If it's a .thumb_func, declare it as so,
19509 otherwise tag label as .code 16. */
19510 if (THUMB_IS_FUNC (sym
))
19511 elf_sym
->internal_elf_sym
.st_info
=
19512 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19513 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19514 elf_sym
->internal_elf_sym
.st_info
=
19515 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19522 /* MD interface: Initialization. */
19525 set_constant_flonums (void)
19529 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19530 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19534 /* Auto-select Thumb mode if it's the only available instruction set for the
19535 given architecture. */
19538 autoselect_thumb_from_cpu_variant (void)
19540 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19541 opcode_select (16);
19550 if ( (arm_ops_hsh
= hash_new ()) == NULL
19551 || (arm_cond_hsh
= hash_new ()) == NULL
19552 || (arm_shift_hsh
= hash_new ()) == NULL
19553 || (arm_psr_hsh
= hash_new ()) == NULL
19554 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19555 || (arm_reg_hsh
= hash_new ()) == NULL
19556 || (arm_reloc_hsh
= hash_new ()) == NULL
19557 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19558 as_fatal (_("virtual memory exhausted"));
19560 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19561 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19562 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19563 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19564 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19565 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19566 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19567 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19568 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19569 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19570 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19571 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19573 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19575 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19576 (PTR
) (barrier_opt_names
+ i
));
19578 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19579 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19582 set_constant_flonums ();
19584 /* Set the cpu variant based on the command-line options. We prefer
19585 -mcpu= over -march= if both are set (as for GCC); and we prefer
19586 -mfpu= over any other way of setting the floating point unit.
19587 Use of legacy options with new options are faulted. */
19590 if (mcpu_cpu_opt
|| march_cpu_opt
)
19591 as_bad (_("use of old and new-style options to set CPU type"));
19593 mcpu_cpu_opt
= legacy_cpu
;
19595 else if (!mcpu_cpu_opt
)
19596 mcpu_cpu_opt
= march_cpu_opt
;
19601 as_bad (_("use of old and new-style options to set FPU type"));
19603 mfpu_opt
= legacy_fpu
;
19605 else if (!mfpu_opt
)
19607 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19608 /* Some environments specify a default FPU. If they don't, infer it
19609 from the processor. */
19611 mfpu_opt
= mcpu_fpu_opt
;
19613 mfpu_opt
= march_fpu_opt
;
19615 mfpu_opt
= &fpu_default
;
19621 if (mcpu_cpu_opt
!= NULL
)
19622 mfpu_opt
= &fpu_default
;
19623 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19624 mfpu_opt
= &fpu_arch_vfp_v2
;
19626 mfpu_opt
= &fpu_arch_fpa
;
19632 mcpu_cpu_opt
= &cpu_default
;
19633 selected_cpu
= cpu_default
;
19637 selected_cpu
= *mcpu_cpu_opt
;
19639 mcpu_cpu_opt
= &arm_arch_any
;
19642 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19644 autoselect_thumb_from_cpu_variant ();
19646 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19648 #if defined OBJ_COFF || defined OBJ_ELF
19650 unsigned int flags
= 0;
19652 #if defined OBJ_ELF
19653 flags
= meabi_flags
;
19655 switch (meabi_flags
)
19657 case EF_ARM_EABI_UNKNOWN
:
19659 /* Set the flags in the private structure. */
19660 if (uses_apcs_26
) flags
|= F_APCS26
;
19661 if (support_interwork
) flags
|= F_INTERWORK
;
19662 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19663 if (pic_code
) flags
|= F_PIC
;
19664 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19665 flags
|= F_SOFT_FLOAT
;
19667 switch (mfloat_abi_opt
)
19669 case ARM_FLOAT_ABI_SOFT
:
19670 case ARM_FLOAT_ABI_SOFTFP
:
19671 flags
|= F_SOFT_FLOAT
;
19674 case ARM_FLOAT_ABI_HARD
:
19675 if (flags
& F_SOFT_FLOAT
)
19676 as_bad (_("hard-float conflicts with specified fpu"));
19680 /* Using pure-endian doubles (even if soft-float). */
19681 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19682 flags
|= F_VFP_FLOAT
;
19684 #if defined OBJ_ELF
19685 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19686 flags
|= EF_ARM_MAVERICK_FLOAT
;
19689 case EF_ARM_EABI_VER4
:
19690 case EF_ARM_EABI_VER5
:
19691 /* No additional flags to set. */
19698 bfd_set_private_flags (stdoutput
, flags
);
19700 /* We have run out flags in the COFF header to encode the
19701 status of ATPCS support, so instead we create a dummy,
19702 empty, debug section called .arm.atpcs. */
19707 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19711 bfd_set_section_flags
19712 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19713 bfd_set_section_size (stdoutput
, sec
, 0);
19714 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19720 /* Record the CPU type as well. */
19721 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19722 mach
= bfd_mach_arm_iWMMXt2
;
19723 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19724 mach
= bfd_mach_arm_iWMMXt
;
19725 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19726 mach
= bfd_mach_arm_XScale
;
19727 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19728 mach
= bfd_mach_arm_ep9312
;
19729 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19730 mach
= bfd_mach_arm_5TE
;
19731 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19733 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19734 mach
= bfd_mach_arm_5T
;
19736 mach
= bfd_mach_arm_5
;
19738 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19740 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19741 mach
= bfd_mach_arm_4T
;
19743 mach
= bfd_mach_arm_4
;
19745 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19746 mach
= bfd_mach_arm_3M
;
19747 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19748 mach
= bfd_mach_arm_3
;
19749 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19750 mach
= bfd_mach_arm_2a
;
19751 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19752 mach
= bfd_mach_arm_2
;
19754 mach
= bfd_mach_arm_unknown
;
19756 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19759 /* Command line processing. */
19762 Invocation line includes a switch not recognized by the base assembler.
19763 See if it's a processor-specific option.
19765 This routine is somewhat complicated by the need for backwards
19766 compatibility (since older releases of gcc can't be changed).
19767 The new options try to make the interface as compatible as
19770 New options (supported) are:
19772 -mcpu=<cpu name> Assemble for selected processor
19773 -march=<architecture name> Assemble for selected architecture
19774 -mfpu=<fpu architecture> Assemble for selected FPU.
19775 -EB/-mbig-endian Big-endian
19776 -EL/-mlittle-endian Little-endian
19777 -k Generate PIC code
19778 -mthumb Start in Thumb mode
19779 -mthumb-interwork Code supports ARM/Thumb interworking
19781 For now we will also provide support for:
19783 -mapcs-32 32-bit Program counter
19784 -mapcs-26 26-bit Program counter
19785 -macps-float Floats passed in FP registers
19786 -mapcs-reentrant Reentrant code
19788 (sometime these will probably be replaced with -mapcs=<list of options>
19789 and -matpcs=<list of options>)
19791 The remaining options are only supported for back-wards compatibility.
19792 Cpu variants, the arm part is optional:
19793 -m[arm]1 Currently not supported.
19794 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19795 -m[arm]3 Arm 3 processor
19796 -m[arm]6[xx], Arm 6 processors
19797 -m[arm]7[xx][t][[d]m] Arm 7 processors
19798 -m[arm]8[10] Arm 8 processors
19799 -m[arm]9[20][tdmi] Arm 9 processors
19800 -mstrongarm[110[0]] StrongARM processors
19801 -mxscale XScale processors
19802 -m[arm]v[2345[t[e]]] Arm architectures
19803 -mall All (except the ARM1)
19805 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19806 -mfpe-old (No float load/store multiples)
19807 -mvfpxd VFP Single precision
19809 -mno-fpu Disable all floating point instructions
19811 The following CPU names are recognized:
19812 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19813 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19814 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19815 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19816 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19817 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19818 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19822 const char * md_shortopts
= "m:k";
19824 #ifdef ARM_BI_ENDIAN
19825 #define OPTION_EB (OPTION_MD_BASE + 0)
19826 #define OPTION_EL (OPTION_MD_BASE + 1)
19828 #if TARGET_BYTES_BIG_ENDIAN
19829 #define OPTION_EB (OPTION_MD_BASE + 0)
19831 #define OPTION_EL (OPTION_MD_BASE + 1)
19834 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
19836 struct option md_longopts
[] =
19839 {"EB", no_argument
, NULL
, OPTION_EB
},
19842 {"EL", no_argument
, NULL
, OPTION_EL
},
19844 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
19845 {NULL
, no_argument
, NULL
, 0}
19848 size_t md_longopts_size
= sizeof (md_longopts
);
19850 struct arm_option_table
19852 char *option
; /* Option name to match. */
19853 char *help
; /* Help information. */
19854 int *var
; /* Variable to change. */
19855 int value
; /* What to change it to. */
19856 char *deprecated
; /* If non-null, print this message. */
19859 struct arm_option_table arm_opts
[] =
19861 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19862 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19863 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19864 &support_interwork
, 1, NULL
},
19865 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19866 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19867 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19869 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19870 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19871 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19872 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19875 /* These are recognized by the assembler, but have no affect on code. */
19876 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19877 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19878 {NULL
, NULL
, NULL
, 0, NULL
}
19881 struct arm_legacy_option_table
19883 char *option
; /* Option name to match. */
19884 const arm_feature_set
**var
; /* Variable to change. */
19885 const arm_feature_set value
; /* What to change it to. */
19886 char *deprecated
; /* If non-null, print this message. */
19889 const struct arm_legacy_option_table arm_legacy_opts
[] =
19891 /* DON'T add any new processors to this list -- we want the whole list
19892 to go away... Add them to the processors table instead. */
19893 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19894 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19895 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19896 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19897 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19898 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19899 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19900 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19901 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19902 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19903 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19904 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19905 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19906 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19907 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19908 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19909 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19910 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19911 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19912 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19913 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19914 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19915 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19916 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19917 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19918 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19919 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19920 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19921 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19922 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19923 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19924 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19925 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19926 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19927 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19928 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19929 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19930 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19931 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19932 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19933 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19934 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19935 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19936 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19937 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19938 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19939 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19940 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19941 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19942 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19943 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19944 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19945 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19946 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19947 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19948 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19949 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19950 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19951 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19952 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19953 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19954 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19955 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19956 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19957 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19958 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19959 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19960 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19961 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19962 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19963 N_("use -mcpu=strongarm110")},
19964 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19965 N_("use -mcpu=strongarm1100")},
19966 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19967 N_("use -mcpu=strongarm1110")},
19968 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19969 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19970 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19972 /* Architecture variants -- don't add any more to this list either. */
19973 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19974 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19975 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19976 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19977 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19978 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19979 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19980 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19981 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19982 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19983 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19984 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19985 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19986 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19987 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19988 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19989 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19990 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19992 /* Floating point variants -- don't add any more to this list either. */
19993 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19994 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19995 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19996 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19997 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19999 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20002 struct arm_cpu_option_table
20005 const arm_feature_set value
;
20006 /* For some CPUs we assume an FPU unless the user explicitly sets
20008 const arm_feature_set default_fpu
;
20009 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20011 const char *canonical_name
;
20014 /* This list should, at a minimum, contain all the cpu names
20015 recognized by GCC. */
20016 static const struct arm_cpu_option_table arm_cpus
[] =
20018 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20019 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20020 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20021 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20022 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20023 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20024 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20025 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20026 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20027 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20028 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20029 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20030 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20031 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20032 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20033 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20034 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20035 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20036 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20037 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20038 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20039 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20040 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20041 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20042 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20043 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20044 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20045 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20046 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20047 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20048 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20049 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20050 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20051 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20052 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20053 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20054 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20055 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20056 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20057 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20058 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20059 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20060 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20061 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20062 /* For V5 or later processors we default to using VFP; but the user
20063 should really set the FPU type explicitly. */
20064 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20065 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20066 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20067 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20068 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20069 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20070 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20071 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20072 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20073 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20074 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20075 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20076 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20077 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20078 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20079 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20080 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20081 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20082 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20083 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20084 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20085 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20086 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20087 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20088 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20089 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20090 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20091 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20092 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20093 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20094 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20095 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20096 | FPU_NEON_EXT_V1
),
20098 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20099 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20100 /* ??? XSCALE is really an architecture. */
20101 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20102 /* ??? iwmmxt is not a processor. */
20103 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20104 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20105 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20107 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20108 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20111 struct arm_arch_option_table
20114 const arm_feature_set value
;
20115 const arm_feature_set default_fpu
;
20118 /* This list should, at a minimum, contain all the architecture names
20119 recognized by GCC. */
20120 static const struct arm_arch_option_table arm_archs
[] =
20122 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20123 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20124 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20125 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20126 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20127 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20128 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20129 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20130 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20131 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20132 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20133 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20134 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20135 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20136 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20137 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20138 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20139 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20140 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20141 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20142 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20143 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20144 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20145 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20146 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20147 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20148 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20149 /* The official spelling of the ARMv7 profile variants is the dashed form.
20150 Accept the non-dashed form for compatibility with old toolchains. */
20151 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20152 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20153 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20154 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20155 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20156 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20157 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20158 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20159 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20160 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20163 /* ISA extensions in the co-processor space. */
20164 struct arm_option_cpu_value_table
20167 const arm_feature_set value
;
20170 static const struct arm_option_cpu_value_table arm_extensions
[] =
20172 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20173 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20174 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20175 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20176 {NULL
, ARM_ARCH_NONE
}
20179 /* This list should, at a minimum, contain all the fpu names
20180 recognized by GCC. */
20181 static const struct arm_option_cpu_value_table arm_fpus
[] =
20183 {"softfpa", FPU_NONE
},
20184 {"fpe", FPU_ARCH_FPE
},
20185 {"fpe2", FPU_ARCH_FPE
},
20186 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20187 {"fpa", FPU_ARCH_FPA
},
20188 {"fpa10", FPU_ARCH_FPA
},
20189 {"fpa11", FPU_ARCH_FPA
},
20190 {"arm7500fe", FPU_ARCH_FPA
},
20191 {"softvfp", FPU_ARCH_VFP
},
20192 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20193 {"vfp", FPU_ARCH_VFP_V2
},
20194 {"vfp9", FPU_ARCH_VFP_V2
},
20195 {"vfp3", FPU_ARCH_VFP_V3
},
20196 {"vfp10", FPU_ARCH_VFP_V2
},
20197 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20198 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20199 {"arm1020t", FPU_ARCH_VFP_V1
},
20200 {"arm1020e", FPU_ARCH_VFP_V2
},
20201 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20202 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20203 {"maverick", FPU_ARCH_MAVERICK
},
20204 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20205 {NULL
, ARM_ARCH_NONE
}
20208 struct arm_option_value_table
20214 static const struct arm_option_value_table arm_float_abis
[] =
20216 {"hard", ARM_FLOAT_ABI_HARD
},
20217 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20218 {"soft", ARM_FLOAT_ABI_SOFT
},
20223 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20224 static const struct arm_option_value_table arm_eabis
[] =
20226 {"gnu", EF_ARM_EABI_UNKNOWN
},
20227 {"4", EF_ARM_EABI_VER4
},
20228 {"5", EF_ARM_EABI_VER5
},
20233 struct arm_long_option_table
20235 char * option
; /* Substring to match. */
20236 char * help
; /* Help information. */
20237 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20238 char * deprecated
; /* If non-null, print this message. */
20242 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20244 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20246 /* Copy the feature set, so that we can modify it. */
20247 *ext_set
= **opt_p
;
20250 while (str
!= NULL
&& *str
!= 0)
20252 const struct arm_option_cpu_value_table
* opt
;
20258 as_bad (_("invalid architectural extension"));
20263 ext
= strchr (str
, '+');
20266 optlen
= ext
- str
;
20268 optlen
= strlen (str
);
20272 as_bad (_("missing architectural extension"));
20276 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20277 if (strncmp (opt
->name
, str
, optlen
) == 0)
20279 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20283 if (opt
->name
== NULL
)
20285 as_bad (_("unknown architectural extension `%s'"), str
);
20296 arm_parse_cpu (char * str
)
20298 const struct arm_cpu_option_table
* opt
;
20299 char * ext
= strchr (str
, '+');
20303 optlen
= ext
- str
;
20305 optlen
= strlen (str
);
20309 as_bad (_("missing cpu name `%s'"), str
);
20313 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20314 if (strncmp (opt
->name
, str
, optlen
) == 0)
20316 mcpu_cpu_opt
= &opt
->value
;
20317 mcpu_fpu_opt
= &opt
->default_fpu
;
20318 if (opt
->canonical_name
)
20319 strcpy (selected_cpu_name
, opt
->canonical_name
);
20323 for (i
= 0; i
< optlen
; i
++)
20324 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20325 selected_cpu_name
[i
] = 0;
20329 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20334 as_bad (_("unknown cpu `%s'"), str
);
20339 arm_parse_arch (char * str
)
20341 const struct arm_arch_option_table
*opt
;
20342 char *ext
= strchr (str
, '+');
20346 optlen
= ext
- str
;
20348 optlen
= strlen (str
);
20352 as_bad (_("missing architecture name `%s'"), str
);
20356 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20357 if (streq (opt
->name
, str
))
20359 march_cpu_opt
= &opt
->value
;
20360 march_fpu_opt
= &opt
->default_fpu
;
20361 strcpy (selected_cpu_name
, opt
->name
);
20364 return arm_parse_extension (ext
, &march_cpu_opt
);
20369 as_bad (_("unknown architecture `%s'\n"), str
);
20374 arm_parse_fpu (char * str
)
20376 const struct arm_option_cpu_value_table
* opt
;
20378 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20379 if (streq (opt
->name
, str
))
20381 mfpu_opt
= &opt
->value
;
20385 as_bad (_("unknown floating point format `%s'\n"), str
);
20390 arm_parse_float_abi (char * str
)
20392 const struct arm_option_value_table
* opt
;
20394 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20395 if (streq (opt
->name
, str
))
20397 mfloat_abi_opt
= opt
->value
;
20401 as_bad (_("unknown floating point abi `%s'\n"), str
);
20407 arm_parse_eabi (char * str
)
20409 const struct arm_option_value_table
*opt
;
20411 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20412 if (streq (opt
->name
, str
))
20414 meabi_flags
= opt
->value
;
20417 as_bad (_("unknown EABI `%s'\n"), str
);
20422 struct arm_long_option_table arm_long_opts
[] =
20424 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20425 arm_parse_cpu
, NULL
},
20426 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20427 arm_parse_arch
, NULL
},
20428 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20429 arm_parse_fpu
, NULL
},
20430 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20431 arm_parse_float_abi
, NULL
},
20433 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20434 arm_parse_eabi
, NULL
},
20436 {NULL
, NULL
, 0, NULL
}
20440 md_parse_option (int c
, char * arg
)
20442 struct arm_option_table
*opt
;
20443 const struct arm_legacy_option_table
*fopt
;
20444 struct arm_long_option_table
*lopt
;
20450 target_big_endian
= 1;
20456 target_big_endian
= 0;
20460 case OPTION_FIX_V4BX
:
20465 /* Listing option. Just ignore these, we don't support additional
20470 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20472 if (c
== opt
->option
[0]
20473 && ((arg
== NULL
&& opt
->option
[1] == 0)
20474 || streq (arg
, opt
->option
+ 1)))
20476 #if WARN_DEPRECATED
20477 /* If the option is deprecated, tell the user. */
20478 if (opt
->deprecated
!= NULL
)
20479 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20480 arg
? arg
: "", _(opt
->deprecated
));
20483 if (opt
->var
!= NULL
)
20484 *opt
->var
= opt
->value
;
20490 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20492 if (c
== fopt
->option
[0]
20493 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20494 || streq (arg
, fopt
->option
+ 1)))
20496 #if WARN_DEPRECATED
20497 /* If the option is deprecated, tell the user. */
20498 if (fopt
->deprecated
!= NULL
)
20499 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20500 arg
? arg
: "", _(fopt
->deprecated
));
20503 if (fopt
->var
!= NULL
)
20504 *fopt
->var
= &fopt
->value
;
20510 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20512 /* These options are expected to have an argument. */
20513 if (c
== lopt
->option
[0]
20515 && strncmp (arg
, lopt
->option
+ 1,
20516 strlen (lopt
->option
+ 1)) == 0)
20518 #if WARN_DEPRECATED
20519 /* If the option is deprecated, tell the user. */
20520 if (lopt
->deprecated
!= NULL
)
20521 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20522 _(lopt
->deprecated
));
20525 /* Call the sup-option parser. */
20526 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20537 md_show_usage (FILE * fp
)
20539 struct arm_option_table
*opt
;
20540 struct arm_long_option_table
*lopt
;
20542 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20544 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20545 if (opt
->help
!= NULL
)
20546 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20548 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20549 if (lopt
->help
!= NULL
)
20550 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20554 -EB assemble code for a big-endian cpu\n"));
20559 -EL assemble code for a little-endian cpu\n"));
20563 --fix-v4bx Allow BX in ARMv4 code\n"));
20571 arm_feature_set flags
;
20572 } cpu_arch_ver_table
;
20574 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20575 least features first. */
20576 static const cpu_arch_ver_table cpu_arch_ver
[] =
20581 {4, ARM_ARCH_V5TE
},
20582 {5, ARM_ARCH_V5TEJ
},
20586 {9, ARM_ARCH_V6T2
},
20587 {10, ARM_ARCH_V7A
},
20588 {10, ARM_ARCH_V7R
},
20589 {10, ARM_ARCH_V7M
},
20593 /* Set the public EABI object attributes. */
20595 aeabi_set_public_attributes (void)
20598 arm_feature_set flags
;
20599 arm_feature_set tmp
;
20600 const cpu_arch_ver_table
*p
;
20602 /* Choose the architecture based on the capabilities of the requested cpu
20603 (if any) and/or the instructions actually used. */
20604 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20605 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20606 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20607 /*Allow the user to override the reported architecture. */
20610 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20611 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20616 for (p
= cpu_arch_ver
; p
->val
; p
++)
20618 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20621 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20625 /* Tag_CPU_name. */
20626 if (selected_cpu_name
[0])
20630 p
= selected_cpu_name
;
20631 if (strncmp (p
, "armv", 4) == 0)
20636 for (i
= 0; p
[i
]; i
++)
20637 p
[i
] = TOUPPER (p
[i
]);
20639 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20641 /* Tag_CPU_arch. */
20642 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20643 /* Tag_CPU_arch_profile. */
20644 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20645 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20646 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20647 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20648 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20649 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20650 /* Tag_ARM_ISA_use. */
20651 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20652 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20653 /* Tag_THUMB_ISA_use. */
20654 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20655 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20656 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20657 /* Tag_VFP_arch. */
20658 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20659 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20660 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20661 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20662 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20663 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20664 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20665 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20666 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20667 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20668 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20669 /* Tag_WMMX_arch. */
20670 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20671 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20672 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20673 /* Tag_NEON_arch. */
20674 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20675 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20676 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20679 /* Add the default contents for the .ARM.attributes section. */
20683 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20686 aeabi_set_public_attributes ();
20688 #endif /* OBJ_ELF */
20691 /* Parse a .cpu directive. */
20694 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20696 const struct arm_cpu_option_table
*opt
;
20700 name
= input_line_pointer
;
20701 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20702 input_line_pointer
++;
20703 saved_char
= *input_line_pointer
;
20704 *input_line_pointer
= 0;
20706 /* Skip the first "all" entry. */
20707 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20708 if (streq (opt
->name
, name
))
20710 mcpu_cpu_opt
= &opt
->value
;
20711 selected_cpu
= opt
->value
;
20712 if (opt
->canonical_name
)
20713 strcpy (selected_cpu_name
, opt
->canonical_name
);
20717 for (i
= 0; opt
->name
[i
]; i
++)
20718 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20719 selected_cpu_name
[i
] = 0;
20721 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20722 *input_line_pointer
= saved_char
;
20723 demand_empty_rest_of_line ();
20726 as_bad (_("unknown cpu `%s'"), name
);
20727 *input_line_pointer
= saved_char
;
20728 ignore_rest_of_line ();
20732 /* Parse a .arch directive. */
20735 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20737 const struct arm_arch_option_table
*opt
;
20741 name
= input_line_pointer
;
20742 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20743 input_line_pointer
++;
20744 saved_char
= *input_line_pointer
;
20745 *input_line_pointer
= 0;
20747 /* Skip the first "all" entry. */
20748 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20749 if (streq (opt
->name
, name
))
20751 mcpu_cpu_opt
= &opt
->value
;
20752 selected_cpu
= opt
->value
;
20753 strcpy (selected_cpu_name
, opt
->name
);
20754 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20755 *input_line_pointer
= saved_char
;
20756 demand_empty_rest_of_line ();
20760 as_bad (_("unknown architecture `%s'\n"), name
);
20761 *input_line_pointer
= saved_char
;
20762 ignore_rest_of_line ();
20766 /* Parse a .object_arch directive. */
20769 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20771 const struct arm_arch_option_table
*opt
;
20775 name
= input_line_pointer
;
20776 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20777 input_line_pointer
++;
20778 saved_char
= *input_line_pointer
;
20779 *input_line_pointer
= 0;
20781 /* Skip the first "all" entry. */
20782 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20783 if (streq (opt
->name
, name
))
20785 object_arch
= &opt
->value
;
20786 *input_line_pointer
= saved_char
;
20787 demand_empty_rest_of_line ();
20791 as_bad (_("unknown architecture `%s'\n"), name
);
20792 *input_line_pointer
= saved_char
;
20793 ignore_rest_of_line ();
20797 /* Parse a .fpu directive. */
20800 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20802 const struct arm_option_cpu_value_table
*opt
;
20806 name
= input_line_pointer
;
20807 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20808 input_line_pointer
++;
20809 saved_char
= *input_line_pointer
;
20810 *input_line_pointer
= 0;
20812 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20813 if (streq (opt
->name
, name
))
20815 mfpu_opt
= &opt
->value
;
20816 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20817 *input_line_pointer
= saved_char
;
20818 demand_empty_rest_of_line ();
20822 as_bad (_("unknown floating point format `%s'\n"), name
);
20823 *input_line_pointer
= saved_char
;
20824 ignore_rest_of_line ();
20827 /* Copy symbol information. */
20829 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20831 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);