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[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include <string.h>
25 #define NO_RELOC 0
26 #include "as.h"
27
28 /* need TARGET_CPU */
29 #include "config.h"
30 #include "subsegs.h"
31 #include "obstack.h"
32 #include "symbols.h"
33 #include "listing.h"
34
35 #ifdef OBJ_ELF
36 #include "elf/arm.h"
37 #endif
38
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
43 #define ARM_250 ARM_3
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
49
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55
56 /* Architectures are the sum of the base and extensions. */
57 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
58 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
59 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
60 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
61
62 /* Some useful combinations: */
63 #define ARM_ANY 0x00ffffff
64 #define ARM_2UP (ARM_ANY - ARM_1)
65 #define ARM_ALL ARM_2UP /* Not arm1 only */
66 #define ARM_3UP 0x00fffffc
67 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
68
69 #define FPU_CORE 0x80000000
70 #define FPU_FPA10 0x40000000
71 #define FPU_FPA11 0x40000000
72 #define FPU_NONE 0
73
74 /* Some useful combinations */
75 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
76 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
77
78
79 #ifndef CPU_DEFAULT
80 #if defined __thumb__
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
82 #else
83 #define CPU_DEFAULT ARM_ALL
84 #endif
85 #endif
86
87 #ifndef FPU_DEFAULT
88 #define FPU_DEFAULT FPU_ALL
89 #endif
90
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
93
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
96
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
103 #endif
104
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
108
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
117
118 CONST char line_separator_chars[] = ";";
119
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
123
124 /* Chars that mean this number is a floating point constant */
125 /* As in 0f12.456 */
126 /* or 0d1.2345e12 */
127
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
129
130 /* Prefix characters that indicate the start of an immediate
131 value. */
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
133
134 #ifdef OBJ_ELF
135 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
136 #endif
137
138 CONST int md_reloc_size = 8; /* Size of relocation record */
139
140 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
141 2: assemble for Thumb even though target cpu
142 does not support thumb instructions. */
143 typedef struct arm_fix
144 {
145 int thumb_mode;
146 } arm_fix_data;
147
148 struct arm_it
149 {
150 CONST char * error;
151 unsigned long instruction;
152 int suffix;
153 int size;
154 struct
155 {
156 bfd_reloc_code_real_type type;
157 expressionS exp;
158 int pc_rel;
159 } reloc;
160 };
161
162 struct arm_it inst;
163
164 struct asm_shift
165 {
166 CONST char * template;
167 unsigned long value;
168 };
169
170 static CONST struct asm_shift shift[] =
171 {
172 {"asl", 0},
173 {"lsl", 0},
174 {"lsr", 0x00000020},
175 {"asr", 0x00000040},
176 {"ror", 0x00000060},
177 {"rrx", 0x00000060},
178 {"ASL", 0},
179 {"LSL", 0},
180 {"LSR", 0x00000020},
181 {"ASR", 0x00000040},
182 {"ROR", 0x00000060},
183 {"RRX", 0x00000060}
184 };
185
186 #define NO_SHIFT_RESTRICT 1
187 #define SHIFT_RESTRICT 0
188
189 #define NUM_FLOAT_VALS 8
190
191 CONST char * fp_const[] =
192 {
193 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
194 };
195
196 /* Number of littlenums required to hold an extended precision number. */
197 #define MAX_LITTLENUMS 6
198
199 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
200
201 #define FAIL (-1)
202 #define SUCCESS (0)
203
204 #define SUFF_S 1
205 #define SUFF_D 2
206 #define SUFF_E 3
207 #define SUFF_P 4
208
209 #define CP_T_X 0x00008000
210 #define CP_T_Y 0x00400000
211 #define CP_T_Pre 0x01000000
212 #define CP_T_UD 0x00800000
213 #define CP_T_WB 0x00200000
214
215 #define CONDS_BIT (0x00100000)
216 #define LOAD_BIT (0x00100000)
217 #define TRANS_BIT (0x00200000)
218
219 struct asm_cond
220 {
221 CONST char * template;
222 unsigned long value;
223 };
224
225 /* This is to save a hash look-up in the common case. */
226 #define COND_ALWAYS 0xe0000000
227
228 static CONST struct asm_cond conds[] =
229 {
230 {"eq", 0x00000000},
231 {"ne", 0x10000000},
232 {"cs", 0x20000000}, {"hs", 0x20000000},
233 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
234 {"mi", 0x40000000},
235 {"pl", 0x50000000},
236 {"vs", 0x60000000},
237 {"vc", 0x70000000},
238 {"hi", 0x80000000},
239 {"ls", 0x90000000},
240 {"ge", 0xa0000000},
241 {"lt", 0xb0000000},
242 {"gt", 0xc0000000},
243 {"le", 0xd0000000},
244 {"al", 0xe0000000},
245 {"nv", 0xf0000000}
246 };
247
248 /* Warning: If the top bit of the set_bits is set, then the standard
249 instruction bitmask is ignored, and the new bitmask is taken from
250 the set_bits: */
251 struct asm_flg
252 {
253 CONST char * template; /* Basic flag string */
254 unsigned long set_bits; /* Bits to set */
255 };
256
257 static CONST struct asm_flg s_flag[] =
258 {
259 {"s", CONDS_BIT},
260 {NULL, 0}
261 };
262
263 static CONST struct asm_flg ldr_flags[] =
264 {
265 {"b", 0x00400000},
266 {"t", TRANS_BIT},
267 {"bt", 0x00400000 | TRANS_BIT},
268 {"h", 0x801000b0},
269 {"sh", 0x801000f0},
270 {"sb", 0x801000d0},
271 {NULL, 0}
272 };
273
274 static CONST struct asm_flg str_flags[] =
275 {
276 {"b", 0x00400000},
277 {"t", TRANS_BIT},
278 {"bt", 0x00400000 | TRANS_BIT},
279 {"h", 0x800000b0},
280 {NULL, 0}
281 };
282
283 static CONST struct asm_flg byte_flag[] =
284 {
285 {"b", 0x00400000},
286 {NULL, 0}
287 };
288
289 static CONST struct asm_flg cmp_flags[] =
290 {
291 {"s", CONDS_BIT},
292 {"p", 0x0010f000},
293 {NULL, 0}
294 };
295
296 static CONST struct asm_flg ldm_flags[] =
297 {
298 {"ed", 0x01800000},
299 {"fd", 0x00800000},
300 {"ea", 0x01000000},
301 {"fa", 0x08000000},
302 {"ib", 0x01800000},
303 {"ia", 0x00800000},
304 {"db", 0x01000000},
305 {"da", 0x08000000},
306 {NULL, 0}
307 };
308
309 static CONST struct asm_flg stm_flags[] =
310 {
311 {"ed", 0x08000000},
312 {"fd", 0x01000000},
313 {"ea", 0x00800000},
314 {"fa", 0x01800000},
315 {"ib", 0x01800000},
316 {"ia", 0x00800000},
317 {"db", 0x01000000},
318 {"da", 0x08000000},
319 {NULL, 0}
320 };
321
322 static CONST struct asm_flg lfm_flags[] =
323 {
324 {"fd", 0x00800000},
325 {"ea", 0x01000000},
326 {NULL, 0}
327 };
328
329 static CONST struct asm_flg sfm_flags[] =
330 {
331 {"fd", 0x01000000},
332 {"ea", 0x00800000},
333 {NULL, 0}
334 };
335
336 static CONST struct asm_flg round_flags[] =
337 {
338 {"p", 0x00000020},
339 {"m", 0x00000040},
340 {"z", 0x00000060},
341 {NULL, 0}
342 };
343
344 /* The implementation of the FIX instruction is broken on some assemblers,
345 in that it accepts a precision specifier as well as a rounding specifier,
346 despite the fact that this is meaningless. To be more compatible, we
347 accept it as well, though of course it does not set any bits. */
348 static CONST struct asm_flg fix_flags[] =
349 {
350 {"p", 0x00000020},
351 {"m", 0x00000040},
352 {"z", 0x00000060},
353 {"sp", 0x00000020},
354 {"sm", 0x00000040},
355 {"sz", 0x00000060},
356 {"dp", 0x00000020},
357 {"dm", 0x00000040},
358 {"dz", 0x00000060},
359 {"ep", 0x00000020},
360 {"em", 0x00000040},
361 {"ez", 0x00000060},
362 {NULL, 0}
363 };
364
365 static CONST struct asm_flg except_flag[] =
366 {
367 {"e", 0x00400000},
368 {NULL, 0}
369 };
370
371 static CONST struct asm_flg cplong_flag[] =
372 {
373 {"l", 0x00400000},
374 {NULL, 0}
375 };
376
377 struct asm_psr
378 {
379 CONST char * template;
380 boolean cpsr;
381 unsigned long field;
382 };
383
384 #define SPSR_BIT (1 << 22) /* The bit that distnguishes CPSR and SPSR. */
385 #define PSR_SHIFT 16 /* How many bits to shift the PSR_xxx bits up by. */
386
387 #define PSR_c (1 << 0)
388 #define PSR_x (1 << 1)
389 #define PSR_s (1 << 2)
390 #define PSR_f (1 << 3)
391
392 static CONST struct asm_psr psrs[] =
393 {
394 {"CPSR", true, PSR_c | PSR_f},
395 {"CPSR_all", true, PSR_c | PSR_f},
396 {"SPSR", false, PSR_c | PSR_f},
397 {"SPSR_all", false, PSR_c | PSR_f},
398 {"CPSR_flg", true, PSR_f},
399 {"CPSR_f", true, PSR_f},
400 {"SPSR_flg", false, PSR_f},
401 {"SPSR_f", false, PSR_f},
402 {"CPSR_c", true, PSR_c},
403 {"CPSR_ctl", true, PSR_c},
404 {"SPSR_c", false, PSR_c},
405 {"SPSR_ctl", false, PSR_c},
406 {"CPSR_x", true, PSR_x},
407 {"CPSR_s", true, PSR_s},
408 {"SPSR_x", false, PSR_x},
409 {"SPSR_s", false, PSR_s},
410 /* For backwards compatability with older toolchain we also
411 support lower case versions of some of these flags. */
412 {"cpsr", true, PSR_c | PSR_f},
413 {"cpsr_all", true, PSR_c | PSR_f},
414 {"spsr", false, PSR_c | PSR_f},
415 {"spsr_all", false, PSR_c | PSR_f},
416 {"cpsr_flg", true, PSR_f},
417 {"cpsr_f", true, PSR_f},
418 {"spsr_flg", false, PSR_f},
419 {"spsr_f", false, PSR_f},
420 {"cpsr_c", true, PSR_c},
421 {"cpsr_ctl", true, PSR_c},
422 {"spsr_c", false, PSR_c},
423 {"spsr_ctl", false, PSR_c}
424 };
425
426 /* Functions called by parser. */
427 /* ARM instructions */
428 static void do_arit PARAMS ((char *, unsigned long));
429 static void do_cmp PARAMS ((char *, unsigned long));
430 static void do_mov PARAMS ((char *, unsigned long));
431 static void do_ldst PARAMS ((char *, unsigned long));
432 static void do_ldmstm PARAMS ((char *, unsigned long));
433 static void do_branch PARAMS ((char *, unsigned long));
434 static void do_swi PARAMS ((char *, unsigned long));
435 /* Pseudo Op codes */
436 static void do_adr PARAMS ((char *, unsigned long));
437 static void do_adrl PARAMS ((char *, unsigned long));
438 static void do_nop PARAMS ((char *, unsigned long));
439 /* ARM 2 */
440 static void do_mul PARAMS ((char *, unsigned long));
441 static void do_mla PARAMS ((char *, unsigned long));
442 /* ARM 3 */
443 static void do_swap PARAMS ((char *, unsigned long));
444 /* ARM 6 */
445 static void do_msr PARAMS ((char *, unsigned long));
446 static void do_mrs PARAMS ((char *, unsigned long));
447 /* ARM 7M */
448 static void do_mull PARAMS ((char *, unsigned long));
449 /* ARM THUMB */
450 static void do_bx PARAMS ((char *, unsigned long));
451
452
453 /* Coprocessor Instructions */
454 static void do_cdp PARAMS ((char *, unsigned long));
455 static void do_lstc PARAMS ((char *, unsigned long));
456 static void do_co_reg PARAMS ((char *, unsigned long));
457 static void do_fp_ctrl PARAMS ((char *, unsigned long));
458 static void do_fp_ldst PARAMS ((char *, unsigned long));
459 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
460 static void do_fp_dyadic PARAMS ((char *, unsigned long));
461 static void do_fp_monadic PARAMS ((char *, unsigned long));
462 static void do_fp_cmp PARAMS ((char *, unsigned long));
463 static void do_fp_from_reg PARAMS ((char *, unsigned long));
464 static void do_fp_to_reg PARAMS ((char *, unsigned long));
465
466 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
467 static int arm_reg_parse PARAMS ((char **));
468 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
469 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
470 static int add_to_lit_pool PARAMS ((void));
471 static unsigned validate_immediate PARAMS ((unsigned));
472 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
473 static int validate_offset_imm PARAMS ((unsigned int, int));
474 static void opcode_select PARAMS ((int));
475 static void end_of_line PARAMS ((char *));
476 static int reg_required_here PARAMS ((char **, int));
477 static int psr_required_here PARAMS ((char **));
478 static int co_proc_number PARAMS ((char **));
479 static int cp_opc_expr PARAMS ((char **, int, int));
480 static int cp_reg_required_here PARAMS ((char **, int));
481 static int fp_reg_required_here PARAMS ((char **, int));
482 static int cp_address_offset PARAMS ((char **));
483 static int cp_address_required_here PARAMS ((char **));
484 static int my_get_float_expression PARAMS ((char **));
485 static int skip_past_comma PARAMS ((char **));
486 static int walk_no_bignums PARAMS ((symbolS *));
487 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
488 static int data_op2 PARAMS ((char **));
489 static int fp_op2 PARAMS ((char **));
490 static long reg_list PARAMS ((char **));
491 static void thumb_load_store PARAMS ((char *, int, int));
492 static int decode_shift PARAMS ((char **, int));
493 static int ldst_extend PARAMS ((char **, int));
494 static void thumb_add_sub PARAMS ((char *, int));
495 static void insert_reg PARAMS ((int));
496 static void thumb_shift PARAMS ((char *, int));
497 static void thumb_mov_compare PARAMS ((char *, int));
498 static void set_constant_flonums PARAMS ((void));
499 static valueT md_chars_to_number PARAMS ((char *, int));
500 static void insert_reg_alias PARAMS ((char *, int));
501 static void output_inst PARAMS ((void));
502 #ifdef OBJ_ELF
503 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
504 #endif
505
506 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 take 2: */
508 #define INSN_SIZE 4
509
510 /* LONGEST_INST is the longest basic instruction name without conditions or
511 flags. ARM7M has 4 of length 5. */
512
513 #define LONGEST_INST 5
514
515
516 struct asm_opcode
517 {
518 CONST char * template; /* Basic string to match */
519 unsigned long value; /* Basic instruction code */
520
521 /* Compulsory suffix that must follow conds. If "", then the
522 instruction is not conditional and must have no suffix. */
523 CONST char * comp_suffix;
524
525 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
526 unsigned long variants; /* Which CPU variants this exists for */
527 /* Function to call to parse args */
528 void (* parms) PARAMS ((char *, unsigned long));
529 };
530
531 static CONST struct asm_opcode insns[] =
532 {
533 /* ARM Instructions */
534 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
535 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
536 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
537 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
538 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
539 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
540 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
541 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
542 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
543 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
544 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
545 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
546 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
547 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
548 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
549 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
550 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
551 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
552 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
553 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
554 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
555 #ifdef TE_WINCE
556 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
557 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
558 #else
559 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
560 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
561 #endif
562
563 /* Pseudo ops */
564 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
565 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
566 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
567
568 /* ARM 2 multiplies */
569 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
570 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
571
572 /* ARM 3 - swp instructions */
573 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
574
575 /* ARM 6 Coprocessor instructions */
576 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
577 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
578 /* ScottB: our code uses 0x0128f000 for msr.
579 NickC: but this is wrong because the bits 16 through 19 are
580 handled by the PSR_xxx defines above. */
581
582 /* ARM 7M long multiplies - need signed/unsigned flags! */
583 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
584 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
585 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
586 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
587
588 /* ARM THUMB interworking */
589 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
590
591 /* Floating point instructions */
592 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
593 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
594 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
595 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
596 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
597 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
598 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
599 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
600 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
607 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
608 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
609 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
610 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
611 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
612 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
613 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
614 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
615 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
616 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
620 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
621 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
622 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
623 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
624 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
625 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
626 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
627 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
628 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
629 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
630 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
631 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
632 be an optional suffix, but part of the instruction. To be compatible,
633 we accept either. */
634 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
635 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
636 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
637 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
638
639 /* Generic copressor instructions. */
640 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
641 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
642 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
643 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
644 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
645 };
646
647 /* Defines for various bits that we will want to toggle. */
648 #define INST_IMMEDIATE 0x02000000
649 #define OFFSET_REG 0x02000000
650 #define HWOFFSET_IMM 0x00400000
651 #define SHIFT_BY_REG 0x00000010
652 #define PRE_INDEX 0x01000000
653 #define INDEX_UP 0x00800000
654 #define WRITE_BACK 0x00200000
655 #define LDM_TYPE_2_OR_3 0x00400000
656
657 #define LITERAL_MASK 0xf000f000
658 #define COND_MASK 0xf0000000
659 #define OPCODE_MASK 0xfe1fffff
660 #define DATA_OP_SHIFT 21
661
662 /* Codes to distinguish the arithmetic instructions. */
663 #define OPCODE_AND 0
664 #define OPCODE_EOR 1
665 #define OPCODE_SUB 2
666 #define OPCODE_RSB 3
667 #define OPCODE_ADD 4
668 #define OPCODE_ADC 5
669 #define OPCODE_SBC 6
670 #define OPCODE_RSC 7
671 #define OPCODE_TST 8
672 #define OPCODE_TEQ 9
673 #define OPCODE_CMP 10
674 #define OPCODE_CMN 11
675 #define OPCODE_ORR 12
676 #define OPCODE_MOV 13
677 #define OPCODE_BIC 14
678 #define OPCODE_MVN 15
679
680 static void do_t_nop PARAMS ((char *));
681 static void do_t_arit PARAMS ((char *));
682 static void do_t_add PARAMS ((char *));
683 static void do_t_asr PARAMS ((char *));
684 static void do_t_branch9 PARAMS ((char *));
685 static void do_t_branch12 PARAMS ((char *));
686 static void do_t_branch23 PARAMS ((char *));
687 static void do_t_bx PARAMS ((char *));
688 static void do_t_compare PARAMS ((char *));
689 static void do_t_ldmstm PARAMS ((char *));
690 static void do_t_ldr PARAMS ((char *));
691 static void do_t_ldrb PARAMS ((char *));
692 static void do_t_ldrh PARAMS ((char *));
693 static void do_t_lds PARAMS ((char *));
694 static void do_t_lsl PARAMS ((char *));
695 static void do_t_lsr PARAMS ((char *));
696 static void do_t_mov PARAMS ((char *));
697 static void do_t_push_pop PARAMS ((char *));
698 static void do_t_str PARAMS ((char *));
699 static void do_t_strb PARAMS ((char *));
700 static void do_t_strh PARAMS ((char *));
701 static void do_t_sub PARAMS ((char *));
702 static void do_t_swi PARAMS ((char *));
703 static void do_t_adr PARAMS ((char *));
704
705 #define T_OPCODE_MUL 0x4340
706 #define T_OPCODE_TST 0x4200
707 #define T_OPCODE_CMN 0x42c0
708 #define T_OPCODE_NEG 0x4240
709 #define T_OPCODE_MVN 0x43c0
710
711 #define T_OPCODE_ADD_R3 0x1800
712 #define T_OPCODE_SUB_R3 0x1a00
713 #define T_OPCODE_ADD_HI 0x4400
714 #define T_OPCODE_ADD_ST 0xb000
715 #define T_OPCODE_SUB_ST 0xb080
716 #define T_OPCODE_ADD_SP 0xa800
717 #define T_OPCODE_ADD_PC 0xa000
718 #define T_OPCODE_ADD_I8 0x3000
719 #define T_OPCODE_SUB_I8 0x3800
720 #define T_OPCODE_ADD_I3 0x1c00
721 #define T_OPCODE_SUB_I3 0x1e00
722
723 #define T_OPCODE_ASR_R 0x4100
724 #define T_OPCODE_LSL_R 0x4080
725 #define T_OPCODE_LSR_R 0x40c0
726 #define T_OPCODE_ASR_I 0x1000
727 #define T_OPCODE_LSL_I 0x0000
728 #define T_OPCODE_LSR_I 0x0800
729
730 #define T_OPCODE_MOV_I8 0x2000
731 #define T_OPCODE_CMP_I8 0x2800
732 #define T_OPCODE_CMP_LR 0x4280
733 #define T_OPCODE_MOV_HR 0x4600
734 #define T_OPCODE_CMP_HR 0x4500
735
736 #define T_OPCODE_LDR_PC 0x4800
737 #define T_OPCODE_LDR_SP 0x9800
738 #define T_OPCODE_STR_SP 0x9000
739 #define T_OPCODE_LDR_IW 0x6800
740 #define T_OPCODE_STR_IW 0x6000
741 #define T_OPCODE_LDR_IH 0x8800
742 #define T_OPCODE_STR_IH 0x8000
743 #define T_OPCODE_LDR_IB 0x7800
744 #define T_OPCODE_STR_IB 0x7000
745 #define T_OPCODE_LDR_RW 0x5800
746 #define T_OPCODE_STR_RW 0x5000
747 #define T_OPCODE_LDR_RH 0x5a00
748 #define T_OPCODE_STR_RH 0x5200
749 #define T_OPCODE_LDR_RB 0x5c00
750 #define T_OPCODE_STR_RB 0x5400
751
752 #define T_OPCODE_PUSH 0xb400
753 #define T_OPCODE_POP 0xbc00
754
755 #define T_OPCODE_BRANCH 0xe7fe
756
757 static int thumb_reg PARAMS ((char ** str, int hi_lo));
758
759 #define THUMB_SIZE 2 /* Size of thumb instruction. */
760 #define THUMB_REG_LO 0x1
761 #define THUMB_REG_HI 0x2
762 #define THUMB_REG_ANY 0x3
763
764 #define THUMB_H1 0x0080
765 #define THUMB_H2 0x0040
766
767 #define THUMB_ASR 0
768 #define THUMB_LSL 1
769 #define THUMB_LSR 2
770
771 #define THUMB_MOVE 0
772 #define THUMB_COMPARE 1
773
774 #define THUMB_LOAD 0
775 #define THUMB_STORE 1
776
777 #define THUMB_PP_PC_LR 0x0100
778
779 /* These three are used for immediate shifts, do not alter. */
780 #define THUMB_WORD 2
781 #define THUMB_HALFWORD 1
782 #define THUMB_BYTE 0
783
784 struct thumb_opcode
785 {
786 CONST char * template; /* Basic string to match */
787 unsigned long value; /* Basic instruction code */
788 int size;
789 unsigned long variants; /* Which CPU variants this exists for */
790 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
791 };
792
793 static CONST struct thumb_opcode tinsns[] =
794 {
795 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
796 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
797 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
798 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
799 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
800 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
801 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
802 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
803 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
804 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
805 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
806 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
807 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
808 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
809 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
810 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
811 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
812 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
813 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
814 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
815 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
816 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
817 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
818 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
819 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
820 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
821 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
822 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
823 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
824 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
825 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
826 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
827 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
828 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
829 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
830 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
831 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
832 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
833 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
834 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
835 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
836 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
837 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
838 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
839 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
840 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
841 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
842 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
843 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
844 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
845 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
846 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
847 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
848 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
849 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
850 /* Pseudo ops: */
851 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
852 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
853 };
854
855 struct reg_entry
856 {
857 CONST char * name;
858 int number;
859 };
860
861 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
862 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
863 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
864
865 #define REG_PC 15
866 #define REG_LR 14
867 #define REG_SP 13
868
869 /* These are the standard names. Users can add aliases with .req */
870 static CONST struct reg_entry reg_table[] =
871 {
872 /* Processor Register Numbers. */
873 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
874 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
875 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
876 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
877 /* APCS conventions. */
878 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
879 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
880 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
881 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
882 /* ATPCS additions to APCS conventions. */
883 {"wr", 7}, {"v8", 11},
884 /* FP Registers. */
885 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
886 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
887 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
888 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
889 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
890 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
891 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
892 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
893 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
894 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
895 /* ATPCS additions to float register names. */
896 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
897 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
898 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
899 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
900 /* FIXME: At some point we need to add VFP register names. */
901 /* Array terminator. */
902 {NULL, 0}
903 };
904
905 #define BAD_ARGS _("Bad arguments to instruction")
906 #define BAD_PC _("r15 not allowed here")
907 #define BAD_FLAGS _("Instruction should not have flags")
908 #define BAD_COND _("Instruction is not conditional")
909
910 static struct hash_control * arm_ops_hsh = NULL;
911 static struct hash_control * arm_tops_hsh = NULL;
912 static struct hash_control * arm_cond_hsh = NULL;
913 static struct hash_control * arm_shift_hsh = NULL;
914 static struct hash_control * arm_reg_hsh = NULL;
915 static struct hash_control * arm_psr_hsh = NULL;
916
917 /* This table describes all the machine specific pseudo-ops the assembler
918 has to support. The fields are:
919 pseudo-op name without dot
920 function to call to execute this pseudo-op
921 Integer arg to pass to the function. */
922
923 static void s_req PARAMS ((int));
924 static void s_align PARAMS ((int));
925 static void s_bss PARAMS ((int));
926 static void s_even PARAMS ((int));
927 static void s_ltorg PARAMS ((int));
928 static void s_arm PARAMS ((int));
929 static void s_thumb PARAMS ((int));
930 static void s_code PARAMS ((int));
931 static void s_force_thumb PARAMS ((int));
932 static void s_thumb_func PARAMS ((int));
933 static void s_thumb_set PARAMS ((int));
934 static void arm_s_text PARAMS ((int));
935 static void arm_s_data PARAMS ((int));
936 #ifdef OBJ_ELF
937 static void arm_s_section PARAMS ((int));
938 static void s_arm_elf_cons PARAMS ((int));
939 #endif
940
941 static int my_get_expression PARAMS ((expressionS *, char **));
942
943 CONST pseudo_typeS md_pseudo_table[] =
944 {
945 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
946 { "bss", s_bss, 0 },
947 { "align", s_align, 0 },
948 { "arm", s_arm, 0 },
949 { "thumb", s_thumb, 0 },
950 { "code", s_code, 0 },
951 { "force_thumb", s_force_thumb, 0 },
952 { "thumb_func", s_thumb_func, 0 },
953 { "thumb_set", s_thumb_set, 0 },
954 { "even", s_even, 0 },
955 { "ltorg", s_ltorg, 0 },
956 { "pool", s_ltorg, 0 },
957 /* Allow for the effect of section changes. */
958 { "text", arm_s_text, 0 },
959 { "data", arm_s_data, 0 },
960 #ifdef OBJ_ELF
961 { "section", arm_s_section, 0 },
962 { "section.s", arm_s_section, 0 },
963 { "sect", arm_s_section, 0 },
964 { "sect.s", arm_s_section, 0 },
965 { "word", s_arm_elf_cons, 4 },
966 { "long", s_arm_elf_cons, 4 },
967 #else
968 { "word", cons, 4},
969 #endif
970 { "extend", float_cons, 'x' },
971 { "ldouble", float_cons, 'x' },
972 { "packed", float_cons, 'p' },
973 { 0, 0, 0 }
974 };
975
976 /* Stuff needed to resolve the label ambiguity
977 As:
978 ...
979 label: <insn>
980 may differ from:
981 ...
982 label:
983 <insn>
984 */
985
986 symbolS * last_label_seen;
987 static int label_is_thumb_function_name = false;
988
989 /* Literal stuff */
990
991 #define MAX_LITERAL_POOL_SIZE 1024
992
993 typedef struct literalS
994 {
995 struct expressionS exp;
996 struct arm_it * inst;
997 } literalT;
998
999 literalT literals[MAX_LITERAL_POOL_SIZE];
1000 int next_literal_pool_place = 0; /* Next free entry in the pool */
1001 int lit_pool_num = 1; /* Next literal pool number */
1002 symbolS * current_poolP = NULL;
1003
1004 static int
1005 add_to_lit_pool ()
1006 {
1007 int lit_count = 0;
1008
1009 if (current_poolP == NULL)
1010 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1011 (valueT) 0, &zero_address_frag);
1012
1013 /* Check if this literal value is already in the pool: */
1014 while (lit_count < next_literal_pool_place)
1015 {
1016 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1017 && inst.reloc.exp.X_op == O_constant
1018 && literals[lit_count].exp.X_add_number
1019 == inst.reloc.exp.X_add_number
1020 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1021 break;
1022 lit_count++;
1023 }
1024
1025 if (lit_count == next_literal_pool_place) /* new entry */
1026 {
1027 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1028 {
1029 inst.error = _("Literal Pool Overflow");
1030 return FAIL;
1031 }
1032
1033 literals[next_literal_pool_place].exp = inst.reloc.exp;
1034 lit_count = next_literal_pool_place++;
1035 }
1036
1037 inst.reloc.exp.X_op = O_symbol;
1038 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1039 inst.reloc.exp.X_add_symbol = current_poolP;
1040
1041 return SUCCESS;
1042 }
1043
1044 /* Can't use symbol_new here, so have to create a symbol and then at
1045 a later date assign it a value. Thats what these functions do. */
1046 static void
1047 symbol_locate (symbolP, name, segment, valu, frag)
1048 symbolS * symbolP;
1049 CONST char * name; /* It is copied, the caller can modify */
1050 segT segment; /* Segment identifier (SEG_<something>) */
1051 valueT valu; /* Symbol value */
1052 fragS * frag; /* Associated fragment */
1053 {
1054 unsigned int name_length;
1055 char * preserved_copy_of_name;
1056
1057 name_length = strlen (name) + 1; /* +1 for \0 */
1058 obstack_grow (&notes, name, name_length);
1059 preserved_copy_of_name = obstack_finish (&notes);
1060 #ifdef STRIP_UNDERSCORE
1061 if (preserved_copy_of_name[0] == '_')
1062 preserved_copy_of_name++;
1063 #endif
1064
1065 #ifdef tc_canonicalize_symbol_name
1066 preserved_copy_of_name =
1067 tc_canonicalize_symbol_name (preserved_copy_of_name);
1068 #endif
1069
1070 S_SET_NAME (symbolP, preserved_copy_of_name);
1071
1072 S_SET_SEGMENT (symbolP, segment);
1073 S_SET_VALUE (symbolP, valu);
1074 symbol_clear_list_pointers(symbolP);
1075
1076 symbol_set_frag (symbolP, frag);
1077
1078 /* Link to end of symbol chain. */
1079 {
1080 extern int symbol_table_frozen;
1081 if (symbol_table_frozen)
1082 abort ();
1083 }
1084
1085 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1086
1087 obj_symbol_new_hook (symbolP);
1088
1089 #ifdef tc_symbol_new_hook
1090 tc_symbol_new_hook (symbolP);
1091 #endif
1092
1093 #ifdef DEBUG_SYMS
1094 verify_symbol_chain (symbol_rootP, symbol_lastP);
1095 #endif /* DEBUG_SYMS */
1096 }
1097
1098 /* Check that an immediate is valid, and if so,
1099 convert it to the right format. */
1100 static unsigned int
1101 validate_immediate (val)
1102 unsigned int val;
1103 {
1104 unsigned int a;
1105 unsigned int i;
1106
1107 #define rotate_left(v, n) (v << n | v >> (32 - n))
1108
1109 for (i = 0; i < 32; i += 2)
1110 if ((a = rotate_left (val, i)) <= 0xff)
1111 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1112
1113 return FAIL;
1114 }
1115
1116 /* Check to see if an immediate can be computed as two seperate immediate
1117 values, added together. We already know that this value cannot be
1118 computed by just one ARM instruction. */
1119 static unsigned int
1120 validate_immediate_twopart (val, highpart)
1121 unsigned int val;
1122 unsigned int * highpart;
1123 {
1124 unsigned int a;
1125 unsigned int i;
1126
1127 for (i = 0; i < 32; i += 2)
1128 if (((a = rotate_left (val, i)) & 0xff) != 0)
1129 {
1130 if (a & 0xff00)
1131 {
1132 if (a & ~ 0xffff)
1133 continue;
1134 * highpart = (a >> 8) | ((i + 24) << 7);
1135 }
1136 else if (a & 0xff0000)
1137 {
1138 if (a & 0xff000000)
1139 continue;
1140
1141 * highpart = (a >> 16) | ((i + 16) << 7);
1142 }
1143 else
1144 {
1145 assert (a & 0xff000000);
1146
1147 * highpart = (a >> 24) | ((i + 8) << 7);
1148 }
1149
1150 return (a & 0xff) | (i << 7);
1151 }
1152
1153 return FAIL;
1154 }
1155
1156 static int
1157 validate_offset_imm (val, hwse)
1158 unsigned int val;
1159 int hwse;
1160 {
1161 if ((hwse && val > 255) || val > 4095)
1162 return FAIL;
1163 return val;
1164 }
1165
1166
1167 static void
1168 s_req (a)
1169 int a ATTRIBUTE_UNUSED;
1170 {
1171 as_bad (_("Invalid syntax for .req directive."));
1172 }
1173
1174 static void
1175 s_bss (ignore)
1176 int ignore ATTRIBUTE_UNUSED;
1177 {
1178 /* We don't support putting frags in the BSS segment, we fake it by
1179 marking in_bss, then looking at s_skip for clues?.. */
1180 subseg_set (bss_section, 0);
1181 demand_empty_rest_of_line ();
1182 }
1183
1184 static void
1185 s_even (ignore)
1186 int ignore ATTRIBUTE_UNUSED;
1187 {
1188 if (!need_pass_2) /* Never make frag if expect extra pass. */
1189 frag_align (1, 0, 0);
1190
1191 record_alignment (now_seg, 1);
1192
1193 demand_empty_rest_of_line ();
1194 }
1195
1196 static void
1197 s_ltorg (ignored)
1198 int ignored ATTRIBUTE_UNUSED;
1199 {
1200 int lit_count = 0;
1201 char sym_name[20];
1202
1203 if (current_poolP == NULL)
1204 return;
1205
1206 /* Align pool as you have word accesses */
1207 /* Only make a frag if we have to ... */
1208 if (!need_pass_2)
1209 frag_align (2, 0, 0);
1210
1211 record_alignment (now_seg, 2);
1212
1213 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1214
1215 symbol_locate (current_poolP, sym_name, now_seg,
1216 (valueT) frag_now_fix (), frag_now);
1217 symbol_table_insert (current_poolP);
1218
1219 ARM_SET_THUMB (current_poolP, thumb_mode);
1220
1221 #if defined OBJ_COFF || defined OBJ_ELF
1222 ARM_SET_INTERWORK (current_poolP, support_interwork);
1223 #endif
1224
1225 while (lit_count < next_literal_pool_place)
1226 /* First output the expression in the instruction to the pool. */
1227 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1228
1229 next_literal_pool_place = 0;
1230 current_poolP = NULL;
1231 }
1232
1233 static void
1234 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1235 int unused ATTRIBUTE_UNUSED;
1236 {
1237 register int temp;
1238 register long temp_fill;
1239 long max_alignment = 15;
1240
1241 temp = get_absolute_expression ();
1242 if (temp > max_alignment)
1243 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1244 else if (temp < 0)
1245 {
1246 as_bad (_("Alignment negative. 0 assumed."));
1247 temp = 0;
1248 }
1249
1250 if (*input_line_pointer == ',')
1251 {
1252 input_line_pointer++;
1253 temp_fill = get_absolute_expression ();
1254 }
1255 else
1256 temp_fill = 0;
1257
1258 if (!temp)
1259 temp = 2;
1260
1261 /* Only make a frag if we HAVE to. . . */
1262 if (temp && !need_pass_2)
1263 frag_align (temp, (int) temp_fill, 0);
1264 demand_empty_rest_of_line ();
1265
1266 record_alignment (now_seg, temp);
1267 }
1268
1269 static void
1270 s_force_thumb (ignore)
1271 int ignore ATTRIBUTE_UNUSED;
1272 {
1273 /* If we are not already in thumb mode go into it, EVEN if
1274 the target processor does not support thumb instructions.
1275 This is used by gcc/config/arm/lib1funcs.asm for example
1276 to compile interworking support functions even if the
1277 target processor should not support interworking. */
1278
1279 if (! thumb_mode)
1280 {
1281 thumb_mode = 2;
1282
1283 record_alignment (now_seg, 1);
1284 }
1285
1286 demand_empty_rest_of_line ();
1287 }
1288
1289 static void
1290 s_thumb_func (ignore)
1291 int ignore ATTRIBUTE_UNUSED;
1292 {
1293 if (! thumb_mode)
1294 opcode_select (16);
1295
1296 /* The following label is the name/address of the start of a Thumb function.
1297 We need to know this for the interworking support. */
1298 label_is_thumb_function_name = true;
1299
1300 demand_empty_rest_of_line ();
1301 }
1302
1303 /* Perform a .set directive, but also mark the alias as
1304 being a thumb function. */
1305
1306 static void
1307 s_thumb_set (equiv)
1308 int equiv;
1309 {
1310 /* XXX the following is a duplicate of the code for s_set() in read.c
1311 We cannot just call that code as we need to get at the symbol that
1312 is created. */
1313 register char * name;
1314 register char delim;
1315 register char * end_name;
1316 register symbolS * symbolP;
1317
1318 /*
1319 * Especial apologies for the random logic:
1320 * this just grew, and could be parsed much more simply!
1321 * Dean in haste.
1322 */
1323 name = input_line_pointer;
1324 delim = get_symbol_end ();
1325 end_name = input_line_pointer;
1326 *end_name = delim;
1327
1328 SKIP_WHITESPACE ();
1329
1330 if (*input_line_pointer != ',')
1331 {
1332 *end_name = 0;
1333 as_bad (_("Expected comma after name \"%s\""), name);
1334 *end_name = delim;
1335 ignore_rest_of_line ();
1336 return;
1337 }
1338
1339 input_line_pointer++;
1340 *end_name = 0;
1341
1342 if (name[0] == '.' && name[1] == '\0')
1343 {
1344 /* XXX - this should not happen to .thumb_set */
1345 abort ();
1346 }
1347
1348 if ((symbolP = symbol_find (name)) == NULL
1349 && (symbolP = md_undefined_symbol (name)) == NULL)
1350 {
1351 #ifndef NO_LISTING
1352 /* When doing symbol listings, play games with dummy fragments living
1353 outside the normal fragment chain to record the file and line info
1354 for this symbol. */
1355 if (listing & LISTING_SYMBOLS)
1356 {
1357 extern struct list_info_struct * listing_tail;
1358 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1359 memset (dummy_frag, 0, sizeof(fragS));
1360 dummy_frag->fr_type = rs_fill;
1361 dummy_frag->line = listing_tail;
1362 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1363 dummy_frag->fr_symbol = symbolP;
1364 }
1365 else
1366 #endif
1367 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1368
1369 #ifdef OBJ_COFF
1370 /* "set" symbols are local unless otherwise specified. */
1371 SF_SET_LOCAL (symbolP);
1372 #endif /* OBJ_COFF */
1373 } /* make a new symbol */
1374
1375 symbol_table_insert (symbolP);
1376
1377 * end_name = delim;
1378
1379 if (equiv
1380 && S_IS_DEFINED (symbolP)
1381 && S_GET_SEGMENT (symbolP) != reg_section)
1382 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1383
1384 pseudo_set (symbolP);
1385
1386 demand_empty_rest_of_line ();
1387
1388 /* XXX Now we come to the Thumb specific bit of code. */
1389
1390 THUMB_SET_FUNC (symbolP, 1);
1391 ARM_SET_THUMB (symbolP, 1);
1392 #if defined OBJ_ELF || defined OBJ_COFF
1393 ARM_SET_INTERWORK (symbolP, support_interwork);
1394 #endif
1395 }
1396
1397 /* If we change section we must dump the literal pool first. */
1398 static void
1399 arm_s_text (ignore)
1400 int ignore;
1401 {
1402 if (now_seg != text_section)
1403 s_ltorg (0);
1404
1405 #ifdef OBJ_ELF
1406 obj_elf_text (ignore);
1407 #else
1408 s_text (ignore);
1409 #endif
1410 }
1411
1412 static void
1413 arm_s_data (ignore)
1414 int ignore;
1415 {
1416 if (flag_readonly_data_in_text)
1417 {
1418 if (now_seg != text_section)
1419 s_ltorg (0);
1420 }
1421 else if (now_seg != data_section)
1422 s_ltorg (0);
1423
1424 #ifdef OBJ_ELF
1425 obj_elf_data (ignore);
1426 #else
1427 s_data (ignore);
1428 #endif
1429 }
1430
1431 #ifdef OBJ_ELF
1432 static void
1433 arm_s_section (ignore)
1434 int ignore;
1435 {
1436 s_ltorg (0);
1437
1438 obj_elf_section (ignore);
1439 }
1440 #endif
1441
1442 static void
1443 opcode_select (width)
1444 int width;
1445 {
1446 switch (width)
1447 {
1448 case 16:
1449 if (! thumb_mode)
1450 {
1451 if (! (cpu_variant & ARM_THUMB))
1452 as_bad (_("selected processor does not support THUMB opcodes"));
1453 thumb_mode = 1;
1454 /* No need to force the alignment, since we will have been
1455 coming from ARM mode, which is word-aligned. */
1456 record_alignment (now_seg, 1);
1457 }
1458 break;
1459
1460 case 32:
1461 if (thumb_mode)
1462 {
1463 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1464 as_bad (_("selected processor does not support ARM opcodes"));
1465 thumb_mode = 0;
1466 if (!need_pass_2)
1467 frag_align (2, 0, 0);
1468 record_alignment (now_seg, 1);
1469 }
1470 break;
1471
1472 default:
1473 as_bad (_("invalid instruction size selected (%d)"), width);
1474 }
1475 }
1476
1477 static void
1478 s_arm (ignore)
1479 int ignore ATTRIBUTE_UNUSED;
1480 {
1481 opcode_select (32);
1482 demand_empty_rest_of_line ();
1483 }
1484
1485 static void
1486 s_thumb (ignore)
1487 int ignore ATTRIBUTE_UNUSED;
1488 {
1489 opcode_select (16);
1490 demand_empty_rest_of_line ();
1491 }
1492
1493 static void
1494 s_code (unused)
1495 int unused ATTRIBUTE_UNUSED;
1496 {
1497 register int temp;
1498
1499 temp = get_absolute_expression ();
1500 switch (temp)
1501 {
1502 case 16:
1503 case 32:
1504 opcode_select (temp);
1505 break;
1506
1507 default:
1508 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1509 }
1510 }
1511
1512 static void
1513 end_of_line (str)
1514 char * str;
1515 {
1516 skip_whitespace (str);
1517
1518 if (* str != '\0')
1519 inst.error = _("Garbage following instruction");
1520 }
1521
1522 static int
1523 skip_past_comma (str)
1524 char ** str;
1525 {
1526 char *p = *str, c;
1527 int comma = 0;
1528
1529 while ((c = *p) == ' ' || c == ',')
1530 {
1531 p++;
1532 if (c == ',' && comma++)
1533 return FAIL;
1534 }
1535
1536 if (c == '\0')
1537 return FAIL;
1538
1539 *str = p;
1540 return comma ? SUCCESS : FAIL;
1541 }
1542
1543 /* A standard register must be given at this point.
1544 Shift is the place to put it in inst.instruction.
1545 Restores input start point on err.
1546 Returns the reg#, or FAIL. */
1547 static int
1548 reg_required_here (str, shift)
1549 char ** str;
1550 int shift;
1551 {
1552 static char buff [128]; /* XXX */
1553 int reg;
1554 char * start = *str;
1555
1556 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1557 {
1558 if (shift >= 0)
1559 inst.instruction |= reg << shift;
1560 return reg;
1561 }
1562
1563 /* Restore the start point, we may have got a reg of the wrong class. */
1564 *str = start;
1565
1566 /* In the few cases where we might be able to accept something else
1567 this error can be overridden. */
1568 sprintf (buff, _("Register expected, not '%.100s'"), start);
1569 inst.error = buff;
1570
1571 return FAIL;
1572 }
1573
1574 static CONST struct asm_psr *
1575 arm_psr_parse (ccp)
1576 register char ** ccp;
1577 {
1578 char * start = * ccp;
1579 char c;
1580 char * p;
1581 CONST struct asm_psr * psr;
1582
1583 p = start;
1584
1585 /* Skip to the end of the next word in the input stream. */
1586 do
1587 {
1588 c = *p++;
1589 }
1590 while (isalpha (c) || c == '_');
1591
1592 /* Terminate the word. */
1593 *--p = 0;
1594
1595 /* Now locate the word in the psr hash table. */
1596 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1597
1598 /* Restore the input stream. */
1599 *p = c;
1600
1601 /* If we found a valid match, advance the
1602 stream pointer past the end of the word. */
1603 *ccp = p;
1604
1605 return psr;
1606 }
1607
1608 /* Parse the input looking for a PSR flag. */
1609 static int
1610 psr_required_here (str)
1611 char ** str;
1612 {
1613 char * start = *str;
1614 CONST struct asm_psr * psr;
1615
1616 psr = arm_psr_parse (str);
1617
1618 if (psr)
1619 {
1620 /* If this is the SPSR that is being modified, set the R bit. */
1621 if (! psr->cpsr)
1622 inst.instruction |= SPSR_BIT;
1623
1624 /* Set the psr flags in the MSR instruction. */
1625 inst.instruction |= psr->field << PSR_SHIFT;
1626
1627 return SUCCESS;
1628 }
1629
1630 /* In the few cases where we might be able to accept
1631 something else this error can be overridden. */
1632 inst.error = _("flag for {c}psr instruction expected");
1633
1634 /* Restore the start point. */
1635 *str = start;
1636 return FAIL;
1637 }
1638
1639 static int
1640 co_proc_number (str)
1641 char ** str;
1642 {
1643 int processor, pchar;
1644
1645 skip_whitespace (* str);
1646
1647 /* The data sheet seems to imply that just a number on its own is valid
1648 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1649 accept either. */
1650 if (**str == 'p' || **str == 'P')
1651 (*str)++;
1652
1653 pchar = *(*str)++;
1654 if (pchar >= '0' && pchar <= '9')
1655 {
1656 processor = pchar - '0';
1657 if (**str >= '0' && **str <= '9')
1658 {
1659 processor = processor * 10 + *(*str)++ - '0';
1660 if (processor > 15)
1661 {
1662 inst.error = _("Illegal co-processor number");
1663 return FAIL;
1664 }
1665 }
1666 }
1667 else
1668 {
1669 inst.error = _("Bad or missing co-processor number");
1670 return FAIL;
1671 }
1672
1673 inst.instruction |= processor << 8;
1674 return SUCCESS;
1675 }
1676
1677 static int
1678 cp_opc_expr (str, where, length)
1679 char ** str;
1680 int where;
1681 int length;
1682 {
1683 expressionS expr;
1684
1685 skip_whitespace (* str);
1686
1687 memset (&expr, '\0', sizeof (expr));
1688
1689 if (my_get_expression (&expr, str))
1690 return FAIL;
1691 if (expr.X_op != O_constant)
1692 {
1693 inst.error = _("bad or missing expression");
1694 return FAIL;
1695 }
1696
1697 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1698 {
1699 inst.error = _("immediate co-processor expression too large");
1700 return FAIL;
1701 }
1702
1703 inst.instruction |= expr.X_add_number << where;
1704 return SUCCESS;
1705 }
1706
1707 static int
1708 cp_reg_required_here (str, where)
1709 char ** str;
1710 int where;
1711 {
1712 int reg;
1713 char * start = *str;
1714
1715 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1716 {
1717 reg &= 15;
1718 inst.instruction |= reg << where;
1719 return reg;
1720 }
1721
1722 /* In the few cases where we might be able to accept something else
1723 this error can be overridden. */
1724 inst.error = _("Co-processor register expected");
1725
1726 /* Restore the start point. */
1727 *str = start;
1728 return FAIL;
1729 }
1730
1731 static int
1732 fp_reg_required_here (str, where)
1733 char ** str;
1734 int where;
1735 {
1736 int reg;
1737 char * start = *str;
1738
1739 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1740 {
1741 reg &= 7;
1742 inst.instruction |= reg << where;
1743 return reg;
1744 }
1745
1746 /* In the few cases where we might be able to accept something else
1747 this error can be overridden. */
1748 inst.error = _("Floating point register expected");
1749
1750 /* Restore the start point. */
1751 *str = start;
1752 return FAIL;
1753 }
1754
1755 static int
1756 cp_address_offset (str)
1757 char ** str;
1758 {
1759 int offset;
1760
1761 skip_whitespace (* str);
1762
1763 if (! is_immediate_prefix (**str))
1764 {
1765 inst.error = _("immediate expression expected");
1766 return FAIL;
1767 }
1768
1769 (*str)++;
1770
1771 if (my_get_expression (& inst.reloc.exp, str))
1772 return FAIL;
1773
1774 if (inst.reloc.exp.X_op == O_constant)
1775 {
1776 offset = inst.reloc.exp.X_add_number;
1777
1778 if (offset & 3)
1779 {
1780 inst.error = _("co-processor address must be word aligned");
1781 return FAIL;
1782 }
1783
1784 if (offset > 1023 || offset < -1023)
1785 {
1786 inst.error = _("offset too large");
1787 return FAIL;
1788 }
1789
1790 if (offset >= 0)
1791 inst.instruction |= INDEX_UP;
1792 else
1793 offset = -offset;
1794
1795 inst.instruction |= offset >> 2;
1796 }
1797 else
1798 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1799
1800 return SUCCESS;
1801 }
1802
1803 static int
1804 cp_address_required_here (str)
1805 char ** str;
1806 {
1807 char * p = * str;
1808 int pre_inc = 0;
1809 int write_back = 0;
1810
1811 if (*p == '[')
1812 {
1813 int reg;
1814
1815 p++;
1816 skip_whitespace (p);
1817
1818 if ((reg = reg_required_here (& p, 16)) == FAIL)
1819 return FAIL;
1820
1821 skip_whitespace (p);
1822
1823 if (*p == ']')
1824 {
1825 p++;
1826
1827 if (skip_past_comma (& p) == SUCCESS)
1828 {
1829 /* [Rn], #expr */
1830 write_back = WRITE_BACK;
1831
1832 if (reg == REG_PC)
1833 {
1834 inst.error = _("pc may not be used in post-increment");
1835 return FAIL;
1836 }
1837
1838 if (cp_address_offset (& p) == FAIL)
1839 return FAIL;
1840 }
1841 else
1842 pre_inc = PRE_INDEX | INDEX_UP;
1843 }
1844 else
1845 {
1846 /* '['Rn, #expr']'[!] */
1847
1848 if (skip_past_comma (& p) == FAIL)
1849 {
1850 inst.error = _("pre-indexed expression expected");
1851 return FAIL;
1852 }
1853
1854 pre_inc = PRE_INDEX;
1855
1856 if (cp_address_offset (& p) == FAIL)
1857 return FAIL;
1858
1859 skip_whitespace (p);
1860
1861 if (*p++ != ']')
1862 {
1863 inst.error = _("missing ]");
1864 return FAIL;
1865 }
1866
1867 skip_whitespace (p);
1868
1869 if (*p == '!')
1870 {
1871 if (reg == REG_PC)
1872 {
1873 inst.error = _("pc may not be used with write-back");
1874 return FAIL;
1875 }
1876
1877 p++;
1878 write_back = WRITE_BACK;
1879 }
1880 }
1881 }
1882 else
1883 {
1884 if (my_get_expression (&inst.reloc.exp, &p))
1885 return FAIL;
1886
1887 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1888 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1889 inst.reloc.pc_rel = 1;
1890 inst.instruction |= (REG_PC << 16);
1891 pre_inc = PRE_INDEX;
1892 }
1893
1894 inst.instruction |= write_back | pre_inc;
1895 *str = p;
1896 return SUCCESS;
1897 }
1898
1899 static void
1900 do_nop (str, flags)
1901 char * str;
1902 unsigned long flags;
1903 {
1904 /* Do nothing really. */
1905 inst.instruction |= flags; /* This is pointless. */
1906 end_of_line (str);
1907 return;
1908 }
1909
1910 static void
1911 do_mrs (str, flags)
1912 char *str;
1913 unsigned long flags;
1914 {
1915 int skip = 0;
1916
1917 /* Only one syntax. */
1918 skip_whitespace (str);
1919
1920 if (reg_required_here (&str, 12) == FAIL)
1921 {
1922 inst.error = BAD_ARGS;
1923 return;
1924 }
1925
1926 if (skip_past_comma (&str) == FAIL)
1927 {
1928 inst.error = _("comma expected after register name");
1929 return;
1930 }
1931
1932 skip_whitespace (str);
1933
1934 if ( strcmp (str, "CPSR") == 0
1935 || strcmp (str, "SPSR") == 0
1936 /* Lower case versions for backwards compatability. */
1937 || strcmp (str, "cpsr") == 0
1938 || strcmp (str, "spsr") == 0)
1939 skip = 4;
1940 /* This is for backwards compatability with older toolchains. */
1941 else if (strcmp (str, "cpsr_all") == 0
1942 || strcmp (str, "spsr_all") == 0)
1943 skip = 7;
1944 else
1945 {
1946 inst.error = _("{C|S}PSR expected");
1947 return;
1948 }
1949
1950 if (* str == 's' || * str == 'S')
1951 inst.instruction |= SPSR_BIT;
1952 str += skip;
1953
1954 inst.instruction |= flags;
1955 end_of_line (str);
1956 }
1957
1958 /* Two possible forms:
1959 "{C|S}PSR_<field>, Rm",
1960 "{C|S}PSR_f, #expression". */
1961 static void
1962 do_msr (str, flags)
1963 char * str;
1964 unsigned long flags;
1965 {
1966 skip_whitespace (str);
1967
1968 if (psr_required_here (& str) == FAIL)
1969 return;
1970
1971 if (skip_past_comma (& str) == FAIL)
1972 {
1973 inst.error = _("comma missing after psr flags");
1974 return;
1975 }
1976
1977 skip_whitespace (str);
1978
1979 if (reg_required_here (& str, 0) != FAIL)
1980 {
1981 inst.error = NULL;
1982 inst.instruction |= flags;
1983 end_of_line (str);
1984 return;
1985 }
1986
1987 if (! is_immediate_prefix (* str))
1988 {
1989 inst.error = _("only a register or immediate value can follow a psr flag");
1990 return;
1991 }
1992
1993 str ++;
1994 inst.error = NULL;
1995
1996 if (my_get_expression (& inst.reloc.exp, & str))
1997 {
1998 inst.error = _("only a register or immediate value can follow a psr flag");
1999 return;
2000 }
2001
2002 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2003 {
2004 inst.error = _("can only set flag field with immediate value");
2005 return;
2006 }
2007
2008 flags |= INST_IMMEDIATE;
2009
2010 if (inst.reloc.exp.X_add_symbol)
2011 {
2012 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2013 inst.reloc.pc_rel = 0;
2014 }
2015 else
2016 {
2017 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2018
2019 if (value == (unsigned) FAIL)
2020 {
2021 inst.error = _("Invalid constant");
2022 return;
2023 }
2024
2025 inst.instruction |= value;
2026 }
2027
2028 inst.error = NULL;
2029 inst.instruction |= flags;
2030 end_of_line (str);
2031 }
2032
2033 /* Long Multiply Parser
2034 UMULL RdLo, RdHi, Rm, Rs
2035 SMULL RdLo, RdHi, Rm, Rs
2036 UMLAL RdLo, RdHi, Rm, Rs
2037 SMLAL RdLo, RdHi, Rm, Rs
2038 */
2039 static void
2040 do_mull (str, flags)
2041 char * str;
2042 unsigned long flags;
2043 {
2044 int rdlo, rdhi, rm, rs;
2045
2046 /* Only one format "rdlo, rdhi, rm, rs" */
2047 skip_whitespace (str);
2048
2049 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2050 {
2051 inst.error = BAD_ARGS;
2052 return;
2053 }
2054
2055 if (skip_past_comma (&str) == FAIL
2056 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2057 {
2058 inst.error = BAD_ARGS;
2059 return;
2060 }
2061
2062 if (skip_past_comma (&str) == FAIL
2063 || (rm = reg_required_here (&str, 0)) == FAIL)
2064 {
2065 inst.error = BAD_ARGS;
2066 return;
2067 }
2068
2069 /* rdhi, rdlo and rm must all be different */
2070 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2071 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2072
2073 if (skip_past_comma (&str) == FAIL
2074 || (rs = reg_required_here (&str, 8)) == FAIL)
2075 {
2076 inst.error = BAD_ARGS;
2077 return;
2078 }
2079
2080 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2081 {
2082 inst.error = BAD_PC;
2083 return;
2084 }
2085
2086 inst.instruction |= flags;
2087 end_of_line (str);
2088 return;
2089 }
2090
2091 static void
2092 do_mul (str, flags)
2093 char * str;
2094 unsigned long flags;
2095 {
2096 int rd, rm;
2097
2098 /* Only one format "rd, rm, rs" */
2099 skip_whitespace (str);
2100
2101 if ((rd = reg_required_here (&str, 16)) == FAIL)
2102 {
2103 inst.error = BAD_ARGS;
2104 return;
2105 }
2106
2107 if (rd == REG_PC)
2108 {
2109 inst.error = BAD_PC;
2110 return;
2111 }
2112
2113 if (skip_past_comma (&str) == FAIL
2114 || (rm = reg_required_here (&str, 0)) == FAIL)
2115 {
2116 inst.error = BAD_ARGS;
2117 return;
2118 }
2119
2120 if (rm == REG_PC)
2121 {
2122 inst.error = BAD_PC;
2123 return;
2124 }
2125
2126 if (rm == rd)
2127 as_tsktsk (_("rd and rm should be different in mul"));
2128
2129 if (skip_past_comma (&str) == FAIL
2130 || (rm = reg_required_here (&str, 8)) == FAIL)
2131 {
2132 inst.error = BAD_ARGS;
2133 return;
2134 }
2135
2136 if (rm == REG_PC)
2137 {
2138 inst.error = BAD_PC;
2139 return;
2140 }
2141
2142 inst.instruction |= flags;
2143 end_of_line (str);
2144 return;
2145 }
2146
2147 static void
2148 do_mla (str, flags)
2149 char * str;
2150 unsigned long flags;
2151 {
2152 int rd, rm;
2153
2154 /* Only one format "rd, rm, rs, rn" */
2155 skip_whitespace (str);
2156
2157 if ((rd = reg_required_here (&str, 16)) == FAIL)
2158 {
2159 inst.error = BAD_ARGS;
2160 return;
2161 }
2162
2163 if (rd == REG_PC)
2164 {
2165 inst.error = BAD_PC;
2166 return;
2167 }
2168
2169 if (skip_past_comma (&str) == FAIL
2170 || (rm = reg_required_here (&str, 0)) == FAIL)
2171 {
2172 inst.error = BAD_ARGS;
2173 return;
2174 }
2175
2176 if (rm == REG_PC)
2177 {
2178 inst.error = BAD_PC;
2179 return;
2180 }
2181
2182 if (rm == rd)
2183 as_tsktsk (_("rd and rm should be different in mla"));
2184
2185 if (skip_past_comma (&str) == FAIL
2186 || (rd = reg_required_here (&str, 8)) == FAIL
2187 || skip_past_comma (&str) == FAIL
2188 || (rm = reg_required_here (&str, 12)) == FAIL)
2189 {
2190 inst.error = BAD_ARGS;
2191 return;
2192 }
2193
2194 if (rd == REG_PC || rm == REG_PC)
2195 {
2196 inst.error = BAD_PC;
2197 return;
2198 }
2199
2200 inst.instruction |= flags;
2201 end_of_line (str);
2202 return;
2203 }
2204
2205 /* Returns the index into fp_values of a floating point number, or -1 if
2206 not in the table. */
2207 static int
2208 my_get_float_expression (str)
2209 char ** str;
2210 {
2211 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2212 char * save_in;
2213 expressionS exp;
2214 int i;
2215 int j;
2216
2217 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2218 /* Look for a raw floating point number */
2219 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2220 && is_end_of_line [(unsigned char) *save_in])
2221 {
2222 for (i = 0; i < NUM_FLOAT_VALS; i++)
2223 {
2224 for (j = 0; j < MAX_LITTLENUMS; j++)
2225 {
2226 if (words[j] != fp_values[i][j])
2227 break;
2228 }
2229
2230 if (j == MAX_LITTLENUMS)
2231 {
2232 *str = save_in;
2233 return i;
2234 }
2235 }
2236 }
2237
2238 /* Try and parse a more complex expression, this will probably fail
2239 unless the code uses a floating point prefix (eg "0f") */
2240 save_in = input_line_pointer;
2241 input_line_pointer = *str;
2242 if (expression (&exp) == absolute_section
2243 && exp.X_op == O_big
2244 && exp.X_add_number < 0)
2245 {
2246 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2247 Ditto for 15. */
2248 if (gen_to_words (words, 5, (long)15) == 0)
2249 {
2250 for (i = 0; i < NUM_FLOAT_VALS; i++)
2251 {
2252 for (j = 0; j < MAX_LITTLENUMS; j++)
2253 {
2254 if (words[j] != fp_values[i][j])
2255 break;
2256 }
2257
2258 if (j == MAX_LITTLENUMS)
2259 {
2260 *str = input_line_pointer;
2261 input_line_pointer = save_in;
2262 return i;
2263 }
2264 }
2265 }
2266 }
2267
2268 *str = input_line_pointer;
2269 input_line_pointer = save_in;
2270 return -1;
2271 }
2272
2273 /* Return true if anything in the expression is a bignum */
2274 static int
2275 walk_no_bignums (sp)
2276 symbolS * sp;
2277 {
2278 if (symbol_get_value_expression (sp)->X_op == O_big)
2279 return 1;
2280
2281 if (symbol_get_value_expression (sp)->X_add_symbol)
2282 {
2283 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2284 || (symbol_get_value_expression (sp)->X_op_symbol
2285 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2286 }
2287
2288 return 0;
2289 }
2290
2291 static int
2292 my_get_expression (ep, str)
2293 expressionS * ep;
2294 char ** str;
2295 {
2296 char * save_in;
2297 segT seg;
2298
2299 save_in = input_line_pointer;
2300 input_line_pointer = *str;
2301 seg = expression (ep);
2302
2303 #ifdef OBJ_AOUT
2304 if (seg != absolute_section
2305 && seg != text_section
2306 && seg != data_section
2307 && seg != bss_section
2308 && seg != undefined_section)
2309 {
2310 inst.error = _("bad_segment");
2311 *str = input_line_pointer;
2312 input_line_pointer = save_in;
2313 return 1;
2314 }
2315 #endif
2316
2317 /* Get rid of any bignums now, so that we don't generate an error for which
2318 we can't establish a line number later on. Big numbers are never valid
2319 in instructions, which is where this routine is always called. */
2320 if (ep->X_op == O_big
2321 || (ep->X_add_symbol
2322 && (walk_no_bignums (ep->X_add_symbol)
2323 || (ep->X_op_symbol
2324 && walk_no_bignums (ep->X_op_symbol)))))
2325 {
2326 inst.error = _("Invalid constant");
2327 *str = input_line_pointer;
2328 input_line_pointer = save_in;
2329 return 1;
2330 }
2331
2332 *str = input_line_pointer;
2333 input_line_pointer = save_in;
2334 return 0;
2335 }
2336
2337 /* unrestrict should be one if <shift> <register> is permitted for this
2338 instruction */
2339
2340 static int
2341 decode_shift (str, unrestrict)
2342 char ** str;
2343 int unrestrict;
2344 {
2345 struct asm_shift * shft;
2346 char * p;
2347 char c;
2348
2349 skip_whitespace (* str);
2350
2351 for (p = *str; isalpha (*p); p++)
2352 ;
2353
2354 if (p == *str)
2355 {
2356 inst.error = _("Shift expression expected");
2357 return FAIL;
2358 }
2359
2360 c = *p;
2361 *p = '\0';
2362 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2363 *p = c;
2364 if (shft)
2365 {
2366 if (!strncmp (*str, "rrx", 3)
2367 || !strncmp (*str, "RRX", 3))
2368 {
2369 *str = p;
2370 inst.instruction |= shft->value;
2371 return SUCCESS;
2372 }
2373
2374 skip_whitespace (p);
2375
2376 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2377 {
2378 inst.instruction |= shft->value | SHIFT_BY_REG;
2379 *str = p;
2380 return SUCCESS;
2381 }
2382 else if (is_immediate_prefix (* p))
2383 {
2384 inst.error = NULL;
2385 p++;
2386 if (my_get_expression (&inst.reloc.exp, &p))
2387 return FAIL;
2388
2389 /* Validate some simple #expressions */
2390 if (inst.reloc.exp.X_op == O_constant)
2391 {
2392 unsigned num = inst.reloc.exp.X_add_number;
2393
2394 /* Reject operations greater than 32, or lsl #32 */
2395 if (num > 32 || (num == 32 && shft->value == 0))
2396 {
2397 inst.error = _("Invalid immediate shift");
2398 return FAIL;
2399 }
2400
2401 /* Shifts of zero should be converted to lsl (which is zero)*/
2402 if (num == 0)
2403 {
2404 *str = p;
2405 return SUCCESS;
2406 }
2407
2408 /* Shifts of 32 are encoded as 0, for those shifts that
2409 support it. */
2410 if (num == 32)
2411 num = 0;
2412
2413 inst.instruction |= (num << 7) | shft->value;
2414 *str = p;
2415 return SUCCESS;
2416 }
2417
2418 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2419 inst.reloc.pc_rel = 0;
2420 inst.instruction |= shft->value;
2421 *str = p;
2422 return SUCCESS;
2423 }
2424 else
2425 {
2426 inst.error = unrestrict ? _("shift requires register or #expression")
2427 : _("shift requires #expression");
2428 *str = p;
2429 return FAIL;
2430 }
2431 }
2432
2433 inst.error = _("Shift expression expected");
2434 return FAIL;
2435 }
2436
2437 /* Do those data_ops which can take a negative immediate constant */
2438 /* by altering the instuction. A bit of a hack really */
2439 /* MOV <-> MVN
2440 AND <-> BIC
2441 ADC <-> SBC
2442 by inverting the second operand, and
2443 ADD <-> SUB
2444 CMP <-> CMN
2445 by negating the second operand.
2446 */
2447 static int
2448 negate_data_op (instruction, value)
2449 unsigned long * instruction;
2450 unsigned long value;
2451 {
2452 int op, new_inst;
2453 unsigned long negated, inverted;
2454
2455 negated = validate_immediate (-value);
2456 inverted = validate_immediate (~value);
2457
2458 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2459 switch (op)
2460 {
2461 /* First negates */
2462 case OPCODE_SUB: /* ADD <-> SUB */
2463 new_inst = OPCODE_ADD;
2464 value = negated;
2465 break;
2466
2467 case OPCODE_ADD:
2468 new_inst = OPCODE_SUB;
2469 value = negated;
2470 break;
2471
2472 case OPCODE_CMP: /* CMP <-> CMN */
2473 new_inst = OPCODE_CMN;
2474 value = negated;
2475 break;
2476
2477 case OPCODE_CMN:
2478 new_inst = OPCODE_CMP;
2479 value = negated;
2480 break;
2481
2482 /* Now Inverted ops */
2483 case OPCODE_MOV: /* MOV <-> MVN */
2484 new_inst = OPCODE_MVN;
2485 value = inverted;
2486 break;
2487
2488 case OPCODE_MVN:
2489 new_inst = OPCODE_MOV;
2490 value = inverted;
2491 break;
2492
2493 case OPCODE_AND: /* AND <-> BIC */
2494 new_inst = OPCODE_BIC;
2495 value = inverted;
2496 break;
2497
2498 case OPCODE_BIC:
2499 new_inst = OPCODE_AND;
2500 value = inverted;
2501 break;
2502
2503 case OPCODE_ADC: /* ADC <-> SBC */
2504 new_inst = OPCODE_SBC;
2505 value = inverted;
2506 break;
2507
2508 case OPCODE_SBC:
2509 new_inst = OPCODE_ADC;
2510 value = inverted;
2511 break;
2512
2513 /* We cannot do anything */
2514 default:
2515 return FAIL;
2516 }
2517
2518 if (value == (unsigned) FAIL)
2519 return FAIL;
2520
2521 *instruction &= OPCODE_MASK;
2522 *instruction |= new_inst << DATA_OP_SHIFT;
2523 return value;
2524 }
2525
2526 static int
2527 data_op2 (str)
2528 char ** str;
2529 {
2530 int value;
2531 expressionS expr;
2532
2533 skip_whitespace (* str);
2534
2535 if (reg_required_here (str, 0) != FAIL)
2536 {
2537 if (skip_past_comma (str) == SUCCESS)
2538 /* Shift operation on register. */
2539 return decode_shift (str, NO_SHIFT_RESTRICT);
2540
2541 return SUCCESS;
2542 }
2543 else
2544 {
2545 /* Immediate expression */
2546 if (is_immediate_prefix (**str))
2547 {
2548 (*str)++;
2549 inst.error = NULL;
2550
2551 if (my_get_expression (&inst.reloc.exp, str))
2552 return FAIL;
2553
2554 if (inst.reloc.exp.X_add_symbol)
2555 {
2556 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2557 inst.reloc.pc_rel = 0;
2558 }
2559 else
2560 {
2561 if (skip_past_comma (str) == SUCCESS)
2562 {
2563 /* #x, y -- ie explicit rotation by Y */
2564 if (my_get_expression (&expr, str))
2565 return FAIL;
2566
2567 if (expr.X_op != O_constant)
2568 {
2569 inst.error = _("Constant expression expected");
2570 return FAIL;
2571 }
2572
2573 /* Rotate must be a multiple of 2 */
2574 if (((unsigned) expr.X_add_number) > 30
2575 || (expr.X_add_number & 1) != 0
2576 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2577 {
2578 inst.error = _("Invalid constant");
2579 return FAIL;
2580 }
2581 inst.instruction |= INST_IMMEDIATE;
2582 inst.instruction |= inst.reloc.exp.X_add_number;
2583 inst.instruction |= expr.X_add_number << 7;
2584 return SUCCESS;
2585 }
2586
2587 /* Implicit rotation, select a suitable one */
2588 value = validate_immediate (inst.reloc.exp.X_add_number);
2589
2590 if (value == FAIL)
2591 {
2592 /* Can't be done, perhaps the code reads something like
2593 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2594 if ((value = negate_data_op (&inst.instruction,
2595 inst.reloc.exp.X_add_number))
2596 == FAIL)
2597 {
2598 inst.error = _("Invalid constant");
2599 return FAIL;
2600 }
2601 }
2602
2603 inst.instruction |= value;
2604 }
2605
2606 inst.instruction |= INST_IMMEDIATE;
2607 return SUCCESS;
2608 }
2609
2610 (*str)++;
2611 inst.error = _("Register or shift expression expected");
2612 return FAIL;
2613 }
2614 }
2615
2616 static int
2617 fp_op2 (str)
2618 char ** str;
2619 {
2620 skip_whitespace (* str);
2621
2622 if (fp_reg_required_here (str, 0) != FAIL)
2623 return SUCCESS;
2624 else
2625 {
2626 /* Immediate expression */
2627 if (*((*str)++) == '#')
2628 {
2629 int i;
2630
2631 inst.error = NULL;
2632
2633 skip_whitespace (* str);
2634
2635 /* First try and match exact strings, this is to guarantee that
2636 some formats will work even for cross assembly */
2637
2638 for (i = 0; fp_const[i]; i++)
2639 {
2640 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2641 {
2642 char *start = *str;
2643
2644 *str += strlen (fp_const[i]);
2645 if (is_end_of_line[(unsigned char) **str])
2646 {
2647 inst.instruction |= i + 8;
2648 return SUCCESS;
2649 }
2650 *str = start;
2651 }
2652 }
2653
2654 /* Just because we didn't get a match doesn't mean that the
2655 constant isn't valid, just that it is in a format that we
2656 don't automatically recognize. Try parsing it with
2657 the standard expression routines. */
2658 if ((i = my_get_float_expression (str)) >= 0)
2659 {
2660 inst.instruction |= i + 8;
2661 return SUCCESS;
2662 }
2663
2664 inst.error = _("Invalid floating point immediate expression");
2665 return FAIL;
2666 }
2667 inst.error = _("Floating point register or immediate expression expected");
2668 return FAIL;
2669 }
2670 }
2671
2672 static void
2673 do_arit (str, flags)
2674 char * str;
2675 unsigned long flags;
2676 {
2677 skip_whitespace (str);
2678
2679 if (reg_required_here (&str, 12) == FAIL
2680 || skip_past_comma (&str) == FAIL
2681 || reg_required_here (&str, 16) == FAIL
2682 || skip_past_comma (&str) == FAIL
2683 || data_op2 (&str) == FAIL)
2684 {
2685 if (!inst.error)
2686 inst.error = BAD_ARGS;
2687 return;
2688 }
2689
2690 inst.instruction |= flags;
2691 end_of_line (str);
2692 return;
2693 }
2694
2695 static void
2696 do_adr (str, flags)
2697 char * str;
2698 unsigned long flags;
2699 {
2700 /* This is a pseudo-op of the form "adr rd, label" to be converted
2701 into a relative address of the form "add rd, pc, #label-.-8". */
2702 skip_whitespace (str);
2703
2704 if (reg_required_here (&str, 12) == FAIL
2705 || skip_past_comma (&str) == FAIL
2706 || my_get_expression (&inst.reloc.exp, &str))
2707 {
2708 if (!inst.error)
2709 inst.error = BAD_ARGS;
2710 return;
2711 }
2712
2713 /* Frag hacking will turn this into a sub instruction if the offset turns
2714 out to be negative. */
2715 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2716 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2717 inst.reloc.pc_rel = 1;
2718 inst.instruction |= flags;
2719
2720 end_of_line (str);
2721 }
2722
2723 static void
2724 do_adrl (str, flags)
2725 char * str;
2726 unsigned long flags;
2727 {
2728 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2729 into a relative address of the form:
2730 add rd, pc, #low(label-.-8)"
2731 add rd, rd, #high(label-.-8)" */
2732
2733 skip_whitespace (str);
2734
2735 if (reg_required_here (& str, 12) == FAIL
2736 || skip_past_comma (& str) == FAIL
2737 || my_get_expression (& inst.reloc.exp, & str))
2738 {
2739 if (!inst.error)
2740 inst.error = BAD_ARGS;
2741 return;
2742 }
2743
2744 end_of_line (str);
2745
2746 /* Frag hacking will turn this into a sub instruction if the offset turns
2747 out to be negative. */
2748 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2749 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2750 inst.reloc.pc_rel = 1;
2751 inst.instruction |= flags;
2752 inst.size = INSN_SIZE * 2;
2753
2754 return;
2755 }
2756
2757 static void
2758 do_cmp (str, flags)
2759 char * str;
2760 unsigned long flags;
2761 {
2762 skip_whitespace (str);
2763
2764 if (reg_required_here (&str, 16) == FAIL)
2765 {
2766 if (!inst.error)
2767 inst.error = BAD_ARGS;
2768 return;
2769 }
2770
2771 if (skip_past_comma (&str) == FAIL
2772 || data_op2 (&str) == FAIL)
2773 {
2774 if (!inst.error)
2775 inst.error = BAD_ARGS;
2776 return;
2777 }
2778
2779 inst.instruction |= flags;
2780 if ((flags & 0x0000f000) == 0)
2781 inst.instruction |= CONDS_BIT;
2782
2783 end_of_line (str);
2784 return;
2785 }
2786
2787 static void
2788 do_mov (str, flags)
2789 char * str;
2790 unsigned long flags;
2791 {
2792 skip_whitespace (str);
2793
2794 if (reg_required_here (&str, 12) == FAIL)
2795 {
2796 if (!inst.error)
2797 inst.error = BAD_ARGS;
2798 return;
2799 }
2800
2801 if (skip_past_comma (&str) == FAIL
2802 || data_op2 (&str) == FAIL)
2803 {
2804 if (!inst.error)
2805 inst.error = BAD_ARGS;
2806 return;
2807 }
2808
2809 inst.instruction |= flags;
2810 end_of_line (str);
2811 return;
2812 }
2813
2814 static int
2815 ldst_extend (str, hwse)
2816 char ** str;
2817 int hwse;
2818 {
2819 int add = INDEX_UP;
2820
2821 switch (**str)
2822 {
2823 case '#':
2824 case '$':
2825 (*str)++;
2826 if (my_get_expression (& inst.reloc.exp, str))
2827 return FAIL;
2828
2829 if (inst.reloc.exp.X_op == O_constant)
2830 {
2831 int value = inst.reloc.exp.X_add_number;
2832
2833 if ((hwse && (value < -255 || value > 255))
2834 || (value < -4095 || value > 4095))
2835 {
2836 inst.error = _("address offset too large");
2837 return FAIL;
2838 }
2839
2840 if (value < 0)
2841 {
2842 value = -value;
2843 add = 0;
2844 }
2845
2846 /* Halfword and signextension instructions have the
2847 immediate value split across bits 11..8 and bits 3..0 */
2848 if (hwse)
2849 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2850 else
2851 inst.instruction |= add | value;
2852 }
2853 else
2854 {
2855 if (hwse)
2856 {
2857 inst.instruction |= HWOFFSET_IMM;
2858 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2859 }
2860 else
2861 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2862 inst.reloc.pc_rel = 0;
2863 }
2864 return SUCCESS;
2865
2866 case '-':
2867 add = 0; /* and fall through */
2868 case '+':
2869 (*str)++; /* and fall through */
2870 default:
2871 if (reg_required_here (str, 0) == FAIL)
2872 return FAIL;
2873
2874 if (hwse)
2875 inst.instruction |= add;
2876 else
2877 {
2878 inst.instruction |= add | OFFSET_REG;
2879 if (skip_past_comma (str) == SUCCESS)
2880 return decode_shift (str, SHIFT_RESTRICT);
2881 }
2882
2883 return SUCCESS;
2884 }
2885 }
2886
2887 static void
2888 do_ldst (str, flags)
2889 char * str;
2890 unsigned long flags;
2891 {
2892 int halfword = 0;
2893 int pre_inc = 0;
2894 int conflict_reg;
2895 int value;
2896
2897 /* This is not ideal, but it is the simplest way of dealing with the
2898 ARM7T halfword instructions (since they use a different
2899 encoding, but the same mnemonic): */
2900 halfword = (flags & 0x80000000) != 0;
2901 if (halfword)
2902 {
2903 /* This is actually a load/store of a halfword, or a
2904 signed-extension load */
2905 if ((cpu_variant & ARM_HALFWORD) == 0)
2906 {
2907 inst.error
2908 = _("Processor does not support halfwords or signed bytes");
2909 return;
2910 }
2911
2912 inst.instruction = (inst.instruction & COND_MASK)
2913 | (flags & ~COND_MASK);
2914
2915 flags = 0;
2916 }
2917
2918 skip_whitespace (str);
2919
2920 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2921 {
2922 if (!inst.error)
2923 inst.error = BAD_ARGS;
2924 return;
2925 }
2926
2927 if (skip_past_comma (& str) == FAIL)
2928 {
2929 inst.error = _("Address expected");
2930 return;
2931 }
2932
2933 if (*str == '[')
2934 {
2935 int reg;
2936
2937 str++;
2938
2939 skip_whitespace (str);
2940
2941 if ((reg = reg_required_here (&str, 16)) == FAIL)
2942 return;
2943
2944 /* Conflicts can occur on stores as well as loads. */
2945 conflict_reg = (conflict_reg == reg);
2946
2947 skip_whitespace (str);
2948
2949 if (*str == ']')
2950 {
2951 str ++;
2952
2953 if (skip_past_comma (&str) == SUCCESS)
2954 {
2955 /* [Rn],... (post inc) */
2956 if (ldst_extend (&str, halfword) == FAIL)
2957 return;
2958 if (conflict_reg)
2959 as_warn (_("%s register same as write-back base"),
2960 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2961 }
2962 else
2963 {
2964 /* [Rn] */
2965 if (halfword)
2966 inst.instruction |= HWOFFSET_IMM;
2967
2968 skip_whitespace (str);
2969
2970 if (*str == '!')
2971 {
2972 if (conflict_reg)
2973 as_warn (_("%s register same as write-back base"),
2974 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2975 str++;
2976 inst.instruction |= WRITE_BACK;
2977 }
2978
2979 flags |= INDEX_UP;
2980 if (! (flags & TRANS_BIT))
2981 pre_inc = 1;
2982 }
2983 }
2984 else
2985 {
2986 /* [Rn,...] */
2987 if (skip_past_comma (&str) == FAIL)
2988 {
2989 inst.error = _("pre-indexed expression expected");
2990 return;
2991 }
2992
2993 pre_inc = 1;
2994 if (ldst_extend (&str, halfword) == FAIL)
2995 return;
2996
2997 skip_whitespace (str);
2998
2999 if (*str++ != ']')
3000 {
3001 inst.error = _("missing ]");
3002 return;
3003 }
3004
3005 skip_whitespace (str);
3006
3007 if (*str == '!')
3008 {
3009 if (conflict_reg)
3010 as_warn (_("%s register same as write-back base"),
3011 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
3012 str++;
3013 inst.instruction |= WRITE_BACK;
3014 }
3015 }
3016 }
3017 else if (*str == '=')
3018 {
3019 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
3020 str++;
3021
3022 skip_whitespace (str);
3023
3024 if (my_get_expression (&inst.reloc.exp, &str))
3025 return;
3026
3027 if (inst.reloc.exp.X_op != O_constant
3028 && inst.reloc.exp.X_op != O_symbol)
3029 {
3030 inst.error = _("Constant expression expected");
3031 return;
3032 }
3033
3034 if (inst.reloc.exp.X_op == O_constant
3035 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
3036 {
3037 /* This can be done with a mov instruction */
3038 inst.instruction &= LITERAL_MASK;
3039 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3040 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3041 end_of_line(str);
3042 return;
3043 }
3044 else
3045 {
3046 /* Insert into literal pool */
3047 if (add_to_lit_pool () == FAIL)
3048 {
3049 if (!inst.error)
3050 inst.error = _("literal pool insertion failed");
3051 return;
3052 }
3053
3054 /* Change the instruction exp to point to the pool */
3055 if (halfword)
3056 {
3057 inst.instruction |= HWOFFSET_IMM;
3058 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3059 }
3060 else
3061 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3062 inst.reloc.pc_rel = 1;
3063 inst.instruction |= (REG_PC << 16);
3064 pre_inc = 1;
3065 }
3066 }
3067 else
3068 {
3069 if (my_get_expression (&inst.reloc.exp, &str))
3070 return;
3071
3072 if (halfword)
3073 {
3074 inst.instruction |= HWOFFSET_IMM;
3075 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3076 }
3077 else
3078 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3079 #ifndef TE_WINCE
3080 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3081 #endif
3082 inst.reloc.pc_rel = 1;
3083 inst.instruction |= (REG_PC << 16);
3084 pre_inc = 1;
3085 }
3086
3087 if (pre_inc && (flags & TRANS_BIT))
3088 inst.error = _("Pre-increment instruction with translate");
3089
3090 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3091 end_of_line (str);
3092 return;
3093 }
3094
3095 static long
3096 reg_list (strp)
3097 char ** strp;
3098 {
3099 char * str = *strp;
3100 long range = 0;
3101 int another_range;
3102
3103 /* We come back here if we get ranges concatenated by '+' or '|' */
3104 do
3105 {
3106 another_range = 0;
3107
3108 if (*str == '{')
3109 {
3110 int in_range = 0;
3111 int cur_reg = -1;
3112
3113 str++;
3114 do
3115 {
3116 int reg;
3117
3118 skip_whitespace (str);
3119
3120 if ((reg = reg_required_here (& str, -1)) == FAIL)
3121 return FAIL;
3122
3123 if (in_range)
3124 {
3125 int i;
3126
3127 if (reg <= cur_reg)
3128 {
3129 inst.error = _("Bad range in register list");
3130 return FAIL;
3131 }
3132
3133 for (i = cur_reg + 1; i < reg; i++)
3134 {
3135 if (range & (1 << i))
3136 as_tsktsk
3137 (_("Warning: Duplicated register (r%d) in register list"),
3138 i);
3139 else
3140 range |= 1 << i;
3141 }
3142 in_range = 0;
3143 }
3144
3145 if (range & (1 << reg))
3146 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3147 reg);
3148 else if (reg <= cur_reg)
3149 as_tsktsk (_("Warning: Register range not in ascending order"));
3150
3151 range |= 1 << reg;
3152 cur_reg = reg;
3153 } while (skip_past_comma (&str) != FAIL
3154 || (in_range = 1, *str++ == '-'));
3155 str--;
3156 skip_whitespace (str);
3157
3158 if (*str++ != '}')
3159 {
3160 inst.error = _("Missing `}'");
3161 return FAIL;
3162 }
3163 }
3164 else
3165 {
3166 expressionS expr;
3167
3168 if (my_get_expression (&expr, &str))
3169 return FAIL;
3170
3171 if (expr.X_op == O_constant)
3172 {
3173 if (expr.X_add_number
3174 != (expr.X_add_number & 0x0000ffff))
3175 {
3176 inst.error = _("invalid register mask");
3177 return FAIL;
3178 }
3179
3180 if ((range & expr.X_add_number) != 0)
3181 {
3182 int regno = range & expr.X_add_number;
3183
3184 regno &= -regno;
3185 regno = (1 << regno) - 1;
3186 as_tsktsk
3187 (_("Warning: Duplicated register (r%d) in register list"),
3188 regno);
3189 }
3190
3191 range |= expr.X_add_number;
3192 }
3193 else
3194 {
3195 if (inst.reloc.type != 0)
3196 {
3197 inst.error = _("expression too complex");
3198 return FAIL;
3199 }
3200
3201 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3202 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3203 inst.reloc.pc_rel = 0;
3204 }
3205 }
3206
3207 skip_whitespace (str);
3208
3209 if (*str == '|' || *str == '+')
3210 {
3211 str++;
3212 another_range = 1;
3213 }
3214 } while (another_range);
3215
3216 *strp = str;
3217 return range;
3218 }
3219
3220 static void
3221 do_ldmstm (str, flags)
3222 char * str;
3223 unsigned long flags;
3224 {
3225 int base_reg;
3226 long range;
3227
3228 skip_whitespace (str);
3229
3230 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3231 return;
3232
3233 if (base_reg == REG_PC)
3234 {
3235 inst.error = _("r15 not allowed as base register");
3236 return;
3237 }
3238
3239 skip_whitespace (str);
3240
3241 if (*str == '!')
3242 {
3243 flags |= WRITE_BACK;
3244 str++;
3245 }
3246
3247 if (skip_past_comma (&str) == FAIL
3248 || (range = reg_list (&str)) == FAIL)
3249 {
3250 if (! inst.error)
3251 inst.error = BAD_ARGS;
3252 return;
3253 }
3254
3255 if (*str == '^')
3256 {
3257 str++;
3258 flags |= LDM_TYPE_2_OR_3;
3259 }
3260
3261 inst.instruction |= flags | range;
3262 end_of_line (str);
3263 return;
3264 }
3265
3266 static void
3267 do_swi (str, flags)
3268 char * str;
3269 unsigned long flags;
3270 {
3271 skip_whitespace (str);
3272
3273 /* Allow optional leading '#'. */
3274 if (is_immediate_prefix (*str))
3275 str++;
3276
3277 if (my_get_expression (& inst.reloc.exp, & str))
3278 return;
3279
3280 inst.reloc.type = BFD_RELOC_ARM_SWI;
3281 inst.reloc.pc_rel = 0;
3282 inst.instruction |= flags;
3283
3284 end_of_line (str);
3285
3286 return;
3287 }
3288
3289 static void
3290 do_swap (str, flags)
3291 char * str;
3292 unsigned long flags;
3293 {
3294 int reg;
3295
3296 skip_whitespace (str);
3297
3298 if ((reg = reg_required_here (&str, 12)) == FAIL)
3299 return;
3300
3301 if (reg == REG_PC)
3302 {
3303 inst.error = _("r15 not allowed in swap");
3304 return;
3305 }
3306
3307 if (skip_past_comma (&str) == FAIL
3308 || (reg = reg_required_here (&str, 0)) == FAIL)
3309 {
3310 if (!inst.error)
3311 inst.error = BAD_ARGS;
3312 return;
3313 }
3314
3315 if (reg == REG_PC)
3316 {
3317 inst.error = _("r15 not allowed in swap");
3318 return;
3319 }
3320
3321 if (skip_past_comma (&str) == FAIL
3322 || *str++ != '[')
3323 {
3324 inst.error = BAD_ARGS;
3325 return;
3326 }
3327
3328 skip_whitespace (str);
3329
3330 if ((reg = reg_required_here (&str, 16)) == FAIL)
3331 return;
3332
3333 if (reg == REG_PC)
3334 {
3335 inst.error = BAD_PC;
3336 return;
3337 }
3338
3339 skip_whitespace (str);
3340
3341 if (*str++ != ']')
3342 {
3343 inst.error = _("missing ]");
3344 return;
3345 }
3346
3347 inst.instruction |= flags;
3348 end_of_line (str);
3349 return;
3350 }
3351
3352 static void
3353 do_branch (str, flags)
3354 char * str;
3355 unsigned long flags ATTRIBUTE_UNUSED;
3356 {
3357 if (my_get_expression (&inst.reloc.exp, &str))
3358 return;
3359
3360 #ifdef OBJ_ELF
3361 {
3362 char * save_in;
3363
3364 /* ScottB: February 5, 1998 */
3365 /* Check to see of PLT32 reloc required for the instruction. */
3366
3367 /* arm_parse_reloc() works on input_line_pointer.
3368 We actually want to parse the operands to the branch instruction
3369 passed in 'str'. Save the input pointer and restore it later. */
3370 save_in = input_line_pointer;
3371 input_line_pointer = str;
3372 if (inst.reloc.exp.X_op == O_symbol
3373 && *str == '('
3374 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3375 {
3376 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3377 inst.reloc.pc_rel = 0;
3378 /* Modify str to point to after parsed operands, otherwise
3379 end_of_line() will complain about the (PLT) left in str. */
3380 str = input_line_pointer;
3381 }
3382 else
3383 {
3384 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3385 inst.reloc.pc_rel = 1;
3386 }
3387 input_line_pointer = save_in;
3388 }
3389 #else
3390 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3391 inst.reloc.pc_rel = 1;
3392 #endif /* OBJ_ELF */
3393
3394 end_of_line (str);
3395 return;
3396 }
3397
3398 static void
3399 do_bx (str, flags)
3400 char * str;
3401 unsigned long flags ATTRIBUTE_UNUSED;
3402 {
3403 int reg;
3404
3405 skip_whitespace (str);
3406
3407 if ((reg = reg_required_here (&str, 0)) == FAIL)
3408 {
3409 inst.error = BAD_ARGS;
3410 return;
3411 }
3412
3413 if (reg == REG_PC)
3414 inst.error = BAD_PC;
3415
3416 end_of_line (str);
3417 }
3418
3419 static void
3420 do_cdp (str, flags)
3421 char * str;
3422 unsigned long flags ATTRIBUTE_UNUSED;
3423 {
3424 /* Co-processor data operation.
3425 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3426 skip_whitespace (str);
3427
3428 if (co_proc_number (&str) == FAIL)
3429 {
3430 if (!inst.error)
3431 inst.error = BAD_ARGS;
3432 return;
3433 }
3434
3435 if (skip_past_comma (&str) == FAIL
3436 || cp_opc_expr (&str, 20,4) == FAIL)
3437 {
3438 if (!inst.error)
3439 inst.error = BAD_ARGS;
3440 return;
3441 }
3442
3443 if (skip_past_comma (&str) == FAIL
3444 || cp_reg_required_here (&str, 12) == FAIL)
3445 {
3446 if (!inst.error)
3447 inst.error = BAD_ARGS;
3448 return;
3449 }
3450
3451 if (skip_past_comma (&str) == FAIL
3452 || cp_reg_required_here (&str, 16) == FAIL)
3453 {
3454 if (!inst.error)
3455 inst.error = BAD_ARGS;
3456 return;
3457 }
3458
3459 if (skip_past_comma (&str) == FAIL
3460 || cp_reg_required_here (&str, 0) == FAIL)
3461 {
3462 if (!inst.error)
3463 inst.error = BAD_ARGS;
3464 return;
3465 }
3466
3467 if (skip_past_comma (&str) == SUCCESS)
3468 {
3469 if (cp_opc_expr (&str, 5, 3) == FAIL)
3470 {
3471 if (!inst.error)
3472 inst.error = BAD_ARGS;
3473 return;
3474 }
3475 }
3476
3477 end_of_line (str);
3478 return;
3479 }
3480
3481 static void
3482 do_lstc (str, flags)
3483 char * str;
3484 unsigned long flags;
3485 {
3486 /* Co-processor register load/store.
3487 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3488
3489 skip_whitespace (str);
3490
3491 if (co_proc_number (&str) == FAIL)
3492 {
3493 if (!inst.error)
3494 inst.error = BAD_ARGS;
3495 return;
3496 }
3497
3498 if (skip_past_comma (&str) == FAIL
3499 || cp_reg_required_here (&str, 12) == FAIL)
3500 {
3501 if (!inst.error)
3502 inst.error = BAD_ARGS;
3503 return;
3504 }
3505
3506 if (skip_past_comma (&str) == FAIL
3507 || cp_address_required_here (&str) == FAIL)
3508 {
3509 if (! inst.error)
3510 inst.error = BAD_ARGS;
3511 return;
3512 }
3513
3514 inst.instruction |= flags;
3515 end_of_line (str);
3516 return;
3517 }
3518
3519 static void
3520 do_co_reg (str, flags)
3521 char * str;
3522 unsigned long flags;
3523 {
3524 /* Co-processor register transfer.
3525 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3526
3527 skip_whitespace (str);
3528
3529 if (co_proc_number (&str) == FAIL)
3530 {
3531 if (!inst.error)
3532 inst.error = BAD_ARGS;
3533 return;
3534 }
3535
3536 if (skip_past_comma (&str) == FAIL
3537 || cp_opc_expr (&str, 21, 3) == FAIL)
3538 {
3539 if (!inst.error)
3540 inst.error = BAD_ARGS;
3541 return;
3542 }
3543
3544 if (skip_past_comma (&str) == FAIL
3545 || reg_required_here (&str, 12) == FAIL)
3546 {
3547 if (!inst.error)
3548 inst.error = BAD_ARGS;
3549 return;
3550 }
3551
3552 if (skip_past_comma (&str) == FAIL
3553 || cp_reg_required_here (&str, 16) == FAIL)
3554 {
3555 if (!inst.error)
3556 inst.error = BAD_ARGS;
3557 return;
3558 }
3559
3560 if (skip_past_comma (&str) == FAIL
3561 || cp_reg_required_here (&str, 0) == FAIL)
3562 {
3563 if (!inst.error)
3564 inst.error = BAD_ARGS;
3565 return;
3566 }
3567
3568 if (skip_past_comma (&str) == SUCCESS)
3569 {
3570 if (cp_opc_expr (&str, 5, 3) == FAIL)
3571 {
3572 if (!inst.error)
3573 inst.error = BAD_ARGS;
3574 return;
3575 }
3576 }
3577 if (flags)
3578 {
3579 inst.error = BAD_COND;
3580 }
3581
3582 end_of_line (str);
3583 return;
3584 }
3585
3586 static void
3587 do_fp_ctrl (str, flags)
3588 char * str;
3589 unsigned long flags ATTRIBUTE_UNUSED;
3590 {
3591 /* FP control registers.
3592 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3593
3594 skip_whitespace (str);
3595
3596 if (reg_required_here (&str, 12) == FAIL)
3597 {
3598 if (!inst.error)
3599 inst.error = BAD_ARGS;
3600 return;
3601 }
3602
3603 end_of_line (str);
3604 return;
3605 }
3606
3607 static void
3608 do_fp_ldst (str, flags)
3609 char * str;
3610 unsigned long flags ATTRIBUTE_UNUSED;
3611 {
3612 skip_whitespace (str);
3613
3614 switch (inst.suffix)
3615 {
3616 case SUFF_S:
3617 break;
3618 case SUFF_D:
3619 inst.instruction |= CP_T_X;
3620 break;
3621 case SUFF_E:
3622 inst.instruction |= CP_T_Y;
3623 break;
3624 case SUFF_P:
3625 inst.instruction |= CP_T_X | CP_T_Y;
3626 break;
3627 default:
3628 abort ();
3629 }
3630
3631 if (fp_reg_required_here (&str, 12) == FAIL)
3632 {
3633 if (!inst.error)
3634 inst.error = BAD_ARGS;
3635 return;
3636 }
3637
3638 if (skip_past_comma (&str) == FAIL
3639 || cp_address_required_here (&str) == FAIL)
3640 {
3641 if (!inst.error)
3642 inst.error = BAD_ARGS;
3643 return;
3644 }
3645
3646 end_of_line (str);
3647 }
3648
3649 static void
3650 do_fp_ldmstm (str, flags)
3651 char * str;
3652 unsigned long flags;
3653 {
3654 int num_regs;
3655
3656 skip_whitespace (str);
3657
3658 if (fp_reg_required_here (&str, 12) == FAIL)
3659 {
3660 if (! inst.error)
3661 inst.error = BAD_ARGS;
3662 return;
3663 }
3664
3665 /* Get Number of registers to transfer */
3666 if (skip_past_comma (&str) == FAIL
3667 || my_get_expression (&inst.reloc.exp, &str))
3668 {
3669 if (! inst.error)
3670 inst.error = _("constant expression expected");
3671 return;
3672 }
3673
3674 if (inst.reloc.exp.X_op != O_constant)
3675 {
3676 inst.error = _("Constant value required for number of registers");
3677 return;
3678 }
3679
3680 num_regs = inst.reloc.exp.X_add_number;
3681
3682 if (num_regs < 1 || num_regs > 4)
3683 {
3684 inst.error = _("number of registers must be in the range [1:4]");
3685 return;
3686 }
3687
3688 switch (num_regs)
3689 {
3690 case 1:
3691 inst.instruction |= CP_T_X;
3692 break;
3693 case 2:
3694 inst.instruction |= CP_T_Y;
3695 break;
3696 case 3:
3697 inst.instruction |= CP_T_Y | CP_T_X;
3698 break;
3699 case 4:
3700 break;
3701 default:
3702 abort ();
3703 }
3704
3705 if (flags)
3706 {
3707 int reg;
3708 int write_back;
3709 int offset;
3710
3711 /* The instruction specified "ea" or "fd", so we can only accept
3712 [Rn]{!}. The instruction does not really support stacking or
3713 unstacking, so we have to emulate these by setting appropriate
3714 bits and offsets. */
3715 if (skip_past_comma (&str) == FAIL
3716 || *str != '[')
3717 {
3718 if (! inst.error)
3719 inst.error = BAD_ARGS;
3720 return;
3721 }
3722
3723 str++;
3724 skip_whitespace (str);
3725
3726 if ((reg = reg_required_here (&str, 16)) == FAIL)
3727 return;
3728
3729 skip_whitespace (str);
3730
3731 if (*str != ']')
3732 {
3733 inst.error = BAD_ARGS;
3734 return;
3735 }
3736
3737 str++;
3738 if (*str == '!')
3739 {
3740 write_back = 1;
3741 str++;
3742 if (reg == REG_PC)
3743 {
3744 inst.error = _("R15 not allowed as base register with write-back");
3745 return;
3746 }
3747 }
3748 else
3749 write_back = 0;
3750
3751 if (flags & CP_T_Pre)
3752 {
3753 /* Pre-decrement */
3754 offset = 3 * num_regs;
3755 if (write_back)
3756 flags |= CP_T_WB;
3757 }
3758 else
3759 {
3760 /* Post-increment */
3761 if (write_back)
3762 {
3763 flags |= CP_T_WB;
3764 offset = 3 * num_regs;
3765 }
3766 else
3767 {
3768 /* No write-back, so convert this into a standard pre-increment
3769 instruction -- aesthetically more pleasing. */
3770 flags = CP_T_Pre | CP_T_UD;
3771 offset = 0;
3772 }
3773 }
3774
3775 inst.instruction |= flags | offset;
3776 }
3777 else if (skip_past_comma (&str) == FAIL
3778 || cp_address_required_here (&str) == FAIL)
3779 {
3780 if (! inst.error)
3781 inst.error = BAD_ARGS;
3782 return;
3783 }
3784
3785 end_of_line (str);
3786 }
3787
3788 static void
3789 do_fp_dyadic (str, flags)
3790 char * str;
3791 unsigned long flags;
3792 {
3793 skip_whitespace (str);
3794
3795 switch (inst.suffix)
3796 {
3797 case SUFF_S:
3798 break;
3799 case SUFF_D:
3800 inst.instruction |= 0x00000080;
3801 break;
3802 case SUFF_E:
3803 inst.instruction |= 0x00080000;
3804 break;
3805 default:
3806 abort ();
3807 }
3808
3809 if (fp_reg_required_here (&str, 12) == FAIL)
3810 {
3811 if (! inst.error)
3812 inst.error = BAD_ARGS;
3813 return;
3814 }
3815
3816 if (skip_past_comma (&str) == FAIL
3817 || fp_reg_required_here (&str, 16) == FAIL)
3818 {
3819 if (! inst.error)
3820 inst.error = BAD_ARGS;
3821 return;
3822 }
3823
3824 if (skip_past_comma (&str) == FAIL
3825 || fp_op2 (&str) == FAIL)
3826 {
3827 if (! inst.error)
3828 inst.error = BAD_ARGS;
3829 return;
3830 }
3831
3832 inst.instruction |= flags;
3833 end_of_line (str);
3834 return;
3835 }
3836
3837 static void
3838 do_fp_monadic (str, flags)
3839 char * str;
3840 unsigned long flags;
3841 {
3842 skip_whitespace (str);
3843
3844 switch (inst.suffix)
3845 {
3846 case SUFF_S:
3847 break;
3848 case SUFF_D:
3849 inst.instruction |= 0x00000080;
3850 break;
3851 case SUFF_E:
3852 inst.instruction |= 0x00080000;
3853 break;
3854 default:
3855 abort ();
3856 }
3857
3858 if (fp_reg_required_here (&str, 12) == FAIL)
3859 {
3860 if (! inst.error)
3861 inst.error = BAD_ARGS;
3862 return;
3863 }
3864
3865 if (skip_past_comma (&str) == FAIL
3866 || fp_op2 (&str) == FAIL)
3867 {
3868 if (! inst.error)
3869 inst.error = BAD_ARGS;
3870 return;
3871 }
3872
3873 inst.instruction |= flags;
3874 end_of_line (str);
3875 return;
3876 }
3877
3878 static void
3879 do_fp_cmp (str, flags)
3880 char * str;
3881 unsigned long flags;
3882 {
3883 skip_whitespace (str);
3884
3885 if (fp_reg_required_here (&str, 16) == FAIL)
3886 {
3887 if (! inst.error)
3888 inst.error = BAD_ARGS;
3889 return;
3890 }
3891
3892 if (skip_past_comma (&str) == FAIL
3893 || fp_op2 (&str) == FAIL)
3894 {
3895 if (! inst.error)
3896 inst.error = BAD_ARGS;
3897 return;
3898 }
3899
3900 inst.instruction |= flags;
3901 end_of_line (str);
3902 return;
3903 }
3904
3905 static void
3906 do_fp_from_reg (str, flags)
3907 char * str;
3908 unsigned long flags;
3909 {
3910 skip_whitespace (str);
3911
3912 switch (inst.suffix)
3913 {
3914 case SUFF_S:
3915 break;
3916 case SUFF_D:
3917 inst.instruction |= 0x00000080;
3918 break;
3919 case SUFF_E:
3920 inst.instruction |= 0x00080000;
3921 break;
3922 default:
3923 abort ();
3924 }
3925
3926 if (fp_reg_required_here (&str, 16) == FAIL)
3927 {
3928 if (! inst.error)
3929 inst.error = BAD_ARGS;
3930 return;
3931 }
3932
3933 if (skip_past_comma (&str) == FAIL
3934 || reg_required_here (&str, 12) == FAIL)
3935 {
3936 if (! inst.error)
3937 inst.error = BAD_ARGS;
3938 return;
3939 }
3940
3941 inst.instruction |= flags;
3942 end_of_line (str);
3943 return;
3944 }
3945
3946 static void
3947 do_fp_to_reg (str, flags)
3948 char * str;
3949 unsigned long flags;
3950 {
3951 skip_whitespace (str);
3952
3953 if (reg_required_here (&str, 12) == FAIL)
3954 return;
3955
3956 if (skip_past_comma (&str) == FAIL
3957 || fp_reg_required_here (&str, 0) == FAIL)
3958 {
3959 if (! inst.error)
3960 inst.error = BAD_ARGS;
3961 return;
3962 }
3963
3964 inst.instruction |= flags;
3965 end_of_line (str);
3966 return;
3967 }
3968
3969 /* Thumb specific routines */
3970
3971 /* Parse and validate that a register is of the right form, this saves
3972 repeated checking of this information in many similar cases.
3973 Unlike the 32-bit case we do not insert the register into the opcode
3974 here, since the position is often unknown until the full instruction
3975 has been parsed. */
3976 static int
3977 thumb_reg (strp, hi_lo)
3978 char ** strp;
3979 int hi_lo;
3980 {
3981 int reg;
3982
3983 if ((reg = reg_required_here (strp, -1)) == FAIL)
3984 return FAIL;
3985
3986 switch (hi_lo)
3987 {
3988 case THUMB_REG_LO:
3989 if (reg > 7)
3990 {
3991 inst.error = _("lo register required");
3992 return FAIL;
3993 }
3994 break;
3995
3996 case THUMB_REG_HI:
3997 if (reg < 8)
3998 {
3999 inst.error = _("hi register required");
4000 return FAIL;
4001 }
4002 break;
4003
4004 default:
4005 break;
4006 }
4007
4008 return reg;
4009 }
4010
4011 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4012 was SUB. */
4013 static void
4014 thumb_add_sub (str, subtract)
4015 char * str;
4016 int subtract;
4017 {
4018 int Rd, Rs, Rn = FAIL;
4019
4020 skip_whitespace (str);
4021
4022 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4023 || skip_past_comma (&str) == FAIL)
4024 {
4025 if (! inst.error)
4026 inst.error = BAD_ARGS;
4027 return;
4028 }
4029
4030 if (is_immediate_prefix (*str))
4031 {
4032 Rs = Rd;
4033 str++;
4034 if (my_get_expression (&inst.reloc.exp, &str))
4035 return;
4036 }
4037 else
4038 {
4039 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4040 return;
4041
4042 if (skip_past_comma (&str) == FAIL)
4043 {
4044 /* Two operand format, shuffle the registers and pretend there
4045 are 3 */
4046 Rn = Rs;
4047 Rs = Rd;
4048 }
4049 else if (is_immediate_prefix (*str))
4050 {
4051 str++;
4052 if (my_get_expression (&inst.reloc.exp, &str))
4053 return;
4054 }
4055 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4056 return;
4057 }
4058
4059 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4060 for the latter case, EXPR contains the immediate that was found. */
4061 if (Rn != FAIL)
4062 {
4063 /* All register format. */
4064 if (Rd > 7 || Rs > 7 || Rn > 7)
4065 {
4066 if (Rs != Rd)
4067 {
4068 inst.error = _("dest and source1 must be the same register");
4069 return;
4070 }
4071
4072 /* Can't do this for SUB */
4073 if (subtract)
4074 {
4075 inst.error = _("subtract valid only on lo regs");
4076 return;
4077 }
4078
4079 inst.instruction = (T_OPCODE_ADD_HI
4080 | (Rd > 7 ? THUMB_H1 : 0)
4081 | (Rn > 7 ? THUMB_H2 : 0));
4082 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4083 }
4084 else
4085 {
4086 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4087 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4088 }
4089 }
4090 else
4091 {
4092 /* Immediate expression, now things start to get nasty. */
4093
4094 /* First deal with HI regs, only very restricted cases allowed:
4095 Adjusting SP, and using PC or SP to get an address. */
4096 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4097 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4098 {
4099 inst.error = _("invalid Hi register with immediate");
4100 return;
4101 }
4102
4103 if (inst.reloc.exp.X_op != O_constant)
4104 {
4105 /* Value isn't known yet, all we can do is store all the fragments
4106 we know about in the instruction and let the reloc hacking
4107 work it all out. */
4108 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4109 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4110 }
4111 else
4112 {
4113 int offset = inst.reloc.exp.X_add_number;
4114
4115 if (subtract)
4116 offset = -offset;
4117
4118 if (offset < 0)
4119 {
4120 offset = -offset;
4121 subtract = 1;
4122
4123 /* Quick check, in case offset is MIN_INT */
4124 if (offset < 0)
4125 {
4126 inst.error = _("immediate value out of range");
4127 return;
4128 }
4129 }
4130 else
4131 subtract = 0;
4132
4133 if (Rd == REG_SP)
4134 {
4135 if (offset & ~0x1fc)
4136 {
4137 inst.error = _("invalid immediate value for stack adjust");
4138 return;
4139 }
4140 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4141 inst.instruction |= offset >> 2;
4142 }
4143 else if (Rs == REG_PC || Rs == REG_SP)
4144 {
4145 if (subtract
4146 || (offset & ~0x3fc))
4147 {
4148 inst.error = _("invalid immediate for address calculation");
4149 return;
4150 }
4151 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4152 : T_OPCODE_ADD_SP);
4153 inst.instruction |= (Rd << 8) | (offset >> 2);
4154 }
4155 else if (Rs == Rd)
4156 {
4157 if (offset & ~0xff)
4158 {
4159 inst.error = _("immediate value out of range");
4160 return;
4161 }
4162 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4163 inst.instruction |= (Rd << 8) | offset;
4164 }
4165 else
4166 {
4167 if (offset & ~0x7)
4168 {
4169 inst.error = _("immediate value out of range");
4170 return;
4171 }
4172 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4173 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4174 }
4175 }
4176 }
4177
4178 end_of_line (str);
4179 }
4180
4181 static void
4182 thumb_shift (str, shift)
4183 char * str;
4184 int shift;
4185 {
4186 int Rd, Rs, Rn = FAIL;
4187
4188 skip_whitespace (str);
4189
4190 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4191 || skip_past_comma (&str) == FAIL)
4192 {
4193 if (! inst.error)
4194 inst.error = BAD_ARGS;
4195 return;
4196 }
4197
4198 if (is_immediate_prefix (*str))
4199 {
4200 /* Two operand immediate format, set Rs to Rd. */
4201 Rs = Rd;
4202 str ++;
4203 if (my_get_expression (&inst.reloc.exp, &str))
4204 return;
4205 }
4206 else
4207 {
4208 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4209 return;
4210
4211 if (skip_past_comma (&str) == FAIL)
4212 {
4213 /* Two operand format, shuffle the registers and pretend there
4214 are 3 */
4215 Rn = Rs;
4216 Rs = Rd;
4217 }
4218 else if (is_immediate_prefix (*str))
4219 {
4220 str++;
4221 if (my_get_expression (&inst.reloc.exp, &str))
4222 return;
4223 }
4224 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4225 return;
4226 }
4227
4228 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4229 for the latter case, EXPR contains the immediate that was found. */
4230
4231 if (Rn != FAIL)
4232 {
4233 if (Rs != Rd)
4234 {
4235 inst.error = _("source1 and dest must be same register");
4236 return;
4237 }
4238
4239 switch (shift)
4240 {
4241 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4242 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4243 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4244 }
4245
4246 inst.instruction |= Rd | (Rn << 3);
4247 }
4248 else
4249 {
4250 switch (shift)
4251 {
4252 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4253 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4254 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4255 }
4256
4257 if (inst.reloc.exp.X_op != O_constant)
4258 {
4259 /* Value isn't known yet, create a dummy reloc and let reloc
4260 hacking fix it up */
4261
4262 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4263 }
4264 else
4265 {
4266 unsigned shift_value = inst.reloc.exp.X_add_number;
4267
4268 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4269 {
4270 inst.error = _("Invalid immediate for shift");
4271 return;
4272 }
4273
4274 /* Shifts of zero are handled by converting to LSL */
4275 if (shift_value == 0)
4276 inst.instruction = T_OPCODE_LSL_I;
4277
4278 /* Shifts of 32 are encoded as a shift of zero */
4279 if (shift_value == 32)
4280 shift_value = 0;
4281
4282 inst.instruction |= shift_value << 6;
4283 }
4284
4285 inst.instruction |= Rd | (Rs << 3);
4286 }
4287
4288 end_of_line (str);
4289 }
4290
4291 static void
4292 thumb_mov_compare (str, move)
4293 char * str;
4294 int move;
4295 {
4296 int Rd, Rs = FAIL;
4297
4298 skip_whitespace (str);
4299
4300 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4301 || skip_past_comma (&str) == FAIL)
4302 {
4303 if (! inst.error)
4304 inst.error = BAD_ARGS;
4305 return;
4306 }
4307
4308 if (is_immediate_prefix (*str))
4309 {
4310 str++;
4311 if (my_get_expression (&inst.reloc.exp, &str))
4312 return;
4313 }
4314 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4315 return;
4316
4317 if (Rs != FAIL)
4318 {
4319 if (Rs < 8 && Rd < 8)
4320 {
4321 if (move == THUMB_MOVE)
4322 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4323 since a MOV instruction produces unpredictable results */
4324 inst.instruction = T_OPCODE_ADD_I3;
4325 else
4326 inst.instruction = T_OPCODE_CMP_LR;
4327 inst.instruction |= Rd | (Rs << 3);
4328 }
4329 else
4330 {
4331 if (move == THUMB_MOVE)
4332 inst.instruction = T_OPCODE_MOV_HR;
4333 else
4334 inst.instruction = T_OPCODE_CMP_HR;
4335
4336 if (Rd > 7)
4337 inst.instruction |= THUMB_H1;
4338
4339 if (Rs > 7)
4340 inst.instruction |= THUMB_H2;
4341
4342 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4343 }
4344 }
4345 else
4346 {
4347 if (Rd > 7)
4348 {
4349 inst.error = _("only lo regs allowed with immediate");
4350 return;
4351 }
4352
4353 if (move == THUMB_MOVE)
4354 inst.instruction = T_OPCODE_MOV_I8;
4355 else
4356 inst.instruction = T_OPCODE_CMP_I8;
4357
4358 inst.instruction |= Rd << 8;
4359
4360 if (inst.reloc.exp.X_op != O_constant)
4361 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4362 else
4363 {
4364 unsigned value = inst.reloc.exp.X_add_number;
4365
4366 if (value > 255)
4367 {
4368 inst.error = _("invalid immediate");
4369 return;
4370 }
4371
4372 inst.instruction |= value;
4373 }
4374 }
4375
4376 end_of_line (str);
4377 }
4378
4379 static void
4380 thumb_load_store (str, load_store, size)
4381 char * str;
4382 int load_store;
4383 int size;
4384 {
4385 int Rd, Rb, Ro = FAIL;
4386
4387 skip_whitespace (str);
4388
4389 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4390 || skip_past_comma (&str) == FAIL)
4391 {
4392 if (! inst.error)
4393 inst.error = BAD_ARGS;
4394 return;
4395 }
4396
4397 if (*str == '[')
4398 {
4399 str++;
4400 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4401 return;
4402
4403 if (skip_past_comma (&str) != FAIL)
4404 {
4405 if (is_immediate_prefix (*str))
4406 {
4407 str++;
4408 if (my_get_expression (&inst.reloc.exp, &str))
4409 return;
4410 }
4411 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4412 return;
4413 }
4414 else
4415 {
4416 inst.reloc.exp.X_op = O_constant;
4417 inst.reloc.exp.X_add_number = 0;
4418 }
4419
4420 if (*str != ']')
4421 {
4422 inst.error = _("expected ']'");
4423 return;
4424 }
4425 str++;
4426 }
4427 else if (*str == '=')
4428 {
4429 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4430 str++;
4431
4432 skip_whitespace (str);
4433
4434 if (my_get_expression (& inst.reloc.exp, & str))
4435 return;
4436
4437 end_of_line (str);
4438
4439 if ( inst.reloc.exp.X_op != O_constant
4440 && inst.reloc.exp.X_op != O_symbol)
4441 {
4442 inst.error = "Constant expression expected";
4443 return;
4444 }
4445
4446 if (inst.reloc.exp.X_op == O_constant
4447 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4448 {
4449 /* This can be done with a mov instruction */
4450
4451 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4452 inst.instruction |= inst.reloc.exp.X_add_number;
4453 return;
4454 }
4455
4456 /* Insert into literal pool */
4457 if (add_to_lit_pool () == FAIL)
4458 {
4459 if (!inst.error)
4460 inst.error = "literal pool insertion failed";
4461 return;
4462 }
4463
4464 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4465 inst.reloc.pc_rel = 1;
4466 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4467 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4468
4469 return;
4470 }
4471 else
4472 {
4473 if (my_get_expression (&inst.reloc.exp, &str))
4474 return;
4475
4476 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4477 inst.reloc.pc_rel = 1;
4478 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4479 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4480 end_of_line (str);
4481 return;
4482 }
4483
4484 if (Rb == REG_PC || Rb == REG_SP)
4485 {
4486 if (size != THUMB_WORD)
4487 {
4488 inst.error = _("byte or halfword not valid for base register");
4489 return;
4490 }
4491 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4492 {
4493 inst.error = _("R15 based store not allowed");
4494 return;
4495 }
4496 else if (Ro != FAIL)
4497 {
4498 inst.error = _("Invalid base register for register offset");
4499 return;
4500 }
4501
4502 if (Rb == REG_PC)
4503 inst.instruction = T_OPCODE_LDR_PC;
4504 else if (load_store == THUMB_LOAD)
4505 inst.instruction = T_OPCODE_LDR_SP;
4506 else
4507 inst.instruction = T_OPCODE_STR_SP;
4508
4509 inst.instruction |= Rd << 8;
4510 if (inst.reloc.exp.X_op == O_constant)
4511 {
4512 unsigned offset = inst.reloc.exp.X_add_number;
4513
4514 if (offset & ~0x3fc)
4515 {
4516 inst.error = _("invalid offset");
4517 return;
4518 }
4519
4520 inst.instruction |= offset >> 2;
4521 }
4522 else
4523 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4524 }
4525 else if (Rb > 7)
4526 {
4527 inst.error = _("invalid base register in load/store");
4528 return;
4529 }
4530 else if (Ro == FAIL)
4531 {
4532 /* Immediate offset */
4533 if (size == THUMB_WORD)
4534 inst.instruction = (load_store == THUMB_LOAD
4535 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4536 else if (size == THUMB_HALFWORD)
4537 inst.instruction = (load_store == THUMB_LOAD
4538 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4539 else
4540 inst.instruction = (load_store == THUMB_LOAD
4541 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4542
4543 inst.instruction |= Rd | (Rb << 3);
4544
4545 if (inst.reloc.exp.X_op == O_constant)
4546 {
4547 unsigned offset = inst.reloc.exp.X_add_number;
4548
4549 if (offset & ~(0x1f << size))
4550 {
4551 inst.error = _("Invalid offset");
4552 return;
4553 }
4554 inst.instruction |= (offset >> size) << 6;
4555 }
4556 else
4557 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4558 }
4559 else
4560 {
4561 /* Register offset */
4562 if (size == THUMB_WORD)
4563 inst.instruction = (load_store == THUMB_LOAD
4564 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4565 else if (size == THUMB_HALFWORD)
4566 inst.instruction = (load_store == THUMB_LOAD
4567 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4568 else
4569 inst.instruction = (load_store == THUMB_LOAD
4570 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4571
4572 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4573 }
4574
4575 end_of_line (str);
4576 }
4577
4578 static void
4579 do_t_nop (str)
4580 char * str;
4581 {
4582 /* Do nothing */
4583 end_of_line (str);
4584 return;
4585 }
4586
4587 /* Handle the Format 4 instructions that do not have equivalents in other
4588 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4589 BIC and MVN. */
4590 static void
4591 do_t_arit (str)
4592 char * str;
4593 {
4594 int Rd, Rs, Rn;
4595
4596 skip_whitespace (str);
4597
4598 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4599 || skip_past_comma (&str) == FAIL
4600 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4601 {
4602 inst.error = BAD_ARGS;
4603 return;
4604 }
4605
4606 if (skip_past_comma (&str) != FAIL)
4607 {
4608 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4609 (It isn't allowed for CMP either, but that isn't handled by this
4610 function.) */
4611 if (inst.instruction == T_OPCODE_TST
4612 || inst.instruction == T_OPCODE_CMN
4613 || inst.instruction == T_OPCODE_NEG
4614 || inst.instruction == T_OPCODE_MVN)
4615 {
4616 inst.error = BAD_ARGS;
4617 return;
4618 }
4619
4620 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4621 return;
4622
4623 if (Rs != Rd)
4624 {
4625 inst.error = _("dest and source1 one must be the same register");
4626 return;
4627 }
4628 Rs = Rn;
4629 }
4630
4631 if (inst.instruction == T_OPCODE_MUL
4632 && Rs == Rd)
4633 as_tsktsk (_("Rs and Rd must be different in MUL"));
4634
4635 inst.instruction |= Rd | (Rs << 3);
4636 end_of_line (str);
4637 }
4638
4639 static void
4640 do_t_add (str)
4641 char * str;
4642 {
4643 thumb_add_sub (str, 0);
4644 }
4645
4646 static void
4647 do_t_asr (str)
4648 char * str;
4649 {
4650 thumb_shift (str, THUMB_ASR);
4651 }
4652
4653 static void
4654 do_t_branch9 (str)
4655 char * str;
4656 {
4657 if (my_get_expression (&inst.reloc.exp, &str))
4658 return;
4659 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4660 inst.reloc.pc_rel = 1;
4661 end_of_line (str);
4662 }
4663
4664 static void
4665 do_t_branch12 (str)
4666 char * str;
4667 {
4668 if (my_get_expression (&inst.reloc.exp, &str))
4669 return;
4670 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4671 inst.reloc.pc_rel = 1;
4672 end_of_line (str);
4673 }
4674
4675 /* Find the real, Thumb encoded start of a Thumb function. */
4676
4677 static symbolS *
4678 find_real_start (symbolP)
4679 symbolS * symbolP;
4680 {
4681 char * real_start;
4682 const char * name = S_GET_NAME (symbolP);
4683 symbolS * new_target;
4684
4685 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4686 #define STUB_NAME ".real_start_of"
4687
4688 if (name == NULL)
4689 abort();
4690
4691 /* Names that start with '.' are local labels, not function entry points.
4692 The compiler may generate BL instructions to these labels because it
4693 needs to perform a branch to a far away location. */
4694 if (name[0] == '.')
4695 return symbolP;
4696
4697 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4698 sprintf (real_start, "%s%s", STUB_NAME, name);
4699
4700 new_target = symbol_find (real_start);
4701
4702 if (new_target == NULL)
4703 {
4704 as_warn ("Failed to find real start of function: %s\n", name);
4705 new_target = symbolP;
4706 }
4707
4708 free (real_start);
4709
4710 return new_target;
4711 }
4712
4713
4714 static void
4715 do_t_branch23 (str)
4716 char * str;
4717 {
4718 if (my_get_expression (& inst.reloc.exp, & str))
4719 return;
4720
4721 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4722 inst.reloc.pc_rel = 1;
4723 end_of_line (str);
4724
4725 /* If the destination of the branch is a defined symbol which does not have
4726 the THUMB_FUNC attribute, then we must be calling a function which has
4727 the (interfacearm) attribute. We look for the Thumb entry point to that
4728 function and change the branch to refer to that function instead. */
4729 if ( inst.reloc.exp.X_op == O_symbol
4730 && inst.reloc.exp.X_add_symbol != NULL
4731 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4732 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4733 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4734 }
4735
4736 static void
4737 do_t_bx (str)
4738 char * str;
4739 {
4740 int reg;
4741
4742 skip_whitespace (str);
4743
4744 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4745 return;
4746
4747 /* This sets THUMB_H2 from the top bit of reg. */
4748 inst.instruction |= reg << 3;
4749
4750 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4751 should cause the alignment to be checked once it is known. This is
4752 because BX PC only works if the instruction is word aligned. */
4753
4754 end_of_line (str);
4755 }
4756
4757 static void
4758 do_t_compare (str)
4759 char * str;
4760 {
4761 thumb_mov_compare (str, THUMB_COMPARE);
4762 }
4763
4764 static void
4765 do_t_ldmstm (str)
4766 char * str;
4767 {
4768 int Rb;
4769 long range;
4770
4771 skip_whitespace (str);
4772
4773 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4774 return;
4775
4776 if (*str != '!')
4777 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4778 else
4779 str++;
4780
4781 if (skip_past_comma (&str) == FAIL
4782 || (range = reg_list (&str)) == FAIL)
4783 {
4784 if (! inst.error)
4785 inst.error = BAD_ARGS;
4786 return;
4787 }
4788
4789 if (inst.reloc.type != BFD_RELOC_NONE)
4790 {
4791 /* This really doesn't seem worth it. */
4792 inst.reloc.type = BFD_RELOC_NONE;
4793 inst.error = _("Expression too complex");
4794 return;
4795 }
4796
4797 if (range & ~0xff)
4798 {
4799 inst.error = _("only lo-regs valid in load/store multiple");
4800 return;
4801 }
4802
4803 inst.instruction |= (Rb << 8) | range;
4804 end_of_line (str);
4805 }
4806
4807 static void
4808 do_t_ldr (str)
4809 char * str;
4810 {
4811 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4812 }
4813
4814 static void
4815 do_t_ldrb (str)
4816 char * str;
4817 {
4818 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4819 }
4820
4821 static void
4822 do_t_ldrh (str)
4823 char * str;
4824 {
4825 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4826 }
4827
4828 static void
4829 do_t_lds (str)
4830 char * str;
4831 {
4832 int Rd, Rb, Ro;
4833
4834 skip_whitespace (str);
4835
4836 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4837 || skip_past_comma (&str) == FAIL
4838 || *str++ != '['
4839 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4840 || skip_past_comma (&str) == FAIL
4841 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4842 || *str++ != ']')
4843 {
4844 if (! inst.error)
4845 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4846 return;
4847 }
4848
4849 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4850 end_of_line (str);
4851 }
4852
4853 static void
4854 do_t_lsl (str)
4855 char * str;
4856 {
4857 thumb_shift (str, THUMB_LSL);
4858 }
4859
4860 static void
4861 do_t_lsr (str)
4862 char * str;
4863 {
4864 thumb_shift (str, THUMB_LSR);
4865 }
4866
4867 static void
4868 do_t_mov (str)
4869 char * str;
4870 {
4871 thumb_mov_compare (str, THUMB_MOVE);
4872 }
4873
4874 static void
4875 do_t_push_pop (str)
4876 char * str;
4877 {
4878 long range;
4879
4880 skip_whitespace (str);
4881
4882 if ((range = reg_list (&str)) == FAIL)
4883 {
4884 if (! inst.error)
4885 inst.error = BAD_ARGS;
4886 return;
4887 }
4888
4889 if (inst.reloc.type != BFD_RELOC_NONE)
4890 {
4891 /* This really doesn't seem worth it. */
4892 inst.reloc.type = BFD_RELOC_NONE;
4893 inst.error = _("Expression too complex");
4894 return;
4895 }
4896
4897 if (range & ~0xff)
4898 {
4899 if ((inst.instruction == T_OPCODE_PUSH
4900 && (range & ~0xff) == 1 << REG_LR)
4901 || (inst.instruction == T_OPCODE_POP
4902 && (range & ~0xff) == 1 << REG_PC))
4903 {
4904 inst.instruction |= THUMB_PP_PC_LR;
4905 range &= 0xff;
4906 }
4907 else
4908 {
4909 inst.error = _("invalid register list to push/pop instruction");
4910 return;
4911 }
4912 }
4913
4914 inst.instruction |= range;
4915 end_of_line (str);
4916 }
4917
4918 static void
4919 do_t_str (str)
4920 char * str;
4921 {
4922 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4923 }
4924
4925 static void
4926 do_t_strb (str)
4927 char * str;
4928 {
4929 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4930 }
4931
4932 static void
4933 do_t_strh (str)
4934 char * str;
4935 {
4936 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4937 }
4938
4939 static void
4940 do_t_sub (str)
4941 char * str;
4942 {
4943 thumb_add_sub (str, 1);
4944 }
4945
4946 static void
4947 do_t_swi (str)
4948 char * str;
4949 {
4950 skip_whitespace (str);
4951
4952 if (my_get_expression (&inst.reloc.exp, &str))
4953 return;
4954
4955 inst.reloc.type = BFD_RELOC_ARM_SWI;
4956 end_of_line (str);
4957 return;
4958 }
4959
4960 static void
4961 do_t_adr (str)
4962 char * str;
4963 {
4964 int reg;
4965
4966 /* This is a pseudo-op of the form "adr rd, label" to be converted
4967 into a relative address of the form "add rd, pc, #label-.-4". */
4968 skip_whitespace (str);
4969
4970 /* Store Rd in temporary location inside instruction. */
4971 if ((reg = reg_required_here (&str, 4)) == FAIL
4972 || (reg > 7) /* For Thumb reg must be r0..r7. */
4973 || skip_past_comma (&str) == FAIL
4974 || my_get_expression (&inst.reloc.exp, &str))
4975 {
4976 if (!inst.error)
4977 inst.error = BAD_ARGS;
4978 return;
4979 }
4980
4981 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4982 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
4983 inst.reloc.pc_rel = 1;
4984 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
4985
4986 end_of_line (str);
4987 }
4988
4989 static void
4990 insert_reg (entry)
4991 int entry;
4992 {
4993 int len = strlen (reg_table[entry].name) + 2;
4994 char * buf = (char *) xmalloc (len);
4995 char * buf2 = (char *) xmalloc (len);
4996 int i = 0;
4997
4998 #ifdef REGISTER_PREFIX
4999 buf[i++] = REGISTER_PREFIX;
5000 #endif
5001
5002 strcpy (buf + i, reg_table[entry].name);
5003
5004 for (i = 0; buf[i]; i++)
5005 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5006
5007 buf2[i] = '\0';
5008
5009 hash_insert (arm_reg_hsh, buf, (PTR) &reg_table[entry]);
5010 hash_insert (arm_reg_hsh, buf2, (PTR) &reg_table[entry]);
5011 }
5012
5013 static void
5014 insert_reg_alias (str, regnum)
5015 char *str;
5016 int regnum;
5017 {
5018 struct reg_entry *new =
5019 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
5020 char *name = xmalloc (strlen (str) + 1);
5021 strcpy (name, str);
5022
5023 new->name = name;
5024 new->number = regnum;
5025
5026 hash_insert (arm_reg_hsh, name, (PTR) new);
5027 }
5028
5029 static void
5030 set_constant_flonums ()
5031 {
5032 int i;
5033
5034 for (i = 0; i < NUM_FLOAT_VALS; i++)
5035 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
5036 abort ();
5037 }
5038
5039 void
5040 md_begin ()
5041 {
5042 unsigned mach;
5043 unsigned int i;
5044
5045 if ( (arm_ops_hsh = hash_new ()) == NULL
5046 || (arm_tops_hsh = hash_new ()) == NULL
5047 || (arm_cond_hsh = hash_new ()) == NULL
5048 || (arm_shift_hsh = hash_new ()) == NULL
5049 || (arm_reg_hsh = hash_new ()) == NULL
5050 || (arm_psr_hsh = hash_new ()) == NULL)
5051 as_fatal (_("Virtual memory exhausted"));
5052
5053 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5054 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5055 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5056 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5057 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5058 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5059 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5060 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5061 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5062 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5063
5064 for (i = 0; reg_table[i].name; i++)
5065 insert_reg (i);
5066
5067 set_constant_flonums ();
5068
5069 #if defined OBJ_COFF || defined OBJ_ELF
5070 {
5071 unsigned int flags = 0;
5072
5073 /* Set the flags in the private structure. */
5074 if (uses_apcs_26) flags |= F_APCS26;
5075 if (support_interwork) flags |= F_INTERWORK;
5076 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5077 if (pic_code) flags |= F_PIC;
5078 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5079
5080 bfd_set_private_flags (stdoutput, flags);
5081 }
5082 #endif
5083
5084 /* Record the CPU type as well. */
5085 switch (cpu_variant & ARM_CPU_MASK)
5086 {
5087 case ARM_2:
5088 mach = bfd_mach_arm_2;
5089 break;
5090
5091 case ARM_3: /* Also ARM_250. */
5092 mach = bfd_mach_arm_2a;
5093 break;
5094
5095 default:
5096 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5097 mach = bfd_mach_arm_4;
5098 break;
5099
5100 case ARM_7: /* Also ARM_6. */
5101 mach = bfd_mach_arm_3;
5102 break;
5103 }
5104
5105 /* Catch special cases. */
5106 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5107 {
5108 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5109 mach = bfd_mach_arm_5T;
5110 else if (cpu_variant & ARM_EXT_V5)
5111 mach = bfd_mach_arm_5;
5112 else if (cpu_variant & ARM_THUMB)
5113 mach = bfd_mach_arm_4T;
5114 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5115 mach = bfd_mach_arm_4;
5116 else if (cpu_variant & ARM_LONGMUL)
5117 mach = bfd_mach_arm_3M;
5118 }
5119
5120 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5121 }
5122
5123 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5124 for use in the a.out file, and stores them in the array pointed to by buf.
5125 This knows about the endian-ness of the target machine and does
5126 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5127 2 (short) and 4 (long) Floating numbers are put out as a series of
5128 LITTLENUMS (shorts, here at least). */
5129 void
5130 md_number_to_chars (buf, val, n)
5131 char * buf;
5132 valueT val;
5133 int n;
5134 {
5135 if (target_big_endian)
5136 number_to_chars_bigendian (buf, val, n);
5137 else
5138 number_to_chars_littleendian (buf, val, n);
5139 }
5140
5141 static valueT
5142 md_chars_to_number (buf, n)
5143 char * buf;
5144 int n;
5145 {
5146 valueT result = 0;
5147 unsigned char * where = (unsigned char *) buf;
5148
5149 if (target_big_endian)
5150 {
5151 while (n--)
5152 {
5153 result <<= 8;
5154 result |= (*where++ & 255);
5155 }
5156 }
5157 else
5158 {
5159 while (n--)
5160 {
5161 result <<= 8;
5162 result |= (where[n] & 255);
5163 }
5164 }
5165
5166 return result;
5167 }
5168
5169 /* Turn a string in input_line_pointer into a floating point constant
5170 of type TYPE, and store the appropriate bytes in *litP. The number
5171 of LITTLENUMS emitted is stored in *sizeP . An error message is
5172 returned, or NULL on OK.
5173
5174 Note that fp constants aren't represent in the normal way on the ARM.
5175 In big endian mode, things are as expected. However, in little endian
5176 mode fp constants are big-endian word-wise, and little-endian byte-wise
5177 within the words. For example, (double) 1.1 in big endian mode is
5178 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5179 the byte sequence 99 99 f1 3f 9a 99 99 99.
5180
5181 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5182
5183 char *
5184 md_atof (type, litP, sizeP)
5185 char type;
5186 char * litP;
5187 int * sizeP;
5188 {
5189 int prec;
5190 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5191 char *t;
5192 int i;
5193
5194 switch (type)
5195 {
5196 case 'f':
5197 case 'F':
5198 case 's':
5199 case 'S':
5200 prec = 2;
5201 break;
5202
5203 case 'd':
5204 case 'D':
5205 case 'r':
5206 case 'R':
5207 prec = 4;
5208 break;
5209
5210 case 'x':
5211 case 'X':
5212 prec = 6;
5213 break;
5214
5215 case 'p':
5216 case 'P':
5217 prec = 6;
5218 break;
5219
5220 default:
5221 *sizeP = 0;
5222 return _("Bad call to MD_ATOF()");
5223 }
5224
5225 t = atof_ieee (input_line_pointer, type, words);
5226 if (t)
5227 input_line_pointer = t;
5228 *sizeP = prec * 2;
5229
5230 if (target_big_endian)
5231 {
5232 for (i = 0; i < prec; i++)
5233 {
5234 md_number_to_chars (litP, (valueT) words[i], 2);
5235 litP += 2;
5236 }
5237 }
5238 else
5239 {
5240 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5241 8 byte float the order is 1 0 3 2. */
5242 for (i = 0; i < prec; i += 2)
5243 {
5244 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5245 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5246 litP += 4;
5247 }
5248 }
5249
5250 return 0;
5251 }
5252
5253 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5254 long
5255 md_pcrel_from (fixP)
5256 fixS * fixP;
5257 {
5258 if ( fixP->fx_addsy
5259 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5260 && fixP->fx_subsy == NULL)
5261 return 0;
5262
5263 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5264 {
5265 /* PC relative addressing on the Thumb is slightly odd
5266 as the bottom two bits of the PC are forced to zero
5267 for the calculation. */
5268 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5269 }
5270
5271 #ifdef TE_WINCE
5272 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5273 so we un-adjust here to compensate for the accomodation. */
5274 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5275 #else
5276 return fixP->fx_where + fixP->fx_frag->fr_address;
5277 #endif
5278 }
5279
5280 /* Round up a section size to the appropriate boundary. */
5281 valueT
5282 md_section_align (segment, size)
5283 segT segment ATTRIBUTE_UNUSED;
5284 valueT size;
5285 {
5286 #ifdef OBJ_ELF
5287 return size;
5288 #else
5289 /* Round all sects to multiple of 4 */
5290 return (size + 3) & ~3;
5291 #endif
5292 }
5293
5294 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5295 we have no need to default values of symbols. */
5296
5297 /* ARGSUSED */
5298 symbolS *
5299 md_undefined_symbol (name)
5300 char * name ATTRIBUTE_UNUSED;
5301 {
5302 #ifdef OBJ_ELF
5303 if (name[0] == '_' && name[1] == 'G'
5304 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5305 {
5306 if (!GOT_symbol)
5307 {
5308 if (symbol_find (name))
5309 as_bad ("GOT already in the symbol table");
5310
5311 GOT_symbol = symbol_new (name, undefined_section,
5312 (valueT)0, & zero_address_frag);
5313 }
5314
5315 return GOT_symbol;
5316 }
5317 #endif
5318
5319 return 0;
5320 }
5321
5322 /* arm_reg_parse () := if it looks like a register, return its token and
5323 advance the pointer. */
5324
5325 static int
5326 arm_reg_parse (ccp)
5327 register char ** ccp;
5328 {
5329 char * start = * ccp;
5330 char c;
5331 char * p;
5332 struct reg_entry * reg;
5333
5334 #ifdef REGISTER_PREFIX
5335 if (*start != REGISTER_PREFIX)
5336 return FAIL;
5337 p = start + 1;
5338 #else
5339 p = start;
5340 #ifdef OPTIONAL_REGISTER_PREFIX
5341 if (*p == OPTIONAL_REGISTER_PREFIX)
5342 p++, start++;
5343 #endif
5344 #endif
5345 if (!isalpha (*p) || !is_name_beginner (*p))
5346 return FAIL;
5347
5348 c = *p++;
5349 while (isalpha (c) || isdigit (c) || c == '_')
5350 c = *p++;
5351
5352 *--p = 0;
5353 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5354 *p = c;
5355
5356 if (reg)
5357 {
5358 *ccp = p;
5359 return reg->number;
5360 }
5361
5362 return FAIL;
5363 }
5364
5365 int
5366 md_apply_fix3 (fixP, val, seg)
5367 fixS * fixP;
5368 valueT * val;
5369 segT seg;
5370 {
5371 offsetT value = * val;
5372 offsetT newval;
5373 unsigned int newimm;
5374 unsigned long temp;
5375 int sign;
5376 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5377 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5378
5379 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5380
5381 /* Note whether this will delete the relocation. */
5382 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5383 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5384 && !fixP->fx_pcrel)
5385 #else
5386 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5387 #endif
5388 fixP->fx_done = 1;
5389
5390 /* If this symbol is in a different section then we need to leave it for
5391 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5392 so we have to undo it's effects here. */
5393 if (fixP->fx_pcrel)
5394 {
5395 if (fixP->fx_addsy != NULL
5396 && S_IS_DEFINED (fixP->fx_addsy)
5397 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5398 {
5399 if (target_oabi
5400 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5401 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5402 ))
5403 value = 0;
5404 else
5405 value += md_pcrel_from (fixP);
5406 }
5407 }
5408
5409 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5410
5411 switch (fixP->fx_r_type)
5412 {
5413 case BFD_RELOC_ARM_IMMEDIATE:
5414 newimm = validate_immediate (value);
5415 temp = md_chars_to_number (buf, INSN_SIZE);
5416
5417 /* If the instruction will fail, see if we can fix things up by
5418 changing the opcode. */
5419 if (newimm == (unsigned int) FAIL
5420 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5421 {
5422 as_bad_where (fixP->fx_file, fixP->fx_line,
5423 _("invalid constant (%lx) after fixup"),
5424 (unsigned long) value);
5425 break;
5426 }
5427
5428 newimm |= (temp & 0xfffff000);
5429 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5430 break;
5431
5432 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5433 {
5434 unsigned int highpart = 0;
5435 unsigned int newinsn = 0xe1a00000; /* nop */
5436 newimm = validate_immediate (value);
5437 temp = md_chars_to_number (buf, INSN_SIZE);
5438
5439 /* If the instruction will fail, see if we can fix things up by
5440 changing the opcode. */
5441 if (newimm == (unsigned int) FAIL
5442 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5443 {
5444 /* No ? OK - try using two ADD instructions to generate the value. */
5445 newimm = validate_immediate_twopart (value, & highpart);
5446
5447 /* Yes - then make sure that the second instruction is also an add. */
5448 if (newimm != (unsigned int) FAIL)
5449 newinsn = temp;
5450 /* Still No ? Try using a negated value. */
5451 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5452 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5453 /* Otherwise - give up. */
5454 else
5455 {
5456 as_bad_where (fixP->fx_file, fixP->fx_line,
5457 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5458 break;
5459 }
5460
5461 /* Replace the first operand in the 2nd instruction (which is the PC)
5462 with the destination register. We have already added in the PC in the
5463 first instruction and we do not want to do it again. */
5464 newinsn &= ~ 0xf0000;
5465 newinsn |= ((newinsn & 0x0f000) << 4);
5466 }
5467
5468 newimm |= (temp & 0xfffff000);
5469 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5470
5471 highpart |= (newinsn & 0xfffff000);
5472 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5473 }
5474 break;
5475
5476 case BFD_RELOC_ARM_OFFSET_IMM:
5477 sign = value >= 0;
5478
5479 if (value < 0)
5480 value = - value;
5481
5482 if (validate_offset_imm (value, 0) == FAIL)
5483 {
5484 as_bad_where (fixP->fx_file, fixP->fx_line,
5485 _("bad immediate value for offset (%ld)"), (long) value);
5486 break;
5487 }
5488
5489 newval = md_chars_to_number (buf, INSN_SIZE);
5490 newval &= 0xff7ff000;
5491 newval |= value | (sign ? INDEX_UP : 0);
5492 md_number_to_chars (buf, newval, INSN_SIZE);
5493 break;
5494
5495 case BFD_RELOC_ARM_OFFSET_IMM8:
5496 case BFD_RELOC_ARM_HWLITERAL:
5497 sign = value >= 0;
5498
5499 if (value < 0)
5500 value = - value;
5501
5502 if (validate_offset_imm (value, 1) == FAIL)
5503 {
5504 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5505 as_bad_where (fixP->fx_file, fixP->fx_line,
5506 _("invalid literal constant: pool needs to be closer"));
5507 else
5508 as_bad (_("bad immediate value for half-word offset (%ld)"),
5509 (long) value);
5510 break;
5511 }
5512
5513 newval = md_chars_to_number (buf, INSN_SIZE);
5514 newval &= 0xff7ff0f0;
5515 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5516 md_number_to_chars (buf, newval, INSN_SIZE);
5517 break;
5518
5519 case BFD_RELOC_ARM_LITERAL:
5520 sign = value >= 0;
5521
5522 if (value < 0)
5523 value = - value;
5524
5525 if (validate_offset_imm (value, 0) == FAIL)
5526 {
5527 as_bad_where (fixP->fx_file, fixP->fx_line,
5528 _("invalid literal constant: pool needs to be closer"));
5529 break;
5530 }
5531
5532 newval = md_chars_to_number (buf, INSN_SIZE);
5533 newval &= 0xff7ff000;
5534 newval |= value | (sign ? INDEX_UP : 0);
5535 md_number_to_chars (buf, newval, INSN_SIZE);
5536 break;
5537
5538 case BFD_RELOC_ARM_SHIFT_IMM:
5539 newval = md_chars_to_number (buf, INSN_SIZE);
5540 if (((unsigned long) value) > 32
5541 || (value == 32
5542 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5543 {
5544 as_bad_where (fixP->fx_file, fixP->fx_line,
5545 _("shift expression is too large"));
5546 break;
5547 }
5548
5549 if (value == 0)
5550 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5551 else if (value == 32)
5552 value = 0;
5553 newval &= 0xfffff07f;
5554 newval |= (value & 0x1f) << 7;
5555 md_number_to_chars (buf, newval , INSN_SIZE);
5556 break;
5557
5558 case BFD_RELOC_ARM_SWI:
5559 if (arm_data->thumb_mode)
5560 {
5561 if (((unsigned long) value) > 0xff)
5562 as_bad_where (fixP->fx_file, fixP->fx_line,
5563 _("Invalid swi expression"));
5564 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5565 newval |= value;
5566 md_number_to_chars (buf, newval, THUMB_SIZE);
5567 }
5568 else
5569 {
5570 if (((unsigned long) value) > 0x00ffffff)
5571 as_bad_where (fixP->fx_file, fixP->fx_line,
5572 _("Invalid swi expression"));
5573 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5574 newval |= value;
5575 md_number_to_chars (buf, newval , INSN_SIZE);
5576 }
5577 break;
5578
5579 case BFD_RELOC_ARM_MULTI:
5580 if (((unsigned long) value) > 0xffff)
5581 as_bad_where (fixP->fx_file, fixP->fx_line,
5582 _("Invalid expression in load/store multiple"));
5583 newval = value | md_chars_to_number (buf, INSN_SIZE);
5584 md_number_to_chars (buf, newval, INSN_SIZE);
5585 break;
5586
5587 case BFD_RELOC_ARM_PCREL_BRANCH:
5588 newval = md_chars_to_number (buf, INSN_SIZE);
5589
5590 /* Sign-extend a 24-bit number. */
5591 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5592
5593 #ifdef OBJ_ELF
5594 if (! target_oabi)
5595 value = fixP->fx_offset;
5596 #endif
5597
5598 /* We are going to store value (shifted right by two) in the
5599 instruction, in a 24 bit, signed field. Thus we need to check
5600 that none of the top 8 bits of the shifted value (top 7 bits of
5601 the unshifted, unsigned value) are set, or that they are all set. */
5602 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5603 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5604 {
5605 #ifdef OBJ_ELF
5606 /* Normally we would be stuck at this point, since we cannot store
5607 the absolute address that is the destination of the branch in the
5608 24 bits of the branch instruction. If however, we happen to know
5609 that the destination of the branch is in the same section as the
5610 branch instruciton itself, then we can compute the relocation for
5611 ourselves and not have to bother the linker with it.
5612
5613 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5614 because I have not worked out how to do this for OBJ_COFF or
5615 target_oabi. */
5616 if (! target_oabi
5617 && fixP->fx_addsy != NULL
5618 && S_IS_DEFINED (fixP->fx_addsy)
5619 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5620 {
5621 /* Get pc relative value to go into the branch. */
5622 value = * val;
5623
5624 /* Permit a backward branch provided that enough bits are set.
5625 Allow a forwards branch, provided that enough bits are clear. */
5626 if ((value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5627 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5628 fixP->fx_done = 1;
5629 }
5630
5631 if (! fixP->fx_done)
5632 #endif
5633 as_bad_where (fixP->fx_file, fixP->fx_line,
5634 _("gas can't handle same-section branch dest >= 0x04000000"));
5635 }
5636
5637 value >>= 2;
5638 value += SEXT24 (newval);
5639
5640 if ((value & ~ ((offsetT) 0xffffff)) != 0
5641 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5642 as_bad_where (fixP->fx_file, fixP->fx_line,
5643 _("out of range branch"));
5644
5645 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5646 md_number_to_chars (buf, newval, INSN_SIZE);
5647 break;
5648
5649 case BFD_RELOC_ARM_PCREL_BLX:
5650 {
5651 offsetT hbit;
5652 newval = md_chars_to_number (buf, INSN_SIZE);
5653
5654 #ifdef OBJ_ELF
5655 if (! target_oabi)
5656 value = fixP->fx_offset;
5657 #endif
5658 hbit = (value >> 1) & 1;
5659 value = (value >> 2) & 0x00ffffff;
5660 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5661 newval = value | (newval & 0xfe000000) | (hbit << 24);
5662 md_number_to_chars (buf, newval, INSN_SIZE);
5663 }
5664 break;
5665
5666 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5667 newval = md_chars_to_number (buf, THUMB_SIZE);
5668 {
5669 addressT diff = (newval & 0xff) << 1;
5670 if (diff & 0x100)
5671 diff |= ~0xff;
5672
5673 value += diff;
5674 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5675 as_bad_where (fixP->fx_file, fixP->fx_line,
5676 _("Branch out of range"));
5677 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5678 }
5679 md_number_to_chars (buf, newval, THUMB_SIZE);
5680 break;
5681
5682 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5683 newval = md_chars_to_number (buf, THUMB_SIZE);
5684 {
5685 addressT diff = (newval & 0x7ff) << 1;
5686 if (diff & 0x800)
5687 diff |= ~0x7ff;
5688
5689 value += diff;
5690 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5691 as_bad_where (fixP->fx_file, fixP->fx_line,
5692 _("Branch out of range"));
5693 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5694 }
5695 md_number_to_chars (buf, newval, THUMB_SIZE);
5696 break;
5697
5698 case BFD_RELOC_THUMB_PCREL_BLX:
5699 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5700 {
5701 offsetT newval2;
5702 addressT diff;
5703
5704 newval = md_chars_to_number (buf, THUMB_SIZE);
5705 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5706 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5707 if (diff & 0x400000)
5708 diff |= ~0x3fffff;
5709 #ifdef OBJ_ELF
5710 value = fixP->fx_offset;
5711 #endif
5712 value += diff;
5713 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5714 as_bad_where (fixP->fx_file, fixP->fx_line,
5715 _("Branch with link out of range"));
5716
5717 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5718 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5719 md_number_to_chars (buf, newval, THUMB_SIZE);
5720 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5721 }
5722 break;
5723
5724 case BFD_RELOC_8:
5725 if (fixP->fx_done || fixP->fx_pcrel)
5726 md_number_to_chars (buf, value, 1);
5727 #ifdef OBJ_ELF
5728 else if (!target_oabi)
5729 {
5730 value = fixP->fx_offset;
5731 md_number_to_chars (buf, value, 1);
5732 }
5733 #endif
5734 break;
5735
5736 case BFD_RELOC_16:
5737 if (fixP->fx_done || fixP->fx_pcrel)
5738 md_number_to_chars (buf, value, 2);
5739 #ifdef OBJ_ELF
5740 else if (!target_oabi)
5741 {
5742 value = fixP->fx_offset;
5743 md_number_to_chars (buf, value, 2);
5744 }
5745 #endif
5746 break;
5747
5748 #ifdef OBJ_ELF
5749 case BFD_RELOC_ARM_GOT32:
5750 case BFD_RELOC_ARM_GOTOFF:
5751 md_number_to_chars (buf, 0, 4);
5752 break;
5753 #endif
5754
5755 case BFD_RELOC_RVA:
5756 case BFD_RELOC_32:
5757 if (fixP->fx_done || fixP->fx_pcrel)
5758 md_number_to_chars (buf, value, 4);
5759 #ifdef OBJ_ELF
5760 else if (!target_oabi)
5761 {
5762 value = fixP->fx_offset;
5763 md_number_to_chars (buf, value, 4);
5764 }
5765 #endif
5766 break;
5767
5768 #ifdef OBJ_ELF
5769 case BFD_RELOC_ARM_PLT32:
5770 /* It appears the instruction is fully prepared at this point. */
5771 break;
5772 #endif
5773
5774 case BFD_RELOC_ARM_GOTPC:
5775 md_number_to_chars (buf, value, 4);
5776 break;
5777
5778 case BFD_RELOC_ARM_CP_OFF_IMM:
5779 sign = value >= 0;
5780 if (value < -1023 || value > 1023 || (value & 3))
5781 as_bad_where (fixP->fx_file, fixP->fx_line,
5782 _("Illegal value for co-processor offset"));
5783 if (value < 0)
5784 value = -value;
5785 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5786 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5787 md_number_to_chars (buf, newval , INSN_SIZE);
5788 break;
5789
5790 case BFD_RELOC_ARM_THUMB_OFFSET:
5791 newval = md_chars_to_number (buf, THUMB_SIZE);
5792 /* Exactly what ranges, and where the offset is inserted depends on
5793 the type of instruction, we can establish this from the top 4 bits */
5794 switch (newval >> 12)
5795 {
5796 case 4: /* PC load */
5797 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5798 forced to zero for these loads, so we will need to round
5799 up the offset if the instruction address is not word
5800 aligned (since the final address produced must be, and
5801 we can only describe word-aligned immediate offsets). */
5802
5803 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5804 as_bad_where (fixP->fx_file, fixP->fx_line,
5805 _("Invalid offset, target not word aligned (0x%08X)"),
5806 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5807
5808 if ((value + 2) & ~0x3fe)
5809 as_bad_where (fixP->fx_file, fixP->fx_line,
5810 _("Invalid offset, value too big (0x%08X)"), value);
5811
5812 /* Round up, since pc will be rounded down. */
5813 newval |= (value + 2) >> 2;
5814 break;
5815
5816 case 9: /* SP load/store */
5817 if (value & ~0x3fc)
5818 as_bad_where (fixP->fx_file, fixP->fx_line,
5819 _("Invalid offset, value too big (0x%08X)"), value);
5820 newval |= value >> 2;
5821 break;
5822
5823 case 6: /* Word load/store */
5824 if (value & ~0x7c)
5825 as_bad_where (fixP->fx_file, fixP->fx_line,
5826 _("Invalid offset, value too big (0x%08X)"), value);
5827 newval |= value << 4; /* 6 - 2 */
5828 break;
5829
5830 case 7: /* Byte load/store */
5831 if (value & ~0x1f)
5832 as_bad_where (fixP->fx_file, fixP->fx_line,
5833 _("Invalid offset, value too big (0x%08X)"), value);
5834 newval |= value << 6;
5835 break;
5836
5837 case 8: /* Halfword load/store */
5838 if (value & ~0x3e)
5839 as_bad_where (fixP->fx_file, fixP->fx_line,
5840 _("Invalid offset, value too big (0x%08X)"), value);
5841 newval |= value << 5; /* 6 - 1 */
5842 break;
5843
5844 default:
5845 as_bad_where (fixP->fx_file, fixP->fx_line,
5846 "Unable to process relocation for thumb opcode: %lx",
5847 (unsigned long) newval);
5848 break;
5849 }
5850 md_number_to_chars (buf, newval, THUMB_SIZE);
5851 break;
5852
5853 case BFD_RELOC_ARM_THUMB_ADD:
5854 /* This is a complicated relocation, since we use it for all of
5855 the following immediate relocations:
5856 3bit ADD/SUB
5857 8bit ADD/SUB
5858 9bit ADD/SUB SP word-aligned
5859 10bit ADD PC/SP word-aligned
5860
5861 The type of instruction being processed is encoded in the
5862 instruction field:
5863 0x8000 SUB
5864 0x00F0 Rd
5865 0x000F Rs
5866 */
5867 newval = md_chars_to_number (buf, THUMB_SIZE);
5868 {
5869 int rd = (newval >> 4) & 0xf;
5870 int rs = newval & 0xf;
5871 int subtract = newval & 0x8000;
5872
5873 if (rd == REG_SP)
5874 {
5875 if (value & ~0x1fc)
5876 as_bad_where (fixP->fx_file, fixP->fx_line,
5877 _("Invalid immediate for stack address calculation"));
5878 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5879 newval |= value >> 2;
5880 }
5881 else if (rs == REG_PC || rs == REG_SP)
5882 {
5883 if (subtract ||
5884 value & ~0x3fc)
5885 as_bad_where (fixP->fx_file, fixP->fx_line,
5886 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5887 (unsigned long) value);
5888 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5889 newval |= rd << 8;
5890 newval |= value >> 2;
5891 }
5892 else if (rs == rd)
5893 {
5894 if (value & ~0xff)
5895 as_bad_where (fixP->fx_file, fixP->fx_line,
5896 _("Invalid 8bit immediate"));
5897 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5898 newval |= (rd << 8) | value;
5899 }
5900 else
5901 {
5902 if (value & ~0x7)
5903 as_bad_where (fixP->fx_file, fixP->fx_line,
5904 _("Invalid 3bit immediate"));
5905 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5906 newval |= rd | (rs << 3) | (value << 6);
5907 }
5908 }
5909 md_number_to_chars (buf, newval , THUMB_SIZE);
5910 break;
5911
5912 case BFD_RELOC_ARM_THUMB_IMM:
5913 newval = md_chars_to_number (buf, THUMB_SIZE);
5914 switch (newval >> 11)
5915 {
5916 case 0x04: /* 8bit immediate MOV */
5917 case 0x05: /* 8bit immediate CMP */
5918 if (value < 0 || value > 255)
5919 as_bad_where (fixP->fx_file, fixP->fx_line,
5920 _("Invalid immediate: %ld is too large"),
5921 (long) value);
5922 newval |= value;
5923 break;
5924
5925 default:
5926 abort ();
5927 }
5928 md_number_to_chars (buf, newval , THUMB_SIZE);
5929 break;
5930
5931 case BFD_RELOC_ARM_THUMB_SHIFT:
5932 /* 5bit shift value (0..31) */
5933 if (value < 0 || value > 31)
5934 as_bad_where (fixP->fx_file, fixP->fx_line,
5935 _("Illegal Thumb shift value: %ld"), (long) value);
5936 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5937 newval |= value << 6;
5938 md_number_to_chars (buf, newval , THUMB_SIZE);
5939 break;
5940
5941 case BFD_RELOC_VTABLE_INHERIT:
5942 case BFD_RELOC_VTABLE_ENTRY:
5943 fixP->fx_done = 0;
5944 return 1;
5945
5946 case BFD_RELOC_NONE:
5947 default:
5948 as_bad_where (fixP->fx_file, fixP->fx_line,
5949 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5950 }
5951
5952 return 1;
5953 }
5954
5955 /* Translate internal representation of relocation info to BFD target
5956 format. */
5957 arelent *
5958 tc_gen_reloc (section, fixp)
5959 asection * section ATTRIBUTE_UNUSED;
5960 fixS * fixp;
5961 {
5962 arelent * reloc;
5963 bfd_reloc_code_real_type code;
5964
5965 reloc = (arelent *) xmalloc (sizeof (arelent));
5966
5967 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5968 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5969 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5970
5971 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5972 #ifndef OBJ_ELF
5973 if (fixp->fx_pcrel == 0)
5974 reloc->addend = fixp->fx_offset;
5975 else
5976 reloc->addend = fixp->fx_offset = reloc->address;
5977 #else /* OBJ_ELF */
5978 reloc->addend = fixp->fx_offset;
5979 #endif
5980
5981 switch (fixp->fx_r_type)
5982 {
5983 case BFD_RELOC_8:
5984 if (fixp->fx_pcrel)
5985 {
5986 code = BFD_RELOC_8_PCREL;
5987 break;
5988 }
5989
5990 case BFD_RELOC_16:
5991 if (fixp->fx_pcrel)
5992 {
5993 code = BFD_RELOC_16_PCREL;
5994 break;
5995 }
5996
5997 case BFD_RELOC_32:
5998 if (fixp->fx_pcrel)
5999 {
6000 code = BFD_RELOC_32_PCREL;
6001 break;
6002 }
6003
6004 case BFD_RELOC_ARM_PCREL_BRANCH:
6005 case BFD_RELOC_ARM_PCREL_BLX:
6006 case BFD_RELOC_RVA:
6007 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6008 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6009 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6010 case BFD_RELOC_THUMB_PCREL_BLX:
6011 case BFD_RELOC_VTABLE_ENTRY:
6012 case BFD_RELOC_VTABLE_INHERIT:
6013 code = fixp->fx_r_type;
6014 break;
6015
6016 case BFD_RELOC_ARM_LITERAL:
6017 case BFD_RELOC_ARM_HWLITERAL:
6018 /* If this is called then the a literal has been referenced across
6019 a section boundary - possibly due to an implicit dump */
6020 as_bad_where (fixp->fx_file, fixp->fx_line,
6021 _("Literal referenced across section boundary (Implicit dump?)"));
6022 return NULL;
6023
6024 #ifdef OBJ_ELF
6025 case BFD_RELOC_ARM_GOT32:
6026 case BFD_RELOC_ARM_GOTOFF:
6027 case BFD_RELOC_ARM_PLT32:
6028 code = fixp->fx_r_type;
6029 break;
6030 #endif
6031
6032 case BFD_RELOC_ARM_IMMEDIATE:
6033 as_bad_where (fixp->fx_file, fixp->fx_line,
6034 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6035 fixp->fx_r_type);
6036 return NULL;
6037
6038 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6039 as_bad_where (fixp->fx_file, fixp->fx_line,
6040 _("ADRL used for a symbol not defined in the same file"),
6041 fixp->fx_r_type);
6042 return NULL;
6043
6044 case BFD_RELOC_ARM_OFFSET_IMM:
6045 as_bad_where (fixp->fx_file, fixp->fx_line,
6046 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6047 fixp->fx_r_type);
6048 return NULL;
6049
6050 default:
6051 {
6052 char * type;
6053 switch (fixp->fx_r_type)
6054 {
6055 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6056 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6057 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6058 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6059 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6060 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6061 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6062 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6063 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6064 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6065 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6066 default: type = _("<unknown>"); break;
6067 }
6068 as_bad_where (fixp->fx_file, fixp->fx_line,
6069 _("Can not represent %s relocation in this object file format (%d)"),
6070 type, fixp->fx_pcrel);
6071 return NULL;
6072 }
6073 }
6074
6075 #ifdef OBJ_ELF
6076 if (code == BFD_RELOC_32_PCREL
6077 && GOT_symbol
6078 && fixp->fx_addsy == GOT_symbol)
6079 {
6080 code = BFD_RELOC_ARM_GOTPC;
6081 reloc->addend = fixp->fx_offset = reloc->address;
6082 }
6083 #endif
6084
6085 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6086
6087 if (reloc->howto == NULL)
6088 {
6089 as_bad_where (fixp->fx_file, fixp->fx_line,
6090 _("Can not represent %s relocation in this object file format"),
6091 bfd_get_reloc_code_name (code));
6092 return NULL;
6093 }
6094
6095 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6096 vtable entry to be used in the relocation's section offset. */
6097 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6098 reloc->address = fixp->fx_offset;
6099
6100 return reloc;
6101 }
6102
6103 int
6104 md_estimate_size_before_relax (fragP, segtype)
6105 fragS * fragP ATTRIBUTE_UNUSED;
6106 segT segtype ATTRIBUTE_UNUSED;
6107 {
6108 as_fatal (_("md_estimate_size_before_relax\n"));
6109 return 1;
6110 }
6111
6112 static void
6113 output_inst PARAMS ((void))
6114 {
6115 char * to = NULL;
6116
6117 if (inst.error)
6118 {
6119 as_bad (inst.error);
6120 return;
6121 }
6122
6123 to = frag_more (inst.size);
6124
6125 if (thumb_mode && (inst.size > THUMB_SIZE))
6126 {
6127 assert (inst.size == (2 * THUMB_SIZE));
6128 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6129 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6130 }
6131 else if (inst.size > INSN_SIZE)
6132 {
6133 assert (inst.size == (2 * INSN_SIZE));
6134 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6135 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6136 }
6137 else
6138 md_number_to_chars (to, inst.instruction, inst.size);
6139
6140 if (inst.reloc.type != BFD_RELOC_NONE)
6141 fix_new_arm (frag_now, to - frag_now->fr_literal,
6142 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6143 inst.reloc.type);
6144
6145 return;
6146 }
6147
6148 void
6149 md_assemble (str)
6150 char * str;
6151 {
6152 char c;
6153 char * p;
6154 char * q;
6155 char * start;
6156
6157 /* Align the instruction.
6158 This may not be the right thing to do but ... */
6159 /* arm_align (2, 0); */
6160 listing_prev_line (); /* Defined in listing.h */
6161
6162 /* Align the previous label if needed. */
6163 if (last_label_seen != NULL)
6164 {
6165 symbol_set_frag (last_label_seen, frag_now);
6166 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6167 S_SET_SEGMENT (last_label_seen, now_seg);
6168 }
6169
6170 memset (&inst, '\0', sizeof (inst));
6171 inst.reloc.type = BFD_RELOC_NONE;
6172
6173 skip_whitespace (str);
6174
6175 /* Scan up to the end of the op-code, which must end in white space or
6176 end of string. */
6177 for (start = p = str; *p != '\0'; p++)
6178 if (*p == ' ')
6179 break;
6180
6181 if (p == str)
6182 {
6183 as_bad (_("No operator -- statement `%s'\n"), str);
6184 return;
6185 }
6186
6187 if (thumb_mode)
6188 {
6189 CONST struct thumb_opcode * opcode;
6190
6191 c = *p;
6192 *p = '\0';
6193 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6194 *p = c;
6195
6196 if (opcode)
6197 {
6198 /* Check that this instruction is supported for this CPU. */
6199 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6200 {
6201 as_bad (_("selected processor does not support this opcode"));
6202 return;
6203 }
6204
6205 inst.instruction = opcode->value;
6206 inst.size = opcode->size;
6207 (*opcode->parms)(p);
6208 output_inst ();
6209 return;
6210 }
6211 }
6212 else
6213 {
6214 CONST struct asm_opcode * opcode;
6215 unsigned long cond_code;
6216
6217 inst.size = INSN_SIZE;
6218 /* p now points to the end of the opcode, probably white space, but we
6219 have to break the opcode up in case it contains condionals and flags;
6220 keep trying with progressively smaller basic instructions until one
6221 matches, or we run out of opcode. */
6222 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6223
6224 for (; q != str; q--)
6225 {
6226 c = *q;
6227 *q = '\0';
6228
6229 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6230 *q = c;
6231
6232 if (opcode && opcode->template)
6233 {
6234 unsigned long flag_bits = 0;
6235 char * r;
6236
6237 /* Check that this instruction is supported for this CPU. */
6238 if ((opcode->variants & cpu_variant) == 0)
6239 goto try_shorter;
6240
6241 inst.instruction = opcode->value;
6242 if (q == p) /* Just a simple opcode. */
6243 {
6244 if (opcode->comp_suffix)
6245 {
6246 if (*opcode->comp_suffix != '\0')
6247 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6248 str, opcode->comp_suffix);
6249 else
6250 /* Not a conditional instruction. */
6251 (*opcode->parms)(q, 0);
6252 }
6253 else
6254 {
6255 /* A conditional instruction with default condition. */
6256 inst.instruction |= COND_ALWAYS;
6257 (*opcode->parms)(q, 0);
6258 }
6259 output_inst ();
6260 return;
6261 }
6262
6263 /* Not just a simple opcode. Check if extra is a conditional. */
6264 r = q;
6265 if (p - r >= 2)
6266 {
6267 CONST struct asm_cond *cond;
6268 char d = *(r + 2);
6269
6270 *(r + 2) = '\0';
6271 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6272 *(r + 2) = d;
6273 if (cond)
6274 {
6275 if (cond->value == 0xf0000000)
6276 as_tsktsk (
6277 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6278
6279 cond_code = cond->value;
6280 r += 2;
6281 }
6282 else
6283 cond_code = COND_ALWAYS;
6284 }
6285 else
6286 cond_code = COND_ALWAYS;
6287
6288 /* Apply the conditional, or complain it's not allowed. */
6289 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6290 {
6291 /* Instruction isn't conditional */
6292 if (cond_code != COND_ALWAYS)
6293 {
6294 as_bad (_("Opcode `%s' is unconditional\n"), str);
6295 return;
6296 }
6297 }
6298 else
6299 /* Instruction is conditional: set the condition into it. */
6300 inst.instruction |= cond_code;
6301
6302
6303 /* If there is a compulsory suffix, it should come here, before
6304 any optional flags. */
6305 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6306 {
6307 CONST char *s = opcode->comp_suffix;
6308
6309 while (*s)
6310 {
6311 inst.suffix++;
6312 if (*r == *s)
6313 break;
6314 s++;
6315 }
6316
6317 if (*s == '\0')
6318 {
6319 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6320 opcode->comp_suffix);
6321 return;
6322 }
6323
6324 r++;
6325 }
6326
6327 /* The remainder, if any should now be flags for the instruction;
6328 Scan these checking each one found with the opcode. */
6329 if (r != p)
6330 {
6331 char d;
6332 CONST struct asm_flg *flag = opcode->flags;
6333
6334 if (flag)
6335 {
6336 int flagno;
6337
6338 d = *p;
6339 *p = '\0';
6340
6341 for (flagno = 0; flag[flagno].template; flagno++)
6342 {
6343 if (streq (r, flag[flagno].template))
6344 {
6345 flag_bits |= flag[flagno].set_bits;
6346 break;
6347 }
6348 }
6349
6350 *p = d;
6351 if (! flag[flagno].template)
6352 goto try_shorter;
6353 }
6354 else
6355 goto try_shorter;
6356 }
6357
6358 (*opcode->parms) (p, flag_bits);
6359 output_inst ();
6360 return;
6361 }
6362
6363 try_shorter:
6364 ;
6365 }
6366 }
6367
6368 /* It wasn't an instruction, but it might be a register alias of the form
6369 alias .req reg */
6370 q = p;
6371 skip_whitespace (q);
6372
6373 c = *p;
6374 *p = '\0';
6375
6376 if (*q && !strncmp (q, ".req ", 4))
6377 {
6378 int reg;
6379 char * copy_of_str = str;
6380 char * r;
6381
6382 q += 4;
6383 skip_whitespace (q);
6384
6385 for (r = q; *r != '\0'; r++)
6386 if (*r == ' ')
6387 break;
6388
6389 if (r != q)
6390 {
6391 int regnum;
6392 char d = *r;
6393
6394 *r = '\0';
6395 regnum = arm_reg_parse (& q);
6396 *r = d;
6397
6398 reg = arm_reg_parse (& str);
6399
6400 if (reg == FAIL)
6401 {
6402 if (regnum != FAIL)
6403 insert_reg_alias (str, regnum);
6404 else
6405 as_warn (_("register '%s' does not exist\n"), q);
6406 }
6407 else if (regnum != FAIL)
6408 {
6409 if (reg != regnum)
6410 as_warn (_("ignoring redefinition of register alias '%s'"),
6411 copy_of_str );
6412
6413 /* Do not warn about redefinitions to the same alias. */
6414 }
6415 else
6416 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6417 copy_of_str, q);
6418 }
6419 else
6420 as_warn (_("ignoring incomplete .req pseuso op"));
6421
6422 *p = c;
6423 return;
6424 }
6425
6426 *p = c;
6427 as_bad (_("bad instruction `%s'"), start);
6428 }
6429
6430 /*
6431 * md_parse_option
6432 * Invocation line includes a switch not recognized by the base assembler.
6433 * See if it's a processor-specific option. These are:
6434 * Cpu variants, the arm part is optional:
6435 * -m[arm]1 Currently not supported.
6436 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6437 * -m[arm]3 Arm 3 processor
6438 * -m[arm]6[xx], Arm 6 processors
6439 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6440 * -m[arm]8[10] Arm 8 processors
6441 * -m[arm]9[20][tdmi] Arm 9 processors
6442 * -mstrongarm[110[0]] StrongARM processors
6443 * -m[arm]v[2345[t]] Arm architectures
6444 * -mall All (except the ARM1)
6445 * FP variants:
6446 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6447 * -mfpe-old (No float load/store multiples)
6448 * -mno-fpu Disable all floating point instructions
6449 * Run-time endian selection:
6450 * -EB big endian cpu
6451 * -EL little endian cpu
6452 * ARM Procedure Calling Standard:
6453 * -mapcs-32 32 bit APCS
6454 * -mapcs-26 26 bit APCS
6455 * -mapcs-float Pass floats in float regs
6456 * -mapcs-reentrant Position independent code
6457 * -mthumb-interwork Code supports Arm/Thumb interworking
6458 * -moabi Old ELF ABI
6459 */
6460
6461 CONST char * md_shortopts = "m:k";
6462 struct option md_longopts[] =
6463 {
6464 #ifdef ARM_BI_ENDIAN
6465 #define OPTION_EB (OPTION_MD_BASE + 0)
6466 {"EB", no_argument, NULL, OPTION_EB},
6467 #define OPTION_EL (OPTION_MD_BASE + 1)
6468 {"EL", no_argument, NULL, OPTION_EL},
6469 #ifdef OBJ_ELF
6470 #define OPTION_OABI (OPTION_MD_BASE +2)
6471 {"oabi", no_argument, NULL, OPTION_OABI},
6472 #endif
6473 #endif
6474 {NULL, no_argument, NULL, 0}
6475 };
6476 size_t md_longopts_size = sizeof (md_longopts);
6477
6478 int
6479 md_parse_option (c, arg)
6480 int c;
6481 char * arg;
6482 {
6483 char * str = arg;
6484
6485 switch (c)
6486 {
6487 #ifdef ARM_BI_ENDIAN
6488 case OPTION_EB:
6489 target_big_endian = 1;
6490 break;
6491 case OPTION_EL:
6492 target_big_endian = 0;
6493 break;
6494 #endif
6495
6496 case 'm':
6497 switch (*str)
6498 {
6499 case 'f':
6500 if (streq (str, "fpa10"))
6501 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6502 else if (streq (str, "fpa11"))
6503 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6504 else if (streq (str, "fpe-old"))
6505 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6506 else
6507 goto bad;
6508 break;
6509
6510 case 'n':
6511 if (streq (str, "no-fpu"))
6512 cpu_variant &= ~FPU_ALL;
6513 break;
6514
6515 #ifdef OBJ_ELF
6516 case 'o':
6517 if (streq (str, "oabi"))
6518 target_oabi = true;
6519 break;
6520 #endif
6521
6522 case 't':
6523 /* Limit assembler to generating only Thumb instructions: */
6524 if (streq (str, "thumb"))
6525 {
6526 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6527 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6528 thumb_mode = 1;
6529 }
6530 else if (streq (str, "thumb-interwork"))
6531 {
6532 if ((cpu_variant & ARM_THUMB) == 0)
6533 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6534 #if defined OBJ_COFF || defined OBJ_ELF
6535 support_interwork = true;
6536 #endif
6537 }
6538 else
6539 goto bad;
6540 break;
6541
6542 default:
6543 if (streq (str, "all"))
6544 {
6545 cpu_variant = ARM_ALL | FPU_ALL;
6546 return 1;
6547 }
6548 #if defined OBJ_COFF || defined OBJ_ELF
6549 if (! strncmp (str, "apcs-", 5))
6550 {
6551 /* GCC passes on all command line options starting "-mapcs-..."
6552 to us, so we must parse them here. */
6553
6554 str += 5;
6555
6556 if (streq (str, "32"))
6557 {
6558 uses_apcs_26 = false;
6559 return 1;
6560 }
6561 else if (streq (str, "26"))
6562 {
6563 uses_apcs_26 = true;
6564 return 1;
6565 }
6566 else if (streq (str, "frame"))
6567 {
6568 /* Stack frames are being generated - does not affect
6569 linkage of code. */
6570 return 1;
6571 }
6572 else if (streq (str, "stack-check"))
6573 {
6574 /* Stack checking is being performed - does not affect
6575 linkage, but does require that the functions
6576 __rt_stkovf_split_small and __rt_stkovf_split_big be
6577 present in the final link. */
6578
6579 return 1;
6580 }
6581 else if (streq (str, "float"))
6582 {
6583 /* Floating point arguments are being passed in the floating
6584 point registers. This does affect linking, since this
6585 version of the APCS is incompatible with the version that
6586 passes floating points in the integer registers. */
6587
6588 uses_apcs_float = true;
6589 return 1;
6590 }
6591 else if (streq (str, "reentrant"))
6592 {
6593 /* Reentrant code has been generated. This does affect
6594 linking, since there is no point in linking reentrant/
6595 position independent code with absolute position code. */
6596 pic_code = true;
6597 return 1;
6598 }
6599
6600 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6601 return 0;
6602 }
6603 #endif
6604 /* Strip off optional "arm" */
6605 if (! strncmp (str, "arm", 3))
6606 str += 3;
6607
6608 switch (*str)
6609 {
6610 case '1':
6611 if (streq (str, "1"))
6612 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6613 else
6614 goto bad;
6615 break;
6616
6617 case '2':
6618 if (streq (str, "2"))
6619 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6620 else if (streq (str, "250"))
6621 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6622 else
6623 goto bad;
6624 break;
6625
6626 case '3':
6627 if (streq (str, "3"))
6628 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6629 else
6630 goto bad;
6631 break;
6632
6633 case '6':
6634 switch (strtol (str, NULL, 10))
6635 {
6636 case 6:
6637 case 60:
6638 case 600:
6639 case 610:
6640 case 620:
6641 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6642 break;
6643 default:
6644 goto bad;
6645 }
6646 break;
6647
6648 case '7':
6649 switch (strtol (str, & str, 10)) /* Eat the processor name */
6650 {
6651 case 7:
6652 case 70:
6653 case 700:
6654 case 710:
6655 case 720:
6656 case 7100:
6657 case 7500:
6658 break;
6659 default:
6660 goto bad;
6661 }
6662 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6663 for (; *str; str++)
6664 {
6665 switch (* str)
6666 {
6667 case 't':
6668 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6669 break;
6670
6671 case 'm':
6672 cpu_variant |= ARM_LONGMUL;
6673 break;
6674
6675 case 'f': /* fe => fp enabled cpu. */
6676 if (str[1] == 'e')
6677 ++ str;
6678 else
6679 goto bad;
6680
6681 case 'c': /* Left over from 710c processor name. */
6682 case 'd': /* Debug */
6683 case 'i': /* Embedded ICE */
6684 /* Included for completeness in ARM processor naming. */
6685 break;
6686
6687 default:
6688 goto bad;
6689 }
6690 }
6691 break;
6692
6693 case '8':
6694 if (streq (str, "8") || streq (str, "810"))
6695 cpu_variant = (cpu_variant & ~ARM_ANY)
6696 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6697 else
6698 goto bad;
6699 break;
6700
6701 case '9':
6702 if (streq (str, "9"))
6703 cpu_variant = (cpu_variant & ~ARM_ANY)
6704 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6705 else if (streq (str, "920"))
6706 cpu_variant = (cpu_variant & ~ARM_ANY)
6707 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6708 else if (streq (str, "920t"))
6709 cpu_variant = (cpu_variant & ~ARM_ANY)
6710 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6711 else if (streq (str, "9tdmi"))
6712 cpu_variant = (cpu_variant & ~ARM_ANY)
6713 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6714 else
6715 goto bad;
6716 break;
6717
6718
6719 case 's':
6720 if (streq (str, "strongarm")
6721 || streq (str, "strongarm110")
6722 || streq (str, "strongarm1100"))
6723 cpu_variant = (cpu_variant & ~ARM_ANY)
6724 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6725 else
6726 goto bad;
6727 break;
6728
6729 case 'v':
6730 /* Select variant based on architecture rather than processor. */
6731 switch (*++str)
6732 {
6733 case '2':
6734 switch (*++str)
6735 {
6736 case 'a':
6737 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6738 break;
6739 case 0:
6740 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6741 break;
6742 default:
6743 as_bad (_("Invalid architecture variant -m%s"), arg);
6744 break;
6745 }
6746 break;
6747
6748 case '3':
6749 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6750
6751 switch (*++str)
6752 {
6753 case 'm': cpu_variant |= ARM_LONGMUL; break;
6754 case 0: break;
6755 default:
6756 as_bad (_("Invalid architecture variant -m%s"), arg);
6757 break;
6758 }
6759 break;
6760
6761 case '4':
6762 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6763
6764 switch (*++str)
6765 {
6766 case 't': cpu_variant |= ARM_THUMB; break;
6767 case 0: break;
6768 default:
6769 as_bad (_("Invalid architecture variant -m%s"), arg);
6770 break;
6771 }
6772 break;
6773
6774 case '5':
6775 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6776 switch (*++str)
6777 {
6778 case 't': cpu_variant |= ARM_THUMB; break;
6779 case 0: break;
6780 default:
6781 as_bad (_("Invalid architecture variant -m%s"), arg);
6782 break;
6783 }
6784 break;
6785
6786 default:
6787 as_bad (_("Invalid architecture variant -m%s"), arg);
6788 break;
6789 }
6790 break;
6791
6792 default:
6793 bad:
6794 as_bad (_("Invalid processor variant -m%s"), arg);
6795 return 0;
6796 }
6797 }
6798 break;
6799
6800 #if defined OBJ_ELF || defined OBJ_COFF
6801 case 'k':
6802 pic_code = 1;
6803 break;
6804 #endif
6805
6806 default:
6807 return 0;
6808 }
6809
6810 return 1;
6811 }
6812
6813 void
6814 md_show_usage (fp)
6815 FILE * fp;
6816 {
6817 fprintf (fp, _("\
6818 ARM Specific Assembler Options:\n\
6819 -m[arm][<processor name>] select processor variant\n\
6820 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6821 -mthumb only allow Thumb instructions\n\
6822 -mthumb-interwork mark the assembled code as supporting interworking\n\
6823 -mall allow any instruction\n\
6824 -mfpa10, -mfpa11 select floating point architecture\n\
6825 -mfpe-old don't allow floating-point multiple instructions\n\
6826 -mno-fpu don't allow any floating-point instructions.\n\
6827 -k generate PIC code.\n"));
6828 #if defined OBJ_COFF || defined OBJ_ELF
6829 fprintf (fp, _("\
6830 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
6831 -mapcs-float floating point args are passed in FP regs\n\
6832 -mapcs-reentrant the code is position independent/reentrant\n"));
6833 #endif
6834 #ifdef OBJ_ELF
6835 fprintf (fp, _("\
6836 -moabi support the old ELF ABI\n"));
6837 #endif
6838 #ifdef ARM_BI_ENDIAN
6839 fprintf (fp, _("\
6840 -EB assemble code for a big endian cpu\n\
6841 -EL assemble code for a little endian cpu\n"));
6842 #endif
6843 }
6844
6845 /* We need to be able to fix up arbitrary expressions in some statements.
6846 This is so that we can handle symbols that are an arbitrary distance from
6847 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6848 which returns part of an address in a form which will be valid for
6849 a data instruction. We do this by pushing the expression into a symbol
6850 in the expr_section, and creating a fix for that. */
6851
6852 static void
6853 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6854 fragS * frag;
6855 int where;
6856 short int size;
6857 expressionS * exp;
6858 int pc_rel;
6859 int reloc;
6860 {
6861 fixS * new_fix;
6862 arm_fix_data * arm_data;
6863
6864 switch (exp->X_op)
6865 {
6866 case O_constant:
6867 case O_symbol:
6868 case O_add:
6869 case O_subtract:
6870 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6871 break;
6872
6873 default:
6874 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6875 pc_rel, reloc);
6876 break;
6877 }
6878
6879 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6880 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6881 new_fix->tc_fix_data = (PTR) arm_data;
6882 arm_data->thumb_mode = thumb_mode;
6883
6884 return;
6885 }
6886
6887
6888 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6889 void
6890 cons_fix_new_arm (frag, where, size, exp)
6891 fragS * frag;
6892 int where;
6893 int size;
6894 expressionS * exp;
6895 {
6896 bfd_reloc_code_real_type type;
6897 int pcrel = 0;
6898
6899 /* Pick a reloc.
6900 FIXME: @@ Should look at CPU word size. */
6901 switch (size)
6902 {
6903 case 1:
6904 type = BFD_RELOC_8;
6905 break;
6906 case 2:
6907 type = BFD_RELOC_16;
6908 break;
6909 case 4:
6910 default:
6911 type = BFD_RELOC_32;
6912 break;
6913 case 8:
6914 type = BFD_RELOC_64;
6915 break;
6916 }
6917
6918 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6919 }
6920
6921 /* A good place to do this, although this was probably not intended
6922 for this kind of use. We need to dump the literal pool before
6923 references are made to a null symbol pointer. */
6924 void
6925 arm_cleanup ()
6926 {
6927 if (current_poolP == NULL)
6928 return;
6929
6930 subseg_set (text_section, 0); /* Put it at the end of text section. */
6931 s_ltorg (0);
6932 listing_prev_line ();
6933 }
6934
6935 void
6936 arm_start_line_hook ()
6937 {
6938 last_label_seen = NULL;
6939 }
6940
6941 void
6942 arm_frob_label (sym)
6943 symbolS * sym;
6944 {
6945 last_label_seen = sym;
6946
6947 ARM_SET_THUMB (sym, thumb_mode);
6948
6949 #if defined OBJ_COFF || defined OBJ_ELF
6950 ARM_SET_INTERWORK (sym, support_interwork);
6951 #endif
6952
6953 if (label_is_thumb_function_name)
6954 {
6955 /* When the address of a Thumb function is taken the bottom
6956 bit of that address should be set. This will allow
6957 interworking between Arm and Thumb functions to work
6958 correctly. */
6959
6960 THUMB_SET_FUNC (sym, 1);
6961
6962 label_is_thumb_function_name = false;
6963 }
6964 }
6965
6966 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6967 ARM ones. */
6968
6969 void
6970 arm_adjust_symtab ()
6971 {
6972 #ifdef OBJ_COFF
6973 symbolS * sym;
6974
6975 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6976 {
6977 if (ARM_IS_THUMB (sym))
6978 {
6979 if (THUMB_IS_FUNC (sym))
6980 {
6981 /* Mark the symbol as a Thumb function. */
6982 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6983 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6984 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6985
6986 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6987 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6988 else
6989 as_bad (_("%s: unexpected function type: %d"),
6990 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6991 }
6992 else switch (S_GET_STORAGE_CLASS (sym))
6993 {
6994 case C_EXT:
6995 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6996 break;
6997 case C_STAT:
6998 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6999 break;
7000 case C_LABEL:
7001 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7002 break;
7003 default: /* do nothing */
7004 break;
7005 }
7006 }
7007
7008 if (ARM_IS_INTERWORK (sym))
7009 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7010 }
7011 #endif
7012 #ifdef OBJ_ELF
7013 symbolS * sym;
7014 char bind;
7015
7016 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7017 {
7018 if (ARM_IS_THUMB (sym))
7019 {
7020 elf_symbol_type * elf_sym;
7021
7022 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7023 bind = ELF_ST_BIND (elf_sym);
7024
7025 /* If it's a .thumb_func, declare it as so,
7026 otherwise tag label as .code 16. */
7027 if (THUMB_IS_FUNC (sym))
7028 elf_sym->internal_elf_sym.st_info =
7029 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7030 else
7031 elf_sym->internal_elf_sym.st_info =
7032 ELF_ST_INFO (bind, STT_ARM_16BIT);
7033 }
7034 }
7035 #endif
7036 }
7037
7038 int
7039 arm_data_in_code ()
7040 {
7041 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7042 {
7043 *input_line_pointer = '/';
7044 input_line_pointer += 5;
7045 *input_line_pointer = 0;
7046 return 1;
7047 }
7048
7049 return 0;
7050 }
7051
7052 char *
7053 arm_canonicalize_symbol_name (name)
7054 char * name;
7055 {
7056 int len;
7057
7058 if (thumb_mode && (len = strlen (name)) > 5
7059 && streq (name + len - 5, "/data"))
7060 *(name + len - 5) = 0;
7061
7062 return name;
7063 }
7064
7065 boolean
7066 arm_validate_fix (fixP)
7067 fixS * fixP;
7068 {
7069 /* If the destination of the branch is a defined symbol which does not have
7070 the THUMB_FUNC attribute, then we must be calling a function which has
7071 the (interfacearm) attribute. We look for the Thumb entry point to that
7072 function and change the branch to refer to that function instead. */
7073 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7074 && fixP->fx_addsy != NULL
7075 && S_IS_DEFINED (fixP->fx_addsy)
7076 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7077 {
7078 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7079 return true;
7080 }
7081
7082 return false;
7083 }
7084
7085 #ifdef OBJ_ELF
7086 /* Relocations against Thumb function names must be left unadjusted,
7087 so that the linker can use this information to correctly set the
7088 bottom bit of their addresses. The MIPS version of this function
7089 also prevents relocations that are mips-16 specific, but I do not
7090 know why it does this.
7091
7092 FIXME:
7093 There is one other problem that ought to be addressed here, but
7094 which currently is not: Taking the address of a label (rather
7095 than a function) and then later jumping to that address. Such
7096 addresses also ought to have their bottom bit set (assuming that
7097 they reside in Thumb code), but at the moment they will not. */
7098
7099 boolean
7100 arm_fix_adjustable (fixP)
7101 fixS * fixP;
7102 {
7103 if (fixP->fx_addsy == NULL)
7104 return 1;
7105
7106 /* Prevent all adjustments to global symbols. */
7107 if (S_IS_EXTERN (fixP->fx_addsy))
7108 return 0;
7109
7110 if (S_IS_WEAK (fixP->fx_addsy))
7111 return 0;
7112
7113 if (THUMB_IS_FUNC (fixP->fx_addsy)
7114 && fixP->fx_subsy == NULL)
7115 return 0;
7116
7117 /* We need the symbol name for the VTABLE entries */
7118 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7119 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7120 return 0;
7121
7122 return 1;
7123 }
7124
7125 const char *
7126 elf32_arm_target_format ()
7127 {
7128 if (target_big_endian)
7129 if (target_oabi)
7130 return "elf32-bigarm-oabi";
7131 else
7132 return "elf32-bigarm";
7133 else
7134 if (target_oabi)
7135 return "elf32-littlearm-oabi";
7136 else
7137 return "elf32-littlearm";
7138 }
7139
7140 void
7141 armelf_frob_symbol (symp, puntp)
7142 symbolS * symp;
7143 int * puntp;
7144 {
7145 elf_frob_symbol (symp, puntp);
7146 }
7147
7148 int
7149 arm_force_relocation (fixp)
7150 struct fix * fixp;
7151 {
7152 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7153 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7154 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7155 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7156 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7157 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7158 return 1;
7159
7160 return 0;
7161 }
7162
7163 static bfd_reloc_code_real_type
7164 arm_parse_reloc ()
7165 {
7166 char id[16];
7167 char * ip;
7168 unsigned int i;
7169 static struct
7170 {
7171 char * str;
7172 int len;
7173 bfd_reloc_code_real_type reloc;
7174 }
7175 reloc_map[] =
7176 {
7177 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7178 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7179 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7180 /* ScottB: Jan 30, 1998 */
7181 /* Added support for parsing "var(PLT)" branch instructions */
7182 /* generated by GCC for PLT relocs */
7183 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7184 { NULL, 0, BFD_RELOC_UNUSED }
7185 #undef MAP
7186 };
7187
7188 for (i = 0, ip = input_line_pointer;
7189 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7190 i++, ip++)
7191 id[i] = tolower (*ip);
7192
7193 for (i = 0; reloc_map[i].str; i++)
7194 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7195 break;
7196
7197 input_line_pointer += reloc_map[i].len;
7198
7199 return reloc_map[i].reloc;
7200 }
7201
7202 static void
7203 s_arm_elf_cons (nbytes)
7204 int nbytes;
7205 {
7206 expressionS exp;
7207
7208 #ifdef md_flush_pending_output
7209 md_flush_pending_output ();
7210 #endif
7211
7212 if (is_it_end_of_statement ())
7213 {
7214 demand_empty_rest_of_line ();
7215 return;
7216 }
7217
7218 #ifdef md_cons_align
7219 md_cons_align (nbytes);
7220 #endif
7221
7222 do
7223 {
7224 bfd_reloc_code_real_type reloc;
7225
7226 expression (& exp);
7227
7228 if (exp.X_op == O_symbol
7229 && * input_line_pointer == '('
7230 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7231 {
7232 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7233 int size = bfd_get_reloc_size (howto);
7234
7235 if (size > nbytes)
7236 as_bad ("%s relocations do not fit in %d bytes",
7237 howto->name, nbytes);
7238 else
7239 {
7240 register char * p = frag_more ((int) nbytes);
7241 int offset = nbytes - size;
7242
7243 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7244 & exp, 0, reloc);
7245 }
7246 }
7247 else
7248 emit_expr (& exp, (unsigned int) nbytes);
7249 }
7250 while (*input_line_pointer++ == ',');
7251
7252 input_line_pointer--; /* Put terminator back into stream. */
7253 demand_empty_rest_of_line ();
7254 }
7255
7256 #endif /* OBJ_ELF */
GDB Binutils - Deliverables
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