1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_m
=
198 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_vfp_ext_d32
=
221 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
222 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
223 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
224 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
227 static int mfloat_abi_opt
= -1;
228 /* Record user cpu selection for object attributes. */
229 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
230 /* Must be long enough to hold any of the names in arm_cpus. */
231 static char selected_cpu_name
[16];
234 static int meabi_flags
= EABI_DEFAULT
;
236 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
244 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
249 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
250 symbolS
* GOT_symbol
;
253 /* 0: assemble for ARM,
254 1: assemble for Thumb,
255 2: assemble for Thumb even though target CPU does not support thumb
257 static int thumb_mode
= 0;
258 /* A value distinct from the possible values for thumb_mode that we
259 can use to record whether thumb_mode has been copied into the
260 tc_frag_data field of a frag. */
261 #define MODE_RECORDED (1 << 4)
263 /* Specifies the intrinsic IT insn behavior mode. */
264 enum implicit_it_mode
266 IMPLICIT_IT_MODE_NEVER
= 0x00,
267 IMPLICIT_IT_MODE_ARM
= 0x01,
268 IMPLICIT_IT_MODE_THUMB
= 0x02,
269 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
271 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
273 /* If unified_syntax is true, we are processing the new unified
274 ARM/Thumb syntax. Important differences from the old ARM mode:
276 - Immediate operands do not require a # prefix.
277 - Conditional affixes always appear at the end of the
278 instruction. (For backward compatibility, those instructions
279 that formerly had them in the middle, continue to accept them
281 - The IT instruction may appear, and if it does is validated
282 against subsequent conditional affixes. It does not generate
285 Important differences from the old Thumb mode:
287 - Immediate operands do not require a # prefix.
288 - Most of the V6T2 instructions are only available in unified mode.
289 - The .N and .W suffixes are recognized and honored (it is an error
290 if they cannot be honored).
291 - All instructions set the flags if and only if they have an 's' affix.
292 - Conditional affixes may be used. They are validated against
293 preceding IT instructions. Unlike ARM mode, you cannot use a
294 conditional affix except in the scope of an IT instruction. */
296 static bfd_boolean unified_syntax
= FALSE
;
311 enum neon_el_type type
;
315 #define NEON_MAX_TYPE_ELS 4
319 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
323 enum it_instruction_type
328 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
329 if inside, should be the last one. */
330 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
331 i.e. BKPT and NOP. */
332 IT_INSN
/* The IT insn has been parsed. */
338 unsigned long instruction
;
342 /* "uncond_value" is set to the value in place of the conditional field in
343 unconditional versions of the instruction, or -1 if nothing is
346 struct neon_type vectype
;
347 /* Set to the opcode if the instruction needs relaxation.
348 Zero if the instruction is not relaxed. */
352 bfd_reloc_code_real_type type
;
357 enum it_instruction_type it_insn_type
;
363 struct neon_type_el vectype
;
364 unsigned present
: 1; /* Operand present. */
365 unsigned isreg
: 1; /* Operand was a register. */
366 unsigned immisreg
: 1; /* .imm field is a second register. */
367 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
368 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
369 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
370 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
371 instructions. This allows us to disambiguate ARM <-> vector insns. */
372 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
373 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
374 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
375 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
376 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
377 unsigned writeback
: 1; /* Operand has trailing ! */
378 unsigned preind
: 1; /* Preindexed address. */
379 unsigned postind
: 1; /* Postindexed address. */
380 unsigned negative
: 1; /* Index register was negated. */
381 unsigned shifted
: 1; /* Shift applied to operation. */
382 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
386 static struct arm_it inst
;
388 #define NUM_FLOAT_VALS 8
390 const char * fp_const
[] =
392 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
395 /* Number of littlenums required to hold an extended precision number. */
396 #define MAX_LITTLENUMS 6
398 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
408 #define CP_T_X 0x00008000
409 #define CP_T_Y 0x00400000
411 #define CONDS_BIT 0x00100000
412 #define LOAD_BIT 0x00100000
414 #define DOUBLE_LOAD_FLAG 0x00000001
418 const char * template_name
;
422 #define COND_ALWAYS 0xE
426 const char * template_name
;
430 struct asm_barrier_opt
432 const char * template_name
;
436 /* The bit that distinguishes CPSR and SPSR. */
437 #define SPSR_BIT (1 << 22)
439 /* The individual PSR flag bits. */
440 #define PSR_c (1 << 16)
441 #define PSR_x (1 << 17)
442 #define PSR_s (1 << 18)
443 #define PSR_f (1 << 19)
448 bfd_reloc_code_real_type reloc
;
453 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
454 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
459 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
462 /* Bits for DEFINED field in neon_typed_alias. */
463 #define NTA_HASTYPE 1
464 #define NTA_HASINDEX 2
466 struct neon_typed_alias
468 unsigned char defined
;
470 struct neon_type_el eltype
;
473 /* ARM register categories. This includes coprocessor numbers and various
474 architecture extensions' registers. */
500 /* Structure for a hash table entry for a register.
501 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
502 information which states whether a vector type or index is specified (for a
503 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
507 unsigned char number
;
509 unsigned char builtin
;
510 struct neon_typed_alias
* neon
;
513 /* Diagnostics used when we don't get a register of the expected type. */
514 const char * const reg_expected_msgs
[] =
516 N_("ARM register expected"),
517 N_("bad or missing co-processor number"),
518 N_("co-processor register expected"),
519 N_("FPA register expected"),
520 N_("VFP single precision register expected"),
521 N_("VFP/Neon double precision register expected"),
522 N_("Neon quad precision register expected"),
523 N_("VFP single or double precision register expected"),
524 N_("Neon double or quad precision register expected"),
525 N_("VFP single, double or Neon quad precision register expected"),
526 N_("VFP system register expected"),
527 N_("Maverick MVF register expected"),
528 N_("Maverick MVD register expected"),
529 N_("Maverick MVFX register expected"),
530 N_("Maverick MVDX register expected"),
531 N_("Maverick MVAX register expected"),
532 N_("Maverick DSPSC register expected"),
533 N_("iWMMXt data register expected"),
534 N_("iWMMXt control register expected"),
535 N_("iWMMXt scalar register expected"),
536 N_("XScale accumulator register expected"),
539 /* Some well known registers that we refer to directly elsewhere. */
544 /* ARM instructions take 4bytes in the object file, Thumb instructions
550 /* Basic string to match. */
551 const char * template_name
;
553 /* Parameters to instruction. */
554 unsigned char operands
[8];
556 /* Conditional tag - see opcode_lookup. */
557 unsigned int tag
: 4;
559 /* Basic instruction code. */
560 unsigned int avalue
: 28;
562 /* Thumb-format instruction code. */
565 /* Which architecture variant provides this instruction. */
566 const arm_feature_set
* avariant
;
567 const arm_feature_set
* tvariant
;
569 /* Function to call to encode instruction in ARM format. */
570 void (* aencode
) (void);
572 /* Function to call to encode instruction in Thumb format. */
573 void (* tencode
) (void);
576 /* Defines for various bits that we will want to toggle. */
577 #define INST_IMMEDIATE 0x02000000
578 #define OFFSET_REG 0x02000000
579 #define HWOFFSET_IMM 0x00400000
580 #define SHIFT_BY_REG 0x00000010
581 #define PRE_INDEX 0x01000000
582 #define INDEX_UP 0x00800000
583 #define WRITE_BACK 0x00200000
584 #define LDM_TYPE_2_OR_3 0x00400000
585 #define CPSI_MMOD 0x00020000
587 #define LITERAL_MASK 0xf000f000
588 #define OPCODE_MASK 0xfe1fffff
589 #define V4_STR_BIT 0x00000020
591 #define T2_SUBS_PC_LR 0xf3de8f00
593 #define DATA_OP_SHIFT 21
595 #define T2_OPCODE_MASK 0xfe1fffff
596 #define T2_DATA_OP_SHIFT 21
598 /* Codes to distinguish the arithmetic instructions. */
609 #define OPCODE_CMP 10
610 #define OPCODE_CMN 11
611 #define OPCODE_ORR 12
612 #define OPCODE_MOV 13
613 #define OPCODE_BIC 14
614 #define OPCODE_MVN 15
616 #define T2_OPCODE_AND 0
617 #define T2_OPCODE_BIC 1
618 #define T2_OPCODE_ORR 2
619 #define T2_OPCODE_ORN 3
620 #define T2_OPCODE_EOR 4
621 #define T2_OPCODE_ADD 8
622 #define T2_OPCODE_ADC 10
623 #define T2_OPCODE_SBC 11
624 #define T2_OPCODE_SUB 13
625 #define T2_OPCODE_RSB 14
627 #define T_OPCODE_MUL 0x4340
628 #define T_OPCODE_TST 0x4200
629 #define T_OPCODE_CMN 0x42c0
630 #define T_OPCODE_NEG 0x4240
631 #define T_OPCODE_MVN 0x43c0
633 #define T_OPCODE_ADD_R3 0x1800
634 #define T_OPCODE_SUB_R3 0x1a00
635 #define T_OPCODE_ADD_HI 0x4400
636 #define T_OPCODE_ADD_ST 0xb000
637 #define T_OPCODE_SUB_ST 0xb080
638 #define T_OPCODE_ADD_SP 0xa800
639 #define T_OPCODE_ADD_PC 0xa000
640 #define T_OPCODE_ADD_I8 0x3000
641 #define T_OPCODE_SUB_I8 0x3800
642 #define T_OPCODE_ADD_I3 0x1c00
643 #define T_OPCODE_SUB_I3 0x1e00
645 #define T_OPCODE_ASR_R 0x4100
646 #define T_OPCODE_LSL_R 0x4080
647 #define T_OPCODE_LSR_R 0x40c0
648 #define T_OPCODE_ROR_R 0x41c0
649 #define T_OPCODE_ASR_I 0x1000
650 #define T_OPCODE_LSL_I 0x0000
651 #define T_OPCODE_LSR_I 0x0800
653 #define T_OPCODE_MOV_I8 0x2000
654 #define T_OPCODE_CMP_I8 0x2800
655 #define T_OPCODE_CMP_LR 0x4280
656 #define T_OPCODE_MOV_HR 0x4600
657 #define T_OPCODE_CMP_HR 0x4500
659 #define T_OPCODE_LDR_PC 0x4800
660 #define T_OPCODE_LDR_SP 0x9800
661 #define T_OPCODE_STR_SP 0x9000
662 #define T_OPCODE_LDR_IW 0x6800
663 #define T_OPCODE_STR_IW 0x6000
664 #define T_OPCODE_LDR_IH 0x8800
665 #define T_OPCODE_STR_IH 0x8000
666 #define T_OPCODE_LDR_IB 0x7800
667 #define T_OPCODE_STR_IB 0x7000
668 #define T_OPCODE_LDR_RW 0x5800
669 #define T_OPCODE_STR_RW 0x5000
670 #define T_OPCODE_LDR_RH 0x5a00
671 #define T_OPCODE_STR_RH 0x5200
672 #define T_OPCODE_LDR_RB 0x5c00
673 #define T_OPCODE_STR_RB 0x5400
675 #define T_OPCODE_PUSH 0xb400
676 #define T_OPCODE_POP 0xbc00
678 #define T_OPCODE_BRANCH 0xe000
680 #define THUMB_SIZE 2 /* Size of thumb instruction. */
681 #define THUMB_PP_PC_LR 0x0100
682 #define THUMB_LOAD_BIT 0x0800
683 #define THUMB2_LOAD_BIT 0x00100000
685 #define BAD_ARGS _("bad arguments to instruction")
686 #define BAD_SP _("r13 not allowed here")
687 #define BAD_PC _("r15 not allowed here")
688 #define BAD_COND _("instruction cannot be conditional")
689 #define BAD_OVERLAP _("registers may not be the same")
690 #define BAD_HIREG _("lo register required")
691 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
692 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
693 #define BAD_BRANCH _("branch must be last instruction in IT block")
694 #define BAD_NOT_IT _("instruction not allowed in IT block")
695 #define BAD_FPU _("selected FPU does not support instruction")
696 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
697 #define BAD_IT_COND _("incorrect condition in IT block")
698 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
699 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
701 static struct hash_control
* arm_ops_hsh
;
702 static struct hash_control
* arm_cond_hsh
;
703 static struct hash_control
* arm_shift_hsh
;
704 static struct hash_control
* arm_psr_hsh
;
705 static struct hash_control
* arm_v7m_psr_hsh
;
706 static struct hash_control
* arm_reg_hsh
;
707 static struct hash_control
* arm_reloc_hsh
;
708 static struct hash_control
* arm_barrier_opt_hsh
;
710 /* Stuff needed to resolve the label ambiguity
719 symbolS
* last_label_seen
;
720 static int label_is_thumb_function_name
= FALSE
;
722 /* Literal pool structure. Held on a per-section
723 and per-sub-section basis. */
725 #define MAX_LITERAL_POOL_SIZE 1024
726 typedef struct literal_pool
728 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
729 unsigned int next_free_entry
;
734 struct literal_pool
* next
;
737 /* Pointer to a linked list of literal pools. */
738 literal_pool
* list_of_pools
= NULL
;
741 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
743 static struct current_it now_it
;
747 now_it_compatible (int cond
)
749 return (cond
& ~1) == (now_it
.cc
& ~1);
753 conditional_insn (void)
755 return inst
.cond
!= COND_ALWAYS
;
758 static int in_it_block (void);
760 static int handle_it_state (void);
762 static void force_automatic_it_block_close (void);
764 static void it_fsm_post_encode (void);
766 #define set_it_insn_type(type) \
769 inst.it_insn_type = type; \
770 if (handle_it_state () == FAIL) \
775 #define set_it_insn_type_nonvoid(type, failret) \
778 inst.it_insn_type = type; \
779 if (handle_it_state () == FAIL) \
784 #define set_it_insn_type_last() \
787 if (inst.cond == COND_ALWAYS) \
788 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
790 set_it_insn_type (INSIDE_IT_LAST_INSN); \
796 /* This array holds the chars that always start a comment. If the
797 pre-processor is disabled, these aren't very useful. */
798 const char comment_chars
[] = "@";
800 /* This array holds the chars that only start a comment at the beginning of
801 a line. If the line seems to have the form '# 123 filename'
802 .line and .file directives will appear in the pre-processed output. */
803 /* Note that input_file.c hand checks for '#' at the beginning of the
804 first line of the input file. This is because the compiler outputs
805 #NO_APP at the beginning of its output. */
806 /* Also note that comments like this one will always work. */
807 const char line_comment_chars
[] = "#";
809 const char line_separator_chars
[] = ";";
811 /* Chars that can be used to separate mant
812 from exp in floating point numbers. */
813 const char EXP_CHARS
[] = "eE";
815 /* Chars that mean this number is a floating point constant. */
819 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
821 /* Prefix characters that indicate the start of an immediate
823 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
825 /* Separator character handling. */
827 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
830 skip_past_char (char ** str
, char c
)
841 #define skip_past_comma(str) skip_past_char (str, ',')
843 /* Arithmetic expressions (possibly involving symbols). */
845 /* Return TRUE if anything in the expression is a bignum. */
848 walk_no_bignums (symbolS
* sp
)
850 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
853 if (symbol_get_value_expression (sp
)->X_add_symbol
)
855 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
856 || (symbol_get_value_expression (sp
)->X_op_symbol
857 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
863 static int in_my_get_expression
= 0;
865 /* Third argument to my_get_expression. */
866 #define GE_NO_PREFIX 0
867 #define GE_IMM_PREFIX 1
868 #define GE_OPT_PREFIX 2
869 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
870 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
871 #define GE_OPT_PREFIX_BIG 3
874 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
879 /* In unified syntax, all prefixes are optional. */
881 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
886 case GE_NO_PREFIX
: break;
888 if (!is_immediate_prefix (**str
))
890 inst
.error
= _("immediate expression requires a # prefix");
896 case GE_OPT_PREFIX_BIG
:
897 if (is_immediate_prefix (**str
))
903 memset (ep
, 0, sizeof (expressionS
));
905 save_in
= input_line_pointer
;
906 input_line_pointer
= *str
;
907 in_my_get_expression
= 1;
908 seg
= expression (ep
);
909 in_my_get_expression
= 0;
911 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
913 /* We found a bad or missing expression in md_operand(). */
914 *str
= input_line_pointer
;
915 input_line_pointer
= save_in
;
916 if (inst
.error
== NULL
)
917 inst
.error
= (ep
->X_op
== O_absent
918 ? _("missing expression") :_("bad expression"));
923 if (seg
!= absolute_section
924 && seg
!= text_section
925 && seg
!= data_section
926 && seg
!= bss_section
927 && seg
!= undefined_section
)
929 inst
.error
= _("bad segment");
930 *str
= input_line_pointer
;
931 input_line_pointer
= save_in
;
936 /* Get rid of any bignums now, so that we don't generate an error for which
937 we can't establish a line number later on. Big numbers are never valid
938 in instructions, which is where this routine is always called. */
939 if (prefix_mode
!= GE_OPT_PREFIX_BIG
940 && (ep
->X_op
== O_big
942 && (walk_no_bignums (ep
->X_add_symbol
)
944 && walk_no_bignums (ep
->X_op_symbol
))))))
946 inst
.error
= _("invalid constant");
947 *str
= input_line_pointer
;
948 input_line_pointer
= save_in
;
952 *str
= input_line_pointer
;
953 input_line_pointer
= save_in
;
957 /* Turn a string in input_line_pointer into a floating point constant
958 of type TYPE, and store the appropriate bytes in *LITP. The number
959 of LITTLENUMS emitted is stored in *SIZEP. An error message is
960 returned, or NULL on OK.
962 Note that fp constants aren't represent in the normal way on the ARM.
963 In big endian mode, things are as expected. However, in little endian
964 mode fp constants are big-endian word-wise, and little-endian byte-wise
965 within the words. For example, (double) 1.1 in big endian mode is
966 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
967 the byte sequence 99 99 f1 3f 9a 99 99 99.
969 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
972 md_atof (int type
, char * litP
, int * sizeP
)
975 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1007 return _("Unrecognized or unsupported floating point constant");
1010 t
= atof_ieee (input_line_pointer
, type
, words
);
1012 input_line_pointer
= t
;
1013 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1015 if (target_big_endian
)
1017 for (i
= 0; i
< prec
; i
++)
1019 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1020 litP
+= sizeof (LITTLENUM_TYPE
);
1025 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1026 for (i
= prec
- 1; i
>= 0; i
--)
1028 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1029 litP
+= sizeof (LITTLENUM_TYPE
);
1032 /* For a 4 byte float the order of elements in `words' is 1 0.
1033 For an 8 byte float the order is 1 0 3 2. */
1034 for (i
= 0; i
< prec
; i
+= 2)
1036 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1037 sizeof (LITTLENUM_TYPE
));
1038 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1039 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1047 /* We handle all bad expressions here, so that we can report the faulty
1048 instruction in the error message. */
1050 md_operand (expressionS
* expr
)
1052 if (in_my_get_expression
)
1053 expr
->X_op
= O_illegal
;
1056 /* Immediate values. */
1058 /* Generic immediate-value read function for use in directives.
1059 Accepts anything that 'expression' can fold to a constant.
1060 *val receives the number. */
1063 immediate_for_directive (int *val
)
1066 exp
.X_op
= O_illegal
;
1068 if (is_immediate_prefix (*input_line_pointer
))
1070 input_line_pointer
++;
1074 if (exp
.X_op
!= O_constant
)
1076 as_bad (_("expected #constant"));
1077 ignore_rest_of_line ();
1080 *val
= exp
.X_add_number
;
1085 /* Register parsing. */
1087 /* Generic register parser. CCP points to what should be the
1088 beginning of a register name. If it is indeed a valid register
1089 name, advance CCP over it and return the reg_entry structure;
1090 otherwise return NULL. Does not issue diagnostics. */
1092 static struct reg_entry
*
1093 arm_reg_parse_multi (char **ccp
)
1097 struct reg_entry
*reg
;
1099 #ifdef REGISTER_PREFIX
1100 if (*start
!= REGISTER_PREFIX
)
1104 #ifdef OPTIONAL_REGISTER_PREFIX
1105 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1110 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1115 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1117 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1127 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1128 enum arm_reg_type type
)
1130 /* Alternative syntaxes are accepted for a few register classes. */
1137 /* Generic coprocessor register names are allowed for these. */
1138 if (reg
&& reg
->type
== REG_TYPE_CN
)
1143 /* For backward compatibility, a bare number is valid here. */
1145 unsigned long processor
= strtoul (start
, ccp
, 10);
1146 if (*ccp
!= start
&& processor
<= 15)
1150 case REG_TYPE_MMXWC
:
1151 /* WC includes WCG. ??? I'm not sure this is true for all
1152 instructions that take WC registers. */
1153 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1164 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1165 return value is the register number or FAIL. */
1168 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1171 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1174 /* Do not allow a scalar (reg+index) to parse as a register. */
1175 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1178 if (reg
&& reg
->type
== type
)
1181 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1188 /* Parse a Neon type specifier. *STR should point at the leading '.'
1189 character. Does no verification at this stage that the type fits the opcode
1196 Can all be legally parsed by this function.
1198 Fills in neon_type struct pointer with parsed information, and updates STR
1199 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1200 type, FAIL if not. */
1203 parse_neon_type (struct neon_type
*type
, char **str
)
1210 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1212 enum neon_el_type thistype
= NT_untyped
;
1213 unsigned thissize
= -1u;
1220 /* Just a size without an explicit type. */
1224 switch (TOLOWER (*ptr
))
1226 case 'i': thistype
= NT_integer
; break;
1227 case 'f': thistype
= NT_float
; break;
1228 case 'p': thistype
= NT_poly
; break;
1229 case 's': thistype
= NT_signed
; break;
1230 case 'u': thistype
= NT_unsigned
; break;
1232 thistype
= NT_float
;
1237 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1243 /* .f is an abbreviation for .f32. */
1244 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1249 thissize
= strtoul (ptr
, &ptr
, 10);
1251 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1254 as_bad (_("bad size %d in type specifier"), thissize
);
1262 type
->el
[type
->elems
].type
= thistype
;
1263 type
->el
[type
->elems
].size
= thissize
;
1268 /* Empty/missing type is not a successful parse. */
1269 if (type
->elems
== 0)
1277 /* Errors may be set multiple times during parsing or bit encoding
1278 (particularly in the Neon bits), but usually the earliest error which is set
1279 will be the most meaningful. Avoid overwriting it with later (cascading)
1280 errors by calling this function. */
1283 first_error (const char *err
)
1289 /* Parse a single type, e.g. ".s32", leading period included. */
1291 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1294 struct neon_type optype
;
1298 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1300 if (optype
.elems
== 1)
1301 *vectype
= optype
.el
[0];
1304 first_error (_("only one type should be specified for operand"));
1310 first_error (_("vector type expected"));
1322 /* Special meanings for indices (which have a range of 0-7), which will fit into
1325 #define NEON_ALL_LANES 15
1326 #define NEON_INTERLEAVE_LANES 14
1328 /* Parse either a register or a scalar, with an optional type. Return the
1329 register number, and optionally fill in the actual type of the register
1330 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1331 type/index information in *TYPEINFO. */
1334 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1335 enum arm_reg_type
*rtype
,
1336 struct neon_typed_alias
*typeinfo
)
1339 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1340 struct neon_typed_alias atype
;
1341 struct neon_type_el parsetype
;
1345 atype
.eltype
.type
= NT_invtype
;
1346 atype
.eltype
.size
= -1;
1348 /* Try alternate syntax for some types of register. Note these are mutually
1349 exclusive with the Neon syntax extensions. */
1352 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1360 /* Undo polymorphism when a set of register types may be accepted. */
1361 if ((type
== REG_TYPE_NDQ
1362 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1363 || (type
== REG_TYPE_VFSD
1364 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1365 || (type
== REG_TYPE_NSDQ
1366 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1367 || reg
->type
== REG_TYPE_NQ
))
1368 || (type
== REG_TYPE_MMXWC
1369 && (reg
->type
== REG_TYPE_MMXWCG
)))
1370 type
= (enum arm_reg_type
) reg
->type
;
1372 if (type
!= reg
->type
)
1378 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1380 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1382 first_error (_("can't redefine type for operand"));
1385 atype
.defined
|= NTA_HASTYPE
;
1386 atype
.eltype
= parsetype
;
1389 if (skip_past_char (&str
, '[') == SUCCESS
)
1391 if (type
!= REG_TYPE_VFD
)
1393 first_error (_("only D registers may be indexed"));
1397 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1399 first_error (_("can't change index for operand"));
1403 atype
.defined
|= NTA_HASINDEX
;
1405 if (skip_past_char (&str
, ']') == SUCCESS
)
1406 atype
.index
= NEON_ALL_LANES
;
1411 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1413 if (exp
.X_op
!= O_constant
)
1415 first_error (_("constant expression required"));
1419 if (skip_past_char (&str
, ']') == FAIL
)
1422 atype
.index
= exp
.X_add_number
;
1437 /* Like arm_reg_parse, but allow allow the following extra features:
1438 - If RTYPE is non-zero, return the (possibly restricted) type of the
1439 register (e.g. Neon double or quad reg when either has been requested).
1440 - If this is a Neon vector type with additional type information, fill
1441 in the struct pointed to by VECTYPE (if non-NULL).
1442 This function will fault on encountering a scalar. */
1445 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1446 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1448 struct neon_typed_alias atype
;
1450 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1455 /* Do not allow a scalar (reg+index) to parse as a register. */
1456 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1458 first_error (_("register operand expected, but got scalar"));
1463 *vectype
= atype
.eltype
;
1470 #define NEON_SCALAR_REG(X) ((X) >> 4)
1471 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1473 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1474 have enough information to be able to do a good job bounds-checking. So, we
1475 just do easy checks here, and do further checks later. */
1478 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1482 struct neon_typed_alias atype
;
1484 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1486 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1489 if (atype
.index
== NEON_ALL_LANES
)
1491 first_error (_("scalar must have an index"));
1494 else if (atype
.index
>= 64 / elsize
)
1496 first_error (_("scalar index out of range"));
1501 *type
= atype
.eltype
;
1505 return reg
* 16 + atype
.index
;
1508 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1511 parse_reg_list (char ** strp
)
1513 char * str
= * strp
;
1517 /* We come back here if we get ranges concatenated by '+' or '|'. */
1532 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1534 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1544 first_error (_("bad range in register list"));
1548 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1550 if (range
& (1 << i
))
1552 (_("Warning: duplicated register (r%d) in register list"),
1560 if (range
& (1 << reg
))
1561 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1563 else if (reg
<= cur_reg
)
1564 as_tsktsk (_("Warning: register range not in ascending order"));
1569 while (skip_past_comma (&str
) != FAIL
1570 || (in_range
= 1, *str
++ == '-'));
1575 first_error (_("missing `}'"));
1583 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1586 if (expr
.X_op
== O_constant
)
1588 if (expr
.X_add_number
1589 != (expr
.X_add_number
& 0x0000ffff))
1591 inst
.error
= _("invalid register mask");
1595 if ((range
& expr
.X_add_number
) != 0)
1597 int regno
= range
& expr
.X_add_number
;
1600 regno
= (1 << regno
) - 1;
1602 (_("Warning: duplicated register (r%d) in register list"),
1606 range
|= expr
.X_add_number
;
1610 if (inst
.reloc
.type
!= 0)
1612 inst
.error
= _("expression too complex");
1616 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1617 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1618 inst
.reloc
.pc_rel
= 0;
1622 if (*str
== '|' || *str
== '+')
1628 while (another_range
);
1634 /* Types of registers in a list. */
1643 /* Parse a VFP register list. If the string is invalid return FAIL.
1644 Otherwise return the number of registers, and set PBASE to the first
1645 register. Parses registers of type ETYPE.
1646 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1647 - Q registers can be used to specify pairs of D registers
1648 - { } can be omitted from around a singleton register list
1649 FIXME: This is not implemented, as it would require backtracking in
1652 This could be done (the meaning isn't really ambiguous), but doesn't
1653 fit in well with the current parsing framework.
1654 - 32 D registers may be used (also true for VFPv3).
1655 FIXME: Types are ignored in these register lists, which is probably a
1659 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1664 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1668 unsigned long mask
= 0;
1673 inst
.error
= _("expecting {");
1682 regtype
= REG_TYPE_VFS
;
1687 regtype
= REG_TYPE_VFD
;
1690 case REGLIST_NEON_D
:
1691 regtype
= REG_TYPE_NDQ
;
1695 if (etype
!= REGLIST_VFP_S
)
1697 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1698 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1702 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1705 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1712 base_reg
= max_regs
;
1716 int setmask
= 1, addregs
= 1;
1718 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1720 if (new_base
== FAIL
)
1722 first_error (_(reg_expected_msgs
[regtype
]));
1726 if (new_base
>= max_regs
)
1728 first_error (_("register out of range in list"));
1732 /* Note: a value of 2 * n is returned for the register Q<n>. */
1733 if (regtype
== REG_TYPE_NQ
)
1739 if (new_base
< base_reg
)
1740 base_reg
= new_base
;
1742 if (mask
& (setmask
<< new_base
))
1744 first_error (_("invalid register list"));
1748 if ((mask
>> new_base
) != 0 && ! warned
)
1750 as_tsktsk (_("register list not in ascending order"));
1754 mask
|= setmask
<< new_base
;
1757 if (*str
== '-') /* We have the start of a range expression */
1763 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1766 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1770 if (high_range
>= max_regs
)
1772 first_error (_("register out of range in list"));
1776 if (regtype
== REG_TYPE_NQ
)
1777 high_range
= high_range
+ 1;
1779 if (high_range
<= new_base
)
1781 inst
.error
= _("register range not in ascending order");
1785 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1787 if (mask
& (setmask
<< new_base
))
1789 inst
.error
= _("invalid register list");
1793 mask
|= setmask
<< new_base
;
1798 while (skip_past_comma (&str
) != FAIL
);
1802 /* Sanity check -- should have raised a parse error above. */
1803 if (count
== 0 || count
> max_regs
)
1808 /* Final test -- the registers must be consecutive. */
1810 for (i
= 0; i
< count
; i
++)
1812 if ((mask
& (1u << i
)) == 0)
1814 inst
.error
= _("non-contiguous register range");
1824 /* True if two alias types are the same. */
1827 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1835 if (a
->defined
!= b
->defined
)
1838 if ((a
->defined
& NTA_HASTYPE
) != 0
1839 && (a
->eltype
.type
!= b
->eltype
.type
1840 || a
->eltype
.size
!= b
->eltype
.size
))
1843 if ((a
->defined
& NTA_HASINDEX
) != 0
1844 && (a
->index
!= b
->index
))
1850 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1851 The base register is put in *PBASE.
1852 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1854 The register stride (minus one) is put in bit 4 of the return value.
1855 Bits [6:5] encode the list length (minus one).
1856 The type of the list elements is put in *ELTYPE, if non-NULL. */
1858 #define NEON_LANE(X) ((X) & 0xf)
1859 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1860 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1863 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1864 struct neon_type_el
*eltype
)
1871 int leading_brace
= 0;
1872 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1874 const char *const incr_error
= _("register stride must be 1 or 2");
1875 const char *const type_error
= _("mismatched element/structure types in list");
1876 struct neon_typed_alias firsttype
;
1878 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1883 struct neon_typed_alias atype
;
1884 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1888 first_error (_(reg_expected_msgs
[rtype
]));
1895 if (rtype
== REG_TYPE_NQ
)
1902 else if (reg_incr
== -1)
1904 reg_incr
= getreg
- base_reg
;
1905 if (reg_incr
< 1 || reg_incr
> 2)
1907 first_error (_(incr_error
));
1911 else if (getreg
!= base_reg
+ reg_incr
* count
)
1913 first_error (_(incr_error
));
1917 if (! neon_alias_types_same (&atype
, &firsttype
))
1919 first_error (_(type_error
));
1923 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1927 struct neon_typed_alias htype
;
1928 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1930 lane
= NEON_INTERLEAVE_LANES
;
1931 else if (lane
!= NEON_INTERLEAVE_LANES
)
1933 first_error (_(type_error
));
1938 else if (reg_incr
!= 1)
1940 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1944 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1947 first_error (_(reg_expected_msgs
[rtype
]));
1950 if (! neon_alias_types_same (&htype
, &firsttype
))
1952 first_error (_(type_error
));
1955 count
+= hireg
+ dregs
- getreg
;
1959 /* If we're using Q registers, we can't use [] or [n] syntax. */
1960 if (rtype
== REG_TYPE_NQ
)
1966 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1970 else if (lane
!= atype
.index
)
1972 first_error (_(type_error
));
1976 else if (lane
== -1)
1977 lane
= NEON_INTERLEAVE_LANES
;
1978 else if (lane
!= NEON_INTERLEAVE_LANES
)
1980 first_error (_(type_error
));
1985 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1987 /* No lane set by [x]. We must be interleaving structures. */
1989 lane
= NEON_INTERLEAVE_LANES
;
1992 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1993 || (count
> 1 && reg_incr
== -1))
1995 first_error (_("error parsing element/structure list"));
1999 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2001 first_error (_("expected }"));
2009 *eltype
= firsttype
.eltype
;
2014 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2017 /* Parse an explicit relocation suffix on an expression. This is
2018 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2019 arm_reloc_hsh contains no entries, so this function can only
2020 succeed if there is no () after the word. Returns -1 on error,
2021 BFD_RELOC_UNUSED if there wasn't any suffix. */
2023 parse_reloc (char **str
)
2025 struct reloc_entry
*r
;
2029 return BFD_RELOC_UNUSED
;
2034 while (*q
&& *q
!= ')' && *q
!= ',')
2039 if ((r
= (struct reloc_entry
*)
2040 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2047 /* Directives: register aliases. */
2049 static struct reg_entry
*
2050 insert_reg_alias (char *str
, int number
, int type
)
2052 struct reg_entry
*new_reg
;
2055 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2057 if (new_reg
->builtin
)
2058 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2060 /* Only warn about a redefinition if it's not defined as the
2062 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2063 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2068 name
= xstrdup (str
);
2069 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2071 new_reg
->name
= name
;
2072 new_reg
->number
= number
;
2073 new_reg
->type
= type
;
2074 new_reg
->builtin
= FALSE
;
2075 new_reg
->neon
= NULL
;
2077 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2084 insert_neon_reg_alias (char *str
, int number
, int type
,
2085 struct neon_typed_alias
*atype
)
2087 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2091 first_error (_("attempt to redefine typed alias"));
2097 reg
->neon
= (struct neon_typed_alias
*)
2098 xmalloc (sizeof (struct neon_typed_alias
));
2099 *reg
->neon
= *atype
;
2103 /* Look for the .req directive. This is of the form:
2105 new_register_name .req existing_register_name
2107 If we find one, or if it looks sufficiently like one that we want to
2108 handle any error here, return TRUE. Otherwise return FALSE. */
2111 create_register_alias (char * newname
, char *p
)
2113 struct reg_entry
*old
;
2114 char *oldname
, *nbuf
;
2117 /* The input scrubber ensures that whitespace after the mnemonic is
2118 collapsed to single spaces. */
2120 if (strncmp (oldname
, " .req ", 6) != 0)
2124 if (*oldname
== '\0')
2127 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2130 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2134 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2135 the desired alias name, and p points to its end. If not, then
2136 the desired alias name is in the global original_case_string. */
2137 #ifdef TC_CASE_SENSITIVE
2140 newname
= original_case_string
;
2141 nlen
= strlen (newname
);
2144 nbuf
= (char *) alloca (nlen
+ 1);
2145 memcpy (nbuf
, newname
, nlen
);
2148 /* Create aliases under the new name as stated; an all-lowercase
2149 version of the new name; and an all-uppercase version of the new
2151 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2153 for (p
= nbuf
; *p
; p
++)
2156 if (strncmp (nbuf
, newname
, nlen
))
2158 /* If this attempt to create an additional alias fails, do not bother
2159 trying to create the all-lower case alias. We will fail and issue
2160 a second, duplicate error message. This situation arises when the
2161 programmer does something like:
2164 The second .req creates the "Foo" alias but then fails to create
2165 the artificial FOO alias because it has already been created by the
2167 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2171 for (p
= nbuf
; *p
; p
++)
2174 if (strncmp (nbuf
, newname
, nlen
))
2175 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2181 /* Create a Neon typed/indexed register alias using directives, e.g.:
2186 These typed registers can be used instead of the types specified after the
2187 Neon mnemonic, so long as all operands given have types. Types can also be
2188 specified directly, e.g.:
2189 vadd d0.s32, d1.s32, d2.s32 */
2192 create_neon_reg_alias (char *newname
, char *p
)
2194 enum arm_reg_type basetype
;
2195 struct reg_entry
*basereg
;
2196 struct reg_entry mybasereg
;
2197 struct neon_type ntype
;
2198 struct neon_typed_alias typeinfo
;
2199 char *namebuf
, *nameend
;
2202 typeinfo
.defined
= 0;
2203 typeinfo
.eltype
.type
= NT_invtype
;
2204 typeinfo
.eltype
.size
= -1;
2205 typeinfo
.index
= -1;
2209 if (strncmp (p
, " .dn ", 5) == 0)
2210 basetype
= REG_TYPE_VFD
;
2211 else if (strncmp (p
, " .qn ", 5) == 0)
2212 basetype
= REG_TYPE_NQ
;
2221 basereg
= arm_reg_parse_multi (&p
);
2223 if (basereg
&& basereg
->type
!= basetype
)
2225 as_bad (_("bad type for register"));
2229 if (basereg
== NULL
)
2232 /* Try parsing as an integer. */
2233 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2234 if (exp
.X_op
!= O_constant
)
2236 as_bad (_("expression must be constant"));
2239 basereg
= &mybasereg
;
2240 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2246 typeinfo
= *basereg
->neon
;
2248 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2250 /* We got a type. */
2251 if (typeinfo
.defined
& NTA_HASTYPE
)
2253 as_bad (_("can't redefine the type of a register alias"));
2257 typeinfo
.defined
|= NTA_HASTYPE
;
2258 if (ntype
.elems
!= 1)
2260 as_bad (_("you must specify a single type only"));
2263 typeinfo
.eltype
= ntype
.el
[0];
2266 if (skip_past_char (&p
, '[') == SUCCESS
)
2269 /* We got a scalar index. */
2271 if (typeinfo
.defined
& NTA_HASINDEX
)
2273 as_bad (_("can't redefine the index of a scalar alias"));
2277 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2279 if (exp
.X_op
!= O_constant
)
2281 as_bad (_("scalar index must be constant"));
2285 typeinfo
.defined
|= NTA_HASINDEX
;
2286 typeinfo
.index
= exp
.X_add_number
;
2288 if (skip_past_char (&p
, ']') == FAIL
)
2290 as_bad (_("expecting ]"));
2295 namelen
= nameend
- newname
;
2296 namebuf
= (char *) alloca (namelen
+ 1);
2297 strncpy (namebuf
, newname
, namelen
);
2298 namebuf
[namelen
] = '\0';
2300 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2301 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2303 /* Insert name in all uppercase. */
2304 for (p
= namebuf
; *p
; p
++)
2307 if (strncmp (namebuf
, newname
, namelen
))
2308 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2309 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2311 /* Insert name in all lowercase. */
2312 for (p
= namebuf
; *p
; p
++)
2315 if (strncmp (namebuf
, newname
, namelen
))
2316 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2317 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Should never be called, as .req goes between the alias and the
2323 register name, not at the beginning of the line. */
2326 s_req (int a ATTRIBUTE_UNUSED
)
2328 as_bad (_("invalid syntax for .req directive"));
2332 s_dn (int a ATTRIBUTE_UNUSED
)
2334 as_bad (_("invalid syntax for .dn directive"));
2338 s_qn (int a ATTRIBUTE_UNUSED
)
2340 as_bad (_("invalid syntax for .qn directive"));
2343 /* The .unreq directive deletes an alias which was previously defined
2344 by .req. For example:
2350 s_unreq (int a ATTRIBUTE_UNUSED
)
2355 name
= input_line_pointer
;
2357 while (*input_line_pointer
!= 0
2358 && *input_line_pointer
!= ' '
2359 && *input_line_pointer
!= '\n')
2360 ++input_line_pointer
;
2362 saved_char
= *input_line_pointer
;
2363 *input_line_pointer
= 0;
2366 as_bad (_("invalid syntax for .unreq directive"));
2369 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2373 as_bad (_("unknown register alias '%s'"), name
);
2374 else if (reg
->builtin
)
2375 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2382 hash_delete (arm_reg_hsh
, name
, FALSE
);
2383 free ((char *) reg
->name
);
2388 /* Also locate the all upper case and all lower case versions.
2389 Do not complain if we cannot find one or the other as it
2390 was probably deleted above. */
2392 nbuf
= strdup (name
);
2393 for (p
= nbuf
; *p
; p
++)
2395 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2398 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2399 free ((char *) reg
->name
);
2405 for (p
= nbuf
; *p
; p
++)
2407 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2410 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2411 free ((char *) reg
->name
);
2421 *input_line_pointer
= saved_char
;
2422 demand_empty_rest_of_line ();
2425 /* Directives: Instruction set selection. */
2428 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2429 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2430 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2431 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2433 /* Create a new mapping symbol for the transition to STATE. */
2436 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2439 const char * symname
;
2446 type
= BSF_NO_FLAGS
;
2450 type
= BSF_NO_FLAGS
;
2454 type
= BSF_NO_FLAGS
;
2460 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2461 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2466 THUMB_SET_FUNC (symbolP
, 0);
2467 ARM_SET_THUMB (symbolP
, 0);
2468 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2472 THUMB_SET_FUNC (symbolP
, 1);
2473 ARM_SET_THUMB (symbolP
, 1);
2474 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2482 /* Save the mapping symbols for future reference. Also check that
2483 we do not place two mapping symbols at the same offset within a
2484 frag. We'll handle overlap between frags in
2485 check_mapping_symbols. */
2488 know (frag
->tc_frag_data
.first_map
== NULL
);
2489 frag
->tc_frag_data
.first_map
= symbolP
;
2491 if (frag
->tc_frag_data
.last_map
!= NULL
)
2492 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2493 frag
->tc_frag_data
.last_map
= symbolP
;
2496 /* We must sometimes convert a region marked as code to data during
2497 code alignment, if an odd number of bytes have to be padded. The
2498 code mapping symbol is pushed to an aligned address. */
2501 insert_data_mapping_symbol (enum mstate state
,
2502 valueT value
, fragS
*frag
, offsetT bytes
)
2504 /* If there was already a mapping symbol, remove it. */
2505 if (frag
->tc_frag_data
.last_map
!= NULL
2506 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2508 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2512 know (frag
->tc_frag_data
.first_map
== symp
);
2513 frag
->tc_frag_data
.first_map
= NULL
;
2515 frag
->tc_frag_data
.last_map
= NULL
;
2516 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2519 make_mapping_symbol (MAP_DATA
, value
, frag
);
2520 make_mapping_symbol (state
, value
+ bytes
, frag
);
2523 static void mapping_state_2 (enum mstate state
, int max_chars
);
2525 /* Set the mapping state to STATE. Only call this when about to
2526 emit some STATE bytes to the file. */
2529 mapping_state (enum mstate state
)
2531 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2533 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2535 if (mapstate
== state
)
2536 /* The mapping symbol has already been emitted.
2537 There is nothing else to do. */
2539 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2540 /* This case will be evaluated later in the next else. */
2542 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2543 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2545 /* Only add the symbol if the offset is > 0:
2546 if we're at the first frag, check it's size > 0;
2547 if we're not at the first frag, then for sure
2548 the offset is > 0. */
2549 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2550 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2553 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2556 mapping_state_2 (state
, 0);
2560 /* Same as mapping_state, but MAX_CHARS bytes have already been
2561 allocated. Put the mapping symbol that far back. */
2564 mapping_state_2 (enum mstate state
, int max_chars
)
2566 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2568 if (!SEG_NORMAL (now_seg
))
2571 if (mapstate
== state
)
2572 /* The mapping symbol has already been emitted.
2573 There is nothing else to do. */
2576 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2577 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2580 #define mapping_state(x) ((void)0)
2581 #define mapping_state_2(x, y) ((void)0)
2584 /* Find the real, Thumb encoded start of a Thumb function. */
2588 find_real_start (symbolS
* symbolP
)
2591 const char * name
= S_GET_NAME (symbolP
);
2592 symbolS
* new_target
;
2594 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2595 #define STUB_NAME ".real_start_of"
2600 /* The compiler may generate BL instructions to local labels because
2601 it needs to perform a branch to a far away location. These labels
2602 do not have a corresponding ".real_start_of" label. We check
2603 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2604 the ".real_start_of" convention for nonlocal branches. */
2605 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2608 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2609 new_target
= symbol_find (real_start
);
2611 if (new_target
== NULL
)
2613 as_warn (_("Failed to find real start of function: %s\n"), name
);
2614 new_target
= symbolP
;
2622 opcode_select (int width
)
2629 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2630 as_bad (_("selected processor does not support THUMB opcodes"));
2633 /* No need to force the alignment, since we will have been
2634 coming from ARM mode, which is word-aligned. */
2635 record_alignment (now_seg
, 1);
2642 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2643 as_bad (_("selected processor does not support ARM opcodes"));
2648 frag_align (2, 0, 0);
2650 record_alignment (now_seg
, 1);
2655 as_bad (_("invalid instruction size selected (%d)"), width
);
2660 s_arm (int ignore ATTRIBUTE_UNUSED
)
2663 demand_empty_rest_of_line ();
2667 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2670 demand_empty_rest_of_line ();
2674 s_code (int unused ATTRIBUTE_UNUSED
)
2678 temp
= get_absolute_expression ();
2683 opcode_select (temp
);
2687 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2692 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2694 /* If we are not already in thumb mode go into it, EVEN if
2695 the target processor does not support thumb instructions.
2696 This is used by gcc/config/arm/lib1funcs.asm for example
2697 to compile interworking support functions even if the
2698 target processor should not support interworking. */
2702 record_alignment (now_seg
, 1);
2705 demand_empty_rest_of_line ();
2709 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2713 /* The following label is the name/address of the start of a Thumb function.
2714 We need to know this for the interworking support. */
2715 label_is_thumb_function_name
= TRUE
;
2718 /* Perform a .set directive, but also mark the alias as
2719 being a thumb function. */
2722 s_thumb_set (int equiv
)
2724 /* XXX the following is a duplicate of the code for s_set() in read.c
2725 We cannot just call that code as we need to get at the symbol that
2732 /* Especial apologies for the random logic:
2733 This just grew, and could be parsed much more simply!
2735 name
= input_line_pointer
;
2736 delim
= get_symbol_end ();
2737 end_name
= input_line_pointer
;
2740 if (*input_line_pointer
!= ',')
2743 as_bad (_("expected comma after name \"%s\""), name
);
2745 ignore_rest_of_line ();
2749 input_line_pointer
++;
2752 if (name
[0] == '.' && name
[1] == '\0')
2754 /* XXX - this should not happen to .thumb_set. */
2758 if ((symbolP
= symbol_find (name
)) == NULL
2759 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2762 /* When doing symbol listings, play games with dummy fragments living
2763 outside the normal fragment chain to record the file and line info
2765 if (listing
& LISTING_SYMBOLS
)
2767 extern struct list_info_struct
* listing_tail
;
2768 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2770 memset (dummy_frag
, 0, sizeof (fragS
));
2771 dummy_frag
->fr_type
= rs_fill
;
2772 dummy_frag
->line
= listing_tail
;
2773 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2774 dummy_frag
->fr_symbol
= symbolP
;
2778 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2781 /* "set" symbols are local unless otherwise specified. */
2782 SF_SET_LOCAL (symbolP
);
2783 #endif /* OBJ_COFF */
2784 } /* Make a new symbol. */
2786 symbol_table_insert (symbolP
);
2791 && S_IS_DEFINED (symbolP
)
2792 && S_GET_SEGMENT (symbolP
) != reg_section
)
2793 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2795 pseudo_set (symbolP
);
2797 demand_empty_rest_of_line ();
2799 /* XXX Now we come to the Thumb specific bit of code. */
2801 THUMB_SET_FUNC (symbolP
, 1);
2802 ARM_SET_THUMB (symbolP
, 1);
2803 #if defined OBJ_ELF || defined OBJ_COFF
2804 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2808 /* Directives: Mode selection. */
2810 /* .syntax [unified|divided] - choose the new unified syntax
2811 (same for Arm and Thumb encoding, modulo slight differences in what
2812 can be represented) or the old divergent syntax for each mode. */
2814 s_syntax (int unused ATTRIBUTE_UNUSED
)
2818 name
= input_line_pointer
;
2819 delim
= get_symbol_end ();
2821 if (!strcasecmp (name
, "unified"))
2822 unified_syntax
= TRUE
;
2823 else if (!strcasecmp (name
, "divided"))
2824 unified_syntax
= FALSE
;
2827 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2830 *input_line_pointer
= delim
;
2831 demand_empty_rest_of_line ();
2834 /* Directives: sectioning and alignment. */
2836 /* Same as s_align_ptwo but align 0 => align 2. */
2839 s_align (int unused ATTRIBUTE_UNUSED
)
2844 long max_alignment
= 15;
2846 temp
= get_absolute_expression ();
2847 if (temp
> max_alignment
)
2848 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2851 as_bad (_("alignment negative. 0 assumed."));
2855 if (*input_line_pointer
== ',')
2857 input_line_pointer
++;
2858 temp_fill
= get_absolute_expression ();
2870 /* Only make a frag if we HAVE to. */
2871 if (temp
&& !need_pass_2
)
2873 if (!fill_p
&& subseg_text_p (now_seg
))
2874 frag_align_code (temp
, 0);
2876 frag_align (temp
, (int) temp_fill
, 0);
2878 demand_empty_rest_of_line ();
2880 record_alignment (now_seg
, temp
);
2884 s_bss (int ignore ATTRIBUTE_UNUSED
)
2886 /* We don't support putting frags in the BSS segment, we fake it by
2887 marking in_bss, then looking at s_skip for clues. */
2888 subseg_set (bss_section
, 0);
2889 demand_empty_rest_of_line ();
2891 #ifdef md_elf_section_change_hook
2892 md_elf_section_change_hook ();
2897 s_even (int ignore ATTRIBUTE_UNUSED
)
2899 /* Never make frag if expect extra pass. */
2901 frag_align (1, 0, 0);
2903 record_alignment (now_seg
, 1);
2905 demand_empty_rest_of_line ();
2908 /* Directives: Literal pools. */
2910 static literal_pool
*
2911 find_literal_pool (void)
2913 literal_pool
* pool
;
2915 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2917 if (pool
->section
== now_seg
2918 && pool
->sub_section
== now_subseg
)
2925 static literal_pool
*
2926 find_or_make_literal_pool (void)
2928 /* Next literal pool ID number. */
2929 static unsigned int latest_pool_num
= 1;
2930 literal_pool
* pool
;
2932 pool
= find_literal_pool ();
2936 /* Create a new pool. */
2937 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2941 pool
->next_free_entry
= 0;
2942 pool
->section
= now_seg
;
2943 pool
->sub_section
= now_subseg
;
2944 pool
->next
= list_of_pools
;
2945 pool
->symbol
= NULL
;
2947 /* Add it to the list. */
2948 list_of_pools
= pool
;
2951 /* New pools, and emptied pools, will have a NULL symbol. */
2952 if (pool
->symbol
== NULL
)
2954 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2955 (valueT
) 0, &zero_address_frag
);
2956 pool
->id
= latest_pool_num
++;
2963 /* Add the literal in the global 'inst'
2964 structure to the relevant literal pool. */
2967 add_to_lit_pool (void)
2969 literal_pool
* pool
;
2972 pool
= find_or_make_literal_pool ();
2974 /* Check if this literal value is already in the pool. */
2975 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2977 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2978 && (inst
.reloc
.exp
.X_op
== O_constant
)
2979 && (pool
->literals
[entry
].X_add_number
2980 == inst
.reloc
.exp
.X_add_number
)
2981 && (pool
->literals
[entry
].X_unsigned
2982 == inst
.reloc
.exp
.X_unsigned
))
2985 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2986 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2987 && (pool
->literals
[entry
].X_add_number
2988 == inst
.reloc
.exp
.X_add_number
)
2989 && (pool
->literals
[entry
].X_add_symbol
2990 == inst
.reloc
.exp
.X_add_symbol
)
2991 && (pool
->literals
[entry
].X_op_symbol
2992 == inst
.reloc
.exp
.X_op_symbol
))
2996 /* Do we need to create a new entry? */
2997 if (entry
== pool
->next_free_entry
)
2999 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3001 inst
.error
= _("literal pool overflow");
3005 pool
->literals
[entry
] = inst
.reloc
.exp
;
3006 pool
->next_free_entry
+= 1;
3009 inst
.reloc
.exp
.X_op
= O_symbol
;
3010 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3011 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3016 /* Can't use symbol_new here, so have to create a symbol and then at
3017 a later date assign it a value. Thats what these functions do. */
3020 symbol_locate (symbolS
* symbolP
,
3021 const char * name
, /* It is copied, the caller can modify. */
3022 segT segment
, /* Segment identifier (SEG_<something>). */
3023 valueT valu
, /* Symbol value. */
3024 fragS
* frag
) /* Associated fragment. */
3026 unsigned int name_length
;
3027 char * preserved_copy_of_name
;
3029 name_length
= strlen (name
) + 1; /* +1 for \0. */
3030 obstack_grow (¬es
, name
, name_length
);
3031 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3033 #ifdef tc_canonicalize_symbol_name
3034 preserved_copy_of_name
=
3035 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3038 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3040 S_SET_SEGMENT (symbolP
, segment
);
3041 S_SET_VALUE (symbolP
, valu
);
3042 symbol_clear_list_pointers (symbolP
);
3044 symbol_set_frag (symbolP
, frag
);
3046 /* Link to end of symbol chain. */
3048 extern int symbol_table_frozen
;
3050 if (symbol_table_frozen
)
3054 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3056 obj_symbol_new_hook (symbolP
);
3058 #ifdef tc_symbol_new_hook
3059 tc_symbol_new_hook (symbolP
);
3063 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3064 #endif /* DEBUG_SYMS */
3069 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3072 literal_pool
* pool
;
3075 pool
= find_literal_pool ();
3077 || pool
->symbol
== NULL
3078 || pool
->next_free_entry
== 0)
3081 mapping_state (MAP_DATA
);
3083 /* Align pool as you have word accesses.
3084 Only make a frag if we have to. */
3086 frag_align (2, 0, 0);
3088 record_alignment (now_seg
, 2);
3090 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3092 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3093 (valueT
) frag_now_fix (), frag_now
);
3094 symbol_table_insert (pool
->symbol
);
3096 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3098 #if defined OBJ_COFF || defined OBJ_ELF
3099 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3102 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3103 /* First output the expression in the instruction to the pool. */
3104 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3106 /* Mark the pool as empty. */
3107 pool
->next_free_entry
= 0;
3108 pool
->symbol
= NULL
;
3112 /* Forward declarations for functions below, in the MD interface
3114 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3115 static valueT
create_unwind_entry (int);
3116 static void start_unwind_section (const segT
, int);
3117 static void add_unwind_opcode (valueT
, int);
3118 static void flush_pending_unwind (void);
3120 /* Directives: Data. */
3123 s_arm_elf_cons (int nbytes
)
3127 #ifdef md_flush_pending_output
3128 md_flush_pending_output ();
3131 if (is_it_end_of_statement ())
3133 demand_empty_rest_of_line ();
3137 #ifdef md_cons_align
3138 md_cons_align (nbytes
);
3141 mapping_state (MAP_DATA
);
3145 char *base
= input_line_pointer
;
3149 if (exp
.X_op
!= O_symbol
)
3150 emit_expr (&exp
, (unsigned int) nbytes
);
3153 char *before_reloc
= input_line_pointer
;
3154 reloc
= parse_reloc (&input_line_pointer
);
3157 as_bad (_("unrecognized relocation suffix"));
3158 ignore_rest_of_line ();
3161 else if (reloc
== BFD_RELOC_UNUSED
)
3162 emit_expr (&exp
, (unsigned int) nbytes
);
3165 reloc_howto_type
*howto
= (reloc_howto_type
*)
3166 bfd_reloc_type_lookup (stdoutput
,
3167 (bfd_reloc_code_real_type
) reloc
);
3168 int size
= bfd_get_reloc_size (howto
);
3170 if (reloc
== BFD_RELOC_ARM_PLT32
)
3172 as_bad (_("(plt) is only valid on branch targets"));
3173 reloc
= BFD_RELOC_UNUSED
;
3178 as_bad (_("%s relocations do not fit in %d bytes"),
3179 howto
->name
, nbytes
);
3182 /* We've parsed an expression stopping at O_symbol.
3183 But there may be more expression left now that we
3184 have parsed the relocation marker. Parse it again.
3185 XXX Surely there is a cleaner way to do this. */
3186 char *p
= input_line_pointer
;
3188 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3189 memcpy (save_buf
, base
, input_line_pointer
- base
);
3190 memmove (base
+ (input_line_pointer
- before_reloc
),
3191 base
, before_reloc
- base
);
3193 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3195 memcpy (base
, save_buf
, p
- base
);
3197 offset
= nbytes
- size
;
3198 p
= frag_more ((int) nbytes
);
3199 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3200 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3205 while (*input_line_pointer
++ == ',');
3207 /* Put terminator back into stream. */
3208 input_line_pointer
--;
3209 demand_empty_rest_of_line ();
3212 /* Emit an expression containing a 32-bit thumb instruction.
3213 Implementation based on put_thumb32_insn. */
3216 emit_thumb32_expr (expressionS
* exp
)
3218 expressionS exp_high
= *exp
;
3220 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3221 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3222 exp
->X_add_number
&= 0xffff;
3223 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3226 /* Guess the instruction size based on the opcode. */
3229 thumb_insn_size (int opcode
)
3231 if ((unsigned int) opcode
< 0xe800u
)
3233 else if ((unsigned int) opcode
>= 0xe8000000u
)
3240 emit_insn (expressionS
*exp
, int nbytes
)
3244 if (exp
->X_op
== O_constant
)
3249 size
= thumb_insn_size (exp
->X_add_number
);
3253 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3255 as_bad (_(".inst.n operand too big. "\
3256 "Use .inst.w instead"));
3261 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3262 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3264 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3266 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3267 emit_thumb32_expr (exp
);
3269 emit_expr (exp
, (unsigned int) size
);
3271 it_fsm_post_encode ();
3275 as_bad (_("cannot determine Thumb instruction size. " \
3276 "Use .inst.n/.inst.w instead"));
3279 as_bad (_("constant expression required"));
3284 /* Like s_arm_elf_cons but do not use md_cons_align and
3285 set the mapping state to MAP_ARM/MAP_THUMB. */
3288 s_arm_elf_inst (int nbytes
)
3290 if (is_it_end_of_statement ())
3292 demand_empty_rest_of_line ();
3296 /* Calling mapping_state () here will not change ARM/THUMB,
3297 but will ensure not to be in DATA state. */
3300 mapping_state (MAP_THUMB
);
3305 as_bad (_("width suffixes are invalid in ARM mode"));
3306 ignore_rest_of_line ();
3312 mapping_state (MAP_ARM
);
3321 if (! emit_insn (& exp
, nbytes
))
3323 ignore_rest_of_line ();
3327 while (*input_line_pointer
++ == ',');
3329 /* Put terminator back into stream. */
3330 input_line_pointer
--;
3331 demand_empty_rest_of_line ();
3334 /* Parse a .rel31 directive. */
3337 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3344 if (*input_line_pointer
== '1')
3345 highbit
= 0x80000000;
3346 else if (*input_line_pointer
!= '0')
3347 as_bad (_("expected 0 or 1"));
3349 input_line_pointer
++;
3350 if (*input_line_pointer
!= ',')
3351 as_bad (_("missing comma"));
3352 input_line_pointer
++;
3354 #ifdef md_flush_pending_output
3355 md_flush_pending_output ();
3358 #ifdef md_cons_align
3362 mapping_state (MAP_DATA
);
3367 md_number_to_chars (p
, highbit
, 4);
3368 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3369 BFD_RELOC_ARM_PREL31
);
3371 demand_empty_rest_of_line ();
3374 /* Directives: AEABI stack-unwind tables. */
3376 /* Parse an unwind_fnstart directive. Simply records the current location. */
3379 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3381 demand_empty_rest_of_line ();
3382 if (unwind
.proc_start
)
3384 as_bad (_("duplicate .fnstart directive"));
3388 /* Mark the start of the function. */
3389 unwind
.proc_start
= expr_build_dot ();
3391 /* Reset the rest of the unwind info. */
3392 unwind
.opcode_count
= 0;
3393 unwind
.table_entry
= NULL
;
3394 unwind
.personality_routine
= NULL
;
3395 unwind
.personality_index
= -1;
3396 unwind
.frame_size
= 0;
3397 unwind
.fp_offset
= 0;
3398 unwind
.fp_reg
= REG_SP
;
3400 unwind
.sp_restored
= 0;
3404 /* Parse a handlerdata directive. Creates the exception handling table entry
3405 for the function. */
3408 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3410 demand_empty_rest_of_line ();
3411 if (!unwind
.proc_start
)
3412 as_bad (MISSING_FNSTART
);
3414 if (unwind
.table_entry
)
3415 as_bad (_("duplicate .handlerdata directive"));
3417 create_unwind_entry (1);
3420 /* Parse an unwind_fnend directive. Generates the index table entry. */
3423 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3428 unsigned int marked_pr_dependency
;
3430 demand_empty_rest_of_line ();
3432 if (!unwind
.proc_start
)
3434 as_bad (_(".fnend directive without .fnstart"));
3438 /* Add eh table entry. */
3439 if (unwind
.table_entry
== NULL
)
3440 val
= create_unwind_entry (0);
3444 /* Add index table entry. This is two words. */
3445 start_unwind_section (unwind
.saved_seg
, 1);
3446 frag_align (2, 0, 0);
3447 record_alignment (now_seg
, 2);
3449 ptr
= frag_more (8);
3450 where
= frag_now_fix () - 8;
3452 /* Self relative offset of the function start. */
3453 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3454 BFD_RELOC_ARM_PREL31
);
3456 /* Indicate dependency on EHABI-defined personality routines to the
3457 linker, if it hasn't been done already. */
3458 marked_pr_dependency
3459 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3460 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3461 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3463 static const char *const name
[] =
3465 "__aeabi_unwind_cpp_pr0",
3466 "__aeabi_unwind_cpp_pr1",
3467 "__aeabi_unwind_cpp_pr2"
3469 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3470 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3471 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3472 |= 1 << unwind
.personality_index
;
3476 /* Inline exception table entry. */
3477 md_number_to_chars (ptr
+ 4, val
, 4);
3479 /* Self relative offset of the table entry. */
3480 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3481 BFD_RELOC_ARM_PREL31
);
3483 /* Restore the original section. */
3484 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3486 unwind
.proc_start
= NULL
;
3490 /* Parse an unwind_cantunwind directive. */
3493 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3495 demand_empty_rest_of_line ();
3496 if (!unwind
.proc_start
)
3497 as_bad (MISSING_FNSTART
);
3499 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3500 as_bad (_("personality routine specified for cantunwind frame"));
3502 unwind
.personality_index
= -2;
3506 /* Parse a personalityindex directive. */
3509 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3513 if (!unwind
.proc_start
)
3514 as_bad (MISSING_FNSTART
);
3516 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3517 as_bad (_("duplicate .personalityindex directive"));
3521 if (exp
.X_op
!= O_constant
3522 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3524 as_bad (_("bad personality routine number"));
3525 ignore_rest_of_line ();
3529 unwind
.personality_index
= exp
.X_add_number
;
3531 demand_empty_rest_of_line ();
3535 /* Parse a personality directive. */
3538 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3542 if (!unwind
.proc_start
)
3543 as_bad (MISSING_FNSTART
);
3545 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3546 as_bad (_("duplicate .personality directive"));
3548 name
= input_line_pointer
;
3549 c
= get_symbol_end ();
3550 p
= input_line_pointer
;
3551 unwind
.personality_routine
= symbol_find_or_make (name
);
3553 demand_empty_rest_of_line ();
3557 /* Parse a directive saving core registers. */
3560 s_arm_unwind_save_core (void)
3566 range
= parse_reg_list (&input_line_pointer
);
3569 as_bad (_("expected register list"));
3570 ignore_rest_of_line ();
3574 demand_empty_rest_of_line ();
3576 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3577 into .unwind_save {..., sp...}. We aren't bothered about the value of
3578 ip because it is clobbered by calls. */
3579 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3580 && (range
& 0x3000) == 0x1000)
3582 unwind
.opcode_count
--;
3583 unwind
.sp_restored
= 0;
3584 range
= (range
| 0x2000) & ~0x1000;
3585 unwind
.pending_offset
= 0;
3591 /* See if we can use the short opcodes. These pop a block of up to 8
3592 registers starting with r4, plus maybe r14. */
3593 for (n
= 0; n
< 8; n
++)
3595 /* Break at the first non-saved register. */
3596 if ((range
& (1 << (n
+ 4))) == 0)
3599 /* See if there are any other bits set. */
3600 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3602 /* Use the long form. */
3603 op
= 0x8000 | ((range
>> 4) & 0xfff);
3604 add_unwind_opcode (op
, 2);
3608 /* Use the short form. */
3610 op
= 0xa8; /* Pop r14. */
3612 op
= 0xa0; /* Do not pop r14. */
3614 add_unwind_opcode (op
, 1);
3621 op
= 0xb100 | (range
& 0xf);
3622 add_unwind_opcode (op
, 2);
3625 /* Record the number of bytes pushed. */
3626 for (n
= 0; n
< 16; n
++)
3628 if (range
& (1 << n
))
3629 unwind
.frame_size
+= 4;
3634 /* Parse a directive saving FPA registers. */
3637 s_arm_unwind_save_fpa (int reg
)
3643 /* Get Number of registers to transfer. */
3644 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3647 exp
.X_op
= O_illegal
;
3649 if (exp
.X_op
!= O_constant
)
3651 as_bad (_("expected , <constant>"));
3652 ignore_rest_of_line ();
3656 num_regs
= exp
.X_add_number
;
3658 if (num_regs
< 1 || num_regs
> 4)
3660 as_bad (_("number of registers must be in the range [1:4]"));
3661 ignore_rest_of_line ();
3665 demand_empty_rest_of_line ();
3670 op
= 0xb4 | (num_regs
- 1);
3671 add_unwind_opcode (op
, 1);
3676 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3677 add_unwind_opcode (op
, 2);
3679 unwind
.frame_size
+= num_regs
* 12;
3683 /* Parse a directive saving VFP registers for ARMv6 and above. */
3686 s_arm_unwind_save_vfp_armv6 (void)
3691 int num_vfpv3_regs
= 0;
3692 int num_regs_below_16
;
3694 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3697 as_bad (_("expected register list"));
3698 ignore_rest_of_line ();
3702 demand_empty_rest_of_line ();
3704 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3705 than FSTMX/FLDMX-style ones). */
3707 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3709 num_vfpv3_regs
= count
;
3710 else if (start
+ count
> 16)
3711 num_vfpv3_regs
= start
+ count
- 16;
3713 if (num_vfpv3_regs
> 0)
3715 int start_offset
= start
> 16 ? start
- 16 : 0;
3716 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3717 add_unwind_opcode (op
, 2);
3720 /* Generate opcode for registers numbered in the range 0 .. 15. */
3721 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3722 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3723 if (num_regs_below_16
> 0)
3725 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3726 add_unwind_opcode (op
, 2);
3729 unwind
.frame_size
+= count
* 8;
3733 /* Parse a directive saving VFP registers for pre-ARMv6. */
3736 s_arm_unwind_save_vfp (void)
3742 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3745 as_bad (_("expected register list"));
3746 ignore_rest_of_line ();
3750 demand_empty_rest_of_line ();
3755 op
= 0xb8 | (count
- 1);
3756 add_unwind_opcode (op
, 1);
3761 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3762 add_unwind_opcode (op
, 2);
3764 unwind
.frame_size
+= count
* 8 + 4;
3768 /* Parse a directive saving iWMMXt data registers. */
3771 s_arm_unwind_save_mmxwr (void)
3779 if (*input_line_pointer
== '{')
3780 input_line_pointer
++;
3784 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3788 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3793 as_tsktsk (_("register list not in ascending order"));
3796 if (*input_line_pointer
== '-')
3798 input_line_pointer
++;
3799 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3802 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3805 else if (reg
>= hi_reg
)
3807 as_bad (_("bad register range"));
3810 for (; reg
< hi_reg
; reg
++)
3814 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3816 if (*input_line_pointer
== '}')
3817 input_line_pointer
++;
3819 demand_empty_rest_of_line ();
3821 /* Generate any deferred opcodes because we're going to be looking at
3823 flush_pending_unwind ();
3825 for (i
= 0; i
< 16; i
++)
3827 if (mask
& (1 << i
))
3828 unwind
.frame_size
+= 8;
3831 /* Attempt to combine with a previous opcode. We do this because gcc
3832 likes to output separate unwind directives for a single block of
3834 if (unwind
.opcode_count
> 0)
3836 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3837 if ((i
& 0xf8) == 0xc0)
3840 /* Only merge if the blocks are contiguous. */
3843 if ((mask
& 0xfe00) == (1 << 9))
3845 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3846 unwind
.opcode_count
--;
3849 else if (i
== 6 && unwind
.opcode_count
>= 2)
3851 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3855 op
= 0xffff << (reg
- 1);
3857 && ((mask
& op
) == (1u << (reg
- 1))))
3859 op
= (1 << (reg
+ i
+ 1)) - 1;
3860 op
&= ~((1 << reg
) - 1);
3862 unwind
.opcode_count
-= 2;
3869 /* We want to generate opcodes in the order the registers have been
3870 saved, ie. descending order. */
3871 for (reg
= 15; reg
>= -1; reg
--)
3873 /* Save registers in blocks. */
3875 || !(mask
& (1 << reg
)))
3877 /* We found an unsaved reg. Generate opcodes to save the
3884 op
= 0xc0 | (hi_reg
- 10);
3885 add_unwind_opcode (op
, 1);
3890 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3891 add_unwind_opcode (op
, 2);
3900 ignore_rest_of_line ();
3904 s_arm_unwind_save_mmxwcg (void)
3911 if (*input_line_pointer
== '{')
3912 input_line_pointer
++;
3916 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3920 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3926 as_tsktsk (_("register list not in ascending order"));
3929 if (*input_line_pointer
== '-')
3931 input_line_pointer
++;
3932 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3935 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3938 else if (reg
>= hi_reg
)
3940 as_bad (_("bad register range"));
3943 for (; reg
< hi_reg
; reg
++)
3947 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3949 if (*input_line_pointer
== '}')
3950 input_line_pointer
++;
3952 demand_empty_rest_of_line ();
3954 /* Generate any deferred opcodes because we're going to be looking at
3956 flush_pending_unwind ();
3958 for (reg
= 0; reg
< 16; reg
++)
3960 if (mask
& (1 << reg
))
3961 unwind
.frame_size
+= 4;
3964 add_unwind_opcode (op
, 2);
3967 ignore_rest_of_line ();
3971 /* Parse an unwind_save directive.
3972 If the argument is non-zero, this is a .vsave directive. */
3975 s_arm_unwind_save (int arch_v6
)
3978 struct reg_entry
*reg
;
3979 bfd_boolean had_brace
= FALSE
;
3981 if (!unwind
.proc_start
)
3982 as_bad (MISSING_FNSTART
);
3984 /* Figure out what sort of save we have. */
3985 peek
= input_line_pointer
;
3993 reg
= arm_reg_parse_multi (&peek
);
3997 as_bad (_("register expected"));
3998 ignore_rest_of_line ();
4007 as_bad (_("FPA .unwind_save does not take a register list"));
4008 ignore_rest_of_line ();
4011 input_line_pointer
= peek
;
4012 s_arm_unwind_save_fpa (reg
->number
);
4015 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4018 s_arm_unwind_save_vfp_armv6 ();
4020 s_arm_unwind_save_vfp ();
4022 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4023 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4026 as_bad (_(".unwind_save does not support this kind of register"));
4027 ignore_rest_of_line ();
4032 /* Parse an unwind_movsp directive. */
4035 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4041 if (!unwind
.proc_start
)
4042 as_bad (MISSING_FNSTART
);
4044 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4047 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4048 ignore_rest_of_line ();
4052 /* Optional constant. */
4053 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4055 if (immediate_for_directive (&offset
) == FAIL
)
4061 demand_empty_rest_of_line ();
4063 if (reg
== REG_SP
|| reg
== REG_PC
)
4065 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4069 if (unwind
.fp_reg
!= REG_SP
)
4070 as_bad (_("unexpected .unwind_movsp directive"));
4072 /* Generate opcode to restore the value. */
4074 add_unwind_opcode (op
, 1);
4076 /* Record the information for later. */
4077 unwind
.fp_reg
= reg
;
4078 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4079 unwind
.sp_restored
= 1;
4082 /* Parse an unwind_pad directive. */
4085 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4089 if (!unwind
.proc_start
)
4090 as_bad (MISSING_FNSTART
);
4092 if (immediate_for_directive (&offset
) == FAIL
)
4097 as_bad (_("stack increment must be multiple of 4"));
4098 ignore_rest_of_line ();
4102 /* Don't generate any opcodes, just record the details for later. */
4103 unwind
.frame_size
+= offset
;
4104 unwind
.pending_offset
+= offset
;
4106 demand_empty_rest_of_line ();
4109 /* Parse an unwind_setfp directive. */
4112 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4118 if (!unwind
.proc_start
)
4119 as_bad (MISSING_FNSTART
);
4121 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4122 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4125 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4127 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4129 as_bad (_("expected <reg>, <reg>"));
4130 ignore_rest_of_line ();
4134 /* Optional constant. */
4135 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4137 if (immediate_for_directive (&offset
) == FAIL
)
4143 demand_empty_rest_of_line ();
4145 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4147 as_bad (_("register must be either sp or set by a previous"
4148 "unwind_movsp directive"));
4152 /* Don't generate any opcodes, just record the information for later. */
4153 unwind
.fp_reg
= fp_reg
;
4155 if (sp_reg
== REG_SP
)
4156 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4158 unwind
.fp_offset
-= offset
;
4161 /* Parse an unwind_raw directive. */
4164 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4167 /* This is an arbitrary limit. */
4168 unsigned char op
[16];
4171 if (!unwind
.proc_start
)
4172 as_bad (MISSING_FNSTART
);
4175 if (exp
.X_op
== O_constant
4176 && skip_past_comma (&input_line_pointer
) != FAIL
)
4178 unwind
.frame_size
+= exp
.X_add_number
;
4182 exp
.X_op
= O_illegal
;
4184 if (exp
.X_op
!= O_constant
)
4186 as_bad (_("expected <offset>, <opcode>"));
4187 ignore_rest_of_line ();
4193 /* Parse the opcode. */
4198 as_bad (_("unwind opcode too long"));
4199 ignore_rest_of_line ();
4201 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4203 as_bad (_("invalid unwind opcode"));
4204 ignore_rest_of_line ();
4207 op
[count
++] = exp
.X_add_number
;
4209 /* Parse the next byte. */
4210 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4216 /* Add the opcode bytes in reverse order. */
4218 add_unwind_opcode (op
[count
], 1);
4220 demand_empty_rest_of_line ();
4224 /* Parse a .eabi_attribute directive. */
4227 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4229 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4231 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4232 attributes_set_explicitly
[tag
] = 1;
4234 #endif /* OBJ_ELF */
4236 static void s_arm_arch (int);
4237 static void s_arm_object_arch (int);
4238 static void s_arm_cpu (int);
4239 static void s_arm_fpu (int);
4244 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4251 if (exp
.X_op
== O_symbol
)
4252 exp
.X_op
= O_secrel
;
4254 emit_expr (&exp
, 4);
4256 while (*input_line_pointer
++ == ',');
4258 input_line_pointer
--;
4259 demand_empty_rest_of_line ();
4263 /* This table describes all the machine specific pseudo-ops the assembler
4264 has to support. The fields are:
4265 pseudo-op name without dot
4266 function to call to execute this pseudo-op
4267 Integer arg to pass to the function. */
4269 const pseudo_typeS md_pseudo_table
[] =
4271 /* Never called because '.req' does not start a line. */
4272 { "req", s_req
, 0 },
4273 /* Following two are likewise never called. */
4276 { "unreq", s_unreq
, 0 },
4277 { "bss", s_bss
, 0 },
4278 { "align", s_align
, 0 },
4279 { "arm", s_arm
, 0 },
4280 { "thumb", s_thumb
, 0 },
4281 { "code", s_code
, 0 },
4282 { "force_thumb", s_force_thumb
, 0 },
4283 { "thumb_func", s_thumb_func
, 0 },
4284 { "thumb_set", s_thumb_set
, 0 },
4285 { "even", s_even
, 0 },
4286 { "ltorg", s_ltorg
, 0 },
4287 { "pool", s_ltorg
, 0 },
4288 { "syntax", s_syntax
, 0 },
4289 { "cpu", s_arm_cpu
, 0 },
4290 { "arch", s_arm_arch
, 0 },
4291 { "object_arch", s_arm_object_arch
, 0 },
4292 { "fpu", s_arm_fpu
, 0 },
4294 { "word", s_arm_elf_cons
, 4 },
4295 { "long", s_arm_elf_cons
, 4 },
4296 { "inst.n", s_arm_elf_inst
, 2 },
4297 { "inst.w", s_arm_elf_inst
, 4 },
4298 { "inst", s_arm_elf_inst
, 0 },
4299 { "rel31", s_arm_rel31
, 0 },
4300 { "fnstart", s_arm_unwind_fnstart
, 0 },
4301 { "fnend", s_arm_unwind_fnend
, 0 },
4302 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4303 { "personality", s_arm_unwind_personality
, 0 },
4304 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4305 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4306 { "save", s_arm_unwind_save
, 0 },
4307 { "vsave", s_arm_unwind_save
, 1 },
4308 { "movsp", s_arm_unwind_movsp
, 0 },
4309 { "pad", s_arm_unwind_pad
, 0 },
4310 { "setfp", s_arm_unwind_setfp
, 0 },
4311 { "unwind_raw", s_arm_unwind_raw
, 0 },
4312 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4316 /* These are used for dwarf. */
4320 /* These are used for dwarf2. */
4321 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4322 { "loc", dwarf2_directive_loc
, 0 },
4323 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4325 { "extend", float_cons
, 'x' },
4326 { "ldouble", float_cons
, 'x' },
4327 { "packed", float_cons
, 'p' },
4329 {"secrel32", pe_directive_secrel
, 0},
4334 /* Parser functions used exclusively in instruction operands. */
4336 /* Generic immediate-value read function for use in insn parsing.
4337 STR points to the beginning of the immediate (the leading #);
4338 VAL receives the value; if the value is outside [MIN, MAX]
4339 issue an error. PREFIX_OPT is true if the immediate prefix is
4343 parse_immediate (char **str
, int *val
, int min
, int max
,
4344 bfd_boolean prefix_opt
)
4347 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4348 if (exp
.X_op
!= O_constant
)
4350 inst
.error
= _("constant expression required");
4354 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4356 inst
.error
= _("immediate value out of range");
4360 *val
= exp
.X_add_number
;
4364 /* Less-generic immediate-value read function with the possibility of loading a
4365 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4366 instructions. Puts the result directly in inst.operands[i]. */
4369 parse_big_immediate (char **str
, int i
)
4374 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4376 if (exp
.X_op
== O_constant
)
4378 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4379 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4380 O_constant. We have to be careful not to break compilation for
4381 32-bit X_add_number, though. */
4382 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4384 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4385 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4386 inst
.operands
[i
].regisimm
= 1;
4389 else if (exp
.X_op
== O_big
4390 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4391 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4393 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4394 /* Bignums have their least significant bits in
4395 generic_bignum[0]. Make sure we put 32 bits in imm and
4396 32 bits in reg, in a (hopefully) portable way. */
4397 gas_assert (parts
!= 0);
4398 inst
.operands
[i
].imm
= 0;
4399 for (j
= 0; j
< parts
; j
++, idx
++)
4400 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4401 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4402 inst
.operands
[i
].reg
= 0;
4403 for (j
= 0; j
< parts
; j
++, idx
++)
4404 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4405 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4406 inst
.operands
[i
].regisimm
= 1;
4416 /* Returns the pseudo-register number of an FPA immediate constant,
4417 or FAIL if there isn't a valid constant here. */
4420 parse_fpa_immediate (char ** str
)
4422 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4428 /* First try and match exact strings, this is to guarantee
4429 that some formats will work even for cross assembly. */
4431 for (i
= 0; fp_const
[i
]; i
++)
4433 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4437 *str
+= strlen (fp_const
[i
]);
4438 if (is_end_of_line
[(unsigned char) **str
])
4444 /* Just because we didn't get a match doesn't mean that the constant
4445 isn't valid, just that it is in a format that we don't
4446 automatically recognize. Try parsing it with the standard
4447 expression routines. */
4449 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4451 /* Look for a raw floating point number. */
4452 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4453 && is_end_of_line
[(unsigned char) *save_in
])
4455 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4457 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4459 if (words
[j
] != fp_values
[i
][j
])
4463 if (j
== MAX_LITTLENUMS
)
4471 /* Try and parse a more complex expression, this will probably fail
4472 unless the code uses a floating point prefix (eg "0f"). */
4473 save_in
= input_line_pointer
;
4474 input_line_pointer
= *str
;
4475 if (expression (&exp
) == absolute_section
4476 && exp
.X_op
== O_big
4477 && exp
.X_add_number
< 0)
4479 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4481 if (gen_to_words (words
, 5, (long) 15) == 0)
4483 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4485 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4487 if (words
[j
] != fp_values
[i
][j
])
4491 if (j
== MAX_LITTLENUMS
)
4493 *str
= input_line_pointer
;
4494 input_line_pointer
= save_in
;
4501 *str
= input_line_pointer
;
4502 input_line_pointer
= save_in
;
4503 inst
.error
= _("invalid FPA immediate expression");
4507 /* Returns 1 if a number has "quarter-precision" float format
4508 0baBbbbbbc defgh000 00000000 00000000. */
4511 is_quarter_float (unsigned imm
)
4513 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4514 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4517 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4518 0baBbbbbbc defgh000 00000000 00000000.
4519 The zero and minus-zero cases need special handling, since they can't be
4520 encoded in the "quarter-precision" float format, but can nonetheless be
4521 loaded as integer constants. */
4524 parse_qfloat_immediate (char **ccp
, int *immed
)
4528 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4529 int found_fpchar
= 0;
4531 skip_past_char (&str
, '#');
4533 /* We must not accidentally parse an integer as a floating-point number. Make
4534 sure that the value we parse is not an integer by checking for special
4535 characters '.' or 'e'.
4536 FIXME: This is a horrible hack, but doing better is tricky because type
4537 information isn't in a very usable state at parse time. */
4539 skip_whitespace (fpnum
);
4541 if (strncmp (fpnum
, "0x", 2) == 0)
4545 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4546 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4556 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4558 unsigned fpword
= 0;
4561 /* Our FP word must be 32 bits (single-precision FP). */
4562 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4564 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4568 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4581 /* Shift operands. */
4584 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4587 struct asm_shift_name
4590 enum shift_kind kind
;
4593 /* Third argument to parse_shift. */
4594 enum parse_shift_mode
4596 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4597 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4598 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4599 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4600 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4603 /* Parse a <shift> specifier on an ARM data processing instruction.
4604 This has three forms:
4606 (LSL|LSR|ASL|ASR|ROR) Rs
4607 (LSL|LSR|ASL|ASR|ROR) #imm
4610 Note that ASL is assimilated to LSL in the instruction encoding, and
4611 RRX to ROR #0 (which cannot be written as such). */
4614 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4616 const struct asm_shift_name
*shift_name
;
4617 enum shift_kind shift
;
4622 for (p
= *str
; ISALPHA (*p
); p
++)
4627 inst
.error
= _("shift expression expected");
4631 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4634 if (shift_name
== NULL
)
4636 inst
.error
= _("shift expression expected");
4640 shift
= shift_name
->kind
;
4644 case NO_SHIFT_RESTRICT
:
4645 case SHIFT_IMMEDIATE
: break;
4647 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4648 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4650 inst
.error
= _("'LSL' or 'ASR' required");
4655 case SHIFT_LSL_IMMEDIATE
:
4656 if (shift
!= SHIFT_LSL
)
4658 inst
.error
= _("'LSL' required");
4663 case SHIFT_ASR_IMMEDIATE
:
4664 if (shift
!= SHIFT_ASR
)
4666 inst
.error
= _("'ASR' required");
4674 if (shift
!= SHIFT_RRX
)
4676 /* Whitespace can appear here if the next thing is a bare digit. */
4677 skip_whitespace (p
);
4679 if (mode
== NO_SHIFT_RESTRICT
4680 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4682 inst
.operands
[i
].imm
= reg
;
4683 inst
.operands
[i
].immisreg
= 1;
4685 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4688 inst
.operands
[i
].shift_kind
= shift
;
4689 inst
.operands
[i
].shifted
= 1;
4694 /* Parse a <shifter_operand> for an ARM data processing instruction:
4697 #<immediate>, <rotate>
4701 where <shift> is defined by parse_shift above, and <rotate> is a
4702 multiple of 2 between 0 and 30. Validation of immediate operands
4703 is deferred to md_apply_fix. */
4706 parse_shifter_operand (char **str
, int i
)
4711 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4713 inst
.operands
[i
].reg
= value
;
4714 inst
.operands
[i
].isreg
= 1;
4716 /* parse_shift will override this if appropriate */
4717 inst
.reloc
.exp
.X_op
= O_constant
;
4718 inst
.reloc
.exp
.X_add_number
= 0;
4720 if (skip_past_comma (str
) == FAIL
)
4723 /* Shift operation on register. */
4724 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4727 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4730 if (skip_past_comma (str
) == SUCCESS
)
4732 /* #x, y -- ie explicit rotation by Y. */
4733 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4736 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4738 inst
.error
= _("constant expression expected");
4742 value
= expr
.X_add_number
;
4743 if (value
< 0 || value
> 30 || value
% 2 != 0)
4745 inst
.error
= _("invalid rotation");
4748 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4750 inst
.error
= _("invalid constant");
4754 /* Convert to decoded value. md_apply_fix will put it back. */
4755 inst
.reloc
.exp
.X_add_number
4756 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4757 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4760 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4761 inst
.reloc
.pc_rel
= 0;
4765 /* Group relocation information. Each entry in the table contains the
4766 textual name of the relocation as may appear in assembler source
4767 and must end with a colon.
4768 Along with this textual name are the relocation codes to be used if
4769 the corresponding instruction is an ALU instruction (ADD or SUB only),
4770 an LDR, an LDRS, or an LDC. */
4772 struct group_reloc_table_entry
4783 /* Varieties of non-ALU group relocation. */
4790 static struct group_reloc_table_entry group_reloc_table
[] =
4791 { /* Program counter relative: */
4793 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4798 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4799 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4800 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4801 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4803 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4808 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4809 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4810 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4811 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4813 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4814 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4815 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4816 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4817 /* Section base relative */
4819 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4824 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4825 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4826 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4827 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4829 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4834 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4835 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4836 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4837 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4839 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4840 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4841 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4842 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4844 /* Given the address of a pointer pointing to the textual name of a group
4845 relocation as may appear in assembler source, attempt to find its details
4846 in group_reloc_table. The pointer will be updated to the character after
4847 the trailing colon. On failure, FAIL will be returned; SUCCESS
4848 otherwise. On success, *entry will be updated to point at the relevant
4849 group_reloc_table entry. */
4852 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4855 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4857 int length
= strlen (group_reloc_table
[i
].name
);
4859 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4860 && (*str
)[length
] == ':')
4862 *out
= &group_reloc_table
[i
];
4863 *str
+= (length
+ 1);
4871 /* Parse a <shifter_operand> for an ARM data processing instruction
4872 (as for parse_shifter_operand) where group relocations are allowed:
4875 #<immediate>, <rotate>
4876 #:<group_reloc>:<expression>
4880 where <group_reloc> is one of the strings defined in group_reloc_table.
4881 The hashes are optional.
4883 Everything else is as for parse_shifter_operand. */
4885 static parse_operand_result
4886 parse_shifter_operand_group_reloc (char **str
, int i
)
4888 /* Determine if we have the sequence of characters #: or just :
4889 coming next. If we do, then we check for a group relocation.
4890 If we don't, punt the whole lot to parse_shifter_operand. */
4892 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4893 || (*str
)[0] == ':')
4895 struct group_reloc_table_entry
*entry
;
4897 if ((*str
)[0] == '#')
4902 /* Try to parse a group relocation. Anything else is an error. */
4903 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4905 inst
.error
= _("unknown group relocation");
4906 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4909 /* We now have the group relocation table entry corresponding to
4910 the name in the assembler source. Next, we parse the expression. */
4911 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4912 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4914 /* Record the relocation type (always the ALU variant here). */
4915 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4916 gas_assert (inst
.reloc
.type
!= 0);
4918 return PARSE_OPERAND_SUCCESS
;
4921 return parse_shifter_operand (str
, i
) == SUCCESS
4922 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4924 /* Never reached. */
4927 /* Parse all forms of an ARM address expression. Information is written
4928 to inst.operands[i] and/or inst.reloc.
4930 Preindexed addressing (.preind=1):
4932 [Rn, #offset] .reg=Rn .reloc.exp=offset
4933 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4934 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4935 .shift_kind=shift .reloc.exp=shift_imm
4937 These three may have a trailing ! which causes .writeback to be set also.
4939 Postindexed addressing (.postind=1, .writeback=1):
4941 [Rn], #offset .reg=Rn .reloc.exp=offset
4942 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4943 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4944 .shift_kind=shift .reloc.exp=shift_imm
4946 Unindexed addressing (.preind=0, .postind=0):
4948 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4952 [Rn]{!} shorthand for [Rn,#0]{!}
4953 =immediate .isreg=0 .reloc.exp=immediate
4954 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4956 It is the caller's responsibility to check for addressing modes not
4957 supported by the instruction, and to set inst.reloc.type. */
4959 static parse_operand_result
4960 parse_address_main (char **str
, int i
, int group_relocations
,
4961 group_reloc_type group_type
)
4966 if (skip_past_char (&p
, '[') == FAIL
)
4968 if (skip_past_char (&p
, '=') == FAIL
)
4970 /* bare address - translate to PC-relative offset */
4971 inst
.reloc
.pc_rel
= 1;
4972 inst
.operands
[i
].reg
= REG_PC
;
4973 inst
.operands
[i
].isreg
= 1;
4974 inst
.operands
[i
].preind
= 1;
4976 /* else a load-constant pseudo op, no special treatment needed here */
4978 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4979 return PARSE_OPERAND_FAIL
;
4982 return PARSE_OPERAND_SUCCESS
;
4985 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4987 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4988 return PARSE_OPERAND_FAIL
;
4990 inst
.operands
[i
].reg
= reg
;
4991 inst
.operands
[i
].isreg
= 1;
4993 if (skip_past_comma (&p
) == SUCCESS
)
4995 inst
.operands
[i
].preind
= 1;
4998 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5000 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5002 inst
.operands
[i
].imm
= reg
;
5003 inst
.operands
[i
].immisreg
= 1;
5005 if (skip_past_comma (&p
) == SUCCESS
)
5006 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5007 return PARSE_OPERAND_FAIL
;
5009 else if (skip_past_char (&p
, ':') == SUCCESS
)
5011 /* FIXME: '@' should be used here, but it's filtered out by generic
5012 code before we get to see it here. This may be subject to
5015 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5016 if (exp
.X_op
!= O_constant
)
5018 inst
.error
= _("alignment must be constant");
5019 return PARSE_OPERAND_FAIL
;
5021 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5022 inst
.operands
[i
].immisalign
= 1;
5023 /* Alignments are not pre-indexes. */
5024 inst
.operands
[i
].preind
= 0;
5028 if (inst
.operands
[i
].negative
)
5030 inst
.operands
[i
].negative
= 0;
5034 if (group_relocations
5035 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5037 struct group_reloc_table_entry
*entry
;
5039 /* Skip over the #: or : sequence. */
5045 /* Try to parse a group relocation. Anything else is an
5047 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5049 inst
.error
= _("unknown group relocation");
5050 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5053 /* We now have the group relocation table entry corresponding to
5054 the name in the assembler source. Next, we parse the
5056 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5057 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5059 /* Record the relocation type. */
5063 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5067 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5071 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5078 if (inst
.reloc
.type
== 0)
5080 inst
.error
= _("this group relocation is not allowed on this instruction");
5081 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5085 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5086 return PARSE_OPERAND_FAIL
;
5090 if (skip_past_char (&p
, ']') == FAIL
)
5092 inst
.error
= _("']' expected");
5093 return PARSE_OPERAND_FAIL
;
5096 if (skip_past_char (&p
, '!') == SUCCESS
)
5097 inst
.operands
[i
].writeback
= 1;
5099 else if (skip_past_comma (&p
) == SUCCESS
)
5101 if (skip_past_char (&p
, '{') == SUCCESS
)
5103 /* [Rn], {expr} - unindexed, with option */
5104 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5105 0, 255, TRUE
) == FAIL
)
5106 return PARSE_OPERAND_FAIL
;
5108 if (skip_past_char (&p
, '}') == FAIL
)
5110 inst
.error
= _("'}' expected at end of 'option' field");
5111 return PARSE_OPERAND_FAIL
;
5113 if (inst
.operands
[i
].preind
)
5115 inst
.error
= _("cannot combine index with option");
5116 return PARSE_OPERAND_FAIL
;
5119 return PARSE_OPERAND_SUCCESS
;
5123 inst
.operands
[i
].postind
= 1;
5124 inst
.operands
[i
].writeback
= 1;
5126 if (inst
.operands
[i
].preind
)
5128 inst
.error
= _("cannot combine pre- and post-indexing");
5129 return PARSE_OPERAND_FAIL
;
5133 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5135 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5137 /* We might be using the immediate for alignment already. If we
5138 are, OR the register number into the low-order bits. */
5139 if (inst
.operands
[i
].immisalign
)
5140 inst
.operands
[i
].imm
|= reg
;
5142 inst
.operands
[i
].imm
= reg
;
5143 inst
.operands
[i
].immisreg
= 1;
5145 if (skip_past_comma (&p
) == SUCCESS
)
5146 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5147 return PARSE_OPERAND_FAIL
;
5151 if (inst
.operands
[i
].negative
)
5153 inst
.operands
[i
].negative
= 0;
5156 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5157 return PARSE_OPERAND_FAIL
;
5162 /* If at this point neither .preind nor .postind is set, we have a
5163 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5164 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5166 inst
.operands
[i
].preind
= 1;
5167 inst
.reloc
.exp
.X_op
= O_constant
;
5168 inst
.reloc
.exp
.X_add_number
= 0;
5171 return PARSE_OPERAND_SUCCESS
;
5175 parse_address (char **str
, int i
)
5177 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5181 static parse_operand_result
5182 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5184 return parse_address_main (str
, i
, 1, type
);
5187 /* Parse an operand for a MOVW or MOVT instruction. */
5189 parse_half (char **str
)
5194 skip_past_char (&p
, '#');
5195 if (strncasecmp (p
, ":lower16:", 9) == 0)
5196 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5197 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5198 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5200 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5203 skip_whitespace (p
);
5206 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5209 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5211 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5213 inst
.error
= _("constant expression expected");
5216 if (inst
.reloc
.exp
.X_add_number
< 0
5217 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5219 inst
.error
= _("immediate value out of range");
5227 /* Miscellaneous. */
5229 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5230 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5232 parse_psr (char **str
)
5235 unsigned long psr_field
;
5236 const struct asm_psr
*psr
;
5239 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5240 feature for ease of use and backwards compatibility. */
5242 if (strncasecmp (p
, "SPSR", 4) == 0)
5243 psr_field
= SPSR_BIT
;
5244 else if (strncasecmp (p
, "CPSR", 4) == 0)
5251 while (ISALNUM (*p
) || *p
== '_');
5253 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5265 /* A suffix follows. */
5271 while (ISALNUM (*p
) || *p
== '_');
5273 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5278 psr_field
|= psr
->field
;
5283 goto error
; /* Garbage after "[CS]PSR". */
5285 psr_field
|= (PSR_c
| PSR_f
);
5291 inst
.error
= _("flag for {c}psr instruction expected");
5295 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5296 value suitable for splatting into the AIF field of the instruction. */
5299 parse_cps_flags (char **str
)
5308 case '\0': case ',':
5311 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5312 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5313 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5316 inst
.error
= _("unrecognized CPS flag");
5321 if (saw_a_flag
== 0)
5323 inst
.error
= _("missing CPS flags");
5331 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5332 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5335 parse_endian_specifier (char **str
)
5340 if (strncasecmp (s
, "BE", 2))
5342 else if (strncasecmp (s
, "LE", 2))
5346 inst
.error
= _("valid endian specifiers are be or le");
5350 if (ISALNUM (s
[2]) || s
[2] == '_')
5352 inst
.error
= _("valid endian specifiers are be or le");
5357 return little_endian
;
5360 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5361 value suitable for poking into the rotate field of an sxt or sxta
5362 instruction, or FAIL on error. */
5365 parse_ror (char **str
)
5370 if (strncasecmp (s
, "ROR", 3) == 0)
5374 inst
.error
= _("missing rotation field after comma");
5378 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5383 case 0: *str
= s
; return 0x0;
5384 case 8: *str
= s
; return 0x1;
5385 case 16: *str
= s
; return 0x2;
5386 case 24: *str
= s
; return 0x3;
5389 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5394 /* Parse a conditional code (from conds[] below). The value returned is in the
5395 range 0 .. 14, or FAIL. */
5397 parse_cond (char **str
)
5400 const struct asm_cond
*c
;
5402 /* Condition codes are always 2 characters, so matching up to
5403 3 characters is sufficient. */
5408 while (ISALPHA (*q
) && n
< 3)
5410 cond
[n
] = TOLOWER (*q
);
5415 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5418 inst
.error
= _("condition required");
5426 /* Parse an option for a barrier instruction. Returns the encoding for the
5429 parse_barrier (char **str
)
5432 const struct asm_barrier_opt
*o
;
5435 while (ISALPHA (*q
))
5438 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5447 /* Parse the operands of a table branch instruction. Similar to a memory
5450 parse_tb (char **str
)
5455 if (skip_past_char (&p
, '[') == FAIL
)
5457 inst
.error
= _("'[' expected");
5461 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5463 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5466 inst
.operands
[0].reg
= reg
;
5468 if (skip_past_comma (&p
) == FAIL
)
5470 inst
.error
= _("',' expected");
5474 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5476 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5479 inst
.operands
[0].imm
= reg
;
5481 if (skip_past_comma (&p
) == SUCCESS
)
5483 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5485 if (inst
.reloc
.exp
.X_add_number
!= 1)
5487 inst
.error
= _("invalid shift");
5490 inst
.operands
[0].shifted
= 1;
5493 if (skip_past_char (&p
, ']') == FAIL
)
5495 inst
.error
= _("']' expected");
5502 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5503 information on the types the operands can take and how they are encoded.
5504 Up to four operands may be read; this function handles setting the
5505 ".present" field for each read operand itself.
5506 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5507 else returns FAIL. */
5510 parse_neon_mov (char **str
, int *which_operand
)
5512 int i
= *which_operand
, val
;
5513 enum arm_reg_type rtype
;
5515 struct neon_type_el optype
;
5517 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5519 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5520 inst
.operands
[i
].reg
= val
;
5521 inst
.operands
[i
].isscalar
= 1;
5522 inst
.operands
[i
].vectype
= optype
;
5523 inst
.operands
[i
++].present
= 1;
5525 if (skip_past_comma (&ptr
) == FAIL
)
5528 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5531 inst
.operands
[i
].reg
= val
;
5532 inst
.operands
[i
].isreg
= 1;
5533 inst
.operands
[i
].present
= 1;
5535 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5538 /* Cases 0, 1, 2, 3, 5 (D only). */
5539 if (skip_past_comma (&ptr
) == FAIL
)
5542 inst
.operands
[i
].reg
= val
;
5543 inst
.operands
[i
].isreg
= 1;
5544 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5545 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5546 inst
.operands
[i
].isvec
= 1;
5547 inst
.operands
[i
].vectype
= optype
;
5548 inst
.operands
[i
++].present
= 1;
5550 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5552 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5553 Case 13: VMOV <Sd>, <Rm> */
5554 inst
.operands
[i
].reg
= val
;
5555 inst
.operands
[i
].isreg
= 1;
5556 inst
.operands
[i
].present
= 1;
5558 if (rtype
== REG_TYPE_NQ
)
5560 first_error (_("can't use Neon quad register here"));
5563 else if (rtype
!= REG_TYPE_VFS
)
5566 if (skip_past_comma (&ptr
) == FAIL
)
5568 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5570 inst
.operands
[i
].reg
= val
;
5571 inst
.operands
[i
].isreg
= 1;
5572 inst
.operands
[i
].present
= 1;
5575 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5578 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5579 Case 1: VMOV<c><q> <Dd>, <Dm>
5580 Case 8: VMOV.F32 <Sd>, <Sm>
5581 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5583 inst
.operands
[i
].reg
= val
;
5584 inst
.operands
[i
].isreg
= 1;
5585 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5586 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5587 inst
.operands
[i
].isvec
= 1;
5588 inst
.operands
[i
].vectype
= optype
;
5589 inst
.operands
[i
].present
= 1;
5591 if (skip_past_comma (&ptr
) == SUCCESS
)
5596 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5599 inst
.operands
[i
].reg
= val
;
5600 inst
.operands
[i
].isreg
= 1;
5601 inst
.operands
[i
++].present
= 1;
5603 if (skip_past_comma (&ptr
) == FAIL
)
5606 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5609 inst
.operands
[i
].reg
= val
;
5610 inst
.operands
[i
].isreg
= 1;
5611 inst
.operands
[i
++].present
= 1;
5614 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5615 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5616 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5617 Case 10: VMOV.F32 <Sd>, #<imm>
5618 Case 11: VMOV.F64 <Dd>, #<imm> */
5619 inst
.operands
[i
].immisfloat
= 1;
5620 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5621 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5622 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5626 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5630 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5633 inst
.operands
[i
].reg
= val
;
5634 inst
.operands
[i
].isreg
= 1;
5635 inst
.operands
[i
++].present
= 1;
5637 if (skip_past_comma (&ptr
) == FAIL
)
5640 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5642 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5643 inst
.operands
[i
].reg
= val
;
5644 inst
.operands
[i
].isscalar
= 1;
5645 inst
.operands
[i
].present
= 1;
5646 inst
.operands
[i
].vectype
= optype
;
5648 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5650 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5651 inst
.operands
[i
].reg
= val
;
5652 inst
.operands
[i
].isreg
= 1;
5653 inst
.operands
[i
++].present
= 1;
5655 if (skip_past_comma (&ptr
) == FAIL
)
5658 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5661 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5665 inst
.operands
[i
].reg
= val
;
5666 inst
.operands
[i
].isreg
= 1;
5667 inst
.operands
[i
].isvec
= 1;
5668 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5669 inst
.operands
[i
].vectype
= optype
;
5670 inst
.operands
[i
].present
= 1;
5672 if (rtype
== REG_TYPE_VFS
)
5676 if (skip_past_comma (&ptr
) == FAIL
)
5678 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5681 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5684 inst
.operands
[i
].reg
= val
;
5685 inst
.operands
[i
].isreg
= 1;
5686 inst
.operands
[i
].isvec
= 1;
5687 inst
.operands
[i
].issingle
= 1;
5688 inst
.operands
[i
].vectype
= optype
;
5689 inst
.operands
[i
].present
= 1;
5692 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5696 inst
.operands
[i
].reg
= val
;
5697 inst
.operands
[i
].isreg
= 1;
5698 inst
.operands
[i
].isvec
= 1;
5699 inst
.operands
[i
].issingle
= 1;
5700 inst
.operands
[i
].vectype
= optype
;
5701 inst
.operands
[i
++].present
= 1;
5706 first_error (_("parse error"));
5710 /* Successfully parsed the operands. Update args. */
5716 first_error (_("expected comma"));
5720 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5724 /* Matcher codes for parse_operands. */
5725 enum operand_parse_code
5727 OP_stop
, /* end of line */
5729 OP_RR
, /* ARM register */
5730 OP_RRnpc
, /* ARM register, not r15 */
5731 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5732 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5733 OP_RCP
, /* Coprocessor number */
5734 OP_RCN
, /* Coprocessor register */
5735 OP_RF
, /* FPA register */
5736 OP_RVS
, /* VFP single precision register */
5737 OP_RVD
, /* VFP double precision register (0..15) */
5738 OP_RND
, /* Neon double precision register (0..31) */
5739 OP_RNQ
, /* Neon quad precision register */
5740 OP_RVSD
, /* VFP single or double precision register */
5741 OP_RNDQ
, /* Neon double or quad precision register */
5742 OP_RNSDQ
, /* Neon single, double or quad precision register */
5743 OP_RNSC
, /* Neon scalar D[X] */
5744 OP_RVC
, /* VFP control register */
5745 OP_RMF
, /* Maverick F register */
5746 OP_RMD
, /* Maverick D register */
5747 OP_RMFX
, /* Maverick FX register */
5748 OP_RMDX
, /* Maverick DX register */
5749 OP_RMAX
, /* Maverick AX register */
5750 OP_RMDS
, /* Maverick DSPSC register */
5751 OP_RIWR
, /* iWMMXt wR register */
5752 OP_RIWC
, /* iWMMXt wC register */
5753 OP_RIWG
, /* iWMMXt wCG register */
5754 OP_RXA
, /* XScale accumulator register */
5756 OP_REGLST
, /* ARM register list */
5757 OP_VRSLST
, /* VFP single-precision register list */
5758 OP_VRDLST
, /* VFP double-precision register list */
5759 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5760 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5761 OP_NSTRLST
, /* Neon element/structure list */
5763 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5764 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5765 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5766 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5767 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5768 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5769 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5770 OP_VMOV
, /* Neon VMOV operands. */
5771 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5772 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5773 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5775 OP_I0
, /* immediate zero */
5776 OP_I7
, /* immediate value 0 .. 7 */
5777 OP_I15
, /* 0 .. 15 */
5778 OP_I16
, /* 1 .. 16 */
5779 OP_I16z
, /* 0 .. 16 */
5780 OP_I31
, /* 0 .. 31 */
5781 OP_I31w
, /* 0 .. 31, optional trailing ! */
5782 OP_I32
, /* 1 .. 32 */
5783 OP_I32z
, /* 0 .. 32 */
5784 OP_I63
, /* 0 .. 63 */
5785 OP_I63s
, /* -64 .. 63 */
5786 OP_I64
, /* 1 .. 64 */
5787 OP_I64z
, /* 0 .. 64 */
5788 OP_I255
, /* 0 .. 255 */
5790 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5791 OP_I7b
, /* 0 .. 7 */
5792 OP_I15b
, /* 0 .. 15 */
5793 OP_I31b
, /* 0 .. 31 */
5795 OP_SH
, /* shifter operand */
5796 OP_SHG
, /* shifter operand with possible group relocation */
5797 OP_ADDR
, /* Memory address expression (any mode) */
5798 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5799 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5800 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5801 OP_EXP
, /* arbitrary expression */
5802 OP_EXPi
, /* same, with optional immediate prefix */
5803 OP_EXPr
, /* same, with optional relocation suffix */
5804 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5806 OP_CPSF
, /* CPS flags */
5807 OP_ENDI
, /* Endianness specifier */
5808 OP_PSR
, /* CPSR/SPSR mask for msr */
5809 OP_COND
, /* conditional code */
5810 OP_TB
, /* Table branch. */
5812 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5813 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5815 OP_RRnpc_I0
, /* ARM register or literal 0 */
5816 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5817 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5818 OP_RF_IF
, /* FPA register or immediate */
5819 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5820 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5822 /* Optional operands. */
5823 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5824 OP_oI31b
, /* 0 .. 31 */
5825 OP_oI32b
, /* 1 .. 32 */
5826 OP_oIffffb
, /* 0 .. 65535 */
5827 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5829 OP_oRR
, /* ARM register */
5830 OP_oRRnpc
, /* ARM register, not the PC */
5831 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5832 OP_oRND
, /* Optional Neon double precision register */
5833 OP_oRNQ
, /* Optional Neon quad precision register */
5834 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5835 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5836 OP_oSHll
, /* LSL immediate */
5837 OP_oSHar
, /* ASR immediate */
5838 OP_oSHllar
, /* LSL or ASR immediate */
5839 OP_oROR
, /* ROR 0/8/16/24 */
5840 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5842 OP_FIRST_OPTIONAL
= OP_oI7b
5845 /* Generic instruction operand parser. This does no encoding and no
5846 semantic validation; it merely squirrels values away in the inst
5847 structure. Returns SUCCESS or FAIL depending on whether the
5848 specified grammar matched. */
5850 parse_operands (char *str
, const unsigned char *pattern
)
5852 unsigned const char *upat
= pattern
;
5853 char *backtrack_pos
= 0;
5854 const char *backtrack_error
= 0;
5855 int i
, val
, backtrack_index
= 0;
5856 enum arm_reg_type rtype
;
5857 parse_operand_result result
;
5859 #define po_char_or_fail(chr) \
5862 if (skip_past_char (&str, chr) == FAIL) \
5867 #define po_reg_or_fail(regtype) \
5870 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5871 & inst.operands[i].vectype); \
5874 first_error (_(reg_expected_msgs[regtype])); \
5877 inst.operands[i].reg = val; \
5878 inst.operands[i].isreg = 1; \
5879 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5880 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5881 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5882 || rtype == REG_TYPE_VFD \
5883 || rtype == REG_TYPE_NQ); \
5887 #define po_reg_or_goto(regtype, label) \
5890 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5891 & inst.operands[i].vectype); \
5895 inst.operands[i].reg = val; \
5896 inst.operands[i].isreg = 1; \
5897 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5898 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5899 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5900 || rtype == REG_TYPE_VFD \
5901 || rtype == REG_TYPE_NQ); \
5905 #define po_imm_or_fail(min, max, popt) \
5908 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5910 inst.operands[i].imm = val; \
5914 #define po_scalar_or_goto(elsz, label) \
5917 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5920 inst.operands[i].reg = val; \
5921 inst.operands[i].isscalar = 1; \
5925 #define po_misc_or_fail(expr) \
5933 #define po_misc_or_fail_no_backtrack(expr) \
5937 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5938 backtrack_pos = 0; \
5939 if (result != PARSE_OPERAND_SUCCESS) \
5944 skip_whitespace (str
);
5946 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5948 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5950 /* Remember where we are in case we need to backtrack. */
5951 gas_assert (!backtrack_pos
);
5952 backtrack_pos
= str
;
5953 backtrack_error
= inst
.error
;
5954 backtrack_index
= i
;
5957 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5958 po_char_or_fail (',');
5966 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5967 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5968 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5969 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5970 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5971 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5973 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5975 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5977 /* Also accept generic coprocessor regs for unknown registers. */
5979 po_reg_or_fail (REG_TYPE_CN
);
5981 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5982 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5983 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5984 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5985 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5986 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5987 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5988 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5989 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5990 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5992 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5994 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5995 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5997 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5999 /* Neon scalar. Using an element size of 8 means that some invalid
6000 scalars are accepted here, so deal with those in later code. */
6001 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6003 /* WARNING: We can expand to two operands here. This has the potential
6004 to totally confuse the backtracking mechanism! It will be OK at
6005 least as long as we don't try to use optional args as well,
6009 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6010 inst
.operands
[i
].present
= 1;
6012 skip_past_comma (&str
);
6013 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6016 /* Optional register operand was omitted. Unfortunately, it's in
6017 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6018 here (this is a bit grotty). */
6019 inst
.operands
[i
] = inst
.operands
[i
-1];
6020 inst
.operands
[i
-1].present
= 0;
6023 /* There's a possibility of getting a 64-bit immediate here, so
6024 we need special handling. */
6025 if (parse_big_immediate (&str
, i
) == FAIL
)
6027 inst
.error
= _("immediate value is out of range");
6035 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6038 po_imm_or_fail (0, 0, TRUE
);
6043 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6048 po_scalar_or_goto (8, try_rr
);
6051 po_reg_or_fail (REG_TYPE_RN
);
6057 po_scalar_or_goto (8, try_nsdq
);
6060 po_reg_or_fail (REG_TYPE_NSDQ
);
6066 po_scalar_or_goto (8, try_ndq
);
6069 po_reg_or_fail (REG_TYPE_NDQ
);
6075 po_scalar_or_goto (8, try_vfd
);
6078 po_reg_or_fail (REG_TYPE_VFD
);
6083 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6084 not careful then bad things might happen. */
6085 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6090 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6093 /* There's a possibility of getting a 64-bit immediate here, so
6094 we need special handling. */
6095 if (parse_big_immediate (&str
, i
) == FAIL
)
6097 inst
.error
= _("immediate value is out of range");
6105 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6108 po_imm_or_fail (0, 63, TRUE
);
6113 po_char_or_fail ('[');
6114 po_reg_or_fail (REG_TYPE_RN
);
6115 po_char_or_fail (']');
6120 po_reg_or_fail (REG_TYPE_RN
);
6121 if (skip_past_char (&str
, '!') == SUCCESS
)
6122 inst
.operands
[i
].writeback
= 1;
6126 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6127 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6128 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6129 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6130 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6131 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6132 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6133 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6134 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6135 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6136 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6137 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6139 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6141 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6142 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6144 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6145 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6146 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6148 /* Immediate variants */
6150 po_char_or_fail ('{');
6151 po_imm_or_fail (0, 255, TRUE
);
6152 po_char_or_fail ('}');
6156 /* The expression parser chokes on a trailing !, so we have
6157 to find it first and zap it. */
6160 while (*s
&& *s
!= ',')
6165 inst
.operands
[i
].writeback
= 1;
6167 po_imm_or_fail (0, 31, TRUE
);
6175 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6180 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6185 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6187 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6189 val
= parse_reloc (&str
);
6192 inst
.error
= _("unrecognized relocation suffix");
6195 else if (val
!= BFD_RELOC_UNUSED
)
6197 inst
.operands
[i
].imm
= val
;
6198 inst
.operands
[i
].hasreloc
= 1;
6203 /* Operand for MOVW or MOVT. */
6205 po_misc_or_fail (parse_half (&str
));
6208 /* Register or expression. */
6209 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6210 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6212 /* Register or immediate. */
6213 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6214 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6216 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6218 if (!is_immediate_prefix (*str
))
6221 val
= parse_fpa_immediate (&str
);
6224 /* FPA immediates are encoded as registers 8-15.
6225 parse_fpa_immediate has already applied the offset. */
6226 inst
.operands
[i
].reg
= val
;
6227 inst
.operands
[i
].isreg
= 1;
6230 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6231 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6233 /* Two kinds of register. */
6236 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6238 || (rege
->type
!= REG_TYPE_MMXWR
6239 && rege
->type
!= REG_TYPE_MMXWC
6240 && rege
->type
!= REG_TYPE_MMXWCG
))
6242 inst
.error
= _("iWMMXt data or control register expected");
6245 inst
.operands
[i
].reg
= rege
->number
;
6246 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6252 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6254 || (rege
->type
!= REG_TYPE_MMXWC
6255 && rege
->type
!= REG_TYPE_MMXWCG
))
6257 inst
.error
= _("iWMMXt control register expected");
6260 inst
.operands
[i
].reg
= rege
->number
;
6261 inst
.operands
[i
].isreg
= 1;
6266 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6267 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6268 case OP_oROR
: val
= parse_ror (&str
); break;
6269 case OP_PSR
: val
= parse_psr (&str
); break;
6270 case OP_COND
: val
= parse_cond (&str
); break;
6271 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6274 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6275 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6278 val
= parse_psr (&str
);
6282 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6285 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6287 if (strncasecmp (str
, "APSR_", 5) == 0)
6294 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6295 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6296 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6297 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6298 default: found
= 16;
6302 inst
.operands
[i
].isvec
= 1;
6309 po_misc_or_fail (parse_tb (&str
));
6312 /* Register lists. */
6314 val
= parse_reg_list (&str
);
6317 inst
.operands
[1].writeback
= 1;
6323 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6327 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6331 /* Allow Q registers too. */
6332 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6337 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6339 inst
.operands
[i
].issingle
= 1;
6344 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6349 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6350 &inst
.operands
[i
].vectype
);
6353 /* Addressing modes */
6355 po_misc_or_fail (parse_address (&str
, i
));
6359 po_misc_or_fail_no_backtrack (
6360 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6364 po_misc_or_fail_no_backtrack (
6365 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6369 po_misc_or_fail_no_backtrack (
6370 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6374 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6378 po_misc_or_fail_no_backtrack (
6379 parse_shifter_operand_group_reloc (&str
, i
));
6383 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6387 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6391 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6395 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6398 /* Various value-based sanity checks and shared operations. We
6399 do not signal immediate failures for the register constraints;
6400 this allows a syntax error to take precedence. */
6409 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6410 inst
.error
= BAD_PC
;
6428 inst
.operands
[i
].imm
= val
;
6435 /* If we get here, this operand was successfully parsed. */
6436 inst
.operands
[i
].present
= 1;
6440 inst
.error
= BAD_ARGS
;
6445 /* The parse routine should already have set inst.error, but set a
6446 default here just in case. */
6448 inst
.error
= _("syntax error");
6452 /* Do not backtrack over a trailing optional argument that
6453 absorbed some text. We will only fail again, with the
6454 'garbage following instruction' error message, which is
6455 probably less helpful than the current one. */
6456 if (backtrack_index
== i
&& backtrack_pos
!= str
6457 && upat
[i
+1] == OP_stop
)
6460 inst
.error
= _("syntax error");
6464 /* Try again, skipping the optional argument at backtrack_pos. */
6465 str
= backtrack_pos
;
6466 inst
.error
= backtrack_error
;
6467 inst
.operands
[backtrack_index
].present
= 0;
6468 i
= backtrack_index
;
6472 /* Check that we have parsed all the arguments. */
6473 if (*str
!= '\0' && !inst
.error
)
6474 inst
.error
= _("garbage following instruction");
6476 return inst
.error
? FAIL
: SUCCESS
;
6479 #undef po_char_or_fail
6480 #undef po_reg_or_fail
6481 #undef po_reg_or_goto
6482 #undef po_imm_or_fail
6483 #undef po_scalar_or_fail
6485 /* Shorthand macro for instruction encoding functions issuing errors. */
6486 #define constraint(expr, err) \
6497 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6498 instructions are unpredictable if these registers are used. This
6499 is the BadReg predicate in ARM's Thumb-2 documentation. */
6500 #define reject_bad_reg(reg) \
6502 if (reg == REG_SP || reg == REG_PC) \
6504 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6509 /* If REG is R13 (the stack pointer), warn that its use is
6511 #define warn_deprecated_sp(reg) \
6513 if (warn_on_deprecated && reg == REG_SP) \
6514 as_warn (_("use of r13 is deprecated")); \
6517 /* Functions for operand encoding. ARM, then Thumb. */
6519 #define rotate_left(v, n) (v << n | v >> (32 - n))
6521 /* If VAL can be encoded in the immediate field of an ARM instruction,
6522 return the encoded form. Otherwise, return FAIL. */
6525 encode_arm_immediate (unsigned int val
)
6529 for (i
= 0; i
< 32; i
+= 2)
6530 if ((a
= rotate_left (val
, i
)) <= 0xff)
6531 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6536 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6537 return the encoded form. Otherwise, return FAIL. */
6539 encode_thumb32_immediate (unsigned int val
)
6546 for (i
= 1; i
<= 24; i
++)
6549 if ((val
& ~(0xff << i
)) == 0)
6550 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6554 if (val
== ((a
<< 16) | a
))
6556 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6560 if (val
== ((a
<< 16) | a
))
6561 return 0x200 | (a
>> 8);
6565 /* Encode a VFP SP or DP register number into inst.instruction. */
6568 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6570 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6573 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6576 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6579 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6584 first_error (_("D register out of range for selected VFP version"));
6592 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6596 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6600 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6604 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6608 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6612 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6620 /* Encode a <shift> in an ARM-format instruction. The immediate,
6621 if any, is handled by md_apply_fix. */
6623 encode_arm_shift (int i
)
6625 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6626 inst
.instruction
|= SHIFT_ROR
<< 5;
6629 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6630 if (inst
.operands
[i
].immisreg
)
6632 inst
.instruction
|= SHIFT_BY_REG
;
6633 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6636 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6641 encode_arm_shifter_operand (int i
)
6643 if (inst
.operands
[i
].isreg
)
6645 inst
.instruction
|= inst
.operands
[i
].reg
;
6646 encode_arm_shift (i
);
6649 inst
.instruction
|= INST_IMMEDIATE
;
6652 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6654 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6656 gas_assert (inst
.operands
[i
].isreg
);
6657 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6659 if (inst
.operands
[i
].preind
)
6663 inst
.error
= _("instruction does not accept preindexed addressing");
6666 inst
.instruction
|= PRE_INDEX
;
6667 if (inst
.operands
[i
].writeback
)
6668 inst
.instruction
|= WRITE_BACK
;
6671 else if (inst
.operands
[i
].postind
)
6673 gas_assert (inst
.operands
[i
].writeback
);
6675 inst
.instruction
|= WRITE_BACK
;
6677 else /* unindexed - only for coprocessor */
6679 inst
.error
= _("instruction does not accept unindexed addressing");
6683 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6684 && (((inst
.instruction
& 0x000f0000) >> 16)
6685 == ((inst
.instruction
& 0x0000f000) >> 12)))
6686 as_warn ((inst
.instruction
& LOAD_BIT
)
6687 ? _("destination register same as write-back base")
6688 : _("source register same as write-back base"));
6691 /* inst.operands[i] was set up by parse_address. Encode it into an
6692 ARM-format mode 2 load or store instruction. If is_t is true,
6693 reject forms that cannot be used with a T instruction (i.e. not
6696 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6698 encode_arm_addr_mode_common (i
, is_t
);
6700 if (inst
.operands
[i
].immisreg
)
6702 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6703 inst
.instruction
|= inst
.operands
[i
].imm
;
6704 if (!inst
.operands
[i
].negative
)
6705 inst
.instruction
|= INDEX_UP
;
6706 if (inst
.operands
[i
].shifted
)
6708 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6709 inst
.instruction
|= SHIFT_ROR
<< 5;
6712 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6713 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6717 else /* immediate offset in inst.reloc */
6719 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6720 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6724 /* inst.operands[i] was set up by parse_address. Encode it into an
6725 ARM-format mode 3 load or store instruction. Reject forms that
6726 cannot be used with such instructions. If is_t is true, reject
6727 forms that cannot be used with a T instruction (i.e. not
6730 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6732 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6734 inst
.error
= _("instruction does not accept scaled register index");
6738 encode_arm_addr_mode_common (i
, is_t
);
6740 if (inst
.operands
[i
].immisreg
)
6742 inst
.instruction
|= inst
.operands
[i
].imm
;
6743 if (!inst
.operands
[i
].negative
)
6744 inst
.instruction
|= INDEX_UP
;
6746 else /* immediate offset in inst.reloc */
6748 inst
.instruction
|= HWOFFSET_IMM
;
6749 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6750 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6754 /* inst.operands[i] was set up by parse_address. Encode it into an
6755 ARM-format instruction. Reject all forms which cannot be encoded
6756 into a coprocessor load/store instruction. If wb_ok is false,
6757 reject use of writeback; if unind_ok is false, reject use of
6758 unindexed addressing. If reloc_override is not 0, use it instead
6759 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6760 (in which case it is preserved). */
6763 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6765 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6767 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6769 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6771 gas_assert (!inst
.operands
[i
].writeback
);
6774 inst
.error
= _("instruction does not support unindexed addressing");
6777 inst
.instruction
|= inst
.operands
[i
].imm
;
6778 inst
.instruction
|= INDEX_UP
;
6782 if (inst
.operands
[i
].preind
)
6783 inst
.instruction
|= PRE_INDEX
;
6785 if (inst
.operands
[i
].writeback
)
6787 if (inst
.operands
[i
].reg
== REG_PC
)
6789 inst
.error
= _("pc may not be used with write-back");
6794 inst
.error
= _("instruction does not support writeback");
6797 inst
.instruction
|= WRITE_BACK
;
6801 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6802 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6803 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6804 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6807 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6809 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6815 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6816 Determine whether it can be performed with a move instruction; if
6817 it can, convert inst.instruction to that move instruction and
6818 return TRUE; if it can't, convert inst.instruction to a literal-pool
6819 load and return FALSE. If this is not a valid thing to do in the
6820 current context, set inst.error and return TRUE.
6822 inst.operands[i] describes the destination register. */
6825 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6830 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6834 if ((inst
.instruction
& tbit
) == 0)
6836 inst
.error
= _("invalid pseudo operation");
6839 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6841 inst
.error
= _("constant expression expected");
6844 if (inst
.reloc
.exp
.X_op
== O_constant
)
6848 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6850 /* This can be done with a mov(1) instruction. */
6851 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6852 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6858 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6861 /* This can be done with a mov instruction. */
6862 inst
.instruction
&= LITERAL_MASK
;
6863 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6864 inst
.instruction
|= value
& 0xfff;
6868 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6871 /* This can be done with a mvn instruction. */
6872 inst
.instruction
&= LITERAL_MASK
;
6873 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6874 inst
.instruction
|= value
& 0xfff;
6880 if (add_to_lit_pool () == FAIL
)
6882 inst
.error
= _("literal pool insertion failed");
6885 inst
.operands
[1].reg
= REG_PC
;
6886 inst
.operands
[1].isreg
= 1;
6887 inst
.operands
[1].preind
= 1;
6888 inst
.reloc
.pc_rel
= 1;
6889 inst
.reloc
.type
= (thumb_p
6890 ? BFD_RELOC_ARM_THUMB_OFFSET
6892 ? BFD_RELOC_ARM_HWLITERAL
6893 : BFD_RELOC_ARM_LITERAL
));
6897 /* Functions for instruction encoding, sorted by sub-architecture.
6898 First some generics; their names are taken from the conventional
6899 bit positions for register arguments in ARM format instructions. */
6909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6916 inst
.instruction
|= inst
.operands
[1].reg
;
6922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6929 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6930 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6936 unsigned Rn
= inst
.operands
[2].reg
;
6937 /* Enforce restrictions on SWP instruction. */
6938 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6939 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6940 _("Rn must not overlap other operands"));
6941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6942 inst
.instruction
|= inst
.operands
[1].reg
;
6943 inst
.instruction
|= Rn
<< 16;
6949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6951 inst
.instruction
|= inst
.operands
[2].reg
;
6957 inst
.instruction
|= inst
.operands
[0].reg
;
6958 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6959 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6965 inst
.instruction
|= inst
.operands
[0].imm
;
6971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6972 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6975 /* ARM instructions, in alphabetical order by function name (except
6976 that wrapper functions appear immediately after the function they
6979 /* This is a pseudo-op of the form "adr rd, label" to be converted
6980 into a relative address of the form "add rd, pc, #label-.-8". */
6985 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6987 /* Frag hacking will turn this into a sub instruction if the offset turns
6988 out to be negative. */
6989 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6990 inst
.reloc
.pc_rel
= 1;
6991 inst
.reloc
.exp
.X_add_number
-= 8;
6994 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6995 into a relative address of the form:
6996 add rd, pc, #low(label-.-8)"
6997 add rd, rd, #high(label-.-8)" */
7002 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7004 /* Frag hacking will turn this into a sub instruction if the offset turns
7005 out to be negative. */
7006 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7007 inst
.reloc
.pc_rel
= 1;
7008 inst
.size
= INSN_SIZE
* 2;
7009 inst
.reloc
.exp
.X_add_number
-= 8;
7015 if (!inst
.operands
[1].present
)
7016 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7018 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7019 encode_arm_shifter_operand (2);
7025 if (inst
.operands
[0].present
)
7027 constraint ((inst
.instruction
& 0xf0) != 0x40
7028 && inst
.operands
[0].imm
!= 0xf,
7029 _("bad barrier type"));
7030 inst
.instruction
|= inst
.operands
[0].imm
;
7033 inst
.instruction
|= 0xf;
7039 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7040 constraint (msb
> 32, _("bit-field extends past end of register"));
7041 /* The instruction encoding stores the LSB and MSB,
7042 not the LSB and width. */
7043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7044 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7045 inst
.instruction
|= (msb
- 1) << 16;
7053 /* #0 in second position is alternative syntax for bfc, which is
7054 the same instruction but with REG_PC in the Rm field. */
7055 if (!inst
.operands
[1].isreg
)
7056 inst
.operands
[1].reg
= REG_PC
;
7058 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7059 constraint (msb
> 32, _("bit-field extends past end of register"));
7060 /* The instruction encoding stores the LSB and MSB,
7061 not the LSB and width. */
7062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7063 inst
.instruction
|= inst
.operands
[1].reg
;
7064 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7065 inst
.instruction
|= (msb
- 1) << 16;
7071 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7072 _("bit-field extends past end of register"));
7073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7074 inst
.instruction
|= inst
.operands
[1].reg
;
7075 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7076 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7079 /* ARM V5 breakpoint instruction (argument parse)
7080 BKPT <16 bit unsigned immediate>
7081 Instruction is not conditional.
7082 The bit pattern given in insns[] has the COND_ALWAYS condition,
7083 and it is an error if the caller tried to override that. */
7088 /* Top 12 of 16 bits to bits 19:8. */
7089 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7091 /* Bottom 4 of 16 bits to bits 3:0. */
7092 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7096 encode_branch (int default_reloc
)
7098 if (inst
.operands
[0].hasreloc
)
7100 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7101 _("the only suffix valid here is '(plt)'"));
7102 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7106 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7108 inst
.reloc
.pc_rel
= 1;
7115 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7116 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7119 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7126 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7128 if (inst
.cond
== COND_ALWAYS
)
7129 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7131 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7135 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7138 /* ARM V5 branch-link-exchange instruction (argument parse)
7139 BLX <target_addr> ie BLX(1)
7140 BLX{<condition>} <Rm> ie BLX(2)
7141 Unfortunately, there are two different opcodes for this mnemonic.
7142 So, the insns[].value is not used, and the code here zaps values
7143 into inst.instruction.
7144 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7149 if (inst
.operands
[0].isreg
)
7151 /* Arg is a register; the opcode provided by insns[] is correct.
7152 It is not illegal to do "blx pc", just useless. */
7153 if (inst
.operands
[0].reg
== REG_PC
)
7154 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7156 inst
.instruction
|= inst
.operands
[0].reg
;
7160 /* Arg is an address; this instruction cannot be executed
7161 conditionally, and the opcode must be adjusted.
7162 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7163 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7164 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7165 inst
.instruction
= 0xfa000000;
7166 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7173 bfd_boolean want_reloc
;
7175 if (inst
.operands
[0].reg
== REG_PC
)
7176 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7178 inst
.instruction
|= inst
.operands
[0].reg
;
7179 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7180 it is for ARMv4t or earlier. */
7181 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7182 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7186 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7191 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7195 /* ARM v5TEJ. Jump to Jazelle code. */
7200 if (inst
.operands
[0].reg
== REG_PC
)
7201 as_tsktsk (_("use of r15 in bxj is not really useful"));
7203 inst
.instruction
|= inst
.operands
[0].reg
;
7206 /* Co-processor data operation:
7207 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7208 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7212 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7213 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7214 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7215 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7216 inst
.instruction
|= inst
.operands
[4].reg
;
7217 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7223 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7224 encode_arm_shifter_operand (1);
7227 /* Transfer between coprocessor and ARM registers.
7228 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7233 No special properties. */
7240 Rd
= inst
.operands
[2].reg
;
7243 if (inst
.instruction
== 0xee000010
7244 || inst
.instruction
== 0xfe000010)
7246 reject_bad_reg (Rd
);
7249 constraint (Rd
== REG_SP
, BAD_SP
);
7254 if (inst
.instruction
== 0xe000010)
7255 constraint (Rd
== REG_PC
, BAD_PC
);
7259 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7260 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7261 inst
.instruction
|= Rd
<< 12;
7262 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7263 inst
.instruction
|= inst
.operands
[4].reg
;
7264 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7267 /* Transfer between coprocessor register and pair of ARM registers.
7268 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7273 Two XScale instructions are special cases of these:
7275 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7276 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7278 Result unpredictable if Rd or Rn is R15. */
7285 Rd
= inst
.operands
[2].reg
;
7286 Rn
= inst
.operands
[3].reg
;
7290 reject_bad_reg (Rd
);
7291 reject_bad_reg (Rn
);
7295 constraint (Rd
== REG_PC
, BAD_PC
);
7296 constraint (Rn
== REG_PC
, BAD_PC
);
7299 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7300 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7301 inst
.instruction
|= Rd
<< 12;
7302 inst
.instruction
|= Rn
<< 16;
7303 inst
.instruction
|= inst
.operands
[4].reg
;
7309 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7310 if (inst
.operands
[1].present
)
7312 inst
.instruction
|= CPSI_MMOD
;
7313 inst
.instruction
|= inst
.operands
[1].imm
;
7320 inst
.instruction
|= inst
.operands
[0].imm
;
7326 /* There is no IT instruction in ARM mode. We
7327 process it to do the validation as if in
7328 thumb mode, just in case the code gets
7329 assembled for thumb using the unified syntax. */
7334 set_it_insn_type (IT_INSN
);
7335 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7336 now_it
.cc
= inst
.operands
[0].imm
;
7343 int base_reg
= inst
.operands
[0].reg
;
7344 int range
= inst
.operands
[1].imm
;
7346 inst
.instruction
|= base_reg
<< 16;
7347 inst
.instruction
|= range
;
7349 if (inst
.operands
[1].writeback
)
7350 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7352 if (inst
.operands
[0].writeback
)
7354 inst
.instruction
|= WRITE_BACK
;
7355 /* Check for unpredictable uses of writeback. */
7356 if (inst
.instruction
& LOAD_BIT
)
7358 /* Not allowed in LDM type 2. */
7359 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7360 && ((range
& (1 << REG_PC
)) == 0))
7361 as_warn (_("writeback of base register is UNPREDICTABLE"));
7362 /* Only allowed if base reg not in list for other types. */
7363 else if (range
& (1 << base_reg
))
7364 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7368 /* Not allowed for type 2. */
7369 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7370 as_warn (_("writeback of base register is UNPREDICTABLE"));
7371 /* Only allowed if base reg not in list, or first in list. */
7372 else if ((range
& (1 << base_reg
))
7373 && (range
& ((1 << base_reg
) - 1)))
7374 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7379 /* ARMv5TE load-consecutive (argument parse)
7388 constraint (inst
.operands
[0].reg
% 2 != 0,
7389 _("first destination register must be even"));
7390 constraint (inst
.operands
[1].present
7391 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7392 _("can only load two consecutive registers"));
7393 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7394 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7396 if (!inst
.operands
[1].present
)
7397 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7399 if (inst
.instruction
& LOAD_BIT
)
7401 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7402 register and the first register written; we have to diagnose
7403 overlap between the base and the second register written here. */
7405 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7406 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7407 as_warn (_("base register written back, and overlaps "
7408 "second destination register"));
7410 /* For an index-register load, the index register must not overlap the
7411 destination (even if not write-back). */
7412 else if (inst
.operands
[2].immisreg
7413 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7414 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7415 as_warn (_("index register overlaps destination register"));
7418 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7419 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7425 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7426 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7427 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7428 || inst
.operands
[1].negative
7429 /* This can arise if the programmer has written
7431 or if they have mistakenly used a register name as the last
7434 It is very difficult to distinguish between these two cases
7435 because "rX" might actually be a label. ie the register
7436 name has been occluded by a symbol of the same name. So we
7437 just generate a general 'bad addressing mode' type error
7438 message and leave it up to the programmer to discover the
7439 true cause and fix their mistake. */
7440 || (inst
.operands
[1].reg
== REG_PC
),
7443 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7444 || inst
.reloc
.exp
.X_add_number
!= 0,
7445 _("offset must be zero in ARM encoding"));
7447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7449 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7455 constraint (inst
.operands
[0].reg
% 2 != 0,
7456 _("even register required"));
7457 constraint (inst
.operands
[1].present
7458 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7459 _("can only load two consecutive registers"));
7460 /* If op 1 were present and equal to PC, this function wouldn't
7461 have been called in the first place. */
7462 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7465 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7472 if (!inst
.operands
[1].isreg
)
7473 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7475 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7481 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7483 if (inst
.operands
[1].preind
)
7485 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7486 || inst
.reloc
.exp
.X_add_number
!= 0,
7487 _("this instruction requires a post-indexed address"));
7489 inst
.operands
[1].preind
= 0;
7490 inst
.operands
[1].postind
= 1;
7491 inst
.operands
[1].writeback
= 1;
7493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7494 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7497 /* Halfword and signed-byte load/store operations. */
7502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7503 if (!inst
.operands
[1].isreg
)
7504 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7506 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7512 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7514 if (inst
.operands
[1].preind
)
7516 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7517 || inst
.reloc
.exp
.X_add_number
!= 0,
7518 _("this instruction requires a post-indexed address"));
7520 inst
.operands
[1].preind
= 0;
7521 inst
.operands
[1].postind
= 1;
7522 inst
.operands
[1].writeback
= 1;
7524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7525 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7528 /* Co-processor register load/store.
7529 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7533 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7534 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7535 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7541 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7542 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7543 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7544 && !(inst
.instruction
& 0x00400000))
7545 as_tsktsk (_("Rd and Rm should be different in mla"));
7547 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7548 inst
.instruction
|= inst
.operands
[1].reg
;
7549 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7550 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7557 encode_arm_shifter_operand (1);
7560 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7567 top
= (inst
.instruction
& 0x00400000) != 0;
7568 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7569 _(":lower16: not allowed this instruction"));
7570 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7571 _(":upper16: not allowed instruction"));
7572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7573 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7575 imm
= inst
.reloc
.exp
.X_add_number
;
7576 /* The value is in two pieces: 0:11, 16:19. */
7577 inst
.instruction
|= (imm
& 0x00000fff);
7578 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7582 static void do_vfp_nsyn_opcode (const char *);
7585 do_vfp_nsyn_mrs (void)
7587 if (inst
.operands
[0].isvec
)
7589 if (inst
.operands
[1].reg
!= 1)
7590 first_error (_("operand 1 must be FPSCR"));
7591 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7592 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7593 do_vfp_nsyn_opcode ("fmstat");
7595 else if (inst
.operands
[1].isvec
)
7596 do_vfp_nsyn_opcode ("fmrx");
7604 do_vfp_nsyn_msr (void)
7606 if (inst
.operands
[0].isvec
)
7607 do_vfp_nsyn_opcode ("fmxr");
7617 if (do_vfp_nsyn_mrs () == SUCCESS
)
7620 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7621 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7623 _("'CPSR' or 'SPSR' expected"));
7624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7625 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7628 /* Two possible forms:
7629 "{C|S}PSR_<field>, Rm",
7630 "{C|S}PSR_f, #expression". */
7635 if (do_vfp_nsyn_msr () == SUCCESS
)
7638 inst
.instruction
|= inst
.operands
[0].imm
;
7639 if (inst
.operands
[1].isreg
)
7640 inst
.instruction
|= inst
.operands
[1].reg
;
7643 inst
.instruction
|= INST_IMMEDIATE
;
7644 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7645 inst
.reloc
.pc_rel
= 0;
7652 if (!inst
.operands
[2].present
)
7653 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7655 inst
.instruction
|= inst
.operands
[1].reg
;
7656 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7658 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7659 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7660 as_tsktsk (_("Rd and Rm should be different in mul"));
7663 /* Long Multiply Parser
7664 UMULL RdLo, RdHi, Rm, Rs
7665 SMULL RdLo, RdHi, Rm, Rs
7666 UMLAL RdLo, RdHi, Rm, Rs
7667 SMLAL RdLo, RdHi, Rm, Rs. */
7672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7673 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7674 inst
.instruction
|= inst
.operands
[2].reg
;
7675 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7677 /* rdhi and rdlo must be different. */
7678 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7679 as_tsktsk (_("rdhi and rdlo must be different"));
7681 /* rdhi, rdlo and rm must all be different before armv6. */
7682 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7683 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7684 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7685 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7691 if (inst
.operands
[0].present
7692 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7694 /* Architectural NOP hints are CPSR sets with no bits selected. */
7695 inst
.instruction
&= 0xf0000000;
7696 inst
.instruction
|= 0x0320f000;
7697 if (inst
.operands
[0].present
)
7698 inst
.instruction
|= inst
.operands
[0].imm
;
7702 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7703 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7704 Condition defaults to COND_ALWAYS.
7705 Error if Rd, Rn or Rm are R15. */
7710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7711 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7712 inst
.instruction
|= inst
.operands
[2].reg
;
7713 if (inst
.operands
[3].present
)
7714 encode_arm_shift (3);
7717 /* ARM V6 PKHTB (Argument Parse). */
7722 if (!inst
.operands
[3].present
)
7724 /* If the shift specifier is omitted, turn the instruction
7725 into pkhbt rd, rm, rn. */
7726 inst
.instruction
&= 0xfff00010;
7727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7728 inst
.instruction
|= inst
.operands
[1].reg
;
7729 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7734 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7735 inst
.instruction
|= inst
.operands
[2].reg
;
7736 encode_arm_shift (3);
7740 /* ARMv5TE: Preload-Cache
7744 Syntactically, like LDR with B=1, W=0, L=1. */
7749 constraint (!inst
.operands
[0].isreg
,
7750 _("'[' expected after PLD mnemonic"));
7751 constraint (inst
.operands
[0].postind
,
7752 _("post-indexed expression used in preload instruction"));
7753 constraint (inst
.operands
[0].writeback
,
7754 _("writeback used in preload instruction"));
7755 constraint (!inst
.operands
[0].preind
,
7756 _("unindexed addressing used in preload instruction"));
7757 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7760 /* ARMv7: PLI <addr_mode> */
7764 constraint (!inst
.operands
[0].isreg
,
7765 _("'[' expected after PLI mnemonic"));
7766 constraint (inst
.operands
[0].postind
,
7767 _("post-indexed expression used in preload instruction"));
7768 constraint (inst
.operands
[0].writeback
,
7769 _("writeback used in preload instruction"));
7770 constraint (!inst
.operands
[0].preind
,
7771 _("unindexed addressing used in preload instruction"));
7772 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7773 inst
.instruction
&= ~PRE_INDEX
;
7779 inst
.operands
[1] = inst
.operands
[0];
7780 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7781 inst
.operands
[0].isreg
= 1;
7782 inst
.operands
[0].writeback
= 1;
7783 inst
.operands
[0].reg
= REG_SP
;
7787 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7788 word at the specified address and the following word
7790 Unconditionally executed.
7791 Error if Rn is R15. */
7796 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7797 if (inst
.operands
[0].writeback
)
7798 inst
.instruction
|= WRITE_BACK
;
7801 /* ARM V6 ssat (argument parse). */
7806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7807 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7808 inst
.instruction
|= inst
.operands
[2].reg
;
7810 if (inst
.operands
[3].present
)
7811 encode_arm_shift (3);
7814 /* ARM V6 usat (argument parse). */
7819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7820 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7821 inst
.instruction
|= inst
.operands
[2].reg
;
7823 if (inst
.operands
[3].present
)
7824 encode_arm_shift (3);
7827 /* ARM V6 ssat16 (argument parse). */
7832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7833 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7834 inst
.instruction
|= inst
.operands
[2].reg
;
7840 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7841 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7842 inst
.instruction
|= inst
.operands
[2].reg
;
7845 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7846 preserving the other bits.
7848 setend <endian_specifier>, where <endian_specifier> is either
7854 if (inst
.operands
[0].imm
)
7855 inst
.instruction
|= 0x200;
7861 unsigned int Rm
= (inst
.operands
[1].present
7862 ? inst
.operands
[1].reg
7863 : inst
.operands
[0].reg
);
7865 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7866 inst
.instruction
|= Rm
;
7867 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7869 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7870 inst
.instruction
|= SHIFT_BY_REG
;
7873 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7879 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7880 inst
.reloc
.pc_rel
= 0;
7886 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7887 inst
.reloc
.pc_rel
= 0;
7890 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7891 SMLAxy{cond} Rd,Rm,Rs,Rn
7892 SMLAWy{cond} Rd,Rm,Rs,Rn
7893 Error if any register is R15. */
7898 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7899 inst
.instruction
|= inst
.operands
[1].reg
;
7900 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7901 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7904 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7905 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7906 Error if any register is R15.
7907 Warning if Rdlo == Rdhi. */
7912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7913 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7914 inst
.instruction
|= inst
.operands
[2].reg
;
7915 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7917 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7918 as_tsktsk (_("rdhi and rdlo must be different"));
7921 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7922 SMULxy{cond} Rd,Rm,Rs
7923 Error if any register is R15. */
7928 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7929 inst
.instruction
|= inst
.operands
[1].reg
;
7930 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7933 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7934 the same for both ARM and Thumb-2. */
7941 if (inst
.operands
[0].present
)
7943 reg
= inst
.operands
[0].reg
;
7944 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7949 inst
.instruction
|= reg
<< 16;
7950 inst
.instruction
|= inst
.operands
[1].imm
;
7951 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7952 inst
.instruction
|= WRITE_BACK
;
7955 /* ARM V6 strex (argument parse). */
7960 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7961 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7962 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7963 || inst
.operands
[2].negative
7964 /* See comment in do_ldrex(). */
7965 || (inst
.operands
[2].reg
== REG_PC
),
7968 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7969 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7971 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7972 || inst
.reloc
.exp
.X_add_number
!= 0,
7973 _("offset must be zero in ARM encoding"));
7975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7976 inst
.instruction
|= inst
.operands
[1].reg
;
7977 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7978 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7984 constraint (inst
.operands
[1].reg
% 2 != 0,
7985 _("even register required"));
7986 constraint (inst
.operands
[2].present
7987 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7988 _("can only store two consecutive registers"));
7989 /* If op 2 were present and equal to PC, this function wouldn't
7990 have been called in the first place. */
7991 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7993 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7994 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7995 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7999 inst
.instruction
|= inst
.operands
[1].reg
;
8000 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8003 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8004 extends it to 32-bits, and adds the result to a value in another
8005 register. You can specify a rotation by 0, 8, 16, or 24 bits
8006 before extracting the 16-bit value.
8007 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8008 Condition defaults to COND_ALWAYS.
8009 Error if any register uses R15. */
8014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8015 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8016 inst
.instruction
|= inst
.operands
[2].reg
;
8017 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8022 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8023 Condition defaults to COND_ALWAYS.
8024 Error if any register uses R15. */
8029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8030 inst
.instruction
|= inst
.operands
[1].reg
;
8031 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8034 /* VFP instructions. In a logical order: SP variant first, monad
8035 before dyad, arithmetic then move then load/store. */
8038 do_vfp_sp_monadic (void)
8040 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8041 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8045 do_vfp_sp_dyadic (void)
8047 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8048 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8049 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8053 do_vfp_sp_compare_z (void)
8055 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8059 do_vfp_dp_sp_cvt (void)
8061 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8062 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8066 do_vfp_sp_dp_cvt (void)
8068 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8069 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8073 do_vfp_reg_from_sp (void)
8075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8076 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8080 do_vfp_reg2_from_sp2 (void)
8082 constraint (inst
.operands
[2].imm
!= 2,
8083 _("only two consecutive VFP SP registers allowed here"));
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8086 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8090 do_vfp_sp_from_reg (void)
8092 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8093 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8097 do_vfp_sp2_from_reg2 (void)
8099 constraint (inst
.operands
[0].imm
!= 2,
8100 _("only two consecutive VFP SP registers allowed here"));
8101 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8102 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8103 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8107 do_vfp_sp_ldst (void)
8109 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8110 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8114 do_vfp_dp_ldst (void)
8116 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8117 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8122 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8124 if (inst
.operands
[0].writeback
)
8125 inst
.instruction
|= WRITE_BACK
;
8127 constraint (ldstm_type
!= VFP_LDSTMIA
,
8128 _("this addressing mode requires base-register writeback"));
8129 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8130 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8131 inst
.instruction
|= inst
.operands
[1].imm
;
8135 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8139 if (inst
.operands
[0].writeback
)
8140 inst
.instruction
|= WRITE_BACK
;
8142 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8143 _("this addressing mode requires base-register writeback"));
8145 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8146 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8148 count
= inst
.operands
[1].imm
<< 1;
8149 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8152 inst
.instruction
|= count
;
8156 do_vfp_sp_ldstmia (void)
8158 vfp_sp_ldstm (VFP_LDSTMIA
);
8162 do_vfp_sp_ldstmdb (void)
8164 vfp_sp_ldstm (VFP_LDSTMDB
);
8168 do_vfp_dp_ldstmia (void)
8170 vfp_dp_ldstm (VFP_LDSTMIA
);
8174 do_vfp_dp_ldstmdb (void)
8176 vfp_dp_ldstm (VFP_LDSTMDB
);
8180 do_vfp_xp_ldstmia (void)
8182 vfp_dp_ldstm (VFP_LDSTMIAX
);
8186 do_vfp_xp_ldstmdb (void)
8188 vfp_dp_ldstm (VFP_LDSTMDBX
);
8192 do_vfp_dp_rd_rm (void)
8194 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8195 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8199 do_vfp_dp_rn_rd (void)
8201 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8202 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8206 do_vfp_dp_rd_rn (void)
8208 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8209 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8213 do_vfp_dp_rd_rn_rm (void)
8215 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8216 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8217 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8223 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8227 do_vfp_dp_rm_rd_rn (void)
8229 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8230 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8231 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8234 /* VFPv3 instructions. */
8236 do_vfp_sp_const (void)
8238 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8239 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8240 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8244 do_vfp_dp_const (void)
8246 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8247 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8248 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8252 vfp_conv (int srcsize
)
8254 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8255 inst
.instruction
|= (immbits
& 1) << 5;
8256 inst
.instruction
|= (immbits
>> 1);
8260 do_vfp_sp_conv_16 (void)
8262 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8267 do_vfp_dp_conv_16 (void)
8269 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8274 do_vfp_sp_conv_32 (void)
8276 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8281 do_vfp_dp_conv_32 (void)
8283 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8287 /* FPA instructions. Also in a logical order. */
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8293 inst
.instruction
|= inst
.operands
[1].reg
;
8297 do_fpa_ldmstm (void)
8299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8300 switch (inst
.operands
[1].imm
)
8302 case 1: inst
.instruction
|= CP_T_X
; break;
8303 case 2: inst
.instruction
|= CP_T_Y
; break;
8304 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8309 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8311 /* The instruction specified "ea" or "fd", so we can only accept
8312 [Rn]{!}. The instruction does not really support stacking or
8313 unstacking, so we have to emulate these by setting appropriate
8314 bits and offsets. */
8315 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8316 || inst
.reloc
.exp
.X_add_number
!= 0,
8317 _("this instruction does not support indexing"));
8319 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8320 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8322 if (!(inst
.instruction
& INDEX_UP
))
8323 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8325 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8327 inst
.operands
[2].preind
= 0;
8328 inst
.operands
[2].postind
= 1;
8332 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8335 /* iWMMXt instructions: strictly in alphabetical order. */
8338 do_iwmmxt_tandorc (void)
8340 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8344 do_iwmmxt_textrc (void)
8346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8347 inst
.instruction
|= inst
.operands
[1].imm
;
8351 do_iwmmxt_textrm (void)
8353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8354 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8355 inst
.instruction
|= inst
.operands
[2].imm
;
8359 do_iwmmxt_tinsr (void)
8361 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8362 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8363 inst
.instruction
|= inst
.operands
[2].imm
;
8367 do_iwmmxt_tmia (void)
8369 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8370 inst
.instruction
|= inst
.operands
[1].reg
;
8371 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8375 do_iwmmxt_waligni (void)
8377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8378 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8379 inst
.instruction
|= inst
.operands
[2].reg
;
8380 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8384 do_iwmmxt_wmerge (void)
8386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8387 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8388 inst
.instruction
|= inst
.operands
[2].reg
;
8389 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8393 do_iwmmxt_wmov (void)
8395 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8397 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8398 inst
.instruction
|= inst
.operands
[1].reg
;
8402 do_iwmmxt_wldstbh (void)
8405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8407 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8409 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8410 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8414 do_iwmmxt_wldstw (void)
8416 /* RIWR_RIWC clears .isreg for a control register. */
8417 if (!inst
.operands
[0].isreg
)
8419 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8420 inst
.instruction
|= 0xf0000000;
8423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8424 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8428 do_iwmmxt_wldstd (void)
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8432 && inst
.operands
[1].immisreg
)
8434 inst
.instruction
&= ~0x1a000ff;
8435 inst
.instruction
|= (0xf << 28);
8436 if (inst
.operands
[1].preind
)
8437 inst
.instruction
|= PRE_INDEX
;
8438 if (!inst
.operands
[1].negative
)
8439 inst
.instruction
|= INDEX_UP
;
8440 if (inst
.operands
[1].writeback
)
8441 inst
.instruction
|= WRITE_BACK
;
8442 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8443 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8444 inst
.instruction
|= inst
.operands
[1].imm
;
8447 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8451 do_iwmmxt_wshufh (void)
8453 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8454 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8455 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8456 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8460 do_iwmmxt_wzero (void)
8462 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8463 inst
.instruction
|= inst
.operands
[0].reg
;
8464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8465 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8469 do_iwmmxt_wrwrwr_or_imm5 (void)
8471 if (inst
.operands
[2].isreg
)
8474 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8475 _("immediate operand requires iWMMXt2"));
8477 if (inst
.operands
[2].imm
== 0)
8479 switch ((inst
.instruction
>> 20) & 0xf)
8485 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8486 inst
.operands
[2].imm
= 16;
8487 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8493 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8494 inst
.operands
[2].imm
= 32;
8495 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8502 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8504 wrn
= (inst
.instruction
>> 16) & 0xf;
8505 inst
.instruction
&= 0xff0fff0f;
8506 inst
.instruction
|= wrn
;
8507 /* Bail out here; the instruction is now assembled. */
8512 /* Map 32 -> 0, etc. */
8513 inst
.operands
[2].imm
&= 0x1f;
8514 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8518 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8519 operations first, then control, shift, and load/store. */
8521 /* Insns like "foo X,Y,Z". */
8524 do_mav_triple (void)
8526 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8527 inst
.instruction
|= inst
.operands
[1].reg
;
8528 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8531 /* Insns like "foo W,X,Y,Z".
8532 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8537 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8538 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8539 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8540 inst
.instruction
|= inst
.operands
[3].reg
;
8543 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8547 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8550 /* Maverick shift immediate instructions.
8551 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8552 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8557 int imm
= inst
.operands
[2].imm
;
8559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8560 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8562 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8563 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8564 Bit 4 should be 0. */
8565 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8567 inst
.instruction
|= imm
;
8570 /* XScale instructions. Also sorted arithmetic before move. */
8572 /* Xscale multiply-accumulate (argument parse)
8575 MIAxycc acc0,Rm,Rs. */
8580 inst
.instruction
|= inst
.operands
[1].reg
;
8581 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8584 /* Xscale move-accumulator-register (argument parse)
8586 MARcc acc0,RdLo,RdHi. */
8591 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8592 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8595 /* Xscale move-register-accumulator (argument parse)
8597 MRAcc RdLo,RdHi,acc0. */
8602 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8604 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8607 /* Encoding functions relevant only to Thumb. */
8609 /* inst.operands[i] is a shifted-register operand; encode
8610 it into inst.instruction in the format used by Thumb32. */
8613 encode_thumb32_shifted_operand (int i
)
8615 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8616 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8618 constraint (inst
.operands
[i
].immisreg
,
8619 _("shift by register not allowed in thumb mode"));
8620 inst
.instruction
|= inst
.operands
[i
].reg
;
8621 if (shift
== SHIFT_RRX
)
8622 inst
.instruction
|= SHIFT_ROR
<< 4;
8625 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8626 _("expression too complex"));
8628 constraint (value
> 32
8629 || (value
== 32 && (shift
== SHIFT_LSL
8630 || shift
== SHIFT_ROR
)),
8631 _("shift expression is too large"));
8635 else if (value
== 32)
8638 inst
.instruction
|= shift
<< 4;
8639 inst
.instruction
|= (value
& 0x1c) << 10;
8640 inst
.instruction
|= (value
& 0x03) << 6;
8645 /* inst.operands[i] was set up by parse_address. Encode it into a
8646 Thumb32 format load or store instruction. Reject forms that cannot
8647 be used with such instructions. If is_t is true, reject forms that
8648 cannot be used with a T instruction; if is_d is true, reject forms
8649 that cannot be used with a D instruction. */
8652 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8654 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8656 constraint (!inst
.operands
[i
].isreg
,
8657 _("Instruction does not support =N addresses"));
8659 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8660 if (inst
.operands
[i
].immisreg
)
8662 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8663 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8664 constraint (inst
.operands
[i
].negative
,
8665 _("Thumb does not support negative register indexing"));
8666 constraint (inst
.operands
[i
].postind
,
8667 _("Thumb does not support register post-indexing"));
8668 constraint (inst
.operands
[i
].writeback
,
8669 _("Thumb does not support register indexing with writeback"));
8670 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8671 _("Thumb supports only LSL in shifted register indexing"));
8673 inst
.instruction
|= inst
.operands
[i
].imm
;
8674 if (inst
.operands
[i
].shifted
)
8676 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8677 _("expression too complex"));
8678 constraint (inst
.reloc
.exp
.X_add_number
< 0
8679 || inst
.reloc
.exp
.X_add_number
> 3,
8680 _("shift out of range"));
8681 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8683 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8685 else if (inst
.operands
[i
].preind
)
8687 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8688 _("cannot use writeback with PC-relative addressing"));
8689 constraint (is_t
&& inst
.operands
[i
].writeback
,
8690 _("cannot use writeback with this instruction"));
8694 inst
.instruction
|= 0x01000000;
8695 if (inst
.operands
[i
].writeback
)
8696 inst
.instruction
|= 0x00200000;
8700 inst
.instruction
|= 0x00000c00;
8701 if (inst
.operands
[i
].writeback
)
8702 inst
.instruction
|= 0x00000100;
8704 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8706 else if (inst
.operands
[i
].postind
)
8708 gas_assert (inst
.operands
[i
].writeback
);
8709 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8710 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8713 inst
.instruction
|= 0x00200000;
8715 inst
.instruction
|= 0x00000900;
8716 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8718 else /* unindexed - only for coprocessor */
8719 inst
.error
= _("instruction does not accept unindexed addressing");
8722 /* Table of Thumb instructions which exist in both 16- and 32-bit
8723 encodings (the latter only in post-V6T2 cores). The index is the
8724 value used in the insns table below. When there is more than one
8725 possible 16-bit encoding for the instruction, this table always
8727 Also contains several pseudo-instructions used during relaxation. */
8728 #define T16_32_TAB \
8729 X(_adc, 4140, eb400000), \
8730 X(_adcs, 4140, eb500000), \
8731 X(_add, 1c00, eb000000), \
8732 X(_adds, 1c00, eb100000), \
8733 X(_addi, 0000, f1000000), \
8734 X(_addis, 0000, f1100000), \
8735 X(_add_pc,000f, f20f0000), \
8736 X(_add_sp,000d, f10d0000), \
8737 X(_adr, 000f, f20f0000), \
8738 X(_and, 4000, ea000000), \
8739 X(_ands, 4000, ea100000), \
8740 X(_asr, 1000, fa40f000), \
8741 X(_asrs, 1000, fa50f000), \
8742 X(_b, e000, f000b000), \
8743 X(_bcond, d000, f0008000), \
8744 X(_bic, 4380, ea200000), \
8745 X(_bics, 4380, ea300000), \
8746 X(_cmn, 42c0, eb100f00), \
8747 X(_cmp, 2800, ebb00f00), \
8748 X(_cpsie, b660, f3af8400), \
8749 X(_cpsid, b670, f3af8600), \
8750 X(_cpy, 4600, ea4f0000), \
8751 X(_dec_sp,80dd, f1ad0d00), \
8752 X(_eor, 4040, ea800000), \
8753 X(_eors, 4040, ea900000), \
8754 X(_inc_sp,00dd, f10d0d00), \
8755 X(_ldmia, c800, e8900000), \
8756 X(_ldr, 6800, f8500000), \
8757 X(_ldrb, 7800, f8100000), \
8758 X(_ldrh, 8800, f8300000), \
8759 X(_ldrsb, 5600, f9100000), \
8760 X(_ldrsh, 5e00, f9300000), \
8761 X(_ldr_pc,4800, f85f0000), \
8762 X(_ldr_pc2,4800, f85f0000), \
8763 X(_ldr_sp,9800, f85d0000), \
8764 X(_lsl, 0000, fa00f000), \
8765 X(_lsls, 0000, fa10f000), \
8766 X(_lsr, 0800, fa20f000), \
8767 X(_lsrs, 0800, fa30f000), \
8768 X(_mov, 2000, ea4f0000), \
8769 X(_movs, 2000, ea5f0000), \
8770 X(_mul, 4340, fb00f000), \
8771 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8772 X(_mvn, 43c0, ea6f0000), \
8773 X(_mvns, 43c0, ea7f0000), \
8774 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8775 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8776 X(_orr, 4300, ea400000), \
8777 X(_orrs, 4300, ea500000), \
8778 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8779 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8780 X(_rev, ba00, fa90f080), \
8781 X(_rev16, ba40, fa90f090), \
8782 X(_revsh, bac0, fa90f0b0), \
8783 X(_ror, 41c0, fa60f000), \
8784 X(_rors, 41c0, fa70f000), \
8785 X(_sbc, 4180, eb600000), \
8786 X(_sbcs, 4180, eb700000), \
8787 X(_stmia, c000, e8800000), \
8788 X(_str, 6000, f8400000), \
8789 X(_strb, 7000, f8000000), \
8790 X(_strh, 8000, f8200000), \
8791 X(_str_sp,9000, f84d0000), \
8792 X(_sub, 1e00, eba00000), \
8793 X(_subs, 1e00, ebb00000), \
8794 X(_subi, 8000, f1a00000), \
8795 X(_subis, 8000, f1b00000), \
8796 X(_sxtb, b240, fa4ff080), \
8797 X(_sxth, b200, fa0ff080), \
8798 X(_tst, 4200, ea100f00), \
8799 X(_uxtb, b2c0, fa5ff080), \
8800 X(_uxth, b280, fa1ff080), \
8801 X(_nop, bf00, f3af8000), \
8802 X(_yield, bf10, f3af8001), \
8803 X(_wfe, bf20, f3af8002), \
8804 X(_wfi, bf30, f3af8003), \
8805 X(_sev, bf40, f3af8004),
8807 /* To catch errors in encoding functions, the codes are all offset by
8808 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8809 as 16-bit instructions. */
8810 #define X(a,b,c) T_MNEM##a
8811 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8814 #define X(a,b,c) 0x##b
8815 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8816 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8819 #define X(a,b,c) 0x##c
8820 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8821 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8822 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8826 /* Thumb instruction encoders, in alphabetical order. */
8831 do_t_add_sub_w (void)
8835 Rd
= inst
.operands
[0].reg
;
8836 Rn
= inst
.operands
[1].reg
;
8838 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8839 is the SP-{plus,minus}-immediate form of the instruction. */
8841 constraint (Rd
== REG_PC
, BAD_PC
);
8843 reject_bad_reg (Rd
);
8845 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8846 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8849 /* Parse an add or subtract instruction. We get here with inst.instruction
8850 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8857 Rd
= inst
.operands
[0].reg
;
8858 Rs
= (inst
.operands
[1].present
8859 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8860 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8863 set_it_insn_type_last ();
8871 flags
= (inst
.instruction
== T_MNEM_adds
8872 || inst
.instruction
== T_MNEM_subs
);
8874 narrow
= !in_it_block ();
8876 narrow
= in_it_block ();
8877 if (!inst
.operands
[2].isreg
)
8881 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8883 add
= (inst
.instruction
== T_MNEM_add
8884 || inst
.instruction
== T_MNEM_adds
);
8886 if (inst
.size_req
!= 4)
8888 /* Attempt to use a narrow opcode, with relaxation if
8890 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8891 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8892 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8893 opcode
= T_MNEM_add_sp
;
8894 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8895 opcode
= T_MNEM_add_pc
;
8896 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8899 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8901 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8905 inst
.instruction
= THUMB_OP16(opcode
);
8906 inst
.instruction
|= (Rd
<< 4) | Rs
;
8907 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8908 if (inst
.size_req
!= 2)
8909 inst
.relax
= opcode
;
8912 constraint (inst
.size_req
== 2, BAD_HIREG
);
8914 if (inst
.size_req
== 4
8915 || (inst
.size_req
!= 2 && !opcode
))
8919 constraint (add
, BAD_PC
);
8920 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8921 _("only SUBS PC, LR, #const allowed"));
8922 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8923 _("expression too complex"));
8924 constraint (inst
.reloc
.exp
.X_add_number
< 0
8925 || inst
.reloc
.exp
.X_add_number
> 0xff,
8926 _("immediate value out of range"));
8927 inst
.instruction
= T2_SUBS_PC_LR
8928 | inst
.reloc
.exp
.X_add_number
;
8929 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8932 else if (Rs
== REG_PC
)
8934 /* Always use addw/subw. */
8935 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8936 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8941 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8944 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8946 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8948 inst
.instruction
|= Rd
<< 8;
8949 inst
.instruction
|= Rs
<< 16;
8954 Rn
= inst
.operands
[2].reg
;
8955 /* See if we can do this with a 16-bit instruction. */
8956 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8958 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8963 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8964 || inst
.instruction
== T_MNEM_add
)
8967 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8971 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8973 /* Thumb-1 cores (except v6-M) require at least one high
8974 register in a narrow non flag setting add. */
8975 if (Rd
> 7 || Rn
> 7
8976 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8977 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8984 inst
.instruction
= T_OPCODE_ADD_HI
;
8985 inst
.instruction
|= (Rd
& 8) << 4;
8986 inst
.instruction
|= (Rd
& 7);
8987 inst
.instruction
|= Rn
<< 3;
8993 constraint (Rd
== REG_PC
, BAD_PC
);
8994 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8995 constraint (Rs
== REG_PC
, BAD_PC
);
8996 reject_bad_reg (Rn
);
8998 /* If we get here, it can't be done in 16 bits. */
8999 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9000 _("shift must be constant"));
9001 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9002 inst
.instruction
|= Rd
<< 8;
9003 inst
.instruction
|= Rs
<< 16;
9004 encode_thumb32_shifted_operand (2);
9009 constraint (inst
.instruction
== T_MNEM_adds
9010 || inst
.instruction
== T_MNEM_subs
,
9013 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9015 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9016 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9019 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9021 inst
.instruction
|= (Rd
<< 4) | Rs
;
9022 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9026 Rn
= inst
.operands
[2].reg
;
9027 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9029 /* We now have Rd, Rs, and Rn set to registers. */
9030 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9032 /* Can't do this for SUB. */
9033 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9034 inst
.instruction
= T_OPCODE_ADD_HI
;
9035 inst
.instruction
|= (Rd
& 8) << 4;
9036 inst
.instruction
|= (Rd
& 7);
9038 inst
.instruction
|= Rn
<< 3;
9040 inst
.instruction
|= Rs
<< 3;
9042 constraint (1, _("dest must overlap one source register"));
9046 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9047 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9048 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9058 Rd
= inst
.operands
[0].reg
;
9059 reject_bad_reg (Rd
);
9061 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9063 /* Defer to section relaxation. */
9064 inst
.relax
= inst
.instruction
;
9065 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9066 inst
.instruction
|= Rd
<< 4;
9068 else if (unified_syntax
&& inst
.size_req
!= 2)
9070 /* Generate a 32-bit opcode. */
9071 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9072 inst
.instruction
|= Rd
<< 8;
9073 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9074 inst
.reloc
.pc_rel
= 1;
9078 /* Generate a 16-bit opcode. */
9079 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9080 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9081 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9082 inst
.reloc
.pc_rel
= 1;
9084 inst
.instruction
|= Rd
<< 4;
9088 /* Arithmetic instructions for which there is just one 16-bit
9089 instruction encoding, and it allows only two low registers.
9090 For maximal compatibility with ARM syntax, we allow three register
9091 operands even when Thumb-32 instructions are not available, as long
9092 as the first two are identical. For instance, both "sbc r0,r1" and
9093 "sbc r0,r0,r1" are allowed. */
9099 Rd
= inst
.operands
[0].reg
;
9100 Rs
= (inst
.operands
[1].present
9101 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9102 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9103 Rn
= inst
.operands
[2].reg
;
9105 reject_bad_reg (Rd
);
9106 reject_bad_reg (Rs
);
9107 if (inst
.operands
[2].isreg
)
9108 reject_bad_reg (Rn
);
9112 if (!inst
.operands
[2].isreg
)
9114 /* For an immediate, we always generate a 32-bit opcode;
9115 section relaxation will shrink it later if possible. */
9116 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9117 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9118 inst
.instruction
|= Rd
<< 8;
9119 inst
.instruction
|= Rs
<< 16;
9120 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9126 /* See if we can do this with a 16-bit instruction. */
9127 if (THUMB_SETS_FLAGS (inst
.instruction
))
9128 narrow
= !in_it_block ();
9130 narrow
= in_it_block ();
9132 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9134 if (inst
.operands
[2].shifted
)
9136 if (inst
.size_req
== 4)
9142 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9143 inst
.instruction
|= Rd
;
9144 inst
.instruction
|= Rn
<< 3;
9148 /* If we get here, it can't be done in 16 bits. */
9149 constraint (inst
.operands
[2].shifted
9150 && inst
.operands
[2].immisreg
,
9151 _("shift must be constant"));
9152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9153 inst
.instruction
|= Rd
<< 8;
9154 inst
.instruction
|= Rs
<< 16;
9155 encode_thumb32_shifted_operand (2);
9160 /* On its face this is a lie - the instruction does set the
9161 flags. However, the only supported mnemonic in this mode
9163 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9165 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9166 _("unshifted register required"));
9167 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9168 constraint (Rd
!= Rs
,
9169 _("dest and source1 must be the same register"));
9171 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9172 inst
.instruction
|= Rd
;
9173 inst
.instruction
|= Rn
<< 3;
9177 /* Similarly, but for instructions where the arithmetic operation is
9178 commutative, so we can allow either of them to be different from
9179 the destination operand in a 16-bit instruction. For instance, all
9180 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9187 Rd
= inst
.operands
[0].reg
;
9188 Rs
= (inst
.operands
[1].present
9189 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9190 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9191 Rn
= inst
.operands
[2].reg
;
9193 reject_bad_reg (Rd
);
9194 reject_bad_reg (Rs
);
9195 if (inst
.operands
[2].isreg
)
9196 reject_bad_reg (Rn
);
9200 if (!inst
.operands
[2].isreg
)
9202 /* For an immediate, we always generate a 32-bit opcode;
9203 section relaxation will shrink it later if possible. */
9204 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9205 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9206 inst
.instruction
|= Rd
<< 8;
9207 inst
.instruction
|= Rs
<< 16;
9208 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9214 /* See if we can do this with a 16-bit instruction. */
9215 if (THUMB_SETS_FLAGS (inst
.instruction
))
9216 narrow
= !in_it_block ();
9218 narrow
= in_it_block ();
9220 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9222 if (inst
.operands
[2].shifted
)
9224 if (inst
.size_req
== 4)
9231 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9232 inst
.instruction
|= Rd
;
9233 inst
.instruction
|= Rn
<< 3;
9238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9239 inst
.instruction
|= Rd
;
9240 inst
.instruction
|= Rs
<< 3;
9245 /* If we get here, it can't be done in 16 bits. */
9246 constraint (inst
.operands
[2].shifted
9247 && inst
.operands
[2].immisreg
,
9248 _("shift must be constant"));
9249 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9250 inst
.instruction
|= Rd
<< 8;
9251 inst
.instruction
|= Rs
<< 16;
9252 encode_thumb32_shifted_operand (2);
9257 /* On its face this is a lie - the instruction does set the
9258 flags. However, the only supported mnemonic in this mode
9260 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9262 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9263 _("unshifted register required"));
9264 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9266 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9267 inst
.instruction
|= Rd
;
9270 inst
.instruction
|= Rn
<< 3;
9272 inst
.instruction
|= Rs
<< 3;
9274 constraint (1, _("dest must overlap one source register"));
9281 if (inst
.operands
[0].present
)
9283 constraint ((inst
.instruction
& 0xf0) != 0x40
9284 && inst
.operands
[0].imm
!= 0xf,
9285 _("bad barrier type"));
9286 inst
.instruction
|= inst
.operands
[0].imm
;
9289 inst
.instruction
|= 0xf;
9296 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9297 constraint (msb
> 32, _("bit-field extends past end of register"));
9298 /* The instruction encoding stores the LSB and MSB,
9299 not the LSB and width. */
9300 Rd
= inst
.operands
[0].reg
;
9301 reject_bad_reg (Rd
);
9302 inst
.instruction
|= Rd
<< 8;
9303 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9304 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9305 inst
.instruction
|= msb
- 1;
9314 Rd
= inst
.operands
[0].reg
;
9315 reject_bad_reg (Rd
);
9317 /* #0 in second position is alternative syntax for bfc, which is
9318 the same instruction but with REG_PC in the Rm field. */
9319 if (!inst
.operands
[1].isreg
)
9323 Rn
= inst
.operands
[1].reg
;
9324 reject_bad_reg (Rn
);
9327 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9328 constraint (msb
> 32, _("bit-field extends past end of register"));
9329 /* The instruction encoding stores the LSB and MSB,
9330 not the LSB and width. */
9331 inst
.instruction
|= Rd
<< 8;
9332 inst
.instruction
|= Rn
<< 16;
9333 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9334 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9335 inst
.instruction
|= msb
- 1;
9343 Rd
= inst
.operands
[0].reg
;
9344 Rn
= inst
.operands
[1].reg
;
9346 reject_bad_reg (Rd
);
9347 reject_bad_reg (Rn
);
9349 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9350 _("bit-field extends past end of register"));
9351 inst
.instruction
|= Rd
<< 8;
9352 inst
.instruction
|= Rn
<< 16;
9353 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9354 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9355 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9358 /* ARM V5 Thumb BLX (argument parse)
9359 BLX <target_addr> which is BLX(1)
9360 BLX <Rm> which is BLX(2)
9361 Unfortunately, there are two different opcodes for this mnemonic.
9362 So, the insns[].value is not used, and the code here zaps values
9363 into inst.instruction.
9365 ??? How to take advantage of the additional two bits of displacement
9366 available in Thumb32 mode? Need new relocation? */
9371 set_it_insn_type_last ();
9373 if (inst
.operands
[0].isreg
)
9375 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9376 /* We have a register, so this is BLX(2). */
9377 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9381 /* No register. This must be BLX(1). */
9382 inst
.instruction
= 0xf000e800;
9383 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9384 inst
.reloc
.pc_rel
= 1;
9395 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9399 /* Conditional branches inside IT blocks are encoded as unconditional
9406 if (cond
!= COND_ALWAYS
)
9407 opcode
= T_MNEM_bcond
;
9409 opcode
= inst
.instruction
;
9411 if (unified_syntax
&& inst
.size_req
== 4)
9413 inst
.instruction
= THUMB_OP32(opcode
);
9414 if (cond
== COND_ALWAYS
)
9415 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9418 gas_assert (cond
!= 0xF);
9419 inst
.instruction
|= cond
<< 22;
9420 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9425 inst
.instruction
= THUMB_OP16(opcode
);
9426 if (cond
== COND_ALWAYS
)
9427 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9430 inst
.instruction
|= cond
<< 8;
9431 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9433 /* Allow section relaxation. */
9434 if (unified_syntax
&& inst
.size_req
!= 2)
9435 inst
.relax
= opcode
;
9438 inst
.reloc
.pc_rel
= 1;
9444 constraint (inst
.cond
!= COND_ALWAYS
,
9445 _("instruction is always unconditional"));
9446 if (inst
.operands
[0].present
)
9448 constraint (inst
.operands
[0].imm
> 255,
9449 _("immediate value out of range"));
9450 inst
.instruction
|= inst
.operands
[0].imm
;
9451 set_it_insn_type (NEUTRAL_IT_INSN
);
9456 do_t_branch23 (void)
9458 set_it_insn_type_last ();
9459 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9460 inst
.reloc
.pc_rel
= 1;
9462 #if defined(OBJ_COFF)
9463 /* If the destination of the branch is a defined symbol which does not have
9464 the THUMB_FUNC attribute, then we must be calling a function which has
9465 the (interfacearm) attribute. We look for the Thumb entry point to that
9466 function and change the branch to refer to that function instead. */
9467 if ( inst
.reloc
.exp
.X_op
== O_symbol
9468 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9469 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9470 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9471 inst
.reloc
.exp
.X_add_symbol
=
9472 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9479 set_it_insn_type_last ();
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9481 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9482 should cause the alignment to be checked once it is known. This is
9483 because BX PC only works if the instruction is word aligned. */
9491 set_it_insn_type_last ();
9492 Rm
= inst
.operands
[0].reg
;
9493 reject_bad_reg (Rm
);
9494 inst
.instruction
|= Rm
<< 16;
9503 Rd
= inst
.operands
[0].reg
;
9504 Rm
= inst
.operands
[1].reg
;
9506 reject_bad_reg (Rd
);
9507 reject_bad_reg (Rm
);
9509 inst
.instruction
|= Rd
<< 8;
9510 inst
.instruction
|= Rm
<< 16;
9511 inst
.instruction
|= Rm
;
9517 set_it_insn_type (OUTSIDE_IT_INSN
);
9518 inst
.instruction
|= inst
.operands
[0].imm
;
9524 set_it_insn_type (OUTSIDE_IT_INSN
);
9526 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9527 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9529 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9530 inst
.instruction
= 0xf3af8000;
9531 inst
.instruction
|= imod
<< 9;
9532 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9533 if (inst
.operands
[1].present
)
9534 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9538 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9539 && (inst
.operands
[0].imm
& 4),
9540 _("selected processor does not support 'A' form "
9541 "of this instruction"));
9542 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9543 _("Thumb does not support the 2-argument "
9544 "form of this instruction"));
9545 inst
.instruction
|= inst
.operands
[0].imm
;
9549 /* THUMB CPY instruction (argument parse). */
9554 if (inst
.size_req
== 4)
9556 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9557 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9558 inst
.instruction
|= inst
.operands
[1].reg
;
9562 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9563 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9564 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9571 set_it_insn_type (OUTSIDE_IT_INSN
);
9572 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9573 inst
.instruction
|= inst
.operands
[0].reg
;
9574 inst
.reloc
.pc_rel
= 1;
9575 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9581 inst
.instruction
|= inst
.operands
[0].imm
;
9587 unsigned Rd
, Rn
, Rm
;
9589 Rd
= inst
.operands
[0].reg
;
9590 Rn
= (inst
.operands
[1].present
9591 ? inst
.operands
[1].reg
: Rd
);
9592 Rm
= inst
.operands
[2].reg
;
9594 reject_bad_reg (Rd
);
9595 reject_bad_reg (Rn
);
9596 reject_bad_reg (Rm
);
9598 inst
.instruction
|= Rd
<< 8;
9599 inst
.instruction
|= Rn
<< 16;
9600 inst
.instruction
|= Rm
;
9606 if (unified_syntax
&& inst
.size_req
== 4)
9607 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9615 unsigned int cond
= inst
.operands
[0].imm
;
9617 set_it_insn_type (IT_INSN
);
9618 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9621 /* If the condition is a negative condition, invert the mask. */
9622 if ((cond
& 0x1) == 0x0)
9624 unsigned int mask
= inst
.instruction
& 0x000f;
9626 if ((mask
& 0x7) == 0)
9627 /* no conversion needed */;
9628 else if ((mask
& 0x3) == 0)
9630 else if ((mask
& 0x1) == 0)
9635 inst
.instruction
&= 0xfff0;
9636 inst
.instruction
|= mask
;
9639 inst
.instruction
|= cond
<< 4;
9642 /* Helper function used for both push/pop and ldm/stm. */
9644 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9648 load
= (inst
.instruction
& (1 << 20)) != 0;
9650 if (mask
& (1 << 13))
9651 inst
.error
= _("SP not allowed in register list");
9654 if (mask
& (1 << 15))
9656 if (mask
& (1 << 14))
9657 inst
.error
= _("LR and PC should not both be in register list");
9659 set_it_insn_type_last ();
9662 if ((mask
& (1 << base
)) != 0
9664 as_warn (_("base register should not be in register list "
9665 "when written back"));
9669 if (mask
& (1 << 15))
9670 inst
.error
= _("PC not allowed in register list");
9672 if (mask
& (1 << base
))
9673 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9676 if ((mask
& (mask
- 1)) == 0)
9678 /* Single register transfers implemented as str/ldr. */
9681 if (inst
.instruction
& (1 << 23))
9682 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9684 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9688 if (inst
.instruction
& (1 << 23))
9689 inst
.instruction
= 0x00800000; /* ia -> [base] */
9691 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9694 inst
.instruction
|= 0xf8400000;
9696 inst
.instruction
|= 0x00100000;
9698 mask
= ffs (mask
) - 1;
9702 inst
.instruction
|= WRITE_BACK
;
9704 inst
.instruction
|= mask
;
9705 inst
.instruction
|= base
<< 16;
9711 /* This really doesn't seem worth it. */
9712 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9713 _("expression too complex"));
9714 constraint (inst
.operands
[1].writeback
,
9715 _("Thumb load/store multiple does not support {reglist}^"));
9723 /* See if we can use a 16-bit instruction. */
9724 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9725 && inst
.size_req
!= 4
9726 && !(inst
.operands
[1].imm
& ~0xff))
9728 mask
= 1 << inst
.operands
[0].reg
;
9730 if (inst
.operands
[0].reg
<= 7
9731 && (inst
.instruction
== T_MNEM_stmia
9732 ? inst
.operands
[0].writeback
9733 : (inst
.operands
[0].writeback
9734 == !(inst
.operands
[1].imm
& mask
))))
9736 if (inst
.instruction
== T_MNEM_stmia
9737 && (inst
.operands
[1].imm
& mask
)
9738 && (inst
.operands
[1].imm
& (mask
- 1)))
9739 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9740 inst
.operands
[0].reg
);
9742 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9743 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9744 inst
.instruction
|= inst
.operands
[1].imm
;
9747 else if (inst
.operands
[0] .reg
== REG_SP
9748 && inst
.operands
[0].writeback
)
9750 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9751 ? T_MNEM_push
: T_MNEM_pop
);
9752 inst
.instruction
|= inst
.operands
[1].imm
;
9759 if (inst
.instruction
< 0xffff)
9760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9762 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9763 inst
.operands
[0].writeback
);
9768 constraint (inst
.operands
[0].reg
> 7
9769 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9770 constraint (inst
.instruction
!= T_MNEM_ldmia
9771 && inst
.instruction
!= T_MNEM_stmia
,
9772 _("Thumb-2 instruction only valid in unified syntax"));
9773 if (inst
.instruction
== T_MNEM_stmia
)
9775 if (!inst
.operands
[0].writeback
)
9776 as_warn (_("this instruction will write back the base register"));
9777 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9778 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9779 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9780 inst
.operands
[0].reg
);
9784 if (!inst
.operands
[0].writeback
9785 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9786 as_warn (_("this instruction will write back the base register"));
9787 else if (inst
.operands
[0].writeback
9788 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9789 as_warn (_("this instruction will not write back the base register"));
9792 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9793 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9794 inst
.instruction
|= inst
.operands
[1].imm
;
9801 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9802 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9803 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9804 || inst
.operands
[1].negative
,
9807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9808 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9809 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9815 if (!inst
.operands
[1].present
)
9817 constraint (inst
.operands
[0].reg
== REG_LR
,
9818 _("r14 not allowed as first register "
9819 "when second register is omitted"));
9820 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9822 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9826 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9827 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9833 unsigned long opcode
;
9836 if (inst
.operands
[0].isreg
9837 && !inst
.operands
[0].preind
9838 && inst
.operands
[0].reg
== REG_PC
)
9839 set_it_insn_type_last ();
9841 opcode
= inst
.instruction
;
9844 if (!inst
.operands
[1].isreg
)
9846 if (opcode
<= 0xffff)
9847 inst
.instruction
= THUMB_OP32 (opcode
);
9848 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9851 if (inst
.operands
[1].isreg
9852 && !inst
.operands
[1].writeback
9853 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9854 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9856 && inst
.size_req
!= 4)
9858 /* Insn may have a 16-bit form. */
9859 Rn
= inst
.operands
[1].reg
;
9860 if (inst
.operands
[1].immisreg
)
9862 inst
.instruction
= THUMB_OP16 (opcode
);
9864 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9867 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9868 && opcode
!= T_MNEM_ldrsb
)
9869 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9870 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9877 if (inst
.reloc
.pc_rel
)
9878 opcode
= T_MNEM_ldr_pc2
;
9880 opcode
= T_MNEM_ldr_pc
;
9884 if (opcode
== T_MNEM_ldr
)
9885 opcode
= T_MNEM_ldr_sp
;
9887 opcode
= T_MNEM_str_sp
;
9889 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9893 inst
.instruction
= inst
.operands
[0].reg
;
9894 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9896 inst
.instruction
|= THUMB_OP16 (opcode
);
9897 if (inst
.size_req
== 2)
9898 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9900 inst
.relax
= opcode
;
9904 /* Definitely a 32-bit variant. */
9905 inst
.instruction
= THUMB_OP32 (opcode
);
9906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9907 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9911 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9913 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9915 /* Only [Rn,Rm] is acceptable. */
9916 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9917 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9918 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9919 || inst
.operands
[1].negative
,
9920 _("Thumb does not support this addressing mode"));
9921 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9925 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9926 if (!inst
.operands
[1].isreg
)
9927 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9930 constraint (!inst
.operands
[1].preind
9931 || inst
.operands
[1].shifted
9932 || inst
.operands
[1].writeback
,
9933 _("Thumb does not support this addressing mode"));
9934 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9936 constraint (inst
.instruction
& 0x0600,
9937 _("byte or halfword not valid for base register"));
9938 constraint (inst
.operands
[1].reg
== REG_PC
9939 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9940 _("r15 based store not allowed"));
9941 constraint (inst
.operands
[1].immisreg
,
9942 _("invalid base register for register offset"));
9944 if (inst
.operands
[1].reg
== REG_PC
)
9945 inst
.instruction
= T_OPCODE_LDR_PC
;
9946 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9947 inst
.instruction
= T_OPCODE_LDR_SP
;
9949 inst
.instruction
= T_OPCODE_STR_SP
;
9951 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9952 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9956 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9957 if (!inst
.operands
[1].immisreg
)
9959 /* Immediate offset. */
9960 inst
.instruction
|= inst
.operands
[0].reg
;
9961 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9962 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9966 /* Register offset. */
9967 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9968 constraint (inst
.operands
[1].negative
,
9969 _("Thumb does not support this addressing mode"));
9972 switch (inst
.instruction
)
9974 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9975 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9976 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9977 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9978 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9979 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9980 case 0x5600 /* ldrsb */:
9981 case 0x5e00 /* ldrsh */: break;
9985 inst
.instruction
|= inst
.operands
[0].reg
;
9986 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9987 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9993 if (!inst
.operands
[1].present
)
9995 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9996 constraint (inst
.operands
[0].reg
== REG_LR
,
9997 _("r14 not allowed here"));
9999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10000 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10001 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10008 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10014 unsigned Rd
, Rn
, Rm
, Ra
;
10016 Rd
= inst
.operands
[0].reg
;
10017 Rn
= inst
.operands
[1].reg
;
10018 Rm
= inst
.operands
[2].reg
;
10019 Ra
= inst
.operands
[3].reg
;
10021 reject_bad_reg (Rd
);
10022 reject_bad_reg (Rn
);
10023 reject_bad_reg (Rm
);
10024 reject_bad_reg (Ra
);
10026 inst
.instruction
|= Rd
<< 8;
10027 inst
.instruction
|= Rn
<< 16;
10028 inst
.instruction
|= Rm
;
10029 inst
.instruction
|= Ra
<< 12;
10035 unsigned RdLo
, RdHi
, Rn
, Rm
;
10037 RdLo
= inst
.operands
[0].reg
;
10038 RdHi
= inst
.operands
[1].reg
;
10039 Rn
= inst
.operands
[2].reg
;
10040 Rm
= inst
.operands
[3].reg
;
10042 reject_bad_reg (RdLo
);
10043 reject_bad_reg (RdHi
);
10044 reject_bad_reg (Rn
);
10045 reject_bad_reg (Rm
);
10047 inst
.instruction
|= RdLo
<< 12;
10048 inst
.instruction
|= RdHi
<< 8;
10049 inst
.instruction
|= Rn
<< 16;
10050 inst
.instruction
|= Rm
;
10054 do_t_mov_cmp (void)
10058 Rn
= inst
.operands
[0].reg
;
10059 Rm
= inst
.operands
[1].reg
;
10062 set_it_insn_type_last ();
10064 if (unified_syntax
)
10066 int r0off
= (inst
.instruction
== T_MNEM_mov
10067 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10068 unsigned long opcode
;
10069 bfd_boolean narrow
;
10070 bfd_boolean low_regs
;
10072 low_regs
= (Rn
<= 7 && Rm
<= 7);
10073 opcode
= inst
.instruction
;
10074 if (in_it_block ())
10075 narrow
= opcode
!= T_MNEM_movs
;
10077 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10078 if (inst
.size_req
== 4
10079 || inst
.operands
[1].shifted
)
10082 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10083 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10084 && !inst
.operands
[1].shifted
10088 inst
.instruction
= T2_SUBS_PC_LR
;
10092 if (opcode
== T_MNEM_cmp
)
10094 constraint (Rn
== REG_PC
, BAD_PC
);
10097 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10099 warn_deprecated_sp (Rm
);
10100 /* R15 was documented as a valid choice for Rm in ARMv6,
10101 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10102 tools reject R15, so we do too. */
10103 constraint (Rm
== REG_PC
, BAD_PC
);
10106 reject_bad_reg (Rm
);
10108 else if (opcode
== T_MNEM_mov
10109 || opcode
== T_MNEM_movs
)
10111 if (inst
.operands
[1].isreg
)
10113 if (opcode
== T_MNEM_movs
)
10115 reject_bad_reg (Rn
);
10116 reject_bad_reg (Rm
);
10118 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10119 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10120 reject_bad_reg (Rm
);
10123 reject_bad_reg (Rn
);
10126 if (!inst
.operands
[1].isreg
)
10128 /* Immediate operand. */
10129 if (!in_it_block () && opcode
== T_MNEM_mov
)
10131 if (low_regs
&& narrow
)
10133 inst
.instruction
= THUMB_OP16 (opcode
);
10134 inst
.instruction
|= Rn
<< 8;
10135 if (inst
.size_req
== 2)
10136 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10138 inst
.relax
= opcode
;
10142 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10143 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10144 inst
.instruction
|= Rn
<< r0off
;
10145 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10148 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10149 && (inst
.instruction
== T_MNEM_mov
10150 || inst
.instruction
== T_MNEM_movs
))
10152 /* Register shifts are encoded as separate shift instructions. */
10153 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10155 if (in_it_block ())
10160 if (inst
.size_req
== 4)
10163 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10169 switch (inst
.operands
[1].shift_kind
)
10172 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10175 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10178 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10181 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10187 inst
.instruction
= opcode
;
10190 inst
.instruction
|= Rn
;
10191 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10196 inst
.instruction
|= CONDS_BIT
;
10198 inst
.instruction
|= Rn
<< 8;
10199 inst
.instruction
|= Rm
<< 16;
10200 inst
.instruction
|= inst
.operands
[1].imm
;
10205 /* Some mov with immediate shift have narrow variants.
10206 Register shifts are handled above. */
10207 if (low_regs
&& inst
.operands
[1].shifted
10208 && (inst
.instruction
== T_MNEM_mov
10209 || inst
.instruction
== T_MNEM_movs
))
10211 if (in_it_block ())
10212 narrow
= (inst
.instruction
== T_MNEM_mov
);
10214 narrow
= (inst
.instruction
== T_MNEM_movs
);
10219 switch (inst
.operands
[1].shift_kind
)
10221 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10222 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10223 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10224 default: narrow
= FALSE
; break;
10230 inst
.instruction
|= Rn
;
10231 inst
.instruction
|= Rm
<< 3;
10232 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10236 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10237 inst
.instruction
|= Rn
<< r0off
;
10238 encode_thumb32_shifted_operand (1);
10242 switch (inst
.instruction
)
10245 inst
.instruction
= T_OPCODE_MOV_HR
;
10246 inst
.instruction
|= (Rn
& 0x8) << 4;
10247 inst
.instruction
|= (Rn
& 0x7);
10248 inst
.instruction
|= Rm
<< 3;
10252 /* We know we have low registers at this point.
10253 Generate ADD Rd, Rs, #0. */
10254 inst
.instruction
= T_OPCODE_ADD_I3
;
10255 inst
.instruction
|= Rn
;
10256 inst
.instruction
|= Rm
<< 3;
10262 inst
.instruction
= T_OPCODE_CMP_LR
;
10263 inst
.instruction
|= Rn
;
10264 inst
.instruction
|= Rm
<< 3;
10268 inst
.instruction
= T_OPCODE_CMP_HR
;
10269 inst
.instruction
|= (Rn
& 0x8) << 4;
10270 inst
.instruction
|= (Rn
& 0x7);
10271 inst
.instruction
|= Rm
<< 3;
10278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10280 /* PR 10443: Do not silently ignore shifted operands. */
10281 constraint (inst
.operands
[1].shifted
,
10282 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10284 if (inst
.operands
[1].isreg
)
10286 if (Rn
< 8 && Rm
< 8)
10288 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10289 since a MOV instruction produces unpredictable results. */
10290 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10291 inst
.instruction
= T_OPCODE_ADD_I3
;
10293 inst
.instruction
= T_OPCODE_CMP_LR
;
10295 inst
.instruction
|= Rn
;
10296 inst
.instruction
|= Rm
<< 3;
10300 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10301 inst
.instruction
= T_OPCODE_MOV_HR
;
10303 inst
.instruction
= T_OPCODE_CMP_HR
;
10309 constraint (Rn
> 7,
10310 _("only lo regs allowed with immediate"));
10311 inst
.instruction
|= Rn
<< 8;
10312 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10323 top
= (inst
.instruction
& 0x00800000) != 0;
10324 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10326 constraint (top
, _(":lower16: not allowed this instruction"));
10327 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10329 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10331 constraint (!top
, _(":upper16: not allowed this instruction"));
10332 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10335 Rd
= inst
.operands
[0].reg
;
10336 reject_bad_reg (Rd
);
10338 inst
.instruction
|= Rd
<< 8;
10339 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10341 imm
= inst
.reloc
.exp
.X_add_number
;
10342 inst
.instruction
|= (imm
& 0xf000) << 4;
10343 inst
.instruction
|= (imm
& 0x0800) << 15;
10344 inst
.instruction
|= (imm
& 0x0700) << 4;
10345 inst
.instruction
|= (imm
& 0x00ff);
10350 do_t_mvn_tst (void)
10354 Rn
= inst
.operands
[0].reg
;
10355 Rm
= inst
.operands
[1].reg
;
10357 if (inst
.instruction
== T_MNEM_cmp
10358 || inst
.instruction
== T_MNEM_cmn
)
10359 constraint (Rn
== REG_PC
, BAD_PC
);
10361 reject_bad_reg (Rn
);
10362 reject_bad_reg (Rm
);
10364 if (unified_syntax
)
10366 int r0off
= (inst
.instruction
== T_MNEM_mvn
10367 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10368 bfd_boolean narrow
;
10370 if (inst
.size_req
== 4
10371 || inst
.instruction
> 0xffff
10372 || inst
.operands
[1].shifted
10373 || Rn
> 7 || Rm
> 7)
10375 else if (inst
.instruction
== T_MNEM_cmn
)
10377 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10378 narrow
= !in_it_block ();
10380 narrow
= in_it_block ();
10382 if (!inst
.operands
[1].isreg
)
10384 /* For an immediate, we always generate a 32-bit opcode;
10385 section relaxation will shrink it later if possible. */
10386 if (inst
.instruction
< 0xffff)
10387 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10388 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10389 inst
.instruction
|= Rn
<< r0off
;
10390 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10394 /* See if we can do this with a 16-bit instruction. */
10397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10398 inst
.instruction
|= Rn
;
10399 inst
.instruction
|= Rm
<< 3;
10403 constraint (inst
.operands
[1].shifted
10404 && inst
.operands
[1].immisreg
,
10405 _("shift must be constant"));
10406 if (inst
.instruction
< 0xffff)
10407 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10408 inst
.instruction
|= Rn
<< r0off
;
10409 encode_thumb32_shifted_operand (1);
10415 constraint (inst
.instruction
> 0xffff
10416 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10417 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10418 _("unshifted register required"));
10419 constraint (Rn
> 7 || Rm
> 7,
10422 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10423 inst
.instruction
|= Rn
;
10424 inst
.instruction
|= Rm
<< 3;
10434 if (do_vfp_nsyn_mrs () == SUCCESS
)
10437 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10440 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10441 _("selected processor does not support "
10442 "requested special purpose register"));
10446 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10447 _("selected processor does not support "
10448 "requested special purpose register"));
10449 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10450 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10451 _("'CPSR' or 'SPSR' expected"));
10454 Rd
= inst
.operands
[0].reg
;
10455 reject_bad_reg (Rd
);
10457 inst
.instruction
|= Rd
<< 8;
10458 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10459 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10468 if (do_vfp_nsyn_msr () == SUCCESS
)
10471 constraint (!inst
.operands
[1].isreg
,
10472 _("Thumb encoding does not support an immediate here"));
10473 flags
= inst
.operands
[0].imm
;
10476 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10477 _("selected processor does not support "
10478 "requested special purpose register"));
10482 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10483 _("selected processor does not support "
10484 "requested special purpose register"));
10488 Rn
= inst
.operands
[1].reg
;
10489 reject_bad_reg (Rn
);
10491 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10492 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10493 inst
.instruction
|= (flags
& 0xff);
10494 inst
.instruction
|= Rn
<< 16;
10500 bfd_boolean narrow
;
10501 unsigned Rd
, Rn
, Rm
;
10503 if (!inst
.operands
[2].present
)
10504 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10506 Rd
= inst
.operands
[0].reg
;
10507 Rn
= inst
.operands
[1].reg
;
10508 Rm
= inst
.operands
[2].reg
;
10510 if (unified_syntax
)
10512 if (inst
.size_req
== 4
10518 else if (inst
.instruction
== T_MNEM_muls
)
10519 narrow
= !in_it_block ();
10521 narrow
= in_it_block ();
10525 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10526 constraint (Rn
> 7 || Rm
> 7,
10533 /* 16-bit MULS/Conditional MUL. */
10534 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10535 inst
.instruction
|= Rd
;
10538 inst
.instruction
|= Rm
<< 3;
10540 inst
.instruction
|= Rn
<< 3;
10542 constraint (1, _("dest must overlap one source register"));
10546 constraint (inst
.instruction
!= T_MNEM_mul
,
10547 _("Thumb-2 MUL must not set flags"));
10549 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10550 inst
.instruction
|= Rd
<< 8;
10551 inst
.instruction
|= Rn
<< 16;
10552 inst
.instruction
|= Rm
<< 0;
10554 reject_bad_reg (Rd
);
10555 reject_bad_reg (Rn
);
10556 reject_bad_reg (Rm
);
10563 unsigned RdLo
, RdHi
, Rn
, Rm
;
10565 RdLo
= inst
.operands
[0].reg
;
10566 RdHi
= inst
.operands
[1].reg
;
10567 Rn
= inst
.operands
[2].reg
;
10568 Rm
= inst
.operands
[3].reg
;
10570 reject_bad_reg (RdLo
);
10571 reject_bad_reg (RdHi
);
10572 reject_bad_reg (Rn
);
10573 reject_bad_reg (Rm
);
10575 inst
.instruction
|= RdLo
<< 12;
10576 inst
.instruction
|= RdHi
<< 8;
10577 inst
.instruction
|= Rn
<< 16;
10578 inst
.instruction
|= Rm
;
10581 as_tsktsk (_("rdhi and rdlo must be different"));
10587 set_it_insn_type (NEUTRAL_IT_INSN
);
10589 if (unified_syntax
)
10591 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10593 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10594 inst
.instruction
|= inst
.operands
[0].imm
;
10598 /* PR9722: Check for Thumb2 availability before
10599 generating a thumb2 nop instruction. */
10600 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10602 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10603 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10606 inst
.instruction
= 0x46c0;
10611 constraint (inst
.operands
[0].present
,
10612 _("Thumb does not support NOP with hints"));
10613 inst
.instruction
= 0x46c0;
10620 if (unified_syntax
)
10622 bfd_boolean narrow
;
10624 if (THUMB_SETS_FLAGS (inst
.instruction
))
10625 narrow
= !in_it_block ();
10627 narrow
= in_it_block ();
10628 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10630 if (inst
.size_req
== 4)
10635 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10636 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10637 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10641 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10642 inst
.instruction
|= inst
.operands
[0].reg
;
10643 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10648 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10650 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10652 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10653 inst
.instruction
|= inst
.operands
[0].reg
;
10654 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10663 Rd
= inst
.operands
[0].reg
;
10664 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10666 reject_bad_reg (Rd
);
10667 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10668 reject_bad_reg (Rn
);
10670 inst
.instruction
|= Rd
<< 8;
10671 inst
.instruction
|= Rn
<< 16;
10673 if (!inst
.operands
[2].isreg
)
10675 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10676 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10682 Rm
= inst
.operands
[2].reg
;
10683 reject_bad_reg (Rm
);
10685 constraint (inst
.operands
[2].shifted
10686 && inst
.operands
[2].immisreg
,
10687 _("shift must be constant"));
10688 encode_thumb32_shifted_operand (2);
10695 unsigned Rd
, Rn
, Rm
;
10697 Rd
= inst
.operands
[0].reg
;
10698 Rn
= inst
.operands
[1].reg
;
10699 Rm
= inst
.operands
[2].reg
;
10701 reject_bad_reg (Rd
);
10702 reject_bad_reg (Rn
);
10703 reject_bad_reg (Rm
);
10705 inst
.instruction
|= Rd
<< 8;
10706 inst
.instruction
|= Rn
<< 16;
10707 inst
.instruction
|= Rm
;
10708 if (inst
.operands
[3].present
)
10710 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10711 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10712 _("expression too complex"));
10713 inst
.instruction
|= (val
& 0x1c) << 10;
10714 inst
.instruction
|= (val
& 0x03) << 6;
10721 if (!inst
.operands
[3].present
)
10725 inst
.instruction
&= ~0x00000020;
10727 /* PR 10168. Swap the Rm and Rn registers. */
10728 Rtmp
= inst
.operands
[1].reg
;
10729 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10730 inst
.operands
[2].reg
= Rtmp
;
10738 if (inst
.operands
[0].immisreg
)
10739 reject_bad_reg (inst
.operands
[0].imm
);
10741 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10745 do_t_push_pop (void)
10749 constraint (inst
.operands
[0].writeback
,
10750 _("push/pop do not support {reglist}^"));
10751 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10752 _("expression too complex"));
10754 mask
= inst
.operands
[0].imm
;
10755 if ((mask
& ~0xff) == 0)
10756 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10757 else if ((inst
.instruction
== T_MNEM_push
10758 && (mask
& ~0xff) == 1 << REG_LR
)
10759 || (inst
.instruction
== T_MNEM_pop
10760 && (mask
& ~0xff) == 1 << REG_PC
))
10762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10763 inst
.instruction
|= THUMB_PP_PC_LR
;
10764 inst
.instruction
|= mask
& 0xff;
10766 else if (unified_syntax
)
10768 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10769 encode_thumb2_ldmstm (13, mask
, TRUE
);
10773 inst
.error
= _("invalid register list to push/pop instruction");
10783 Rd
= inst
.operands
[0].reg
;
10784 Rm
= inst
.operands
[1].reg
;
10786 reject_bad_reg (Rd
);
10787 reject_bad_reg (Rm
);
10789 inst
.instruction
|= Rd
<< 8;
10790 inst
.instruction
|= Rm
<< 16;
10791 inst
.instruction
|= Rm
;
10799 Rd
= inst
.operands
[0].reg
;
10800 Rm
= inst
.operands
[1].reg
;
10802 reject_bad_reg (Rd
);
10803 reject_bad_reg (Rm
);
10805 if (Rd
<= 7 && Rm
<= 7
10806 && inst
.size_req
!= 4)
10808 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10809 inst
.instruction
|= Rd
;
10810 inst
.instruction
|= Rm
<< 3;
10812 else if (unified_syntax
)
10814 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10815 inst
.instruction
|= Rd
<< 8;
10816 inst
.instruction
|= Rm
<< 16;
10817 inst
.instruction
|= Rm
;
10820 inst
.error
= BAD_HIREG
;
10828 Rd
= inst
.operands
[0].reg
;
10829 Rm
= inst
.operands
[1].reg
;
10831 reject_bad_reg (Rd
);
10832 reject_bad_reg (Rm
);
10834 inst
.instruction
|= Rd
<< 8;
10835 inst
.instruction
|= Rm
;
10843 Rd
= inst
.operands
[0].reg
;
10844 Rs
= (inst
.operands
[1].present
10845 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10846 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10848 reject_bad_reg (Rd
);
10849 reject_bad_reg (Rs
);
10850 if (inst
.operands
[2].isreg
)
10851 reject_bad_reg (inst
.operands
[2].reg
);
10853 inst
.instruction
|= Rd
<< 8;
10854 inst
.instruction
|= Rs
<< 16;
10855 if (!inst
.operands
[2].isreg
)
10857 bfd_boolean narrow
;
10859 if ((inst
.instruction
& 0x00100000) != 0)
10860 narrow
= !in_it_block ();
10862 narrow
= in_it_block ();
10864 if (Rd
> 7 || Rs
> 7)
10867 if (inst
.size_req
== 4 || !unified_syntax
)
10870 if (inst
.reloc
.exp
.X_op
!= O_constant
10871 || inst
.reloc
.exp
.X_add_number
!= 0)
10874 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10875 relaxation, but it doesn't seem worth the hassle. */
10878 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10879 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10880 inst
.instruction
|= Rs
<< 3;
10881 inst
.instruction
|= Rd
;
10885 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10886 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10890 encode_thumb32_shifted_operand (2);
10896 set_it_insn_type (OUTSIDE_IT_INSN
);
10897 if (inst
.operands
[0].imm
)
10898 inst
.instruction
|= 0x8;
10904 if (!inst
.operands
[1].present
)
10905 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10907 if (unified_syntax
)
10909 bfd_boolean narrow
;
10912 switch (inst
.instruction
)
10915 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10917 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10919 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10921 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10925 if (THUMB_SETS_FLAGS (inst
.instruction
))
10926 narrow
= !in_it_block ();
10928 narrow
= in_it_block ();
10929 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10931 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10933 if (inst
.operands
[2].isreg
10934 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10935 || inst
.operands
[2].reg
> 7))
10937 if (inst
.size_req
== 4)
10940 reject_bad_reg (inst
.operands
[0].reg
);
10941 reject_bad_reg (inst
.operands
[1].reg
);
10945 if (inst
.operands
[2].isreg
)
10947 reject_bad_reg (inst
.operands
[2].reg
);
10948 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10949 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10951 inst
.instruction
|= inst
.operands
[2].reg
;
10955 inst
.operands
[1].shifted
= 1;
10956 inst
.operands
[1].shift_kind
= shift_kind
;
10957 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10958 ? T_MNEM_movs
: T_MNEM_mov
);
10959 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10960 encode_thumb32_shifted_operand (1);
10961 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10962 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10967 if (inst
.operands
[2].isreg
)
10969 switch (shift_kind
)
10971 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10972 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10973 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10974 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10978 inst
.instruction
|= inst
.operands
[0].reg
;
10979 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10983 switch (shift_kind
)
10985 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10986 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10987 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10990 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10991 inst
.instruction
|= inst
.operands
[0].reg
;
10992 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10998 constraint (inst
.operands
[0].reg
> 7
10999 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11000 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11002 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11004 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11005 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11006 _("source1 and dest must be same register"));
11008 switch (inst
.instruction
)
11010 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11011 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11012 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11013 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11017 inst
.instruction
|= inst
.operands
[0].reg
;
11018 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11022 switch (inst
.instruction
)
11024 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11025 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11026 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11027 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11030 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11031 inst
.instruction
|= inst
.operands
[0].reg
;
11032 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11040 unsigned Rd
, Rn
, Rm
;
11042 Rd
= inst
.operands
[0].reg
;
11043 Rn
= inst
.operands
[1].reg
;
11044 Rm
= inst
.operands
[2].reg
;
11046 reject_bad_reg (Rd
);
11047 reject_bad_reg (Rn
);
11048 reject_bad_reg (Rm
);
11050 inst
.instruction
|= Rd
<< 8;
11051 inst
.instruction
|= Rn
<< 16;
11052 inst
.instruction
|= Rm
;
11058 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11059 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11060 _("expression too complex"));
11061 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11062 inst
.instruction
|= (value
& 0xf000) >> 12;
11063 inst
.instruction
|= (value
& 0x0ff0);
11064 inst
.instruction
|= (value
& 0x000f) << 16;
11068 do_t_ssat_usat (int bias
)
11072 Rd
= inst
.operands
[0].reg
;
11073 Rn
= inst
.operands
[2].reg
;
11075 reject_bad_reg (Rd
);
11076 reject_bad_reg (Rn
);
11078 inst
.instruction
|= Rd
<< 8;
11079 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11080 inst
.instruction
|= Rn
<< 16;
11082 if (inst
.operands
[3].present
)
11084 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11086 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11088 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11089 _("expression too complex"));
11091 if (shift_amount
!= 0)
11093 constraint (shift_amount
> 31,
11094 _("shift expression is too large"));
11096 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11097 inst
.instruction
|= 0x00200000; /* sh bit. */
11099 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11100 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11108 do_t_ssat_usat (1);
11116 Rd
= inst
.operands
[0].reg
;
11117 Rn
= inst
.operands
[2].reg
;
11119 reject_bad_reg (Rd
);
11120 reject_bad_reg (Rn
);
11122 inst
.instruction
|= Rd
<< 8;
11123 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11124 inst
.instruction
|= Rn
<< 16;
11130 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11131 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11132 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11133 || inst
.operands
[2].negative
,
11136 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11137 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11138 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11139 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11145 if (!inst
.operands
[2].present
)
11146 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11148 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11149 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11150 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11151 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11154 inst
.instruction
|= inst
.operands
[0].reg
;
11155 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11156 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11157 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11163 unsigned Rd
, Rn
, Rm
;
11165 Rd
= inst
.operands
[0].reg
;
11166 Rn
= inst
.operands
[1].reg
;
11167 Rm
= inst
.operands
[2].reg
;
11169 reject_bad_reg (Rd
);
11170 reject_bad_reg (Rn
);
11171 reject_bad_reg (Rm
);
11173 inst
.instruction
|= Rd
<< 8;
11174 inst
.instruction
|= Rn
<< 16;
11175 inst
.instruction
|= Rm
;
11176 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11184 Rd
= inst
.operands
[0].reg
;
11185 Rm
= inst
.operands
[1].reg
;
11187 reject_bad_reg (Rd
);
11188 reject_bad_reg (Rm
);
11190 if (inst
.instruction
<= 0xffff
11191 && inst
.size_req
!= 4
11192 && Rd
<= 7 && Rm
<= 7
11193 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11195 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11196 inst
.instruction
|= Rd
;
11197 inst
.instruction
|= Rm
<< 3;
11199 else if (unified_syntax
)
11201 if (inst
.instruction
<= 0xffff)
11202 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11203 inst
.instruction
|= Rd
<< 8;
11204 inst
.instruction
|= Rm
;
11205 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11209 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11210 _("Thumb encoding does not support rotation"));
11211 constraint (1, BAD_HIREG
);
11218 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11227 half
= (inst
.instruction
& 0x10) != 0;
11228 set_it_insn_type_last ();
11229 constraint (inst
.operands
[0].immisreg
,
11230 _("instruction requires register index"));
11232 Rn
= inst
.operands
[0].reg
;
11233 Rm
= inst
.operands
[0].imm
;
11235 constraint (Rn
== REG_SP
, BAD_SP
);
11236 reject_bad_reg (Rm
);
11238 constraint (!half
&& inst
.operands
[0].shifted
,
11239 _("instruction does not allow shifted index"));
11240 inst
.instruction
|= (Rn
<< 16) | Rm
;
11246 do_t_ssat_usat (0);
11254 Rd
= inst
.operands
[0].reg
;
11255 Rn
= inst
.operands
[2].reg
;
11257 reject_bad_reg (Rd
);
11258 reject_bad_reg (Rn
);
11260 inst
.instruction
|= Rd
<< 8;
11261 inst
.instruction
|= inst
.operands
[1].imm
;
11262 inst
.instruction
|= Rn
<< 16;
11265 /* Neon instruction encoder helpers. */
11267 /* Encodings for the different types for various Neon opcodes. */
11269 /* An "invalid" code for the following tables. */
11272 struct neon_tab_entry
11275 unsigned float_or_poly
;
11276 unsigned scalar_or_imm
;
11279 /* Map overloaded Neon opcodes to their respective encodings. */
11280 #define NEON_ENC_TAB \
11281 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11282 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11283 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11284 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11285 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11286 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11287 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11288 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11289 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11290 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11291 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11292 /* Register variants of the following two instructions are encoded as
11293 vcge / vcgt with the operands reversed. */ \
11294 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11295 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11296 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11297 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11298 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11299 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11300 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11301 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11302 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11303 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11304 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11305 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11306 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11307 X(vshl, 0x0000400, N_INV, 0x0800510), \
11308 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11309 X(vand, 0x0000110, N_INV, 0x0800030), \
11310 X(vbic, 0x0100110, N_INV, 0x0800030), \
11311 X(veor, 0x1000110, N_INV, N_INV), \
11312 X(vorn, 0x0300110, N_INV, 0x0800010), \
11313 X(vorr, 0x0200110, N_INV, 0x0800010), \
11314 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11315 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11316 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11317 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11318 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11319 X(vst1, 0x0000000, 0x0800000, N_INV), \
11320 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11321 X(vst2, 0x0000100, 0x0800100, N_INV), \
11322 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11323 X(vst3, 0x0000200, 0x0800200, N_INV), \
11324 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11325 X(vst4, 0x0000300, 0x0800300, N_INV), \
11326 X(vmovn, 0x1b20200, N_INV, N_INV), \
11327 X(vtrn, 0x1b20080, N_INV, N_INV), \
11328 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11329 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11330 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11331 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11332 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11333 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11334 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11335 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11336 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11340 #define X(OPC,I,F,S) N_MNEM_##OPC
11345 static const struct neon_tab_entry neon_enc_tab
[] =
11347 #define X(OPC,I,F,S) { (I), (F), (S) }
11352 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11353 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11354 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11355 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11356 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11357 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11358 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11359 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11360 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11361 #define NEON_ENC_SINGLE(X) \
11362 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11363 #define NEON_ENC_DOUBLE(X) \
11364 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11366 /* Define shapes for instruction operands. The following mnemonic characters
11367 are used in this table:
11369 F - VFP S<n> register
11370 D - Neon D<n> register
11371 Q - Neon Q<n> register
11375 L - D<n> register list
11377 This table is used to generate various data:
11378 - enumerations of the form NS_DDR to be used as arguments to
11380 - a table classifying shapes into single, double, quad, mixed.
11381 - a table used to drive neon_select_shape. */
11383 #define NEON_SHAPE_DEF \
11384 X(3, (D, D, D), DOUBLE), \
11385 X(3, (Q, Q, Q), QUAD), \
11386 X(3, (D, D, I), DOUBLE), \
11387 X(3, (Q, Q, I), QUAD), \
11388 X(3, (D, D, S), DOUBLE), \
11389 X(3, (Q, Q, S), QUAD), \
11390 X(2, (D, D), DOUBLE), \
11391 X(2, (Q, Q), QUAD), \
11392 X(2, (D, S), DOUBLE), \
11393 X(2, (Q, S), QUAD), \
11394 X(2, (D, R), DOUBLE), \
11395 X(2, (Q, R), QUAD), \
11396 X(2, (D, I), DOUBLE), \
11397 X(2, (Q, I), QUAD), \
11398 X(3, (D, L, D), DOUBLE), \
11399 X(2, (D, Q), MIXED), \
11400 X(2, (Q, D), MIXED), \
11401 X(3, (D, Q, I), MIXED), \
11402 X(3, (Q, D, I), MIXED), \
11403 X(3, (Q, D, D), MIXED), \
11404 X(3, (D, Q, Q), MIXED), \
11405 X(3, (Q, Q, D), MIXED), \
11406 X(3, (Q, D, S), MIXED), \
11407 X(3, (D, Q, S), MIXED), \
11408 X(4, (D, D, D, I), DOUBLE), \
11409 X(4, (Q, Q, Q, I), QUAD), \
11410 X(2, (F, F), SINGLE), \
11411 X(3, (F, F, F), SINGLE), \
11412 X(2, (F, I), SINGLE), \
11413 X(2, (F, D), MIXED), \
11414 X(2, (D, F), MIXED), \
11415 X(3, (F, F, I), MIXED), \
11416 X(4, (R, R, F, F), SINGLE), \
11417 X(4, (F, F, R, R), SINGLE), \
11418 X(3, (D, R, R), DOUBLE), \
11419 X(3, (R, R, D), DOUBLE), \
11420 X(2, (S, R), SINGLE), \
11421 X(2, (R, S), SINGLE), \
11422 X(2, (F, R), SINGLE), \
11423 X(2, (R, F), SINGLE)
11425 #define S2(A,B) NS_##A##B
11426 #define S3(A,B,C) NS_##A##B##C
11427 #define S4(A,B,C,D) NS_##A##B##C##D
11429 #define X(N, L, C) S##N L
11442 enum neon_shape_class
11450 #define X(N, L, C) SC_##C
11452 static enum neon_shape_class neon_shape_class
[] =
11470 /* Register widths of above. */
11471 static unsigned neon_shape_el_size
[] =
11482 struct neon_shape_info
11485 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11488 #define S2(A,B) { SE_##A, SE_##B }
11489 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11490 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11492 #define X(N, L, C) { N, S##N L }
11494 static struct neon_shape_info neon_shape_tab
[] =
11504 /* Bit masks used in type checking given instructions.
11505 'N_EQK' means the type must be the same as (or based on in some way) the key
11506 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11507 set, various other bits can be set as well in order to modify the meaning of
11508 the type constraint. */
11510 enum neon_type_mask
11533 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11534 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11535 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11536 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11537 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11538 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11539 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11540 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11541 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11542 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11544 N_MAX_NONSPECIAL
= N_F64
11547 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11549 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11550 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11551 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11552 #define N_SUF_32 (N_SU_32 | N_F32)
11553 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11554 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11556 /* Pass this as the first type argument to neon_check_type to ignore types
11558 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11560 /* Select a "shape" for the current instruction (describing register types or
11561 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11562 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11563 function of operand parsing, so this function doesn't need to be called.
11564 Shapes should be listed in order of decreasing length. */
11566 static enum neon_shape
11567 neon_select_shape (enum neon_shape shape
, ...)
11570 enum neon_shape first_shape
= shape
;
11572 /* Fix missing optional operands. FIXME: we don't know at this point how
11573 many arguments we should have, so this makes the assumption that we have
11574 > 1. This is true of all current Neon opcodes, I think, but may not be
11575 true in the future. */
11576 if (!inst
.operands
[1].present
)
11577 inst
.operands
[1] = inst
.operands
[0];
11579 va_start (ap
, shape
);
11581 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11586 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11588 if (!inst
.operands
[j
].present
)
11594 switch (neon_shape_tab
[shape
].el
[j
])
11597 if (!(inst
.operands
[j
].isreg
11598 && inst
.operands
[j
].isvec
11599 && inst
.operands
[j
].issingle
11600 && !inst
.operands
[j
].isquad
))
11605 if (!(inst
.operands
[j
].isreg
11606 && inst
.operands
[j
].isvec
11607 && !inst
.operands
[j
].isquad
11608 && !inst
.operands
[j
].issingle
))
11613 if (!(inst
.operands
[j
].isreg
11614 && !inst
.operands
[j
].isvec
))
11619 if (!(inst
.operands
[j
].isreg
11620 && inst
.operands
[j
].isvec
11621 && inst
.operands
[j
].isquad
11622 && !inst
.operands
[j
].issingle
))
11627 if (!(!inst
.operands
[j
].isreg
11628 && !inst
.operands
[j
].isscalar
))
11633 if (!(!inst
.operands
[j
].isreg
11634 && inst
.operands
[j
].isscalar
))
11648 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11649 first_error (_("invalid instruction shape"));
11654 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11655 means the Q bit should be set). */
11658 neon_quad (enum neon_shape shape
)
11660 return neon_shape_class
[shape
] == SC_QUAD
;
11664 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11667 /* Allow modification to be made to types which are constrained to be
11668 based on the key element, based on bits set alongside N_EQK. */
11669 if ((typebits
& N_EQK
) != 0)
11671 if ((typebits
& N_HLF
) != 0)
11673 else if ((typebits
& N_DBL
) != 0)
11675 if ((typebits
& N_SGN
) != 0)
11676 *g_type
= NT_signed
;
11677 else if ((typebits
& N_UNS
) != 0)
11678 *g_type
= NT_unsigned
;
11679 else if ((typebits
& N_INT
) != 0)
11680 *g_type
= NT_integer
;
11681 else if ((typebits
& N_FLT
) != 0)
11682 *g_type
= NT_float
;
11683 else if ((typebits
& N_SIZ
) != 0)
11684 *g_type
= NT_untyped
;
11688 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11689 operand type, i.e. the single type specified in a Neon instruction when it
11690 is the only one given. */
11692 static struct neon_type_el
11693 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11695 struct neon_type_el dest
= *key
;
11697 gas_assert ((thisarg
& N_EQK
) != 0);
11699 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11704 /* Convert Neon type and size into compact bitmask representation. */
11706 static enum neon_type_mask
11707 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11714 case 8: return N_8
;
11715 case 16: return N_16
;
11716 case 32: return N_32
;
11717 case 64: return N_64
;
11725 case 8: return N_I8
;
11726 case 16: return N_I16
;
11727 case 32: return N_I32
;
11728 case 64: return N_I64
;
11736 case 16: return N_F16
;
11737 case 32: return N_F32
;
11738 case 64: return N_F64
;
11746 case 8: return N_P8
;
11747 case 16: return N_P16
;
11755 case 8: return N_S8
;
11756 case 16: return N_S16
;
11757 case 32: return N_S32
;
11758 case 64: return N_S64
;
11766 case 8: return N_U8
;
11767 case 16: return N_U16
;
11768 case 32: return N_U32
;
11769 case 64: return N_U64
;
11780 /* Convert compact Neon bitmask type representation to a type and size. Only
11781 handles the case where a single bit is set in the mask. */
11784 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11785 enum neon_type_mask mask
)
11787 if ((mask
& N_EQK
) != 0)
11790 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11792 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11794 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11796 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11801 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11803 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11804 *type
= NT_unsigned
;
11805 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11806 *type
= NT_integer
;
11807 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11808 *type
= NT_untyped
;
11809 else if ((mask
& (N_P8
| N_P16
)) != 0)
11811 else if ((mask
& (N_F32
| N_F64
)) != 0)
11819 /* Modify a bitmask of allowed types. This is only needed for type
11823 modify_types_allowed (unsigned allowed
, unsigned mods
)
11826 enum neon_el_type type
;
11832 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11834 if (el_type_of_type_chk (&type
, &size
,
11835 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11837 neon_modify_type_size (mods
, &type
, &size
);
11838 destmask
|= type_chk_of_el_type (type
, size
);
11845 /* Check type and return type classification.
11846 The manual states (paraphrase): If one datatype is given, it indicates the
11848 - the second operand, if there is one
11849 - the operand, if there is no second operand
11850 - the result, if there are no operands.
11851 This isn't quite good enough though, so we use a concept of a "key" datatype
11852 which is set on a per-instruction basis, which is the one which matters when
11853 only one data type is written.
11854 Note: this function has side-effects (e.g. filling in missing operands). All
11855 Neon instructions should call it before performing bit encoding. */
11857 static struct neon_type_el
11858 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11861 unsigned i
, pass
, key_el
= 0;
11862 unsigned types
[NEON_MAX_TYPE_ELS
];
11863 enum neon_el_type k_type
= NT_invtype
;
11864 unsigned k_size
= -1u;
11865 struct neon_type_el badtype
= {NT_invtype
, -1};
11866 unsigned key_allowed
= 0;
11868 /* Optional registers in Neon instructions are always (not) in operand 1.
11869 Fill in the missing operand here, if it was omitted. */
11870 if (els
> 1 && !inst
.operands
[1].present
)
11871 inst
.operands
[1] = inst
.operands
[0];
11873 /* Suck up all the varargs. */
11875 for (i
= 0; i
< els
; i
++)
11877 unsigned thisarg
= va_arg (ap
, unsigned);
11878 if (thisarg
== N_IGNORE_TYPE
)
11883 types
[i
] = thisarg
;
11884 if ((thisarg
& N_KEY
) != 0)
11889 if (inst
.vectype
.elems
> 0)
11890 for (i
= 0; i
< els
; i
++)
11891 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11893 first_error (_("types specified in both the mnemonic and operands"));
11897 /* Duplicate inst.vectype elements here as necessary.
11898 FIXME: No idea if this is exactly the same as the ARM assembler,
11899 particularly when an insn takes one register and one non-register
11901 if (inst
.vectype
.elems
== 1 && els
> 1)
11904 inst
.vectype
.elems
= els
;
11905 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11906 for (j
= 0; j
< els
; j
++)
11908 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11911 else if (inst
.vectype
.elems
== 0 && els
> 0)
11914 /* No types were given after the mnemonic, so look for types specified
11915 after each operand. We allow some flexibility here; as long as the
11916 "key" operand has a type, we can infer the others. */
11917 for (j
= 0; j
< els
; j
++)
11918 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11919 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11921 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11923 for (j
= 0; j
< els
; j
++)
11924 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11925 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11930 first_error (_("operand types can't be inferred"));
11934 else if (inst
.vectype
.elems
!= els
)
11936 first_error (_("type specifier has the wrong number of parts"));
11940 for (pass
= 0; pass
< 2; pass
++)
11942 for (i
= 0; i
< els
; i
++)
11944 unsigned thisarg
= types
[i
];
11945 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11946 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11947 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11948 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11950 /* Decay more-specific signed & unsigned types to sign-insensitive
11951 integer types if sign-specific variants are unavailable. */
11952 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11953 && (types_allowed
& N_SU_ALL
) == 0)
11954 g_type
= NT_integer
;
11956 /* If only untyped args are allowed, decay any more specific types to
11957 them. Some instructions only care about signs for some element
11958 sizes, so handle that properly. */
11959 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11960 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11961 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11962 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11963 g_type
= NT_untyped
;
11967 if ((thisarg
& N_KEY
) != 0)
11971 key_allowed
= thisarg
& ~N_KEY
;
11976 if ((thisarg
& N_VFP
) != 0)
11978 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11979 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11981 /* In VFP mode, operands must match register widths. If we
11982 have a key operand, use its width, else use the width of
11983 the current operand. */
11989 if (regwidth
!= match
)
11991 first_error (_("operand size must match register width"));
11996 if ((thisarg
& N_EQK
) == 0)
11998 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12000 if ((given_type
& types_allowed
) == 0)
12002 first_error (_("bad type in Neon instruction"));
12008 enum neon_el_type mod_k_type
= k_type
;
12009 unsigned mod_k_size
= k_size
;
12010 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12011 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12013 first_error (_("inconsistent types in Neon instruction"));
12021 return inst
.vectype
.el
[key_el
];
12024 /* Neon-style VFP instruction forwarding. */
12026 /* Thumb VFP instructions have 0xE in the condition field. */
12029 do_vfp_cond_or_thumb (void)
12032 inst
.instruction
|= 0xe0000000;
12034 inst
.instruction
|= inst
.cond
<< 28;
12037 /* Look up and encode a simple mnemonic, for use as a helper function for the
12038 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12039 etc. It is assumed that operand parsing has already been done, and that the
12040 operands are in the form expected by the given opcode (this isn't necessarily
12041 the same as the form in which they were parsed, hence some massaging must
12042 take place before this function is called).
12043 Checks current arch version against that in the looked-up opcode. */
12046 do_vfp_nsyn_opcode (const char *opname
)
12048 const struct asm_opcode
*opcode
;
12050 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12055 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12056 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12061 inst
.instruction
= opcode
->tvalue
;
12062 opcode
->tencode ();
12066 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12067 opcode
->aencode ();
12072 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12074 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12079 do_vfp_nsyn_opcode ("fadds");
12081 do_vfp_nsyn_opcode ("fsubs");
12086 do_vfp_nsyn_opcode ("faddd");
12088 do_vfp_nsyn_opcode ("fsubd");
12092 /* Check operand types to see if this is a VFP instruction, and if so call
12096 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12098 enum neon_shape rs
;
12099 struct neon_type_el et
;
12104 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12105 et
= neon_check_type (2, rs
,
12106 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12110 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12111 et
= neon_check_type (3, rs
,
12112 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12119 if (et
.type
!= NT_invtype
)
12131 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12133 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12138 do_vfp_nsyn_opcode ("fmacs");
12140 do_vfp_nsyn_opcode ("fmscs");
12145 do_vfp_nsyn_opcode ("fmacd");
12147 do_vfp_nsyn_opcode ("fmscd");
12152 do_vfp_nsyn_mul (enum neon_shape rs
)
12155 do_vfp_nsyn_opcode ("fmuls");
12157 do_vfp_nsyn_opcode ("fmuld");
12161 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12163 int is_neg
= (inst
.instruction
& 0x80) != 0;
12164 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12169 do_vfp_nsyn_opcode ("fnegs");
12171 do_vfp_nsyn_opcode ("fabss");
12176 do_vfp_nsyn_opcode ("fnegd");
12178 do_vfp_nsyn_opcode ("fabsd");
12182 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12183 insns belong to Neon, and are handled elsewhere. */
12186 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12188 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12192 do_vfp_nsyn_opcode ("fldmdbs");
12194 do_vfp_nsyn_opcode ("fldmias");
12199 do_vfp_nsyn_opcode ("fstmdbs");
12201 do_vfp_nsyn_opcode ("fstmias");
12206 do_vfp_nsyn_sqrt (void)
12208 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12209 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12212 do_vfp_nsyn_opcode ("fsqrts");
12214 do_vfp_nsyn_opcode ("fsqrtd");
12218 do_vfp_nsyn_div (void)
12220 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12221 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12222 N_F32
| N_F64
| N_KEY
| N_VFP
);
12225 do_vfp_nsyn_opcode ("fdivs");
12227 do_vfp_nsyn_opcode ("fdivd");
12231 do_vfp_nsyn_nmul (void)
12233 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12234 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12235 N_F32
| N_F64
| N_KEY
| N_VFP
);
12239 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12240 do_vfp_sp_dyadic ();
12244 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12245 do_vfp_dp_rd_rn_rm ();
12247 do_vfp_cond_or_thumb ();
12251 do_vfp_nsyn_cmp (void)
12253 if (inst
.operands
[1].isreg
)
12255 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12256 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12260 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12261 do_vfp_sp_monadic ();
12265 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12266 do_vfp_dp_rd_rm ();
12271 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12272 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12274 switch (inst
.instruction
& 0x0fffffff)
12277 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12280 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12288 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12289 do_vfp_sp_compare_z ();
12293 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12297 do_vfp_cond_or_thumb ();
12301 nsyn_insert_sp (void)
12303 inst
.operands
[1] = inst
.operands
[0];
12304 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12305 inst
.operands
[0].reg
= REG_SP
;
12306 inst
.operands
[0].isreg
= 1;
12307 inst
.operands
[0].writeback
= 1;
12308 inst
.operands
[0].present
= 1;
12312 do_vfp_nsyn_push (void)
12315 if (inst
.operands
[1].issingle
)
12316 do_vfp_nsyn_opcode ("fstmdbs");
12318 do_vfp_nsyn_opcode ("fstmdbd");
12322 do_vfp_nsyn_pop (void)
12325 if (inst
.operands
[1].issingle
)
12326 do_vfp_nsyn_opcode ("fldmias");
12328 do_vfp_nsyn_opcode ("fldmiad");
12331 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12332 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12335 neon_dp_fixup (unsigned i
)
12339 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12353 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12357 neon_logbits (unsigned x
)
12359 return ffs (x
) - 4;
12362 #define LOW4(R) ((R) & 0xf)
12363 #define HI1(R) (((R) >> 4) & 1)
12365 /* Encode insns with bit pattern:
12367 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12368 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12370 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12371 different meaning for some instruction. */
12374 neon_three_same (int isquad
, int ubit
, int size
)
12376 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12377 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12378 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12379 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12380 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12381 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12382 inst
.instruction
|= (isquad
!= 0) << 6;
12383 inst
.instruction
|= (ubit
!= 0) << 24;
12385 inst
.instruction
|= neon_logbits (size
) << 20;
12387 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12390 /* Encode instructions of the form:
12392 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12393 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12395 Don't write size if SIZE == -1. */
12398 neon_two_same (int qbit
, int ubit
, int size
)
12400 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12401 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12402 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12403 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12404 inst
.instruction
|= (qbit
!= 0) << 6;
12405 inst
.instruction
|= (ubit
!= 0) << 24;
12408 inst
.instruction
|= neon_logbits (size
) << 18;
12410 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12413 /* Neon instruction encoders, in approximate order of appearance. */
12416 do_neon_dyadic_i_su (void)
12418 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12419 struct neon_type_el et
= neon_check_type (3, rs
,
12420 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12421 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12425 do_neon_dyadic_i64_su (void)
12427 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12428 struct neon_type_el et
= neon_check_type (3, rs
,
12429 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12430 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12434 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12437 unsigned size
= et
.size
>> 3;
12438 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12439 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12440 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12442 inst
.instruction
|= (isquad
!= 0) << 6;
12443 inst
.instruction
|= immbits
<< 16;
12444 inst
.instruction
|= (size
>> 3) << 7;
12445 inst
.instruction
|= (size
& 0x7) << 19;
12447 inst
.instruction
|= (uval
!= 0) << 24;
12449 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12453 do_neon_shl_imm (void)
12455 if (!inst
.operands
[2].isreg
)
12457 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12458 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12459 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12460 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12464 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12465 struct neon_type_el et
= neon_check_type (3, rs
,
12466 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12469 /* VSHL/VQSHL 3-register variants have syntax such as:
12471 whereas other 3-register operations encoded by neon_three_same have
12474 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12476 tmp
= inst
.operands
[2].reg
;
12477 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12478 inst
.operands
[1].reg
= tmp
;
12479 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12480 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12485 do_neon_qshl_imm (void)
12487 if (!inst
.operands
[2].isreg
)
12489 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12490 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12492 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12493 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12494 inst
.operands
[2].imm
);
12498 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12499 struct neon_type_el et
= neon_check_type (3, rs
,
12500 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12503 /* See note in do_neon_shl_imm. */
12504 tmp
= inst
.operands
[2].reg
;
12505 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12506 inst
.operands
[1].reg
= tmp
;
12507 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12508 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12513 do_neon_rshl (void)
12515 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12516 struct neon_type_el et
= neon_check_type (3, rs
,
12517 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12520 tmp
= inst
.operands
[2].reg
;
12521 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12522 inst
.operands
[1].reg
= tmp
;
12523 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12527 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12529 /* Handle .I8 pseudo-instructions. */
12532 /* Unfortunately, this will make everything apart from zero out-of-range.
12533 FIXME is this the intended semantics? There doesn't seem much point in
12534 accepting .I8 if so. */
12535 immediate
|= immediate
<< 8;
12541 if (immediate
== (immediate
& 0x000000ff))
12543 *immbits
= immediate
;
12546 else if (immediate
== (immediate
& 0x0000ff00))
12548 *immbits
= immediate
>> 8;
12551 else if (immediate
== (immediate
& 0x00ff0000))
12553 *immbits
= immediate
>> 16;
12556 else if (immediate
== (immediate
& 0xff000000))
12558 *immbits
= immediate
>> 24;
12561 if ((immediate
& 0xffff) != (immediate
>> 16))
12562 goto bad_immediate
;
12563 immediate
&= 0xffff;
12566 if (immediate
== (immediate
& 0x000000ff))
12568 *immbits
= immediate
;
12571 else if (immediate
== (immediate
& 0x0000ff00))
12573 *immbits
= immediate
>> 8;
12578 first_error (_("immediate value out of range"));
12582 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12586 neon_bits_same_in_bytes (unsigned imm
)
12588 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12589 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12590 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12591 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12594 /* For immediate of above form, return 0bABCD. */
12597 neon_squash_bits (unsigned imm
)
12599 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12600 | ((imm
& 0x01000000) >> 21);
12603 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12606 neon_qfloat_bits (unsigned imm
)
12608 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12611 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12612 the instruction. *OP is passed as the initial value of the op field, and
12613 may be set to a different value depending on the constant (i.e.
12614 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12615 MVN). If the immediate looks like a repeated pattern then also
12616 try smaller element sizes. */
12619 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12620 unsigned *immbits
, int *op
, int size
,
12621 enum neon_el_type type
)
12623 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12625 if (type
== NT_float
&& !float_p
)
12628 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12630 if (size
!= 32 || *op
== 1)
12632 *immbits
= neon_qfloat_bits (immlo
);
12638 if (neon_bits_same_in_bytes (immhi
)
12639 && neon_bits_same_in_bytes (immlo
))
12643 *immbits
= (neon_squash_bits (immhi
) << 4)
12644 | neon_squash_bits (immlo
);
12649 if (immhi
!= immlo
)
12655 if (immlo
== (immlo
& 0x000000ff))
12660 else if (immlo
== (immlo
& 0x0000ff00))
12662 *immbits
= immlo
>> 8;
12665 else if (immlo
== (immlo
& 0x00ff0000))
12667 *immbits
= immlo
>> 16;
12670 else if (immlo
== (immlo
& 0xff000000))
12672 *immbits
= immlo
>> 24;
12675 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12677 *immbits
= (immlo
>> 8) & 0xff;
12680 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12682 *immbits
= (immlo
>> 16) & 0xff;
12686 if ((immlo
& 0xffff) != (immlo
>> 16))
12693 if (immlo
== (immlo
& 0x000000ff))
12698 else if (immlo
== (immlo
& 0x0000ff00))
12700 *immbits
= immlo
>> 8;
12704 if ((immlo
& 0xff) != (immlo
>> 8))
12709 if (immlo
== (immlo
& 0x000000ff))
12711 /* Don't allow MVN with 8-bit immediate. */
12721 /* Write immediate bits [7:0] to the following locations:
12723 |28/24|23 19|18 16|15 4|3 0|
12724 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12726 This function is used by VMOV/VMVN/VORR/VBIC. */
12729 neon_write_immbits (unsigned immbits
)
12731 inst
.instruction
|= immbits
& 0xf;
12732 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12733 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12736 /* Invert low-order SIZE bits of XHI:XLO. */
12739 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12741 unsigned immlo
= xlo
? *xlo
: 0;
12742 unsigned immhi
= xhi
? *xhi
: 0;
12747 immlo
= (~immlo
) & 0xff;
12751 immlo
= (~immlo
) & 0xffff;
12755 immhi
= (~immhi
) & 0xffffffff;
12756 /* fall through. */
12759 immlo
= (~immlo
) & 0xffffffff;
12774 do_neon_logic (void)
12776 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12778 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12779 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12780 /* U bit and size field were set as part of the bitmask. */
12781 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12782 neon_three_same (neon_quad (rs
), 0, -1);
12786 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12787 struct neon_type_el et
= neon_check_type (2, rs
,
12788 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12789 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12793 if (et
.type
== NT_invtype
)
12796 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12798 immbits
= inst
.operands
[1].imm
;
12801 /* .i64 is a pseudo-op, so the immediate must be a repeating
12803 if (immbits
!= (inst
.operands
[1].regisimm
?
12804 inst
.operands
[1].reg
: 0))
12806 /* Set immbits to an invalid constant. */
12807 immbits
= 0xdeadbeef;
12814 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12818 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12822 /* Pseudo-instruction for VBIC. */
12823 neon_invert_size (&immbits
, 0, et
.size
);
12824 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12828 /* Pseudo-instruction for VORR. */
12829 neon_invert_size (&immbits
, 0, et
.size
);
12830 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12840 inst
.instruction
|= neon_quad (rs
) << 6;
12841 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12842 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12843 inst
.instruction
|= cmode
<< 8;
12844 neon_write_immbits (immbits
);
12846 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12851 do_neon_bitfield (void)
12853 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12854 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12855 neon_three_same (neon_quad (rs
), 0, -1);
12859 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12862 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12863 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12865 if (et
.type
== NT_float
)
12867 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12868 neon_three_same (neon_quad (rs
), 0, -1);
12872 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12873 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12878 do_neon_dyadic_if_su (void)
12880 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12884 do_neon_dyadic_if_su_d (void)
12886 /* This version only allow D registers, but that constraint is enforced during
12887 operand parsing so we don't need to do anything extra here. */
12888 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12892 do_neon_dyadic_if_i_d (void)
12894 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12895 affected if we specify unsigned args. */
12896 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12899 enum vfp_or_neon_is_neon_bits
12902 NEON_CHECK_ARCH
= 2
12905 /* Call this function if an instruction which may have belonged to the VFP or
12906 Neon instruction sets, but turned out to be a Neon instruction (due to the
12907 operand types involved, etc.). We have to check and/or fix-up a couple of
12910 - Make sure the user hasn't attempted to make a Neon instruction
12912 - Alter the value in the condition code field if necessary.
12913 - Make sure that the arch supports Neon instructions.
12915 Which of these operations take place depends on bits from enum
12916 vfp_or_neon_is_neon_bits.
12918 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12919 current instruction's condition is COND_ALWAYS, the condition field is
12920 changed to inst.uncond_value. This is necessary because instructions shared
12921 between VFP and Neon may be conditional for the VFP variants only, and the
12922 unconditional Neon version must have, e.g., 0xF in the condition field. */
12925 vfp_or_neon_is_neon (unsigned check
)
12927 /* Conditions are always legal in Thumb mode (IT blocks). */
12928 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12930 if (inst
.cond
!= COND_ALWAYS
)
12932 first_error (_(BAD_COND
));
12935 if (inst
.uncond_value
!= -1)
12936 inst
.instruction
|= inst
.uncond_value
<< 28;
12939 if ((check
& NEON_CHECK_ARCH
)
12940 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12942 first_error (_(BAD_FPU
));
12950 do_neon_addsub_if_i (void)
12952 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12955 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12958 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12959 affected if we specify unsigned args. */
12960 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12963 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12965 V<op> A,B (A is operand 0, B is operand 2)
12970 so handle that case specially. */
12973 neon_exchange_operands (void)
12975 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12976 if (inst
.operands
[1].present
)
12978 /* Swap operands[1] and operands[2]. */
12979 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12980 inst
.operands
[1] = inst
.operands
[2];
12981 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12985 inst
.operands
[1] = inst
.operands
[2];
12986 inst
.operands
[2] = inst
.operands
[0];
12991 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12993 if (inst
.operands
[2].isreg
)
12996 neon_exchange_operands ();
12997 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13001 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13002 struct neon_type_el et
= neon_check_type (2, rs
,
13003 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13005 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13007 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13008 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13009 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13010 inst
.instruction
|= neon_quad (rs
) << 6;
13011 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13012 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13014 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13021 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13025 do_neon_cmp_inv (void)
13027 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13033 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13036 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13037 scalars, which are encoded in 5 bits, M : Rm.
13038 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13039 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13043 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13045 unsigned regno
= NEON_SCALAR_REG (scalar
);
13046 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13051 if (regno
> 7 || elno
> 3)
13053 return regno
| (elno
<< 3);
13056 if (regno
> 15 || elno
> 1)
13058 return regno
| (elno
<< 4);
13062 first_error (_("scalar out of range for multiply instruction"));
13068 /* Encode multiply / multiply-accumulate scalar instructions. */
13071 neon_mul_mac (struct neon_type_el et
, int ubit
)
13075 /* Give a more helpful error message if we have an invalid type. */
13076 if (et
.type
== NT_invtype
)
13079 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13080 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13081 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13082 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13083 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13084 inst
.instruction
|= LOW4 (scalar
);
13085 inst
.instruction
|= HI1 (scalar
) << 5;
13086 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13087 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13088 inst
.instruction
|= (ubit
!= 0) << 24;
13090 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13094 do_neon_mac_maybe_scalar (void)
13096 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13099 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13102 if (inst
.operands
[2].isscalar
)
13104 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13105 struct neon_type_el et
= neon_check_type (3, rs
,
13106 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13107 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13108 neon_mul_mac (et
, neon_quad (rs
));
13112 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13113 affected if we specify unsigned args. */
13114 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13121 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13122 struct neon_type_el et
= neon_check_type (3, rs
,
13123 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13124 neon_three_same (neon_quad (rs
), 0, et
.size
);
13127 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13128 same types as the MAC equivalents. The polynomial type for this instruction
13129 is encoded the same as the integer type. */
13134 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13137 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13140 if (inst
.operands
[2].isscalar
)
13141 do_neon_mac_maybe_scalar ();
13143 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13147 do_neon_qdmulh (void)
13149 if (inst
.operands
[2].isscalar
)
13151 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13152 struct neon_type_el et
= neon_check_type (3, rs
,
13153 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13154 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13155 neon_mul_mac (et
, neon_quad (rs
));
13159 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13160 struct neon_type_el et
= neon_check_type (3, rs
,
13161 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13162 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13163 /* The U bit (rounding) comes from bit mask. */
13164 neon_three_same (neon_quad (rs
), 0, et
.size
);
13169 do_neon_fcmp_absolute (void)
13171 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13172 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13173 /* Size field comes from bit mask. */
13174 neon_three_same (neon_quad (rs
), 1, -1);
13178 do_neon_fcmp_absolute_inv (void)
13180 neon_exchange_operands ();
13181 do_neon_fcmp_absolute ();
13185 do_neon_step (void)
13187 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13188 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13189 neon_three_same (neon_quad (rs
), 0, -1);
13193 do_neon_abs_neg (void)
13195 enum neon_shape rs
;
13196 struct neon_type_el et
;
13198 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13201 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13204 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13205 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13207 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13208 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13209 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13210 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13211 inst
.instruction
|= neon_quad (rs
) << 6;
13212 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13213 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13215 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13221 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13222 struct neon_type_el et
= neon_check_type (2, rs
,
13223 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13224 int imm
= inst
.operands
[2].imm
;
13225 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13226 _("immediate out of range for insert"));
13227 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13233 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13234 struct neon_type_el et
= neon_check_type (2, rs
,
13235 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13236 int imm
= inst
.operands
[2].imm
;
13237 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13238 _("immediate out of range for insert"));
13239 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13243 do_neon_qshlu_imm (void)
13245 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13246 struct neon_type_el et
= neon_check_type (2, rs
,
13247 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13248 int imm
= inst
.operands
[2].imm
;
13249 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13250 _("immediate out of range for shift"));
13251 /* Only encodes the 'U present' variant of the instruction.
13252 In this case, signed types have OP (bit 8) set to 0.
13253 Unsigned types have OP set to 1. */
13254 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13255 /* The rest of the bits are the same as other immediate shifts. */
13256 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13260 do_neon_qmovn (void)
13262 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13263 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13264 /* Saturating move where operands can be signed or unsigned, and the
13265 destination has the same signedness. */
13266 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13267 if (et
.type
== NT_unsigned
)
13268 inst
.instruction
|= 0xc0;
13270 inst
.instruction
|= 0x80;
13271 neon_two_same (0, 1, et
.size
/ 2);
13275 do_neon_qmovun (void)
13277 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13278 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13279 /* Saturating move with unsigned results. Operands must be signed. */
13280 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13281 neon_two_same (0, 1, et
.size
/ 2);
13285 do_neon_rshift_sat_narrow (void)
13287 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13288 or unsigned. If operands are unsigned, results must also be unsigned. */
13289 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13290 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13291 int imm
= inst
.operands
[2].imm
;
13292 /* This gets the bounds check, size encoding and immediate bits calculation
13296 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13297 VQMOVN.I<size> <Dd>, <Qm>. */
13300 inst
.operands
[2].present
= 0;
13301 inst
.instruction
= N_MNEM_vqmovn
;
13306 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13307 _("immediate out of range"));
13308 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13312 do_neon_rshift_sat_narrow_u (void)
13314 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13315 or unsigned. If operands are unsigned, results must also be unsigned. */
13316 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13317 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13318 int imm
= inst
.operands
[2].imm
;
13319 /* This gets the bounds check, size encoding and immediate bits calculation
13323 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13324 VQMOVUN.I<size> <Dd>, <Qm>. */
13327 inst
.operands
[2].present
= 0;
13328 inst
.instruction
= N_MNEM_vqmovun
;
13333 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13334 _("immediate out of range"));
13335 /* FIXME: The manual is kind of unclear about what value U should have in
13336 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13338 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13342 do_neon_movn (void)
13344 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13345 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13346 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13347 neon_two_same (0, 1, et
.size
/ 2);
13351 do_neon_rshift_narrow (void)
13353 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13354 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13355 int imm
= inst
.operands
[2].imm
;
13356 /* This gets the bounds check, size encoding and immediate bits calculation
13360 /* If immediate is zero then we are a pseudo-instruction for
13361 VMOVN.I<size> <Dd>, <Qm> */
13364 inst
.operands
[2].present
= 0;
13365 inst
.instruction
= N_MNEM_vmovn
;
13370 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13371 _("immediate out of range for narrowing operation"));
13372 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13376 do_neon_shll (void)
13378 /* FIXME: Type checking when lengthening. */
13379 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13380 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13381 unsigned imm
= inst
.operands
[2].imm
;
13383 if (imm
== et
.size
)
13385 /* Maximum shift variant. */
13386 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13389 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13391 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13393 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13397 /* A more-specific type check for non-max versions. */
13398 et
= neon_check_type (2, NS_QDI
,
13399 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13400 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13401 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13405 /* Check the various types for the VCVT instruction, and return which version
13406 the current instruction is. */
13409 neon_cvt_flavour (enum neon_shape rs
)
13411 #define CVT_VAR(C,X,Y) \
13412 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13413 if (et.type != NT_invtype) \
13415 inst.error = NULL; \
13418 struct neon_type_el et
;
13419 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13420 || rs
== NS_FF
) ? N_VFP
: 0;
13421 /* The instruction versions which take an immediate take one register
13422 argument, which is extended to the width of the full register. Thus the
13423 "source" and "destination" registers must have the same width. Hack that
13424 here by making the size equal to the key (wider, in this case) operand. */
13425 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13427 CVT_VAR (0, N_S32
, N_F32
);
13428 CVT_VAR (1, N_U32
, N_F32
);
13429 CVT_VAR (2, N_F32
, N_S32
);
13430 CVT_VAR (3, N_F32
, N_U32
);
13431 /* Half-precision conversions. */
13432 CVT_VAR (4, N_F32
, N_F16
);
13433 CVT_VAR (5, N_F16
, N_F32
);
13437 /* VFP instructions. */
13438 CVT_VAR (6, N_F32
, N_F64
);
13439 CVT_VAR (7, N_F64
, N_F32
);
13440 CVT_VAR (8, N_S32
, N_F64
| key
);
13441 CVT_VAR (9, N_U32
, N_F64
| key
);
13442 CVT_VAR (10, N_F64
| key
, N_S32
);
13443 CVT_VAR (11, N_F64
| key
, N_U32
);
13444 /* VFP instructions with bitshift. */
13445 CVT_VAR (12, N_F32
| key
, N_S16
);
13446 CVT_VAR (13, N_F32
| key
, N_U16
);
13447 CVT_VAR (14, N_F64
| key
, N_S16
);
13448 CVT_VAR (15, N_F64
| key
, N_U16
);
13449 CVT_VAR (16, N_S16
, N_F32
| key
);
13450 CVT_VAR (17, N_U16
, N_F32
| key
);
13451 CVT_VAR (18, N_S16
, N_F64
| key
);
13452 CVT_VAR (19, N_U16
, N_F64
| key
);
13458 /* Neon-syntax VFP conversions. */
13461 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13463 const char *opname
= 0;
13465 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13467 /* Conversions with immediate bitshift. */
13468 const char *enc
[] =
13492 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13494 opname
= enc
[flavour
];
13495 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13496 _("operands 0 and 1 must be the same register"));
13497 inst
.operands
[1] = inst
.operands
[2];
13498 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13503 /* Conversions without bitshift. */
13504 const char *enc
[] =
13520 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13521 opname
= enc
[flavour
];
13525 do_vfp_nsyn_opcode (opname
);
13529 do_vfp_nsyn_cvtz (void)
13531 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13532 int flavour
= neon_cvt_flavour (rs
);
13533 const char *enc
[] =
13547 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13548 do_vfp_nsyn_opcode (enc
[flavour
]);
13554 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13555 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13556 int flavour
= neon_cvt_flavour (rs
);
13558 /* VFP rather than Neon conversions. */
13561 do_vfp_nsyn_cvt (rs
, flavour
);
13571 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13573 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13576 /* Fixed-point conversion with #0 immediate is encoded as an
13577 integer conversion. */
13578 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13580 immbits
= 32 - inst
.operands
[2].imm
;
13581 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13583 inst
.instruction
|= enctab
[flavour
];
13584 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13585 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13586 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13587 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13588 inst
.instruction
|= neon_quad (rs
) << 6;
13589 inst
.instruction
|= 1 << 21;
13590 inst
.instruction
|= immbits
<< 16;
13592 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13600 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13602 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13604 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13608 inst
.instruction
|= enctab
[flavour
];
13610 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13611 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13612 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13613 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13614 inst
.instruction
|= neon_quad (rs
) << 6;
13615 inst
.instruction
|= 2 << 18;
13617 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13621 /* Half-precision conversions for Advanced SIMD -- neon. */
13626 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13628 as_bad (_("operand size must match register width"));
13633 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13635 as_bad (_("operand size must match register width"));
13640 inst
.instruction
= 0x3b60600;
13642 inst
.instruction
= 0x3b60700;
13644 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13645 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13646 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13647 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13648 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13652 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13653 do_vfp_nsyn_cvt (rs
, flavour
);
13658 do_neon_cvtb (void)
13660 inst
.instruction
= 0xeb20a40;
13662 /* The sizes are attached to the mnemonic. */
13663 if (inst
.vectype
.el
[0].type
!= NT_invtype
13664 && inst
.vectype
.el
[0].size
== 16)
13665 inst
.instruction
|= 0x00010000;
13667 /* Programmer's syntax: the sizes are attached to the operands. */
13668 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13669 && inst
.operands
[0].vectype
.size
== 16)
13670 inst
.instruction
|= 0x00010000;
13672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13673 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13674 do_vfp_cond_or_thumb ();
13679 do_neon_cvtt (void)
13682 inst
.instruction
|= 0x80;
13686 neon_move_immediate (void)
13688 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13689 struct neon_type_el et
= neon_check_type (2, rs
,
13690 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13691 unsigned immlo
, immhi
= 0, immbits
;
13692 int op
, cmode
, float_p
;
13694 constraint (et
.type
== NT_invtype
,
13695 _("operand size must be specified for immediate VMOV"));
13697 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13698 op
= (inst
.instruction
& (1 << 5)) != 0;
13700 immlo
= inst
.operands
[1].imm
;
13701 if (inst
.operands
[1].regisimm
)
13702 immhi
= inst
.operands
[1].reg
;
13704 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13705 _("immediate has bits set outside the operand size"));
13707 float_p
= inst
.operands
[1].immisfloat
;
13709 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13710 et
.size
, et
.type
)) == FAIL
)
13712 /* Invert relevant bits only. */
13713 neon_invert_size (&immlo
, &immhi
, et
.size
);
13714 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13715 with one or the other; those cases are caught by
13716 neon_cmode_for_move_imm. */
13718 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13719 &op
, et
.size
, et
.type
)) == FAIL
)
13721 first_error (_("immediate out of range"));
13726 inst
.instruction
&= ~(1 << 5);
13727 inst
.instruction
|= op
<< 5;
13729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13731 inst
.instruction
|= neon_quad (rs
) << 6;
13732 inst
.instruction
|= cmode
<< 8;
13734 neon_write_immbits (immbits
);
13740 if (inst
.operands
[1].isreg
)
13742 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13744 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13745 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13746 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13747 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13748 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13749 inst
.instruction
|= neon_quad (rs
) << 6;
13753 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13754 neon_move_immediate ();
13757 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13760 /* Encode instructions of form:
13762 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13763 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13766 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13768 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13769 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13770 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13771 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13772 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13773 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13774 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13775 inst
.instruction
|= neon_logbits (size
) << 20;
13777 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13781 do_neon_dyadic_long (void)
13783 /* FIXME: Type checking for lengthening op. */
13784 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13785 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13786 neon_mixed_length (et
, et
.size
);
13790 do_neon_abal (void)
13792 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13793 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13794 neon_mixed_length (et
, et
.size
);
13798 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13800 if (inst
.operands
[2].isscalar
)
13802 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13803 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13804 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13805 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13809 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13810 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13811 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13812 neon_mixed_length (et
, et
.size
);
13817 do_neon_mac_maybe_scalar_long (void)
13819 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13823 do_neon_dyadic_wide (void)
13825 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13826 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13827 neon_mixed_length (et
, et
.size
);
13831 do_neon_dyadic_narrow (void)
13833 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13834 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13835 /* Operand sign is unimportant, and the U bit is part of the opcode,
13836 so force the operand type to integer. */
13837 et
.type
= NT_integer
;
13838 neon_mixed_length (et
, et
.size
/ 2);
13842 do_neon_mul_sat_scalar_long (void)
13844 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13848 do_neon_vmull (void)
13850 if (inst
.operands
[2].isscalar
)
13851 do_neon_mac_maybe_scalar_long ();
13854 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13855 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13856 if (et
.type
== NT_poly
)
13857 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13859 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13860 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13861 zero. Should be OK as-is. */
13862 neon_mixed_length (et
, et
.size
);
13869 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13870 struct neon_type_el et
= neon_check_type (3, rs
,
13871 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13872 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13874 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13875 _("shift out of range"));
13876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13878 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13879 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13880 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13881 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13882 inst
.instruction
|= neon_quad (rs
) << 6;
13883 inst
.instruction
|= imm
<< 8;
13885 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13891 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13892 struct neon_type_el et
= neon_check_type (2, rs
,
13893 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13894 unsigned op
= (inst
.instruction
>> 7) & 3;
13895 /* N (width of reversed regions) is encoded as part of the bitmask. We
13896 extract it here to check the elements to be reversed are smaller.
13897 Otherwise we'd get a reserved instruction. */
13898 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13899 gas_assert (elsize
!= 0);
13900 constraint (et
.size
>= elsize
,
13901 _("elements must be smaller than reversal region"));
13902 neon_two_same (neon_quad (rs
), 1, et
.size
);
13908 if (inst
.operands
[1].isscalar
)
13910 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13911 struct neon_type_el et
= neon_check_type (2, rs
,
13912 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13913 unsigned sizebits
= et
.size
>> 3;
13914 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13915 int logsize
= neon_logbits (et
.size
);
13916 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13918 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13921 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13922 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13923 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13924 inst
.instruction
|= LOW4 (dm
);
13925 inst
.instruction
|= HI1 (dm
) << 5;
13926 inst
.instruction
|= neon_quad (rs
) << 6;
13927 inst
.instruction
|= x
<< 17;
13928 inst
.instruction
|= sizebits
<< 16;
13930 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13934 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13935 struct neon_type_el et
= neon_check_type (2, rs
,
13936 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13937 /* Duplicate ARM register to lanes of vector. */
13938 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13941 case 8: inst
.instruction
|= 0x400000; break;
13942 case 16: inst
.instruction
|= 0x000020; break;
13943 case 32: inst
.instruction
|= 0x000000; break;
13946 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13947 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13948 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13949 inst
.instruction
|= neon_quad (rs
) << 21;
13950 /* The encoding for this instruction is identical for the ARM and Thumb
13951 variants, except for the condition field. */
13952 do_vfp_cond_or_thumb ();
13956 /* VMOV has particularly many variations. It can be one of:
13957 0. VMOV<c><q> <Qd>, <Qm>
13958 1. VMOV<c><q> <Dd>, <Dm>
13959 (Register operations, which are VORR with Rm = Rn.)
13960 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13961 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13963 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13964 (ARM register to scalar.)
13965 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13966 (Two ARM registers to vector.)
13967 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13968 (Scalar to ARM register.)
13969 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13970 (Vector to two ARM registers.)
13971 8. VMOV.F32 <Sd>, <Sm>
13972 9. VMOV.F64 <Dd>, <Dm>
13973 (VFP register moves.)
13974 10. VMOV.F32 <Sd>, #imm
13975 11. VMOV.F64 <Dd>, #imm
13976 (VFP float immediate load.)
13977 12. VMOV <Rd>, <Sm>
13978 (VFP single to ARM reg.)
13979 13. VMOV <Sd>, <Rm>
13980 (ARM reg to VFP single.)
13981 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13982 (Two ARM regs to two VFP singles.)
13983 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13984 (Two VFP singles to two ARM regs.)
13986 These cases can be disambiguated using neon_select_shape, except cases 1/9
13987 and 3/11 which depend on the operand type too.
13989 All the encoded bits are hardcoded by this function.
13991 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13992 Cases 5, 7 may be used with VFPv2 and above.
13994 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13995 can specify a type where it doesn't make sense to, and is ignored). */
14000 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14001 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14003 struct neon_type_el et
;
14004 const char *ldconst
= 0;
14008 case NS_DD
: /* case 1/9. */
14009 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14010 /* It is not an error here if no type is given. */
14012 if (et
.type
== NT_float
&& et
.size
== 64)
14014 do_vfp_nsyn_opcode ("fcpyd");
14017 /* fall through. */
14019 case NS_QQ
: /* case 0/1. */
14021 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14023 /* The architecture manual I have doesn't explicitly state which
14024 value the U bit should have for register->register moves, but
14025 the equivalent VORR instruction has U = 0, so do that. */
14026 inst
.instruction
= 0x0200110;
14027 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14028 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14029 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14033 inst
.instruction
|= neon_quad (rs
) << 6;
14035 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14039 case NS_DI
: /* case 3/11. */
14040 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14042 if (et
.type
== NT_float
&& et
.size
== 64)
14044 /* case 11 (fconstd). */
14045 ldconst
= "fconstd";
14046 goto encode_fconstd
;
14048 /* fall through. */
14050 case NS_QI
: /* case 2/3. */
14051 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14053 inst
.instruction
= 0x0800010;
14054 neon_move_immediate ();
14055 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14058 case NS_SR
: /* case 4. */
14060 unsigned bcdebits
= 0;
14061 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14062 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14063 int logsize
= neon_logbits (et
.size
);
14064 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14065 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14070 && et
.size
!= 32, _(BAD_FPU
));
14071 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14072 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14076 case 8: bcdebits
= 0x8; break;
14077 case 16: bcdebits
= 0x1; break;
14078 case 32: bcdebits
= 0x0; break;
14082 bcdebits
|= x
<< logsize
;
14084 inst
.instruction
= 0xe000b10;
14085 do_vfp_cond_or_thumb ();
14086 inst
.instruction
|= LOW4 (dn
) << 16;
14087 inst
.instruction
|= HI1 (dn
) << 7;
14088 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14089 inst
.instruction
|= (bcdebits
& 3) << 5;
14090 inst
.instruction
|= (bcdebits
>> 2) << 21;
14094 case NS_DRR
: /* case 5 (fmdrr). */
14095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14098 inst
.instruction
= 0xc400b10;
14099 do_vfp_cond_or_thumb ();
14100 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14101 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14102 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14103 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14106 case NS_RS
: /* case 6. */
14108 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14109 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14110 unsigned logsize
= neon_logbits (et
.size
);
14111 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14112 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14113 unsigned abcdebits
= 0;
14115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14117 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14118 && et
.size
!= 32, _(BAD_FPU
));
14119 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14120 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14124 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14125 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14126 case 32: abcdebits
= 0x00; break;
14130 abcdebits
|= x
<< logsize
;
14131 inst
.instruction
= 0xe100b10;
14132 do_vfp_cond_or_thumb ();
14133 inst
.instruction
|= LOW4 (dn
) << 16;
14134 inst
.instruction
|= HI1 (dn
) << 7;
14135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14136 inst
.instruction
|= (abcdebits
& 3) << 5;
14137 inst
.instruction
|= (abcdebits
>> 2) << 21;
14141 case NS_RRD
: /* case 7 (fmrrd). */
14142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14145 inst
.instruction
= 0xc500b10;
14146 do_vfp_cond_or_thumb ();
14147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14148 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14149 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14150 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14153 case NS_FF
: /* case 8 (fcpys). */
14154 do_vfp_nsyn_opcode ("fcpys");
14157 case NS_FI
: /* case 10 (fconsts). */
14158 ldconst
= "fconsts";
14160 if (is_quarter_float (inst
.operands
[1].imm
))
14162 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14163 do_vfp_nsyn_opcode (ldconst
);
14166 first_error (_("immediate out of range"));
14169 case NS_RF
: /* case 12 (fmrs). */
14170 do_vfp_nsyn_opcode ("fmrs");
14173 case NS_FR
: /* case 13 (fmsr). */
14174 do_vfp_nsyn_opcode ("fmsr");
14177 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14178 (one of which is a list), but we have parsed four. Do some fiddling to
14179 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14181 case NS_RRFF
: /* case 14 (fmrrs). */
14182 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14183 _("VFP registers must be adjacent"));
14184 inst
.operands
[2].imm
= 2;
14185 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14186 do_vfp_nsyn_opcode ("fmrrs");
14189 case NS_FFRR
: /* case 15 (fmsrr). */
14190 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14191 _("VFP registers must be adjacent"));
14192 inst
.operands
[1] = inst
.operands
[2];
14193 inst
.operands
[2] = inst
.operands
[3];
14194 inst
.operands
[0].imm
= 2;
14195 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14196 do_vfp_nsyn_opcode ("fmsrr");
14205 do_neon_rshift_round_imm (void)
14207 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14208 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14209 int imm
= inst
.operands
[2].imm
;
14211 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14214 inst
.operands
[2].present
= 0;
14219 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14220 _("immediate out of range for shift"));
14221 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14226 do_neon_movl (void)
14228 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14229 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14230 unsigned sizebits
= et
.size
>> 3;
14231 inst
.instruction
|= sizebits
<< 19;
14232 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14238 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14239 struct neon_type_el et
= neon_check_type (2, rs
,
14240 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14241 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14242 neon_two_same (neon_quad (rs
), 1, et
.size
);
14246 do_neon_zip_uzp (void)
14248 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14249 struct neon_type_el et
= neon_check_type (2, rs
,
14250 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14251 if (rs
== NS_DD
&& et
.size
== 32)
14253 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14254 inst
.instruction
= N_MNEM_vtrn
;
14258 neon_two_same (neon_quad (rs
), 1, et
.size
);
14262 do_neon_sat_abs_neg (void)
14264 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14265 struct neon_type_el et
= neon_check_type (2, rs
,
14266 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14267 neon_two_same (neon_quad (rs
), 1, et
.size
);
14271 do_neon_pair_long (void)
14273 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14274 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14275 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14276 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14277 neon_two_same (neon_quad (rs
), 1, et
.size
);
14281 do_neon_recip_est (void)
14283 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14284 struct neon_type_el et
= neon_check_type (2, rs
,
14285 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14286 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14287 neon_two_same (neon_quad (rs
), 1, et
.size
);
14293 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14294 struct neon_type_el et
= neon_check_type (2, rs
,
14295 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14296 neon_two_same (neon_quad (rs
), 1, et
.size
);
14302 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14303 struct neon_type_el et
= neon_check_type (2, rs
,
14304 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14305 neon_two_same (neon_quad (rs
), 1, et
.size
);
14311 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14312 struct neon_type_el et
= neon_check_type (2, rs
,
14313 N_EQK
| N_INT
, N_8
| N_KEY
);
14314 neon_two_same (neon_quad (rs
), 1, et
.size
);
14320 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14321 neon_two_same (neon_quad (rs
), 1, -1);
14325 do_neon_tbl_tbx (void)
14327 unsigned listlenbits
;
14328 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14330 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14332 first_error (_("bad list length for table lookup"));
14336 listlenbits
= inst
.operands
[1].imm
- 1;
14337 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14338 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14339 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14340 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14341 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14342 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14343 inst
.instruction
|= listlenbits
<< 8;
14345 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14349 do_neon_ldm_stm (void)
14351 /* P, U and L bits are part of bitmask. */
14352 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14353 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14355 if (inst
.operands
[1].issingle
)
14357 do_vfp_nsyn_ldm_stm (is_dbmode
);
14361 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14362 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14364 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14365 _("register list must contain at least 1 and at most 16 "
14368 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14369 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14373 inst
.instruction
|= offsetbits
;
14375 do_vfp_cond_or_thumb ();
14379 do_neon_ldr_str (void)
14381 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14383 if (inst
.operands
[0].issingle
)
14386 do_vfp_nsyn_opcode ("flds");
14388 do_vfp_nsyn_opcode ("fsts");
14393 do_vfp_nsyn_opcode ("fldd");
14395 do_vfp_nsyn_opcode ("fstd");
14399 /* "interleave" version also handles non-interleaving register VLD1/VST1
14403 do_neon_ld_st_interleave (void)
14405 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14406 N_8
| N_16
| N_32
| N_64
);
14407 unsigned alignbits
= 0;
14409 /* The bits in this table go:
14410 0: register stride of one (0) or two (1)
14411 1,2: register list length, minus one (1, 2, 3, 4).
14412 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14413 We use -1 for invalid entries. */
14414 const int typetable
[] =
14416 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14417 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14418 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14419 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14423 if (et
.type
== NT_invtype
)
14426 if (inst
.operands
[1].immisalign
)
14427 switch (inst
.operands
[1].imm
>> 8)
14429 case 64: alignbits
= 1; break;
14431 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14432 goto bad_alignment
;
14436 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14437 goto bad_alignment
;
14442 first_error (_("bad alignment"));
14446 inst
.instruction
|= alignbits
<< 4;
14447 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14449 /* Bits [4:6] of the immediate in a list specifier encode register stride
14450 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14451 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14452 up the right value for "type" in a table based on this value and the given
14453 list style, then stick it back. */
14454 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14455 | (((inst
.instruction
>> 8) & 3) << 3);
14457 typebits
= typetable
[idx
];
14459 constraint (typebits
== -1, _("bad list type for instruction"));
14461 inst
.instruction
&= ~0xf00;
14462 inst
.instruction
|= typebits
<< 8;
14465 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14466 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14467 otherwise. The variable arguments are a list of pairs of legal (size, align)
14468 values, terminated with -1. */
14471 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14474 int result
= FAIL
, thissize
, thisalign
;
14476 if (!inst
.operands
[1].immisalign
)
14482 va_start (ap
, do_align
);
14486 thissize
= va_arg (ap
, int);
14487 if (thissize
== -1)
14489 thisalign
= va_arg (ap
, int);
14491 if (size
== thissize
&& align
== thisalign
)
14494 while (result
!= SUCCESS
);
14498 if (result
== SUCCESS
)
14501 first_error (_("unsupported alignment for instruction"));
14507 do_neon_ld_st_lane (void)
14509 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14510 int align_good
, do_align
= 0;
14511 int logsize
= neon_logbits (et
.size
);
14512 int align
= inst
.operands
[1].imm
>> 8;
14513 int n
= (inst
.instruction
>> 8) & 3;
14514 int max_el
= 64 / et
.size
;
14516 if (et
.type
== NT_invtype
)
14519 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14520 _("bad list length"));
14521 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14522 _("scalar index out of range"));
14523 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14525 _("stride of 2 unavailable when element size is 8"));
14529 case 0: /* VLD1 / VST1. */
14530 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14532 if (align_good
== FAIL
)
14536 unsigned alignbits
= 0;
14539 case 16: alignbits
= 0x1; break;
14540 case 32: alignbits
= 0x3; break;
14543 inst
.instruction
|= alignbits
<< 4;
14547 case 1: /* VLD2 / VST2. */
14548 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14550 if (align_good
== FAIL
)
14553 inst
.instruction
|= 1 << 4;
14556 case 2: /* VLD3 / VST3. */
14557 constraint (inst
.operands
[1].immisalign
,
14558 _("can't use alignment with this instruction"));
14561 case 3: /* VLD4 / VST4. */
14562 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14563 16, 64, 32, 64, 32, 128, -1);
14564 if (align_good
== FAIL
)
14568 unsigned alignbits
= 0;
14571 case 8: alignbits
= 0x1; break;
14572 case 16: alignbits
= 0x1; break;
14573 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14576 inst
.instruction
|= alignbits
<< 4;
14583 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14584 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14585 inst
.instruction
|= 1 << (4 + logsize
);
14587 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14588 inst
.instruction
|= logsize
<< 10;
14591 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14594 do_neon_ld_dup (void)
14596 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14597 int align_good
, do_align
= 0;
14599 if (et
.type
== NT_invtype
)
14602 switch ((inst
.instruction
>> 8) & 3)
14604 case 0: /* VLD1. */
14605 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14606 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14607 &do_align
, 16, 16, 32, 32, -1);
14608 if (align_good
== FAIL
)
14610 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14613 case 2: inst
.instruction
|= 1 << 5; break;
14614 default: first_error (_("bad list length")); return;
14616 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14619 case 1: /* VLD2. */
14620 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14621 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14622 if (align_good
== FAIL
)
14624 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14625 _("bad list length"));
14626 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14627 inst
.instruction
|= 1 << 5;
14628 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14631 case 2: /* VLD3. */
14632 constraint (inst
.operands
[1].immisalign
,
14633 _("can't use alignment with this instruction"));
14634 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14635 _("bad list length"));
14636 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14637 inst
.instruction
|= 1 << 5;
14638 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14641 case 3: /* VLD4. */
14643 int align
= inst
.operands
[1].imm
>> 8;
14644 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14645 16, 64, 32, 64, 32, 128, -1);
14646 if (align_good
== FAIL
)
14648 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14649 _("bad list length"));
14650 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14651 inst
.instruction
|= 1 << 5;
14652 if (et
.size
== 32 && align
== 128)
14653 inst
.instruction
|= 0x3 << 6;
14655 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14662 inst
.instruction
|= do_align
<< 4;
14665 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14666 apart from bits [11:4]. */
14669 do_neon_ldx_stx (void)
14671 switch (NEON_LANE (inst
.operands
[0].imm
))
14673 case NEON_INTERLEAVE_LANES
:
14674 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14675 do_neon_ld_st_interleave ();
14678 case NEON_ALL_LANES
:
14679 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14684 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14685 do_neon_ld_st_lane ();
14688 /* L bit comes from bit mask. */
14689 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14690 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14691 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14693 if (inst
.operands
[1].postind
)
14695 int postreg
= inst
.operands
[1].imm
& 0xf;
14696 constraint (!inst
.operands
[1].immisreg
,
14697 _("post-index must be a register"));
14698 constraint (postreg
== 0xd || postreg
== 0xf,
14699 _("bad register for post-index"));
14700 inst
.instruction
|= postreg
;
14702 else if (inst
.operands
[1].writeback
)
14704 inst
.instruction
|= 0xd;
14707 inst
.instruction
|= 0xf;
14710 inst
.instruction
|= 0xf9000000;
14712 inst
.instruction
|= 0xf4000000;
14715 /* Overall per-instruction processing. */
14717 /* We need to be able to fix up arbitrary expressions in some statements.
14718 This is so that we can handle symbols that are an arbitrary distance from
14719 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14720 which returns part of an address in a form which will be valid for
14721 a data instruction. We do this by pushing the expression into a symbol
14722 in the expr_section, and creating a fix for that. */
14725 fix_new_arm (fragS
* frag
,
14740 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14741 (enum bfd_reloc_code_real
) reloc
);
14745 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14746 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14750 /* Mark whether the fix is to a THUMB instruction, or an ARM
14752 new_fix
->tc_fix_data
= thumb_mode
;
14755 /* Create a frg for an instruction requiring relaxation. */
14757 output_relax_insn (void)
14763 /* The size of the instruction is unknown, so tie the debug info to the
14764 start of the instruction. */
14765 dwarf2_emit_insn (0);
14767 switch (inst
.reloc
.exp
.X_op
)
14770 sym
= inst
.reloc
.exp
.X_add_symbol
;
14771 offset
= inst
.reloc
.exp
.X_add_number
;
14775 offset
= inst
.reloc
.exp
.X_add_number
;
14778 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14782 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14783 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14784 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14787 /* Write a 32-bit thumb instruction to buf. */
14789 put_thumb32_insn (char * buf
, unsigned long insn
)
14791 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14792 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14796 output_inst (const char * str
)
14802 as_bad ("%s -- `%s'", inst
.error
, str
);
14807 output_relax_insn ();
14810 if (inst
.size
== 0)
14813 to
= frag_more (inst
.size
);
14814 /* PR 9814: Record the thumb mode into the current frag so that we know
14815 what type of NOP padding to use, if necessary. We override any previous
14816 setting so that if the mode has changed then the NOPS that we use will
14817 match the encoding of the last instruction in the frag. */
14818 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14820 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14822 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14823 put_thumb32_insn (to
, inst
.instruction
);
14825 else if (inst
.size
> INSN_SIZE
)
14827 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14828 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14829 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14832 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14834 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14835 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14836 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14839 dwarf2_emit_insn (inst
.size
);
14843 output_it_inst (int cond
, int mask
, char * to
)
14845 unsigned long instruction
= 0xbf00;
14848 instruction
|= mask
;
14849 instruction
|= cond
<< 4;
14853 to
= frag_more (2);
14855 dwarf2_emit_insn (2);
14859 md_number_to_chars (to
, instruction
, 2);
14864 /* Tag values used in struct asm_opcode's tag field. */
14867 OT_unconditional
, /* Instruction cannot be conditionalized.
14868 The ARM condition field is still 0xE. */
14869 OT_unconditionalF
, /* Instruction cannot be conditionalized
14870 and carries 0xF in its ARM condition field. */
14871 OT_csuffix
, /* Instruction takes a conditional suffix. */
14872 OT_csuffixF
, /* Some forms of the instruction take a conditional
14873 suffix, others place 0xF where the condition field
14875 OT_cinfix3
, /* Instruction takes a conditional infix,
14876 beginning at character index 3. (In
14877 unified mode, it becomes a suffix.) */
14878 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14879 tsts, cmps, cmns, and teqs. */
14880 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14881 character index 3, even in unified mode. Used for
14882 legacy instructions where suffix and infix forms
14883 may be ambiguous. */
14884 OT_csuf_or_in3
, /* Instruction takes either a conditional
14885 suffix or an infix at character index 3. */
14886 OT_odd_infix_unc
, /* This is the unconditional variant of an
14887 instruction that takes a conditional infix
14888 at an unusual position. In unified mode,
14889 this variant will accept a suffix. */
14890 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14891 are the conditional variants of instructions that
14892 take conditional infixes in unusual positions.
14893 The infix appears at character index
14894 (tag - OT_odd_infix_0). These are not accepted
14895 in unified mode. */
14898 /* Subroutine of md_assemble, responsible for looking up the primary
14899 opcode from the mnemonic the user wrote. STR points to the
14900 beginning of the mnemonic.
14902 This is not simply a hash table lookup, because of conditional
14903 variants. Most instructions have conditional variants, which are
14904 expressed with a _conditional affix_ to the mnemonic. If we were
14905 to encode each conditional variant as a literal string in the opcode
14906 table, it would have approximately 20,000 entries.
14908 Most mnemonics take this affix as a suffix, and in unified syntax,
14909 'most' is upgraded to 'all'. However, in the divided syntax, some
14910 instructions take the affix as an infix, notably the s-variants of
14911 the arithmetic instructions. Of those instructions, all but six
14912 have the infix appear after the third character of the mnemonic.
14914 Accordingly, the algorithm for looking up primary opcodes given
14917 1. Look up the identifier in the opcode table.
14918 If we find a match, go to step U.
14920 2. Look up the last two characters of the identifier in the
14921 conditions table. If we find a match, look up the first N-2
14922 characters of the identifier in the opcode table. If we
14923 find a match, go to step CE.
14925 3. Look up the fourth and fifth characters of the identifier in
14926 the conditions table. If we find a match, extract those
14927 characters from the identifier, and look up the remaining
14928 characters in the opcode table. If we find a match, go
14933 U. Examine the tag field of the opcode structure, in case this is
14934 one of the six instructions with its conditional infix in an
14935 unusual place. If it is, the tag tells us where to find the
14936 infix; look it up in the conditions table and set inst.cond
14937 accordingly. Otherwise, this is an unconditional instruction.
14938 Again set inst.cond accordingly. Return the opcode structure.
14940 CE. Examine the tag field to make sure this is an instruction that
14941 should receive a conditional suffix. If it is not, fail.
14942 Otherwise, set inst.cond from the suffix we already looked up,
14943 and return the opcode structure.
14945 CM. Examine the tag field to make sure this is an instruction that
14946 should receive a conditional infix after the third character.
14947 If it is not, fail. Otherwise, undo the edits to the current
14948 line of input and proceed as for case CE. */
14950 static const struct asm_opcode
*
14951 opcode_lookup (char **str
)
14955 const struct asm_opcode
*opcode
;
14956 const struct asm_cond
*cond
;
14959 /* Scan up to the end of the mnemonic, which must end in white space,
14960 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
14961 for (base
= end
= *str
; *end
!= '\0'; end
++)
14962 if (*end
== ' ' || *end
== '.')
14968 /* Handle a possible width suffix and/or Neon type suffix. */
14973 /* The .w and .n suffixes are only valid if the unified syntax is in
14975 if (unified_syntax
&& end
[1] == 'w')
14977 else if (unified_syntax
&& end
[1] == 'n')
14982 inst
.vectype
.elems
= 0;
14984 *str
= end
+ offset
;
14986 if (end
[offset
] == '.')
14988 /* See if we have a Neon type suffix (possible in either unified or
14989 non-unified ARM syntax mode). */
14990 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14993 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14999 /* Look for unaffixed or special-case affixed mnemonic. */
15000 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15005 if (opcode
->tag
< OT_odd_infix_0
)
15007 inst
.cond
= COND_ALWAYS
;
15011 if (warn_on_deprecated
&& unified_syntax
)
15012 as_warn (_("conditional infixes are deprecated in unified syntax"));
15013 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15014 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15017 inst
.cond
= cond
->value
;
15021 /* Cannot have a conditional suffix on a mnemonic of less than two
15023 if (end
- base
< 3)
15026 /* Look for suffixed mnemonic. */
15028 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15029 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15031 if (opcode
&& cond
)
15034 switch (opcode
->tag
)
15036 case OT_cinfix3_legacy
:
15037 /* Ignore conditional suffixes matched on infix only mnemonics. */
15041 case OT_cinfix3_deprecated
:
15042 case OT_odd_infix_unc
:
15043 if (!unified_syntax
)
15045 /* else fall through */
15049 case OT_csuf_or_in3
:
15050 inst
.cond
= cond
->value
;
15053 case OT_unconditional
:
15054 case OT_unconditionalF
:
15056 inst
.cond
= cond
->value
;
15059 /* Delayed diagnostic. */
15060 inst
.error
= BAD_COND
;
15061 inst
.cond
= COND_ALWAYS
;
15070 /* Cannot have a usual-position infix on a mnemonic of less than
15071 six characters (five would be a suffix). */
15072 if (end
- base
< 6)
15075 /* Look for infixed mnemonic in the usual position. */
15077 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15081 memcpy (save
, affix
, 2);
15082 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15083 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15085 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15086 memcpy (affix
, save
, 2);
15089 && (opcode
->tag
== OT_cinfix3
15090 || opcode
->tag
== OT_cinfix3_deprecated
15091 || opcode
->tag
== OT_csuf_or_in3
15092 || opcode
->tag
== OT_cinfix3_legacy
))
15095 if (warn_on_deprecated
&& unified_syntax
15096 && (opcode
->tag
== OT_cinfix3
15097 || opcode
->tag
== OT_cinfix3_deprecated
))
15098 as_warn (_("conditional infixes are deprecated in unified syntax"));
15100 inst
.cond
= cond
->value
;
15107 /* This function generates an initial IT instruction, leaving its block
15108 virtually open for the new instructions. Eventually,
15109 the mask will be updated by now_it_add_mask () each time
15110 a new instruction needs to be included in the IT block.
15111 Finally, the block is closed with close_automatic_it_block ().
15112 The block closure can be requested either from md_assemble (),
15113 a tencode (), or due to a label hook. */
15116 new_automatic_it_block (int cond
)
15118 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15119 now_it
.mask
= 0x18;
15121 now_it
.block_length
= 1;
15122 mapping_state (MAP_THUMB
);
15123 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15126 /* Close an automatic IT block.
15127 See comments in new_automatic_it_block (). */
15130 close_automatic_it_block (void)
15132 now_it
.mask
= 0x10;
15133 now_it
.block_length
= 0;
15136 /* Update the mask of the current automatically-generated IT
15137 instruction. See comments in new_automatic_it_block (). */
15140 now_it_add_mask (int cond
)
15142 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15143 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15144 | ((bitvalue) << (nbit)))
15145 const int resulting_bit
= (cond
& 1);
15147 now_it
.mask
&= 0xf;
15148 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15150 (5 - now_it
.block_length
));
15151 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15153 ((5 - now_it
.block_length
) - 1) );
15154 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15157 #undef SET_BIT_VALUE
15160 /* The IT blocks handling machinery is accessed through the these functions:
15161 it_fsm_pre_encode () from md_assemble ()
15162 set_it_insn_type () optional, from the tencode functions
15163 set_it_insn_type_last () ditto
15164 in_it_block () ditto
15165 it_fsm_post_encode () from md_assemble ()
15166 force_automatic_it_block_close () from label habdling functions
15169 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15170 initializing the IT insn type with a generic initial value depending
15171 on the inst.condition.
15172 2) During the tencode function, two things may happen:
15173 a) The tencode function overrides the IT insn type by
15174 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15175 b) The tencode function queries the IT block state by
15176 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15178 Both set_it_insn_type and in_it_block run the internal FSM state
15179 handling function (handle_it_state), because: a) setting the IT insn
15180 type may incur in an invalid state (exiting the function),
15181 and b) querying the state requires the FSM to be updated.
15182 Specifically we want to avoid creating an IT block for conditional
15183 branches, so it_fsm_pre_encode is actually a guess and we can't
15184 determine whether an IT block is required until the tencode () routine
15185 has decided what type of instruction this actually it.
15186 Because of this, if set_it_insn_type and in_it_block have to be used,
15187 set_it_insn_type has to be called first.
15189 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15190 determines the insn IT type depending on the inst.cond code.
15191 When a tencode () routine encodes an instruction that can be
15192 either outside an IT block, or, in the case of being inside, has to be
15193 the last one, set_it_insn_type_last () will determine the proper
15194 IT instruction type based on the inst.cond code. Otherwise,
15195 set_it_insn_type can be called for overriding that logic or
15196 for covering other cases.
15198 Calling handle_it_state () may not transition the IT block state to
15199 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15200 still queried. Instead, if the FSM determines that the state should
15201 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15202 after the tencode () function: that's what it_fsm_post_encode () does.
15204 Since in_it_block () calls the state handling function to get an
15205 updated state, an error may occur (due to invalid insns combination).
15206 In that case, inst.error is set.
15207 Therefore, inst.error has to be checked after the execution of
15208 the tencode () routine.
15210 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15211 any pending state change (if any) that didn't take place in
15212 handle_it_state () as explained above. */
15215 it_fsm_pre_encode (void)
15217 if (inst
.cond
!= COND_ALWAYS
)
15218 inst
.it_insn_type
= INSIDE_IT_INSN
;
15220 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15222 now_it
.state_handled
= 0;
15225 /* IT state FSM handling function. */
15228 handle_it_state (void)
15230 now_it
.state_handled
= 1;
15232 switch (now_it
.state
)
15234 case OUTSIDE_IT_BLOCK
:
15235 switch (inst
.it_insn_type
)
15237 case OUTSIDE_IT_INSN
:
15240 case INSIDE_IT_INSN
:
15241 case INSIDE_IT_LAST_INSN
:
15242 if (thumb_mode
== 0)
15245 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15246 as_tsktsk (_("Warning: conditional outside an IT block"\
15251 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15252 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15254 /* Automatically generate the IT instruction. */
15255 new_automatic_it_block (inst
.cond
);
15256 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15257 close_automatic_it_block ();
15261 inst
.error
= BAD_OUT_IT
;
15267 case IF_INSIDE_IT_LAST_INSN
:
15268 case NEUTRAL_IT_INSN
:
15272 now_it
.state
= MANUAL_IT_BLOCK
;
15273 now_it
.block_length
= 0;
15278 case AUTOMATIC_IT_BLOCK
:
15279 /* Three things may happen now:
15280 a) We should increment current it block size;
15281 b) We should close current it block (closing insn or 4 insns);
15282 c) We should close current it block and start a new one (due
15283 to incompatible conditions or
15284 4 insns-length block reached). */
15286 switch (inst
.it_insn_type
)
15288 case OUTSIDE_IT_INSN
:
15289 /* The closure of the block shall happen immediatelly,
15290 so any in_it_block () call reports the block as closed. */
15291 force_automatic_it_block_close ();
15294 case INSIDE_IT_INSN
:
15295 case INSIDE_IT_LAST_INSN
:
15296 case IF_INSIDE_IT_LAST_INSN
:
15297 now_it
.block_length
++;
15299 if (now_it
.block_length
> 4
15300 || !now_it_compatible (inst
.cond
))
15302 force_automatic_it_block_close ();
15303 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15304 new_automatic_it_block (inst
.cond
);
15308 now_it_add_mask (inst
.cond
);
15311 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15312 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15313 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15314 close_automatic_it_block ();
15317 case NEUTRAL_IT_INSN
:
15318 now_it
.block_length
++;
15320 if (now_it
.block_length
> 4)
15321 force_automatic_it_block_close ();
15323 now_it_add_mask (now_it
.cc
& 1);
15327 close_automatic_it_block ();
15328 now_it
.state
= MANUAL_IT_BLOCK
;
15333 case MANUAL_IT_BLOCK
:
15335 /* Check conditional suffixes. */
15336 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15339 now_it
.mask
&= 0x1f;
15340 is_last
= (now_it
.mask
== 0x10);
15342 switch (inst
.it_insn_type
)
15344 case OUTSIDE_IT_INSN
:
15345 inst
.error
= BAD_NOT_IT
;
15348 case INSIDE_IT_INSN
:
15349 if (cond
!= inst
.cond
)
15351 inst
.error
= BAD_IT_COND
;
15356 case INSIDE_IT_LAST_INSN
:
15357 case IF_INSIDE_IT_LAST_INSN
:
15358 if (cond
!= inst
.cond
)
15360 inst
.error
= BAD_IT_COND
;
15365 inst
.error
= BAD_BRANCH
;
15370 case NEUTRAL_IT_INSN
:
15371 /* The BKPT instruction is unconditional even in an IT block. */
15375 inst
.error
= BAD_IT_IT
;
15386 it_fsm_post_encode (void)
15390 if (!now_it
.state_handled
)
15391 handle_it_state ();
15393 is_last
= (now_it
.mask
== 0x10);
15396 now_it
.state
= OUTSIDE_IT_BLOCK
;
15402 force_automatic_it_block_close (void)
15404 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15406 close_automatic_it_block ();
15407 now_it
.state
= OUTSIDE_IT_BLOCK
;
15415 if (!now_it
.state_handled
)
15416 handle_it_state ();
15418 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15422 md_assemble (char *str
)
15425 const struct asm_opcode
* opcode
;
15427 /* Align the previous label if needed. */
15428 if (last_label_seen
!= NULL
)
15430 symbol_set_frag (last_label_seen
, frag_now
);
15431 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15432 S_SET_SEGMENT (last_label_seen
, now_seg
);
15435 memset (&inst
, '\0', sizeof (inst
));
15436 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15438 opcode
= opcode_lookup (&p
);
15441 /* It wasn't an instruction, but it might be a register alias of
15442 the form alias .req reg, or a Neon .dn/.qn directive. */
15443 if (! create_register_alias (str
, p
)
15444 && ! create_neon_reg_alias (str
, p
))
15445 as_bad (_("bad instruction `%s'"), str
);
15450 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15451 as_warn (_("s suffix on comparison instruction is deprecated"));
15453 /* The value which unconditional instructions should have in place of the
15454 condition field. */
15455 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15459 arm_feature_set variant
;
15461 variant
= cpu_variant
;
15462 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15463 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15464 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15465 /* Check that this instruction is supported for this CPU. */
15466 if (!opcode
->tvariant
15467 || (thumb_mode
== 1
15468 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15470 as_bad (_("selected processor does not support `%s'"), str
);
15473 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15474 && opcode
->tencode
!= do_t_branch
)
15476 as_bad (_("Thumb does not support conditional execution"));
15480 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15482 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15483 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15484 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15486 /* Two things are addressed here.
15487 1) Implicit require narrow instructions on Thumb-1.
15488 This avoids relaxation accidentally introducing Thumb-2
15490 2) Reject wide instructions in non Thumb-2 cores. */
15491 if (inst
.size_req
== 0)
15493 else if (inst
.size_req
== 4)
15495 as_bad (_("selected processor does not support `%s'"), str
);
15501 inst
.instruction
= opcode
->tvalue
;
15503 if (!parse_operands (p
, opcode
->operands
))
15505 /* Prepare the it_insn_type for those encodings that don't set
15507 it_fsm_pre_encode ();
15509 opcode
->tencode ();
15511 it_fsm_post_encode ();
15514 if (!(inst
.error
|| inst
.relax
))
15516 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15517 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15518 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15520 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15525 /* Something has gone badly wrong if we try to relax a fixed size
15527 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15529 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15530 *opcode
->tvariant
);
15531 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15532 set those bits when Thumb-2 32-bit instructions are seen. ie.
15533 anything other than bl/blx and v6-M instructions.
15534 This is overly pessimistic for relaxable instructions. */
15535 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15537 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15538 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15539 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15544 mapping_state (MAP_THUMB
);
15547 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15551 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15552 is_bx
= (opcode
->aencode
== do_bx
);
15554 /* Check that this instruction is supported for this CPU. */
15555 if (!(is_bx
&& fix_v4bx
)
15556 && !(opcode
->avariant
&&
15557 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15559 as_bad (_("selected processor does not support `%s'"), str
);
15564 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15568 inst
.instruction
= opcode
->avalue
;
15569 if (opcode
->tag
== OT_unconditionalF
)
15570 inst
.instruction
|= 0xF << 28;
15572 inst
.instruction
|= inst
.cond
<< 28;
15573 inst
.size
= INSN_SIZE
;
15574 if (!parse_operands (p
, opcode
->operands
))
15576 it_fsm_pre_encode ();
15577 opcode
->aencode ();
15578 it_fsm_post_encode ();
15580 /* Arm mode bx is marked as both v4T and v5 because it's still required
15581 on a hypothetical non-thumb v5 core. */
15583 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15585 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15586 *opcode
->avariant
);
15589 mapping_state (MAP_ARM
);
15594 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15602 check_it_blocks_finished (void)
15607 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15608 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15609 == MANUAL_IT_BLOCK
)
15611 as_warn (_("section '%s' finished with an open IT block."),
15615 if (now_it
.state
== MANUAL_IT_BLOCK
)
15616 as_warn (_("file finished with an open IT block."));
15620 /* Various frobbings of labels and their addresses. */
15623 arm_start_line_hook (void)
15625 last_label_seen
= NULL
;
15629 arm_frob_label (symbolS
* sym
)
15631 last_label_seen
= sym
;
15633 ARM_SET_THUMB (sym
, thumb_mode
);
15635 #if defined OBJ_COFF || defined OBJ_ELF
15636 ARM_SET_INTERWORK (sym
, support_interwork
);
15639 force_automatic_it_block_close ();
15641 /* Note - do not allow local symbols (.Lxxx) to be labelled
15642 as Thumb functions. This is because these labels, whilst
15643 they exist inside Thumb code, are not the entry points for
15644 possible ARM->Thumb calls. Also, these labels can be used
15645 as part of a computed goto or switch statement. eg gcc
15646 can generate code that looks like this:
15648 ldr r2, [pc, .Laaa]
15658 The first instruction loads the address of the jump table.
15659 The second instruction converts a table index into a byte offset.
15660 The third instruction gets the jump address out of the table.
15661 The fourth instruction performs the jump.
15663 If the address stored at .Laaa is that of a symbol which has the
15664 Thumb_Func bit set, then the linker will arrange for this address
15665 to have the bottom bit set, which in turn would mean that the
15666 address computation performed by the third instruction would end
15667 up with the bottom bit set. Since the ARM is capable of unaligned
15668 word loads, the instruction would then load the incorrect address
15669 out of the jump table, and chaos would ensue. */
15670 if (label_is_thumb_function_name
15671 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15672 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15674 /* When the address of a Thumb function is taken the bottom
15675 bit of that address should be set. This will allow
15676 interworking between Arm and Thumb functions to work
15679 THUMB_SET_FUNC (sym
, 1);
15681 label_is_thumb_function_name
= FALSE
;
15684 dwarf2_emit_label (sym
);
15688 arm_data_in_code (void)
15690 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15692 *input_line_pointer
= '/';
15693 input_line_pointer
+= 5;
15694 *input_line_pointer
= 0;
15702 arm_canonicalize_symbol_name (char * name
)
15706 if (thumb_mode
&& (len
= strlen (name
)) > 5
15707 && streq (name
+ len
- 5, "/data"))
15708 *(name
+ len
- 5) = 0;
15713 /* Table of all register names defined by default. The user can
15714 define additional names with .req. Note that all register names
15715 should appear in both upper and lowercase variants. Some registers
15716 also have mixed-case names. */
15718 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15719 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15720 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15721 #define REGSET(p,t) \
15722 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15723 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15724 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15725 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15726 #define REGSETH(p,t) \
15727 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15728 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15729 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15730 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15731 #define REGSET2(p,t) \
15732 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15733 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15734 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15735 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15737 static const struct reg_entry reg_names
[] =
15739 /* ARM integer registers. */
15740 REGSET(r
, RN
), REGSET(R
, RN
),
15742 /* ATPCS synonyms. */
15743 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15744 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15745 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15747 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15748 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15749 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15751 /* Well-known aliases. */
15752 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15753 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15755 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15756 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15758 /* Coprocessor numbers. */
15759 REGSET(p
, CP
), REGSET(P
, CP
),
15761 /* Coprocessor register numbers. The "cr" variants are for backward
15763 REGSET(c
, CN
), REGSET(C
, CN
),
15764 REGSET(cr
, CN
), REGSET(CR
, CN
),
15766 /* FPA registers. */
15767 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15768 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15770 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15771 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15773 /* VFP SP registers. */
15774 REGSET(s
,VFS
), REGSET(S
,VFS
),
15775 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15777 /* VFP DP Registers. */
15778 REGSET(d
,VFD
), REGSET(D
,VFD
),
15779 /* Extra Neon DP registers. */
15780 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15782 /* Neon QP registers. */
15783 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15785 /* VFP control registers. */
15786 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15787 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15788 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15789 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15790 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15791 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15793 /* Maverick DSP coprocessor registers. */
15794 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15795 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15797 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15798 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15799 REGDEF(dspsc
,0,DSPSC
),
15801 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15802 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15803 REGDEF(DSPSC
,0,DSPSC
),
15805 /* iWMMXt data registers - p0, c0-15. */
15806 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15808 /* iWMMXt control registers - p1, c0-3. */
15809 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15810 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15811 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15812 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15814 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15815 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15816 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15817 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15818 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15820 /* XScale accumulator registers. */
15821 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15827 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15828 within psr_required_here. */
15829 static const struct asm_psr psrs
[] =
15831 /* Backward compatibility notation. Note that "all" is no longer
15832 truly all possible PSR bits. */
15833 {"all", PSR_c
| PSR_f
},
15837 /* Individual flags. */
15842 /* Combinations of flags. */
15843 {"fs", PSR_f
| PSR_s
},
15844 {"fx", PSR_f
| PSR_x
},
15845 {"fc", PSR_f
| PSR_c
},
15846 {"sf", PSR_s
| PSR_f
},
15847 {"sx", PSR_s
| PSR_x
},
15848 {"sc", PSR_s
| PSR_c
},
15849 {"xf", PSR_x
| PSR_f
},
15850 {"xs", PSR_x
| PSR_s
},
15851 {"xc", PSR_x
| PSR_c
},
15852 {"cf", PSR_c
| PSR_f
},
15853 {"cs", PSR_c
| PSR_s
},
15854 {"cx", PSR_c
| PSR_x
},
15855 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15856 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15857 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15858 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15859 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15860 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15861 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15862 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15863 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15864 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15865 {"scf", PSR_s
| PSR_c
| PSR_f
},
15866 {"scx", PSR_s
| PSR_c
| PSR_x
},
15867 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15868 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15869 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15870 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15871 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15872 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15873 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15874 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15875 {"csf", PSR_c
| PSR_s
| PSR_f
},
15876 {"csx", PSR_c
| PSR_s
| PSR_x
},
15877 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15878 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15879 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15880 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15881 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15882 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15883 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15884 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15885 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15886 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15887 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15888 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15889 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15890 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15891 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15892 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15893 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15894 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15895 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15896 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15897 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15898 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15899 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15900 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15901 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15902 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15905 /* Table of V7M psr names. */
15906 static const struct asm_psr v7m_psrs
[] =
15908 {"apsr", 0 }, {"APSR", 0 },
15909 {"iapsr", 1 }, {"IAPSR", 1 },
15910 {"eapsr", 2 }, {"EAPSR", 2 },
15911 {"psr", 3 }, {"PSR", 3 },
15912 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15913 {"ipsr", 5 }, {"IPSR", 5 },
15914 {"epsr", 6 }, {"EPSR", 6 },
15915 {"iepsr", 7 }, {"IEPSR", 7 },
15916 {"msp", 8 }, {"MSP", 8 },
15917 {"psp", 9 }, {"PSP", 9 },
15918 {"primask", 16}, {"PRIMASK", 16},
15919 {"basepri", 17}, {"BASEPRI", 17},
15920 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15921 {"faultmask", 19}, {"FAULTMASK", 19},
15922 {"control", 20}, {"CONTROL", 20}
15925 /* Table of all shift-in-operand names. */
15926 static const struct asm_shift_name shift_names
[] =
15928 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15929 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15930 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15931 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15932 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15933 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15936 /* Table of all explicit relocation names. */
15938 static struct reloc_entry reloc_names
[] =
15940 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15941 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15942 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15943 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15944 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15945 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15946 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15947 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15948 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15949 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15950 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15954 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15955 static const struct asm_cond conds
[] =
15959 {"cs", 0x2}, {"hs", 0x2},
15960 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15974 static struct asm_barrier_opt barrier_opt_names
[] =
15982 /* Table of ARM-format instructions. */
15984 /* Macros for gluing together operand strings. N.B. In all cases
15985 other than OPS0, the trailing OP_stop comes from default
15986 zero-initialization of the unspecified elements of the array. */
15987 #define OPS0() { OP_stop, }
15988 #define OPS1(a) { OP_##a, }
15989 #define OPS2(a,b) { OP_##a,OP_##b, }
15990 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15991 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15992 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15993 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15995 /* These macros abstract out the exact format of the mnemonic table and
15996 save some repeated characters. */
15998 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15999 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16000 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16001 THUMB_VARIANT, do_##ae, do_##te }
16003 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16004 a T_MNEM_xyz enumerator. */
16005 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16006 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16007 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16008 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16010 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16011 infix after the third character. */
16012 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16013 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16014 THUMB_VARIANT, do_##ae, do_##te }
16015 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16016 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16017 THUMB_VARIANT, do_##ae, do_##te }
16018 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16019 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16020 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16021 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16022 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16023 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16024 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16025 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16027 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16028 appear in the condition table. */
16029 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16030 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16031 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16033 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16034 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16035 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16036 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16037 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16038 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16039 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16040 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16041 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16042 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16043 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16044 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16045 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16046 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16047 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16048 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16049 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16050 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16051 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16052 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16054 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16055 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16056 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16057 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16059 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16060 field is still 0xE. Many of the Thumb variants can be executed
16061 conditionally, so this is checked separately. */
16062 #define TUE(mnem, op, top, nops, ops, ae, te) \
16063 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16064 THUMB_VARIANT, do_##ae, do_##te }
16066 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16067 condition code field. */
16068 #define TUF(mnem, op, top, nops, ops, ae, te) \
16069 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16070 THUMB_VARIANT, do_##ae, do_##te }
16072 /* ARM-only variants of all the above. */
16073 #define CE(mnem, op, nops, ops, ae) \
16074 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16076 #define C3(mnem, op, nops, ops, ae) \
16077 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16079 /* Legacy mnemonics that always have conditional infix after the third
16081 #define CL(mnem, op, nops, ops, ae) \
16082 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16083 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16085 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16086 #define cCE(mnem, op, nops, ops, ae) \
16087 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16089 /* Legacy coprocessor instructions where conditional infix and conditional
16090 suffix are ambiguous. For consistency this includes all FPA instructions,
16091 not just the potentially ambiguous ones. */
16092 #define cCL(mnem, op, nops, ops, ae) \
16093 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16094 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16096 /* Coprocessor, takes either a suffix or a position-3 infix
16097 (for an FPA corner case). */
16098 #define C3E(mnem, op, nops, ops, ae) \
16099 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16100 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16102 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16103 { m1 #m2 m3, OPS##nops ops, \
16104 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16105 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16107 #define CM(m1, m2, op, nops, ops, ae) \
16108 xCM_ (m1, , m2, op, nops, ops, ae), \
16109 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16110 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16111 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16112 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16113 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16114 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16115 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16116 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16117 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16118 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16119 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16120 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16121 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16122 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16123 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16124 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16125 xCM_ (m1, le, m2, op, nops, ops, ae), \
16126 xCM_ (m1, al, m2, op, nops, ops, ae)
16128 #define UE(mnem, op, nops, ops, ae) \
16129 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16131 #define UF(mnem, op, nops, ops, ae) \
16132 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16134 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16135 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16136 use the same encoding function for each. */
16137 #define NUF(mnem, op, nops, ops, enc) \
16138 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16139 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16141 /* Neon data processing, version which indirects through neon_enc_tab for
16142 the various overloaded versions of opcodes. */
16143 #define nUF(mnem, op, nops, ops, enc) \
16144 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16145 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16147 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16149 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16150 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16151 THUMB_VARIANT, do_##enc, do_##enc }
16153 #define NCE(mnem, op, nops, ops, enc) \
16154 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16156 #define NCEF(mnem, op, nops, ops, enc) \
16157 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16159 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16160 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16161 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16162 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16164 #define nCE(mnem, op, nops, ops, enc) \
16165 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16167 #define nCEF(mnem, op, nops, ops, enc) \
16168 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16172 /* Thumb-only, unconditional. */
16173 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16175 static const struct asm_opcode insns
[] =
16177 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16178 #define THUMB_VARIANT &arm_ext_v4t
16179 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16180 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16181 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16182 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16183 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16184 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16185 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16186 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16187 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16188 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16189 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16190 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16191 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16192 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16193 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16194 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16196 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16197 for setting PSR flag bits. They are obsolete in V6 and do not
16198 have Thumb equivalents. */
16199 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16200 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16201 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16202 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16203 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16204 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16205 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16206 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16207 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16209 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16210 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16211 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16212 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16214 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16215 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16216 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16217 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16219 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16220 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16221 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16222 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16223 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16224 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16226 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16227 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16228 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16229 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16232 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16233 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16234 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16236 /* Thumb-compatibility pseudo ops. */
16237 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16238 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16239 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16240 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16241 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16242 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16243 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16244 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16245 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16246 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16247 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16248 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16250 /* These may simplify to neg. */
16251 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16252 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16254 #undef THUMB_VARIANT
16255 #define THUMB_VARIANT & arm_ext_v6
16257 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16259 /* V1 instructions with no Thumb analogue prior to V6T2. */
16260 #undef THUMB_VARIANT
16261 #define THUMB_VARIANT & arm_ext_v6t2
16263 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16264 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16265 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16267 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16268 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16269 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16270 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16272 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16273 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16275 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16276 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16278 /* V1 instructions with no Thumb analogue at all. */
16279 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16280 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16282 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16283 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16284 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16285 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16286 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16287 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16288 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16289 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16292 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16293 #undef THUMB_VARIANT
16294 #define THUMB_VARIANT & arm_ext_v4t
16296 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16297 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16299 #undef THUMB_VARIANT
16300 #define THUMB_VARIANT & arm_ext_v6t2
16302 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16303 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16305 /* Generic coprocessor instructions. */
16306 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16307 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16308 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16309 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16310 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16311 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16312 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16315 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16317 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16318 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16321 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16322 #undef THUMB_VARIANT
16323 #define THUMB_VARIANT & arm_ext_msr
16325 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16326 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16329 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16330 #undef THUMB_VARIANT
16331 #define THUMB_VARIANT & arm_ext_v6t2
16333 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16334 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16335 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16336 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16337 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16338 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16339 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16340 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16343 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16344 #undef THUMB_VARIANT
16345 #define THUMB_VARIANT & arm_ext_v4t
16347 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16348 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16349 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16350 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16351 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16352 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16355 #define ARM_VARIANT & arm_ext_v4t_5
16357 /* ARM Architecture 4T. */
16358 /* Note: bx (and blx) are required on V5, even if the processor does
16359 not support Thumb. */
16360 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16363 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16364 #undef THUMB_VARIANT
16365 #define THUMB_VARIANT & arm_ext_v5t
16367 /* Note: blx has 2 variants; the .value coded here is for
16368 BLX(2). Only this variant has conditional execution. */
16369 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16370 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16372 #undef THUMB_VARIANT
16373 #define THUMB_VARIANT & arm_ext_v6t2
16375 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16376 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16377 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16378 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16379 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16380 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16381 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16382 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16385 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16387 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16388 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16389 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16390 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16392 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16393 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16395 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16396 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16397 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16398 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16400 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16401 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16402 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16403 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16405 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16406 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16408 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16409 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16410 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16411 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16414 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16416 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16417 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16418 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16420 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16421 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16424 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16426 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16429 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16430 #undef THUMB_VARIANT
16431 #define THUMB_VARIANT & arm_ext_v6
16433 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16434 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16435 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16436 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16437 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16438 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16439 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16440 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16441 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16442 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16444 #undef THUMB_VARIANT
16445 #define THUMB_VARIANT & arm_ext_v6t2
16447 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16448 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16449 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16450 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16452 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16453 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16455 /* ARM V6 not included in V7M (eg. integer SIMD). */
16456 #undef THUMB_VARIANT
16457 #define THUMB_VARIANT & arm_ext_v6_notm
16459 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16460 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16461 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16462 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16463 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16464 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16465 /* Old name for QASX. */
16466 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16467 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16468 /* Old name for QSAX. */
16469 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16470 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16471 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16472 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16473 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16474 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16475 /* Old name for SASX. */
16476 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16477 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16478 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16479 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16480 /* Old name for SHASX. */
16481 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16482 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16483 /* Old name for SHSAX. */
16484 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16485 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16486 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16487 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16488 /* Old name for SSAX. */
16489 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16490 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16491 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16492 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16493 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16494 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16495 /* Old name for UASX. */
16496 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16497 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16498 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16499 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16500 /* Old name for UHASX. */
16501 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16502 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16503 /* Old name for UHSAX. */
16504 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16505 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16506 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16507 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16508 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16509 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16510 /* Old name for UQASX. */
16511 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16512 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16513 /* Old name for UQSAX. */
16514 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16515 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16516 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16517 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16518 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16519 /* Old name for USAX. */
16520 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16521 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16522 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16523 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16524 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16525 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16526 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16527 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16528 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16529 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16530 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16531 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16532 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16533 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16534 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16535 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16536 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16537 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16538 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16539 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16540 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16541 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16542 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16543 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16544 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16545 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16546 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16547 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16548 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16549 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16550 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16551 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16552 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16553 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16554 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16555 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16556 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16557 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16558 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16559 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16560 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16561 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16562 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16563 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16564 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16565 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16568 #define ARM_VARIANT & arm_ext_v6k
16569 #undef THUMB_VARIANT
16570 #define THUMB_VARIANT & arm_ext_v6k
16572 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16573 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16574 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16575 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16577 #undef THUMB_VARIANT
16578 #define THUMB_VARIANT & arm_ext_v6_notm
16580 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16581 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16583 #undef THUMB_VARIANT
16584 #define THUMB_VARIANT & arm_ext_v6t2
16586 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16587 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16588 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16589 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16590 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16593 #define ARM_VARIANT & arm_ext_v6z
16595 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16598 #define ARM_VARIANT & arm_ext_v6t2
16600 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16601 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16602 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16603 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16605 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16606 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16607 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16608 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16610 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16611 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16612 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16613 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16615 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16616 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16618 /* ARM does not really have an IT instruction, so always allow it.
16619 The opcode is copied from Thumb in order to allow warnings in
16620 -mimplicit-it=[never | arm] modes. */
16622 #define ARM_VARIANT & arm_ext_v1
16624 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16625 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16626 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16627 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16628 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16629 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16630 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16631 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16632 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16633 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16634 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16635 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16636 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16637 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16638 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16639 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16640 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16641 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16643 /* Thumb2 only instructions. */
16645 #define ARM_VARIANT NULL
16647 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16648 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16649 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16650 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16651 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16652 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16654 /* Thumb-2 hardware division instructions (R and M profiles only). */
16655 #undef THUMB_VARIANT
16656 #define THUMB_VARIANT & arm_ext_div
16658 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16659 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16661 /* ARM V6M/V7 instructions. */
16663 #define ARM_VARIANT & arm_ext_barrier
16664 #undef THUMB_VARIANT
16665 #define THUMB_VARIANT & arm_ext_barrier
16667 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16668 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16669 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16671 /* ARM V7 instructions. */
16673 #define ARM_VARIANT & arm_ext_v7
16674 #undef THUMB_VARIANT
16675 #define THUMB_VARIANT & arm_ext_v7
16677 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16678 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16681 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16683 cCE("wfs", e200110
, 1, (RR
), rd
),
16684 cCE("rfs", e300110
, 1, (RR
), rd
),
16685 cCE("wfc", e400110
, 1, (RR
), rd
),
16686 cCE("rfc", e500110
, 1, (RR
), rd
),
16688 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16689 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16690 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16691 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16693 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16694 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16695 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16696 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16698 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16699 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16700 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16701 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16702 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16703 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16704 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16705 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16706 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16707 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16708 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16709 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16711 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16712 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16713 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16714 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16715 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16716 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16717 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16718 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16719 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16720 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16721 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16722 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16724 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16725 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16726 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16727 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16728 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16729 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16730 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16731 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16732 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16733 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16734 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16735 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16737 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16738 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16739 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16740 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16741 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16742 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16743 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16744 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16745 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16746 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16747 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16748 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16750 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16751 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16752 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16753 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16754 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16755 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16756 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16757 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16758 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16759 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16760 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16761 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16763 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16764 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16765 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16766 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16767 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16768 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16769 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16770 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16771 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16772 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16773 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16774 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16776 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16777 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16778 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16779 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16780 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16781 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16782 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16783 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16784 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16785 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16786 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16787 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16789 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16790 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16791 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16792 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16793 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16794 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16795 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16796 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16797 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16798 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16799 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16800 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16802 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16803 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16804 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16805 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16806 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16807 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16808 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16809 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16810 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16811 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16812 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16813 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16815 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16816 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16817 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16821 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16822 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16828 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16829 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16834 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16835 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16841 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16842 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16847 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16848 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16854 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16855 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16867 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16868 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16880 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16881 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16886 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16887 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16893 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16894 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16899 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16900 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16906 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16907 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16908 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16909 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16910 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16911 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16912 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16913 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16914 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16915 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16916 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16917 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16919 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16920 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16921 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16922 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16923 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16924 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16925 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16926 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16927 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16928 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16929 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16930 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16932 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16933 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16934 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16935 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16936 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16937 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16938 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16939 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16940 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16941 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16942 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16943 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16945 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16946 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16947 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16948 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16949 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16950 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16951 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16952 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16953 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16954 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16955 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16956 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16958 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16959 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16960 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16961 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16962 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16963 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16964 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16965 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16966 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16967 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16968 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16969 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16971 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16972 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16973 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16974 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16975 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16976 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16977 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16978 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16979 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16980 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16981 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16982 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16984 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16985 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16986 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16987 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16988 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16989 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16990 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16991 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16992 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16993 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16994 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16995 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16997 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16998 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16999 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17000 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17001 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17002 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17003 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17004 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17005 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17006 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17007 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17008 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17010 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17011 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17012 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17013 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17014 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17015 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17016 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17017 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17018 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17019 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17020 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17021 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17023 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17024 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17025 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17029 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17030 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17036 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17037 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17042 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17043 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17049 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17050 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17052 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17053 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17054 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17055 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17056 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17057 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17058 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17059 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17060 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17062 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17063 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17068 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17069 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17075 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17076 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17077 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17078 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17080 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17081 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17082 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17083 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17084 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17085 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17086 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17087 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17088 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17089 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17090 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17091 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17093 /* The implementation of the FIX instruction is broken on some
17094 assemblers, in that it accepts a precision specifier as well as a
17095 rounding specifier, despite the fact that this is meaningless.
17096 To be more compatible, we accept it as well, though of course it
17097 does not set any bits. */
17098 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17099 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17100 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17101 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17102 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17103 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17104 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17105 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17106 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17107 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17108 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17109 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17110 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17112 /* Instructions that were new with the real FPA, call them V2. */
17114 #define ARM_VARIANT & fpu_fpa_ext_v2
17116 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17117 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17118 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17119 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17120 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17121 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17124 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17126 /* Moves and type conversions. */
17127 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17128 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17129 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17130 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17131 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17132 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17133 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17134 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17135 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17136 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17137 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17138 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17140 /* Memory operations. */
17141 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17142 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17143 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17144 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17145 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17146 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17147 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17148 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17149 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17150 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17151 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17152 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17153 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17154 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17155 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17156 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17157 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17158 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17160 /* Monadic operations. */
17161 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17162 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17163 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17165 /* Dyadic operations. */
17166 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17167 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17168 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17169 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17170 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17171 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17172 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17173 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17174 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17177 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17178 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17179 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17180 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17183 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17185 /* Moves and type conversions. */
17186 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17187 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17188 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17189 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17190 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17191 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17192 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17193 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17194 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17195 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17196 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17197 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17198 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17200 /* Memory operations. */
17201 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17202 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17203 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17204 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17205 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17206 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17207 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17208 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17209 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17210 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17212 /* Monadic operations. */
17213 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17214 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17215 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17217 /* Dyadic operations. */
17218 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17219 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17220 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17221 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17222 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17223 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17224 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17225 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17226 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17229 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17230 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17231 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17232 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17235 #define ARM_VARIANT & fpu_vfp_ext_v2
17237 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17238 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17239 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17240 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17242 /* Instructions which may belong to either the Neon or VFP instruction sets.
17243 Individual encoder functions perform additional architecture checks. */
17245 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17246 #undef THUMB_VARIANT
17247 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17249 /* These mnemonics are unique to VFP. */
17250 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17251 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17252 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17253 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17254 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17255 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17256 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17257 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17258 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17259 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17261 /* Mnemonics shared by Neon and VFP. */
17262 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17263 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17264 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17266 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17267 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17269 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17270 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17272 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17273 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17274 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17275 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17276 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17277 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17278 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17279 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17281 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17282 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17283 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17286 /* NOTE: All VMOV encoding is special-cased! */
17287 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17288 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17290 #undef THUMB_VARIANT
17291 #define THUMB_VARIANT & fpu_neon_ext_v1
17293 #define ARM_VARIANT & fpu_neon_ext_v1
17295 /* Data processing with three registers of the same length. */
17296 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17297 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17298 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17299 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17300 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17301 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17302 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17303 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17304 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17305 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17306 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17307 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17308 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17309 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17310 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17311 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17312 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17313 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17314 /* If not immediate, fall back to neon_dyadic_i64_su.
17315 shl_imm should accept I8 I16 I32 I64,
17316 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17317 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17318 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17319 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17320 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17321 /* Logic ops, types optional & ignored. */
17322 nUF(vand
, _vand
, 2, (RNDQ
, NILO
), neon_logic
),
17323 nUF(vandq
, _vand
, 2, (RNQ
, NILO
), neon_logic
),
17324 nUF(vbic
, _vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17325 nUF(vbicq
, _vbic
, 2, (RNQ
, NILO
), neon_logic
),
17326 nUF(vorr
, _vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17327 nUF(vorrq
, _vorr
, 2, (RNQ
, NILO
), neon_logic
),
17328 nUF(vorn
, _vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17329 nUF(vornq
, _vorn
, 2, (RNQ
, NILO
), neon_logic
),
17330 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17331 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17332 /* Bitfield ops, untyped. */
17333 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17334 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17335 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17336 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17337 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17338 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17339 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17340 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17341 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17342 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17343 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17344 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17345 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17346 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17347 back to neon_dyadic_if_su. */
17348 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17349 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17350 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17351 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17352 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17353 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17354 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17355 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17356 /* Comparison. Type I8 I16 I32 F32. */
17357 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17358 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17359 /* As above, D registers only. */
17360 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17361 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17362 /* Int and float variants, signedness unimportant. */
17363 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17364 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17365 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17366 /* Add/sub take types I8 I16 I32 I64 F32. */
17367 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17368 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17369 /* vtst takes sizes 8, 16, 32. */
17370 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17371 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17372 /* VMUL takes I8 I16 I32 F32 P8. */
17373 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17374 /* VQD{R}MULH takes S16 S32. */
17375 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17376 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17377 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17378 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17379 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17380 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17381 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17382 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17383 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17384 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17385 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17386 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17387 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17388 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17389 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17390 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17392 /* Two address, int/float. Types S8 S16 S32 F32. */
17393 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17394 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17396 /* Data processing with two registers and a shift amount. */
17397 /* Right shifts, and variants with rounding.
17398 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17399 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17400 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17401 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17402 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17403 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17404 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17405 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17406 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17407 /* Shift and insert. Sizes accepted 8 16 32 64. */
17408 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17409 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17410 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17411 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17412 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17413 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17414 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17415 /* Right shift immediate, saturating & narrowing, with rounding variants.
17416 Types accepted S16 S32 S64 U16 U32 U64. */
17417 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17418 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17419 /* As above, unsigned. Types accepted S16 S32 S64. */
17420 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17421 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17422 /* Right shift narrowing. Types accepted I16 I32 I64. */
17423 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17424 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17425 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17426 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17427 /* CVT with optional immediate for fixed-point variant. */
17428 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17430 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17431 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17433 /* Data processing, three registers of different lengths. */
17434 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17435 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17436 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17437 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17438 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17439 /* If not scalar, fall back to neon_dyadic_long.
17440 Vector types as above, scalar types S16 S32 U16 U32. */
17441 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17442 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17443 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17444 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17445 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17446 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17447 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17448 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17449 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17450 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17451 /* Saturating doubling multiplies. Types S16 S32. */
17452 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17453 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17454 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17455 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17456 S16 S32 U16 U32. */
17457 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17459 /* Extract. Size 8. */
17460 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17461 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17463 /* Two registers, miscellaneous. */
17464 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17465 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17466 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17467 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17468 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17469 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17470 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17471 /* Vector replicate. Sizes 8 16 32. */
17472 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17473 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17474 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17475 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17476 /* VMOVN. Types I16 I32 I64. */
17477 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17478 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17479 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17480 /* VQMOVUN. Types S16 S32 S64. */
17481 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17482 /* VZIP / VUZP. Sizes 8 16 32. */
17483 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17484 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17485 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17486 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17487 /* VQABS / VQNEG. Types S8 S16 S32. */
17488 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17489 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17490 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17491 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17492 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17493 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17494 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17495 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17496 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17497 /* Reciprocal estimates. Types U32 F32. */
17498 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17499 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17500 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17501 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17502 /* VCLS. Types S8 S16 S32. */
17503 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17504 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17505 /* VCLZ. Types I8 I16 I32. */
17506 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17507 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17508 /* VCNT. Size 8. */
17509 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17510 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17511 /* Two address, untyped. */
17512 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17513 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17514 /* VTRN. Sizes 8 16 32. */
17515 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17516 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17518 /* Table lookup. Size 8. */
17519 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17520 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17522 #undef THUMB_VARIANT
17523 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17525 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17527 /* Neon element/structure load/store. */
17528 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17529 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17530 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17531 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17532 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17533 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17534 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17535 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17537 #undef THUMB_VARIANT
17538 #define THUMB_VARIANT & fpu_vfp_ext_v3
17540 #define ARM_VARIANT & fpu_vfp_ext_v3
17542 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17543 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17544 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17545 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17546 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17547 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17548 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17549 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17550 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17551 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17552 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17553 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17554 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17555 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17556 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17557 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17558 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17559 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17561 #undef THUMB_VARIANT
17563 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17565 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17566 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17567 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17568 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17569 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17570 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17571 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17572 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17575 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17577 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17578 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17579 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17580 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17581 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17582 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17583 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17584 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17585 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17586 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17587 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17588 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17589 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17590 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17591 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17592 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17593 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17594 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17595 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17596 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17597 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17598 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17599 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17600 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17601 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17602 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17603 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17604 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17605 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17606 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17607 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17608 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17609 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17610 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17611 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17612 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17613 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17614 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17615 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17616 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17617 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17618 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17619 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17620 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17621 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17622 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17623 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17624 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17625 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17626 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17627 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17628 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17629 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17630 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17631 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17632 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17633 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17634 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17635 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17636 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17637 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17638 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17639 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17640 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17641 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17642 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17643 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17644 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17645 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17646 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17647 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17648 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17649 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17650 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17651 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17652 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17653 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17654 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17655 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17656 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17657 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17658 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17659 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17660 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17661 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17662 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17663 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17664 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17665 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17666 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17667 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17668 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17669 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17670 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17671 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17672 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17673 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17674 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17675 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17676 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17677 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17678 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17679 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17680 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17681 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17682 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17683 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17684 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17685 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17686 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17687 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17688 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17689 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17690 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17691 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17692 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17693 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17694 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17695 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17696 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17697 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17698 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17699 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17700 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17701 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17702 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17703 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17704 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17705 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17706 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17707 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17708 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17709 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17710 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17711 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17712 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17713 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17714 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17715 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17716 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17717 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17718 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17719 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17720 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17721 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17722 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17723 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17724 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17725 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17726 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17727 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17728 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17729 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17730 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17731 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17732 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17733 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17734 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17735 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17736 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17737 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17738 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17741 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17743 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17744 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17745 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17746 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17747 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17748 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17749 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17750 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17751 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17752 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17753 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17754 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17755 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17756 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17757 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17758 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17759 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17760 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17761 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17762 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17763 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17764 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17765 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17766 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17767 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17768 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17769 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17770 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17771 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17772 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17773 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17774 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17776 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17777 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17779 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17780 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17781 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17782 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17783 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17784 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17785 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17786 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17787 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17788 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17789 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17790 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17791 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17792 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17793 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17794 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17795 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17796 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17797 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17798 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17799 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17802 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17804 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17805 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17806 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17807 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17808 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17809 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17810 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17811 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17812 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17813 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17814 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17815 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
17816 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
17817 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
17818 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
17819 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
17820 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
17821 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
17822 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17823 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17824 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17825 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17826 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17827 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17828 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17829 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17830 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17831 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17832 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17833 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
17834 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
17835 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
17836 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
17837 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
17838 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
17839 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17840 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17841 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17842 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
17843 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17844 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17845 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17846 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17847 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17848 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17849 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17850 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17851 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17852 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17853 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17854 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
17855 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
17856 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
17857 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
17858 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17859 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17860 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17861 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17862 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17863 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17864 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17865 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17866 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17867 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17868 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17869 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17870 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17871 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17872 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17873 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17874 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17875 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17876 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17877 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17878 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17879 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17882 #undef THUMB_VARIANT
17909 /* MD interface: bits in the object file. */
17911 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17912 for use in the a.out file, and stores them in the array pointed to by buf.
17913 This knows about the endian-ness of the target machine and does
17914 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17915 2 (short) and 4 (long) Floating numbers are put out as a series of
17916 LITTLENUMS (shorts, here at least). */
17919 md_number_to_chars (char * buf
, valueT val
, int n
)
17921 if (target_big_endian
)
17922 number_to_chars_bigendian (buf
, val
, n
);
17924 number_to_chars_littleendian (buf
, val
, n
);
17928 md_chars_to_number (char * buf
, int n
)
17931 unsigned char * where
= (unsigned char *) buf
;
17933 if (target_big_endian
)
17938 result
|= (*where
++ & 255);
17946 result
|= (where
[n
] & 255);
17953 /* MD interface: Sections. */
17955 /* Estimate the size of a frag before relaxing. Assume everything fits in
17959 md_estimate_size_before_relax (fragS
* fragp
,
17960 segT segtype ATTRIBUTE_UNUSED
)
17966 /* Convert a machine dependent frag. */
17969 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17971 unsigned long insn
;
17972 unsigned long old_op
;
17980 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17982 old_op
= bfd_get_16(abfd
, buf
);
17983 if (fragp
->fr_symbol
)
17985 exp
.X_op
= O_symbol
;
17986 exp
.X_add_symbol
= fragp
->fr_symbol
;
17990 exp
.X_op
= O_constant
;
17992 exp
.X_add_number
= fragp
->fr_offset
;
17993 opcode
= fragp
->fr_subtype
;
17996 case T_MNEM_ldr_pc
:
17997 case T_MNEM_ldr_pc2
:
17998 case T_MNEM_ldr_sp
:
17999 case T_MNEM_str_sp
:
18006 if (fragp
->fr_var
== 4)
18008 insn
= THUMB_OP32 (opcode
);
18009 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18011 insn
|= (old_op
& 0x700) << 4;
18015 insn
|= (old_op
& 7) << 12;
18016 insn
|= (old_op
& 0x38) << 13;
18018 insn
|= 0x00000c00;
18019 put_thumb32_insn (buf
, insn
);
18020 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18024 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18026 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18029 if (fragp
->fr_var
== 4)
18031 insn
= THUMB_OP32 (opcode
);
18032 insn
|= (old_op
& 0xf0) << 4;
18033 put_thumb32_insn (buf
, insn
);
18034 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18038 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18039 exp
.X_add_number
-= 4;
18047 if (fragp
->fr_var
== 4)
18049 int r0off
= (opcode
== T_MNEM_mov
18050 || opcode
== T_MNEM_movs
) ? 0 : 8;
18051 insn
= THUMB_OP32 (opcode
);
18052 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18053 insn
|= (old_op
& 0x700) << r0off
;
18054 put_thumb32_insn (buf
, insn
);
18055 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18059 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18064 if (fragp
->fr_var
== 4)
18066 insn
= THUMB_OP32(opcode
);
18067 put_thumb32_insn (buf
, insn
);
18068 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18071 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18075 if (fragp
->fr_var
== 4)
18077 insn
= THUMB_OP32(opcode
);
18078 insn
|= (old_op
& 0xf00) << 14;
18079 put_thumb32_insn (buf
, insn
);
18080 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18083 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18086 case T_MNEM_add_sp
:
18087 case T_MNEM_add_pc
:
18088 case T_MNEM_inc_sp
:
18089 case T_MNEM_dec_sp
:
18090 if (fragp
->fr_var
== 4)
18092 /* ??? Choose between add and addw. */
18093 insn
= THUMB_OP32 (opcode
);
18094 insn
|= (old_op
& 0xf0) << 4;
18095 put_thumb32_insn (buf
, insn
);
18096 if (opcode
== T_MNEM_add_pc
)
18097 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18099 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18102 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18110 if (fragp
->fr_var
== 4)
18112 insn
= THUMB_OP32 (opcode
);
18113 insn
|= (old_op
& 0xf0) << 4;
18114 insn
|= (old_op
& 0xf) << 16;
18115 put_thumb32_insn (buf
, insn
);
18116 if (insn
& (1 << 20))
18117 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18119 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18122 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18128 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18129 (enum bfd_reloc_code_real
) reloc_type
);
18130 fixp
->fx_file
= fragp
->fr_file
;
18131 fixp
->fx_line
= fragp
->fr_line
;
18132 fragp
->fr_fix
+= fragp
->fr_var
;
18135 /* Return the size of a relaxable immediate operand instruction.
18136 SHIFT and SIZE specify the form of the allowable immediate. */
18138 relax_immediate (fragS
*fragp
, int size
, int shift
)
18144 /* ??? Should be able to do better than this. */
18145 if (fragp
->fr_symbol
)
18148 low
= (1 << shift
) - 1;
18149 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18150 offset
= fragp
->fr_offset
;
18151 /* Force misaligned offsets to 32-bit variant. */
18154 if (offset
& ~mask
)
18159 /* Get the address of a symbol during relaxation. */
18161 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18167 sym
= fragp
->fr_symbol
;
18168 sym_frag
= symbol_get_frag (sym
);
18169 know (S_GET_SEGMENT (sym
) != absolute_section
18170 || sym_frag
== &zero_address_frag
);
18171 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18173 /* If frag has yet to be reached on this pass, assume it will
18174 move by STRETCH just as we did. If this is not so, it will
18175 be because some frag between grows, and that will force
18179 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18183 /* Adjust stretch for any alignment frag. Note that if have
18184 been expanding the earlier code, the symbol may be
18185 defined in what appears to be an earlier frag. FIXME:
18186 This doesn't handle the fr_subtype field, which specifies
18187 a maximum number of bytes to skip when doing an
18189 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18191 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18194 stretch
= - ((- stretch
)
18195 & ~ ((1 << (int) f
->fr_offset
) - 1));
18197 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18209 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18212 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18217 /* Assume worst case for symbols not known to be in the same section. */
18218 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18219 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18222 val
= relaxed_symbol_addr (fragp
, stretch
);
18223 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18224 addr
= (addr
+ 4) & ~3;
18225 /* Force misaligned targets to 32-bit variant. */
18229 if (val
< 0 || val
> 1020)
18234 /* Return the size of a relaxable add/sub immediate instruction. */
18236 relax_addsub (fragS
*fragp
, asection
*sec
)
18241 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18242 op
= bfd_get_16(sec
->owner
, buf
);
18243 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18244 return relax_immediate (fragp
, 8, 0);
18246 return relax_immediate (fragp
, 3, 0);
18250 /* Return the size of a relaxable branch instruction. BITS is the
18251 size of the offset field in the narrow instruction. */
18254 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18260 /* Assume worst case for symbols not known to be in the same section. */
18261 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18262 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18266 if (S_IS_DEFINED (fragp
->fr_symbol
)
18267 && ARM_IS_FUNC (fragp
->fr_symbol
))
18271 val
= relaxed_symbol_addr (fragp
, stretch
);
18272 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18275 /* Offset is a signed value *2 */
18277 if (val
>= limit
|| val
< -limit
)
18283 /* Relax a machine dependent frag. This returns the amount by which
18284 the current size of the frag should change. */
18287 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18292 oldsize
= fragp
->fr_var
;
18293 switch (fragp
->fr_subtype
)
18295 case T_MNEM_ldr_pc2
:
18296 newsize
= relax_adr (fragp
, sec
, stretch
);
18298 case T_MNEM_ldr_pc
:
18299 case T_MNEM_ldr_sp
:
18300 case T_MNEM_str_sp
:
18301 newsize
= relax_immediate (fragp
, 8, 2);
18305 newsize
= relax_immediate (fragp
, 5, 2);
18309 newsize
= relax_immediate (fragp
, 5, 1);
18313 newsize
= relax_immediate (fragp
, 5, 0);
18316 newsize
= relax_adr (fragp
, sec
, stretch
);
18322 newsize
= relax_immediate (fragp
, 8, 0);
18325 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18328 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18330 case T_MNEM_add_sp
:
18331 case T_MNEM_add_pc
:
18332 newsize
= relax_immediate (fragp
, 8, 2);
18334 case T_MNEM_inc_sp
:
18335 case T_MNEM_dec_sp
:
18336 newsize
= relax_immediate (fragp
, 7, 2);
18342 newsize
= relax_addsub (fragp
, sec
);
18348 fragp
->fr_var
= newsize
;
18349 /* Freeze wide instructions that are at or before the same location as
18350 in the previous pass. This avoids infinite loops.
18351 Don't freeze them unconditionally because targets may be artificially
18352 misaligned by the expansion of preceding frags. */
18353 if (stretch
<= 0 && newsize
> 2)
18355 md_convert_frag (sec
->owner
, sec
, fragp
);
18359 return newsize
- oldsize
;
18362 /* Round up a section size to the appropriate boundary. */
18365 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18368 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18369 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18371 /* For a.out, force the section size to be aligned. If we don't do
18372 this, BFD will align it for us, but it will not write out the
18373 final bytes of the section. This may be a bug in BFD, but it is
18374 easier to fix it here since that is how the other a.out targets
18378 align
= bfd_get_section_alignment (stdoutput
, segment
);
18379 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18386 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18387 of an rs_align_code fragment. */
18390 arm_handle_align (fragS
* fragP
)
18392 static char const arm_noop
[2][2][4] =
18395 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18396 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18399 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18400 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18403 static char const thumb_noop
[2][2][2] =
18406 {0xc0, 0x46}, /* LE */
18407 {0x46, 0xc0}, /* BE */
18410 {0x00, 0xbf}, /* LE */
18411 {0xbf, 0x00} /* BE */
18414 static char const wide_thumb_noop
[2][4] =
18415 { /* Wide Thumb-2 */
18416 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18417 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18420 unsigned bytes
, fix
, noop_size
;
18423 const char *narrow_noop
= NULL
;
18428 if (fragP
->fr_type
!= rs_align_code
)
18431 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18432 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18435 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18436 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18439 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18442 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18444 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18446 narrow_noop
= thumb_noop
[1][target_big_endian
];
18447 noop
= wide_thumb_noop
[target_big_endian
];
18450 noop
= thumb_noop
[0][target_big_endian
];
18458 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18459 [target_big_endian
];
18466 fragP
->fr_var
= noop_size
;
18468 if (bytes
& (noop_size
- 1))
18470 fix
= bytes
& (noop_size
- 1);
18472 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18474 memset (p
, 0, fix
);
18481 if (bytes
& noop_size
)
18483 /* Insert a narrow noop. */
18484 memcpy (p
, narrow_noop
, noop_size
);
18486 bytes
-= noop_size
;
18490 /* Use wide noops for the remainder */
18494 while (bytes
>= noop_size
)
18496 memcpy (p
, noop
, noop_size
);
18498 bytes
-= noop_size
;
18502 fragP
->fr_fix
+= fix
;
18505 /* Called from md_do_align. Used to create an alignment
18506 frag in a code section. */
18509 arm_frag_align_code (int n
, int max
)
18513 /* We assume that there will never be a requirement
18514 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18515 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18520 _("alignments greater than %d bytes not supported in .text sections."),
18521 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18522 as_fatal ("%s", err_msg
);
18525 p
= frag_var (rs_align_code
,
18526 MAX_MEM_FOR_RS_ALIGN_CODE
,
18528 (relax_substateT
) max
,
18535 /* Perform target specific initialisation of a frag.
18536 Note - despite the name this initialisation is not done when the frag
18537 is created, but only when its type is assigned. A frag can be created
18538 and used a long time before its type is set, so beware of assuming that
18539 this initialisationis performed first. */
18543 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18545 /* Record whether this frag is in an ARM or a THUMB area. */
18546 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
;
18549 #else /* OBJ_ELF is defined. */
18551 arm_init_frag (fragS
* fragP
, int max_chars
)
18553 /* If the current ARM vs THUMB mode has not already
18554 been recorded into this frag then do so now. */
18555 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18557 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18559 /* Record a mapping symbol for alignment frags. We will delete this
18560 later if the alignment ends up empty. */
18561 switch (fragP
->fr_type
)
18564 case rs_align_test
:
18566 mapping_state_2 (MAP_DATA
, max_chars
);
18568 case rs_align_code
:
18569 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18577 /* When we change sections we need to issue a new mapping symbol. */
18580 arm_elf_change_section (void)
18582 /* Link an unlinked unwind index table section to the .text section. */
18583 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18584 && elf_linked_to_section (now_seg
) == NULL
)
18585 elf_linked_to_section (now_seg
) = text_section
;
18589 arm_elf_section_type (const char * str
, size_t len
)
18591 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18592 return SHT_ARM_EXIDX
;
18597 /* Code to deal with unwinding tables. */
18599 static void add_unwind_adjustsp (offsetT
);
18601 /* Generate any deferred unwind frame offset. */
18604 flush_pending_unwind (void)
18608 offset
= unwind
.pending_offset
;
18609 unwind
.pending_offset
= 0;
18611 add_unwind_adjustsp (offset
);
18614 /* Add an opcode to this list for this function. Two-byte opcodes should
18615 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18619 add_unwind_opcode (valueT op
, int length
)
18621 /* Add any deferred stack adjustment. */
18622 if (unwind
.pending_offset
)
18623 flush_pending_unwind ();
18625 unwind
.sp_restored
= 0;
18627 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18629 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18630 if (unwind
.opcodes
)
18631 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18632 unwind
.opcode_alloc
);
18634 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18639 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18641 unwind
.opcode_count
++;
18645 /* Add unwind opcodes to adjust the stack pointer. */
18648 add_unwind_adjustsp (offsetT offset
)
18652 if (offset
> 0x200)
18654 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18659 /* Long form: 0xb2, uleb128. */
18660 /* This might not fit in a word so add the individual bytes,
18661 remembering the list is built in reverse order. */
18662 o
= (valueT
) ((offset
- 0x204) >> 2);
18664 add_unwind_opcode (0, 1);
18666 /* Calculate the uleb128 encoding of the offset. */
18670 bytes
[n
] = o
& 0x7f;
18676 /* Add the insn. */
18678 add_unwind_opcode (bytes
[n
- 1], 1);
18679 add_unwind_opcode (0xb2, 1);
18681 else if (offset
> 0x100)
18683 /* Two short opcodes. */
18684 add_unwind_opcode (0x3f, 1);
18685 op
= (offset
- 0x104) >> 2;
18686 add_unwind_opcode (op
, 1);
18688 else if (offset
> 0)
18690 /* Short opcode. */
18691 op
= (offset
- 4) >> 2;
18692 add_unwind_opcode (op
, 1);
18694 else if (offset
< 0)
18697 while (offset
> 0x100)
18699 add_unwind_opcode (0x7f, 1);
18702 op
= ((offset
- 4) >> 2) | 0x40;
18703 add_unwind_opcode (op
, 1);
18707 /* Finish the list of unwind opcodes for this function. */
18709 finish_unwind_opcodes (void)
18713 if (unwind
.fp_used
)
18715 /* Adjust sp as necessary. */
18716 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18717 flush_pending_unwind ();
18719 /* After restoring sp from the frame pointer. */
18720 op
= 0x90 | unwind
.fp_reg
;
18721 add_unwind_opcode (op
, 1);
18724 flush_pending_unwind ();
18728 /* Start an exception table entry. If idx is nonzero this is an index table
18732 start_unwind_section (const segT text_seg
, int idx
)
18734 const char * text_name
;
18735 const char * prefix
;
18736 const char * prefix_once
;
18737 const char * group_name
;
18741 size_t sec_name_len
;
18748 prefix
= ELF_STRING_ARM_unwind
;
18749 prefix_once
= ELF_STRING_ARM_unwind_once
;
18750 type
= SHT_ARM_EXIDX
;
18754 prefix
= ELF_STRING_ARM_unwind_info
;
18755 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18756 type
= SHT_PROGBITS
;
18759 text_name
= segment_name (text_seg
);
18760 if (streq (text_name
, ".text"))
18763 if (strncmp (text_name
, ".gnu.linkonce.t.",
18764 strlen (".gnu.linkonce.t.")) == 0)
18766 prefix
= prefix_once
;
18767 text_name
+= strlen (".gnu.linkonce.t.");
18770 prefix_len
= strlen (prefix
);
18771 text_len
= strlen (text_name
);
18772 sec_name_len
= prefix_len
+ text_len
;
18773 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18774 memcpy (sec_name
, prefix
, prefix_len
);
18775 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18776 sec_name
[prefix_len
+ text_len
] = '\0';
18782 /* Handle COMDAT group. */
18783 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18785 group_name
= elf_group_name (text_seg
);
18786 if (group_name
== NULL
)
18788 as_bad (_("Group section `%s' has no group signature"),
18789 segment_name (text_seg
));
18790 ignore_rest_of_line ();
18793 flags
|= SHF_GROUP
;
18797 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18799 /* Set the section link for index tables. */
18801 elf_linked_to_section (now_seg
) = text_seg
;
18805 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18806 personality routine data. Returns zero, or the index table value for
18807 and inline entry. */
18810 create_unwind_entry (int have_data
)
18815 /* The current word of data. */
18817 /* The number of bytes left in this word. */
18820 finish_unwind_opcodes ();
18822 /* Remember the current text section. */
18823 unwind
.saved_seg
= now_seg
;
18824 unwind
.saved_subseg
= now_subseg
;
18826 start_unwind_section (now_seg
, 0);
18828 if (unwind
.personality_routine
== NULL
)
18830 if (unwind
.personality_index
== -2)
18833 as_bad (_("handlerdata in cantunwind frame"));
18834 return 1; /* EXIDX_CANTUNWIND. */
18837 /* Use a default personality routine if none is specified. */
18838 if (unwind
.personality_index
== -1)
18840 if (unwind
.opcode_count
> 3)
18841 unwind
.personality_index
= 1;
18843 unwind
.personality_index
= 0;
18846 /* Space for the personality routine entry. */
18847 if (unwind
.personality_index
== 0)
18849 if (unwind
.opcode_count
> 3)
18850 as_bad (_("too many unwind opcodes for personality routine 0"));
18854 /* All the data is inline in the index table. */
18857 while (unwind
.opcode_count
> 0)
18859 unwind
.opcode_count
--;
18860 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18864 /* Pad with "finish" opcodes. */
18866 data
= (data
<< 8) | 0xb0;
18873 /* We get two opcodes "free" in the first word. */
18874 size
= unwind
.opcode_count
- 2;
18877 /* An extra byte is required for the opcode count. */
18878 size
= unwind
.opcode_count
+ 1;
18880 size
= (size
+ 3) >> 2;
18882 as_bad (_("too many unwind opcodes"));
18884 frag_align (2, 0, 0);
18885 record_alignment (now_seg
, 2);
18886 unwind
.table_entry
= expr_build_dot ();
18888 /* Allocate the table entry. */
18889 ptr
= frag_more ((size
<< 2) + 4);
18890 where
= frag_now_fix () - ((size
<< 2) + 4);
18892 switch (unwind
.personality_index
)
18895 /* ??? Should this be a PLT generating relocation? */
18896 /* Custom personality routine. */
18897 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18898 BFD_RELOC_ARM_PREL31
);
18903 /* Set the first byte to the number of additional words. */
18908 /* ABI defined personality routines. */
18910 /* Three opcodes bytes are packed into the first word. */
18917 /* The size and first two opcode bytes go in the first word. */
18918 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18923 /* Should never happen. */
18927 /* Pack the opcodes into words (MSB first), reversing the list at the same
18929 while (unwind
.opcode_count
> 0)
18933 md_number_to_chars (ptr
, data
, 4);
18938 unwind
.opcode_count
--;
18940 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18943 /* Finish off the last word. */
18946 /* Pad with "finish" opcodes. */
18948 data
= (data
<< 8) | 0xb0;
18950 md_number_to_chars (ptr
, data
, 4);
18955 /* Add an empty descriptor if there is no user-specified data. */
18956 ptr
= frag_more (4);
18957 md_number_to_chars (ptr
, 0, 4);
18964 /* Initialize the DWARF-2 unwind information for this procedure. */
18967 tc_arm_frame_initial_instructions (void)
18969 cfi_add_CFA_def_cfa (REG_SP
, 0);
18971 #endif /* OBJ_ELF */
18973 /* Convert REGNAME to a DWARF-2 register number. */
18976 tc_arm_regname_to_dw2regnum (char *regname
)
18978 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18988 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18992 expr
.X_op
= O_secrel
;
18993 expr
.X_add_symbol
= symbol
;
18994 expr
.X_add_number
= 0;
18995 emit_expr (&expr
, size
);
18999 /* MD interface: Symbol and relocation handling. */
19001 /* Return the address within the segment that a PC-relative fixup is
19002 relative to. For ARM, PC-relative fixups applied to instructions
19003 are generally relative to the location of the fixup plus 8 bytes.
19004 Thumb branches are offset by 4, and Thumb loads relative to PC
19005 require special handling. */
19008 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19010 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19012 /* If this is pc-relative and we are going to emit a relocation
19013 then we just want to put out any pipeline compensation that the linker
19014 will need. Otherwise we want to use the calculated base.
19015 For WinCE we skip the bias for externals as well, since this
19016 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19018 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19019 || (arm_force_relocation (fixP
)
19021 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19027 switch (fixP
->fx_r_type
)
19029 /* PC relative addressing on the Thumb is slightly odd as the
19030 bottom two bits of the PC are forced to zero for the
19031 calculation. This happens *after* application of the
19032 pipeline offset. However, Thumb adrl already adjusts for
19033 this, so we need not do it again. */
19034 case BFD_RELOC_ARM_THUMB_ADD
:
19037 case BFD_RELOC_ARM_THUMB_OFFSET
:
19038 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19039 case BFD_RELOC_ARM_T32_ADD_PC12
:
19040 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19041 return (base
+ 4) & ~3;
19043 /* Thumb branches are simply offset by +4. */
19044 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19045 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19046 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19047 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19048 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19051 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19053 && ARM_IS_FUNC (fixP
->fx_addsy
)
19054 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19055 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19058 /* BLX is like branches above, but forces the low two bits of PC to
19060 case BFD_RELOC_THUMB_PCREL_BLX
:
19062 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19063 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19064 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19065 return (base
+ 4) & ~3;
19067 /* ARM mode branches are offset by +8. However, the Windows CE
19068 loader expects the relocation not to take this into account. */
19069 case BFD_RELOC_ARM_PCREL_BLX
:
19071 && ARM_IS_FUNC (fixP
->fx_addsy
)
19072 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19073 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19076 case BFD_RELOC_ARM_PCREL_CALL
:
19078 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19079 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19080 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19083 case BFD_RELOC_ARM_PCREL_BRANCH
:
19084 case BFD_RELOC_ARM_PCREL_JUMP
:
19085 case BFD_RELOC_ARM_PLT32
:
19087 /* When handling fixups immediately, because we have already
19088 discovered the value of a symbol, or the address of the frag involved
19089 we must account for the offset by +8, as the OS loader will never see the reloc.
19090 see fixup_segment() in write.c
19091 The S_IS_EXTERNAL test handles the case of global symbols.
19092 Those need the calculated base, not just the pipe compensation the linker will need. */
19094 && fixP
->fx_addsy
!= NULL
19095 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19096 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19104 /* ARM mode loads relative to PC are also offset by +8. Unlike
19105 branches, the Windows CE loader *does* expect the relocation
19106 to take this into account. */
19107 case BFD_RELOC_ARM_OFFSET_IMM
:
19108 case BFD_RELOC_ARM_OFFSET_IMM8
:
19109 case BFD_RELOC_ARM_HWLITERAL
:
19110 case BFD_RELOC_ARM_LITERAL
:
19111 case BFD_RELOC_ARM_CP_OFF_IMM
:
19115 /* Other PC-relative relocations are un-offset. */
19121 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19122 Otherwise we have no need to default values of symbols. */
19125 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19128 if (name
[0] == '_' && name
[1] == 'G'
19129 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19133 if (symbol_find (name
))
19134 as_bad (_("GOT already in the symbol table"));
19136 GOT_symbol
= symbol_new (name
, undefined_section
,
19137 (valueT
) 0, & zero_address_frag
);
19147 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19148 computed as two separate immediate values, added together. We
19149 already know that this value cannot be computed by just one ARM
19152 static unsigned int
19153 validate_immediate_twopart (unsigned int val
,
19154 unsigned int * highpart
)
19159 for (i
= 0; i
< 32; i
+= 2)
19160 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19166 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19168 else if (a
& 0xff0000)
19170 if (a
& 0xff000000)
19172 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19176 gas_assert (a
& 0xff000000);
19177 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19180 return (a
& 0xff) | (i
<< 7);
19187 validate_offset_imm (unsigned int val
, int hwse
)
19189 if ((hwse
&& val
> 255) || val
> 4095)
19194 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19195 negative immediate constant by altering the instruction. A bit of
19200 by inverting the second operand, and
19203 by negating the second operand. */
19206 negate_data_op (unsigned long * instruction
,
19207 unsigned long value
)
19210 unsigned long negated
, inverted
;
19212 negated
= encode_arm_immediate (-value
);
19213 inverted
= encode_arm_immediate (~value
);
19215 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19218 /* First negates. */
19219 case OPCODE_SUB
: /* ADD <-> SUB */
19220 new_inst
= OPCODE_ADD
;
19225 new_inst
= OPCODE_SUB
;
19229 case OPCODE_CMP
: /* CMP <-> CMN */
19230 new_inst
= OPCODE_CMN
;
19235 new_inst
= OPCODE_CMP
;
19239 /* Now Inverted ops. */
19240 case OPCODE_MOV
: /* MOV <-> MVN */
19241 new_inst
= OPCODE_MVN
;
19246 new_inst
= OPCODE_MOV
;
19250 case OPCODE_AND
: /* AND <-> BIC */
19251 new_inst
= OPCODE_BIC
;
19256 new_inst
= OPCODE_AND
;
19260 case OPCODE_ADC
: /* ADC <-> SBC */
19261 new_inst
= OPCODE_SBC
;
19266 new_inst
= OPCODE_ADC
;
19270 /* We cannot do anything. */
19275 if (value
== (unsigned) FAIL
)
19278 *instruction
&= OPCODE_MASK
;
19279 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19283 /* Like negate_data_op, but for Thumb-2. */
19285 static unsigned int
19286 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19290 unsigned int negated
, inverted
;
19292 negated
= encode_thumb32_immediate (-value
);
19293 inverted
= encode_thumb32_immediate (~value
);
19295 rd
= (*instruction
>> 8) & 0xf;
19296 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19299 /* ADD <-> SUB. Includes CMP <-> CMN. */
19300 case T2_OPCODE_SUB
:
19301 new_inst
= T2_OPCODE_ADD
;
19305 case T2_OPCODE_ADD
:
19306 new_inst
= T2_OPCODE_SUB
;
19310 /* ORR <-> ORN. Includes MOV <-> MVN. */
19311 case T2_OPCODE_ORR
:
19312 new_inst
= T2_OPCODE_ORN
;
19316 case T2_OPCODE_ORN
:
19317 new_inst
= T2_OPCODE_ORR
;
19321 /* AND <-> BIC. TST has no inverted equivalent. */
19322 case T2_OPCODE_AND
:
19323 new_inst
= T2_OPCODE_BIC
;
19330 case T2_OPCODE_BIC
:
19331 new_inst
= T2_OPCODE_AND
;
19336 case T2_OPCODE_ADC
:
19337 new_inst
= T2_OPCODE_SBC
;
19341 case T2_OPCODE_SBC
:
19342 new_inst
= T2_OPCODE_ADC
;
19346 /* We cannot do anything. */
19351 if (value
== (unsigned int)FAIL
)
19354 *instruction
&= T2_OPCODE_MASK
;
19355 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19359 /* Read a 32-bit thumb instruction from buf. */
19360 static unsigned long
19361 get_thumb32_insn (char * buf
)
19363 unsigned long insn
;
19364 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19365 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19371 /* We usually want to set the low bit on the address of thumb function
19372 symbols. In particular .word foo - . should have the low bit set.
19373 Generic code tries to fold the difference of two symbols to
19374 a constant. Prevent this and force a relocation when the first symbols
19375 is a thumb function. */
19378 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19380 if (op
== O_subtract
19381 && l
->X_op
== O_symbol
19382 && r
->X_op
== O_symbol
19383 && THUMB_IS_FUNC (l
->X_add_symbol
))
19385 l
->X_op
= O_subtract
;
19386 l
->X_op_symbol
= r
->X_add_symbol
;
19387 l
->X_add_number
-= r
->X_add_number
;
19391 /* Process as normal. */
19396 md_apply_fix (fixS
* fixP
,
19400 offsetT value
= * valP
;
19402 unsigned int newimm
;
19403 unsigned long temp
;
19405 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19407 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19409 /* Note whether this will delete the relocation. */
19411 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19414 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19415 consistency with the behaviour on 32-bit hosts. Remember value
19417 value
&= 0xffffffff;
19418 value
^= 0x80000000;
19419 value
-= 0x80000000;
19422 fixP
->fx_addnumber
= value
;
19424 /* Same treatment for fixP->fx_offset. */
19425 fixP
->fx_offset
&= 0xffffffff;
19426 fixP
->fx_offset
^= 0x80000000;
19427 fixP
->fx_offset
-= 0x80000000;
19429 switch (fixP
->fx_r_type
)
19431 case BFD_RELOC_NONE
:
19432 /* This will need to go in the object file. */
19436 case BFD_RELOC_ARM_IMMEDIATE
:
19437 /* We claim that this fixup has been processed here,
19438 even if in fact we generate an error because we do
19439 not have a reloc for it, so tc_gen_reloc will reject it. */
19443 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19446 _("undefined symbol %s used as an immediate value"),
19447 S_GET_NAME (fixP
->fx_addsy
));
19452 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19455 _("symbol %s is in a different section"),
19456 S_GET_NAME (fixP
->fx_addsy
));
19460 newimm
= encode_arm_immediate (value
);
19461 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19463 /* If the instruction will fail, see if we can fix things up by
19464 changing the opcode. */
19465 if (newimm
== (unsigned int) FAIL
19466 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19469 _("invalid constant (%lx) after fixup"),
19470 (unsigned long) value
);
19474 newimm
|= (temp
& 0xfffff000);
19475 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19478 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19480 unsigned int highpart
= 0;
19481 unsigned int newinsn
= 0xe1a00000; /* nop. */
19484 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19487 _("undefined symbol %s used as an immediate value"),
19488 S_GET_NAME (fixP
->fx_addsy
));
19493 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19496 _("symbol %s is in a different section"),
19497 S_GET_NAME (fixP
->fx_addsy
));
19501 newimm
= encode_arm_immediate (value
);
19502 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19504 /* If the instruction will fail, see if we can fix things up by
19505 changing the opcode. */
19506 if (newimm
== (unsigned int) FAIL
19507 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19509 /* No ? OK - try using two ADD instructions to generate
19511 newimm
= validate_immediate_twopart (value
, & highpart
);
19513 /* Yes - then make sure that the second instruction is
19515 if (newimm
!= (unsigned int) FAIL
)
19517 /* Still No ? Try using a negated value. */
19518 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19519 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19520 /* Otherwise - give up. */
19523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19524 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19529 /* Replace the first operand in the 2nd instruction (which
19530 is the PC) with the destination register. We have
19531 already added in the PC in the first instruction and we
19532 do not want to do it again. */
19533 newinsn
&= ~ 0xf0000;
19534 newinsn
|= ((newinsn
& 0x0f000) << 4);
19537 newimm
|= (temp
& 0xfffff000);
19538 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19540 highpart
|= (newinsn
& 0xfffff000);
19541 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19545 case BFD_RELOC_ARM_OFFSET_IMM
:
19546 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19549 case BFD_RELOC_ARM_LITERAL
:
19555 if (validate_offset_imm (value
, 0) == FAIL
)
19557 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19559 _("invalid literal constant: pool needs to be closer"));
19561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19562 _("bad immediate value for offset (%ld)"),
19567 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19568 newval
&= 0xff7ff000;
19569 newval
|= value
| (sign
? INDEX_UP
: 0);
19570 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19573 case BFD_RELOC_ARM_OFFSET_IMM8
:
19574 case BFD_RELOC_ARM_HWLITERAL
:
19580 if (validate_offset_imm (value
, 1) == FAIL
)
19582 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19583 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19584 _("invalid literal constant: pool needs to be closer"));
19586 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19591 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19592 newval
&= 0xff7ff0f0;
19593 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19594 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19597 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19598 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19600 _("bad immediate value for offset (%ld)"), (long) value
);
19603 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19605 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19608 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19609 /* This is a complicated relocation used for all varieties of Thumb32
19610 load/store instruction with immediate offset:
19612 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19613 *4, optional writeback(W)
19614 (doubleword load/store)
19616 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19617 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19618 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19619 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19620 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19622 Uppercase letters indicate bits that are already encoded at
19623 this point. Lowercase letters are our problem. For the
19624 second block of instructions, the secondary opcode nybble
19625 (bits 8..11) is present, and bit 23 is zero, even if this is
19626 a PC-relative operation. */
19627 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19629 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19631 if ((newval
& 0xf0000000) == 0xe0000000)
19633 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19635 newval
|= (1 << 23);
19638 if (value
% 4 != 0)
19640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19641 _("offset not a multiple of 4"));
19647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19648 _("offset out of range"));
19653 else if ((newval
& 0x000f0000) == 0x000f0000)
19655 /* PC-relative, 12-bit offset. */
19657 newval
|= (1 << 23);
19662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19663 _("offset out of range"));
19668 else if ((newval
& 0x00000100) == 0x00000100)
19670 /* Writeback: 8-bit, +/- offset. */
19672 newval
|= (1 << 9);
19677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19678 _("offset out of range"));
19683 else if ((newval
& 0x00000f00) == 0x00000e00)
19685 /* T-instruction: positive 8-bit offset. */
19686 if (value
< 0 || value
> 0xff)
19688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19689 _("offset out of range"));
19697 /* Positive 12-bit or negative 8-bit offset. */
19701 newval
|= (1 << 23);
19711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19712 _("offset out of range"));
19719 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19720 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19723 case BFD_RELOC_ARM_SHIFT_IMM
:
19724 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19725 if (((unsigned long) value
) > 32
19727 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19730 _("shift expression is too large"));
19735 /* Shifts of zero must be done as lsl. */
19737 else if (value
== 32)
19739 newval
&= 0xfffff07f;
19740 newval
|= (value
& 0x1f) << 7;
19741 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19744 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19745 case BFD_RELOC_ARM_T32_ADD_IMM
:
19746 case BFD_RELOC_ARM_T32_IMM12
:
19747 case BFD_RELOC_ARM_T32_ADD_PC12
:
19748 /* We claim that this fixup has been processed here,
19749 even if in fact we generate an error because we do
19750 not have a reloc for it, so tc_gen_reloc will reject it. */
19754 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19757 _("undefined symbol %s used as an immediate value"),
19758 S_GET_NAME (fixP
->fx_addsy
));
19762 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19764 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19767 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19768 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19770 newimm
= encode_thumb32_immediate (value
);
19771 if (newimm
== (unsigned int) FAIL
)
19772 newimm
= thumb32_negate_data_op (&newval
, value
);
19774 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19775 && newimm
== (unsigned int) FAIL
)
19777 /* Turn add/sum into addw/subw. */
19778 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19779 newval
= (newval
& 0xfeffffff) | 0x02000000;
19781 /* 12 bit immediate for addw/subw. */
19785 newval
^= 0x00a00000;
19788 newimm
= (unsigned int) FAIL
;
19793 if (newimm
== (unsigned int)FAIL
)
19795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19796 _("invalid constant (%lx) after fixup"),
19797 (unsigned long) value
);
19801 newval
|= (newimm
& 0x800) << 15;
19802 newval
|= (newimm
& 0x700) << 4;
19803 newval
|= (newimm
& 0x0ff);
19805 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19806 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19809 case BFD_RELOC_ARM_SMC
:
19810 if (((unsigned long) value
) > 0xffff)
19811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19812 _("invalid smc expression"));
19813 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19814 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19815 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19818 case BFD_RELOC_ARM_SWI
:
19819 if (fixP
->tc_fix_data
!= 0)
19821 if (((unsigned long) value
) > 0xff)
19822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19823 _("invalid swi expression"));
19824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19826 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19830 if (((unsigned long) value
) > 0x00ffffff)
19831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19832 _("invalid swi expression"));
19833 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19835 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19839 case BFD_RELOC_ARM_MULTI
:
19840 if (((unsigned long) value
) > 0xffff)
19841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19842 _("invalid expression in load/store multiple"));
19843 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19844 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19848 case BFD_RELOC_ARM_PCREL_CALL
:
19850 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19852 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19853 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19854 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19855 /* Flip the bl to blx. This is a simple flip
19856 bit here because we generate PCREL_CALL for
19857 unconditional bls. */
19859 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19860 newval
= newval
| 0x10000000;
19861 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19867 goto arm_branch_common
;
19869 case BFD_RELOC_ARM_PCREL_JUMP
:
19870 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19872 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19873 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19874 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19876 /* This would map to a bl<cond>, b<cond>,
19877 b<always> to a Thumb function. We
19878 need to force a relocation for this particular
19880 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19884 case BFD_RELOC_ARM_PLT32
:
19886 case BFD_RELOC_ARM_PCREL_BRANCH
:
19888 goto arm_branch_common
;
19890 case BFD_RELOC_ARM_PCREL_BLX
:
19893 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19895 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19896 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19897 && ARM_IS_FUNC (fixP
->fx_addsy
))
19899 /* Flip the blx to a bl and warn. */
19900 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19901 newval
= 0xeb000000;
19902 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19903 _("blx to '%s' an ARM ISA state function changed to bl"),
19905 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19911 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19912 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
19916 /* We are going to store value (shifted right by two) in the
19917 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19918 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19919 also be be clear. */
19921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19922 _("misaligned branch destination"));
19923 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19924 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19926 _("branch out of range"));
19928 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19930 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19931 newval
|= (value
>> 2) & 0x00ffffff;
19932 /* Set the H bit on BLX instructions. */
19936 newval
|= 0x01000000;
19938 newval
&= ~0x01000000;
19940 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19944 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
19945 /* CBZ can only branch forward. */
19947 /* Attempts to use CBZ to branch to the next instruction
19948 (which, strictly speaking, are prohibited) will be turned into
19951 FIXME: It may be better to remove the instruction completely and
19952 perform relaxation. */
19955 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19956 newval
= 0xbf00; /* NOP encoding T1 */
19957 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19963 _("branch out of range"));
19965 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19967 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19968 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19969 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19974 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19975 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19977 _("branch out of range"));
19979 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19981 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19982 newval
|= (value
& 0x1ff) >> 1;
19983 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19987 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19988 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19990 _("branch out of range"));
19992 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19995 newval
|= (value
& 0xfff) >> 1;
19996 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20000 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20002 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20003 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20004 && S_IS_DEFINED (fixP
->fx_addsy
)
20005 && ARM_IS_FUNC (fixP
->fx_addsy
)
20006 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20008 /* Force a relocation for a branch 20 bits wide. */
20011 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20013 _("conditional branch out of range"));
20015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20018 addressT S
, J1
, J2
, lo
, hi
;
20020 S
= (value
& 0x00100000) >> 20;
20021 J2
= (value
& 0x00080000) >> 19;
20022 J1
= (value
& 0x00040000) >> 18;
20023 hi
= (value
& 0x0003f000) >> 12;
20024 lo
= (value
& 0x00000ffe) >> 1;
20026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20027 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20028 newval
|= (S
<< 10) | hi
;
20029 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20030 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20031 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20035 case BFD_RELOC_THUMB_PCREL_BLX
:
20037 /* If there is a blx from a thumb state function to
20038 another thumb function flip this to a bl and warn
20042 && S_IS_DEFINED (fixP
->fx_addsy
)
20043 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20044 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20045 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20047 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20048 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20049 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20051 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20052 newval
= newval
| 0x1000;
20053 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20054 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20059 goto thumb_bl_common
;
20061 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20063 /* A bl from Thumb state ISA to an internal ARM state function
20064 is converted to a blx. */
20066 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20067 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20068 && S_IS_DEFINED (fixP
->fx_addsy
)
20069 && ARM_IS_FUNC (fixP
->fx_addsy
)
20070 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20072 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20073 newval
= newval
& ~0x1000;
20074 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20075 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20082 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20083 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20084 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20087 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20089 _("branch out of range"));
20091 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20092 /* For a BLX instruction, make sure that the relocation is rounded up
20093 to a word boundary. This follows the semantics of the instruction
20094 which specifies that bit 1 of the target address will come from bit
20095 1 of the base address. */
20096 value
= (value
+ 1) & ~ 1;
20098 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20102 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20103 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20104 newval
|= (value
& 0x7fffff) >> 12;
20105 newval2
|= (value
& 0xfff) >> 1;
20106 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20107 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20111 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20112 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20114 _("branch out of range"));
20116 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20119 addressT S
, I1
, I2
, lo
, hi
;
20121 S
= (value
& 0x01000000) >> 24;
20122 I1
= (value
& 0x00800000) >> 23;
20123 I2
= (value
& 0x00400000) >> 22;
20124 hi
= (value
& 0x003ff000) >> 12;
20125 lo
= (value
& 0x00000ffe) >> 1;
20130 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20131 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20132 newval
|= (S
<< 10) | hi
;
20133 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
20134 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20135 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20140 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20141 md_number_to_chars (buf
, value
, 1);
20145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20146 md_number_to_chars (buf
, value
, 2);
20150 case BFD_RELOC_ARM_TLS_GD32
:
20151 case BFD_RELOC_ARM_TLS_LE32
:
20152 case BFD_RELOC_ARM_TLS_IE32
:
20153 case BFD_RELOC_ARM_TLS_LDM32
:
20154 case BFD_RELOC_ARM_TLS_LDO32
:
20155 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20158 case BFD_RELOC_ARM_GOT32
:
20159 case BFD_RELOC_ARM_GOTOFF
:
20160 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20161 md_number_to_chars (buf
, 0, 4);
20164 case BFD_RELOC_ARM_TARGET2
:
20165 /* TARGET2 is not partial-inplace, so we need to write the
20166 addend here for REL targets, because it won't be written out
20167 during reloc processing later. */
20168 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20169 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20173 case BFD_RELOC_RVA
:
20175 case BFD_RELOC_ARM_TARGET1
:
20176 case BFD_RELOC_ARM_ROSEGREL32
:
20177 case BFD_RELOC_ARM_SBREL32
:
20178 case BFD_RELOC_32_PCREL
:
20180 case BFD_RELOC_32_SECREL
:
20182 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20184 /* For WinCE we only do this for pcrel fixups. */
20185 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20187 md_number_to_chars (buf
, value
, 4);
20191 case BFD_RELOC_ARM_PREL31
:
20192 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20194 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20195 if ((value
^ (value
>> 1)) & 0x40000000)
20197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20198 _("rel31 relocation overflow"));
20200 newval
|= value
& 0x7fffffff;
20201 md_number_to_chars (buf
, newval
, 4);
20206 case BFD_RELOC_ARM_CP_OFF_IMM
:
20207 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20208 if (value
< -1023 || value
> 1023 || (value
& 3))
20209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20210 _("co-processor offset out of range"));
20215 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20216 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20217 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20219 newval
= get_thumb32_insn (buf
);
20220 newval
&= 0xff7fff00;
20221 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20222 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20223 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20224 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20226 put_thumb32_insn (buf
, newval
);
20229 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20230 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20231 if (value
< -255 || value
> 255)
20232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20233 _("co-processor offset out of range"));
20235 goto cp_off_common
;
20237 case BFD_RELOC_ARM_THUMB_OFFSET
:
20238 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20239 /* Exactly what ranges, and where the offset is inserted depends
20240 on the type of instruction, we can establish this from the
20242 switch (newval
>> 12)
20244 case 4: /* PC load. */
20245 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20246 forced to zero for these loads; md_pcrel_from has already
20247 compensated for this. */
20249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20250 _("invalid offset, target not word aligned (0x%08lX)"),
20251 (((unsigned long) fixP
->fx_frag
->fr_address
20252 + (unsigned long) fixP
->fx_where
) & ~3)
20253 + (unsigned long) value
);
20255 if (value
& ~0x3fc)
20256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20257 _("invalid offset, value too big (0x%08lX)"),
20260 newval
|= value
>> 2;
20263 case 9: /* SP load/store. */
20264 if (value
& ~0x3fc)
20265 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20266 _("invalid offset, value too big (0x%08lX)"),
20268 newval
|= value
>> 2;
20271 case 6: /* Word load/store. */
20273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20274 _("invalid offset, value too big (0x%08lX)"),
20276 newval
|= value
<< 4; /* 6 - 2. */
20279 case 7: /* Byte load/store. */
20281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20282 _("invalid offset, value too big (0x%08lX)"),
20284 newval
|= value
<< 6;
20287 case 8: /* Halfword load/store. */
20289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20290 _("invalid offset, value too big (0x%08lX)"),
20292 newval
|= value
<< 5; /* 6 - 1. */
20296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20297 "Unable to process relocation for thumb opcode: %lx",
20298 (unsigned long) newval
);
20301 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20304 case BFD_RELOC_ARM_THUMB_ADD
:
20305 /* This is a complicated relocation, since we use it for all of
20306 the following immediate relocations:
20310 9bit ADD/SUB SP word-aligned
20311 10bit ADD PC/SP word-aligned
20313 The type of instruction being processed is encoded in the
20320 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20322 int rd
= (newval
>> 4) & 0xf;
20323 int rs
= newval
& 0xf;
20324 int subtract
= !!(newval
& 0x8000);
20326 /* Check for HI regs, only very restricted cases allowed:
20327 Adjusting SP, and using PC or SP to get an address. */
20328 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20329 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20331 _("invalid Hi register with immediate"));
20333 /* If value is negative, choose the opposite instruction. */
20337 subtract
= !subtract
;
20339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20340 _("immediate value out of range"));
20345 if (value
& ~0x1fc)
20346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20347 _("invalid immediate for stack address calculation"));
20348 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20349 newval
|= value
>> 2;
20351 else if (rs
== REG_PC
|| rs
== REG_SP
)
20353 if (subtract
|| value
& ~0x3fc)
20354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20355 _("invalid immediate for address calculation (value = 0x%08lX)"),
20356 (unsigned long) value
);
20357 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20359 newval
|= value
>> 2;
20364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20365 _("immediate value out of range"));
20366 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20367 newval
|= (rd
<< 8) | value
;
20372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20373 _("immediate value out of range"));
20374 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20375 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20378 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20381 case BFD_RELOC_ARM_THUMB_IMM
:
20382 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20383 if (value
< 0 || value
> 255)
20384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20385 _("invalid immediate: %ld is out of range"),
20388 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20391 case BFD_RELOC_ARM_THUMB_SHIFT
:
20392 /* 5bit shift value (0..32). LSL cannot take 32. */
20393 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20394 temp
= newval
& 0xf800;
20395 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20397 _("invalid shift value: %ld"), (long) value
);
20398 /* Shifts of zero must be encoded as LSL. */
20400 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20401 /* Shifts of 32 are encoded as zero. */
20402 else if (value
== 32)
20404 newval
|= value
<< 6;
20405 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20408 case BFD_RELOC_VTABLE_INHERIT
:
20409 case BFD_RELOC_VTABLE_ENTRY
:
20413 case BFD_RELOC_ARM_MOVW
:
20414 case BFD_RELOC_ARM_MOVT
:
20415 case BFD_RELOC_ARM_THUMB_MOVW
:
20416 case BFD_RELOC_ARM_THUMB_MOVT
:
20417 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20419 /* REL format relocations are limited to a 16-bit addend. */
20420 if (!fixP
->fx_done
)
20422 if (value
< -0x8000 || value
> 0x7fff)
20423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20424 _("offset out of range"));
20426 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20427 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20432 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20433 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20435 newval
= get_thumb32_insn (buf
);
20436 newval
&= 0xfbf08f00;
20437 newval
|= (value
& 0xf000) << 4;
20438 newval
|= (value
& 0x0800) << 15;
20439 newval
|= (value
& 0x0700) << 4;
20440 newval
|= (value
& 0x00ff);
20441 put_thumb32_insn (buf
, newval
);
20445 newval
= md_chars_to_number (buf
, 4);
20446 newval
&= 0xfff0f000;
20447 newval
|= value
& 0x0fff;
20448 newval
|= (value
& 0xf000) << 4;
20449 md_number_to_chars (buf
, newval
, 4);
20454 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20455 case BFD_RELOC_ARM_ALU_PC_G0
:
20456 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20457 case BFD_RELOC_ARM_ALU_PC_G1
:
20458 case BFD_RELOC_ARM_ALU_PC_G2
:
20459 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20460 case BFD_RELOC_ARM_ALU_SB_G0
:
20461 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20462 case BFD_RELOC_ARM_ALU_SB_G1
:
20463 case BFD_RELOC_ARM_ALU_SB_G2
:
20464 gas_assert (!fixP
->fx_done
);
20465 if (!seg
->use_rela_p
)
20468 bfd_vma encoded_addend
;
20469 bfd_vma addend_abs
= abs (value
);
20471 /* Check that the absolute value of the addend can be
20472 expressed as an 8-bit constant plus a rotation. */
20473 encoded_addend
= encode_arm_immediate (addend_abs
);
20474 if (encoded_addend
== (unsigned int) FAIL
)
20475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20476 _("the offset 0x%08lX is not representable"),
20477 (unsigned long) addend_abs
);
20479 /* Extract the instruction. */
20480 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20482 /* If the addend is positive, use an ADD instruction.
20483 Otherwise use a SUB. Take care not to destroy the S bit. */
20484 insn
&= 0xff1fffff;
20490 /* Place the encoded addend into the first 12 bits of the
20492 insn
&= 0xfffff000;
20493 insn
|= encoded_addend
;
20495 /* Update the instruction. */
20496 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20500 case BFD_RELOC_ARM_LDR_PC_G0
:
20501 case BFD_RELOC_ARM_LDR_PC_G1
:
20502 case BFD_RELOC_ARM_LDR_PC_G2
:
20503 case BFD_RELOC_ARM_LDR_SB_G0
:
20504 case BFD_RELOC_ARM_LDR_SB_G1
:
20505 case BFD_RELOC_ARM_LDR_SB_G2
:
20506 gas_assert (!fixP
->fx_done
);
20507 if (!seg
->use_rela_p
)
20510 bfd_vma addend_abs
= abs (value
);
20512 /* Check that the absolute value of the addend can be
20513 encoded in 12 bits. */
20514 if (addend_abs
>= 0x1000)
20515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20516 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20517 (unsigned long) addend_abs
);
20519 /* Extract the instruction. */
20520 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20522 /* If the addend is negative, clear bit 23 of the instruction.
20523 Otherwise set it. */
20525 insn
&= ~(1 << 23);
20529 /* Place the absolute value of the addend into the first 12 bits
20530 of the instruction. */
20531 insn
&= 0xfffff000;
20532 insn
|= addend_abs
;
20534 /* Update the instruction. */
20535 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20539 case BFD_RELOC_ARM_LDRS_PC_G0
:
20540 case BFD_RELOC_ARM_LDRS_PC_G1
:
20541 case BFD_RELOC_ARM_LDRS_PC_G2
:
20542 case BFD_RELOC_ARM_LDRS_SB_G0
:
20543 case BFD_RELOC_ARM_LDRS_SB_G1
:
20544 case BFD_RELOC_ARM_LDRS_SB_G2
:
20545 gas_assert (!fixP
->fx_done
);
20546 if (!seg
->use_rela_p
)
20549 bfd_vma addend_abs
= abs (value
);
20551 /* Check that the absolute value of the addend can be
20552 encoded in 8 bits. */
20553 if (addend_abs
>= 0x100)
20554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20555 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20556 (unsigned long) addend_abs
);
20558 /* Extract the instruction. */
20559 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20561 /* If the addend is negative, clear bit 23 of the instruction.
20562 Otherwise set it. */
20564 insn
&= ~(1 << 23);
20568 /* Place the first four bits of the absolute value of the addend
20569 into the first 4 bits of the instruction, and the remaining
20570 four into bits 8 .. 11. */
20571 insn
&= 0xfffff0f0;
20572 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20574 /* Update the instruction. */
20575 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20579 case BFD_RELOC_ARM_LDC_PC_G0
:
20580 case BFD_RELOC_ARM_LDC_PC_G1
:
20581 case BFD_RELOC_ARM_LDC_PC_G2
:
20582 case BFD_RELOC_ARM_LDC_SB_G0
:
20583 case BFD_RELOC_ARM_LDC_SB_G1
:
20584 case BFD_RELOC_ARM_LDC_SB_G2
:
20585 gas_assert (!fixP
->fx_done
);
20586 if (!seg
->use_rela_p
)
20589 bfd_vma addend_abs
= abs (value
);
20591 /* Check that the absolute value of the addend is a multiple of
20592 four and, when divided by four, fits in 8 bits. */
20593 if (addend_abs
& 0x3)
20594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20595 _("bad offset 0x%08lX (must be word-aligned)"),
20596 (unsigned long) addend_abs
);
20598 if ((addend_abs
>> 2) > 0xff)
20599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20600 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20601 (unsigned long) addend_abs
);
20603 /* Extract the instruction. */
20604 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20606 /* If the addend is negative, clear bit 23 of the instruction.
20607 Otherwise set it. */
20609 insn
&= ~(1 << 23);
20613 /* Place the addend (divided by four) into the first eight
20614 bits of the instruction. */
20615 insn
&= 0xfffffff0;
20616 insn
|= addend_abs
>> 2;
20618 /* Update the instruction. */
20619 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20623 case BFD_RELOC_ARM_V4BX
:
20624 /* This will need to go in the object file. */
20628 case BFD_RELOC_UNUSED
:
20630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20631 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20635 /* Translate internal representation of relocation info to BFD target
20639 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20642 bfd_reloc_code_real_type code
;
20644 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20646 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20647 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20648 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20650 if (fixp
->fx_pcrel
)
20652 if (section
->use_rela_p
)
20653 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20655 fixp
->fx_offset
= reloc
->address
;
20657 reloc
->addend
= fixp
->fx_offset
;
20659 switch (fixp
->fx_r_type
)
20662 if (fixp
->fx_pcrel
)
20664 code
= BFD_RELOC_8_PCREL
;
20669 if (fixp
->fx_pcrel
)
20671 code
= BFD_RELOC_16_PCREL
;
20676 if (fixp
->fx_pcrel
)
20678 code
= BFD_RELOC_32_PCREL
;
20682 case BFD_RELOC_ARM_MOVW
:
20683 if (fixp
->fx_pcrel
)
20685 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20689 case BFD_RELOC_ARM_MOVT
:
20690 if (fixp
->fx_pcrel
)
20692 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20696 case BFD_RELOC_ARM_THUMB_MOVW
:
20697 if (fixp
->fx_pcrel
)
20699 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20703 case BFD_RELOC_ARM_THUMB_MOVT
:
20704 if (fixp
->fx_pcrel
)
20706 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20710 case BFD_RELOC_NONE
:
20711 case BFD_RELOC_ARM_PCREL_BRANCH
:
20712 case BFD_RELOC_ARM_PCREL_BLX
:
20713 case BFD_RELOC_RVA
:
20714 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20715 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20716 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20717 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20718 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20719 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20720 case BFD_RELOC_VTABLE_ENTRY
:
20721 case BFD_RELOC_VTABLE_INHERIT
:
20723 case BFD_RELOC_32_SECREL
:
20725 code
= fixp
->fx_r_type
;
20728 case BFD_RELOC_THUMB_PCREL_BLX
:
20730 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20731 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20734 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20737 case BFD_RELOC_ARM_LITERAL
:
20738 case BFD_RELOC_ARM_HWLITERAL
:
20739 /* If this is called then the a literal has
20740 been referenced across a section boundary. */
20741 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20742 _("literal referenced across section boundary"));
20746 case BFD_RELOC_ARM_GOT32
:
20747 case BFD_RELOC_ARM_GOTOFF
:
20748 case BFD_RELOC_ARM_PLT32
:
20749 case BFD_RELOC_ARM_TARGET1
:
20750 case BFD_RELOC_ARM_ROSEGREL32
:
20751 case BFD_RELOC_ARM_SBREL32
:
20752 case BFD_RELOC_ARM_PREL31
:
20753 case BFD_RELOC_ARM_TARGET2
:
20754 case BFD_RELOC_ARM_TLS_LE32
:
20755 case BFD_RELOC_ARM_TLS_LDO32
:
20756 case BFD_RELOC_ARM_PCREL_CALL
:
20757 case BFD_RELOC_ARM_PCREL_JUMP
:
20758 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20759 case BFD_RELOC_ARM_ALU_PC_G0
:
20760 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20761 case BFD_RELOC_ARM_ALU_PC_G1
:
20762 case BFD_RELOC_ARM_ALU_PC_G2
:
20763 case BFD_RELOC_ARM_LDR_PC_G0
:
20764 case BFD_RELOC_ARM_LDR_PC_G1
:
20765 case BFD_RELOC_ARM_LDR_PC_G2
:
20766 case BFD_RELOC_ARM_LDRS_PC_G0
:
20767 case BFD_RELOC_ARM_LDRS_PC_G1
:
20768 case BFD_RELOC_ARM_LDRS_PC_G2
:
20769 case BFD_RELOC_ARM_LDC_PC_G0
:
20770 case BFD_RELOC_ARM_LDC_PC_G1
:
20771 case BFD_RELOC_ARM_LDC_PC_G2
:
20772 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20773 case BFD_RELOC_ARM_ALU_SB_G0
:
20774 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20775 case BFD_RELOC_ARM_ALU_SB_G1
:
20776 case BFD_RELOC_ARM_ALU_SB_G2
:
20777 case BFD_RELOC_ARM_LDR_SB_G0
:
20778 case BFD_RELOC_ARM_LDR_SB_G1
:
20779 case BFD_RELOC_ARM_LDR_SB_G2
:
20780 case BFD_RELOC_ARM_LDRS_SB_G0
:
20781 case BFD_RELOC_ARM_LDRS_SB_G1
:
20782 case BFD_RELOC_ARM_LDRS_SB_G2
:
20783 case BFD_RELOC_ARM_LDC_SB_G0
:
20784 case BFD_RELOC_ARM_LDC_SB_G1
:
20785 case BFD_RELOC_ARM_LDC_SB_G2
:
20786 case BFD_RELOC_ARM_V4BX
:
20787 code
= fixp
->fx_r_type
;
20790 case BFD_RELOC_ARM_TLS_GD32
:
20791 case BFD_RELOC_ARM_TLS_IE32
:
20792 case BFD_RELOC_ARM_TLS_LDM32
:
20793 /* BFD will include the symbol's address in the addend.
20794 But we don't want that, so subtract it out again here. */
20795 if (!S_IS_COMMON (fixp
->fx_addsy
))
20796 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20797 code
= fixp
->fx_r_type
;
20801 case BFD_RELOC_ARM_IMMEDIATE
:
20802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20803 _("internal relocation (type: IMMEDIATE) not fixed up"));
20806 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20807 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20808 _("ADRL used for a symbol not defined in the same file"));
20811 case BFD_RELOC_ARM_OFFSET_IMM
:
20812 if (section
->use_rela_p
)
20814 code
= fixp
->fx_r_type
;
20818 if (fixp
->fx_addsy
!= NULL
20819 && !S_IS_DEFINED (fixp
->fx_addsy
)
20820 && S_IS_LOCAL (fixp
->fx_addsy
))
20822 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20823 _("undefined local label `%s'"),
20824 S_GET_NAME (fixp
->fx_addsy
));
20828 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20829 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20836 switch (fixp
->fx_r_type
)
20838 case BFD_RELOC_NONE
: type
= "NONE"; break;
20839 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20840 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20841 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20842 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20843 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20844 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20845 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20846 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20847 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20848 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20849 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20850 default: type
= _("<unknown>"); break;
20852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20853 _("cannot represent %s relocation in this object file format"),
20860 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20862 && fixp
->fx_addsy
== GOT_symbol
)
20864 code
= BFD_RELOC_ARM_GOTPC
;
20865 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20869 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20871 if (reloc
->howto
== NULL
)
20873 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20874 _("cannot represent %s relocation in this object file format"),
20875 bfd_get_reloc_code_name (code
));
20879 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20880 vtable entry to be used in the relocation's section offset. */
20881 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20882 reloc
->address
= fixp
->fx_offset
;
20887 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
20890 cons_fix_new_arm (fragS
* frag
,
20895 bfd_reloc_code_real_type type
;
20899 FIXME: @@ Should look at CPU word size. */
20903 type
= BFD_RELOC_8
;
20906 type
= BFD_RELOC_16
;
20910 type
= BFD_RELOC_32
;
20913 type
= BFD_RELOC_64
;
20918 if (exp
->X_op
== O_secrel
)
20920 exp
->X_op
= O_symbol
;
20921 type
= BFD_RELOC_32_SECREL
;
20925 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
20928 #if defined (OBJ_COFF)
20930 arm_validate_fix (fixS
* fixP
)
20932 /* If the destination of the branch is a defined symbol which does not have
20933 the THUMB_FUNC attribute, then we must be calling a function which has
20934 the (interfacearm) attribute. We look for the Thumb entry point to that
20935 function and change the branch to refer to that function instead. */
20936 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
20937 && fixP
->fx_addsy
!= NULL
20938 && S_IS_DEFINED (fixP
->fx_addsy
)
20939 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
20941 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
20948 arm_force_relocation (struct fix
* fixp
)
20950 #if defined (OBJ_COFF) && defined (TE_PE)
20951 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
20955 /* In case we have a call or a branch to a function in ARM ISA mode from
20956 a thumb function or vice-versa force the relocation. These relocations
20957 are cleared off for some cores that might have blx and simple transformations
20961 switch (fixp
->fx_r_type
)
20963 case BFD_RELOC_ARM_PCREL_JUMP
:
20964 case BFD_RELOC_ARM_PCREL_CALL
:
20965 case BFD_RELOC_THUMB_PCREL_BLX
:
20966 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
20970 case BFD_RELOC_ARM_PCREL_BLX
:
20971 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20972 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20973 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20974 if (ARM_IS_FUNC (fixp
->fx_addsy
))
20983 /* Resolve these relocations even if the symbol is extern or weak. */
20984 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
20985 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
20986 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
20987 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
20988 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20989 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
20990 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
20993 /* Always leave these relocations for the linker. */
20994 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20995 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20996 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20999 /* Always generate relocations against function symbols. */
21000 if (fixp
->fx_r_type
== BFD_RELOC_32
21002 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21005 return generic_force_reloc (fixp
);
21008 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21009 /* Relocations against function names must be left unadjusted,
21010 so that the linker can use this information to generate interworking
21011 stubs. The MIPS version of this function
21012 also prevents relocations that are mips-16 specific, but I do not
21013 know why it does this.
21016 There is one other problem that ought to be addressed here, but
21017 which currently is not: Taking the address of a label (rather
21018 than a function) and then later jumping to that address. Such
21019 addresses also ought to have their bottom bit set (assuming that
21020 they reside in Thumb code), but at the moment they will not. */
21023 arm_fix_adjustable (fixS
* fixP
)
21025 if (fixP
->fx_addsy
== NULL
)
21028 /* Preserve relocations against symbols with function type. */
21029 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21032 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21033 && fixP
->fx_subsy
== NULL
)
21036 /* We need the symbol name for the VTABLE entries. */
21037 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21038 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21041 /* Don't allow symbols to be discarded on GOT related relocs. */
21042 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21043 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21044 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21045 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21046 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21047 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21048 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21049 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21050 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21053 /* Similarly for group relocations. */
21054 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21055 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21056 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21059 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21060 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21061 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21062 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21063 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21064 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21065 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21066 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21067 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21072 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21077 elf32_arm_target_format (void)
21080 return (target_big_endian
21081 ? "elf32-bigarm-symbian"
21082 : "elf32-littlearm-symbian");
21083 #elif defined (TE_VXWORKS)
21084 return (target_big_endian
21085 ? "elf32-bigarm-vxworks"
21086 : "elf32-littlearm-vxworks");
21088 if (target_big_endian
)
21089 return "elf32-bigarm";
21091 return "elf32-littlearm";
21096 armelf_frob_symbol (symbolS
* symp
,
21099 elf_frob_symbol (symp
, puntp
);
21103 /* MD interface: Finalization. */
21108 literal_pool
* pool
;
21110 /* Ensure that all the IT blocks are properly closed. */
21111 check_it_blocks_finished ();
21113 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21115 /* Put it at the end of the relevant section. */
21116 subseg_set (pool
->section
, pool
->sub_section
);
21118 arm_elf_change_section ();
21125 /* Remove any excess mapping symbols generated for alignment frags in
21126 SEC. We may have created a mapping symbol before a zero byte
21127 alignment; remove it if there's a mapping symbol after the
21130 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21131 void *dummy ATTRIBUTE_UNUSED
)
21133 segment_info_type
*seginfo
= seg_info (sec
);
21136 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21139 for (fragp
= seginfo
->frchainP
->frch_root
;
21141 fragp
= fragp
->fr_next
)
21143 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21144 fragS
*next
= fragp
->fr_next
;
21146 /* Variable-sized frags have been converted to fixed size by
21147 this point. But if this was variable-sized to start with,
21148 there will be a fixed-size frag after it. So don't handle
21150 if (sym
== NULL
|| next
== NULL
)
21153 if (S_GET_VALUE (sym
) < next
->fr_address
)
21154 /* Not at the end of this frag. */
21156 know (S_GET_VALUE (sym
) == next
->fr_address
);
21160 if (next
->tc_frag_data
.first_map
!= NULL
)
21162 /* Next frag starts with a mapping symbol. Discard this
21164 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21168 if (next
->fr_next
== NULL
)
21170 /* This mapping symbol is at the end of the section. Discard
21172 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21173 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21177 /* As long as we have empty frags without any mapping symbols,
21179 /* If the next frag is non-empty and does not start with a
21180 mapping symbol, then this mapping symbol is required. */
21181 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21184 next
= next
->fr_next
;
21186 while (next
!= NULL
);
21191 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21195 arm_adjust_symtab (void)
21200 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21202 if (ARM_IS_THUMB (sym
))
21204 if (THUMB_IS_FUNC (sym
))
21206 /* Mark the symbol as a Thumb function. */
21207 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21208 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21209 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21211 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21212 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21214 as_bad (_("%s: unexpected function type: %d"),
21215 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21217 else switch (S_GET_STORAGE_CLASS (sym
))
21220 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21223 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21226 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21234 if (ARM_IS_INTERWORK (sym
))
21235 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21242 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21244 if (ARM_IS_THUMB (sym
))
21246 elf_symbol_type
* elf_sym
;
21248 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21249 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21251 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21252 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21254 /* If it's a .thumb_func, declare it as so,
21255 otherwise tag label as .code 16. */
21256 if (THUMB_IS_FUNC (sym
))
21257 elf_sym
->internal_elf_sym
.st_info
=
21258 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21259 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21260 elf_sym
->internal_elf_sym
.st_info
=
21261 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21266 /* Remove any overlapping mapping symbols generated by alignment frags. */
21267 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21271 /* MD interface: Initialization. */
21274 set_constant_flonums (void)
21278 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21279 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21283 /* Auto-select Thumb mode if it's the only available instruction set for the
21284 given architecture. */
21287 autoselect_thumb_from_cpu_variant (void)
21289 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21290 opcode_select (16);
21299 if ( (arm_ops_hsh
= hash_new ()) == NULL
21300 || (arm_cond_hsh
= hash_new ()) == NULL
21301 || (arm_shift_hsh
= hash_new ()) == NULL
21302 || (arm_psr_hsh
= hash_new ()) == NULL
21303 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21304 || (arm_reg_hsh
= hash_new ()) == NULL
21305 || (arm_reloc_hsh
= hash_new ()) == NULL
21306 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21307 as_fatal (_("virtual memory exhausted"));
21309 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21310 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21311 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21312 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21313 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21314 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21315 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21316 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21317 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21318 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21319 (void *) (v7m_psrs
+ i
));
21320 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21321 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21323 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21325 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21326 (void *) (barrier_opt_names
+ i
));
21328 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21329 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21332 set_constant_flonums ();
21334 /* Set the cpu variant based on the command-line options. We prefer
21335 -mcpu= over -march= if both are set (as for GCC); and we prefer
21336 -mfpu= over any other way of setting the floating point unit.
21337 Use of legacy options with new options are faulted. */
21340 if (mcpu_cpu_opt
|| march_cpu_opt
)
21341 as_bad (_("use of old and new-style options to set CPU type"));
21343 mcpu_cpu_opt
= legacy_cpu
;
21345 else if (!mcpu_cpu_opt
)
21346 mcpu_cpu_opt
= march_cpu_opt
;
21351 as_bad (_("use of old and new-style options to set FPU type"));
21353 mfpu_opt
= legacy_fpu
;
21355 else if (!mfpu_opt
)
21357 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21358 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21359 /* Some environments specify a default FPU. If they don't, infer it
21360 from the processor. */
21362 mfpu_opt
= mcpu_fpu_opt
;
21364 mfpu_opt
= march_fpu_opt
;
21366 mfpu_opt
= &fpu_default
;
21372 if (mcpu_cpu_opt
!= NULL
)
21373 mfpu_opt
= &fpu_default
;
21374 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21375 mfpu_opt
= &fpu_arch_vfp_v2
;
21377 mfpu_opt
= &fpu_arch_fpa
;
21383 mcpu_cpu_opt
= &cpu_default
;
21384 selected_cpu
= cpu_default
;
21388 selected_cpu
= *mcpu_cpu_opt
;
21390 mcpu_cpu_opt
= &arm_arch_any
;
21393 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21395 autoselect_thumb_from_cpu_variant ();
21397 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21399 #if defined OBJ_COFF || defined OBJ_ELF
21401 unsigned int flags
= 0;
21403 #if defined OBJ_ELF
21404 flags
= meabi_flags
;
21406 switch (meabi_flags
)
21408 case EF_ARM_EABI_UNKNOWN
:
21410 /* Set the flags in the private structure. */
21411 if (uses_apcs_26
) flags
|= F_APCS26
;
21412 if (support_interwork
) flags
|= F_INTERWORK
;
21413 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21414 if (pic_code
) flags
|= F_PIC
;
21415 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21416 flags
|= F_SOFT_FLOAT
;
21418 switch (mfloat_abi_opt
)
21420 case ARM_FLOAT_ABI_SOFT
:
21421 case ARM_FLOAT_ABI_SOFTFP
:
21422 flags
|= F_SOFT_FLOAT
;
21425 case ARM_FLOAT_ABI_HARD
:
21426 if (flags
& F_SOFT_FLOAT
)
21427 as_bad (_("hard-float conflicts with specified fpu"));
21431 /* Using pure-endian doubles (even if soft-float). */
21432 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21433 flags
|= F_VFP_FLOAT
;
21435 #if defined OBJ_ELF
21436 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21437 flags
|= EF_ARM_MAVERICK_FLOAT
;
21440 case EF_ARM_EABI_VER4
:
21441 case EF_ARM_EABI_VER5
:
21442 /* No additional flags to set. */
21449 bfd_set_private_flags (stdoutput
, flags
);
21451 /* We have run out flags in the COFF header to encode the
21452 status of ATPCS support, so instead we create a dummy,
21453 empty, debug section called .arm.atpcs. */
21458 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21462 bfd_set_section_flags
21463 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21464 bfd_set_section_size (stdoutput
, sec
, 0);
21465 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21471 /* Record the CPU type as well. */
21472 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21473 mach
= bfd_mach_arm_iWMMXt2
;
21474 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21475 mach
= bfd_mach_arm_iWMMXt
;
21476 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21477 mach
= bfd_mach_arm_XScale
;
21478 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21479 mach
= bfd_mach_arm_ep9312
;
21480 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21481 mach
= bfd_mach_arm_5TE
;
21482 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21484 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21485 mach
= bfd_mach_arm_5T
;
21487 mach
= bfd_mach_arm_5
;
21489 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21491 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21492 mach
= bfd_mach_arm_4T
;
21494 mach
= bfd_mach_arm_4
;
21496 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21497 mach
= bfd_mach_arm_3M
;
21498 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21499 mach
= bfd_mach_arm_3
;
21500 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21501 mach
= bfd_mach_arm_2a
;
21502 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21503 mach
= bfd_mach_arm_2
;
21505 mach
= bfd_mach_arm_unknown
;
21507 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21510 /* Command line processing. */
21513 Invocation line includes a switch not recognized by the base assembler.
21514 See if it's a processor-specific option.
21516 This routine is somewhat complicated by the need for backwards
21517 compatibility (since older releases of gcc can't be changed).
21518 The new options try to make the interface as compatible as
21521 New options (supported) are:
21523 -mcpu=<cpu name> Assemble for selected processor
21524 -march=<architecture name> Assemble for selected architecture
21525 -mfpu=<fpu architecture> Assemble for selected FPU.
21526 -EB/-mbig-endian Big-endian
21527 -EL/-mlittle-endian Little-endian
21528 -k Generate PIC code
21529 -mthumb Start in Thumb mode
21530 -mthumb-interwork Code supports ARM/Thumb interworking
21532 -m[no-]warn-deprecated Warn about deprecated features
21534 For now we will also provide support for:
21536 -mapcs-32 32-bit Program counter
21537 -mapcs-26 26-bit Program counter
21538 -macps-float Floats passed in FP registers
21539 -mapcs-reentrant Reentrant code
21541 (sometime these will probably be replaced with -mapcs=<list of options>
21542 and -matpcs=<list of options>)
21544 The remaining options are only supported for back-wards compatibility.
21545 Cpu variants, the arm part is optional:
21546 -m[arm]1 Currently not supported.
21547 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21548 -m[arm]3 Arm 3 processor
21549 -m[arm]6[xx], Arm 6 processors
21550 -m[arm]7[xx][t][[d]m] Arm 7 processors
21551 -m[arm]8[10] Arm 8 processors
21552 -m[arm]9[20][tdmi] Arm 9 processors
21553 -mstrongarm[110[0]] StrongARM processors
21554 -mxscale XScale processors
21555 -m[arm]v[2345[t[e]]] Arm architectures
21556 -mall All (except the ARM1)
21558 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21559 -mfpe-old (No float load/store multiples)
21560 -mvfpxd VFP Single precision
21562 -mno-fpu Disable all floating point instructions
21564 The following CPU names are recognized:
21565 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21566 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21567 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21568 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21569 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21570 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21571 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21575 const char * md_shortopts
= "m:k";
21577 #ifdef ARM_BI_ENDIAN
21578 #define OPTION_EB (OPTION_MD_BASE + 0)
21579 #define OPTION_EL (OPTION_MD_BASE + 1)
21581 #if TARGET_BYTES_BIG_ENDIAN
21582 #define OPTION_EB (OPTION_MD_BASE + 0)
21584 #define OPTION_EL (OPTION_MD_BASE + 1)
21587 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21589 struct option md_longopts
[] =
21592 {"EB", no_argument
, NULL
, OPTION_EB
},
21595 {"EL", no_argument
, NULL
, OPTION_EL
},
21597 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21598 {NULL
, no_argument
, NULL
, 0}
21601 size_t md_longopts_size
= sizeof (md_longopts
);
21603 struct arm_option_table
21605 char *option
; /* Option name to match. */
21606 char *help
; /* Help information. */
21607 int *var
; /* Variable to change. */
21608 int value
; /* What to change it to. */
21609 char *deprecated
; /* If non-null, print this message. */
21612 struct arm_option_table arm_opts
[] =
21614 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21615 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21616 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21617 &support_interwork
, 1, NULL
},
21618 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21619 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21620 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21622 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21623 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21624 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21625 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21628 /* These are recognized by the assembler, but have no affect on code. */
21629 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21630 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21632 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21633 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21634 &warn_on_deprecated
, 0, NULL
},
21635 {NULL
, NULL
, NULL
, 0, NULL
}
21638 struct arm_legacy_option_table
21640 char *option
; /* Option name to match. */
21641 const arm_feature_set
**var
; /* Variable to change. */
21642 const arm_feature_set value
; /* What to change it to. */
21643 char *deprecated
; /* If non-null, print this message. */
21646 const struct arm_legacy_option_table arm_legacy_opts
[] =
21648 /* DON'T add any new processors to this list -- we want the whole list
21649 to go away... Add them to the processors table instead. */
21650 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21651 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21652 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21653 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21654 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21655 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21656 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21657 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21658 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21659 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21660 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21661 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21662 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21663 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21664 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21665 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21666 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21667 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21668 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21669 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21670 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21671 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21672 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21673 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21674 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21675 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21676 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21677 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21678 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21679 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21680 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21681 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21682 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21683 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21684 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21685 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21686 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21687 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21688 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21689 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21690 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21691 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21692 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21693 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21694 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21695 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21696 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21697 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21698 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21699 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21700 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21701 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21702 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21703 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21704 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21705 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21706 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21707 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21708 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21709 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21710 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21711 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21712 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21713 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21714 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21715 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21716 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21717 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21718 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21719 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21720 N_("use -mcpu=strongarm110")},
21721 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21722 N_("use -mcpu=strongarm1100")},
21723 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21724 N_("use -mcpu=strongarm1110")},
21725 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21726 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21727 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21729 /* Architecture variants -- don't add any more to this list either. */
21730 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21731 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21732 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21733 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21734 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21735 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21736 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21737 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21738 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21739 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21740 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21741 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21742 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21743 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21744 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21745 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21746 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21747 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21749 /* Floating point variants -- don't add any more to this list either. */
21750 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21751 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21752 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21753 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21754 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21756 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21759 struct arm_cpu_option_table
21762 const arm_feature_set value
;
21763 /* For some CPUs we assume an FPU unless the user explicitly sets
21765 const arm_feature_set default_fpu
;
21766 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21768 const char *canonical_name
;
21771 /* This list should, at a minimum, contain all the cpu names
21772 recognized by GCC. */
21773 static const struct arm_cpu_option_table arm_cpus
[] =
21775 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21776 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21777 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21778 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21779 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21780 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21781 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21782 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21783 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21784 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21785 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21786 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21787 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21788 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21789 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21790 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21791 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21792 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21793 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21794 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21795 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21796 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21797 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21798 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21799 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21800 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21801 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21802 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21803 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21804 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21805 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21806 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21807 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21808 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21809 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21810 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21811 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21812 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21813 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21814 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21815 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21816 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21817 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21818 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21819 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21820 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21821 /* For V5 or later processors we default to using VFP; but the user
21822 should really set the FPU type explicitly. */
21823 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21824 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21825 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21826 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21827 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21828 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21829 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21830 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21831 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21832 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21833 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21834 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21835 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21836 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21837 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21838 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21839 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21840 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21841 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21842 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21843 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21844 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21845 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21846 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21847 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21848 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21849 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21850 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21851 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21852 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21853 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21854 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21855 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21856 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
21857 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21858 | FPU_NEON_EXT_V1
),
21860 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21861 | FPU_NEON_EXT_V1
),
21863 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
21864 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
21865 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
21866 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21867 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21868 /* ??? XSCALE is really an architecture. */
21869 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21870 /* ??? iwmmxt is not a processor. */
21871 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
21872 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
21873 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21875 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
21876 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
21879 struct arm_arch_option_table
21882 const arm_feature_set value
;
21883 const arm_feature_set default_fpu
;
21886 /* This list should, at a minimum, contain all the architecture names
21887 recognized by GCC. */
21888 static const struct arm_arch_option_table arm_archs
[] =
21890 {"all", ARM_ANY
, FPU_ARCH_FPA
},
21891 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
21892 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
21893 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21894 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21895 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
21896 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
21897 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
21898 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
21899 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
21900 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
21901 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
21902 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
21903 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
21904 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
21905 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
21906 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
21907 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21908 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21909 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
21910 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
21911 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
21912 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
21913 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
21914 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
21915 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
21916 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
21917 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
21918 /* The official spelling of the ARMv7 profile variants is the dashed form.
21919 Accept the non-dashed form for compatibility with old toolchains. */
21920 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21921 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21922 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21923 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21924 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21925 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21926 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
21927 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
21928 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
21929 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
21932 /* ISA extensions in the co-processor space. */
21933 struct arm_option_cpu_value_table
21936 const arm_feature_set value
;
21939 static const struct arm_option_cpu_value_table arm_extensions
[] =
21941 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
21942 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
21943 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
21944 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
21945 {NULL
, ARM_ARCH_NONE
}
21948 /* This list should, at a minimum, contain all the fpu names
21949 recognized by GCC. */
21950 static const struct arm_option_cpu_value_table arm_fpus
[] =
21952 {"softfpa", FPU_NONE
},
21953 {"fpe", FPU_ARCH_FPE
},
21954 {"fpe2", FPU_ARCH_FPE
},
21955 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
21956 {"fpa", FPU_ARCH_FPA
},
21957 {"fpa10", FPU_ARCH_FPA
},
21958 {"fpa11", FPU_ARCH_FPA
},
21959 {"arm7500fe", FPU_ARCH_FPA
},
21960 {"softvfp", FPU_ARCH_VFP
},
21961 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
21962 {"vfp", FPU_ARCH_VFP_V2
},
21963 {"vfp9", FPU_ARCH_VFP_V2
},
21964 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
21965 {"vfp10", FPU_ARCH_VFP_V2
},
21966 {"vfp10-r0", FPU_ARCH_VFP_V1
},
21967 {"vfpxd", FPU_ARCH_VFP_V1xD
},
21968 {"vfpv2", FPU_ARCH_VFP_V2
},
21969 {"vfpv3", FPU_ARCH_VFP_V3
},
21970 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
21971 {"arm1020t", FPU_ARCH_VFP_V1
},
21972 {"arm1020e", FPU_ARCH_VFP_V2
},
21973 {"arm1136jfs", FPU_ARCH_VFP_V2
},
21974 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
21975 {"maverick", FPU_ARCH_MAVERICK
},
21976 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
21977 {"neon-fp16", FPU_ARCH_NEON_FP16
},
21978 {NULL
, ARM_ARCH_NONE
}
21981 struct arm_option_value_table
21987 static const struct arm_option_value_table arm_float_abis
[] =
21989 {"hard", ARM_FLOAT_ABI_HARD
},
21990 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
21991 {"soft", ARM_FLOAT_ABI_SOFT
},
21996 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
21997 static const struct arm_option_value_table arm_eabis
[] =
21999 {"gnu", EF_ARM_EABI_UNKNOWN
},
22000 {"4", EF_ARM_EABI_VER4
},
22001 {"5", EF_ARM_EABI_VER5
},
22006 struct arm_long_option_table
22008 char * option
; /* Substring to match. */
22009 char * help
; /* Help information. */
22010 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22011 char * deprecated
; /* If non-null, print this message. */
22015 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22017 arm_feature_set
*ext_set
= (arm_feature_set
*)
22018 xmalloc (sizeof (arm_feature_set
));
22020 /* Copy the feature set, so that we can modify it. */
22021 *ext_set
= **opt_p
;
22024 while (str
!= NULL
&& *str
!= 0)
22026 const struct arm_option_cpu_value_table
* opt
;
22032 as_bad (_("invalid architectural extension"));
22037 ext
= strchr (str
, '+');
22040 optlen
= ext
- str
;
22042 optlen
= strlen (str
);
22046 as_bad (_("missing architectural extension"));
22050 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22051 if (strncmp (opt
->name
, str
, optlen
) == 0)
22053 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22057 if (opt
->name
== NULL
)
22059 as_bad (_("unknown architectural extension `%s'"), str
);
22070 arm_parse_cpu (char * str
)
22072 const struct arm_cpu_option_table
* opt
;
22073 char * ext
= strchr (str
, '+');
22077 optlen
= ext
- str
;
22079 optlen
= strlen (str
);
22083 as_bad (_("missing cpu name `%s'"), str
);
22087 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22088 if (strncmp (opt
->name
, str
, optlen
) == 0)
22090 mcpu_cpu_opt
= &opt
->value
;
22091 mcpu_fpu_opt
= &opt
->default_fpu
;
22092 if (opt
->canonical_name
)
22093 strcpy (selected_cpu_name
, opt
->canonical_name
);
22098 for (i
= 0; i
< optlen
; i
++)
22099 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22100 selected_cpu_name
[i
] = 0;
22104 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22109 as_bad (_("unknown cpu `%s'"), str
);
22114 arm_parse_arch (char * str
)
22116 const struct arm_arch_option_table
*opt
;
22117 char *ext
= strchr (str
, '+');
22121 optlen
= ext
- str
;
22123 optlen
= strlen (str
);
22127 as_bad (_("missing architecture name `%s'"), str
);
22131 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22132 if (streq (opt
->name
, str
))
22134 march_cpu_opt
= &opt
->value
;
22135 march_fpu_opt
= &opt
->default_fpu
;
22136 strcpy (selected_cpu_name
, opt
->name
);
22139 return arm_parse_extension (ext
, &march_cpu_opt
);
22144 as_bad (_("unknown architecture `%s'\n"), str
);
22149 arm_parse_fpu (char * str
)
22151 const struct arm_option_cpu_value_table
* opt
;
22153 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22154 if (streq (opt
->name
, str
))
22156 mfpu_opt
= &opt
->value
;
22160 as_bad (_("unknown floating point format `%s'\n"), str
);
22165 arm_parse_float_abi (char * str
)
22167 const struct arm_option_value_table
* opt
;
22169 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22170 if (streq (opt
->name
, str
))
22172 mfloat_abi_opt
= opt
->value
;
22176 as_bad (_("unknown floating point abi `%s'\n"), str
);
22182 arm_parse_eabi (char * str
)
22184 const struct arm_option_value_table
*opt
;
22186 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22187 if (streq (opt
->name
, str
))
22189 meabi_flags
= opt
->value
;
22192 as_bad (_("unknown EABI `%s'\n"), str
);
22198 arm_parse_it_mode (char * str
)
22200 bfd_boolean ret
= TRUE
;
22202 if (streq ("arm", str
))
22203 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22204 else if (streq ("thumb", str
))
22205 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22206 else if (streq ("always", str
))
22207 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22208 else if (streq ("never", str
))
22209 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22212 as_bad (_("unknown implicit IT mode `%s', should be "\
22213 "arm, thumb, always, or never."), str
);
22220 struct arm_long_option_table arm_long_opts
[] =
22222 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22223 arm_parse_cpu
, NULL
},
22224 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22225 arm_parse_arch
, NULL
},
22226 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22227 arm_parse_fpu
, NULL
},
22228 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22229 arm_parse_float_abi
, NULL
},
22231 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22232 arm_parse_eabi
, NULL
},
22234 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22235 arm_parse_it_mode
, NULL
},
22236 {NULL
, NULL
, 0, NULL
}
22240 md_parse_option (int c
, char * arg
)
22242 struct arm_option_table
*opt
;
22243 const struct arm_legacy_option_table
*fopt
;
22244 struct arm_long_option_table
*lopt
;
22250 target_big_endian
= 1;
22256 target_big_endian
= 0;
22260 case OPTION_FIX_V4BX
:
22265 /* Listing option. Just ignore these, we don't support additional
22270 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22272 if (c
== opt
->option
[0]
22273 && ((arg
== NULL
&& opt
->option
[1] == 0)
22274 || streq (arg
, opt
->option
+ 1)))
22276 /* If the option is deprecated, tell the user. */
22277 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22278 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22279 arg
? arg
: "", _(opt
->deprecated
));
22281 if (opt
->var
!= NULL
)
22282 *opt
->var
= opt
->value
;
22288 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22290 if (c
== fopt
->option
[0]
22291 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22292 || streq (arg
, fopt
->option
+ 1)))
22294 /* If the option is deprecated, tell the user. */
22295 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22296 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22297 arg
? arg
: "", _(fopt
->deprecated
));
22299 if (fopt
->var
!= NULL
)
22300 *fopt
->var
= &fopt
->value
;
22306 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22308 /* These options are expected to have an argument. */
22309 if (c
== lopt
->option
[0]
22311 && strncmp (arg
, lopt
->option
+ 1,
22312 strlen (lopt
->option
+ 1)) == 0)
22314 /* If the option is deprecated, tell the user. */
22315 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22316 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22317 _(lopt
->deprecated
));
22319 /* Call the sup-option parser. */
22320 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22331 md_show_usage (FILE * fp
)
22333 struct arm_option_table
*opt
;
22334 struct arm_long_option_table
*lopt
;
22336 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22338 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22339 if (opt
->help
!= NULL
)
22340 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22342 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22343 if (lopt
->help
!= NULL
)
22344 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22348 -EB assemble code for a big-endian cpu\n"));
22353 -EL assemble code for a little-endian cpu\n"));
22357 --fix-v4bx Allow BX in ARMv4 code\n"));
22365 arm_feature_set flags
;
22366 } cpu_arch_ver_table
;
22368 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22369 least features first. */
22370 static const cpu_arch_ver_table cpu_arch_ver
[] =
22376 {4, ARM_ARCH_V5TE
},
22377 {5, ARM_ARCH_V5TEJ
},
22381 {11, ARM_ARCH_V6M
},
22382 {8, ARM_ARCH_V6T2
},
22383 {10, ARM_ARCH_V7A
},
22384 {10, ARM_ARCH_V7R
},
22385 {10, ARM_ARCH_V7M
},
22389 /* Set an attribute if it has not already been set by the user. */
22391 aeabi_set_attribute_int (int tag
, int value
)
22394 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22395 || !attributes_set_explicitly
[tag
])
22396 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22400 aeabi_set_attribute_string (int tag
, const char *value
)
22403 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22404 || !attributes_set_explicitly
[tag
])
22405 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22408 /* Set the public EABI object attributes. */
22410 aeabi_set_public_attributes (void)
22413 arm_feature_set flags
;
22414 arm_feature_set tmp
;
22415 const cpu_arch_ver_table
*p
;
22417 /* Choose the architecture based on the capabilities of the requested cpu
22418 (if any) and/or the instructions actually used. */
22419 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22420 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22421 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22422 /*Allow the user to override the reported architecture. */
22425 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22426 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22431 for (p
= cpu_arch_ver
; p
->val
; p
++)
22433 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22436 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22440 /* Tag_CPU_name. */
22441 if (selected_cpu_name
[0])
22445 p
= selected_cpu_name
;
22446 if (strncmp (p
, "armv", 4) == 0)
22451 for (i
= 0; p
[i
]; i
++)
22452 p
[i
] = TOUPPER (p
[i
]);
22454 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22456 /* Tag_CPU_arch. */
22457 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22458 /* Tag_CPU_arch_profile. */
22459 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22460 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22461 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22462 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22463 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22464 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22465 /* Tag_ARM_ISA_use. */
22466 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22468 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22469 /* Tag_THUMB_ISA_use. */
22470 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22472 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22473 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22474 /* Tag_VFP_arch. */
22475 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22476 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22477 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
22478 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22479 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22480 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22481 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22482 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22483 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22484 /* Tag_WMMX_arch. */
22485 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22486 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22487 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22488 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22489 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22490 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22491 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
22492 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22493 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
22494 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22497 /* Add the default contents for the .ARM.attributes section. */
22501 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22504 aeabi_set_public_attributes ();
22506 #endif /* OBJ_ELF */
22509 /* Parse a .cpu directive. */
22512 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22514 const struct arm_cpu_option_table
*opt
;
22518 name
= input_line_pointer
;
22519 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22520 input_line_pointer
++;
22521 saved_char
= *input_line_pointer
;
22522 *input_line_pointer
= 0;
22524 /* Skip the first "all" entry. */
22525 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22526 if (streq (opt
->name
, name
))
22528 mcpu_cpu_opt
= &opt
->value
;
22529 selected_cpu
= opt
->value
;
22530 if (opt
->canonical_name
)
22531 strcpy (selected_cpu_name
, opt
->canonical_name
);
22535 for (i
= 0; opt
->name
[i
]; i
++)
22536 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22537 selected_cpu_name
[i
] = 0;
22539 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22540 *input_line_pointer
= saved_char
;
22541 demand_empty_rest_of_line ();
22544 as_bad (_("unknown cpu `%s'"), name
);
22545 *input_line_pointer
= saved_char
;
22546 ignore_rest_of_line ();
22550 /* Parse a .arch directive. */
22553 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22555 const struct arm_arch_option_table
*opt
;
22559 name
= input_line_pointer
;
22560 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22561 input_line_pointer
++;
22562 saved_char
= *input_line_pointer
;
22563 *input_line_pointer
= 0;
22565 /* Skip the first "all" entry. */
22566 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22567 if (streq (opt
->name
, name
))
22569 mcpu_cpu_opt
= &opt
->value
;
22570 selected_cpu
= opt
->value
;
22571 strcpy (selected_cpu_name
, opt
->name
);
22572 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22573 *input_line_pointer
= saved_char
;
22574 demand_empty_rest_of_line ();
22578 as_bad (_("unknown architecture `%s'\n"), name
);
22579 *input_line_pointer
= saved_char
;
22580 ignore_rest_of_line ();
22584 /* Parse a .object_arch directive. */
22587 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22589 const struct arm_arch_option_table
*opt
;
22593 name
= input_line_pointer
;
22594 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22595 input_line_pointer
++;
22596 saved_char
= *input_line_pointer
;
22597 *input_line_pointer
= 0;
22599 /* Skip the first "all" entry. */
22600 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22601 if (streq (opt
->name
, name
))
22603 object_arch
= &opt
->value
;
22604 *input_line_pointer
= saved_char
;
22605 demand_empty_rest_of_line ();
22609 as_bad (_("unknown architecture `%s'\n"), name
);
22610 *input_line_pointer
= saved_char
;
22611 ignore_rest_of_line ();
22614 /* Parse a .fpu directive. */
22617 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22619 const struct arm_option_cpu_value_table
*opt
;
22623 name
= input_line_pointer
;
22624 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22625 input_line_pointer
++;
22626 saved_char
= *input_line_pointer
;
22627 *input_line_pointer
= 0;
22629 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22630 if (streq (opt
->name
, name
))
22632 mfpu_opt
= &opt
->value
;
22633 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22634 *input_line_pointer
= saved_char
;
22635 demand_empty_rest_of_line ();
22639 as_bad (_("unknown floating point format `%s'\n"), name
);
22640 *input_line_pointer
= saved_char
;
22641 ignore_rest_of_line ();
22644 /* Copy symbol information. */
22647 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22649 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22653 /* Given a symbolic attribute NAME, return the proper integer value.
22654 Returns -1 if the attribute is not known. */
22657 arm_convert_symbolic_attribute (const char *name
)
22659 static const struct
22664 attribute_table
[] =
22666 /* When you modify this table you should
22667 also modify the list in doc/c-arm.texi. */
22668 #define T(tag) {#tag, tag}
22669 T (Tag_CPU_raw_name
),
22672 T (Tag_CPU_arch_profile
),
22673 T (Tag_ARM_ISA_use
),
22674 T (Tag_THUMB_ISA_use
),
22677 T (Tag_Advanced_SIMD_arch
),
22678 T (Tag_PCS_config
),
22679 T (Tag_ABI_PCS_R9_use
),
22680 T (Tag_ABI_PCS_RW_data
),
22681 T (Tag_ABI_PCS_RO_data
),
22682 T (Tag_ABI_PCS_GOT_use
),
22683 T (Tag_ABI_PCS_wchar_t
),
22684 T (Tag_ABI_FP_rounding
),
22685 T (Tag_ABI_FP_denormal
),
22686 T (Tag_ABI_FP_exceptions
),
22687 T (Tag_ABI_FP_user_exceptions
),
22688 T (Tag_ABI_FP_number_model
),
22689 T (Tag_ABI_align8_needed
),
22690 T (Tag_ABI_align8_preserved
),
22691 T (Tag_ABI_enum_size
),
22692 T (Tag_ABI_HardFP_use
),
22693 T (Tag_ABI_VFP_args
),
22694 T (Tag_ABI_WMMX_args
),
22695 T (Tag_ABI_optimization_goals
),
22696 T (Tag_ABI_FP_optimization_goals
),
22697 T (Tag_compatibility
),
22698 T (Tag_CPU_unaligned_access
),
22699 T (Tag_VFP_HP_extension
),
22700 T (Tag_ABI_FP_16bit_format
),
22701 T (Tag_nodefaults
),
22702 T (Tag_also_compatible_with
),
22703 T (Tag_conformance
),
22705 T (Tag_Virtualization_use
),
22706 T (Tag_MPextension_use
)
22714 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22715 if (streq (name
, attribute_table
[i
].name
))
22716 return attribute_table
[i
].tag
;
22722 /* Apply sym value for relocations only in the case that
22723 they are for local symbols and you have the respective
22724 architectural feature for blx and simple switches. */
22726 arm_apply_sym_value (struct fix
* fixP
)
22729 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22730 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22732 switch (fixP
->fx_r_type
)
22734 case BFD_RELOC_ARM_PCREL_BLX
:
22735 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22736 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22740 case BFD_RELOC_ARM_PCREL_CALL
:
22741 case BFD_RELOC_THUMB_PCREL_BLX
:
22742 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22753 #endif /* OBJ_ELF */