1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_arch_any
= ARM_ANY
;
239 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
240 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
241 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
243 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
246 static const arm_feature_set arm_cext_iwmmxt2
=
247 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
248 static const arm_feature_set arm_cext_iwmmxt
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
250 static const arm_feature_set arm_cext_xscale
=
251 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
252 static const arm_feature_set arm_cext_maverick
=
253 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
254 static const arm_feature_set fpu_fpa_ext_v1
=
255 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
256 static const arm_feature_set fpu_fpa_ext_v2
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
258 static const arm_feature_set fpu_vfp_ext_v1xd
=
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
260 static const arm_feature_set fpu_vfp_ext_v1
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
262 static const arm_feature_set fpu_vfp_ext_v2
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
264 static const arm_feature_set fpu_vfp_ext_v3xd
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
266 static const arm_feature_set fpu_vfp_ext_v3
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
268 static const arm_feature_set fpu_vfp_ext_d32
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
270 static const arm_feature_set fpu_neon_ext_v1
=
271 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
272 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
275 static const arm_feature_set fpu_vfp_fp16
=
276 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
277 static const arm_feature_set fpu_neon_ext_fma
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
280 static const arm_feature_set fpu_vfp_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_armv8
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
284 static const arm_feature_set fpu_vfp_ext_armv8xd
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
286 static const arm_feature_set fpu_neon_ext_armv8
=
287 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
288 static const arm_feature_set fpu_crypto_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
290 static const arm_feature_set crc_ext_armv8
=
291 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
292 static const arm_feature_set fpu_neon_ext_v8_1
=
293 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
295 static int mfloat_abi_opt
= -1;
296 /* Record user cpu selection for object attributes. */
297 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
298 /* Must be long enough to hold any of the names in arm_cpus. */
299 static char selected_cpu_name
[20];
301 extern FLONUM_TYPE generic_floating_point_number
;
303 /* Return if no cpu was selected on command-line. */
305 no_cpu_selected (void)
307 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
312 static int meabi_flags
= EABI_DEFAULT
;
314 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
317 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
322 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
327 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
328 symbolS
* GOT_symbol
;
331 /* 0: assemble for ARM,
332 1: assemble for Thumb,
333 2: assemble for Thumb even though target CPU does not support thumb
335 static int thumb_mode
= 0;
336 /* A value distinct from the possible values for thumb_mode that we
337 can use to record whether thumb_mode has been copied into the
338 tc_frag_data field of a frag. */
339 #define MODE_RECORDED (1 << 4)
341 /* Specifies the intrinsic IT insn behavior mode. */
342 enum implicit_it_mode
344 IMPLICIT_IT_MODE_NEVER
= 0x00,
345 IMPLICIT_IT_MODE_ARM
= 0x01,
346 IMPLICIT_IT_MODE_THUMB
= 0x02,
347 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
349 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
351 /* If unified_syntax is true, we are processing the new unified
352 ARM/Thumb syntax. Important differences from the old ARM mode:
354 - Immediate operands do not require a # prefix.
355 - Conditional affixes always appear at the end of the
356 instruction. (For backward compatibility, those instructions
357 that formerly had them in the middle, continue to accept them
359 - The IT instruction may appear, and if it does is validated
360 against subsequent conditional affixes. It does not generate
363 Important differences from the old Thumb mode:
365 - Immediate operands do not require a # prefix.
366 - Most of the V6T2 instructions are only available in unified mode.
367 - The .N and .W suffixes are recognized and honored (it is an error
368 if they cannot be honored).
369 - All instructions set the flags if and only if they have an 's' affix.
370 - Conditional affixes may be used. They are validated against
371 preceding IT instructions. Unlike ARM mode, you cannot use a
372 conditional affix except in the scope of an IT instruction. */
374 static bfd_boolean unified_syntax
= FALSE
;
376 /* An immediate operand can start with #, and ld*, st*, pld operands
377 can contain [ and ]. We need to tell APP not to elide whitespace
378 before a [, which can appear as the first operand for pld.
379 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
380 const char arm_symbol_chars
[] = "#[]{}";
395 enum neon_el_type type
;
399 #define NEON_MAX_TYPE_ELS 4
403 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
407 enum it_instruction_type
412 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
413 if inside, should be the last one. */
414 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
415 i.e. BKPT and NOP. */
416 IT_INSN
/* The IT insn has been parsed. */
419 /* The maximum number of operands we need. */
420 #define ARM_IT_MAX_OPERANDS 6
425 unsigned long instruction
;
429 /* "uncond_value" is set to the value in place of the conditional field in
430 unconditional versions of the instruction, or -1 if nothing is
433 struct neon_type vectype
;
434 /* This does not indicate an actual NEON instruction, only that
435 the mnemonic accepts neon-style type suffixes. */
437 /* Set to the opcode if the instruction needs relaxation.
438 Zero if the instruction is not relaxed. */
442 bfd_reloc_code_real_type type
;
447 enum it_instruction_type it_insn_type
;
453 struct neon_type_el vectype
;
454 unsigned present
: 1; /* Operand present. */
455 unsigned isreg
: 1; /* Operand was a register. */
456 unsigned immisreg
: 1; /* .imm field is a second register. */
457 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
458 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
459 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
460 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
461 instructions. This allows us to disambiguate ARM <-> vector insns. */
462 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
463 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
464 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
465 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
466 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
467 unsigned writeback
: 1; /* Operand has trailing ! */
468 unsigned preind
: 1; /* Preindexed address. */
469 unsigned postind
: 1; /* Postindexed address. */
470 unsigned negative
: 1; /* Index register was negated. */
471 unsigned shifted
: 1; /* Shift applied to operation. */
472 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
473 } operands
[ARM_IT_MAX_OPERANDS
];
476 static struct arm_it inst
;
478 #define NUM_FLOAT_VALS 8
480 const char * fp_const
[] =
482 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
485 /* Number of littlenums required to hold an extended precision number. */
486 #define MAX_LITTLENUMS 6
488 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
498 #define CP_T_X 0x00008000
499 #define CP_T_Y 0x00400000
501 #define CONDS_BIT 0x00100000
502 #define LOAD_BIT 0x00100000
504 #define DOUBLE_LOAD_FLAG 0x00000001
508 const char * template_name
;
512 #define COND_ALWAYS 0xE
516 const char * template_name
;
520 struct asm_barrier_opt
522 const char * template_name
;
524 const arm_feature_set arch
;
527 /* The bit that distinguishes CPSR and SPSR. */
528 #define SPSR_BIT (1 << 22)
530 /* The individual PSR flag bits. */
531 #define PSR_c (1 << 16)
532 #define PSR_x (1 << 17)
533 #define PSR_s (1 << 18)
534 #define PSR_f (1 << 19)
539 bfd_reloc_code_real_type reloc
;
544 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
545 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
550 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
553 /* Bits for DEFINED field in neon_typed_alias. */
554 #define NTA_HASTYPE 1
555 #define NTA_HASINDEX 2
557 struct neon_typed_alias
559 unsigned char defined
;
561 struct neon_type_el eltype
;
564 /* ARM register categories. This includes coprocessor numbers and various
565 architecture extensions' registers. */
592 /* Structure for a hash table entry for a register.
593 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
594 information which states whether a vector type or index is specified (for a
595 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
601 unsigned char builtin
;
602 struct neon_typed_alias
* neon
;
605 /* Diagnostics used when we don't get a register of the expected type. */
606 const char * const reg_expected_msgs
[] =
608 N_("ARM register expected"),
609 N_("bad or missing co-processor number"),
610 N_("co-processor register expected"),
611 N_("FPA register expected"),
612 N_("VFP single precision register expected"),
613 N_("VFP/Neon double precision register expected"),
614 N_("Neon quad precision register expected"),
615 N_("VFP single or double precision register expected"),
616 N_("Neon double or quad precision register expected"),
617 N_("VFP single, double or Neon quad precision register expected"),
618 N_("VFP system register expected"),
619 N_("Maverick MVF register expected"),
620 N_("Maverick MVD register expected"),
621 N_("Maverick MVFX register expected"),
622 N_("Maverick MVDX register expected"),
623 N_("Maverick MVAX register expected"),
624 N_("Maverick DSPSC register expected"),
625 N_("iWMMXt data register expected"),
626 N_("iWMMXt control register expected"),
627 N_("iWMMXt scalar register expected"),
628 N_("XScale accumulator register expected"),
631 /* Some well known registers that we refer to directly elsewhere. */
637 /* ARM instructions take 4bytes in the object file, Thumb instructions
643 /* Basic string to match. */
644 const char * template_name
;
646 /* Parameters to instruction. */
647 unsigned int operands
[8];
649 /* Conditional tag - see opcode_lookup. */
650 unsigned int tag
: 4;
652 /* Basic instruction code. */
653 unsigned int avalue
: 28;
655 /* Thumb-format instruction code. */
658 /* Which architecture variant provides this instruction. */
659 const arm_feature_set
* avariant
;
660 const arm_feature_set
* tvariant
;
662 /* Function to call to encode instruction in ARM format. */
663 void (* aencode
) (void);
665 /* Function to call to encode instruction in Thumb format. */
666 void (* tencode
) (void);
669 /* Defines for various bits that we will want to toggle. */
670 #define INST_IMMEDIATE 0x02000000
671 #define OFFSET_REG 0x02000000
672 #define HWOFFSET_IMM 0x00400000
673 #define SHIFT_BY_REG 0x00000010
674 #define PRE_INDEX 0x01000000
675 #define INDEX_UP 0x00800000
676 #define WRITE_BACK 0x00200000
677 #define LDM_TYPE_2_OR_3 0x00400000
678 #define CPSI_MMOD 0x00020000
680 #define LITERAL_MASK 0xf000f000
681 #define OPCODE_MASK 0xfe1fffff
682 #define V4_STR_BIT 0x00000020
683 #define VLDR_VMOV_SAME 0x0040f000
685 #define T2_SUBS_PC_LR 0xf3de8f00
687 #define DATA_OP_SHIFT 21
689 #define T2_OPCODE_MASK 0xfe1fffff
690 #define T2_DATA_OP_SHIFT 21
692 #define A_COND_MASK 0xf0000000
693 #define A_PUSH_POP_OP_MASK 0x0fff0000
695 /* Opcodes for pushing/poping registers to/from the stack. */
696 #define A1_OPCODE_PUSH 0x092d0000
697 #define A2_OPCODE_PUSH 0x052d0004
698 #define A2_OPCODE_POP 0x049d0004
700 /* Codes to distinguish the arithmetic instructions. */
711 #define OPCODE_CMP 10
712 #define OPCODE_CMN 11
713 #define OPCODE_ORR 12
714 #define OPCODE_MOV 13
715 #define OPCODE_BIC 14
716 #define OPCODE_MVN 15
718 #define T2_OPCODE_AND 0
719 #define T2_OPCODE_BIC 1
720 #define T2_OPCODE_ORR 2
721 #define T2_OPCODE_ORN 3
722 #define T2_OPCODE_EOR 4
723 #define T2_OPCODE_ADD 8
724 #define T2_OPCODE_ADC 10
725 #define T2_OPCODE_SBC 11
726 #define T2_OPCODE_SUB 13
727 #define T2_OPCODE_RSB 14
729 #define T_OPCODE_MUL 0x4340
730 #define T_OPCODE_TST 0x4200
731 #define T_OPCODE_CMN 0x42c0
732 #define T_OPCODE_NEG 0x4240
733 #define T_OPCODE_MVN 0x43c0
735 #define T_OPCODE_ADD_R3 0x1800
736 #define T_OPCODE_SUB_R3 0x1a00
737 #define T_OPCODE_ADD_HI 0x4400
738 #define T_OPCODE_ADD_ST 0xb000
739 #define T_OPCODE_SUB_ST 0xb080
740 #define T_OPCODE_ADD_SP 0xa800
741 #define T_OPCODE_ADD_PC 0xa000
742 #define T_OPCODE_ADD_I8 0x3000
743 #define T_OPCODE_SUB_I8 0x3800
744 #define T_OPCODE_ADD_I3 0x1c00
745 #define T_OPCODE_SUB_I3 0x1e00
747 #define T_OPCODE_ASR_R 0x4100
748 #define T_OPCODE_LSL_R 0x4080
749 #define T_OPCODE_LSR_R 0x40c0
750 #define T_OPCODE_ROR_R 0x41c0
751 #define T_OPCODE_ASR_I 0x1000
752 #define T_OPCODE_LSL_I 0x0000
753 #define T_OPCODE_LSR_I 0x0800
755 #define T_OPCODE_MOV_I8 0x2000
756 #define T_OPCODE_CMP_I8 0x2800
757 #define T_OPCODE_CMP_LR 0x4280
758 #define T_OPCODE_MOV_HR 0x4600
759 #define T_OPCODE_CMP_HR 0x4500
761 #define T_OPCODE_LDR_PC 0x4800
762 #define T_OPCODE_LDR_SP 0x9800
763 #define T_OPCODE_STR_SP 0x9000
764 #define T_OPCODE_LDR_IW 0x6800
765 #define T_OPCODE_STR_IW 0x6000
766 #define T_OPCODE_LDR_IH 0x8800
767 #define T_OPCODE_STR_IH 0x8000
768 #define T_OPCODE_LDR_IB 0x7800
769 #define T_OPCODE_STR_IB 0x7000
770 #define T_OPCODE_LDR_RW 0x5800
771 #define T_OPCODE_STR_RW 0x5000
772 #define T_OPCODE_LDR_RH 0x5a00
773 #define T_OPCODE_STR_RH 0x5200
774 #define T_OPCODE_LDR_RB 0x5c00
775 #define T_OPCODE_STR_RB 0x5400
777 #define T_OPCODE_PUSH 0xb400
778 #define T_OPCODE_POP 0xbc00
780 #define T_OPCODE_BRANCH 0xe000
782 #define THUMB_SIZE 2 /* Size of thumb instruction. */
783 #define THUMB_PP_PC_LR 0x0100
784 #define THUMB_LOAD_BIT 0x0800
785 #define THUMB2_LOAD_BIT 0x00100000
787 #define BAD_ARGS _("bad arguments to instruction")
788 #define BAD_SP _("r13 not allowed here")
789 #define BAD_PC _("r15 not allowed here")
790 #define BAD_COND _("instruction cannot be conditional")
791 #define BAD_OVERLAP _("registers may not be the same")
792 #define BAD_HIREG _("lo register required")
793 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
794 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
795 #define BAD_BRANCH _("branch must be last instruction in IT block")
796 #define BAD_NOT_IT _("instruction not allowed in IT block")
797 #define BAD_FPU _("selected FPU does not support instruction")
798 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
799 #define BAD_IT_COND _("incorrect condition in IT block")
800 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
801 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
802 #define BAD_PC_ADDRESSING \
803 _("cannot use register index with PC-relative addressing")
804 #define BAD_PC_WRITEBACK \
805 _("cannot use writeback with PC-relative addressing")
806 #define BAD_RANGE _("branch out of range")
807 #define BAD_FP16 _("selected processor does not support fp16 instruction")
808 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
809 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
811 static struct hash_control
* arm_ops_hsh
;
812 static struct hash_control
* arm_cond_hsh
;
813 static struct hash_control
* arm_shift_hsh
;
814 static struct hash_control
* arm_psr_hsh
;
815 static struct hash_control
* arm_v7m_psr_hsh
;
816 static struct hash_control
* arm_reg_hsh
;
817 static struct hash_control
* arm_reloc_hsh
;
818 static struct hash_control
* arm_barrier_opt_hsh
;
820 /* Stuff needed to resolve the label ambiguity
829 symbolS
* last_label_seen
;
830 static int label_is_thumb_function_name
= FALSE
;
832 /* Literal pool structure. Held on a per-section
833 and per-sub-section basis. */
835 #define MAX_LITERAL_POOL_SIZE 1024
836 typedef struct literal_pool
838 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
839 unsigned int next_free_entry
;
845 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
847 struct literal_pool
* next
;
848 unsigned int alignment
;
851 /* Pointer to a linked list of literal pools. */
852 literal_pool
* list_of_pools
= NULL
;
854 typedef enum asmfunc_states
857 WAITING_ASMFUNC_NAME
,
861 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
864 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
866 static struct current_it now_it
;
870 now_it_compatible (int cond
)
872 return (cond
& ~1) == (now_it
.cc
& ~1);
876 conditional_insn (void)
878 return inst
.cond
!= COND_ALWAYS
;
881 static int in_it_block (void);
883 static int handle_it_state (void);
885 static void force_automatic_it_block_close (void);
887 static void it_fsm_post_encode (void);
889 #define set_it_insn_type(type) \
892 inst.it_insn_type = type; \
893 if (handle_it_state () == FAIL) \
898 #define set_it_insn_type_nonvoid(type, failret) \
901 inst.it_insn_type = type; \
902 if (handle_it_state () == FAIL) \
907 #define set_it_insn_type_last() \
910 if (inst.cond == COND_ALWAYS) \
911 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
913 set_it_insn_type (INSIDE_IT_LAST_INSN); \
919 /* This array holds the chars that always start a comment. If the
920 pre-processor is disabled, these aren't very useful. */
921 char arm_comment_chars
[] = "@";
923 /* This array holds the chars that only start a comment at the beginning of
924 a line. If the line seems to have the form '# 123 filename'
925 .line and .file directives will appear in the pre-processed output. */
926 /* Note that input_file.c hand checks for '#' at the beginning of the
927 first line of the input file. This is because the compiler outputs
928 #NO_APP at the beginning of its output. */
929 /* Also note that comments like this one will always work. */
930 const char line_comment_chars
[] = "#";
932 char arm_line_separator_chars
[] = ";";
934 /* Chars that can be used to separate mant
935 from exp in floating point numbers. */
936 const char EXP_CHARS
[] = "eE";
938 /* Chars that mean this number is a floating point constant. */
942 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
944 /* Prefix characters that indicate the start of an immediate
946 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
948 /* Separator character handling. */
950 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
953 skip_past_char (char ** str
, char c
)
955 /* PR gas/14987: Allow for whitespace before the expected character. */
956 skip_whitespace (*str
);
967 #define skip_past_comma(str) skip_past_char (str, ',')
969 /* Arithmetic expressions (possibly involving symbols). */
971 /* Return TRUE if anything in the expression is a bignum. */
974 walk_no_bignums (symbolS
* sp
)
976 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
979 if (symbol_get_value_expression (sp
)->X_add_symbol
)
981 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
982 || (symbol_get_value_expression (sp
)->X_op_symbol
983 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
989 static int in_my_get_expression
= 0;
991 /* Third argument to my_get_expression. */
992 #define GE_NO_PREFIX 0
993 #define GE_IMM_PREFIX 1
994 #define GE_OPT_PREFIX 2
995 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
996 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
997 #define GE_OPT_PREFIX_BIG 3
1000 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1005 /* In unified syntax, all prefixes are optional. */
1007 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1010 switch (prefix_mode
)
1012 case GE_NO_PREFIX
: break;
1014 if (!is_immediate_prefix (**str
))
1016 inst
.error
= _("immediate expression requires a # prefix");
1022 case GE_OPT_PREFIX_BIG
:
1023 if (is_immediate_prefix (**str
))
1029 memset (ep
, 0, sizeof (expressionS
));
1031 save_in
= input_line_pointer
;
1032 input_line_pointer
= *str
;
1033 in_my_get_expression
= 1;
1034 seg
= expression (ep
);
1035 in_my_get_expression
= 0;
1037 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1039 /* We found a bad or missing expression in md_operand(). */
1040 *str
= input_line_pointer
;
1041 input_line_pointer
= save_in
;
1042 if (inst
.error
== NULL
)
1043 inst
.error
= (ep
->X_op
== O_absent
1044 ? _("missing expression") :_("bad expression"));
1049 if (seg
!= absolute_section
1050 && seg
!= text_section
1051 && seg
!= data_section
1052 && seg
!= bss_section
1053 && seg
!= undefined_section
)
1055 inst
.error
= _("bad segment");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1064 /* Get rid of any bignums now, so that we don't generate an error for which
1065 we can't establish a line number later on. Big numbers are never valid
1066 in instructions, which is where this routine is always called. */
1067 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1068 && (ep
->X_op
== O_big
1069 || (ep
->X_add_symbol
1070 && (walk_no_bignums (ep
->X_add_symbol
)
1072 && walk_no_bignums (ep
->X_op_symbol
))))))
1074 inst
.error
= _("invalid constant");
1075 *str
= input_line_pointer
;
1076 input_line_pointer
= save_in
;
1080 *str
= input_line_pointer
;
1081 input_line_pointer
= save_in
;
1085 /* Turn a string in input_line_pointer into a floating point constant
1086 of type TYPE, and store the appropriate bytes in *LITP. The number
1087 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1088 returned, or NULL on OK.
1090 Note that fp constants aren't represent in the normal way on the ARM.
1091 In big endian mode, things are as expected. However, in little endian
1092 mode fp constants are big-endian word-wise, and little-endian byte-wise
1093 within the words. For example, (double) 1.1 in big endian mode is
1094 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1095 the byte sequence 99 99 f1 3f 9a 99 99 99.
1097 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1100 md_atof (int type
, char * litP
, int * sizeP
)
1103 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1135 return _("Unrecognized or unsupported floating point constant");
1138 t
= atof_ieee (input_line_pointer
, type
, words
);
1140 input_line_pointer
= t
;
1141 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1143 if (target_big_endian
)
1145 for (i
= 0; i
< prec
; i
++)
1147 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1148 litP
+= sizeof (LITTLENUM_TYPE
);
1153 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1154 for (i
= prec
- 1; i
>= 0; i
--)
1156 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1157 litP
+= sizeof (LITTLENUM_TYPE
);
1160 /* For a 4 byte float the order of elements in `words' is 1 0.
1161 For an 8 byte float the order is 1 0 3 2. */
1162 for (i
= 0; i
< prec
; i
+= 2)
1164 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1165 sizeof (LITTLENUM_TYPE
));
1166 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1167 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1168 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1175 /* We handle all bad expressions here, so that we can report the faulty
1176 instruction in the error message. */
1178 md_operand (expressionS
* exp
)
1180 if (in_my_get_expression
)
1181 exp
->X_op
= O_illegal
;
1184 /* Immediate values. */
1186 /* Generic immediate-value read function for use in directives.
1187 Accepts anything that 'expression' can fold to a constant.
1188 *val receives the number. */
1191 immediate_for_directive (int *val
)
1194 exp
.X_op
= O_illegal
;
1196 if (is_immediate_prefix (*input_line_pointer
))
1198 input_line_pointer
++;
1202 if (exp
.X_op
!= O_constant
)
1204 as_bad (_("expected #constant"));
1205 ignore_rest_of_line ();
1208 *val
= exp
.X_add_number
;
1213 /* Register parsing. */
1215 /* Generic register parser. CCP points to what should be the
1216 beginning of a register name. If it is indeed a valid register
1217 name, advance CCP over it and return the reg_entry structure;
1218 otherwise return NULL. Does not issue diagnostics. */
1220 static struct reg_entry
*
1221 arm_reg_parse_multi (char **ccp
)
1225 struct reg_entry
*reg
;
1227 skip_whitespace (start
);
1229 #ifdef REGISTER_PREFIX
1230 if (*start
!= REGISTER_PREFIX
)
1234 #ifdef OPTIONAL_REGISTER_PREFIX
1235 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1240 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1245 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1247 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1257 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1258 enum arm_reg_type type
)
1260 /* Alternative syntaxes are accepted for a few register classes. */
1267 /* Generic coprocessor register names are allowed for these. */
1268 if (reg
&& reg
->type
== REG_TYPE_CN
)
1273 /* For backward compatibility, a bare number is valid here. */
1275 unsigned long processor
= strtoul (start
, ccp
, 10);
1276 if (*ccp
!= start
&& processor
<= 15)
1281 case REG_TYPE_MMXWC
:
1282 /* WC includes WCG. ??? I'm not sure this is true for all
1283 instructions that take WC registers. */
1284 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1295 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1296 return value is the register number or FAIL. */
1299 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1302 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1305 /* Do not allow a scalar (reg+index) to parse as a register. */
1306 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1309 if (reg
&& reg
->type
== type
)
1312 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1319 /* Parse a Neon type specifier. *STR should point at the leading '.'
1320 character. Does no verification at this stage that the type fits the opcode
1327 Can all be legally parsed by this function.
1329 Fills in neon_type struct pointer with parsed information, and updates STR
1330 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1331 type, FAIL if not. */
1334 parse_neon_type (struct neon_type
*type
, char **str
)
1341 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1343 enum neon_el_type thistype
= NT_untyped
;
1344 unsigned thissize
= -1u;
1351 /* Just a size without an explicit type. */
1355 switch (TOLOWER (*ptr
))
1357 case 'i': thistype
= NT_integer
; break;
1358 case 'f': thistype
= NT_float
; break;
1359 case 'p': thistype
= NT_poly
; break;
1360 case 's': thistype
= NT_signed
; break;
1361 case 'u': thistype
= NT_unsigned
; break;
1363 thistype
= NT_float
;
1368 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1374 /* .f is an abbreviation for .f32. */
1375 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1380 thissize
= strtoul (ptr
, &ptr
, 10);
1382 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1385 as_bad (_("bad size %d in type specifier"), thissize
);
1393 type
->el
[type
->elems
].type
= thistype
;
1394 type
->el
[type
->elems
].size
= thissize
;
1399 /* Empty/missing type is not a successful parse. */
1400 if (type
->elems
== 0)
1408 /* Errors may be set multiple times during parsing or bit encoding
1409 (particularly in the Neon bits), but usually the earliest error which is set
1410 will be the most meaningful. Avoid overwriting it with later (cascading)
1411 errors by calling this function. */
1414 first_error (const char *err
)
1420 /* Parse a single type, e.g. ".s32", leading period included. */
1422 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1425 struct neon_type optype
;
1429 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1431 if (optype
.elems
== 1)
1432 *vectype
= optype
.el
[0];
1435 first_error (_("only one type should be specified for operand"));
1441 first_error (_("vector type expected"));
1453 /* Special meanings for indices (which have a range of 0-7), which will fit into
1456 #define NEON_ALL_LANES 15
1457 #define NEON_INTERLEAVE_LANES 14
1459 /* Parse either a register or a scalar, with an optional type. Return the
1460 register number, and optionally fill in the actual type of the register
1461 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1462 type/index information in *TYPEINFO. */
1465 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1466 enum arm_reg_type
*rtype
,
1467 struct neon_typed_alias
*typeinfo
)
1470 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1471 struct neon_typed_alias atype
;
1472 struct neon_type_el parsetype
;
1476 atype
.eltype
.type
= NT_invtype
;
1477 atype
.eltype
.size
= -1;
1479 /* Try alternate syntax for some types of register. Note these are mutually
1480 exclusive with the Neon syntax extensions. */
1483 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1491 /* Undo polymorphism when a set of register types may be accepted. */
1492 if ((type
== REG_TYPE_NDQ
1493 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1494 || (type
== REG_TYPE_VFSD
1495 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1496 || (type
== REG_TYPE_NSDQ
1497 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1498 || reg
->type
== REG_TYPE_NQ
))
1499 || (type
== REG_TYPE_MMXWC
1500 && (reg
->type
== REG_TYPE_MMXWCG
)))
1501 type
= (enum arm_reg_type
) reg
->type
;
1503 if (type
!= reg
->type
)
1509 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1511 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1513 first_error (_("can't redefine type for operand"));
1516 atype
.defined
|= NTA_HASTYPE
;
1517 atype
.eltype
= parsetype
;
1520 if (skip_past_char (&str
, '[') == SUCCESS
)
1522 if (type
!= REG_TYPE_VFD
)
1524 first_error (_("only D registers may be indexed"));
1528 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1530 first_error (_("can't change index for operand"));
1534 atype
.defined
|= NTA_HASINDEX
;
1536 if (skip_past_char (&str
, ']') == SUCCESS
)
1537 atype
.index
= NEON_ALL_LANES
;
1542 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1544 if (exp
.X_op
!= O_constant
)
1546 first_error (_("constant expression required"));
1550 if (skip_past_char (&str
, ']') == FAIL
)
1553 atype
.index
= exp
.X_add_number
;
1568 /* Like arm_reg_parse, but allow allow the following extra features:
1569 - If RTYPE is non-zero, return the (possibly restricted) type of the
1570 register (e.g. Neon double or quad reg when either has been requested).
1571 - If this is a Neon vector type with additional type information, fill
1572 in the struct pointed to by VECTYPE (if non-NULL).
1573 This function will fault on encountering a scalar. */
1576 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1577 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1579 struct neon_typed_alias atype
;
1581 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1586 /* Do not allow regname(... to parse as a register. */
1590 /* Do not allow a scalar (reg+index) to parse as a register. */
1591 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1593 first_error (_("register operand expected, but got scalar"));
1598 *vectype
= atype
.eltype
;
1605 #define NEON_SCALAR_REG(X) ((X) >> 4)
1606 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1608 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1609 have enough information to be able to do a good job bounds-checking. So, we
1610 just do easy checks here, and do further checks later. */
1613 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1617 struct neon_typed_alias atype
;
1619 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1621 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1624 if (atype
.index
== NEON_ALL_LANES
)
1626 first_error (_("scalar must have an index"));
1629 else if (atype
.index
>= 64 / elsize
)
1631 first_error (_("scalar index out of range"));
1636 *type
= atype
.eltype
;
1640 return reg
* 16 + atype
.index
;
1643 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1646 parse_reg_list (char ** strp
)
1648 char * str
= * strp
;
1652 /* We come back here if we get ranges concatenated by '+' or '|'. */
1655 skip_whitespace (str
);
1669 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1671 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1681 first_error (_("bad range in register list"));
1685 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1687 if (range
& (1 << i
))
1689 (_("Warning: duplicated register (r%d) in register list"),
1697 if (range
& (1 << reg
))
1698 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1700 else if (reg
<= cur_reg
)
1701 as_tsktsk (_("Warning: register range not in ascending order"));
1706 while (skip_past_comma (&str
) != FAIL
1707 || (in_range
= 1, *str
++ == '-'));
1710 if (skip_past_char (&str
, '}') == FAIL
)
1712 first_error (_("missing `}'"));
1720 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1723 if (exp
.X_op
== O_constant
)
1725 if (exp
.X_add_number
1726 != (exp
.X_add_number
& 0x0000ffff))
1728 inst
.error
= _("invalid register mask");
1732 if ((range
& exp
.X_add_number
) != 0)
1734 int regno
= range
& exp
.X_add_number
;
1737 regno
= (1 << regno
) - 1;
1739 (_("Warning: duplicated register (r%d) in register list"),
1743 range
|= exp
.X_add_number
;
1747 if (inst
.reloc
.type
!= 0)
1749 inst
.error
= _("expression too complex");
1753 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1754 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1755 inst
.reloc
.pc_rel
= 0;
1759 if (*str
== '|' || *str
== '+')
1765 while (another_range
);
1771 /* Types of registers in a list. */
1780 /* Parse a VFP register list. If the string is invalid return FAIL.
1781 Otherwise return the number of registers, and set PBASE to the first
1782 register. Parses registers of type ETYPE.
1783 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1784 - Q registers can be used to specify pairs of D registers
1785 - { } can be omitted from around a singleton register list
1786 FIXME: This is not implemented, as it would require backtracking in
1789 This could be done (the meaning isn't really ambiguous), but doesn't
1790 fit in well with the current parsing framework.
1791 - 32 D registers may be used (also true for VFPv3).
1792 FIXME: Types are ignored in these register lists, which is probably a
1796 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1801 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1805 unsigned long mask
= 0;
1808 if (skip_past_char (&str
, '{') == FAIL
)
1810 inst
.error
= _("expecting {");
1817 regtype
= REG_TYPE_VFS
;
1822 regtype
= REG_TYPE_VFD
;
1825 case REGLIST_NEON_D
:
1826 regtype
= REG_TYPE_NDQ
;
1830 if (etype
!= REGLIST_VFP_S
)
1832 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1833 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1837 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1840 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1847 base_reg
= max_regs
;
1851 int setmask
= 1, addregs
= 1;
1853 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1855 if (new_base
== FAIL
)
1857 first_error (_(reg_expected_msgs
[regtype
]));
1861 if (new_base
>= max_regs
)
1863 first_error (_("register out of range in list"));
1867 /* Note: a value of 2 * n is returned for the register Q<n>. */
1868 if (regtype
== REG_TYPE_NQ
)
1874 if (new_base
< base_reg
)
1875 base_reg
= new_base
;
1877 if (mask
& (setmask
<< new_base
))
1879 first_error (_("invalid register list"));
1883 if ((mask
>> new_base
) != 0 && ! warned
)
1885 as_tsktsk (_("register list not in ascending order"));
1889 mask
|= setmask
<< new_base
;
1892 if (*str
== '-') /* We have the start of a range expression */
1898 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1901 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1905 if (high_range
>= max_regs
)
1907 first_error (_("register out of range in list"));
1911 if (regtype
== REG_TYPE_NQ
)
1912 high_range
= high_range
+ 1;
1914 if (high_range
<= new_base
)
1916 inst
.error
= _("register range not in ascending order");
1920 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1922 if (mask
& (setmask
<< new_base
))
1924 inst
.error
= _("invalid register list");
1928 mask
|= setmask
<< new_base
;
1933 while (skip_past_comma (&str
) != FAIL
);
1937 /* Sanity check -- should have raised a parse error above. */
1938 if (count
== 0 || count
> max_regs
)
1943 /* Final test -- the registers must be consecutive. */
1945 for (i
= 0; i
< count
; i
++)
1947 if ((mask
& (1u << i
)) == 0)
1949 inst
.error
= _("non-contiguous register range");
1959 /* True if two alias types are the same. */
1962 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1970 if (a
->defined
!= b
->defined
)
1973 if ((a
->defined
& NTA_HASTYPE
) != 0
1974 && (a
->eltype
.type
!= b
->eltype
.type
1975 || a
->eltype
.size
!= b
->eltype
.size
))
1978 if ((a
->defined
& NTA_HASINDEX
) != 0
1979 && (a
->index
!= b
->index
))
1985 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1986 The base register is put in *PBASE.
1987 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1989 The register stride (minus one) is put in bit 4 of the return value.
1990 Bits [6:5] encode the list length (minus one).
1991 The type of the list elements is put in *ELTYPE, if non-NULL. */
1993 #define NEON_LANE(X) ((X) & 0xf)
1994 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1995 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1998 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1999 struct neon_type_el
*eltype
)
2006 int leading_brace
= 0;
2007 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2008 const char *const incr_error
= _("register stride must be 1 or 2");
2009 const char *const type_error
= _("mismatched element/structure types in list");
2010 struct neon_typed_alias firsttype
;
2011 firsttype
.defined
= 0;
2012 firsttype
.eltype
.type
= NT_invtype
;
2013 firsttype
.eltype
.size
= -1;
2014 firsttype
.index
= -1;
2016 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2021 struct neon_typed_alias atype
;
2022 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2026 first_error (_(reg_expected_msgs
[rtype
]));
2033 if (rtype
== REG_TYPE_NQ
)
2039 else if (reg_incr
== -1)
2041 reg_incr
= getreg
- base_reg
;
2042 if (reg_incr
< 1 || reg_incr
> 2)
2044 first_error (_(incr_error
));
2048 else if (getreg
!= base_reg
+ reg_incr
* count
)
2050 first_error (_(incr_error
));
2054 if (! neon_alias_types_same (&atype
, &firsttype
))
2056 first_error (_(type_error
));
2060 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2064 struct neon_typed_alias htype
;
2065 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2067 lane
= NEON_INTERLEAVE_LANES
;
2068 else if (lane
!= NEON_INTERLEAVE_LANES
)
2070 first_error (_(type_error
));
2075 else if (reg_incr
!= 1)
2077 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2081 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2084 first_error (_(reg_expected_msgs
[rtype
]));
2087 if (! neon_alias_types_same (&htype
, &firsttype
))
2089 first_error (_(type_error
));
2092 count
+= hireg
+ dregs
- getreg
;
2096 /* If we're using Q registers, we can't use [] or [n] syntax. */
2097 if (rtype
== REG_TYPE_NQ
)
2103 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2107 else if (lane
!= atype
.index
)
2109 first_error (_(type_error
));
2113 else if (lane
== -1)
2114 lane
= NEON_INTERLEAVE_LANES
;
2115 else if (lane
!= NEON_INTERLEAVE_LANES
)
2117 first_error (_(type_error
));
2122 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2124 /* No lane set by [x]. We must be interleaving structures. */
2126 lane
= NEON_INTERLEAVE_LANES
;
2129 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2130 || (count
> 1 && reg_incr
== -1))
2132 first_error (_("error parsing element/structure list"));
2136 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2138 first_error (_("expected }"));
2146 *eltype
= firsttype
.eltype
;
2151 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2154 /* Parse an explicit relocation suffix on an expression. This is
2155 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2156 arm_reloc_hsh contains no entries, so this function can only
2157 succeed if there is no () after the word. Returns -1 on error,
2158 BFD_RELOC_UNUSED if there wasn't any suffix. */
2161 parse_reloc (char **str
)
2163 struct reloc_entry
*r
;
2167 return BFD_RELOC_UNUSED
;
2172 while (*q
&& *q
!= ')' && *q
!= ',')
2177 if ((r
= (struct reloc_entry
*)
2178 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2185 /* Directives: register aliases. */
2187 static struct reg_entry
*
2188 insert_reg_alias (char *str
, unsigned number
, int type
)
2190 struct reg_entry
*new_reg
;
2193 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2195 if (new_reg
->builtin
)
2196 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2198 /* Only warn about a redefinition if it's not defined as the
2200 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2201 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2206 name
= xstrdup (str
);
2207 new_reg
= XNEW (struct reg_entry
);
2209 new_reg
->name
= name
;
2210 new_reg
->number
= number
;
2211 new_reg
->type
= type
;
2212 new_reg
->builtin
= FALSE
;
2213 new_reg
->neon
= NULL
;
2215 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2222 insert_neon_reg_alias (char *str
, int number
, int type
,
2223 struct neon_typed_alias
*atype
)
2225 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2229 first_error (_("attempt to redefine typed alias"));
2235 reg
->neon
= XNEW (struct neon_typed_alias
);
2236 *reg
->neon
= *atype
;
2240 /* Look for the .req directive. This is of the form:
2242 new_register_name .req existing_register_name
2244 If we find one, or if it looks sufficiently like one that we want to
2245 handle any error here, return TRUE. Otherwise return FALSE. */
2248 create_register_alias (char * newname
, char *p
)
2250 struct reg_entry
*old
;
2251 char *oldname
, *nbuf
;
2254 /* The input scrubber ensures that whitespace after the mnemonic is
2255 collapsed to single spaces. */
2257 if (strncmp (oldname
, " .req ", 6) != 0)
2261 if (*oldname
== '\0')
2264 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2267 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2271 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2272 the desired alias name, and p points to its end. If not, then
2273 the desired alias name is in the global original_case_string. */
2274 #ifdef TC_CASE_SENSITIVE
2277 newname
= original_case_string
;
2278 nlen
= strlen (newname
);
2281 nbuf
= xmemdup0 (newname
, nlen
);
2283 /* Create aliases under the new name as stated; an all-lowercase
2284 version of the new name; and an all-uppercase version of the new
2286 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2288 for (p
= nbuf
; *p
; p
++)
2291 if (strncmp (nbuf
, newname
, nlen
))
2293 /* If this attempt to create an additional alias fails, do not bother
2294 trying to create the all-lower case alias. We will fail and issue
2295 a second, duplicate error message. This situation arises when the
2296 programmer does something like:
2299 The second .req creates the "Foo" alias but then fails to create
2300 the artificial FOO alias because it has already been created by the
2302 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2309 for (p
= nbuf
; *p
; p
++)
2312 if (strncmp (nbuf
, newname
, nlen
))
2313 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2320 /* Create a Neon typed/indexed register alias using directives, e.g.:
2325 These typed registers can be used instead of the types specified after the
2326 Neon mnemonic, so long as all operands given have types. Types can also be
2327 specified directly, e.g.:
2328 vadd d0.s32, d1.s32, d2.s32 */
2331 create_neon_reg_alias (char *newname
, char *p
)
2333 enum arm_reg_type basetype
;
2334 struct reg_entry
*basereg
;
2335 struct reg_entry mybasereg
;
2336 struct neon_type ntype
;
2337 struct neon_typed_alias typeinfo
;
2338 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2341 typeinfo
.defined
= 0;
2342 typeinfo
.eltype
.type
= NT_invtype
;
2343 typeinfo
.eltype
.size
= -1;
2344 typeinfo
.index
= -1;
2348 if (strncmp (p
, " .dn ", 5) == 0)
2349 basetype
= REG_TYPE_VFD
;
2350 else if (strncmp (p
, " .qn ", 5) == 0)
2351 basetype
= REG_TYPE_NQ
;
2360 basereg
= arm_reg_parse_multi (&p
);
2362 if (basereg
&& basereg
->type
!= basetype
)
2364 as_bad (_("bad type for register"));
2368 if (basereg
== NULL
)
2371 /* Try parsing as an integer. */
2372 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2373 if (exp
.X_op
!= O_constant
)
2375 as_bad (_("expression must be constant"));
2378 basereg
= &mybasereg
;
2379 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2385 typeinfo
= *basereg
->neon
;
2387 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2389 /* We got a type. */
2390 if (typeinfo
.defined
& NTA_HASTYPE
)
2392 as_bad (_("can't redefine the type of a register alias"));
2396 typeinfo
.defined
|= NTA_HASTYPE
;
2397 if (ntype
.elems
!= 1)
2399 as_bad (_("you must specify a single type only"));
2402 typeinfo
.eltype
= ntype
.el
[0];
2405 if (skip_past_char (&p
, '[') == SUCCESS
)
2408 /* We got a scalar index. */
2410 if (typeinfo
.defined
& NTA_HASINDEX
)
2412 as_bad (_("can't redefine the index of a scalar alias"));
2416 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2418 if (exp
.X_op
!= O_constant
)
2420 as_bad (_("scalar index must be constant"));
2424 typeinfo
.defined
|= NTA_HASINDEX
;
2425 typeinfo
.index
= exp
.X_add_number
;
2427 if (skip_past_char (&p
, ']') == FAIL
)
2429 as_bad (_("expecting ]"));
2434 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2435 the desired alias name, and p points to its end. If not, then
2436 the desired alias name is in the global original_case_string. */
2437 #ifdef TC_CASE_SENSITIVE
2438 namelen
= nameend
- newname
;
2440 newname
= original_case_string
;
2441 namelen
= strlen (newname
);
2444 namebuf
= xmemdup0 (newname
, namelen
);
2446 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2447 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2449 /* Insert name in all uppercase. */
2450 for (p
= namebuf
; *p
; p
++)
2453 if (strncmp (namebuf
, newname
, namelen
))
2454 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2455 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2457 /* Insert name in all lowercase. */
2458 for (p
= namebuf
; *p
; p
++)
2461 if (strncmp (namebuf
, newname
, namelen
))
2462 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2463 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2469 /* Should never be called, as .req goes between the alias and the
2470 register name, not at the beginning of the line. */
2473 s_req (int a ATTRIBUTE_UNUSED
)
2475 as_bad (_("invalid syntax for .req directive"));
2479 s_dn (int a ATTRIBUTE_UNUSED
)
2481 as_bad (_("invalid syntax for .dn directive"));
2485 s_qn (int a ATTRIBUTE_UNUSED
)
2487 as_bad (_("invalid syntax for .qn directive"));
2490 /* The .unreq directive deletes an alias which was previously defined
2491 by .req. For example:
2497 s_unreq (int a ATTRIBUTE_UNUSED
)
2502 name
= input_line_pointer
;
2504 while (*input_line_pointer
!= 0
2505 && *input_line_pointer
!= ' '
2506 && *input_line_pointer
!= '\n')
2507 ++input_line_pointer
;
2509 saved_char
= *input_line_pointer
;
2510 *input_line_pointer
= 0;
2513 as_bad (_("invalid syntax for .unreq directive"));
2516 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2520 as_bad (_("unknown register alias '%s'"), name
);
2521 else if (reg
->builtin
)
2522 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2529 hash_delete (arm_reg_hsh
, name
, FALSE
);
2530 free ((char *) reg
->name
);
2535 /* Also locate the all upper case and all lower case versions.
2536 Do not complain if we cannot find one or the other as it
2537 was probably deleted above. */
2539 nbuf
= strdup (name
);
2540 for (p
= nbuf
; *p
; p
++)
2542 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2545 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2546 free ((char *) reg
->name
);
2552 for (p
= nbuf
; *p
; p
++)
2554 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2557 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2558 free ((char *) reg
->name
);
2568 *input_line_pointer
= saved_char
;
2569 demand_empty_rest_of_line ();
2572 /* Directives: Instruction set selection. */
2575 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2576 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2577 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2578 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2580 /* Create a new mapping symbol for the transition to STATE. */
2583 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2586 const char * symname
;
2593 type
= BSF_NO_FLAGS
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2607 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2608 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2613 THUMB_SET_FUNC (symbolP
, 0);
2614 ARM_SET_THUMB (symbolP
, 0);
2615 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2619 THUMB_SET_FUNC (symbolP
, 1);
2620 ARM_SET_THUMB (symbolP
, 1);
2621 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2629 /* Save the mapping symbols for future reference. Also check that
2630 we do not place two mapping symbols at the same offset within a
2631 frag. We'll handle overlap between frags in
2632 check_mapping_symbols.
2634 If .fill or other data filling directive generates zero sized data,
2635 the mapping symbol for the following code will have the same value
2636 as the one generated for the data filling directive. In this case,
2637 we replace the old symbol with the new one at the same address. */
2640 if (frag
->tc_frag_data
.first_map
!= NULL
)
2642 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2643 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2645 frag
->tc_frag_data
.first_map
= symbolP
;
2647 if (frag
->tc_frag_data
.last_map
!= NULL
)
2649 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2650 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2651 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2653 frag
->tc_frag_data
.last_map
= symbolP
;
2656 /* We must sometimes convert a region marked as code to data during
2657 code alignment, if an odd number of bytes have to be padded. The
2658 code mapping symbol is pushed to an aligned address. */
2661 insert_data_mapping_symbol (enum mstate state
,
2662 valueT value
, fragS
*frag
, offsetT bytes
)
2664 /* If there was already a mapping symbol, remove it. */
2665 if (frag
->tc_frag_data
.last_map
!= NULL
2666 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2668 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2672 know (frag
->tc_frag_data
.first_map
== symp
);
2673 frag
->tc_frag_data
.first_map
= NULL
;
2675 frag
->tc_frag_data
.last_map
= NULL
;
2676 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2679 make_mapping_symbol (MAP_DATA
, value
, frag
);
2680 make_mapping_symbol (state
, value
+ bytes
, frag
);
2683 static void mapping_state_2 (enum mstate state
, int max_chars
);
2685 /* Set the mapping state to STATE. Only call this when about to
2686 emit some STATE bytes to the file. */
2688 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2690 mapping_state (enum mstate state
)
2692 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2694 if (mapstate
== state
)
2695 /* The mapping symbol has already been emitted.
2696 There is nothing else to do. */
2699 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2701 All ARM instructions require 4-byte alignment.
2702 (Almost) all Thumb instructions require 2-byte alignment.
2704 When emitting instructions into any section, mark the section
2707 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2708 but themselves require 2-byte alignment; this applies to some
2709 PC- relative forms. However, these cases will invovle implicit
2710 literal pool generation or an explicit .align >=2, both of
2711 which will cause the section to me marked with sufficient
2712 alignment. Thus, we don't handle those cases here. */
2713 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2715 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2716 /* This case will be evaluated later. */
2719 mapping_state_2 (state
, 0);
2722 /* Same as mapping_state, but MAX_CHARS bytes have already been
2723 allocated. Put the mapping symbol that far back. */
2726 mapping_state_2 (enum mstate state
, int max_chars
)
2728 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2730 if (!SEG_NORMAL (now_seg
))
2733 if (mapstate
== state
)
2734 /* The mapping symbol has already been emitted.
2735 There is nothing else to do. */
2738 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2739 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2741 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2742 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2745 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2748 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2749 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2753 #define mapping_state(x) ((void)0)
2754 #define mapping_state_2(x, y) ((void)0)
2757 /* Find the real, Thumb encoded start of a Thumb function. */
2761 find_real_start (symbolS
* symbolP
)
2764 const char * name
= S_GET_NAME (symbolP
);
2765 symbolS
* new_target
;
2767 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2768 #define STUB_NAME ".real_start_of"
2773 /* The compiler may generate BL instructions to local labels because
2774 it needs to perform a branch to a far away location. These labels
2775 do not have a corresponding ".real_start_of" label. We check
2776 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2777 the ".real_start_of" convention for nonlocal branches. */
2778 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2781 real_start
= concat (STUB_NAME
, name
, NULL
);
2782 new_target
= symbol_find (real_start
);
2785 if (new_target
== NULL
)
2787 as_warn (_("Failed to find real start of function: %s\n"), name
);
2788 new_target
= symbolP
;
2796 opcode_select (int width
)
2803 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2804 as_bad (_("selected processor does not support THUMB opcodes"));
2807 /* No need to force the alignment, since we will have been
2808 coming from ARM mode, which is word-aligned. */
2809 record_alignment (now_seg
, 1);
2816 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2817 as_bad (_("selected processor does not support ARM opcodes"));
2822 frag_align (2, 0, 0);
2824 record_alignment (now_seg
, 1);
2829 as_bad (_("invalid instruction size selected (%d)"), width
);
2834 s_arm (int ignore ATTRIBUTE_UNUSED
)
2837 demand_empty_rest_of_line ();
2841 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2844 demand_empty_rest_of_line ();
2848 s_code (int unused ATTRIBUTE_UNUSED
)
2852 temp
= get_absolute_expression ();
2857 opcode_select (temp
);
2861 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2866 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2868 /* If we are not already in thumb mode go into it, EVEN if
2869 the target processor does not support thumb instructions.
2870 This is used by gcc/config/arm/lib1funcs.asm for example
2871 to compile interworking support functions even if the
2872 target processor should not support interworking. */
2876 record_alignment (now_seg
, 1);
2879 demand_empty_rest_of_line ();
2883 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2887 /* The following label is the name/address of the start of a Thumb function.
2888 We need to know this for the interworking support. */
2889 label_is_thumb_function_name
= TRUE
;
2892 /* Perform a .set directive, but also mark the alias as
2893 being a thumb function. */
2896 s_thumb_set (int equiv
)
2898 /* XXX the following is a duplicate of the code for s_set() in read.c
2899 We cannot just call that code as we need to get at the symbol that
2906 /* Especial apologies for the random logic:
2907 This just grew, and could be parsed much more simply!
2909 delim
= get_symbol_name (& name
);
2910 end_name
= input_line_pointer
;
2911 (void) restore_line_pointer (delim
);
2913 if (*input_line_pointer
!= ',')
2916 as_bad (_("expected comma after name \"%s\""), name
);
2918 ignore_rest_of_line ();
2922 input_line_pointer
++;
2925 if (name
[0] == '.' && name
[1] == '\0')
2927 /* XXX - this should not happen to .thumb_set. */
2931 if ((symbolP
= symbol_find (name
)) == NULL
2932 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2935 /* When doing symbol listings, play games with dummy fragments living
2936 outside the normal fragment chain to record the file and line info
2938 if (listing
& LISTING_SYMBOLS
)
2940 extern struct list_info_struct
* listing_tail
;
2941 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2943 memset (dummy_frag
, 0, sizeof (fragS
));
2944 dummy_frag
->fr_type
= rs_fill
;
2945 dummy_frag
->line
= listing_tail
;
2946 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2947 dummy_frag
->fr_symbol
= symbolP
;
2951 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2954 /* "set" symbols are local unless otherwise specified. */
2955 SF_SET_LOCAL (symbolP
);
2956 #endif /* OBJ_COFF */
2957 } /* Make a new symbol. */
2959 symbol_table_insert (symbolP
);
2964 && S_IS_DEFINED (symbolP
)
2965 && S_GET_SEGMENT (symbolP
) != reg_section
)
2966 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2968 pseudo_set (symbolP
);
2970 demand_empty_rest_of_line ();
2972 /* XXX Now we come to the Thumb specific bit of code. */
2974 THUMB_SET_FUNC (symbolP
, 1);
2975 ARM_SET_THUMB (symbolP
, 1);
2976 #if defined OBJ_ELF || defined OBJ_COFF
2977 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2981 /* Directives: Mode selection. */
2983 /* .syntax [unified|divided] - choose the new unified syntax
2984 (same for Arm and Thumb encoding, modulo slight differences in what
2985 can be represented) or the old divergent syntax for each mode. */
2987 s_syntax (int unused ATTRIBUTE_UNUSED
)
2991 delim
= get_symbol_name (& name
);
2993 if (!strcasecmp (name
, "unified"))
2994 unified_syntax
= TRUE
;
2995 else if (!strcasecmp (name
, "divided"))
2996 unified_syntax
= FALSE
;
2999 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3002 (void) restore_line_pointer (delim
);
3003 demand_empty_rest_of_line ();
3006 /* Directives: sectioning and alignment. */
3009 s_bss (int ignore ATTRIBUTE_UNUSED
)
3011 /* We don't support putting frags in the BSS segment, we fake it by
3012 marking in_bss, then looking at s_skip for clues. */
3013 subseg_set (bss_section
, 0);
3014 demand_empty_rest_of_line ();
3016 #ifdef md_elf_section_change_hook
3017 md_elf_section_change_hook ();
3022 s_even (int ignore ATTRIBUTE_UNUSED
)
3024 /* Never make frag if expect extra pass. */
3026 frag_align (1, 0, 0);
3028 record_alignment (now_seg
, 1);
3030 demand_empty_rest_of_line ();
3033 /* Directives: CodeComposer Studio. */
3035 /* .ref (for CodeComposer Studio syntax only). */
3037 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3039 if (codecomposer_syntax
)
3040 ignore_rest_of_line ();
3042 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3045 /* If name is not NULL, then it is used for marking the beginning of a
3046 function, wherease if it is NULL then it means the function end. */
3048 asmfunc_debug (const char * name
)
3050 static const char * last_name
= NULL
;
3054 gas_assert (last_name
== NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_func (name
, name
);
3062 gas_assert (last_name
!= NULL
);
3064 if (debug_type
== DEBUG_STABS
)
3065 stabs_generate_asm_endfunc (last_name
, last_name
);
3072 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3074 if (codecomposer_syntax
)
3076 switch (asmfunc_state
)
3078 case OUTSIDE_ASMFUNC
:
3079 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3082 case WAITING_ASMFUNC_NAME
:
3083 as_bad (_(".asmfunc repeated."));
3086 case WAITING_ENDASMFUNC
:
3087 as_bad (_(".asmfunc without function."));
3090 demand_empty_rest_of_line ();
3093 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3097 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3099 if (codecomposer_syntax
)
3101 switch (asmfunc_state
)
3103 case OUTSIDE_ASMFUNC
:
3104 as_bad (_(".endasmfunc without a .asmfunc."));
3107 case WAITING_ASMFUNC_NAME
:
3108 as_bad (_(".endasmfunc without function."));
3111 case WAITING_ENDASMFUNC
:
3112 asmfunc_state
= OUTSIDE_ASMFUNC
;
3113 asmfunc_debug (NULL
);
3116 demand_empty_rest_of_line ();
3119 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3123 s_ccs_def (int name
)
3125 if (codecomposer_syntax
)
3128 as_bad (_(".def pseudo-op only available with -mccs flag."));
3131 /* Directives: Literal pools. */
3133 static literal_pool
*
3134 find_literal_pool (void)
3136 literal_pool
* pool
;
3138 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3140 if (pool
->section
== now_seg
3141 && pool
->sub_section
== now_subseg
)
3148 static literal_pool
*
3149 find_or_make_literal_pool (void)
3151 /* Next literal pool ID number. */
3152 static unsigned int latest_pool_num
= 1;
3153 literal_pool
* pool
;
3155 pool
= find_literal_pool ();
3159 /* Create a new pool. */
3160 pool
= XNEW (literal_pool
);
3164 pool
->next_free_entry
= 0;
3165 pool
->section
= now_seg
;
3166 pool
->sub_section
= now_subseg
;
3167 pool
->next
= list_of_pools
;
3168 pool
->symbol
= NULL
;
3169 pool
->alignment
= 2;
3171 /* Add it to the list. */
3172 list_of_pools
= pool
;
3175 /* New pools, and emptied pools, will have a NULL symbol. */
3176 if (pool
->symbol
== NULL
)
3178 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3179 (valueT
) 0, &zero_address_frag
);
3180 pool
->id
= latest_pool_num
++;
3187 /* Add the literal in the global 'inst'
3188 structure to the relevant literal pool. */
3191 add_to_lit_pool (unsigned int nbytes
)
3193 #define PADDING_SLOT 0x1
3194 #define LIT_ENTRY_SIZE_MASK 0xFF
3195 literal_pool
* pool
;
3196 unsigned int entry
, pool_size
= 0;
3197 bfd_boolean padding_slot_p
= FALSE
;
3203 imm1
= inst
.operands
[1].imm
;
3204 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3205 : inst
.reloc
.exp
.X_unsigned
? 0
3206 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3207 if (target_big_endian
)
3210 imm2
= inst
.operands
[1].imm
;
3214 pool
= find_or_make_literal_pool ();
3216 /* Check if this literal value is already in the pool. */
3217 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3221 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3222 && (inst
.reloc
.exp
.X_op
== O_constant
)
3223 && (pool
->literals
[entry
].X_add_number
3224 == inst
.reloc
.exp
.X_add_number
)
3225 && (pool
->literals
[entry
].X_md
== nbytes
)
3226 && (pool
->literals
[entry
].X_unsigned
3227 == inst
.reloc
.exp
.X_unsigned
))
3230 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3231 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3232 && (pool
->literals
[entry
].X_add_number
3233 == inst
.reloc
.exp
.X_add_number
)
3234 && (pool
->literals
[entry
].X_add_symbol
3235 == inst
.reloc
.exp
.X_add_symbol
)
3236 && (pool
->literals
[entry
].X_op_symbol
3237 == inst
.reloc
.exp
.X_op_symbol
)
3238 && (pool
->literals
[entry
].X_md
== nbytes
))
3241 else if ((nbytes
== 8)
3242 && !(pool_size
& 0x7)
3243 && ((entry
+ 1) != pool
->next_free_entry
)
3244 && (pool
->literals
[entry
].X_op
== O_constant
)
3245 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3246 && (pool
->literals
[entry
].X_unsigned
3247 == inst
.reloc
.exp
.X_unsigned
)
3248 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3249 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3250 && (pool
->literals
[entry
+ 1].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
))
3254 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3255 if (padding_slot_p
&& (nbytes
== 4))
3261 /* Do we need to create a new entry? */
3262 if (entry
== pool
->next_free_entry
)
3264 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3266 inst
.error
= _("literal pool overflow");
3272 /* For 8-byte entries, we align to an 8-byte boundary,
3273 and split it into two 4-byte entries, because on 32-bit
3274 host, 8-byte constants are treated as big num, thus
3275 saved in "generic_bignum" which will be overwritten
3276 by later assignments.
3278 We also need to make sure there is enough space for
3281 We also check to make sure the literal operand is a
3283 if (!(inst
.reloc
.exp
.X_op
== O_constant
3284 || inst
.reloc
.exp
.X_op
== O_big
))
3286 inst
.error
= _("invalid type for literal pool");
3289 else if (pool_size
& 0x7)
3291 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3293 inst
.error
= _("literal pool overflow");
3297 pool
->literals
[entry
] = inst
.reloc
.exp
;
3298 pool
->literals
[entry
].X_op
= O_constant
;
3299 pool
->literals
[entry
].X_add_number
= 0;
3300 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3301 pool
->next_free_entry
+= 1;
3304 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3306 inst
.error
= _("literal pool overflow");
3310 pool
->literals
[entry
] = inst
.reloc
.exp
;
3311 pool
->literals
[entry
].X_op
= O_constant
;
3312 pool
->literals
[entry
].X_add_number
= imm1
;
3313 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3314 pool
->literals
[entry
++].X_md
= 4;
3315 pool
->literals
[entry
] = inst
.reloc
.exp
;
3316 pool
->literals
[entry
].X_op
= O_constant
;
3317 pool
->literals
[entry
].X_add_number
= imm2
;
3318 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3319 pool
->literals
[entry
].X_md
= 4;
3320 pool
->alignment
= 3;
3321 pool
->next_free_entry
+= 1;
3325 pool
->literals
[entry
] = inst
.reloc
.exp
;
3326 pool
->literals
[entry
].X_md
= 4;
3330 /* PR ld/12974: Record the location of the first source line to reference
3331 this entry in the literal pool. If it turns out during linking that the
3332 symbol does not exist we will be able to give an accurate line number for
3333 the (first use of the) missing reference. */
3334 if (debug_type
== DEBUG_DWARF2
)
3335 dwarf2_where (pool
->locs
+ entry
);
3337 pool
->next_free_entry
+= 1;
3339 else if (padding_slot_p
)
3341 pool
->literals
[entry
] = inst
.reloc
.exp
;
3342 pool
->literals
[entry
].X_md
= nbytes
;
3345 inst
.reloc
.exp
.X_op
= O_symbol
;
3346 inst
.reloc
.exp
.X_add_number
= pool_size
;
3347 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3353 tc_start_label_without_colon (void)
3355 bfd_boolean ret
= TRUE
;
3357 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3359 const char *label
= input_line_pointer
;
3361 while (!is_end_of_line
[(int) label
[-1]])
3366 as_bad (_("Invalid label '%s'"), label
);
3370 asmfunc_debug (label
);
3372 asmfunc_state
= WAITING_ENDASMFUNC
;
3378 /* Can't use symbol_new here, so have to create a symbol and then at
3379 a later date assign it a value. Thats what these functions do. */
3382 symbol_locate (symbolS
* symbolP
,
3383 const char * name
, /* It is copied, the caller can modify. */
3384 segT segment
, /* Segment identifier (SEG_<something>). */
3385 valueT valu
, /* Symbol value. */
3386 fragS
* frag
) /* Associated fragment. */
3389 char * preserved_copy_of_name
;
3391 name_length
= strlen (name
) + 1; /* +1 for \0. */
3392 obstack_grow (¬es
, name
, name_length
);
3393 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3395 #ifdef tc_canonicalize_symbol_name
3396 preserved_copy_of_name
=
3397 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3400 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3402 S_SET_SEGMENT (symbolP
, segment
);
3403 S_SET_VALUE (symbolP
, valu
);
3404 symbol_clear_list_pointers (symbolP
);
3406 symbol_set_frag (symbolP
, frag
);
3408 /* Link to end of symbol chain. */
3410 extern int symbol_table_frozen
;
3412 if (symbol_table_frozen
)
3416 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3418 obj_symbol_new_hook (symbolP
);
3420 #ifdef tc_symbol_new_hook
3421 tc_symbol_new_hook (symbolP
);
3425 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3426 #endif /* DEBUG_SYMS */
3430 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3433 literal_pool
* pool
;
3436 pool
= find_literal_pool ();
3438 || pool
->symbol
== NULL
3439 || pool
->next_free_entry
== 0)
3442 /* Align pool as you have word accesses.
3443 Only make a frag if we have to. */
3445 frag_align (pool
->alignment
, 0, 0);
3447 record_alignment (now_seg
, 2);
3450 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3451 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3453 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3455 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3456 (valueT
) frag_now_fix (), frag_now
);
3457 symbol_table_insert (pool
->symbol
);
3459 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3461 #if defined OBJ_COFF || defined OBJ_ELF
3462 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3465 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if (debug_type
== DEBUG_DWARF2
)
3469 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3471 /* First output the expression in the instruction to the pool. */
3472 emit_expr (&(pool
->literals
[entry
]),
3473 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3476 /* Mark the pool as empty. */
3477 pool
->next_free_entry
= 0;
3478 pool
->symbol
= NULL
;
3482 /* Forward declarations for functions below, in the MD interface
3484 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3485 static valueT
create_unwind_entry (int);
3486 static void start_unwind_section (const segT
, int);
3487 static void add_unwind_opcode (valueT
, int);
3488 static void flush_pending_unwind (void);
3490 /* Directives: Data. */
3493 s_arm_elf_cons (int nbytes
)
3497 #ifdef md_flush_pending_output
3498 md_flush_pending_output ();
3501 if (is_it_end_of_statement ())
3503 demand_empty_rest_of_line ();
3507 #ifdef md_cons_align
3508 md_cons_align (nbytes
);
3511 mapping_state (MAP_DATA
);
3515 char *base
= input_line_pointer
;
3519 if (exp
.X_op
!= O_symbol
)
3520 emit_expr (&exp
, (unsigned int) nbytes
);
3523 char *before_reloc
= input_line_pointer
;
3524 reloc
= parse_reloc (&input_line_pointer
);
3527 as_bad (_("unrecognized relocation suffix"));
3528 ignore_rest_of_line ();
3531 else if (reloc
== BFD_RELOC_UNUSED
)
3532 emit_expr (&exp
, (unsigned int) nbytes
);
3535 reloc_howto_type
*howto
= (reloc_howto_type
*)
3536 bfd_reloc_type_lookup (stdoutput
,
3537 (bfd_reloc_code_real_type
) reloc
);
3538 int size
= bfd_get_reloc_size (howto
);
3540 if (reloc
== BFD_RELOC_ARM_PLT32
)
3542 as_bad (_("(plt) is only valid on branch targets"));
3543 reloc
= BFD_RELOC_UNUSED
;
3548 as_bad (_("%s relocations do not fit in %d bytes"),
3549 howto
->name
, nbytes
);
3552 /* We've parsed an expression stopping at O_symbol.
3553 But there may be more expression left now that we
3554 have parsed the relocation marker. Parse it again.
3555 XXX Surely there is a cleaner way to do this. */
3556 char *p
= input_line_pointer
;
3558 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3560 memcpy (save_buf
, base
, input_line_pointer
- base
);
3561 memmove (base
+ (input_line_pointer
- before_reloc
),
3562 base
, before_reloc
- base
);
3564 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3566 memcpy (base
, save_buf
, p
- base
);
3568 offset
= nbytes
- size
;
3569 p
= frag_more (nbytes
);
3570 memset (p
, 0, nbytes
);
3571 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3572 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3578 while (*input_line_pointer
++ == ',');
3580 /* Put terminator back into stream. */
3581 input_line_pointer
--;
3582 demand_empty_rest_of_line ();
3585 /* Emit an expression containing a 32-bit thumb instruction.
3586 Implementation based on put_thumb32_insn. */
3589 emit_thumb32_expr (expressionS
* exp
)
3591 expressionS exp_high
= *exp
;
3593 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3594 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3595 exp
->X_add_number
&= 0xffff;
3596 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3599 /* Guess the instruction size based on the opcode. */
3602 thumb_insn_size (int opcode
)
3604 if ((unsigned int) opcode
< 0xe800u
)
3606 else if ((unsigned int) opcode
>= 0xe8000000u
)
3613 emit_insn (expressionS
*exp
, int nbytes
)
3617 if (exp
->X_op
== O_constant
)
3622 size
= thumb_insn_size (exp
->X_add_number
);
3626 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3628 as_bad (_(".inst.n operand too big. "\
3629 "Use .inst.w instead"));
3634 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3635 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3637 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3639 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3640 emit_thumb32_expr (exp
);
3642 emit_expr (exp
, (unsigned int) size
);
3644 it_fsm_post_encode ();
3648 as_bad (_("cannot determine Thumb instruction size. " \
3649 "Use .inst.n/.inst.w instead"));
3652 as_bad (_("constant expression required"));
3657 /* Like s_arm_elf_cons but do not use md_cons_align and
3658 set the mapping state to MAP_ARM/MAP_THUMB. */
3661 s_arm_elf_inst (int nbytes
)
3663 if (is_it_end_of_statement ())
3665 demand_empty_rest_of_line ();
3669 /* Calling mapping_state () here will not change ARM/THUMB,
3670 but will ensure not to be in DATA state. */
3673 mapping_state (MAP_THUMB
);
3678 as_bad (_("width suffixes are invalid in ARM mode"));
3679 ignore_rest_of_line ();
3685 mapping_state (MAP_ARM
);
3694 if (! emit_insn (& exp
, nbytes
))
3696 ignore_rest_of_line ();
3700 while (*input_line_pointer
++ == ',');
3702 /* Put terminator back into stream. */
3703 input_line_pointer
--;
3704 demand_empty_rest_of_line ();
3707 /* Parse a .rel31 directive. */
3710 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3717 if (*input_line_pointer
== '1')
3718 highbit
= 0x80000000;
3719 else if (*input_line_pointer
!= '0')
3720 as_bad (_("expected 0 or 1"));
3722 input_line_pointer
++;
3723 if (*input_line_pointer
!= ',')
3724 as_bad (_("missing comma"));
3725 input_line_pointer
++;
3727 #ifdef md_flush_pending_output
3728 md_flush_pending_output ();
3731 #ifdef md_cons_align
3735 mapping_state (MAP_DATA
);
3740 md_number_to_chars (p
, highbit
, 4);
3741 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3742 BFD_RELOC_ARM_PREL31
);
3744 demand_empty_rest_of_line ();
3747 /* Directives: AEABI stack-unwind tables. */
3749 /* Parse an unwind_fnstart directive. Simply records the current location. */
3752 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3754 demand_empty_rest_of_line ();
3755 if (unwind
.proc_start
)
3757 as_bad (_("duplicate .fnstart directive"));
3761 /* Mark the start of the function. */
3762 unwind
.proc_start
= expr_build_dot ();
3764 /* Reset the rest of the unwind info. */
3765 unwind
.opcode_count
= 0;
3766 unwind
.table_entry
= NULL
;
3767 unwind
.personality_routine
= NULL
;
3768 unwind
.personality_index
= -1;
3769 unwind
.frame_size
= 0;
3770 unwind
.fp_offset
= 0;
3771 unwind
.fp_reg
= REG_SP
;
3773 unwind
.sp_restored
= 0;
3777 /* Parse a handlerdata directive. Creates the exception handling table entry
3778 for the function. */
3781 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3783 demand_empty_rest_of_line ();
3784 if (!unwind
.proc_start
)
3785 as_bad (MISSING_FNSTART
);
3787 if (unwind
.table_entry
)
3788 as_bad (_("duplicate .handlerdata directive"));
3790 create_unwind_entry (1);
3793 /* Parse an unwind_fnend directive. Generates the index table entry. */
3796 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3801 unsigned int marked_pr_dependency
;
3803 demand_empty_rest_of_line ();
3805 if (!unwind
.proc_start
)
3807 as_bad (_(".fnend directive without .fnstart"));
3811 /* Add eh table entry. */
3812 if (unwind
.table_entry
== NULL
)
3813 val
= create_unwind_entry (0);
3817 /* Add index table entry. This is two words. */
3818 start_unwind_section (unwind
.saved_seg
, 1);
3819 frag_align (2, 0, 0);
3820 record_alignment (now_seg
, 2);
3822 ptr
= frag_more (8);
3824 where
= frag_now_fix () - 8;
3826 /* Self relative offset of the function start. */
3827 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3828 BFD_RELOC_ARM_PREL31
);
3830 /* Indicate dependency on EHABI-defined personality routines to the
3831 linker, if it hasn't been done already. */
3832 marked_pr_dependency
3833 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3834 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3835 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3837 static const char *const name
[] =
3839 "__aeabi_unwind_cpp_pr0",
3840 "__aeabi_unwind_cpp_pr1",
3841 "__aeabi_unwind_cpp_pr2"
3843 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3844 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3845 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3846 |= 1 << unwind
.personality_index
;
3850 /* Inline exception table entry. */
3851 md_number_to_chars (ptr
+ 4, val
, 4);
3853 /* Self relative offset of the table entry. */
3854 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3855 BFD_RELOC_ARM_PREL31
);
3857 /* Restore the original section. */
3858 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3860 unwind
.proc_start
= NULL
;
3864 /* Parse an unwind_cantunwind directive. */
3867 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3869 demand_empty_rest_of_line ();
3870 if (!unwind
.proc_start
)
3871 as_bad (MISSING_FNSTART
);
3873 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3874 as_bad (_("personality routine specified for cantunwind frame"));
3876 unwind
.personality_index
= -2;
3880 /* Parse a personalityindex directive. */
3883 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3887 if (!unwind
.proc_start
)
3888 as_bad (MISSING_FNSTART
);
3890 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3891 as_bad (_("duplicate .personalityindex directive"));
3895 if (exp
.X_op
!= O_constant
3896 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3898 as_bad (_("bad personality routine number"));
3899 ignore_rest_of_line ();
3903 unwind
.personality_index
= exp
.X_add_number
;
3905 demand_empty_rest_of_line ();
3909 /* Parse a personality directive. */
3912 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3916 if (!unwind
.proc_start
)
3917 as_bad (MISSING_FNSTART
);
3919 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3920 as_bad (_("duplicate .personality directive"));
3922 c
= get_symbol_name (& name
);
3923 p
= input_line_pointer
;
3925 ++ input_line_pointer
;
3926 unwind
.personality_routine
= symbol_find_or_make (name
);
3928 demand_empty_rest_of_line ();
3932 /* Parse a directive saving core registers. */
3935 s_arm_unwind_save_core (void)
3941 range
= parse_reg_list (&input_line_pointer
);
3944 as_bad (_("expected register list"));
3945 ignore_rest_of_line ();
3949 demand_empty_rest_of_line ();
3951 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3952 into .unwind_save {..., sp...}. We aren't bothered about the value of
3953 ip because it is clobbered by calls. */
3954 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3955 && (range
& 0x3000) == 0x1000)
3957 unwind
.opcode_count
--;
3958 unwind
.sp_restored
= 0;
3959 range
= (range
| 0x2000) & ~0x1000;
3960 unwind
.pending_offset
= 0;
3966 /* See if we can use the short opcodes. These pop a block of up to 8
3967 registers starting with r4, plus maybe r14. */
3968 for (n
= 0; n
< 8; n
++)
3970 /* Break at the first non-saved register. */
3971 if ((range
& (1 << (n
+ 4))) == 0)
3974 /* See if there are any other bits set. */
3975 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3977 /* Use the long form. */
3978 op
= 0x8000 | ((range
>> 4) & 0xfff);
3979 add_unwind_opcode (op
, 2);
3983 /* Use the short form. */
3985 op
= 0xa8; /* Pop r14. */
3987 op
= 0xa0; /* Do not pop r14. */
3989 add_unwind_opcode (op
, 1);
3996 op
= 0xb100 | (range
& 0xf);
3997 add_unwind_opcode (op
, 2);
4000 /* Record the number of bytes pushed. */
4001 for (n
= 0; n
< 16; n
++)
4003 if (range
& (1 << n
))
4004 unwind
.frame_size
+= 4;
4009 /* Parse a directive saving FPA registers. */
4012 s_arm_unwind_save_fpa (int reg
)
4018 /* Get Number of registers to transfer. */
4019 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4022 exp
.X_op
= O_illegal
;
4024 if (exp
.X_op
!= O_constant
)
4026 as_bad (_("expected , <constant>"));
4027 ignore_rest_of_line ();
4031 num_regs
= exp
.X_add_number
;
4033 if (num_regs
< 1 || num_regs
> 4)
4035 as_bad (_("number of registers must be in the range [1:4]"));
4036 ignore_rest_of_line ();
4040 demand_empty_rest_of_line ();
4045 op
= 0xb4 | (num_regs
- 1);
4046 add_unwind_opcode (op
, 1);
4051 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4052 add_unwind_opcode (op
, 2);
4054 unwind
.frame_size
+= num_regs
* 12;
4058 /* Parse a directive saving VFP registers for ARMv6 and above. */
4061 s_arm_unwind_save_vfp_armv6 (void)
4066 int num_vfpv3_regs
= 0;
4067 int num_regs_below_16
;
4069 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4072 as_bad (_("expected register list"));
4073 ignore_rest_of_line ();
4077 demand_empty_rest_of_line ();
4079 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4080 than FSTMX/FLDMX-style ones). */
4082 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4084 num_vfpv3_regs
= count
;
4085 else if (start
+ count
> 16)
4086 num_vfpv3_regs
= start
+ count
- 16;
4088 if (num_vfpv3_regs
> 0)
4090 int start_offset
= start
> 16 ? start
- 16 : 0;
4091 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4092 add_unwind_opcode (op
, 2);
4095 /* Generate opcode for registers numbered in the range 0 .. 15. */
4096 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4097 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4098 if (num_regs_below_16
> 0)
4100 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4101 add_unwind_opcode (op
, 2);
4104 unwind
.frame_size
+= count
* 8;
4108 /* Parse a directive saving VFP registers for pre-ARMv6. */
4111 s_arm_unwind_save_vfp (void)
4117 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4120 as_bad (_("expected register list"));
4121 ignore_rest_of_line ();
4125 demand_empty_rest_of_line ();
4130 op
= 0xb8 | (count
- 1);
4131 add_unwind_opcode (op
, 1);
4136 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4137 add_unwind_opcode (op
, 2);
4139 unwind
.frame_size
+= count
* 8 + 4;
4143 /* Parse a directive saving iWMMXt data registers. */
4146 s_arm_unwind_save_mmxwr (void)
4154 if (*input_line_pointer
== '{')
4155 input_line_pointer
++;
4159 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4163 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4168 as_tsktsk (_("register list not in ascending order"));
4171 if (*input_line_pointer
== '-')
4173 input_line_pointer
++;
4174 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4177 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4180 else if (reg
>= hi_reg
)
4182 as_bad (_("bad register range"));
4185 for (; reg
< hi_reg
; reg
++)
4189 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4191 skip_past_char (&input_line_pointer
, '}');
4193 demand_empty_rest_of_line ();
4195 /* Generate any deferred opcodes because we're going to be looking at
4197 flush_pending_unwind ();
4199 for (i
= 0; i
< 16; i
++)
4201 if (mask
& (1 << i
))
4202 unwind
.frame_size
+= 8;
4205 /* Attempt to combine with a previous opcode. We do this because gcc
4206 likes to output separate unwind directives for a single block of
4208 if (unwind
.opcode_count
> 0)
4210 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4211 if ((i
& 0xf8) == 0xc0)
4214 /* Only merge if the blocks are contiguous. */
4217 if ((mask
& 0xfe00) == (1 << 9))
4219 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4220 unwind
.opcode_count
--;
4223 else if (i
== 6 && unwind
.opcode_count
>= 2)
4225 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4229 op
= 0xffff << (reg
- 1);
4231 && ((mask
& op
) == (1u << (reg
- 1))))
4233 op
= (1 << (reg
+ i
+ 1)) - 1;
4234 op
&= ~((1 << reg
) - 1);
4236 unwind
.opcode_count
-= 2;
4243 /* We want to generate opcodes in the order the registers have been
4244 saved, ie. descending order. */
4245 for (reg
= 15; reg
>= -1; reg
--)
4247 /* Save registers in blocks. */
4249 || !(mask
& (1 << reg
)))
4251 /* We found an unsaved reg. Generate opcodes to save the
4258 op
= 0xc0 | (hi_reg
- 10);
4259 add_unwind_opcode (op
, 1);
4264 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4265 add_unwind_opcode (op
, 2);
4274 ignore_rest_of_line ();
4278 s_arm_unwind_save_mmxwcg (void)
4285 if (*input_line_pointer
== '{')
4286 input_line_pointer
++;
4288 skip_whitespace (input_line_pointer
);
4292 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4296 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4302 as_tsktsk (_("register list not in ascending order"));
4305 if (*input_line_pointer
== '-')
4307 input_line_pointer
++;
4308 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4311 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4314 else if (reg
>= hi_reg
)
4316 as_bad (_("bad register range"));
4319 for (; reg
< hi_reg
; reg
++)
4323 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4325 skip_past_char (&input_line_pointer
, '}');
4327 demand_empty_rest_of_line ();
4329 /* Generate any deferred opcodes because we're going to be looking at
4331 flush_pending_unwind ();
4333 for (reg
= 0; reg
< 16; reg
++)
4335 if (mask
& (1 << reg
))
4336 unwind
.frame_size
+= 4;
4339 add_unwind_opcode (op
, 2);
4342 ignore_rest_of_line ();
4346 /* Parse an unwind_save directive.
4347 If the argument is non-zero, this is a .vsave directive. */
4350 s_arm_unwind_save (int arch_v6
)
4353 struct reg_entry
*reg
;
4354 bfd_boolean had_brace
= FALSE
;
4356 if (!unwind
.proc_start
)
4357 as_bad (MISSING_FNSTART
);
4359 /* Figure out what sort of save we have. */
4360 peek
= input_line_pointer
;
4368 reg
= arm_reg_parse_multi (&peek
);
4372 as_bad (_("register expected"));
4373 ignore_rest_of_line ();
4382 as_bad (_("FPA .unwind_save does not take a register list"));
4383 ignore_rest_of_line ();
4386 input_line_pointer
= peek
;
4387 s_arm_unwind_save_fpa (reg
->number
);
4391 s_arm_unwind_save_core ();
4396 s_arm_unwind_save_vfp_armv6 ();
4398 s_arm_unwind_save_vfp ();
4401 case REG_TYPE_MMXWR
:
4402 s_arm_unwind_save_mmxwr ();
4405 case REG_TYPE_MMXWCG
:
4406 s_arm_unwind_save_mmxwcg ();
4410 as_bad (_(".unwind_save does not support this kind of register"));
4411 ignore_rest_of_line ();
4416 /* Parse an unwind_movsp directive. */
4419 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4425 if (!unwind
.proc_start
)
4426 as_bad (MISSING_FNSTART
);
4428 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4431 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4432 ignore_rest_of_line ();
4436 /* Optional constant. */
4437 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4439 if (immediate_for_directive (&offset
) == FAIL
)
4445 demand_empty_rest_of_line ();
4447 if (reg
== REG_SP
|| reg
== REG_PC
)
4449 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4453 if (unwind
.fp_reg
!= REG_SP
)
4454 as_bad (_("unexpected .unwind_movsp directive"));
4456 /* Generate opcode to restore the value. */
4458 add_unwind_opcode (op
, 1);
4460 /* Record the information for later. */
4461 unwind
.fp_reg
= reg
;
4462 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4463 unwind
.sp_restored
= 1;
4466 /* Parse an unwind_pad directive. */
4469 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4473 if (!unwind
.proc_start
)
4474 as_bad (MISSING_FNSTART
);
4476 if (immediate_for_directive (&offset
) == FAIL
)
4481 as_bad (_("stack increment must be multiple of 4"));
4482 ignore_rest_of_line ();
4486 /* Don't generate any opcodes, just record the details for later. */
4487 unwind
.frame_size
+= offset
;
4488 unwind
.pending_offset
+= offset
;
4490 demand_empty_rest_of_line ();
4493 /* Parse an unwind_setfp directive. */
4496 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4502 if (!unwind
.proc_start
)
4503 as_bad (MISSING_FNSTART
);
4505 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4506 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4509 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4511 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4513 as_bad (_("expected <reg>, <reg>"));
4514 ignore_rest_of_line ();
4518 /* Optional constant. */
4519 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4521 if (immediate_for_directive (&offset
) == FAIL
)
4527 demand_empty_rest_of_line ();
4529 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4531 as_bad (_("register must be either sp or set by a previous"
4532 "unwind_movsp directive"));
4536 /* Don't generate any opcodes, just record the information for later. */
4537 unwind
.fp_reg
= fp_reg
;
4539 if (sp_reg
== REG_SP
)
4540 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4542 unwind
.fp_offset
-= offset
;
4545 /* Parse an unwind_raw directive. */
4548 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4551 /* This is an arbitrary limit. */
4552 unsigned char op
[16];
4555 if (!unwind
.proc_start
)
4556 as_bad (MISSING_FNSTART
);
4559 if (exp
.X_op
== O_constant
4560 && skip_past_comma (&input_line_pointer
) != FAIL
)
4562 unwind
.frame_size
+= exp
.X_add_number
;
4566 exp
.X_op
= O_illegal
;
4568 if (exp
.X_op
!= O_constant
)
4570 as_bad (_("expected <offset>, <opcode>"));
4571 ignore_rest_of_line ();
4577 /* Parse the opcode. */
4582 as_bad (_("unwind opcode too long"));
4583 ignore_rest_of_line ();
4585 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4587 as_bad (_("invalid unwind opcode"));
4588 ignore_rest_of_line ();
4591 op
[count
++] = exp
.X_add_number
;
4593 /* Parse the next byte. */
4594 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4600 /* Add the opcode bytes in reverse order. */
4602 add_unwind_opcode (op
[count
], 1);
4604 demand_empty_rest_of_line ();
4608 /* Parse a .eabi_attribute directive. */
4611 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4613 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4615 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4616 attributes_set_explicitly
[tag
] = 1;
4619 /* Emit a tls fix for the symbol. */
4622 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4626 #ifdef md_flush_pending_output
4627 md_flush_pending_output ();
4630 #ifdef md_cons_align
4634 /* Since we're just labelling the code, there's no need to define a
4637 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4638 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4639 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4640 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4642 #endif /* OBJ_ELF */
4644 static void s_arm_arch (int);
4645 static void s_arm_object_arch (int);
4646 static void s_arm_cpu (int);
4647 static void s_arm_fpu (int);
4648 static void s_arm_arch_extension (int);
4653 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4660 if (exp
.X_op
== O_symbol
)
4661 exp
.X_op
= O_secrel
;
4663 emit_expr (&exp
, 4);
4665 while (*input_line_pointer
++ == ',');
4667 input_line_pointer
--;
4668 demand_empty_rest_of_line ();
4672 /* This table describes all the machine specific pseudo-ops the assembler
4673 has to support. The fields are:
4674 pseudo-op name without dot
4675 function to call to execute this pseudo-op
4676 Integer arg to pass to the function. */
4678 const pseudo_typeS md_pseudo_table
[] =
4680 /* Never called because '.req' does not start a line. */
4681 { "req", s_req
, 0 },
4682 /* Following two are likewise never called. */
4685 { "unreq", s_unreq
, 0 },
4686 { "bss", s_bss
, 0 },
4687 { "align", s_align_ptwo
, 2 },
4688 { "arm", s_arm
, 0 },
4689 { "thumb", s_thumb
, 0 },
4690 { "code", s_code
, 0 },
4691 { "force_thumb", s_force_thumb
, 0 },
4692 { "thumb_func", s_thumb_func
, 0 },
4693 { "thumb_set", s_thumb_set
, 0 },
4694 { "even", s_even
, 0 },
4695 { "ltorg", s_ltorg
, 0 },
4696 { "pool", s_ltorg
, 0 },
4697 { "syntax", s_syntax
, 0 },
4698 { "cpu", s_arm_cpu
, 0 },
4699 { "arch", s_arm_arch
, 0 },
4700 { "object_arch", s_arm_object_arch
, 0 },
4701 { "fpu", s_arm_fpu
, 0 },
4702 { "arch_extension", s_arm_arch_extension
, 0 },
4704 { "word", s_arm_elf_cons
, 4 },
4705 { "long", s_arm_elf_cons
, 4 },
4706 { "inst.n", s_arm_elf_inst
, 2 },
4707 { "inst.w", s_arm_elf_inst
, 4 },
4708 { "inst", s_arm_elf_inst
, 0 },
4709 { "rel31", s_arm_rel31
, 0 },
4710 { "fnstart", s_arm_unwind_fnstart
, 0 },
4711 { "fnend", s_arm_unwind_fnend
, 0 },
4712 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4713 { "personality", s_arm_unwind_personality
, 0 },
4714 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4715 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4716 { "save", s_arm_unwind_save
, 0 },
4717 { "vsave", s_arm_unwind_save
, 1 },
4718 { "movsp", s_arm_unwind_movsp
, 0 },
4719 { "pad", s_arm_unwind_pad
, 0 },
4720 { "setfp", s_arm_unwind_setfp
, 0 },
4721 { "unwind_raw", s_arm_unwind_raw
, 0 },
4722 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4723 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4727 /* These are used for dwarf. */
4731 /* These are used for dwarf2. */
4732 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4733 { "loc", dwarf2_directive_loc
, 0 },
4734 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4736 { "extend", float_cons
, 'x' },
4737 { "ldouble", float_cons
, 'x' },
4738 { "packed", float_cons
, 'p' },
4740 {"secrel32", pe_directive_secrel
, 0},
4743 /* These are for compatibility with CodeComposer Studio. */
4744 {"ref", s_ccs_ref
, 0},
4745 {"def", s_ccs_def
, 0},
4746 {"asmfunc", s_ccs_asmfunc
, 0},
4747 {"endasmfunc", s_ccs_endasmfunc
, 0},
4752 /* Parser functions used exclusively in instruction operands. */
4754 /* Generic immediate-value read function for use in insn parsing.
4755 STR points to the beginning of the immediate (the leading #);
4756 VAL receives the value; if the value is outside [MIN, MAX]
4757 issue an error. PREFIX_OPT is true if the immediate prefix is
4761 parse_immediate (char **str
, int *val
, int min
, int max
,
4762 bfd_boolean prefix_opt
)
4765 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4766 if (exp
.X_op
!= O_constant
)
4768 inst
.error
= _("constant expression required");
4772 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4774 inst
.error
= _("immediate value out of range");
4778 *val
= exp
.X_add_number
;
4782 /* Less-generic immediate-value read function with the possibility of loading a
4783 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4784 instructions. Puts the result directly in inst.operands[i]. */
4787 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4788 bfd_boolean allow_symbol_p
)
4791 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4794 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4796 if (exp_p
->X_op
== O_constant
)
4798 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4799 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4800 O_constant. We have to be careful not to break compilation for
4801 32-bit X_add_number, though. */
4802 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4804 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4805 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4807 inst
.operands
[i
].regisimm
= 1;
4810 else if (exp_p
->X_op
== O_big
4811 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4813 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4815 /* Bignums have their least significant bits in
4816 generic_bignum[0]. Make sure we put 32 bits in imm and
4817 32 bits in reg, in a (hopefully) portable way. */
4818 gas_assert (parts
!= 0);
4820 /* Make sure that the number is not too big.
4821 PR 11972: Bignums can now be sign-extended to the
4822 size of a .octa so check that the out of range bits
4823 are all zero or all one. */
4824 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4826 LITTLENUM_TYPE m
= -1;
4828 if (generic_bignum
[parts
* 2] != 0
4829 && generic_bignum
[parts
* 2] != m
)
4832 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4833 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4837 inst
.operands
[i
].imm
= 0;
4838 for (j
= 0; j
< parts
; j
++, idx
++)
4839 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4840 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4841 inst
.operands
[i
].reg
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].regisimm
= 1;
4847 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4855 /* Returns the pseudo-register number of an FPA immediate constant,
4856 or FAIL if there isn't a valid constant here. */
4859 parse_fpa_immediate (char ** str
)
4861 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4867 /* First try and match exact strings, this is to guarantee
4868 that some formats will work even for cross assembly. */
4870 for (i
= 0; fp_const
[i
]; i
++)
4872 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4876 *str
+= strlen (fp_const
[i
]);
4877 if (is_end_of_line
[(unsigned char) **str
])
4883 /* Just because we didn't get a match doesn't mean that the constant
4884 isn't valid, just that it is in a format that we don't
4885 automatically recognize. Try parsing it with the standard
4886 expression routines. */
4888 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4890 /* Look for a raw floating point number. */
4891 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4892 && is_end_of_line
[(unsigned char) *save_in
])
4894 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4896 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4898 if (words
[j
] != fp_values
[i
][j
])
4902 if (j
== MAX_LITTLENUMS
)
4910 /* Try and parse a more complex expression, this will probably fail
4911 unless the code uses a floating point prefix (eg "0f"). */
4912 save_in
= input_line_pointer
;
4913 input_line_pointer
= *str
;
4914 if (expression (&exp
) == absolute_section
4915 && exp
.X_op
== O_big
4916 && exp
.X_add_number
< 0)
4918 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4920 #define X_PRECISION 5
4921 #define E_PRECISION 15L
4922 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4924 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4926 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4928 if (words
[j
] != fp_values
[i
][j
])
4932 if (j
== MAX_LITTLENUMS
)
4934 *str
= input_line_pointer
;
4935 input_line_pointer
= save_in
;
4942 *str
= input_line_pointer
;
4943 input_line_pointer
= save_in
;
4944 inst
.error
= _("invalid FPA immediate expression");
4948 /* Returns 1 if a number has "quarter-precision" float format
4949 0baBbbbbbc defgh000 00000000 00000000. */
4952 is_quarter_float (unsigned imm
)
4954 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4955 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4959 /* Detect the presence of a floating point or integer zero constant,
4963 parse_ifimm_zero (char **in
)
4967 if (!is_immediate_prefix (**in
))
4972 /* Accept #0x0 as a synonym for #0. */
4973 if (strncmp (*in
, "0x", 2) == 0)
4976 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4981 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4982 &generic_floating_point_number
);
4985 && generic_floating_point_number
.sign
== '+'
4986 && (generic_floating_point_number
.low
4987 > generic_floating_point_number
.leader
))
4993 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4994 0baBbbbbbc defgh000 00000000 00000000.
4995 The zero and minus-zero cases need special handling, since they can't be
4996 encoded in the "quarter-precision" float format, but can nonetheless be
4997 loaded as integer constants. */
5000 parse_qfloat_immediate (char **ccp
, int *immed
)
5004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5005 int found_fpchar
= 0;
5007 skip_past_char (&str
, '#');
5009 /* We must not accidentally parse an integer as a floating-point number. Make
5010 sure that the value we parse is not an integer by checking for special
5011 characters '.' or 'e'.
5012 FIXME: This is a horrible hack, but doing better is tricky because type
5013 information isn't in a very usable state at parse time. */
5015 skip_whitespace (fpnum
);
5017 if (strncmp (fpnum
, "0x", 2) == 0)
5021 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5022 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5032 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5034 unsigned fpword
= 0;
5037 /* Our FP word must be 32 bits (single-precision FP). */
5038 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5040 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5044 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5057 /* Shift operands. */
5060 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5063 struct asm_shift_name
5066 enum shift_kind kind
;
5069 /* Third argument to parse_shift. */
5070 enum parse_shift_mode
5072 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5073 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5074 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5075 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5076 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5079 /* Parse a <shift> specifier on an ARM data processing instruction.
5080 This has three forms:
5082 (LSL|LSR|ASL|ASR|ROR) Rs
5083 (LSL|LSR|ASL|ASR|ROR) #imm
5086 Note that ASL is assimilated to LSL in the instruction encoding, and
5087 RRX to ROR #0 (which cannot be written as such). */
5090 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5092 const struct asm_shift_name
*shift_name
;
5093 enum shift_kind shift
;
5098 for (p
= *str
; ISALPHA (*p
); p
++)
5103 inst
.error
= _("shift expression expected");
5107 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5110 if (shift_name
== NULL
)
5112 inst
.error
= _("shift expression expected");
5116 shift
= shift_name
->kind
;
5120 case NO_SHIFT_RESTRICT
:
5121 case SHIFT_IMMEDIATE
: break;
5123 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5124 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5126 inst
.error
= _("'LSL' or 'ASR' required");
5131 case SHIFT_LSL_IMMEDIATE
:
5132 if (shift
!= SHIFT_LSL
)
5134 inst
.error
= _("'LSL' required");
5139 case SHIFT_ASR_IMMEDIATE
:
5140 if (shift
!= SHIFT_ASR
)
5142 inst
.error
= _("'ASR' required");
5150 if (shift
!= SHIFT_RRX
)
5152 /* Whitespace can appear here if the next thing is a bare digit. */
5153 skip_whitespace (p
);
5155 if (mode
== NO_SHIFT_RESTRICT
5156 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5158 inst
.operands
[i
].imm
= reg
;
5159 inst
.operands
[i
].immisreg
= 1;
5161 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5164 inst
.operands
[i
].shift_kind
= shift
;
5165 inst
.operands
[i
].shifted
= 1;
5170 /* Parse a <shifter_operand> for an ARM data processing instruction:
5173 #<immediate>, <rotate>
5177 where <shift> is defined by parse_shift above, and <rotate> is a
5178 multiple of 2 between 0 and 30. Validation of immediate operands
5179 is deferred to md_apply_fix. */
5182 parse_shifter_operand (char **str
, int i
)
5187 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5189 inst
.operands
[i
].reg
= value
;
5190 inst
.operands
[i
].isreg
= 1;
5192 /* parse_shift will override this if appropriate */
5193 inst
.reloc
.exp
.X_op
= O_constant
;
5194 inst
.reloc
.exp
.X_add_number
= 0;
5196 if (skip_past_comma (str
) == FAIL
)
5199 /* Shift operation on register. */
5200 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5203 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5206 if (skip_past_comma (str
) == SUCCESS
)
5208 /* #x, y -- ie explicit rotation by Y. */
5209 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5212 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5214 inst
.error
= _("constant expression expected");
5218 value
= exp
.X_add_number
;
5219 if (value
< 0 || value
> 30 || value
% 2 != 0)
5221 inst
.error
= _("invalid rotation");
5224 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5226 inst
.error
= _("invalid constant");
5230 /* Encode as specified. */
5231 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5235 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5236 inst
.reloc
.pc_rel
= 0;
5240 /* Group relocation information. Each entry in the table contains the
5241 textual name of the relocation as may appear in assembler source
5242 and must end with a colon.
5243 Along with this textual name are the relocation codes to be used if
5244 the corresponding instruction is an ALU instruction (ADD or SUB only),
5245 an LDR, an LDRS, or an LDC. */
5247 struct group_reloc_table_entry
5258 /* Varieties of non-ALU group relocation. */
5265 static struct group_reloc_table_entry group_reloc_table
[] =
5266 { /* Program counter relative: */
5268 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5273 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5274 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5278 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5283 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5284 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5285 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5286 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5288 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5289 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5290 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5291 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5292 /* Section base relative */
5294 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5299 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5300 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5301 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5302 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5304 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5309 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5310 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5311 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5312 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5314 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5315 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5316 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5317 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5318 /* Absolute thumb alu relocations. */
5320 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5325 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5330 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5335 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5340 /* Given the address of a pointer pointing to the textual name of a group
5341 relocation as may appear in assembler source, attempt to find its details
5342 in group_reloc_table. The pointer will be updated to the character after
5343 the trailing colon. On failure, FAIL will be returned; SUCCESS
5344 otherwise. On success, *entry will be updated to point at the relevant
5345 group_reloc_table entry. */
5348 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5351 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5353 int length
= strlen (group_reloc_table
[i
].name
);
5355 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5356 && (*str
)[length
] == ':')
5358 *out
= &group_reloc_table
[i
];
5359 *str
+= (length
+ 1);
5367 /* Parse a <shifter_operand> for an ARM data processing instruction
5368 (as for parse_shifter_operand) where group relocations are allowed:
5371 #<immediate>, <rotate>
5372 #:<group_reloc>:<expression>
5376 where <group_reloc> is one of the strings defined in group_reloc_table.
5377 The hashes are optional.
5379 Everything else is as for parse_shifter_operand. */
5381 static parse_operand_result
5382 parse_shifter_operand_group_reloc (char **str
, int i
)
5384 /* Determine if we have the sequence of characters #: or just :
5385 coming next. If we do, then we check for a group relocation.
5386 If we don't, punt the whole lot to parse_shifter_operand. */
5388 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5389 || (*str
)[0] == ':')
5391 struct group_reloc_table_entry
*entry
;
5393 if ((*str
)[0] == '#')
5398 /* Try to parse a group relocation. Anything else is an error. */
5399 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5401 inst
.error
= _("unknown group relocation");
5402 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5405 /* We now have the group relocation table entry corresponding to
5406 the name in the assembler source. Next, we parse the expression. */
5407 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5408 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5410 /* Record the relocation type (always the ALU variant here). */
5411 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5412 gas_assert (inst
.reloc
.type
!= 0);
5414 return PARSE_OPERAND_SUCCESS
;
5417 return parse_shifter_operand (str
, i
) == SUCCESS
5418 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5420 /* Never reached. */
5423 /* Parse a Neon alignment expression. Information is written to
5424 inst.operands[i]. We assume the initial ':' has been skipped.
5426 align .imm = align << 8, .immisalign=1, .preind=0 */
5427 static parse_operand_result
5428 parse_neon_alignment (char **str
, int i
)
5433 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5435 if (exp
.X_op
!= O_constant
)
5437 inst
.error
= _("alignment must be constant");
5438 return PARSE_OPERAND_FAIL
;
5441 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5442 inst
.operands
[i
].immisalign
= 1;
5443 /* Alignments are not pre-indexes. */
5444 inst
.operands
[i
].preind
= 0;
5447 return PARSE_OPERAND_SUCCESS
;
5450 /* Parse all forms of an ARM address expression. Information is written
5451 to inst.operands[i] and/or inst.reloc.
5453 Preindexed addressing (.preind=1):
5455 [Rn, #offset] .reg=Rn .reloc.exp=offset
5456 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5457 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5458 .shift_kind=shift .reloc.exp=shift_imm
5460 These three may have a trailing ! which causes .writeback to be set also.
5462 Postindexed addressing (.postind=1, .writeback=1):
5464 [Rn], #offset .reg=Rn .reloc.exp=offset
5465 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5467 .shift_kind=shift .reloc.exp=shift_imm
5469 Unindexed addressing (.preind=0, .postind=0):
5471 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5475 [Rn]{!} shorthand for [Rn,#0]{!}
5476 =immediate .isreg=0 .reloc.exp=immediate
5477 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5479 It is the caller's responsibility to check for addressing modes not
5480 supported by the instruction, and to set inst.reloc.type. */
5482 static parse_operand_result
5483 parse_address_main (char **str
, int i
, int group_relocations
,
5484 group_reloc_type group_type
)
5489 if (skip_past_char (&p
, '[') == FAIL
)
5491 if (skip_past_char (&p
, '=') == FAIL
)
5493 /* Bare address - translate to PC-relative offset. */
5494 inst
.reloc
.pc_rel
= 1;
5495 inst
.operands
[i
].reg
= REG_PC
;
5496 inst
.operands
[i
].isreg
= 1;
5497 inst
.operands
[i
].preind
= 1;
5499 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5500 return PARSE_OPERAND_FAIL
;
5502 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5503 /*allow_symbol_p=*/TRUE
))
5504 return PARSE_OPERAND_FAIL
;
5507 return PARSE_OPERAND_SUCCESS
;
5510 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5511 skip_whitespace (p
);
5513 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5515 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5516 return PARSE_OPERAND_FAIL
;
5518 inst
.operands
[i
].reg
= reg
;
5519 inst
.operands
[i
].isreg
= 1;
5521 if (skip_past_comma (&p
) == SUCCESS
)
5523 inst
.operands
[i
].preind
= 1;
5526 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5528 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5530 inst
.operands
[i
].imm
= reg
;
5531 inst
.operands
[i
].immisreg
= 1;
5533 if (skip_past_comma (&p
) == SUCCESS
)
5534 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5535 return PARSE_OPERAND_FAIL
;
5537 else if (skip_past_char (&p
, ':') == SUCCESS
)
5539 /* FIXME: '@' should be used here, but it's filtered out by generic
5540 code before we get to see it here. This may be subject to
5542 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5544 if (result
!= PARSE_OPERAND_SUCCESS
)
5549 if (inst
.operands
[i
].negative
)
5551 inst
.operands
[i
].negative
= 0;
5555 if (group_relocations
5556 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5558 struct group_reloc_table_entry
*entry
;
5560 /* Skip over the #: or : sequence. */
5566 /* Try to parse a group relocation. Anything else is an
5568 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5570 inst
.error
= _("unknown group relocation");
5571 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5574 /* We now have the group relocation table entry corresponding to
5575 the name in the assembler source. Next, we parse the
5577 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5578 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5580 /* Record the relocation type. */
5584 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5588 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5599 if (inst
.reloc
.type
== 0)
5601 inst
.error
= _("this group relocation is not allowed on this instruction");
5602 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5608 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5609 return PARSE_OPERAND_FAIL
;
5610 /* If the offset is 0, find out if it's a +0 or -0. */
5611 if (inst
.reloc
.exp
.X_op
== O_constant
5612 && inst
.reloc
.exp
.X_add_number
== 0)
5614 skip_whitespace (q
);
5618 skip_whitespace (q
);
5621 inst
.operands
[i
].negative
= 1;
5626 else if (skip_past_char (&p
, ':') == SUCCESS
)
5628 /* FIXME: '@' should be used here, but it's filtered out by generic code
5629 before we get to see it here. This may be subject to change. */
5630 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5632 if (result
!= PARSE_OPERAND_SUCCESS
)
5636 if (skip_past_char (&p
, ']') == FAIL
)
5638 inst
.error
= _("']' expected");
5639 return PARSE_OPERAND_FAIL
;
5642 if (skip_past_char (&p
, '!') == SUCCESS
)
5643 inst
.operands
[i
].writeback
= 1;
5645 else if (skip_past_comma (&p
) == SUCCESS
)
5647 if (skip_past_char (&p
, '{') == SUCCESS
)
5649 /* [Rn], {expr} - unindexed, with option */
5650 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5651 0, 255, TRUE
) == FAIL
)
5652 return PARSE_OPERAND_FAIL
;
5654 if (skip_past_char (&p
, '}') == FAIL
)
5656 inst
.error
= _("'}' expected at end of 'option' field");
5657 return PARSE_OPERAND_FAIL
;
5659 if (inst
.operands
[i
].preind
)
5661 inst
.error
= _("cannot combine index with option");
5662 return PARSE_OPERAND_FAIL
;
5665 return PARSE_OPERAND_SUCCESS
;
5669 inst
.operands
[i
].postind
= 1;
5670 inst
.operands
[i
].writeback
= 1;
5672 if (inst
.operands
[i
].preind
)
5674 inst
.error
= _("cannot combine pre- and post-indexing");
5675 return PARSE_OPERAND_FAIL
;
5679 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5681 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5683 /* We might be using the immediate for alignment already. If we
5684 are, OR the register number into the low-order bits. */
5685 if (inst
.operands
[i
].immisalign
)
5686 inst
.operands
[i
].imm
|= reg
;
5688 inst
.operands
[i
].imm
= reg
;
5689 inst
.operands
[i
].immisreg
= 1;
5691 if (skip_past_comma (&p
) == SUCCESS
)
5692 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5693 return PARSE_OPERAND_FAIL
;
5698 if (inst
.operands
[i
].negative
)
5700 inst
.operands
[i
].negative
= 0;
5703 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5704 return PARSE_OPERAND_FAIL
;
5705 /* If the offset is 0, find out if it's a +0 or -0. */
5706 if (inst
.reloc
.exp
.X_op
== O_constant
5707 && inst
.reloc
.exp
.X_add_number
== 0)
5709 skip_whitespace (q
);
5713 skip_whitespace (q
);
5716 inst
.operands
[i
].negative
= 1;
5722 /* If at this point neither .preind nor .postind is set, we have a
5723 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5724 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5726 inst
.operands
[i
].preind
= 1;
5727 inst
.reloc
.exp
.X_op
= O_constant
;
5728 inst
.reloc
.exp
.X_add_number
= 0;
5731 return PARSE_OPERAND_SUCCESS
;
5735 parse_address (char **str
, int i
)
5737 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5741 static parse_operand_result
5742 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5744 return parse_address_main (str
, i
, 1, type
);
5747 /* Parse an operand for a MOVW or MOVT instruction. */
5749 parse_half (char **str
)
5754 skip_past_char (&p
, '#');
5755 if (strncasecmp (p
, ":lower16:", 9) == 0)
5756 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5757 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5758 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5760 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5763 skip_whitespace (p
);
5766 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5769 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5771 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5773 inst
.error
= _("constant expression expected");
5776 if (inst
.reloc
.exp
.X_add_number
< 0
5777 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5779 inst
.error
= _("immediate value out of range");
5787 /* Miscellaneous. */
5789 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5790 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5792 parse_psr (char **str
, bfd_boolean lhs
)
5795 unsigned long psr_field
;
5796 const struct asm_psr
*psr
;
5798 bfd_boolean is_apsr
= FALSE
;
5799 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5801 /* PR gas/12698: If the user has specified -march=all then m_profile will
5802 be TRUE, but we want to ignore it in this case as we are building for any
5803 CPU type, including non-m variants. */
5804 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5807 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5808 feature for ease of use and backwards compatibility. */
5810 if (strncasecmp (p
, "SPSR", 4) == 0)
5813 goto unsupported_psr
;
5815 psr_field
= SPSR_BIT
;
5817 else if (strncasecmp (p
, "CPSR", 4) == 0)
5820 goto unsupported_psr
;
5824 else if (strncasecmp (p
, "APSR", 4) == 0)
5826 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5827 and ARMv7-R architecture CPUs. */
5836 while (ISALNUM (*p
) || *p
== '_');
5838 if (strncasecmp (start
, "iapsr", 5) == 0
5839 || strncasecmp (start
, "eapsr", 5) == 0
5840 || strncasecmp (start
, "xpsr", 4) == 0
5841 || strncasecmp (start
, "psr", 3) == 0)
5842 p
= start
+ strcspn (start
, "rR") + 1;
5844 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5850 /* If APSR is being written, a bitfield may be specified. Note that
5851 APSR itself is handled above. */
5852 if (psr
->field
<= 3)
5854 psr_field
= psr
->field
;
5860 /* M-profile MSR instructions have the mask field set to "10", except
5861 *PSR variants which modify APSR, which may use a different mask (and
5862 have been handled already). Do that by setting the PSR_f field
5864 return psr
->field
| (lhs
? PSR_f
: 0);
5867 goto unsupported_psr
;
5873 /* A suffix follows. */
5879 while (ISALNUM (*p
) || *p
== '_');
5883 /* APSR uses a notation for bits, rather than fields. */
5884 unsigned int nzcvq_bits
= 0;
5885 unsigned int g_bit
= 0;
5888 for (bit
= start
; bit
!= p
; bit
++)
5890 switch (TOLOWER (*bit
))
5893 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5897 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5901 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5913 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5917 inst
.error
= _("unexpected bit specified after APSR");
5922 if (nzcvq_bits
== 0x1f)
5927 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5929 inst
.error
= _("selected processor does not "
5930 "support DSP extension");
5937 if ((nzcvq_bits
& 0x20) != 0
5938 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5939 || (g_bit
& 0x2) != 0)
5941 inst
.error
= _("bad bitmask specified after APSR");
5947 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5952 psr_field
|= psr
->field
;
5958 goto error
; /* Garbage after "[CS]PSR". */
5960 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5961 is deprecated, but allow it anyway. */
5965 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5968 else if (!m_profile
)
5969 /* These bits are never right for M-profile devices: don't set them
5970 (only code paths which read/write APSR reach here). */
5971 psr_field
|= (PSR_c
| PSR_f
);
5977 inst
.error
= _("selected processor does not support requested special "
5978 "purpose register");
5982 inst
.error
= _("flag for {c}psr instruction expected");
5986 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5987 value suitable for splatting into the AIF field of the instruction. */
5990 parse_cps_flags (char **str
)
5999 case '\0': case ',':
6002 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6003 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6004 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6007 inst
.error
= _("unrecognized CPS flag");
6012 if (saw_a_flag
== 0)
6014 inst
.error
= _("missing CPS flags");
6022 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6023 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6026 parse_endian_specifier (char **str
)
6031 if (strncasecmp (s
, "BE", 2))
6033 else if (strncasecmp (s
, "LE", 2))
6037 inst
.error
= _("valid endian specifiers are be or le");
6041 if (ISALNUM (s
[2]) || s
[2] == '_')
6043 inst
.error
= _("valid endian specifiers are be or le");
6048 return little_endian
;
6051 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6052 value suitable for poking into the rotate field of an sxt or sxta
6053 instruction, or FAIL on error. */
6056 parse_ror (char **str
)
6061 if (strncasecmp (s
, "ROR", 3) == 0)
6065 inst
.error
= _("missing rotation field after comma");
6069 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6074 case 0: *str
= s
; return 0x0;
6075 case 8: *str
= s
; return 0x1;
6076 case 16: *str
= s
; return 0x2;
6077 case 24: *str
= s
; return 0x3;
6080 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6085 /* Parse a conditional code (from conds[] below). The value returned is in the
6086 range 0 .. 14, or FAIL. */
6088 parse_cond (char **str
)
6091 const struct asm_cond
*c
;
6093 /* Condition codes are always 2 characters, so matching up to
6094 3 characters is sufficient. */
6099 while (ISALPHA (*q
) && n
< 3)
6101 cond
[n
] = TOLOWER (*q
);
6106 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6109 inst
.error
= _("condition required");
6117 /* Record a use of the given feature. */
6119 record_feature_use (const arm_feature_set
*feature
)
6122 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6124 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6127 /* If the given feature available in the selected CPU, mark it as used.
6128 Returns TRUE iff feature is available. */
6130 mark_feature_used (const arm_feature_set
*feature
)
6132 /* Ensure the option is valid on the current architecture. */
6133 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6136 /* Add the appropriate architecture feature for the barrier option used.
6138 record_feature_use (feature
);
6143 /* Parse an option for a barrier instruction. Returns the encoding for the
6146 parse_barrier (char **str
)
6149 const struct asm_barrier_opt
*o
;
6152 while (ISALPHA (*q
))
6155 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6160 if (!mark_feature_used (&o
->arch
))
6167 /* Parse the operands of a table branch instruction. Similar to a memory
6170 parse_tb (char **str
)
6175 if (skip_past_char (&p
, '[') == FAIL
)
6177 inst
.error
= _("'[' expected");
6181 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6183 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6186 inst
.operands
[0].reg
= reg
;
6188 if (skip_past_comma (&p
) == FAIL
)
6190 inst
.error
= _("',' expected");
6194 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6196 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6199 inst
.operands
[0].imm
= reg
;
6201 if (skip_past_comma (&p
) == SUCCESS
)
6203 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6205 if (inst
.reloc
.exp
.X_add_number
!= 1)
6207 inst
.error
= _("invalid shift");
6210 inst
.operands
[0].shifted
= 1;
6213 if (skip_past_char (&p
, ']') == FAIL
)
6215 inst
.error
= _("']' expected");
6222 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6223 information on the types the operands can take and how they are encoded.
6224 Up to four operands may be read; this function handles setting the
6225 ".present" field for each read operand itself.
6226 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6227 else returns FAIL. */
6230 parse_neon_mov (char **str
, int *which_operand
)
6232 int i
= *which_operand
, val
;
6233 enum arm_reg_type rtype
;
6235 struct neon_type_el optype
;
6237 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6239 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6240 inst
.operands
[i
].reg
= val
;
6241 inst
.operands
[i
].isscalar
= 1;
6242 inst
.operands
[i
].vectype
= optype
;
6243 inst
.operands
[i
++].present
= 1;
6245 if (skip_past_comma (&ptr
) == FAIL
)
6248 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isreg
= 1;
6253 inst
.operands
[i
].present
= 1;
6255 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6258 /* Cases 0, 1, 2, 3, 5 (D only). */
6259 if (skip_past_comma (&ptr
) == FAIL
)
6262 inst
.operands
[i
].reg
= val
;
6263 inst
.operands
[i
].isreg
= 1;
6264 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6265 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6266 inst
.operands
[i
].isvec
= 1;
6267 inst
.operands
[i
].vectype
= optype
;
6268 inst
.operands
[i
++].present
= 1;
6270 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6272 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6273 Case 13: VMOV <Sd>, <Rm> */
6274 inst
.operands
[i
].reg
= val
;
6275 inst
.operands
[i
].isreg
= 1;
6276 inst
.operands
[i
].present
= 1;
6278 if (rtype
== REG_TYPE_NQ
)
6280 first_error (_("can't use Neon quad register here"));
6283 else if (rtype
!= REG_TYPE_VFS
)
6286 if (skip_past_comma (&ptr
) == FAIL
)
6288 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6290 inst
.operands
[i
].reg
= val
;
6291 inst
.operands
[i
].isreg
= 1;
6292 inst
.operands
[i
].present
= 1;
6295 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6298 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6299 Case 1: VMOV<c><q> <Dd>, <Dm>
6300 Case 8: VMOV.F32 <Sd>, <Sm>
6301 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6306 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6307 inst
.operands
[i
].isvec
= 1;
6308 inst
.operands
[i
].vectype
= optype
;
6309 inst
.operands
[i
].present
= 1;
6311 if (skip_past_comma (&ptr
) == SUCCESS
)
6316 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6319 inst
.operands
[i
].reg
= val
;
6320 inst
.operands
[i
].isreg
= 1;
6321 inst
.operands
[i
++].present
= 1;
6323 if (skip_past_comma (&ptr
) == FAIL
)
6326 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6329 inst
.operands
[i
].reg
= val
;
6330 inst
.operands
[i
].isreg
= 1;
6331 inst
.operands
[i
].present
= 1;
6334 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6335 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6336 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6337 Case 10: VMOV.F32 <Sd>, #<imm>
6338 Case 11: VMOV.F64 <Dd>, #<imm> */
6339 inst
.operands
[i
].immisfloat
= 1;
6340 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6342 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6343 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6347 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6351 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6354 inst
.operands
[i
].reg
= val
;
6355 inst
.operands
[i
].isreg
= 1;
6356 inst
.operands
[i
++].present
= 1;
6358 if (skip_past_comma (&ptr
) == FAIL
)
6361 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6363 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6364 inst
.operands
[i
].reg
= val
;
6365 inst
.operands
[i
].isscalar
= 1;
6366 inst
.operands
[i
].present
= 1;
6367 inst
.operands
[i
].vectype
= optype
;
6369 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6371 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isreg
= 1;
6374 inst
.operands
[i
++].present
= 1;
6376 if (skip_past_comma (&ptr
) == FAIL
)
6379 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6382 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6386 inst
.operands
[i
].reg
= val
;
6387 inst
.operands
[i
].isreg
= 1;
6388 inst
.operands
[i
].isvec
= 1;
6389 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6390 inst
.operands
[i
].vectype
= optype
;
6391 inst
.operands
[i
].present
= 1;
6393 if (rtype
== REG_TYPE_VFS
)
6397 if (skip_past_comma (&ptr
) == FAIL
)
6399 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6402 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6405 inst
.operands
[i
].reg
= val
;
6406 inst
.operands
[i
].isreg
= 1;
6407 inst
.operands
[i
].isvec
= 1;
6408 inst
.operands
[i
].issingle
= 1;
6409 inst
.operands
[i
].vectype
= optype
;
6410 inst
.operands
[i
].present
= 1;
6413 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6417 inst
.operands
[i
].reg
= val
;
6418 inst
.operands
[i
].isreg
= 1;
6419 inst
.operands
[i
].isvec
= 1;
6420 inst
.operands
[i
].issingle
= 1;
6421 inst
.operands
[i
].vectype
= optype
;
6422 inst
.operands
[i
].present
= 1;
6427 first_error (_("parse error"));
6431 /* Successfully parsed the operands. Update args. */
6437 first_error (_("expected comma"));
6441 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6445 /* Use this macro when the operand constraints are different
6446 for ARM and THUMB (e.g. ldrd). */
6447 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6448 ((arm_operand) | ((thumb_operand) << 16))
6450 /* Matcher codes for parse_operands. */
6451 enum operand_parse_code
6453 OP_stop
, /* end of line */
6455 OP_RR
, /* ARM register */
6456 OP_RRnpc
, /* ARM register, not r15 */
6457 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6458 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6459 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6460 optional trailing ! */
6461 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6462 OP_RCP
, /* Coprocessor number */
6463 OP_RCN
, /* Coprocessor register */
6464 OP_RF
, /* FPA register */
6465 OP_RVS
, /* VFP single precision register */
6466 OP_RVD
, /* VFP double precision register (0..15) */
6467 OP_RND
, /* Neon double precision register (0..31) */
6468 OP_RNQ
, /* Neon quad precision register */
6469 OP_RVSD
, /* VFP single or double precision register */
6470 OP_RNDQ
, /* Neon double or quad precision register */
6471 OP_RNSDQ
, /* Neon single, double or quad precision register */
6472 OP_RNSC
, /* Neon scalar D[X] */
6473 OP_RVC
, /* VFP control register */
6474 OP_RMF
, /* Maverick F register */
6475 OP_RMD
, /* Maverick D register */
6476 OP_RMFX
, /* Maverick FX register */
6477 OP_RMDX
, /* Maverick DX register */
6478 OP_RMAX
, /* Maverick AX register */
6479 OP_RMDS
, /* Maverick DSPSC register */
6480 OP_RIWR
, /* iWMMXt wR register */
6481 OP_RIWC
, /* iWMMXt wC register */
6482 OP_RIWG
, /* iWMMXt wCG register */
6483 OP_RXA
, /* XScale accumulator register */
6485 OP_REGLST
, /* ARM register list */
6486 OP_VRSLST
, /* VFP single-precision register list */
6487 OP_VRDLST
, /* VFP double-precision register list */
6488 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6489 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6490 OP_NSTRLST
, /* Neon element/structure list */
6492 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6493 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6494 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6495 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6496 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6497 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6498 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6499 OP_VMOV
, /* Neon VMOV operands. */
6500 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6501 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6502 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6504 OP_I0
, /* immediate zero */
6505 OP_I7
, /* immediate value 0 .. 7 */
6506 OP_I15
, /* 0 .. 15 */
6507 OP_I16
, /* 1 .. 16 */
6508 OP_I16z
, /* 0 .. 16 */
6509 OP_I31
, /* 0 .. 31 */
6510 OP_I31w
, /* 0 .. 31, optional trailing ! */
6511 OP_I32
, /* 1 .. 32 */
6512 OP_I32z
, /* 0 .. 32 */
6513 OP_I63
, /* 0 .. 63 */
6514 OP_I63s
, /* -64 .. 63 */
6515 OP_I64
, /* 1 .. 64 */
6516 OP_I64z
, /* 0 .. 64 */
6517 OP_I255
, /* 0 .. 255 */
6519 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6520 OP_I7b
, /* 0 .. 7 */
6521 OP_I15b
, /* 0 .. 15 */
6522 OP_I31b
, /* 0 .. 31 */
6524 OP_SH
, /* shifter operand */
6525 OP_SHG
, /* shifter operand with possible group relocation */
6526 OP_ADDR
, /* Memory address expression (any mode) */
6527 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6528 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6529 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6530 OP_EXP
, /* arbitrary expression */
6531 OP_EXPi
, /* same, with optional immediate prefix */
6532 OP_EXPr
, /* same, with optional relocation suffix */
6533 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6535 OP_CPSF
, /* CPS flags */
6536 OP_ENDI
, /* Endianness specifier */
6537 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6538 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6539 OP_COND
, /* conditional code */
6540 OP_TB
, /* Table branch. */
6542 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6544 OP_RRnpc_I0
, /* ARM register or literal 0 */
6545 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6546 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6547 OP_RF_IF
, /* FPA register or immediate */
6548 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6549 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6551 /* Optional operands. */
6552 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6553 OP_oI31b
, /* 0 .. 31 */
6554 OP_oI32b
, /* 1 .. 32 */
6555 OP_oI32z
, /* 0 .. 32 */
6556 OP_oIffffb
, /* 0 .. 65535 */
6557 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6559 OP_oRR
, /* ARM register */
6560 OP_oRRnpc
, /* ARM register, not the PC */
6561 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6562 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6563 OP_oRND
, /* Optional Neon double precision register */
6564 OP_oRNQ
, /* Optional Neon quad precision register */
6565 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6566 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6567 OP_oSHll
, /* LSL immediate */
6568 OP_oSHar
, /* ASR immediate */
6569 OP_oSHllar
, /* LSL or ASR immediate */
6570 OP_oROR
, /* ROR 0/8/16/24 */
6571 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6573 /* Some pre-defined mixed (ARM/THUMB) operands. */
6574 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6575 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6576 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6578 OP_FIRST_OPTIONAL
= OP_oI7b
6581 /* Generic instruction operand parser. This does no encoding and no
6582 semantic validation; it merely squirrels values away in the inst
6583 structure. Returns SUCCESS or FAIL depending on whether the
6584 specified grammar matched. */
6586 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6588 unsigned const int *upat
= pattern
;
6589 char *backtrack_pos
= 0;
6590 const char *backtrack_error
= 0;
6591 int i
, val
= 0, backtrack_index
= 0;
6592 enum arm_reg_type rtype
;
6593 parse_operand_result result
;
6594 unsigned int op_parse_code
;
6596 #define po_char_or_fail(chr) \
6599 if (skip_past_char (&str, chr) == FAIL) \
6604 #define po_reg_or_fail(regtype) \
6607 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6608 & inst.operands[i].vectype); \
6611 first_error (_(reg_expected_msgs[regtype])); \
6614 inst.operands[i].reg = val; \
6615 inst.operands[i].isreg = 1; \
6616 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6617 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6618 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6619 || rtype == REG_TYPE_VFD \
6620 || rtype == REG_TYPE_NQ); \
6624 #define po_reg_or_goto(regtype, label) \
6627 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6628 & inst.operands[i].vectype); \
6632 inst.operands[i].reg = val; \
6633 inst.operands[i].isreg = 1; \
6634 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6635 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6636 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6637 || rtype == REG_TYPE_VFD \
6638 || rtype == REG_TYPE_NQ); \
6642 #define po_imm_or_fail(min, max, popt) \
6645 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6647 inst.operands[i].imm = val; \
6651 #define po_scalar_or_goto(elsz, label) \
6654 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6657 inst.operands[i].reg = val; \
6658 inst.operands[i].isscalar = 1; \
6662 #define po_misc_or_fail(expr) \
6670 #define po_misc_or_fail_no_backtrack(expr) \
6674 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6675 backtrack_pos = 0; \
6676 if (result != PARSE_OPERAND_SUCCESS) \
6681 #define po_barrier_or_imm(str) \
6684 val = parse_barrier (&str); \
6685 if (val == FAIL && ! ISALPHA (*str)) \
6688 /* ISB can only take SY as an option. */ \
6689 || ((inst.instruction & 0xf0) == 0x60 \
6692 inst.error = _("invalid barrier type"); \
6693 backtrack_pos = 0; \
6699 skip_whitespace (str
);
6701 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6703 op_parse_code
= upat
[i
];
6704 if (op_parse_code
>= 1<<16)
6705 op_parse_code
= thumb
? (op_parse_code
>> 16)
6706 : (op_parse_code
& ((1<<16)-1));
6708 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6710 /* Remember where we are in case we need to backtrack. */
6711 gas_assert (!backtrack_pos
);
6712 backtrack_pos
= str
;
6713 backtrack_error
= inst
.error
;
6714 backtrack_index
= i
;
6717 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6718 po_char_or_fail (',');
6720 switch (op_parse_code
)
6728 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6729 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6730 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6731 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6732 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6733 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6735 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6737 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6739 /* Also accept generic coprocessor regs for unknown registers. */
6741 po_reg_or_fail (REG_TYPE_CN
);
6743 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6744 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6745 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6746 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6747 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6748 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6749 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6750 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6751 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6752 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6754 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6756 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6757 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6759 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6761 /* Neon scalar. Using an element size of 8 means that some invalid
6762 scalars are accepted here, so deal with those in later code. */
6763 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6767 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6770 po_imm_or_fail (0, 0, TRUE
);
6775 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6780 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6783 if (parse_ifimm_zero (&str
))
6784 inst
.operands
[i
].imm
= 0;
6788 = _("only floating point zero is allowed as immediate value");
6796 po_scalar_or_goto (8, try_rr
);
6799 po_reg_or_fail (REG_TYPE_RN
);
6805 po_scalar_or_goto (8, try_nsdq
);
6808 po_reg_or_fail (REG_TYPE_NSDQ
);
6814 po_scalar_or_goto (8, try_ndq
);
6817 po_reg_or_fail (REG_TYPE_NDQ
);
6823 po_scalar_or_goto (8, try_vfd
);
6826 po_reg_or_fail (REG_TYPE_VFD
);
6831 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6832 not careful then bad things might happen. */
6833 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6838 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6841 /* There's a possibility of getting a 64-bit immediate here, so
6842 we need special handling. */
6843 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6846 inst
.error
= _("immediate value is out of range");
6854 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6857 po_imm_or_fail (0, 63, TRUE
);
6862 po_char_or_fail ('[');
6863 po_reg_or_fail (REG_TYPE_RN
);
6864 po_char_or_fail (']');
6870 po_reg_or_fail (REG_TYPE_RN
);
6871 if (skip_past_char (&str
, '!') == SUCCESS
)
6872 inst
.operands
[i
].writeback
= 1;
6876 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6877 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6878 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6879 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6880 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6881 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6882 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6883 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6884 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6885 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6886 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6887 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6889 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6891 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6892 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6894 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6895 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6896 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6897 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6899 /* Immediate variants */
6901 po_char_or_fail ('{');
6902 po_imm_or_fail (0, 255, TRUE
);
6903 po_char_or_fail ('}');
6907 /* The expression parser chokes on a trailing !, so we have
6908 to find it first and zap it. */
6911 while (*s
&& *s
!= ',')
6916 inst
.operands
[i
].writeback
= 1;
6918 po_imm_or_fail (0, 31, TRUE
);
6926 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6931 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6938 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6940 val
= parse_reloc (&str
);
6943 inst
.error
= _("unrecognized relocation suffix");
6946 else if (val
!= BFD_RELOC_UNUSED
)
6948 inst
.operands
[i
].imm
= val
;
6949 inst
.operands
[i
].hasreloc
= 1;
6954 /* Operand for MOVW or MOVT. */
6956 po_misc_or_fail (parse_half (&str
));
6959 /* Register or expression. */
6960 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6961 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6963 /* Register or immediate. */
6964 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6965 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6967 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6969 if (!is_immediate_prefix (*str
))
6972 val
= parse_fpa_immediate (&str
);
6975 /* FPA immediates are encoded as registers 8-15.
6976 parse_fpa_immediate has already applied the offset. */
6977 inst
.operands
[i
].reg
= val
;
6978 inst
.operands
[i
].isreg
= 1;
6981 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6982 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6984 /* Two kinds of register. */
6987 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6989 || (rege
->type
!= REG_TYPE_MMXWR
6990 && rege
->type
!= REG_TYPE_MMXWC
6991 && rege
->type
!= REG_TYPE_MMXWCG
))
6993 inst
.error
= _("iWMMXt data or control register expected");
6996 inst
.operands
[i
].reg
= rege
->number
;
6997 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7003 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7005 || (rege
->type
!= REG_TYPE_MMXWC
7006 && rege
->type
!= REG_TYPE_MMXWCG
))
7008 inst
.error
= _("iWMMXt control register expected");
7011 inst
.operands
[i
].reg
= rege
->number
;
7012 inst
.operands
[i
].isreg
= 1;
7017 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7018 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7019 case OP_oROR
: val
= parse_ror (&str
); break;
7020 case OP_COND
: val
= parse_cond (&str
); break;
7021 case OP_oBARRIER_I15
:
7022 po_barrier_or_imm (str
); break;
7024 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7030 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7031 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7033 inst
.error
= _("Banked registers are not available with this "
7039 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7043 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7046 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7048 if (strncasecmp (str
, "APSR_", 5) == 0)
7055 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7056 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7057 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7058 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7059 default: found
= 16;
7063 inst
.operands
[i
].isvec
= 1;
7064 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7065 inst
.operands
[i
].reg
= REG_PC
;
7072 po_misc_or_fail (parse_tb (&str
));
7075 /* Register lists. */
7077 val
= parse_reg_list (&str
);
7080 inst
.operands
[i
].writeback
= 1;
7086 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7090 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7094 /* Allow Q registers too. */
7095 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7102 inst
.operands
[i
].issingle
= 1;
7107 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7112 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7113 &inst
.operands
[i
].vectype
);
7116 /* Addressing modes */
7118 po_misc_or_fail (parse_address (&str
, i
));
7122 po_misc_or_fail_no_backtrack (
7123 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7127 po_misc_or_fail_no_backtrack (
7128 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7132 po_misc_or_fail_no_backtrack (
7133 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7137 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7141 po_misc_or_fail_no_backtrack (
7142 parse_shifter_operand_group_reloc (&str
, i
));
7146 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7150 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7154 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7158 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7161 /* Various value-based sanity checks and shared operations. We
7162 do not signal immediate failures for the register constraints;
7163 this allows a syntax error to take precedence. */
7164 switch (op_parse_code
)
7172 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7173 inst
.error
= BAD_PC
;
7178 if (inst
.operands
[i
].isreg
)
7180 if (inst
.operands
[i
].reg
== REG_PC
)
7181 inst
.error
= BAD_PC
;
7182 else if (inst
.operands
[i
].reg
== REG_SP
)
7183 inst
.error
= BAD_SP
;
7188 if (inst
.operands
[i
].isreg
7189 && inst
.operands
[i
].reg
== REG_PC
7190 && (inst
.operands
[i
].writeback
|| thumb
))
7191 inst
.error
= BAD_PC
;
7200 case OP_oBARRIER_I15
:
7209 inst
.operands
[i
].imm
= val
;
7216 /* If we get here, this operand was successfully parsed. */
7217 inst
.operands
[i
].present
= 1;
7221 inst
.error
= BAD_ARGS
;
7226 /* The parse routine should already have set inst.error, but set a
7227 default here just in case. */
7229 inst
.error
= _("syntax error");
7233 /* Do not backtrack over a trailing optional argument that
7234 absorbed some text. We will only fail again, with the
7235 'garbage following instruction' error message, which is
7236 probably less helpful than the current one. */
7237 if (backtrack_index
== i
&& backtrack_pos
!= str
7238 && upat
[i
+1] == OP_stop
)
7241 inst
.error
= _("syntax error");
7245 /* Try again, skipping the optional argument at backtrack_pos. */
7246 str
= backtrack_pos
;
7247 inst
.error
= backtrack_error
;
7248 inst
.operands
[backtrack_index
].present
= 0;
7249 i
= backtrack_index
;
7253 /* Check that we have parsed all the arguments. */
7254 if (*str
!= '\0' && !inst
.error
)
7255 inst
.error
= _("garbage following instruction");
7257 return inst
.error
? FAIL
: SUCCESS
;
7260 #undef po_char_or_fail
7261 #undef po_reg_or_fail
7262 #undef po_reg_or_goto
7263 #undef po_imm_or_fail
7264 #undef po_scalar_or_fail
7265 #undef po_barrier_or_imm
7267 /* Shorthand macro for instruction encoding functions issuing errors. */
7268 #define constraint(expr, err) \
7279 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7280 instructions are unpredictable if these registers are used. This
7281 is the BadReg predicate in ARM's Thumb-2 documentation. */
7282 #define reject_bad_reg(reg) \
7284 if (reg == REG_SP || reg == REG_PC) \
7286 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7291 /* If REG is R13 (the stack pointer), warn that its use is
7293 #define warn_deprecated_sp(reg) \
7295 if (warn_on_deprecated && reg == REG_SP) \
7296 as_tsktsk (_("use of r13 is deprecated")); \
7299 /* Functions for operand encoding. ARM, then Thumb. */
7301 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7303 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7305 The only binary encoding difference is the Coprocessor number. Coprocessor
7306 9 is used for half-precision calculations or conversions. The format of the
7307 instruction is the same as the equivalent Coprocessor 10 instuction that
7308 exists for Single-Precision operation. */
7311 do_scalar_fp16_v82_encode (void)
7313 if (inst
.cond
!= COND_ALWAYS
)
7314 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7315 " the behaviour is UNPREDICTABLE"));
7316 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7319 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7320 mark_feature_used (&arm_ext_fp16
);
7323 /* If VAL can be encoded in the immediate field of an ARM instruction,
7324 return the encoded form. Otherwise, return FAIL. */
7327 encode_arm_immediate (unsigned int val
)
7334 for (i
= 2; i
< 32; i
+= 2)
7335 if ((a
= rotate_left (val
, i
)) <= 0xff)
7336 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7341 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7342 return the encoded form. Otherwise, return FAIL. */
7344 encode_thumb32_immediate (unsigned int val
)
7351 for (i
= 1; i
<= 24; i
++)
7354 if ((val
& ~(0xff << i
)) == 0)
7355 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7359 if (val
== ((a
<< 16) | a
))
7361 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7365 if (val
== ((a
<< 16) | a
))
7366 return 0x200 | (a
>> 8);
7370 /* Encode a VFP SP or DP register number into inst.instruction. */
7373 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7375 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7378 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7381 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7384 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7389 first_error (_("D register out of range for selected VFP version"));
7397 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7401 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7405 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7409 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7413 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7417 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7425 /* Encode a <shift> in an ARM-format instruction. The immediate,
7426 if any, is handled by md_apply_fix. */
7428 encode_arm_shift (int i
)
7430 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7431 inst
.instruction
|= SHIFT_ROR
<< 5;
7434 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7435 if (inst
.operands
[i
].immisreg
)
7437 inst
.instruction
|= SHIFT_BY_REG
;
7438 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7441 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7446 encode_arm_shifter_operand (int i
)
7448 if (inst
.operands
[i
].isreg
)
7450 inst
.instruction
|= inst
.operands
[i
].reg
;
7451 encode_arm_shift (i
);
7455 inst
.instruction
|= INST_IMMEDIATE
;
7456 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7457 inst
.instruction
|= inst
.operands
[i
].imm
;
7461 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7463 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7466 Generate an error if the operand is not a register. */
7467 constraint (!inst
.operands
[i
].isreg
,
7468 _("Instruction does not support =N addresses"));
7470 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7472 if (inst
.operands
[i
].preind
)
7476 inst
.error
= _("instruction does not accept preindexed addressing");
7479 inst
.instruction
|= PRE_INDEX
;
7480 if (inst
.operands
[i
].writeback
)
7481 inst
.instruction
|= WRITE_BACK
;
7484 else if (inst
.operands
[i
].postind
)
7486 gas_assert (inst
.operands
[i
].writeback
);
7488 inst
.instruction
|= WRITE_BACK
;
7490 else /* unindexed - only for coprocessor */
7492 inst
.error
= _("instruction does not accept unindexed addressing");
7496 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7497 && (((inst
.instruction
& 0x000f0000) >> 16)
7498 == ((inst
.instruction
& 0x0000f000) >> 12)))
7499 as_warn ((inst
.instruction
& LOAD_BIT
)
7500 ? _("destination register same as write-back base")
7501 : _("source register same as write-back base"));
7504 /* inst.operands[i] was set up by parse_address. Encode it into an
7505 ARM-format mode 2 load or store instruction. If is_t is true,
7506 reject forms that cannot be used with a T instruction (i.e. not
7509 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7511 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7513 encode_arm_addr_mode_common (i
, is_t
);
7515 if (inst
.operands
[i
].immisreg
)
7517 constraint ((inst
.operands
[i
].imm
== REG_PC
7518 || (is_pc
&& inst
.operands
[i
].writeback
)),
7520 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7521 inst
.instruction
|= inst
.operands
[i
].imm
;
7522 if (!inst
.operands
[i
].negative
)
7523 inst
.instruction
|= INDEX_UP
;
7524 if (inst
.operands
[i
].shifted
)
7526 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7527 inst
.instruction
|= SHIFT_ROR
<< 5;
7530 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7531 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7535 else /* immediate offset in inst.reloc */
7537 if (is_pc
&& !inst
.reloc
.pc_rel
)
7539 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7541 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7542 cannot use PC in addressing.
7543 PC cannot be used in writeback addressing, either. */
7544 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7547 /* Use of PC in str is deprecated for ARMv7. */
7548 if (warn_on_deprecated
7550 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7551 as_tsktsk (_("use of PC in this instruction is deprecated"));
7554 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7556 /* Prefer + for zero encoded value. */
7557 if (!inst
.operands
[i
].negative
)
7558 inst
.instruction
|= INDEX_UP
;
7559 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7564 /* inst.operands[i] was set up by parse_address. Encode it into an
7565 ARM-format mode 3 load or store instruction. Reject forms that
7566 cannot be used with such instructions. If is_t is true, reject
7567 forms that cannot be used with a T instruction (i.e. not
7570 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7572 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7574 inst
.error
= _("instruction does not accept scaled register index");
7578 encode_arm_addr_mode_common (i
, is_t
);
7580 if (inst
.operands
[i
].immisreg
)
7582 constraint ((inst
.operands
[i
].imm
== REG_PC
7583 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7585 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7587 inst
.instruction
|= inst
.operands
[i
].imm
;
7588 if (!inst
.operands
[i
].negative
)
7589 inst
.instruction
|= INDEX_UP
;
7591 else /* immediate offset in inst.reloc */
7593 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7594 && inst
.operands
[i
].writeback
),
7596 inst
.instruction
|= HWOFFSET_IMM
;
7597 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7599 /* Prefer + for zero encoded value. */
7600 if (!inst
.operands
[i
].negative
)
7601 inst
.instruction
|= INDEX_UP
;
7603 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7608 /* Write immediate bits [7:0] to the following locations:
7610 |28/24|23 19|18 16|15 4|3 0|
7611 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7613 This function is used by VMOV/VMVN/VORR/VBIC. */
7616 neon_write_immbits (unsigned immbits
)
7618 inst
.instruction
|= immbits
& 0xf;
7619 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7620 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7623 /* Invert low-order SIZE bits of XHI:XLO. */
7626 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7628 unsigned immlo
= xlo
? *xlo
: 0;
7629 unsigned immhi
= xhi
? *xhi
: 0;
7634 immlo
= (~immlo
) & 0xff;
7638 immlo
= (~immlo
) & 0xffff;
7642 immhi
= (~immhi
) & 0xffffffff;
7646 immlo
= (~immlo
) & 0xffffffff;
7660 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7664 neon_bits_same_in_bytes (unsigned imm
)
7666 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7667 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7668 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7669 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7672 /* For immediate of above form, return 0bABCD. */
7675 neon_squash_bits (unsigned imm
)
7677 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7678 | ((imm
& 0x01000000) >> 21);
7681 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7684 neon_qfloat_bits (unsigned imm
)
7686 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7689 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7690 the instruction. *OP is passed as the initial value of the op field, and
7691 may be set to a different value depending on the constant (i.e.
7692 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7693 MVN). If the immediate looks like a repeated pattern then also
7694 try smaller element sizes. */
7697 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7698 unsigned *immbits
, int *op
, int size
,
7699 enum neon_el_type type
)
7701 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7703 if (type
== NT_float
&& !float_p
)
7706 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7708 if (size
!= 32 || *op
== 1)
7710 *immbits
= neon_qfloat_bits (immlo
);
7716 if (neon_bits_same_in_bytes (immhi
)
7717 && neon_bits_same_in_bytes (immlo
))
7721 *immbits
= (neon_squash_bits (immhi
) << 4)
7722 | neon_squash_bits (immlo
);
7733 if (immlo
== (immlo
& 0x000000ff))
7738 else if (immlo
== (immlo
& 0x0000ff00))
7740 *immbits
= immlo
>> 8;
7743 else if (immlo
== (immlo
& 0x00ff0000))
7745 *immbits
= immlo
>> 16;
7748 else if (immlo
== (immlo
& 0xff000000))
7750 *immbits
= immlo
>> 24;
7753 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7755 *immbits
= (immlo
>> 8) & 0xff;
7758 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7760 *immbits
= (immlo
>> 16) & 0xff;
7764 if ((immlo
& 0xffff) != (immlo
>> 16))
7771 if (immlo
== (immlo
& 0x000000ff))
7776 else if (immlo
== (immlo
& 0x0000ff00))
7778 *immbits
= immlo
>> 8;
7782 if ((immlo
& 0xff) != (immlo
>> 8))
7787 if (immlo
== (immlo
& 0x000000ff))
7789 /* Don't allow MVN with 8-bit immediate. */
7799 #if defined BFD_HOST_64_BIT
7800 /* Returns TRUE if double precision value V may be cast
7801 to single precision without loss of accuracy. */
7804 is_double_a_single (bfd_int64_t v
)
7806 int exp
= (int)((v
>> 52) & 0x7FF);
7807 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7809 return (exp
== 0 || exp
== 0x7FF
7810 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7811 && (mantissa
& 0x1FFFFFFFl
) == 0;
7814 /* Returns a double precision value casted to single precision
7815 (ignoring the least significant bits in exponent and mantissa). */
7818 double_to_single (bfd_int64_t v
)
7820 int sign
= (int) ((v
>> 63) & 1l);
7821 int exp
= (int) ((v
>> 52) & 0x7FF);
7822 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7828 exp
= exp
- 1023 + 127;
7837 /* No denormalized numbers. */
7843 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7845 #endif /* BFD_HOST_64_BIT */
7854 static void do_vfp_nsyn_opcode (const char *);
7856 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7857 Determine whether it can be performed with a move instruction; if
7858 it can, convert inst.instruction to that move instruction and
7859 return TRUE; if it can't, convert inst.instruction to a literal-pool
7860 load and return FALSE. If this is not a valid thing to do in the
7861 current context, set inst.error and return TRUE.
7863 inst.operands[i] describes the destination register. */
7866 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7869 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7870 bfd_boolean arm_p
= (t
== CONST_ARM
);
7873 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7877 if ((inst
.instruction
& tbit
) == 0)
7879 inst
.error
= _("invalid pseudo operation");
7883 if (inst
.reloc
.exp
.X_op
!= O_constant
7884 && inst
.reloc
.exp
.X_op
!= O_symbol
7885 && inst
.reloc
.exp
.X_op
!= O_big
)
7887 inst
.error
= _("constant expression expected");
7891 if (inst
.reloc
.exp
.X_op
== O_constant
7892 || inst
.reloc
.exp
.X_op
== O_big
)
7894 #if defined BFD_HOST_64_BIT
7899 if (inst
.reloc
.exp
.X_op
== O_big
)
7901 LITTLENUM_TYPE w
[X_PRECISION
];
7904 if (inst
.reloc
.exp
.X_add_number
== -1)
7906 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7908 /* FIXME: Should we check words w[2..5] ? */
7913 #if defined BFD_HOST_64_BIT
7915 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7916 << LITTLENUM_NUMBER_OF_BITS
)
7917 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7918 << LITTLENUM_NUMBER_OF_BITS
)
7919 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7920 << LITTLENUM_NUMBER_OF_BITS
)
7921 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7923 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7924 | (l
[0] & LITTLENUM_MASK
);
7928 v
= inst
.reloc
.exp
.X_add_number
;
7930 if (!inst
.operands
[i
].issingle
)
7934 /* This can be encoded only for a low register. */
7935 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7937 /* This can be done with a mov(1) instruction. */
7938 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7939 inst
.instruction
|= v
;
7943 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7944 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7946 /* Check if on thumb2 it can be done with a mov.w, mvn or
7947 movw instruction. */
7948 unsigned int newimm
;
7949 bfd_boolean isNegated
;
7951 newimm
= encode_thumb32_immediate (v
);
7952 if (newimm
!= (unsigned int) FAIL
)
7956 newimm
= encode_thumb32_immediate (~v
);
7957 if (newimm
!= (unsigned int) FAIL
)
7961 /* The number can be loaded with a mov.w or mvn
7963 if (newimm
!= (unsigned int) FAIL
7964 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7966 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7967 | (inst
.operands
[i
].reg
<< 8));
7968 /* Change to MOVN. */
7969 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7970 inst
.instruction
|= (newimm
& 0x800) << 15;
7971 inst
.instruction
|= (newimm
& 0x700) << 4;
7972 inst
.instruction
|= (newimm
& 0x0ff);
7975 /* The number can be loaded with a movw instruction. */
7976 else if ((v
& ~0xFFFF) == 0
7977 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7979 int imm
= v
& 0xFFFF;
7981 inst
.instruction
= 0xf2400000; /* MOVW. */
7982 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7983 inst
.instruction
|= (imm
& 0xf000) << 4;
7984 inst
.instruction
|= (imm
& 0x0800) << 15;
7985 inst
.instruction
|= (imm
& 0x0700) << 4;
7986 inst
.instruction
|= (imm
& 0x00ff);
7993 int value
= encode_arm_immediate (v
);
7997 /* This can be done with a mov instruction. */
7998 inst
.instruction
&= LITERAL_MASK
;
7999 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8000 inst
.instruction
|= value
& 0xfff;
8004 value
= encode_arm_immediate (~ v
);
8007 /* This can be done with a mvn instruction. */
8008 inst
.instruction
&= LITERAL_MASK
;
8009 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8010 inst
.instruction
|= value
& 0xfff;
8014 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8017 unsigned immbits
= 0;
8018 unsigned immlo
= inst
.operands
[1].imm
;
8019 unsigned immhi
= inst
.operands
[1].regisimm
8020 ? inst
.operands
[1].reg
8021 : inst
.reloc
.exp
.X_unsigned
8023 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8024 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8025 &op
, 64, NT_invtype
);
8029 neon_invert_size (&immlo
, &immhi
, 64);
8031 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8032 &op
, 64, NT_invtype
);
8037 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8043 /* Fill other bits in vmov encoding for both thumb and arm. */
8045 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8047 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8048 neon_write_immbits (immbits
);
8056 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8057 if (inst
.operands
[i
].issingle
8058 && is_quarter_float (inst
.operands
[1].imm
)
8059 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8061 inst
.operands
[1].imm
=
8062 neon_qfloat_bits (v
);
8063 do_vfp_nsyn_opcode ("fconsts");
8067 /* If our host does not support a 64-bit type then we cannot perform
8068 the following optimization. This mean that there will be a
8069 discrepancy between the output produced by an assembler built for
8070 a 32-bit-only host and the output produced from a 64-bit host, but
8071 this cannot be helped. */
8072 #if defined BFD_HOST_64_BIT
8073 else if (!inst
.operands
[1].issingle
8074 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8076 if (is_double_a_single (v
)
8077 && is_quarter_float (double_to_single (v
)))
8079 inst
.operands
[1].imm
=
8080 neon_qfloat_bits (double_to_single (v
));
8081 do_vfp_nsyn_opcode ("fconstd");
8089 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8090 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8093 inst
.operands
[1].reg
= REG_PC
;
8094 inst
.operands
[1].isreg
= 1;
8095 inst
.operands
[1].preind
= 1;
8096 inst
.reloc
.pc_rel
= 1;
8097 inst
.reloc
.type
= (thumb_p
8098 ? BFD_RELOC_ARM_THUMB_OFFSET
8100 ? BFD_RELOC_ARM_HWLITERAL
8101 : BFD_RELOC_ARM_LITERAL
));
8105 /* inst.operands[i] was set up by parse_address. Encode it into an
8106 ARM-format instruction. Reject all forms which cannot be encoded
8107 into a coprocessor load/store instruction. If wb_ok is false,
8108 reject use of writeback; if unind_ok is false, reject use of
8109 unindexed addressing. If reloc_override is not 0, use it instead
8110 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8111 (in which case it is preserved). */
8114 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8116 if (!inst
.operands
[i
].isreg
)
8119 if (! inst
.operands
[0].isvec
)
8121 inst
.error
= _("invalid co-processor operand");
8124 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8128 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8130 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8132 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8134 gas_assert (!inst
.operands
[i
].writeback
);
8137 inst
.error
= _("instruction does not support unindexed addressing");
8140 inst
.instruction
|= inst
.operands
[i
].imm
;
8141 inst
.instruction
|= INDEX_UP
;
8145 if (inst
.operands
[i
].preind
)
8146 inst
.instruction
|= PRE_INDEX
;
8148 if (inst
.operands
[i
].writeback
)
8150 if (inst
.operands
[i
].reg
== REG_PC
)
8152 inst
.error
= _("pc may not be used with write-back");
8157 inst
.error
= _("instruction does not support writeback");
8160 inst
.instruction
|= WRITE_BACK
;
8164 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8165 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8166 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8167 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8170 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8172 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8175 /* Prefer + for zero encoded value. */
8176 if (!inst
.operands
[i
].negative
)
8177 inst
.instruction
|= INDEX_UP
;
8182 /* Functions for instruction encoding, sorted by sub-architecture.
8183 First some generics; their names are taken from the conventional
8184 bit positions for register arguments in ARM format instructions. */
8194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8206 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8207 inst
.instruction
|= inst
.operands
[1].reg
;
8213 inst
.instruction
|= inst
.operands
[0].reg
;
8214 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8221 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8227 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8228 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8239 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8241 if (ARM_CPU_IS_ANY (cpu_variant
))
8243 as_tsktsk ("%s", msg
);
8246 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8258 unsigned Rn
= inst
.operands
[2].reg
;
8259 /* Enforce restrictions on SWP instruction. */
8260 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8262 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8263 _("Rn must not overlap other operands"));
8265 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8267 if (!check_obsolete (&arm_ext_v8
,
8268 _("swp{b} use is obsoleted for ARMv8 and later"))
8269 && warn_on_deprecated
8270 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8271 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8275 inst
.instruction
|= inst
.operands
[1].reg
;
8276 inst
.instruction
|= Rn
<< 16;
8282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8283 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8284 inst
.instruction
|= inst
.operands
[2].reg
;
8290 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8291 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8292 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8293 || inst
.reloc
.exp
.X_add_number
!= 0),
8295 inst
.instruction
|= inst
.operands
[0].reg
;
8296 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8297 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8303 inst
.instruction
|= inst
.operands
[0].imm
;
8309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8310 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8313 /* ARM instructions, in alphabetical order by function name (except
8314 that wrapper functions appear immediately after the function they
8317 /* This is a pseudo-op of the form "adr rd, label" to be converted
8318 into a relative address of the form "add rd, pc, #label-.-8". */
8323 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8325 /* Frag hacking will turn this into a sub instruction if the offset turns
8326 out to be negative. */
8327 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8328 inst
.reloc
.pc_rel
= 1;
8329 inst
.reloc
.exp
.X_add_number
-= 8;
8332 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8333 into a relative address of the form:
8334 add rd, pc, #low(label-.-8)"
8335 add rd, rd, #high(label-.-8)" */
8340 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8342 /* Frag hacking will turn this into a sub instruction if the offset turns
8343 out to be negative. */
8344 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8345 inst
.reloc
.pc_rel
= 1;
8346 inst
.size
= INSN_SIZE
* 2;
8347 inst
.reloc
.exp
.X_add_number
-= 8;
8353 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8354 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8356 if (!inst
.operands
[1].present
)
8357 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8359 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8360 encode_arm_shifter_operand (2);
8366 if (inst
.operands
[0].present
)
8367 inst
.instruction
|= inst
.operands
[0].imm
;
8369 inst
.instruction
|= 0xf;
8375 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8376 constraint (msb
> 32, _("bit-field extends past end of register"));
8377 /* The instruction encoding stores the LSB and MSB,
8378 not the LSB and width. */
8379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8380 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8381 inst
.instruction
|= (msb
- 1) << 16;
8389 /* #0 in second position is alternative syntax for bfc, which is
8390 the same instruction but with REG_PC in the Rm field. */
8391 if (!inst
.operands
[1].isreg
)
8392 inst
.operands
[1].reg
= REG_PC
;
8394 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8395 constraint (msb
> 32, _("bit-field extends past end of register"));
8396 /* The instruction encoding stores the LSB and MSB,
8397 not the LSB and width. */
8398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8399 inst
.instruction
|= inst
.operands
[1].reg
;
8400 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8401 inst
.instruction
|= (msb
- 1) << 16;
8407 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8408 _("bit-field extends past end of register"));
8409 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8410 inst
.instruction
|= inst
.operands
[1].reg
;
8411 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8412 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8415 /* ARM V5 breakpoint instruction (argument parse)
8416 BKPT <16 bit unsigned immediate>
8417 Instruction is not conditional.
8418 The bit pattern given in insns[] has the COND_ALWAYS condition,
8419 and it is an error if the caller tried to override that. */
8424 /* Top 12 of 16 bits to bits 19:8. */
8425 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8427 /* Bottom 4 of 16 bits to bits 3:0. */
8428 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8432 encode_branch (int default_reloc
)
8434 if (inst
.operands
[0].hasreloc
)
8436 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8437 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8438 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8439 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8440 ? BFD_RELOC_ARM_PLT32
8441 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8444 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8445 inst
.reloc
.pc_rel
= 1;
8452 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8453 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8456 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8463 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8465 if (inst
.cond
== COND_ALWAYS
)
8466 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8468 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8472 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8475 /* ARM V5 branch-link-exchange instruction (argument parse)
8476 BLX <target_addr> ie BLX(1)
8477 BLX{<condition>} <Rm> ie BLX(2)
8478 Unfortunately, there are two different opcodes for this mnemonic.
8479 So, the insns[].value is not used, and the code here zaps values
8480 into inst.instruction.
8481 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8486 if (inst
.operands
[0].isreg
)
8488 /* Arg is a register; the opcode provided by insns[] is correct.
8489 It is not illegal to do "blx pc", just useless. */
8490 if (inst
.operands
[0].reg
== REG_PC
)
8491 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8493 inst
.instruction
|= inst
.operands
[0].reg
;
8497 /* Arg is an address; this instruction cannot be executed
8498 conditionally, and the opcode must be adjusted.
8499 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8500 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8501 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8502 inst
.instruction
= 0xfa000000;
8503 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8510 bfd_boolean want_reloc
;
8512 if (inst
.operands
[0].reg
== REG_PC
)
8513 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8515 inst
.instruction
|= inst
.operands
[0].reg
;
8516 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8517 it is for ARMv4t or earlier. */
8518 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8519 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8523 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8528 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8532 /* ARM v5TEJ. Jump to Jazelle code. */
8537 if (inst
.operands
[0].reg
== REG_PC
)
8538 as_tsktsk (_("use of r15 in bxj is not really useful"));
8540 inst
.instruction
|= inst
.operands
[0].reg
;
8543 /* Co-processor data operation:
8544 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8545 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8549 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8550 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8551 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8552 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8553 inst
.instruction
|= inst
.operands
[4].reg
;
8554 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8560 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8561 encode_arm_shifter_operand (1);
8564 /* Transfer between coprocessor and ARM registers.
8565 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8570 No special properties. */
8572 struct deprecated_coproc_regs_s
8579 arm_feature_set deprecated
;
8580 arm_feature_set obsoleted
;
8581 const char *dep_msg
;
8582 const char *obs_msg
;
8585 #define DEPR_ACCESS_V8 \
8586 N_("This coprocessor register access is deprecated in ARMv8")
8588 /* Table of all deprecated coprocessor registers. */
8589 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8591 {15, 0, 7, 10, 5, /* CP15DMB. */
8592 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8593 DEPR_ACCESS_V8
, NULL
},
8594 {15, 0, 7, 10, 4, /* CP15DSB. */
8595 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8596 DEPR_ACCESS_V8
, NULL
},
8597 {15, 0, 7, 5, 4, /* CP15ISB. */
8598 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8599 DEPR_ACCESS_V8
, NULL
},
8600 {14, 6, 1, 0, 0, /* TEEHBR. */
8601 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8602 DEPR_ACCESS_V8
, NULL
},
8603 {14, 6, 0, 0, 0, /* TEECR. */
8604 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8605 DEPR_ACCESS_V8
, NULL
},
8608 #undef DEPR_ACCESS_V8
8610 static const size_t deprecated_coproc_reg_count
=
8611 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8619 Rd
= inst
.operands
[2].reg
;
8622 if (inst
.instruction
== 0xee000010
8623 || inst
.instruction
== 0xfe000010)
8625 reject_bad_reg (Rd
);
8628 constraint (Rd
== REG_SP
, BAD_SP
);
8633 if (inst
.instruction
== 0xe000010)
8634 constraint (Rd
== REG_PC
, BAD_PC
);
8637 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8639 const struct deprecated_coproc_regs_s
*r
=
8640 deprecated_coproc_regs
+ i
;
8642 if (inst
.operands
[0].reg
== r
->cp
8643 && inst
.operands
[1].imm
== r
->opc1
8644 && inst
.operands
[3].reg
== r
->crn
8645 && inst
.operands
[4].reg
== r
->crm
8646 && inst
.operands
[5].imm
== r
->opc2
)
8648 if (! ARM_CPU_IS_ANY (cpu_variant
)
8649 && warn_on_deprecated
8650 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8651 as_tsktsk ("%s", r
->dep_msg
);
8655 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8656 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8657 inst
.instruction
|= Rd
<< 12;
8658 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8659 inst
.instruction
|= inst
.operands
[4].reg
;
8660 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8663 /* Transfer between coprocessor register and pair of ARM registers.
8664 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8669 Two XScale instructions are special cases of these:
8671 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8672 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8674 Result unpredictable if Rd or Rn is R15. */
8681 Rd
= inst
.operands
[2].reg
;
8682 Rn
= inst
.operands
[3].reg
;
8686 reject_bad_reg (Rd
);
8687 reject_bad_reg (Rn
);
8691 constraint (Rd
== REG_PC
, BAD_PC
);
8692 constraint (Rn
== REG_PC
, BAD_PC
);
8695 /* Only check the MRRC{2} variants. */
8696 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8698 /* If Rd == Rn, error that the operation is
8699 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8700 constraint (Rd
== Rn
, BAD_OVERLAP
);
8703 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8704 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8705 inst
.instruction
|= Rd
<< 12;
8706 inst
.instruction
|= Rn
<< 16;
8707 inst
.instruction
|= inst
.operands
[4].reg
;
8713 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8714 if (inst
.operands
[1].present
)
8716 inst
.instruction
|= CPSI_MMOD
;
8717 inst
.instruction
|= inst
.operands
[1].imm
;
8724 inst
.instruction
|= inst
.operands
[0].imm
;
8730 unsigned Rd
, Rn
, Rm
;
8732 Rd
= inst
.operands
[0].reg
;
8733 Rn
= (inst
.operands
[1].present
8734 ? inst
.operands
[1].reg
: Rd
);
8735 Rm
= inst
.operands
[2].reg
;
8737 constraint ((Rd
== REG_PC
), BAD_PC
);
8738 constraint ((Rn
== REG_PC
), BAD_PC
);
8739 constraint ((Rm
== REG_PC
), BAD_PC
);
8741 inst
.instruction
|= Rd
<< 16;
8742 inst
.instruction
|= Rn
<< 0;
8743 inst
.instruction
|= Rm
<< 8;
8749 /* There is no IT instruction in ARM mode. We
8750 process it to do the validation as if in
8751 thumb mode, just in case the code gets
8752 assembled for thumb using the unified syntax. */
8757 set_it_insn_type (IT_INSN
);
8758 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8759 now_it
.cc
= inst
.operands
[0].imm
;
8763 /* If there is only one register in the register list,
8764 then return its register number. Otherwise return -1. */
8766 only_one_reg_in_list (int range
)
8768 int i
= ffs (range
) - 1;
8769 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8773 encode_ldmstm(int from_push_pop_mnem
)
8775 int base_reg
= inst
.operands
[0].reg
;
8776 int range
= inst
.operands
[1].imm
;
8779 inst
.instruction
|= base_reg
<< 16;
8780 inst
.instruction
|= range
;
8782 if (inst
.operands
[1].writeback
)
8783 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8785 if (inst
.operands
[0].writeback
)
8787 inst
.instruction
|= WRITE_BACK
;
8788 /* Check for unpredictable uses of writeback. */
8789 if (inst
.instruction
& LOAD_BIT
)
8791 /* Not allowed in LDM type 2. */
8792 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8793 && ((range
& (1 << REG_PC
)) == 0))
8794 as_warn (_("writeback of base register is UNPREDICTABLE"));
8795 /* Only allowed if base reg not in list for other types. */
8796 else if (range
& (1 << base_reg
))
8797 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8801 /* Not allowed for type 2. */
8802 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8803 as_warn (_("writeback of base register is UNPREDICTABLE"));
8804 /* Only allowed if base reg not in list, or first in list. */
8805 else if ((range
& (1 << base_reg
))
8806 && (range
& ((1 << base_reg
) - 1)))
8807 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8811 /* If PUSH/POP has only one register, then use the A2 encoding. */
8812 one_reg
= only_one_reg_in_list (range
);
8813 if (from_push_pop_mnem
&& one_reg
>= 0)
8815 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8817 inst
.instruction
&= A_COND_MASK
;
8818 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8819 inst
.instruction
|= one_reg
<< 12;
8826 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8829 /* ARMv5TE load-consecutive (argument parse)
8838 constraint (inst
.operands
[0].reg
% 2 != 0,
8839 _("first transfer register must be even"));
8840 constraint (inst
.operands
[1].present
8841 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8842 _("can only transfer two consecutive registers"));
8843 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8844 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8846 if (!inst
.operands
[1].present
)
8847 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8849 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8850 register and the first register written; we have to diagnose
8851 overlap between the base and the second register written here. */
8853 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8854 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8855 as_warn (_("base register written back, and overlaps "
8856 "second transfer register"));
8858 if (!(inst
.instruction
& V4_STR_BIT
))
8860 /* For an index-register load, the index register must not overlap the
8861 destination (even if not write-back). */
8862 if (inst
.operands
[2].immisreg
8863 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8864 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8865 as_warn (_("index register overlaps transfer register"));
8867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8868 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8874 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8875 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8876 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8877 || inst
.operands
[1].negative
8878 /* This can arise if the programmer has written
8880 or if they have mistakenly used a register name as the last
8883 It is very difficult to distinguish between these two cases
8884 because "rX" might actually be a label. ie the register
8885 name has been occluded by a symbol of the same name. So we
8886 just generate a general 'bad addressing mode' type error
8887 message and leave it up to the programmer to discover the
8888 true cause and fix their mistake. */
8889 || (inst
.operands
[1].reg
== REG_PC
),
8892 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8893 || inst
.reloc
.exp
.X_add_number
!= 0,
8894 _("offset must be zero in ARM encoding"));
8896 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8899 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8900 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8906 constraint (inst
.operands
[0].reg
% 2 != 0,
8907 _("even register required"));
8908 constraint (inst
.operands
[1].present
8909 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8910 _("can only load two consecutive registers"));
8911 /* If op 1 were present and equal to PC, this function wouldn't
8912 have been called in the first place. */
8913 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8919 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8920 which is not a multiple of four is UNPREDICTABLE. */
8922 check_ldr_r15_aligned (void)
8924 constraint (!(inst
.operands
[1].immisreg
)
8925 && (inst
.operands
[0].reg
== REG_PC
8926 && inst
.operands
[1].reg
== REG_PC
8927 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8928 _("ldr to register 15 must be 4-byte alligned"));
8934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8935 if (!inst
.operands
[1].isreg
)
8936 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8938 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8939 check_ldr_r15_aligned ();
8945 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8947 if (inst
.operands
[1].preind
)
8949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8950 || inst
.reloc
.exp
.X_add_number
!= 0,
8951 _("this instruction requires a post-indexed address"));
8953 inst
.operands
[1].preind
= 0;
8954 inst
.operands
[1].postind
= 1;
8955 inst
.operands
[1].writeback
= 1;
8957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8958 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8961 /* Halfword and signed-byte load/store operations. */
8966 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8968 if (!inst
.operands
[1].isreg
)
8969 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8971 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8977 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8979 if (inst
.operands
[1].preind
)
8981 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8982 || inst
.reloc
.exp
.X_add_number
!= 0,
8983 _("this instruction requires a post-indexed address"));
8985 inst
.operands
[1].preind
= 0;
8986 inst
.operands
[1].postind
= 1;
8987 inst
.operands
[1].writeback
= 1;
8989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8990 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8993 /* Co-processor register load/store.
8994 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8998 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8999 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9000 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9006 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9007 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9008 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9009 && !(inst
.instruction
& 0x00400000))
9010 as_tsktsk (_("Rd and Rm should be different in mla"));
9012 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9013 inst
.instruction
|= inst
.operands
[1].reg
;
9014 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9015 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9021 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9022 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9025 encode_arm_shifter_operand (1);
9028 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9035 top
= (inst
.instruction
& 0x00400000) != 0;
9036 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9037 _(":lower16: not allowed this instruction"));
9038 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9039 _(":upper16: not allowed instruction"));
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9041 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9043 imm
= inst
.reloc
.exp
.X_add_number
;
9044 /* The value is in two pieces: 0:11, 16:19. */
9045 inst
.instruction
|= (imm
& 0x00000fff);
9046 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9051 do_vfp_nsyn_mrs (void)
9053 if (inst
.operands
[0].isvec
)
9055 if (inst
.operands
[1].reg
!= 1)
9056 first_error (_("operand 1 must be FPSCR"));
9057 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9058 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9059 do_vfp_nsyn_opcode ("fmstat");
9061 else if (inst
.operands
[1].isvec
)
9062 do_vfp_nsyn_opcode ("fmrx");
9070 do_vfp_nsyn_msr (void)
9072 if (inst
.operands
[0].isvec
)
9073 do_vfp_nsyn_opcode ("fmxr");
9083 unsigned Rt
= inst
.operands
[0].reg
;
9085 if (thumb_mode
&& Rt
== REG_SP
)
9087 inst
.error
= BAD_SP
;
9091 /* APSR_ sets isvec. All other refs to PC are illegal. */
9092 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9094 inst
.error
= BAD_PC
;
9098 /* If we get through parsing the register name, we just insert the number
9099 generated into the instruction without further validation. */
9100 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9101 inst
.instruction
|= (Rt
<< 12);
9107 unsigned Rt
= inst
.operands
[1].reg
;
9110 reject_bad_reg (Rt
);
9111 else if (Rt
== REG_PC
)
9113 inst
.error
= BAD_PC
;
9117 /* If we get through parsing the register name, we just insert the number
9118 generated into the instruction without further validation. */
9119 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9120 inst
.instruction
|= (Rt
<< 12);
9128 if (do_vfp_nsyn_mrs () == SUCCESS
)
9131 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9134 if (inst
.operands
[1].isreg
)
9136 br
= inst
.operands
[1].reg
;
9137 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9138 as_bad (_("bad register for mrs"));
9142 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9143 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9145 _("'APSR', 'CPSR' or 'SPSR' expected"));
9146 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9149 inst
.instruction
|= br
;
9152 /* Two possible forms:
9153 "{C|S}PSR_<field>, Rm",
9154 "{C|S}PSR_f, #expression". */
9159 if (do_vfp_nsyn_msr () == SUCCESS
)
9162 inst
.instruction
|= inst
.operands
[0].imm
;
9163 if (inst
.operands
[1].isreg
)
9164 inst
.instruction
|= inst
.operands
[1].reg
;
9167 inst
.instruction
|= INST_IMMEDIATE
;
9168 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9169 inst
.reloc
.pc_rel
= 0;
9176 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9178 if (!inst
.operands
[2].present
)
9179 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9180 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9181 inst
.instruction
|= inst
.operands
[1].reg
;
9182 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9184 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9185 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9186 as_tsktsk (_("Rd and Rm should be different in mul"));
9189 /* Long Multiply Parser
9190 UMULL RdLo, RdHi, Rm, Rs
9191 SMULL RdLo, RdHi, Rm, Rs
9192 UMLAL RdLo, RdHi, Rm, Rs
9193 SMLAL RdLo, RdHi, Rm, Rs. */
9198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9200 inst
.instruction
|= inst
.operands
[2].reg
;
9201 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9203 /* rdhi and rdlo must be different. */
9204 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9205 as_tsktsk (_("rdhi and rdlo must be different"));
9207 /* rdhi, rdlo and rm must all be different before armv6. */
9208 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9209 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9210 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9211 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9217 if (inst
.operands
[0].present
9218 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9220 /* Architectural NOP hints are CPSR sets with no bits selected. */
9221 inst
.instruction
&= 0xf0000000;
9222 inst
.instruction
|= 0x0320f000;
9223 if (inst
.operands
[0].present
)
9224 inst
.instruction
|= inst
.operands
[0].imm
;
9228 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9229 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9230 Condition defaults to COND_ALWAYS.
9231 Error if Rd, Rn or Rm are R15. */
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9237 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9238 inst
.instruction
|= inst
.operands
[2].reg
;
9239 if (inst
.operands
[3].present
)
9240 encode_arm_shift (3);
9243 /* ARM V6 PKHTB (Argument Parse). */
9248 if (!inst
.operands
[3].present
)
9250 /* If the shift specifier is omitted, turn the instruction
9251 into pkhbt rd, rm, rn. */
9252 inst
.instruction
&= 0xfff00010;
9253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9254 inst
.instruction
|= inst
.operands
[1].reg
;
9255 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9261 inst
.instruction
|= inst
.operands
[2].reg
;
9262 encode_arm_shift (3);
9266 /* ARMv5TE: Preload-Cache
9267 MP Extensions: Preload for write
9271 Syntactically, like LDR with B=1, W=0, L=1. */
9276 constraint (!inst
.operands
[0].isreg
,
9277 _("'[' expected after PLD mnemonic"));
9278 constraint (inst
.operands
[0].postind
,
9279 _("post-indexed expression used in preload instruction"));
9280 constraint (inst
.operands
[0].writeback
,
9281 _("writeback used in preload instruction"));
9282 constraint (!inst
.operands
[0].preind
,
9283 _("unindexed addressing used in preload instruction"));
9284 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9287 /* ARMv7: PLI <addr_mode> */
9291 constraint (!inst
.operands
[0].isreg
,
9292 _("'[' expected after PLI mnemonic"));
9293 constraint (inst
.operands
[0].postind
,
9294 _("post-indexed expression used in preload instruction"));
9295 constraint (inst
.operands
[0].writeback
,
9296 _("writeback used in preload instruction"));
9297 constraint (!inst
.operands
[0].preind
,
9298 _("unindexed addressing used in preload instruction"));
9299 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9300 inst
.instruction
&= ~PRE_INDEX
;
9306 constraint (inst
.operands
[0].writeback
,
9307 _("push/pop do not support {reglist}^"));
9308 inst
.operands
[1] = inst
.operands
[0];
9309 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9310 inst
.operands
[0].isreg
= 1;
9311 inst
.operands
[0].writeback
= 1;
9312 inst
.operands
[0].reg
= REG_SP
;
9313 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9316 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9317 word at the specified address and the following word
9319 Unconditionally executed.
9320 Error if Rn is R15. */
9325 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9326 if (inst
.operands
[0].writeback
)
9327 inst
.instruction
|= WRITE_BACK
;
9330 /* ARM V6 ssat (argument parse). */
9335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9336 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9337 inst
.instruction
|= inst
.operands
[2].reg
;
9339 if (inst
.operands
[3].present
)
9340 encode_arm_shift (3);
9343 /* ARM V6 usat (argument parse). */
9348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9349 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9350 inst
.instruction
|= inst
.operands
[2].reg
;
9352 if (inst
.operands
[3].present
)
9353 encode_arm_shift (3);
9356 /* ARM V6 ssat16 (argument parse). */
9361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9362 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9363 inst
.instruction
|= inst
.operands
[2].reg
;
9369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9370 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9371 inst
.instruction
|= inst
.operands
[2].reg
;
9374 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9375 preserving the other bits.
9377 setend <endian_specifier>, where <endian_specifier> is either
9383 if (warn_on_deprecated
9384 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9385 as_tsktsk (_("setend use is deprecated for ARMv8"));
9387 if (inst
.operands
[0].imm
)
9388 inst
.instruction
|= 0x200;
9394 unsigned int Rm
= (inst
.operands
[1].present
9395 ? inst
.operands
[1].reg
9396 : inst
.operands
[0].reg
);
9398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9399 inst
.instruction
|= Rm
;
9400 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9402 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9403 inst
.instruction
|= SHIFT_BY_REG
;
9404 /* PR 12854: Error on extraneous shifts. */
9405 constraint (inst
.operands
[2].shifted
,
9406 _("extraneous shift as part of operand to shift insn"));
9409 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9415 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9416 inst
.reloc
.pc_rel
= 0;
9422 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9423 inst
.reloc
.pc_rel
= 0;
9429 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9430 inst
.reloc
.pc_rel
= 0;
9436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9437 _("selected processor does not support SETPAN instruction"));
9439 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9445 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9446 _("selected processor does not support SETPAN instruction"));
9448 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9451 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9452 SMLAxy{cond} Rd,Rm,Rs,Rn
9453 SMLAWy{cond} Rd,Rm,Rs,Rn
9454 Error if any register is R15. */
9459 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9460 inst
.instruction
|= inst
.operands
[1].reg
;
9461 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9462 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9465 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9466 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9467 Error if any register is R15.
9468 Warning if Rdlo == Rdhi. */
9473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9474 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9475 inst
.instruction
|= inst
.operands
[2].reg
;
9476 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9478 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9479 as_tsktsk (_("rdhi and rdlo must be different"));
9482 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9483 SMULxy{cond} Rd,Rm,Rs
9484 Error if any register is R15. */
9489 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9490 inst
.instruction
|= inst
.operands
[1].reg
;
9491 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9494 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9495 the same for both ARM and Thumb-2. */
9502 if (inst
.operands
[0].present
)
9504 reg
= inst
.operands
[0].reg
;
9505 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9510 inst
.instruction
|= reg
<< 16;
9511 inst
.instruction
|= inst
.operands
[1].imm
;
9512 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9513 inst
.instruction
|= WRITE_BACK
;
9516 /* ARM V6 strex (argument parse). */
9521 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9522 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9523 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9524 || inst
.operands
[2].negative
9525 /* See comment in do_ldrex(). */
9526 || (inst
.operands
[2].reg
== REG_PC
),
9529 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9530 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9532 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9533 || inst
.reloc
.exp
.X_add_number
!= 0,
9534 _("offset must be zero in ARM encoding"));
9536 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9537 inst
.instruction
|= inst
.operands
[1].reg
;
9538 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9539 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9545 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9546 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9547 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9548 || inst
.operands
[2].negative
,
9551 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9552 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9560 constraint (inst
.operands
[1].reg
% 2 != 0,
9561 _("even register required"));
9562 constraint (inst
.operands
[2].present
9563 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9564 _("can only store two consecutive registers"));
9565 /* If op 2 were present and equal to PC, this function wouldn't
9566 have been called in the first place. */
9567 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9569 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9570 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9571 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9574 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9575 inst
.instruction
|= inst
.operands
[1].reg
;
9576 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9583 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9584 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9592 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9593 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9598 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9599 extends it to 32-bits, and adds the result to a value in another
9600 register. You can specify a rotation by 0, 8, 16, or 24 bits
9601 before extracting the 16-bit value.
9602 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9603 Condition defaults to COND_ALWAYS.
9604 Error if any register uses R15. */
9609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9610 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[2].reg
;
9612 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9617 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9618 Condition defaults to COND_ALWAYS.
9619 Error if any register uses R15. */
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9625 inst
.instruction
|= inst
.operands
[1].reg
;
9626 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9629 /* VFP instructions. In a logical order: SP variant first, monad
9630 before dyad, arithmetic then move then load/store. */
9633 do_vfp_sp_monadic (void)
9635 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9636 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9640 do_vfp_sp_dyadic (void)
9642 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9643 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9644 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9648 do_vfp_sp_compare_z (void)
9650 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9654 do_vfp_dp_sp_cvt (void)
9656 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9657 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9661 do_vfp_sp_dp_cvt (void)
9663 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9664 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9668 do_vfp_reg_from_sp (void)
9670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9671 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9675 do_vfp_reg2_from_sp2 (void)
9677 constraint (inst
.operands
[2].imm
!= 2,
9678 _("only two consecutive VFP SP registers allowed here"));
9679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9680 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9681 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9685 do_vfp_sp_from_reg (void)
9687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9688 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9692 do_vfp_sp2_from_reg2 (void)
9694 constraint (inst
.operands
[0].imm
!= 2,
9695 _("only two consecutive VFP SP registers allowed here"));
9696 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9697 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9698 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9702 do_vfp_sp_ldst (void)
9704 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9705 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9709 do_vfp_dp_ldst (void)
9711 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9712 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9717 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9719 if (inst
.operands
[0].writeback
)
9720 inst
.instruction
|= WRITE_BACK
;
9722 constraint (ldstm_type
!= VFP_LDSTMIA
,
9723 _("this addressing mode requires base-register writeback"));
9724 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9725 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9726 inst
.instruction
|= inst
.operands
[1].imm
;
9730 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9734 if (inst
.operands
[0].writeback
)
9735 inst
.instruction
|= WRITE_BACK
;
9737 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9738 _("this addressing mode requires base-register writeback"));
9740 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9741 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9743 count
= inst
.operands
[1].imm
<< 1;
9744 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9747 inst
.instruction
|= count
;
9751 do_vfp_sp_ldstmia (void)
9753 vfp_sp_ldstm (VFP_LDSTMIA
);
9757 do_vfp_sp_ldstmdb (void)
9759 vfp_sp_ldstm (VFP_LDSTMDB
);
9763 do_vfp_dp_ldstmia (void)
9765 vfp_dp_ldstm (VFP_LDSTMIA
);
9769 do_vfp_dp_ldstmdb (void)
9771 vfp_dp_ldstm (VFP_LDSTMDB
);
9775 do_vfp_xp_ldstmia (void)
9777 vfp_dp_ldstm (VFP_LDSTMIAX
);
9781 do_vfp_xp_ldstmdb (void)
9783 vfp_dp_ldstm (VFP_LDSTMDBX
);
9787 do_vfp_dp_rd_rm (void)
9789 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9790 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9794 do_vfp_dp_rn_rd (void)
9796 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9797 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9801 do_vfp_dp_rd_rn (void)
9803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9804 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9808 do_vfp_dp_rd_rn_rm (void)
9810 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9811 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9812 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9822 do_vfp_dp_rm_rd_rn (void)
9824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9825 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9826 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9829 /* VFPv3 instructions. */
9831 do_vfp_sp_const (void)
9833 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9834 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9835 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9839 do_vfp_dp_const (void)
9841 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9842 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9843 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9847 vfp_conv (int srcsize
)
9849 int immbits
= srcsize
- inst
.operands
[1].imm
;
9851 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9853 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9854 i.e. immbits must be in range 0 - 16. */
9855 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9858 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9860 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9861 i.e. immbits must be in range 0 - 31. */
9862 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9866 inst
.instruction
|= (immbits
& 1) << 5;
9867 inst
.instruction
|= (immbits
>> 1);
9871 do_vfp_sp_conv_16 (void)
9873 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9878 do_vfp_dp_conv_16 (void)
9880 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9885 do_vfp_sp_conv_32 (void)
9887 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9892 do_vfp_dp_conv_32 (void)
9894 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9898 /* FPA instructions. Also in a logical order. */
9903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9904 inst
.instruction
|= inst
.operands
[1].reg
;
9908 do_fpa_ldmstm (void)
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9911 switch (inst
.operands
[1].imm
)
9913 case 1: inst
.instruction
|= CP_T_X
; break;
9914 case 2: inst
.instruction
|= CP_T_Y
; break;
9915 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9920 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9922 /* The instruction specified "ea" or "fd", so we can only accept
9923 [Rn]{!}. The instruction does not really support stacking or
9924 unstacking, so we have to emulate these by setting appropriate
9925 bits and offsets. */
9926 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9927 || inst
.reloc
.exp
.X_add_number
!= 0,
9928 _("this instruction does not support indexing"));
9930 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9931 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9933 if (!(inst
.instruction
& INDEX_UP
))
9934 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9936 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9938 inst
.operands
[2].preind
= 0;
9939 inst
.operands
[2].postind
= 1;
9943 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9946 /* iWMMXt instructions: strictly in alphabetical order. */
9949 do_iwmmxt_tandorc (void)
9951 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9955 do_iwmmxt_textrc (void)
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9958 inst
.instruction
|= inst
.operands
[1].imm
;
9962 do_iwmmxt_textrm (void)
9964 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9965 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9966 inst
.instruction
|= inst
.operands
[2].imm
;
9970 do_iwmmxt_tinsr (void)
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9973 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9974 inst
.instruction
|= inst
.operands
[2].imm
;
9978 do_iwmmxt_tmia (void)
9980 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9981 inst
.instruction
|= inst
.operands
[1].reg
;
9982 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9986 do_iwmmxt_waligni (void)
9988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9989 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[2].reg
;
9991 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9995 do_iwmmxt_wmerge (void)
9997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9999 inst
.instruction
|= inst
.operands
[2].reg
;
10000 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10004 do_iwmmxt_wmov (void)
10006 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10008 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10009 inst
.instruction
|= inst
.operands
[1].reg
;
10013 do_iwmmxt_wldstbh (void)
10016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10018 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10020 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10021 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10025 do_iwmmxt_wldstw (void)
10027 /* RIWR_RIWC clears .isreg for a control register. */
10028 if (!inst
.operands
[0].isreg
)
10030 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10031 inst
.instruction
|= 0xf0000000;
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10035 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10039 do_iwmmxt_wldstd (void)
10041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10042 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10043 && inst
.operands
[1].immisreg
)
10045 inst
.instruction
&= ~0x1a000ff;
10046 inst
.instruction
|= (0xfU
<< 28);
10047 if (inst
.operands
[1].preind
)
10048 inst
.instruction
|= PRE_INDEX
;
10049 if (!inst
.operands
[1].negative
)
10050 inst
.instruction
|= INDEX_UP
;
10051 if (inst
.operands
[1].writeback
)
10052 inst
.instruction
|= WRITE_BACK
;
10053 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10054 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10055 inst
.instruction
|= inst
.operands
[1].imm
;
10058 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10062 do_iwmmxt_wshufh (void)
10064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10065 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10066 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10067 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10071 do_iwmmxt_wzero (void)
10073 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10074 inst
.instruction
|= inst
.operands
[0].reg
;
10075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10080 do_iwmmxt_wrwrwr_or_imm5 (void)
10082 if (inst
.operands
[2].isreg
)
10085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10086 _("immediate operand requires iWMMXt2"));
10088 if (inst
.operands
[2].imm
== 0)
10090 switch ((inst
.instruction
>> 20) & 0xf)
10096 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10097 inst
.operands
[2].imm
= 16;
10098 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10104 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10105 inst
.operands
[2].imm
= 32;
10106 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10113 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10115 wrn
= (inst
.instruction
>> 16) & 0xf;
10116 inst
.instruction
&= 0xff0fff0f;
10117 inst
.instruction
|= wrn
;
10118 /* Bail out here; the instruction is now assembled. */
10123 /* Map 32 -> 0, etc. */
10124 inst
.operands
[2].imm
&= 0x1f;
10125 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10129 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10130 operations first, then control, shift, and load/store. */
10132 /* Insns like "foo X,Y,Z". */
10135 do_mav_triple (void)
10137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10138 inst
.instruction
|= inst
.operands
[1].reg
;
10139 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10142 /* Insns like "foo W,X,Y,Z".
10143 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10148 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10149 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10150 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10151 inst
.instruction
|= inst
.operands
[3].reg
;
10154 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10156 do_mav_dspsc (void)
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10161 /* Maverick shift immediate instructions.
10162 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10163 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10166 do_mav_shift (void)
10168 int imm
= inst
.operands
[2].imm
;
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10173 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10174 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10175 Bit 4 should be 0. */
10176 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10178 inst
.instruction
|= imm
;
10181 /* XScale instructions. Also sorted arithmetic before move. */
10183 /* Xscale multiply-accumulate (argument parse)
10186 MIAxycc acc0,Rm,Rs. */
10191 inst
.instruction
|= inst
.operands
[1].reg
;
10192 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10195 /* Xscale move-accumulator-register (argument parse)
10197 MARcc acc0,RdLo,RdHi. */
10202 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10203 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10206 /* Xscale move-register-accumulator (argument parse)
10208 MRAcc RdLo,RdHi,acc0. */
10213 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10214 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10215 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10218 /* Encoding functions relevant only to Thumb. */
10220 /* inst.operands[i] is a shifted-register operand; encode
10221 it into inst.instruction in the format used by Thumb32. */
10224 encode_thumb32_shifted_operand (int i
)
10226 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10227 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10229 constraint (inst
.operands
[i
].immisreg
,
10230 _("shift by register not allowed in thumb mode"));
10231 inst
.instruction
|= inst
.operands
[i
].reg
;
10232 if (shift
== SHIFT_RRX
)
10233 inst
.instruction
|= SHIFT_ROR
<< 4;
10236 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10237 _("expression too complex"));
10239 constraint (value
> 32
10240 || (value
== 32 && (shift
== SHIFT_LSL
10241 || shift
== SHIFT_ROR
)),
10242 _("shift expression is too large"));
10246 else if (value
== 32)
10249 inst
.instruction
|= shift
<< 4;
10250 inst
.instruction
|= (value
& 0x1c) << 10;
10251 inst
.instruction
|= (value
& 0x03) << 6;
10256 /* inst.operands[i] was set up by parse_address. Encode it into a
10257 Thumb32 format load or store instruction. Reject forms that cannot
10258 be used with such instructions. If is_t is true, reject forms that
10259 cannot be used with a T instruction; if is_d is true, reject forms
10260 that cannot be used with a D instruction. If it is a store insn,
10261 reject PC in Rn. */
10264 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10266 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10268 constraint (!inst
.operands
[i
].isreg
,
10269 _("Instruction does not support =N addresses"));
10271 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10272 if (inst
.operands
[i
].immisreg
)
10274 constraint (is_pc
, BAD_PC_ADDRESSING
);
10275 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10276 constraint (inst
.operands
[i
].negative
,
10277 _("Thumb does not support negative register indexing"));
10278 constraint (inst
.operands
[i
].postind
,
10279 _("Thumb does not support register post-indexing"));
10280 constraint (inst
.operands
[i
].writeback
,
10281 _("Thumb does not support register indexing with writeback"));
10282 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10283 _("Thumb supports only LSL in shifted register indexing"));
10285 inst
.instruction
|= inst
.operands
[i
].imm
;
10286 if (inst
.operands
[i
].shifted
)
10288 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10289 _("expression too complex"));
10290 constraint (inst
.reloc
.exp
.X_add_number
< 0
10291 || inst
.reloc
.exp
.X_add_number
> 3,
10292 _("shift out of range"));
10293 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10295 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10297 else if (inst
.operands
[i
].preind
)
10299 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10300 constraint (is_t
&& inst
.operands
[i
].writeback
,
10301 _("cannot use writeback with this instruction"));
10302 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10303 BAD_PC_ADDRESSING
);
10307 inst
.instruction
|= 0x01000000;
10308 if (inst
.operands
[i
].writeback
)
10309 inst
.instruction
|= 0x00200000;
10313 inst
.instruction
|= 0x00000c00;
10314 if (inst
.operands
[i
].writeback
)
10315 inst
.instruction
|= 0x00000100;
10317 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10319 else if (inst
.operands
[i
].postind
)
10321 gas_assert (inst
.operands
[i
].writeback
);
10322 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10323 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10326 inst
.instruction
|= 0x00200000;
10328 inst
.instruction
|= 0x00000900;
10329 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10331 else /* unindexed - only for coprocessor */
10332 inst
.error
= _("instruction does not accept unindexed addressing");
10335 /* Table of Thumb instructions which exist in both 16- and 32-bit
10336 encodings (the latter only in post-V6T2 cores). The index is the
10337 value used in the insns table below. When there is more than one
10338 possible 16-bit encoding for the instruction, this table always
10340 Also contains several pseudo-instructions used during relaxation. */
10341 #define T16_32_TAB \
10342 X(_adc, 4140, eb400000), \
10343 X(_adcs, 4140, eb500000), \
10344 X(_add, 1c00, eb000000), \
10345 X(_adds, 1c00, eb100000), \
10346 X(_addi, 0000, f1000000), \
10347 X(_addis, 0000, f1100000), \
10348 X(_add_pc,000f, f20f0000), \
10349 X(_add_sp,000d, f10d0000), \
10350 X(_adr, 000f, f20f0000), \
10351 X(_and, 4000, ea000000), \
10352 X(_ands, 4000, ea100000), \
10353 X(_asr, 1000, fa40f000), \
10354 X(_asrs, 1000, fa50f000), \
10355 X(_b, e000, f000b000), \
10356 X(_bcond, d000, f0008000), \
10357 X(_bic, 4380, ea200000), \
10358 X(_bics, 4380, ea300000), \
10359 X(_cmn, 42c0, eb100f00), \
10360 X(_cmp, 2800, ebb00f00), \
10361 X(_cpsie, b660, f3af8400), \
10362 X(_cpsid, b670, f3af8600), \
10363 X(_cpy, 4600, ea4f0000), \
10364 X(_dec_sp,80dd, f1ad0d00), \
10365 X(_eor, 4040, ea800000), \
10366 X(_eors, 4040, ea900000), \
10367 X(_inc_sp,00dd, f10d0d00), \
10368 X(_ldmia, c800, e8900000), \
10369 X(_ldr, 6800, f8500000), \
10370 X(_ldrb, 7800, f8100000), \
10371 X(_ldrh, 8800, f8300000), \
10372 X(_ldrsb, 5600, f9100000), \
10373 X(_ldrsh, 5e00, f9300000), \
10374 X(_ldr_pc,4800, f85f0000), \
10375 X(_ldr_pc2,4800, f85f0000), \
10376 X(_ldr_sp,9800, f85d0000), \
10377 X(_lsl, 0000, fa00f000), \
10378 X(_lsls, 0000, fa10f000), \
10379 X(_lsr, 0800, fa20f000), \
10380 X(_lsrs, 0800, fa30f000), \
10381 X(_mov, 2000, ea4f0000), \
10382 X(_movs, 2000, ea5f0000), \
10383 X(_mul, 4340, fb00f000), \
10384 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10385 X(_mvn, 43c0, ea6f0000), \
10386 X(_mvns, 43c0, ea7f0000), \
10387 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10388 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10389 X(_orr, 4300, ea400000), \
10390 X(_orrs, 4300, ea500000), \
10391 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10392 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10393 X(_rev, ba00, fa90f080), \
10394 X(_rev16, ba40, fa90f090), \
10395 X(_revsh, bac0, fa90f0b0), \
10396 X(_ror, 41c0, fa60f000), \
10397 X(_rors, 41c0, fa70f000), \
10398 X(_sbc, 4180, eb600000), \
10399 X(_sbcs, 4180, eb700000), \
10400 X(_stmia, c000, e8800000), \
10401 X(_str, 6000, f8400000), \
10402 X(_strb, 7000, f8000000), \
10403 X(_strh, 8000, f8200000), \
10404 X(_str_sp,9000, f84d0000), \
10405 X(_sub, 1e00, eba00000), \
10406 X(_subs, 1e00, ebb00000), \
10407 X(_subi, 8000, f1a00000), \
10408 X(_subis, 8000, f1b00000), \
10409 X(_sxtb, b240, fa4ff080), \
10410 X(_sxth, b200, fa0ff080), \
10411 X(_tst, 4200, ea100f00), \
10412 X(_uxtb, b2c0, fa5ff080), \
10413 X(_uxth, b280, fa1ff080), \
10414 X(_nop, bf00, f3af8000), \
10415 X(_yield, bf10, f3af8001), \
10416 X(_wfe, bf20, f3af8002), \
10417 X(_wfi, bf30, f3af8003), \
10418 X(_sev, bf40, f3af8004), \
10419 X(_sevl, bf50, f3af8005), \
10420 X(_udf, de00, f7f0a000)
10422 /* To catch errors in encoding functions, the codes are all offset by
10423 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10424 as 16-bit instructions. */
10425 #define X(a,b,c) T_MNEM##a
10426 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10429 #define X(a,b,c) 0x##b
10430 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10431 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10434 #define X(a,b,c) 0x##c
10435 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10436 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10437 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10441 /* Thumb instruction encoders, in alphabetical order. */
10443 /* ADDW or SUBW. */
10446 do_t_add_sub_w (void)
10450 Rd
= inst
.operands
[0].reg
;
10451 Rn
= inst
.operands
[1].reg
;
10453 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10454 is the SP-{plus,minus}-immediate form of the instruction. */
10456 constraint (Rd
== REG_PC
, BAD_PC
);
10458 reject_bad_reg (Rd
);
10460 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10461 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10464 /* Parse an add or subtract instruction. We get here with inst.instruction
10465 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10468 do_t_add_sub (void)
10472 Rd
= inst
.operands
[0].reg
;
10473 Rs
= (inst
.operands
[1].present
10474 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10475 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10478 set_it_insn_type_last ();
10480 if (unified_syntax
)
10483 bfd_boolean narrow
;
10486 flags
= (inst
.instruction
== T_MNEM_adds
10487 || inst
.instruction
== T_MNEM_subs
);
10489 narrow
= !in_it_block ();
10491 narrow
= in_it_block ();
10492 if (!inst
.operands
[2].isreg
)
10496 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10498 add
= (inst
.instruction
== T_MNEM_add
10499 || inst
.instruction
== T_MNEM_adds
);
10501 if (inst
.size_req
!= 4)
10503 /* Attempt to use a narrow opcode, with relaxation if
10505 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10506 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10507 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10508 opcode
= T_MNEM_add_sp
;
10509 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10510 opcode
= T_MNEM_add_pc
;
10511 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10514 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10516 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10520 inst
.instruction
= THUMB_OP16(opcode
);
10521 inst
.instruction
|= (Rd
<< 4) | Rs
;
10522 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10523 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10525 if (inst
.size_req
== 2)
10526 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10528 inst
.relax
= opcode
;
10532 constraint (inst
.size_req
== 2, BAD_HIREG
);
10534 if (inst
.size_req
== 4
10535 || (inst
.size_req
!= 2 && !opcode
))
10537 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10538 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10539 THUMB1_RELOC_ONLY
);
10542 constraint (add
, BAD_PC
);
10543 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10544 _("only SUBS PC, LR, #const allowed"));
10545 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10546 _("expression too complex"));
10547 constraint (inst
.reloc
.exp
.X_add_number
< 0
10548 || inst
.reloc
.exp
.X_add_number
> 0xff,
10549 _("immediate value out of range"));
10550 inst
.instruction
= T2_SUBS_PC_LR
10551 | inst
.reloc
.exp
.X_add_number
;
10552 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10555 else if (Rs
== REG_PC
)
10557 /* Always use addw/subw. */
10558 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10559 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10564 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10567 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10569 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10571 inst
.instruction
|= Rd
<< 8;
10572 inst
.instruction
|= Rs
<< 16;
10577 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10578 unsigned int shift
= inst
.operands
[2].shift_kind
;
10580 Rn
= inst
.operands
[2].reg
;
10581 /* See if we can do this with a 16-bit instruction. */
10582 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10584 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10589 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10590 || inst
.instruction
== T_MNEM_add
)
10592 : T_OPCODE_SUB_R3
);
10593 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10597 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10599 /* Thumb-1 cores (except v6-M) require at least one high
10600 register in a narrow non flag setting add. */
10601 if (Rd
> 7 || Rn
> 7
10602 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10603 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10610 inst
.instruction
= T_OPCODE_ADD_HI
;
10611 inst
.instruction
|= (Rd
& 8) << 4;
10612 inst
.instruction
|= (Rd
& 7);
10613 inst
.instruction
|= Rn
<< 3;
10619 constraint (Rd
== REG_PC
, BAD_PC
);
10620 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10621 constraint (Rs
== REG_PC
, BAD_PC
);
10622 reject_bad_reg (Rn
);
10624 /* If we get here, it can't be done in 16 bits. */
10625 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10626 _("shift must be constant"));
10627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10628 inst
.instruction
|= Rd
<< 8;
10629 inst
.instruction
|= Rs
<< 16;
10630 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10631 _("shift value over 3 not allowed in thumb mode"));
10632 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10633 _("only LSL shift allowed in thumb mode"));
10634 encode_thumb32_shifted_operand (2);
10639 constraint (inst
.instruction
== T_MNEM_adds
10640 || inst
.instruction
== T_MNEM_subs
,
10643 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10645 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10646 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10649 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10650 ? 0x0000 : 0x8000);
10651 inst
.instruction
|= (Rd
<< 4) | Rs
;
10652 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10656 Rn
= inst
.operands
[2].reg
;
10657 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10659 /* We now have Rd, Rs, and Rn set to registers. */
10660 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10662 /* Can't do this for SUB. */
10663 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10664 inst
.instruction
= T_OPCODE_ADD_HI
;
10665 inst
.instruction
|= (Rd
& 8) << 4;
10666 inst
.instruction
|= (Rd
& 7);
10668 inst
.instruction
|= Rn
<< 3;
10670 inst
.instruction
|= Rs
<< 3;
10672 constraint (1, _("dest must overlap one source register"));
10676 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10677 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10678 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10688 Rd
= inst
.operands
[0].reg
;
10689 reject_bad_reg (Rd
);
10691 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10693 /* Defer to section relaxation. */
10694 inst
.relax
= inst
.instruction
;
10695 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10696 inst
.instruction
|= Rd
<< 4;
10698 else if (unified_syntax
&& inst
.size_req
!= 2)
10700 /* Generate a 32-bit opcode. */
10701 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10702 inst
.instruction
|= Rd
<< 8;
10703 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10704 inst
.reloc
.pc_rel
= 1;
10708 /* Generate a 16-bit opcode. */
10709 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10710 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10711 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10712 inst
.reloc
.pc_rel
= 1;
10714 inst
.instruction
|= Rd
<< 4;
10718 /* Arithmetic instructions for which there is just one 16-bit
10719 instruction encoding, and it allows only two low registers.
10720 For maximal compatibility with ARM syntax, we allow three register
10721 operands even when Thumb-32 instructions are not available, as long
10722 as the first two are identical. For instance, both "sbc r0,r1" and
10723 "sbc r0,r0,r1" are allowed. */
10729 Rd
= inst
.operands
[0].reg
;
10730 Rs
= (inst
.operands
[1].present
10731 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10732 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10733 Rn
= inst
.operands
[2].reg
;
10735 reject_bad_reg (Rd
);
10736 reject_bad_reg (Rs
);
10737 if (inst
.operands
[2].isreg
)
10738 reject_bad_reg (Rn
);
10740 if (unified_syntax
)
10742 if (!inst
.operands
[2].isreg
)
10744 /* For an immediate, we always generate a 32-bit opcode;
10745 section relaxation will shrink it later if possible. */
10746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10747 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10748 inst
.instruction
|= Rd
<< 8;
10749 inst
.instruction
|= Rs
<< 16;
10750 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10754 bfd_boolean narrow
;
10756 /* See if we can do this with a 16-bit instruction. */
10757 if (THUMB_SETS_FLAGS (inst
.instruction
))
10758 narrow
= !in_it_block ();
10760 narrow
= in_it_block ();
10762 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10764 if (inst
.operands
[2].shifted
)
10766 if (inst
.size_req
== 4)
10772 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10773 inst
.instruction
|= Rd
;
10774 inst
.instruction
|= Rn
<< 3;
10778 /* If we get here, it can't be done in 16 bits. */
10779 constraint (inst
.operands
[2].shifted
10780 && inst
.operands
[2].immisreg
,
10781 _("shift must be constant"));
10782 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10783 inst
.instruction
|= Rd
<< 8;
10784 inst
.instruction
|= Rs
<< 16;
10785 encode_thumb32_shifted_operand (2);
10790 /* On its face this is a lie - the instruction does set the
10791 flags. However, the only supported mnemonic in this mode
10792 says it doesn't. */
10793 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10795 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10796 _("unshifted register required"));
10797 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10798 constraint (Rd
!= Rs
,
10799 _("dest and source1 must be the same register"));
10801 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10802 inst
.instruction
|= Rd
;
10803 inst
.instruction
|= Rn
<< 3;
10807 /* Similarly, but for instructions where the arithmetic operation is
10808 commutative, so we can allow either of them to be different from
10809 the destination operand in a 16-bit instruction. For instance, all
10810 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10817 Rd
= inst
.operands
[0].reg
;
10818 Rs
= (inst
.operands
[1].present
10819 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10820 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10821 Rn
= inst
.operands
[2].reg
;
10823 reject_bad_reg (Rd
);
10824 reject_bad_reg (Rs
);
10825 if (inst
.operands
[2].isreg
)
10826 reject_bad_reg (Rn
);
10828 if (unified_syntax
)
10830 if (!inst
.operands
[2].isreg
)
10832 /* For an immediate, we always generate a 32-bit opcode;
10833 section relaxation will shrink it later if possible. */
10834 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10835 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10836 inst
.instruction
|= Rd
<< 8;
10837 inst
.instruction
|= Rs
<< 16;
10838 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10842 bfd_boolean narrow
;
10844 /* See if we can do this with a 16-bit instruction. */
10845 if (THUMB_SETS_FLAGS (inst
.instruction
))
10846 narrow
= !in_it_block ();
10848 narrow
= in_it_block ();
10850 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10852 if (inst
.operands
[2].shifted
)
10854 if (inst
.size_req
== 4)
10861 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10862 inst
.instruction
|= Rd
;
10863 inst
.instruction
|= Rn
<< 3;
10868 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10869 inst
.instruction
|= Rd
;
10870 inst
.instruction
|= Rs
<< 3;
10875 /* If we get here, it can't be done in 16 bits. */
10876 constraint (inst
.operands
[2].shifted
10877 && inst
.operands
[2].immisreg
,
10878 _("shift must be constant"));
10879 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10880 inst
.instruction
|= Rd
<< 8;
10881 inst
.instruction
|= Rs
<< 16;
10882 encode_thumb32_shifted_operand (2);
10887 /* On its face this is a lie - the instruction does set the
10888 flags. However, the only supported mnemonic in this mode
10889 says it doesn't. */
10890 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10892 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10893 _("unshifted register required"));
10894 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10896 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10897 inst
.instruction
|= Rd
;
10900 inst
.instruction
|= Rn
<< 3;
10902 inst
.instruction
|= Rs
<< 3;
10904 constraint (1, _("dest must overlap one source register"));
10912 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10913 constraint (msb
> 32, _("bit-field extends past end of register"));
10914 /* The instruction encoding stores the LSB and MSB,
10915 not the LSB and width. */
10916 Rd
= inst
.operands
[0].reg
;
10917 reject_bad_reg (Rd
);
10918 inst
.instruction
|= Rd
<< 8;
10919 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10920 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10921 inst
.instruction
|= msb
- 1;
10930 Rd
= inst
.operands
[0].reg
;
10931 reject_bad_reg (Rd
);
10933 /* #0 in second position is alternative syntax for bfc, which is
10934 the same instruction but with REG_PC in the Rm field. */
10935 if (!inst
.operands
[1].isreg
)
10939 Rn
= inst
.operands
[1].reg
;
10940 reject_bad_reg (Rn
);
10943 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10944 constraint (msb
> 32, _("bit-field extends past end of register"));
10945 /* The instruction encoding stores the LSB and MSB,
10946 not the LSB and width. */
10947 inst
.instruction
|= Rd
<< 8;
10948 inst
.instruction
|= Rn
<< 16;
10949 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10950 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10951 inst
.instruction
|= msb
- 1;
10959 Rd
= inst
.operands
[0].reg
;
10960 Rn
= inst
.operands
[1].reg
;
10962 reject_bad_reg (Rd
);
10963 reject_bad_reg (Rn
);
10965 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10966 _("bit-field extends past end of register"));
10967 inst
.instruction
|= Rd
<< 8;
10968 inst
.instruction
|= Rn
<< 16;
10969 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10970 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10971 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10974 /* ARM V5 Thumb BLX (argument parse)
10975 BLX <target_addr> which is BLX(1)
10976 BLX <Rm> which is BLX(2)
10977 Unfortunately, there are two different opcodes for this mnemonic.
10978 So, the insns[].value is not used, and the code here zaps values
10979 into inst.instruction.
10981 ??? How to take advantage of the additional two bits of displacement
10982 available in Thumb32 mode? Need new relocation? */
10987 set_it_insn_type_last ();
10989 if (inst
.operands
[0].isreg
)
10991 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10992 /* We have a register, so this is BLX(2). */
10993 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10997 /* No register. This must be BLX(1). */
10998 inst
.instruction
= 0xf000e800;
10999 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11008 bfd_reloc_code_real_type reloc
;
11011 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11013 if (in_it_block ())
11015 /* Conditional branches inside IT blocks are encoded as unconditional
11017 cond
= COND_ALWAYS
;
11022 if (cond
!= COND_ALWAYS
)
11023 opcode
= T_MNEM_bcond
;
11025 opcode
= inst
.instruction
;
11028 && (inst
.size_req
== 4
11029 || (inst
.size_req
!= 2
11030 && (inst
.operands
[0].hasreloc
11031 || inst
.reloc
.exp
.X_op
== O_constant
))))
11033 inst
.instruction
= THUMB_OP32(opcode
);
11034 if (cond
== COND_ALWAYS
)
11035 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11038 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11039 _("selected architecture does not support "
11040 "wide conditional branch instruction"));
11042 gas_assert (cond
!= 0xF);
11043 inst
.instruction
|= cond
<< 22;
11044 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11049 inst
.instruction
= THUMB_OP16(opcode
);
11050 if (cond
== COND_ALWAYS
)
11051 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11054 inst
.instruction
|= cond
<< 8;
11055 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11057 /* Allow section relaxation. */
11058 if (unified_syntax
&& inst
.size_req
!= 2)
11059 inst
.relax
= opcode
;
11061 inst
.reloc
.type
= reloc
;
11062 inst
.reloc
.pc_rel
= 1;
11065 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11066 between the two is the maximum immediate allowed - which is passed in
11069 do_t_bkpt_hlt1 (int range
)
11071 constraint (inst
.cond
!= COND_ALWAYS
,
11072 _("instruction is always unconditional"));
11073 if (inst
.operands
[0].present
)
11075 constraint (inst
.operands
[0].imm
> range
,
11076 _("immediate value out of range"));
11077 inst
.instruction
|= inst
.operands
[0].imm
;
11080 set_it_insn_type (NEUTRAL_IT_INSN
);
11086 do_t_bkpt_hlt1 (63);
11092 do_t_bkpt_hlt1 (255);
11096 do_t_branch23 (void)
11098 set_it_insn_type_last ();
11099 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11101 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11102 this file. We used to simply ignore the PLT reloc type here --
11103 the branch encoding is now needed to deal with TLSCALL relocs.
11104 So if we see a PLT reloc now, put it back to how it used to be to
11105 keep the preexisting behaviour. */
11106 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11107 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11109 #if defined(OBJ_COFF)
11110 /* If the destination of the branch is a defined symbol which does not have
11111 the THUMB_FUNC attribute, then we must be calling a function which has
11112 the (interfacearm) attribute. We look for the Thumb entry point to that
11113 function and change the branch to refer to that function instead. */
11114 if ( inst
.reloc
.exp
.X_op
== O_symbol
11115 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11116 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11117 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11118 inst
.reloc
.exp
.X_add_symbol
=
11119 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11126 set_it_insn_type_last ();
11127 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11128 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11129 should cause the alignment to be checked once it is known. This is
11130 because BX PC only works if the instruction is word aligned. */
11138 set_it_insn_type_last ();
11139 Rm
= inst
.operands
[0].reg
;
11140 reject_bad_reg (Rm
);
11141 inst
.instruction
|= Rm
<< 16;
11150 Rd
= inst
.operands
[0].reg
;
11151 Rm
= inst
.operands
[1].reg
;
11153 reject_bad_reg (Rd
);
11154 reject_bad_reg (Rm
);
11156 inst
.instruction
|= Rd
<< 8;
11157 inst
.instruction
|= Rm
<< 16;
11158 inst
.instruction
|= Rm
;
11164 set_it_insn_type (OUTSIDE_IT_INSN
);
11165 inst
.instruction
|= inst
.operands
[0].imm
;
11171 set_it_insn_type (OUTSIDE_IT_INSN
);
11173 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11174 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11176 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11177 inst
.instruction
= 0xf3af8000;
11178 inst
.instruction
|= imod
<< 9;
11179 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11180 if (inst
.operands
[1].present
)
11181 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11186 && (inst
.operands
[0].imm
& 4),
11187 _("selected processor does not support 'A' form "
11188 "of this instruction"));
11189 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11190 _("Thumb does not support the 2-argument "
11191 "form of this instruction"));
11192 inst
.instruction
|= inst
.operands
[0].imm
;
11196 /* THUMB CPY instruction (argument parse). */
11201 if (inst
.size_req
== 4)
11203 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11204 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11205 inst
.instruction
|= inst
.operands
[1].reg
;
11209 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11210 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11211 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11218 set_it_insn_type (OUTSIDE_IT_INSN
);
11219 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11220 inst
.instruction
|= inst
.operands
[0].reg
;
11221 inst
.reloc
.pc_rel
= 1;
11222 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11228 inst
.instruction
|= inst
.operands
[0].imm
;
11234 unsigned Rd
, Rn
, Rm
;
11236 Rd
= inst
.operands
[0].reg
;
11237 Rn
= (inst
.operands
[1].present
11238 ? inst
.operands
[1].reg
: Rd
);
11239 Rm
= inst
.operands
[2].reg
;
11241 reject_bad_reg (Rd
);
11242 reject_bad_reg (Rn
);
11243 reject_bad_reg (Rm
);
11245 inst
.instruction
|= Rd
<< 8;
11246 inst
.instruction
|= Rn
<< 16;
11247 inst
.instruction
|= Rm
;
11253 if (unified_syntax
&& inst
.size_req
== 4)
11254 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11256 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11262 unsigned int cond
= inst
.operands
[0].imm
;
11264 set_it_insn_type (IT_INSN
);
11265 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11267 now_it
.warn_deprecated
= FALSE
;
11269 /* If the condition is a negative condition, invert the mask. */
11270 if ((cond
& 0x1) == 0x0)
11272 unsigned int mask
= inst
.instruction
& 0x000f;
11274 if ((mask
& 0x7) == 0)
11276 /* No conversion needed. */
11277 now_it
.block_length
= 1;
11279 else if ((mask
& 0x3) == 0)
11282 now_it
.block_length
= 2;
11284 else if ((mask
& 0x1) == 0)
11287 now_it
.block_length
= 3;
11292 now_it
.block_length
= 4;
11295 inst
.instruction
&= 0xfff0;
11296 inst
.instruction
|= mask
;
11299 inst
.instruction
|= cond
<< 4;
11302 /* Helper function used for both push/pop and ldm/stm. */
11304 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11308 load
= (inst
.instruction
& (1 << 20)) != 0;
11310 if (mask
& (1 << 13))
11311 inst
.error
= _("SP not allowed in register list");
11313 if ((mask
& (1 << base
)) != 0
11315 inst
.error
= _("having the base register in the register list when "
11316 "using write back is UNPREDICTABLE");
11320 if (mask
& (1 << 15))
11322 if (mask
& (1 << 14))
11323 inst
.error
= _("LR and PC should not both be in register list");
11325 set_it_insn_type_last ();
11330 if (mask
& (1 << 15))
11331 inst
.error
= _("PC not allowed in register list");
11334 if ((mask
& (mask
- 1)) == 0)
11336 /* Single register transfers implemented as str/ldr. */
11339 if (inst
.instruction
& (1 << 23))
11340 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11342 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11346 if (inst
.instruction
& (1 << 23))
11347 inst
.instruction
= 0x00800000; /* ia -> [base] */
11349 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11352 inst
.instruction
|= 0xf8400000;
11354 inst
.instruction
|= 0x00100000;
11356 mask
= ffs (mask
) - 1;
11359 else if (writeback
)
11360 inst
.instruction
|= WRITE_BACK
;
11362 inst
.instruction
|= mask
;
11363 inst
.instruction
|= base
<< 16;
11369 /* This really doesn't seem worth it. */
11370 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11371 _("expression too complex"));
11372 constraint (inst
.operands
[1].writeback
,
11373 _("Thumb load/store multiple does not support {reglist}^"));
11375 if (unified_syntax
)
11377 bfd_boolean narrow
;
11381 /* See if we can use a 16-bit instruction. */
11382 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11383 && inst
.size_req
!= 4
11384 && !(inst
.operands
[1].imm
& ~0xff))
11386 mask
= 1 << inst
.operands
[0].reg
;
11388 if (inst
.operands
[0].reg
<= 7)
11390 if (inst
.instruction
== T_MNEM_stmia
11391 ? inst
.operands
[0].writeback
11392 : (inst
.operands
[0].writeback
11393 == !(inst
.operands
[1].imm
& mask
)))
11395 if (inst
.instruction
== T_MNEM_stmia
11396 && (inst
.operands
[1].imm
& mask
)
11397 && (inst
.operands
[1].imm
& (mask
- 1)))
11398 as_warn (_("value stored for r%d is UNKNOWN"),
11399 inst
.operands
[0].reg
);
11401 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11402 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11403 inst
.instruction
|= inst
.operands
[1].imm
;
11406 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11408 /* This means 1 register in reg list one of 3 situations:
11409 1. Instruction is stmia, but without writeback.
11410 2. lmdia without writeback, but with Rn not in
11412 3. ldmia with writeback, but with Rn in reglist.
11413 Case 3 is UNPREDICTABLE behaviour, so we handle
11414 case 1 and 2 which can be converted into a 16-bit
11415 str or ldr. The SP cases are handled below. */
11416 unsigned long opcode
;
11417 /* First, record an error for Case 3. */
11418 if (inst
.operands
[1].imm
& mask
11419 && inst
.operands
[0].writeback
)
11421 _("having the base register in the register list when "
11422 "using write back is UNPREDICTABLE");
11424 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11426 inst
.instruction
= THUMB_OP16 (opcode
);
11427 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11428 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11432 else if (inst
.operands
[0] .reg
== REG_SP
)
11434 if (inst
.operands
[0].writeback
)
11437 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11438 ? T_MNEM_push
: T_MNEM_pop
);
11439 inst
.instruction
|= inst
.operands
[1].imm
;
11442 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11445 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11446 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11447 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11455 if (inst
.instruction
< 0xffff)
11456 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11458 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11459 inst
.operands
[0].writeback
);
11464 constraint (inst
.operands
[0].reg
> 7
11465 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11466 constraint (inst
.instruction
!= T_MNEM_ldmia
11467 && inst
.instruction
!= T_MNEM_stmia
,
11468 _("Thumb-2 instruction only valid in unified syntax"));
11469 if (inst
.instruction
== T_MNEM_stmia
)
11471 if (!inst
.operands
[0].writeback
)
11472 as_warn (_("this instruction will write back the base register"));
11473 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11474 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11475 as_warn (_("value stored for r%d is UNKNOWN"),
11476 inst
.operands
[0].reg
);
11480 if (!inst
.operands
[0].writeback
11481 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11482 as_warn (_("this instruction will write back the base register"));
11483 else if (inst
.operands
[0].writeback
11484 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11485 as_warn (_("this instruction will not write back the base register"));
11488 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11489 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11490 inst
.instruction
|= inst
.operands
[1].imm
;
11497 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11498 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11499 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11500 || inst
.operands
[1].negative
,
11503 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11506 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11507 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11513 if (!inst
.operands
[1].present
)
11515 constraint (inst
.operands
[0].reg
== REG_LR
,
11516 _("r14 not allowed as first register "
11517 "when second register is omitted"));
11518 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11520 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11524 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11525 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11531 unsigned long opcode
;
11534 if (inst
.operands
[0].isreg
11535 && !inst
.operands
[0].preind
11536 && inst
.operands
[0].reg
== REG_PC
)
11537 set_it_insn_type_last ();
11539 opcode
= inst
.instruction
;
11540 if (unified_syntax
)
11542 if (!inst
.operands
[1].isreg
)
11544 if (opcode
<= 0xffff)
11545 inst
.instruction
= THUMB_OP32 (opcode
);
11546 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11549 if (inst
.operands
[1].isreg
11550 && !inst
.operands
[1].writeback
11551 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11552 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11553 && opcode
<= 0xffff
11554 && inst
.size_req
!= 4)
11556 /* Insn may have a 16-bit form. */
11557 Rn
= inst
.operands
[1].reg
;
11558 if (inst
.operands
[1].immisreg
)
11560 inst
.instruction
= THUMB_OP16 (opcode
);
11562 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11564 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11565 reject_bad_reg (inst
.operands
[1].imm
);
11567 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11568 && opcode
!= T_MNEM_ldrsb
)
11569 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11570 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11577 if (inst
.reloc
.pc_rel
)
11578 opcode
= T_MNEM_ldr_pc2
;
11580 opcode
= T_MNEM_ldr_pc
;
11584 if (opcode
== T_MNEM_ldr
)
11585 opcode
= T_MNEM_ldr_sp
;
11587 opcode
= T_MNEM_str_sp
;
11589 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11593 inst
.instruction
= inst
.operands
[0].reg
;
11594 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11596 inst
.instruction
|= THUMB_OP16 (opcode
);
11597 if (inst
.size_req
== 2)
11598 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11600 inst
.relax
= opcode
;
11604 /* Definitely a 32-bit variant. */
11606 /* Warning for Erratum 752419. */
11607 if (opcode
== T_MNEM_ldr
11608 && inst
.operands
[0].reg
== REG_SP
11609 && inst
.operands
[1].writeback
== 1
11610 && !inst
.operands
[1].immisreg
)
11612 if (no_cpu_selected ()
11613 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11614 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11615 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11616 as_warn (_("This instruction may be unpredictable "
11617 "if executed on M-profile cores "
11618 "with interrupts enabled."));
11621 /* Do some validations regarding addressing modes. */
11622 if (inst
.operands
[1].immisreg
)
11623 reject_bad_reg (inst
.operands
[1].imm
);
11625 constraint (inst
.operands
[1].writeback
== 1
11626 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11629 inst
.instruction
= THUMB_OP32 (opcode
);
11630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11631 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11632 check_ldr_r15_aligned ();
11636 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11638 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11640 /* Only [Rn,Rm] is acceptable. */
11641 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11642 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11643 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11644 || inst
.operands
[1].negative
,
11645 _("Thumb does not support this addressing mode"));
11646 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11650 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11651 if (!inst
.operands
[1].isreg
)
11652 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11655 constraint (!inst
.operands
[1].preind
11656 || inst
.operands
[1].shifted
11657 || inst
.operands
[1].writeback
,
11658 _("Thumb does not support this addressing mode"));
11659 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11661 constraint (inst
.instruction
& 0x0600,
11662 _("byte or halfword not valid for base register"));
11663 constraint (inst
.operands
[1].reg
== REG_PC
11664 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11665 _("r15 based store not allowed"));
11666 constraint (inst
.operands
[1].immisreg
,
11667 _("invalid base register for register offset"));
11669 if (inst
.operands
[1].reg
== REG_PC
)
11670 inst
.instruction
= T_OPCODE_LDR_PC
;
11671 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11672 inst
.instruction
= T_OPCODE_LDR_SP
;
11674 inst
.instruction
= T_OPCODE_STR_SP
;
11676 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11677 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11681 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11682 if (!inst
.operands
[1].immisreg
)
11684 /* Immediate offset. */
11685 inst
.instruction
|= inst
.operands
[0].reg
;
11686 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11687 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11691 /* Register offset. */
11692 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11693 constraint (inst
.operands
[1].negative
,
11694 _("Thumb does not support this addressing mode"));
11697 switch (inst
.instruction
)
11699 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11700 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11701 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11702 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11703 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11704 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11705 case 0x5600 /* ldrsb */:
11706 case 0x5e00 /* ldrsh */: break;
11710 inst
.instruction
|= inst
.operands
[0].reg
;
11711 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11712 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11718 if (!inst
.operands
[1].present
)
11720 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11721 constraint (inst
.operands
[0].reg
== REG_LR
,
11722 _("r14 not allowed here"));
11723 constraint (inst
.operands
[0].reg
== REG_R12
,
11724 _("r12 not allowed here"));
11727 if (inst
.operands
[2].writeback
11728 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11729 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11730 as_warn (_("base register written back, and overlaps "
11731 "one of transfer registers"));
11733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11734 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11735 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11742 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11748 unsigned Rd
, Rn
, Rm
, Ra
;
11750 Rd
= inst
.operands
[0].reg
;
11751 Rn
= inst
.operands
[1].reg
;
11752 Rm
= inst
.operands
[2].reg
;
11753 Ra
= inst
.operands
[3].reg
;
11755 reject_bad_reg (Rd
);
11756 reject_bad_reg (Rn
);
11757 reject_bad_reg (Rm
);
11758 reject_bad_reg (Ra
);
11760 inst
.instruction
|= Rd
<< 8;
11761 inst
.instruction
|= Rn
<< 16;
11762 inst
.instruction
|= Rm
;
11763 inst
.instruction
|= Ra
<< 12;
11769 unsigned RdLo
, RdHi
, Rn
, Rm
;
11771 RdLo
= inst
.operands
[0].reg
;
11772 RdHi
= inst
.operands
[1].reg
;
11773 Rn
= inst
.operands
[2].reg
;
11774 Rm
= inst
.operands
[3].reg
;
11776 reject_bad_reg (RdLo
);
11777 reject_bad_reg (RdHi
);
11778 reject_bad_reg (Rn
);
11779 reject_bad_reg (Rm
);
11781 inst
.instruction
|= RdLo
<< 12;
11782 inst
.instruction
|= RdHi
<< 8;
11783 inst
.instruction
|= Rn
<< 16;
11784 inst
.instruction
|= Rm
;
11788 do_t_mov_cmp (void)
11792 Rn
= inst
.operands
[0].reg
;
11793 Rm
= inst
.operands
[1].reg
;
11796 set_it_insn_type_last ();
11798 if (unified_syntax
)
11800 int r0off
= (inst
.instruction
== T_MNEM_mov
11801 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11802 unsigned long opcode
;
11803 bfd_boolean narrow
;
11804 bfd_boolean low_regs
;
11806 low_regs
= (Rn
<= 7 && Rm
<= 7);
11807 opcode
= inst
.instruction
;
11808 if (in_it_block ())
11809 narrow
= opcode
!= T_MNEM_movs
;
11811 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11812 if (inst
.size_req
== 4
11813 || inst
.operands
[1].shifted
)
11816 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11817 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11818 && !inst
.operands
[1].shifted
11822 inst
.instruction
= T2_SUBS_PC_LR
;
11826 if (opcode
== T_MNEM_cmp
)
11828 constraint (Rn
== REG_PC
, BAD_PC
);
11831 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11833 warn_deprecated_sp (Rm
);
11834 /* R15 was documented as a valid choice for Rm in ARMv6,
11835 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11836 tools reject R15, so we do too. */
11837 constraint (Rm
== REG_PC
, BAD_PC
);
11840 reject_bad_reg (Rm
);
11842 else if (opcode
== T_MNEM_mov
11843 || opcode
== T_MNEM_movs
)
11845 if (inst
.operands
[1].isreg
)
11847 if (opcode
== T_MNEM_movs
)
11849 reject_bad_reg (Rn
);
11850 reject_bad_reg (Rm
);
11854 /* This is mov.n. */
11855 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11856 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11858 as_tsktsk (_("Use of r%u as a source register is "
11859 "deprecated when r%u is the destination "
11860 "register."), Rm
, Rn
);
11865 /* This is mov.w. */
11866 constraint (Rn
== REG_PC
, BAD_PC
);
11867 constraint (Rm
== REG_PC
, BAD_PC
);
11868 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11872 reject_bad_reg (Rn
);
11875 if (!inst
.operands
[1].isreg
)
11877 /* Immediate operand. */
11878 if (!in_it_block () && opcode
== T_MNEM_mov
)
11880 if (low_regs
&& narrow
)
11882 inst
.instruction
= THUMB_OP16 (opcode
);
11883 inst
.instruction
|= Rn
<< 8;
11884 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11885 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11887 if (inst
.size_req
== 2)
11888 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11890 inst
.relax
= opcode
;
11895 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11896 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11897 THUMB1_RELOC_ONLY
);
11899 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11900 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11901 inst
.instruction
|= Rn
<< r0off
;
11902 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11905 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11906 && (inst
.instruction
== T_MNEM_mov
11907 || inst
.instruction
== T_MNEM_movs
))
11909 /* Register shifts are encoded as separate shift instructions. */
11910 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11912 if (in_it_block ())
11917 if (inst
.size_req
== 4)
11920 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11926 switch (inst
.operands
[1].shift_kind
)
11929 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11932 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11935 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11938 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11944 inst
.instruction
= opcode
;
11947 inst
.instruction
|= Rn
;
11948 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11953 inst
.instruction
|= CONDS_BIT
;
11955 inst
.instruction
|= Rn
<< 8;
11956 inst
.instruction
|= Rm
<< 16;
11957 inst
.instruction
|= inst
.operands
[1].imm
;
11962 /* Some mov with immediate shift have narrow variants.
11963 Register shifts are handled above. */
11964 if (low_regs
&& inst
.operands
[1].shifted
11965 && (inst
.instruction
== T_MNEM_mov
11966 || inst
.instruction
== T_MNEM_movs
))
11968 if (in_it_block ())
11969 narrow
= (inst
.instruction
== T_MNEM_mov
);
11971 narrow
= (inst
.instruction
== T_MNEM_movs
);
11976 switch (inst
.operands
[1].shift_kind
)
11978 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11979 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11980 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11981 default: narrow
= FALSE
; break;
11987 inst
.instruction
|= Rn
;
11988 inst
.instruction
|= Rm
<< 3;
11989 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11993 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11994 inst
.instruction
|= Rn
<< r0off
;
11995 encode_thumb32_shifted_operand (1);
11999 switch (inst
.instruction
)
12002 /* In v4t or v5t a move of two lowregs produces unpredictable
12003 results. Don't allow this. */
12006 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12007 "MOV Rd, Rs with two low registers is not "
12008 "permitted on this architecture");
12009 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12013 inst
.instruction
= T_OPCODE_MOV_HR
;
12014 inst
.instruction
|= (Rn
& 0x8) << 4;
12015 inst
.instruction
|= (Rn
& 0x7);
12016 inst
.instruction
|= Rm
<< 3;
12020 /* We know we have low registers at this point.
12021 Generate LSLS Rd, Rs, #0. */
12022 inst
.instruction
= T_OPCODE_LSL_I
;
12023 inst
.instruction
|= Rn
;
12024 inst
.instruction
|= Rm
<< 3;
12030 inst
.instruction
= T_OPCODE_CMP_LR
;
12031 inst
.instruction
|= Rn
;
12032 inst
.instruction
|= Rm
<< 3;
12036 inst
.instruction
= T_OPCODE_CMP_HR
;
12037 inst
.instruction
|= (Rn
& 0x8) << 4;
12038 inst
.instruction
|= (Rn
& 0x7);
12039 inst
.instruction
|= Rm
<< 3;
12046 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12048 /* PR 10443: Do not silently ignore shifted operands. */
12049 constraint (inst
.operands
[1].shifted
,
12050 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12052 if (inst
.operands
[1].isreg
)
12054 if (Rn
< 8 && Rm
< 8)
12056 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12057 since a MOV instruction produces unpredictable results. */
12058 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12059 inst
.instruction
= T_OPCODE_ADD_I3
;
12061 inst
.instruction
= T_OPCODE_CMP_LR
;
12063 inst
.instruction
|= Rn
;
12064 inst
.instruction
|= Rm
<< 3;
12068 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12069 inst
.instruction
= T_OPCODE_MOV_HR
;
12071 inst
.instruction
= T_OPCODE_CMP_HR
;
12077 constraint (Rn
> 7,
12078 _("only lo regs allowed with immediate"));
12079 inst
.instruction
|= Rn
<< 8;
12080 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12091 top
= (inst
.instruction
& 0x00800000) != 0;
12092 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12094 constraint (top
, _(":lower16: not allowed this instruction"));
12095 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12097 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12099 constraint (!top
, _(":upper16: not allowed this instruction"));
12100 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12103 Rd
= inst
.operands
[0].reg
;
12104 reject_bad_reg (Rd
);
12106 inst
.instruction
|= Rd
<< 8;
12107 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12109 imm
= inst
.reloc
.exp
.X_add_number
;
12110 inst
.instruction
|= (imm
& 0xf000) << 4;
12111 inst
.instruction
|= (imm
& 0x0800) << 15;
12112 inst
.instruction
|= (imm
& 0x0700) << 4;
12113 inst
.instruction
|= (imm
& 0x00ff);
12118 do_t_mvn_tst (void)
12122 Rn
= inst
.operands
[0].reg
;
12123 Rm
= inst
.operands
[1].reg
;
12125 if (inst
.instruction
== T_MNEM_cmp
12126 || inst
.instruction
== T_MNEM_cmn
)
12127 constraint (Rn
== REG_PC
, BAD_PC
);
12129 reject_bad_reg (Rn
);
12130 reject_bad_reg (Rm
);
12132 if (unified_syntax
)
12134 int r0off
= (inst
.instruction
== T_MNEM_mvn
12135 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12136 bfd_boolean narrow
;
12138 if (inst
.size_req
== 4
12139 || inst
.instruction
> 0xffff
12140 || inst
.operands
[1].shifted
12141 || Rn
> 7 || Rm
> 7)
12143 else if (inst
.instruction
== T_MNEM_cmn
12144 || inst
.instruction
== T_MNEM_tst
)
12146 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12147 narrow
= !in_it_block ();
12149 narrow
= in_it_block ();
12151 if (!inst
.operands
[1].isreg
)
12153 /* For an immediate, we always generate a 32-bit opcode;
12154 section relaxation will shrink it later if possible. */
12155 if (inst
.instruction
< 0xffff)
12156 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12157 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12158 inst
.instruction
|= Rn
<< r0off
;
12159 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12163 /* See if we can do this with a 16-bit instruction. */
12166 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12167 inst
.instruction
|= Rn
;
12168 inst
.instruction
|= Rm
<< 3;
12172 constraint (inst
.operands
[1].shifted
12173 && inst
.operands
[1].immisreg
,
12174 _("shift must be constant"));
12175 if (inst
.instruction
< 0xffff)
12176 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12177 inst
.instruction
|= Rn
<< r0off
;
12178 encode_thumb32_shifted_operand (1);
12184 constraint (inst
.instruction
> 0xffff
12185 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12186 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12187 _("unshifted register required"));
12188 constraint (Rn
> 7 || Rm
> 7,
12191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12192 inst
.instruction
|= Rn
;
12193 inst
.instruction
|= Rm
<< 3;
12202 if (do_vfp_nsyn_mrs () == SUCCESS
)
12205 Rd
= inst
.operands
[0].reg
;
12206 reject_bad_reg (Rd
);
12207 inst
.instruction
|= Rd
<< 8;
12209 if (inst
.operands
[1].isreg
)
12211 unsigned br
= inst
.operands
[1].reg
;
12212 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12213 as_bad (_("bad register for mrs"));
12215 inst
.instruction
|= br
& (0xf << 16);
12216 inst
.instruction
|= (br
& 0x300) >> 4;
12217 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12221 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12223 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12225 /* PR gas/12698: The constraint is only applied for m_profile.
12226 If the user has specified -march=all, we want to ignore it as
12227 we are building for any CPU type, including non-m variants. */
12228 bfd_boolean m_profile
=
12229 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12230 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12231 "not support requested special purpose register"));
12234 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12236 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12237 _("'APSR', 'CPSR' or 'SPSR' expected"));
12239 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12240 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12241 inst
.instruction
|= 0xf0000;
12251 if (do_vfp_nsyn_msr () == SUCCESS
)
12254 constraint (!inst
.operands
[1].isreg
,
12255 _("Thumb encoding does not support an immediate here"));
12257 if (inst
.operands
[0].isreg
)
12258 flags
= (int)(inst
.operands
[0].reg
);
12260 flags
= inst
.operands
[0].imm
;
12262 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12264 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12266 /* PR gas/12698: The constraint is only applied for m_profile.
12267 If the user has specified -march=all, we want to ignore it as
12268 we are building for any CPU type, including non-m variants. */
12269 bfd_boolean m_profile
=
12270 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12271 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12272 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12273 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12274 && bits
!= PSR_f
)) && m_profile
,
12275 _("selected processor does not support requested special "
12276 "purpose register"));
12279 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12280 "requested special purpose register"));
12282 Rn
= inst
.operands
[1].reg
;
12283 reject_bad_reg (Rn
);
12285 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12286 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12287 inst
.instruction
|= (flags
& 0x300) >> 4;
12288 inst
.instruction
|= (flags
& 0xff);
12289 inst
.instruction
|= Rn
<< 16;
12295 bfd_boolean narrow
;
12296 unsigned Rd
, Rn
, Rm
;
12298 if (!inst
.operands
[2].present
)
12299 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12301 Rd
= inst
.operands
[0].reg
;
12302 Rn
= inst
.operands
[1].reg
;
12303 Rm
= inst
.operands
[2].reg
;
12305 if (unified_syntax
)
12307 if (inst
.size_req
== 4
12313 else if (inst
.instruction
== T_MNEM_muls
)
12314 narrow
= !in_it_block ();
12316 narrow
= in_it_block ();
12320 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12321 constraint (Rn
> 7 || Rm
> 7,
12328 /* 16-bit MULS/Conditional MUL. */
12329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12330 inst
.instruction
|= Rd
;
12333 inst
.instruction
|= Rm
<< 3;
12335 inst
.instruction
|= Rn
<< 3;
12337 constraint (1, _("dest must overlap one source register"));
12341 constraint (inst
.instruction
!= T_MNEM_mul
,
12342 _("Thumb-2 MUL must not set flags"));
12344 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12345 inst
.instruction
|= Rd
<< 8;
12346 inst
.instruction
|= Rn
<< 16;
12347 inst
.instruction
|= Rm
<< 0;
12349 reject_bad_reg (Rd
);
12350 reject_bad_reg (Rn
);
12351 reject_bad_reg (Rm
);
12358 unsigned RdLo
, RdHi
, Rn
, Rm
;
12360 RdLo
= inst
.operands
[0].reg
;
12361 RdHi
= inst
.operands
[1].reg
;
12362 Rn
= inst
.operands
[2].reg
;
12363 Rm
= inst
.operands
[3].reg
;
12365 reject_bad_reg (RdLo
);
12366 reject_bad_reg (RdHi
);
12367 reject_bad_reg (Rn
);
12368 reject_bad_reg (Rm
);
12370 inst
.instruction
|= RdLo
<< 12;
12371 inst
.instruction
|= RdHi
<< 8;
12372 inst
.instruction
|= Rn
<< 16;
12373 inst
.instruction
|= Rm
;
12376 as_tsktsk (_("rdhi and rdlo must be different"));
12382 set_it_insn_type (NEUTRAL_IT_INSN
);
12384 if (unified_syntax
)
12386 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12388 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12389 inst
.instruction
|= inst
.operands
[0].imm
;
12393 /* PR9722: Check for Thumb2 availability before
12394 generating a thumb2 nop instruction. */
12395 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12398 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12401 inst
.instruction
= 0x46c0;
12406 constraint (inst
.operands
[0].present
,
12407 _("Thumb does not support NOP with hints"));
12408 inst
.instruction
= 0x46c0;
12415 if (unified_syntax
)
12417 bfd_boolean narrow
;
12419 if (THUMB_SETS_FLAGS (inst
.instruction
))
12420 narrow
= !in_it_block ();
12422 narrow
= in_it_block ();
12423 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12425 if (inst
.size_req
== 4)
12430 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12431 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12436 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12437 inst
.instruction
|= inst
.operands
[0].reg
;
12438 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12443 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12445 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12447 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12448 inst
.instruction
|= inst
.operands
[0].reg
;
12449 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12458 Rd
= inst
.operands
[0].reg
;
12459 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12461 reject_bad_reg (Rd
);
12462 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12463 reject_bad_reg (Rn
);
12465 inst
.instruction
|= Rd
<< 8;
12466 inst
.instruction
|= Rn
<< 16;
12468 if (!inst
.operands
[2].isreg
)
12470 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12471 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12477 Rm
= inst
.operands
[2].reg
;
12478 reject_bad_reg (Rm
);
12480 constraint (inst
.operands
[2].shifted
12481 && inst
.operands
[2].immisreg
,
12482 _("shift must be constant"));
12483 encode_thumb32_shifted_operand (2);
12490 unsigned Rd
, Rn
, Rm
;
12492 Rd
= inst
.operands
[0].reg
;
12493 Rn
= inst
.operands
[1].reg
;
12494 Rm
= inst
.operands
[2].reg
;
12496 reject_bad_reg (Rd
);
12497 reject_bad_reg (Rn
);
12498 reject_bad_reg (Rm
);
12500 inst
.instruction
|= Rd
<< 8;
12501 inst
.instruction
|= Rn
<< 16;
12502 inst
.instruction
|= Rm
;
12503 if (inst
.operands
[3].present
)
12505 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12506 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12507 _("expression too complex"));
12508 inst
.instruction
|= (val
& 0x1c) << 10;
12509 inst
.instruction
|= (val
& 0x03) << 6;
12516 if (!inst
.operands
[3].present
)
12520 inst
.instruction
&= ~0x00000020;
12522 /* PR 10168. Swap the Rm and Rn registers. */
12523 Rtmp
= inst
.operands
[1].reg
;
12524 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12525 inst
.operands
[2].reg
= Rtmp
;
12533 if (inst
.operands
[0].immisreg
)
12534 reject_bad_reg (inst
.operands
[0].imm
);
12536 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12540 do_t_push_pop (void)
12544 constraint (inst
.operands
[0].writeback
,
12545 _("push/pop do not support {reglist}^"));
12546 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12547 _("expression too complex"));
12549 mask
= inst
.operands
[0].imm
;
12550 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12551 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12552 else if (inst
.size_req
!= 4
12553 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12554 ? REG_LR
: REG_PC
)))
12556 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12557 inst
.instruction
|= THUMB_PP_PC_LR
;
12558 inst
.instruction
|= mask
& 0xff;
12560 else if (unified_syntax
)
12562 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12563 encode_thumb2_ldmstm (13, mask
, TRUE
);
12567 inst
.error
= _("invalid register list to push/pop instruction");
12577 Rd
= inst
.operands
[0].reg
;
12578 Rm
= inst
.operands
[1].reg
;
12580 reject_bad_reg (Rd
);
12581 reject_bad_reg (Rm
);
12583 inst
.instruction
|= Rd
<< 8;
12584 inst
.instruction
|= Rm
<< 16;
12585 inst
.instruction
|= Rm
;
12593 Rd
= inst
.operands
[0].reg
;
12594 Rm
= inst
.operands
[1].reg
;
12596 reject_bad_reg (Rd
);
12597 reject_bad_reg (Rm
);
12599 if (Rd
<= 7 && Rm
<= 7
12600 && inst
.size_req
!= 4)
12602 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12603 inst
.instruction
|= Rd
;
12604 inst
.instruction
|= Rm
<< 3;
12606 else if (unified_syntax
)
12608 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12609 inst
.instruction
|= Rd
<< 8;
12610 inst
.instruction
|= Rm
<< 16;
12611 inst
.instruction
|= Rm
;
12614 inst
.error
= BAD_HIREG
;
12622 Rd
= inst
.operands
[0].reg
;
12623 Rm
= inst
.operands
[1].reg
;
12625 reject_bad_reg (Rd
);
12626 reject_bad_reg (Rm
);
12628 inst
.instruction
|= Rd
<< 8;
12629 inst
.instruction
|= Rm
;
12637 Rd
= inst
.operands
[0].reg
;
12638 Rs
= (inst
.operands
[1].present
12639 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12640 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12642 reject_bad_reg (Rd
);
12643 reject_bad_reg (Rs
);
12644 if (inst
.operands
[2].isreg
)
12645 reject_bad_reg (inst
.operands
[2].reg
);
12647 inst
.instruction
|= Rd
<< 8;
12648 inst
.instruction
|= Rs
<< 16;
12649 if (!inst
.operands
[2].isreg
)
12651 bfd_boolean narrow
;
12653 if ((inst
.instruction
& 0x00100000) != 0)
12654 narrow
= !in_it_block ();
12656 narrow
= in_it_block ();
12658 if (Rd
> 7 || Rs
> 7)
12661 if (inst
.size_req
== 4 || !unified_syntax
)
12664 if (inst
.reloc
.exp
.X_op
!= O_constant
12665 || inst
.reloc
.exp
.X_add_number
!= 0)
12668 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12669 relaxation, but it doesn't seem worth the hassle. */
12672 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12673 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12674 inst
.instruction
|= Rs
<< 3;
12675 inst
.instruction
|= Rd
;
12679 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12680 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12684 encode_thumb32_shifted_operand (2);
12690 if (warn_on_deprecated
12691 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12692 as_tsktsk (_("setend use is deprecated for ARMv8"));
12694 set_it_insn_type (OUTSIDE_IT_INSN
);
12695 if (inst
.operands
[0].imm
)
12696 inst
.instruction
|= 0x8;
12702 if (!inst
.operands
[1].present
)
12703 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12705 if (unified_syntax
)
12707 bfd_boolean narrow
;
12710 switch (inst
.instruction
)
12713 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12715 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12717 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12719 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12723 if (THUMB_SETS_FLAGS (inst
.instruction
))
12724 narrow
= !in_it_block ();
12726 narrow
= in_it_block ();
12727 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12729 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12731 if (inst
.operands
[2].isreg
12732 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12733 || inst
.operands
[2].reg
> 7))
12735 if (inst
.size_req
== 4)
12738 reject_bad_reg (inst
.operands
[0].reg
);
12739 reject_bad_reg (inst
.operands
[1].reg
);
12743 if (inst
.operands
[2].isreg
)
12745 reject_bad_reg (inst
.operands
[2].reg
);
12746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12747 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12748 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12749 inst
.instruction
|= inst
.operands
[2].reg
;
12751 /* PR 12854: Error on extraneous shifts. */
12752 constraint (inst
.operands
[2].shifted
,
12753 _("extraneous shift as part of operand to shift insn"));
12757 inst
.operands
[1].shifted
= 1;
12758 inst
.operands
[1].shift_kind
= shift_kind
;
12759 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12760 ? T_MNEM_movs
: T_MNEM_mov
);
12761 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12762 encode_thumb32_shifted_operand (1);
12763 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12764 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12769 if (inst
.operands
[2].isreg
)
12771 switch (shift_kind
)
12773 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12774 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12775 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12776 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12780 inst
.instruction
|= inst
.operands
[0].reg
;
12781 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12783 /* PR 12854: Error on extraneous shifts. */
12784 constraint (inst
.operands
[2].shifted
,
12785 _("extraneous shift as part of operand to shift insn"));
12789 switch (shift_kind
)
12791 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12792 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12793 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12796 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12797 inst
.instruction
|= inst
.operands
[0].reg
;
12798 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12804 constraint (inst
.operands
[0].reg
> 7
12805 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12806 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12808 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12810 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12811 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12812 _("source1 and dest must be same register"));
12814 switch (inst
.instruction
)
12816 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12817 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12818 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12819 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12823 inst
.instruction
|= inst
.operands
[0].reg
;
12824 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12826 /* PR 12854: Error on extraneous shifts. */
12827 constraint (inst
.operands
[2].shifted
,
12828 _("extraneous shift as part of operand to shift insn"));
12832 switch (inst
.instruction
)
12834 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12835 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12836 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12837 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12840 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12841 inst
.instruction
|= inst
.operands
[0].reg
;
12842 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12850 unsigned Rd
, Rn
, Rm
;
12852 Rd
= inst
.operands
[0].reg
;
12853 Rn
= inst
.operands
[1].reg
;
12854 Rm
= inst
.operands
[2].reg
;
12856 reject_bad_reg (Rd
);
12857 reject_bad_reg (Rn
);
12858 reject_bad_reg (Rm
);
12860 inst
.instruction
|= Rd
<< 8;
12861 inst
.instruction
|= Rn
<< 16;
12862 inst
.instruction
|= Rm
;
12868 unsigned Rd
, Rn
, Rm
;
12870 Rd
= inst
.operands
[0].reg
;
12871 Rm
= inst
.operands
[1].reg
;
12872 Rn
= inst
.operands
[2].reg
;
12874 reject_bad_reg (Rd
);
12875 reject_bad_reg (Rn
);
12876 reject_bad_reg (Rm
);
12878 inst
.instruction
|= Rd
<< 8;
12879 inst
.instruction
|= Rn
<< 16;
12880 inst
.instruction
|= Rm
;
12886 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12887 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12888 _("SMC is not permitted on this architecture"));
12889 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12890 _("expression too complex"));
12891 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12892 inst
.instruction
|= (value
& 0xf000) >> 12;
12893 inst
.instruction
|= (value
& 0x0ff0);
12894 inst
.instruction
|= (value
& 0x000f) << 16;
12895 /* PR gas/15623: SMC instructions must be last in an IT block. */
12896 set_it_insn_type_last ();
12902 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12904 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12905 inst
.instruction
|= (value
& 0x0fff);
12906 inst
.instruction
|= (value
& 0xf000) << 4;
12910 do_t_ssat_usat (int bias
)
12914 Rd
= inst
.operands
[0].reg
;
12915 Rn
= inst
.operands
[2].reg
;
12917 reject_bad_reg (Rd
);
12918 reject_bad_reg (Rn
);
12920 inst
.instruction
|= Rd
<< 8;
12921 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12922 inst
.instruction
|= Rn
<< 16;
12924 if (inst
.operands
[3].present
)
12926 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12928 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12930 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12931 _("expression too complex"));
12933 if (shift_amount
!= 0)
12935 constraint (shift_amount
> 31,
12936 _("shift expression is too large"));
12938 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12939 inst
.instruction
|= 0x00200000; /* sh bit. */
12941 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12942 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12950 do_t_ssat_usat (1);
12958 Rd
= inst
.operands
[0].reg
;
12959 Rn
= inst
.operands
[2].reg
;
12961 reject_bad_reg (Rd
);
12962 reject_bad_reg (Rn
);
12964 inst
.instruction
|= Rd
<< 8;
12965 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12966 inst
.instruction
|= Rn
<< 16;
12972 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12973 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12974 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12975 || inst
.operands
[2].negative
,
12978 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12980 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12981 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12982 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12983 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12989 if (!inst
.operands
[2].present
)
12990 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12992 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12993 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12994 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12997 inst
.instruction
|= inst
.operands
[0].reg
;
12998 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12999 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13000 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13006 unsigned Rd
, Rn
, Rm
;
13008 Rd
= inst
.operands
[0].reg
;
13009 Rn
= inst
.operands
[1].reg
;
13010 Rm
= inst
.operands
[2].reg
;
13012 reject_bad_reg (Rd
);
13013 reject_bad_reg (Rn
);
13014 reject_bad_reg (Rm
);
13016 inst
.instruction
|= Rd
<< 8;
13017 inst
.instruction
|= Rn
<< 16;
13018 inst
.instruction
|= Rm
;
13019 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13027 Rd
= inst
.operands
[0].reg
;
13028 Rm
= inst
.operands
[1].reg
;
13030 reject_bad_reg (Rd
);
13031 reject_bad_reg (Rm
);
13033 if (inst
.instruction
<= 0xffff
13034 && inst
.size_req
!= 4
13035 && Rd
<= 7 && Rm
<= 7
13036 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13038 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13039 inst
.instruction
|= Rd
;
13040 inst
.instruction
|= Rm
<< 3;
13042 else if (unified_syntax
)
13044 if (inst
.instruction
<= 0xffff)
13045 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13046 inst
.instruction
|= Rd
<< 8;
13047 inst
.instruction
|= Rm
;
13048 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13052 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13053 _("Thumb encoding does not support rotation"));
13054 constraint (1, BAD_HIREG
);
13061 /* We have to do the following check manually as ARM_EXT_OS only applies
13063 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13065 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13066 /* This only applies to the v6m howver, not later architectures. */
13067 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13068 as_bad (_("SVC is not permitted on this architecture"));
13069 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13072 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13081 half
= (inst
.instruction
& 0x10) != 0;
13082 set_it_insn_type_last ();
13083 constraint (inst
.operands
[0].immisreg
,
13084 _("instruction requires register index"));
13086 Rn
= inst
.operands
[0].reg
;
13087 Rm
= inst
.operands
[0].imm
;
13089 constraint (Rn
== REG_SP
, BAD_SP
);
13090 reject_bad_reg (Rm
);
13092 constraint (!half
&& inst
.operands
[0].shifted
,
13093 _("instruction does not allow shifted index"));
13094 inst
.instruction
|= (Rn
<< 16) | Rm
;
13100 if (!inst
.operands
[0].present
)
13101 inst
.operands
[0].imm
= 0;
13103 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13105 constraint (inst
.size_req
== 2,
13106 _("immediate value out of range"));
13107 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13108 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13109 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13113 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13114 inst
.instruction
|= inst
.operands
[0].imm
;
13117 set_it_insn_type (NEUTRAL_IT_INSN
);
13124 do_t_ssat_usat (0);
13132 Rd
= inst
.operands
[0].reg
;
13133 Rn
= inst
.operands
[2].reg
;
13135 reject_bad_reg (Rd
);
13136 reject_bad_reg (Rn
);
13138 inst
.instruction
|= Rd
<< 8;
13139 inst
.instruction
|= inst
.operands
[1].imm
;
13140 inst
.instruction
|= Rn
<< 16;
13143 /* Neon instruction encoder helpers. */
13145 /* Encodings for the different types for various Neon opcodes. */
13147 /* An "invalid" code for the following tables. */
13150 struct neon_tab_entry
13153 unsigned float_or_poly
;
13154 unsigned scalar_or_imm
;
13157 /* Map overloaded Neon opcodes to their respective encodings. */
13158 #define NEON_ENC_TAB \
13159 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13160 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13161 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13162 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13163 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13164 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13165 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13166 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13167 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13168 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13169 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13170 /* Register variants of the following two instructions are encoded as
13171 vcge / vcgt with the operands reversed. */ \
13172 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13173 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13174 X(vfma, N_INV, 0x0000c10, N_INV), \
13175 X(vfms, N_INV, 0x0200c10, N_INV), \
13176 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13177 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13178 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13179 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13180 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13181 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13182 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13183 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13184 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13185 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13186 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13187 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13188 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13189 X(vshl, 0x0000400, N_INV, 0x0800510), \
13190 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13191 X(vand, 0x0000110, N_INV, 0x0800030), \
13192 X(vbic, 0x0100110, N_INV, 0x0800030), \
13193 X(veor, 0x1000110, N_INV, N_INV), \
13194 X(vorn, 0x0300110, N_INV, 0x0800010), \
13195 X(vorr, 0x0200110, N_INV, 0x0800010), \
13196 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13197 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13198 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13199 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13200 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13201 X(vst1, 0x0000000, 0x0800000, N_INV), \
13202 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13203 X(vst2, 0x0000100, 0x0800100, N_INV), \
13204 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13205 X(vst3, 0x0000200, 0x0800200, N_INV), \
13206 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13207 X(vst4, 0x0000300, 0x0800300, N_INV), \
13208 X(vmovn, 0x1b20200, N_INV, N_INV), \
13209 X(vtrn, 0x1b20080, N_INV, N_INV), \
13210 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13211 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13212 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13213 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13214 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13215 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13216 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13217 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13218 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13219 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13220 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13221 X(vseleq, 0xe000a00, N_INV, N_INV), \
13222 X(vselvs, 0xe100a00, N_INV, N_INV), \
13223 X(vselge, 0xe200a00, N_INV, N_INV), \
13224 X(vselgt, 0xe300a00, N_INV, N_INV), \
13225 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13226 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13227 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13228 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13229 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13230 X(aes, 0x3b00300, N_INV, N_INV), \
13231 X(sha3op, 0x2000c00, N_INV, N_INV), \
13232 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13233 X(sha2op, 0x3ba0380, N_INV, N_INV)
13237 #define X(OPC,I,F,S) N_MNEM_##OPC
13242 static const struct neon_tab_entry neon_enc_tab
[] =
13244 #define X(OPC,I,F,S) { (I), (F), (S) }
13249 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13250 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13251 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13252 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13253 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13254 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13255 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13256 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13257 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13258 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13259 #define NEON_ENC_SINGLE_(X) \
13260 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13261 #define NEON_ENC_DOUBLE_(X) \
13262 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13263 #define NEON_ENC_FPV8_(X) \
13264 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13266 #define NEON_ENCODE(type, inst) \
13269 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13270 inst.is_neon = 1; \
13274 #define check_neon_suffixes \
13277 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13279 as_bad (_("invalid neon suffix for non neon instruction")); \
13285 /* Define shapes for instruction operands. The following mnemonic characters
13286 are used in this table:
13288 F - VFP S<n> register
13289 D - Neon D<n> register
13290 Q - Neon Q<n> register
13294 L - D<n> register list
13296 This table is used to generate various data:
13297 - enumerations of the form NS_DDR to be used as arguments to
13299 - a table classifying shapes into single, double, quad, mixed.
13300 - a table used to drive neon_select_shape. */
13302 #define NEON_SHAPE_DEF \
13303 X(3, (D, D, D), DOUBLE), \
13304 X(3, (Q, Q, Q), QUAD), \
13305 X(3, (D, D, I), DOUBLE), \
13306 X(3, (Q, Q, I), QUAD), \
13307 X(3, (D, D, S), DOUBLE), \
13308 X(3, (Q, Q, S), QUAD), \
13309 X(2, (D, D), DOUBLE), \
13310 X(2, (Q, Q), QUAD), \
13311 X(2, (D, S), DOUBLE), \
13312 X(2, (Q, S), QUAD), \
13313 X(2, (D, R), DOUBLE), \
13314 X(2, (Q, R), QUAD), \
13315 X(2, (D, I), DOUBLE), \
13316 X(2, (Q, I), QUAD), \
13317 X(3, (D, L, D), DOUBLE), \
13318 X(2, (D, Q), MIXED), \
13319 X(2, (Q, D), MIXED), \
13320 X(3, (D, Q, I), MIXED), \
13321 X(3, (Q, D, I), MIXED), \
13322 X(3, (Q, D, D), MIXED), \
13323 X(3, (D, Q, Q), MIXED), \
13324 X(3, (Q, Q, D), MIXED), \
13325 X(3, (Q, D, S), MIXED), \
13326 X(3, (D, Q, S), MIXED), \
13327 X(4, (D, D, D, I), DOUBLE), \
13328 X(4, (Q, Q, Q, I), QUAD), \
13329 X(2, (F, F), SINGLE), \
13330 X(3, (F, F, F), SINGLE), \
13331 X(2, (F, I), SINGLE), \
13332 X(2, (F, D), MIXED), \
13333 X(2, (D, F), MIXED), \
13334 X(3, (F, F, I), MIXED), \
13335 X(4, (R, R, F, F), SINGLE), \
13336 X(4, (F, F, R, R), SINGLE), \
13337 X(3, (D, R, R), DOUBLE), \
13338 X(3, (R, R, D), DOUBLE), \
13339 X(2, (S, R), SINGLE), \
13340 X(2, (R, S), SINGLE), \
13341 X(2, (F, R), SINGLE), \
13342 X(2, (R, F), SINGLE), \
13343 /* Half float shape supported so far. */\
13344 X (2, (H, D), MIXED), \
13345 X (2, (D, H), MIXED), \
13346 X (2, (H, F), MIXED), \
13347 X (2, (F, H), MIXED), \
13348 X (2, (H, H), HALF), \
13349 X (2, (H, R), HALF), \
13350 X (2, (R, H), HALF), \
13351 X (2, (H, I), HALF), \
13352 X (3, (H, H, H), HALF), \
13353 X (3, (H, F, I), MIXED), \
13354 X (3, (F, H, I), MIXED)
13356 #define S2(A,B) NS_##A##B
13357 #define S3(A,B,C) NS_##A##B##C
13358 #define S4(A,B,C,D) NS_##A##B##C##D
13360 #define X(N, L, C) S##N L
13373 enum neon_shape_class
13382 #define X(N, L, C) SC_##C
13384 static enum neon_shape_class neon_shape_class
[] =
13403 /* Register widths of above. */
13404 static unsigned neon_shape_el_size
[] =
13416 struct neon_shape_info
13419 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13422 #define S2(A,B) { SE_##A, SE_##B }
13423 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13424 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13426 #define X(N, L, C) { N, S##N L }
13428 static struct neon_shape_info neon_shape_tab
[] =
13438 /* Bit masks used in type checking given instructions.
13439 'N_EQK' means the type must be the same as (or based on in some way) the key
13440 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13441 set, various other bits can be set as well in order to modify the meaning of
13442 the type constraint. */
13444 enum neon_type_mask
13468 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13469 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13470 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13471 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13472 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13473 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13474 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13475 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13476 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13477 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13478 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13480 N_MAX_NONSPECIAL
= N_P64
13483 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13485 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13486 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13487 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13488 #define N_S_32 (N_S8 | N_S16 | N_S32)
13489 #define N_F_16_32 (N_F16 | N_F32)
13490 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13491 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13492 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13493 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13495 /* Pass this as the first type argument to neon_check_type to ignore types
13497 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13499 /* Select a "shape" for the current instruction (describing register types or
13500 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13501 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13502 function of operand parsing, so this function doesn't need to be called.
13503 Shapes should be listed in order of decreasing length. */
13505 static enum neon_shape
13506 neon_select_shape (enum neon_shape shape
, ...)
13509 enum neon_shape first_shape
= shape
;
13511 /* Fix missing optional operands. FIXME: we don't know at this point how
13512 many arguments we should have, so this makes the assumption that we have
13513 > 1. This is true of all current Neon opcodes, I think, but may not be
13514 true in the future. */
13515 if (!inst
.operands
[1].present
)
13516 inst
.operands
[1] = inst
.operands
[0];
13518 va_start (ap
, shape
);
13520 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13525 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13527 if (!inst
.operands
[j
].present
)
13533 switch (neon_shape_tab
[shape
].el
[j
])
13535 /* If a .f16, .16, .u16, .s16 type specifier is given over
13536 a VFP single precision register operand, it's essentially
13537 means only half of the register is used.
13539 If the type specifier is given after the mnemonics, the
13540 information is stored in inst.vectype. If the type specifier
13541 is given after register operand, the information is stored
13542 in inst.operands[].vectype.
13544 When there is only one type specifier, and all the register
13545 operands are the same type of hardware register, the type
13546 specifier applies to all register operands.
13548 If no type specifier is given, the shape is inferred from
13549 operand information.
13552 vadd.f16 s0, s1, s2: NS_HHH
13553 vabs.f16 s0, s1: NS_HH
13554 vmov.f16 s0, r1: NS_HR
13555 vmov.f16 r0, s1: NS_RH
13556 vcvt.f16 r0, s1: NS_RH
13557 vcvt.f16.s32 s2, s2, #29: NS_HFI
13558 vcvt.f16.s32 s2, s2: NS_HF
13561 if (!(inst
.operands
[j
].isreg
13562 && inst
.operands
[j
].isvec
13563 && inst
.operands
[j
].issingle
13564 && !inst
.operands
[j
].isquad
13565 && ((inst
.vectype
.elems
== 1
13566 && inst
.vectype
.el
[0].size
== 16)
13567 || (inst
.vectype
.elems
> 1
13568 && inst
.vectype
.el
[j
].size
== 16)
13569 || (inst
.vectype
.elems
== 0
13570 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13571 && inst
.operands
[j
].vectype
.size
== 16))))
13576 if (!(inst
.operands
[j
].isreg
13577 && inst
.operands
[j
].isvec
13578 && inst
.operands
[j
].issingle
13579 && !inst
.operands
[j
].isquad
13580 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13581 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13582 || (inst
.vectype
.elems
== 0
13583 && (inst
.operands
[j
].vectype
.size
== 32
13584 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13589 if (!(inst
.operands
[j
].isreg
13590 && inst
.operands
[j
].isvec
13591 && !inst
.operands
[j
].isquad
13592 && !inst
.operands
[j
].issingle
))
13597 if (!(inst
.operands
[j
].isreg
13598 && !inst
.operands
[j
].isvec
))
13603 if (!(inst
.operands
[j
].isreg
13604 && inst
.operands
[j
].isvec
13605 && inst
.operands
[j
].isquad
13606 && !inst
.operands
[j
].issingle
))
13611 if (!(!inst
.operands
[j
].isreg
13612 && !inst
.operands
[j
].isscalar
))
13617 if (!(!inst
.operands
[j
].isreg
13618 && inst
.operands
[j
].isscalar
))
13628 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13629 /* We've matched all the entries in the shape table, and we don't
13630 have any left over operands which have not been matched. */
13636 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13637 first_error (_("invalid instruction shape"));
13642 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13643 means the Q bit should be set). */
13646 neon_quad (enum neon_shape shape
)
13648 return neon_shape_class
[shape
] == SC_QUAD
;
13652 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13655 /* Allow modification to be made to types which are constrained to be
13656 based on the key element, based on bits set alongside N_EQK. */
13657 if ((typebits
& N_EQK
) != 0)
13659 if ((typebits
& N_HLF
) != 0)
13661 else if ((typebits
& N_DBL
) != 0)
13663 if ((typebits
& N_SGN
) != 0)
13664 *g_type
= NT_signed
;
13665 else if ((typebits
& N_UNS
) != 0)
13666 *g_type
= NT_unsigned
;
13667 else if ((typebits
& N_INT
) != 0)
13668 *g_type
= NT_integer
;
13669 else if ((typebits
& N_FLT
) != 0)
13670 *g_type
= NT_float
;
13671 else if ((typebits
& N_SIZ
) != 0)
13672 *g_type
= NT_untyped
;
13676 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13677 operand type, i.e. the single type specified in a Neon instruction when it
13678 is the only one given. */
13680 static struct neon_type_el
13681 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13683 struct neon_type_el dest
= *key
;
13685 gas_assert ((thisarg
& N_EQK
) != 0);
13687 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13692 /* Convert Neon type and size into compact bitmask representation. */
13694 static enum neon_type_mask
13695 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13702 case 8: return N_8
;
13703 case 16: return N_16
;
13704 case 32: return N_32
;
13705 case 64: return N_64
;
13713 case 8: return N_I8
;
13714 case 16: return N_I16
;
13715 case 32: return N_I32
;
13716 case 64: return N_I64
;
13724 case 16: return N_F16
;
13725 case 32: return N_F32
;
13726 case 64: return N_F64
;
13734 case 8: return N_P8
;
13735 case 16: return N_P16
;
13736 case 64: return N_P64
;
13744 case 8: return N_S8
;
13745 case 16: return N_S16
;
13746 case 32: return N_S32
;
13747 case 64: return N_S64
;
13755 case 8: return N_U8
;
13756 case 16: return N_U16
;
13757 case 32: return N_U32
;
13758 case 64: return N_U64
;
13769 /* Convert compact Neon bitmask type representation to a type and size. Only
13770 handles the case where a single bit is set in the mask. */
13773 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13774 enum neon_type_mask mask
)
13776 if ((mask
& N_EQK
) != 0)
13779 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13781 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13783 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13785 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13790 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13792 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13793 *type
= NT_unsigned
;
13794 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13795 *type
= NT_integer
;
13796 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13797 *type
= NT_untyped
;
13798 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13800 else if ((mask
& (N_F_ALL
)) != 0)
13808 /* Modify a bitmask of allowed types. This is only needed for type
13812 modify_types_allowed (unsigned allowed
, unsigned mods
)
13815 enum neon_el_type type
;
13821 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13823 if (el_type_of_type_chk (&type
, &size
,
13824 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13826 neon_modify_type_size (mods
, &type
, &size
);
13827 destmask
|= type_chk_of_el_type (type
, size
);
13834 /* Check type and return type classification.
13835 The manual states (paraphrase): If one datatype is given, it indicates the
13837 - the second operand, if there is one
13838 - the operand, if there is no second operand
13839 - the result, if there are no operands.
13840 This isn't quite good enough though, so we use a concept of a "key" datatype
13841 which is set on a per-instruction basis, which is the one which matters when
13842 only one data type is written.
13843 Note: this function has side-effects (e.g. filling in missing operands). All
13844 Neon instructions should call it before performing bit encoding. */
13846 static struct neon_type_el
13847 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13850 unsigned i
, pass
, key_el
= 0;
13851 unsigned types
[NEON_MAX_TYPE_ELS
];
13852 enum neon_el_type k_type
= NT_invtype
;
13853 unsigned k_size
= -1u;
13854 struct neon_type_el badtype
= {NT_invtype
, -1};
13855 unsigned key_allowed
= 0;
13857 /* Optional registers in Neon instructions are always (not) in operand 1.
13858 Fill in the missing operand here, if it was omitted. */
13859 if (els
> 1 && !inst
.operands
[1].present
)
13860 inst
.operands
[1] = inst
.operands
[0];
13862 /* Suck up all the varargs. */
13864 for (i
= 0; i
< els
; i
++)
13866 unsigned thisarg
= va_arg (ap
, unsigned);
13867 if (thisarg
== N_IGNORE_TYPE
)
13872 types
[i
] = thisarg
;
13873 if ((thisarg
& N_KEY
) != 0)
13878 if (inst
.vectype
.elems
> 0)
13879 for (i
= 0; i
< els
; i
++)
13880 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13882 first_error (_("types specified in both the mnemonic and operands"));
13886 /* Duplicate inst.vectype elements here as necessary.
13887 FIXME: No idea if this is exactly the same as the ARM assembler,
13888 particularly when an insn takes one register and one non-register
13890 if (inst
.vectype
.elems
== 1 && els
> 1)
13893 inst
.vectype
.elems
= els
;
13894 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13895 for (j
= 0; j
< els
; j
++)
13897 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13900 else if (inst
.vectype
.elems
== 0 && els
> 0)
13903 /* No types were given after the mnemonic, so look for types specified
13904 after each operand. We allow some flexibility here; as long as the
13905 "key" operand has a type, we can infer the others. */
13906 for (j
= 0; j
< els
; j
++)
13907 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13908 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13910 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13912 for (j
= 0; j
< els
; j
++)
13913 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13914 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13919 first_error (_("operand types can't be inferred"));
13923 else if (inst
.vectype
.elems
!= els
)
13925 first_error (_("type specifier has the wrong number of parts"));
13929 for (pass
= 0; pass
< 2; pass
++)
13931 for (i
= 0; i
< els
; i
++)
13933 unsigned thisarg
= types
[i
];
13934 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13935 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13936 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13937 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13939 /* Decay more-specific signed & unsigned types to sign-insensitive
13940 integer types if sign-specific variants are unavailable. */
13941 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13942 && (types_allowed
& N_SU_ALL
) == 0)
13943 g_type
= NT_integer
;
13945 /* If only untyped args are allowed, decay any more specific types to
13946 them. Some instructions only care about signs for some element
13947 sizes, so handle that properly. */
13948 if (((types_allowed
& N_UNT
) == 0)
13949 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13950 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13951 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13952 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13953 g_type
= NT_untyped
;
13957 if ((thisarg
& N_KEY
) != 0)
13961 key_allowed
= thisarg
& ~N_KEY
;
13963 /* Check architecture constraint on FP16 extension. */
13965 && k_type
== NT_float
13966 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13968 inst
.error
= _(BAD_FP16
);
13975 if ((thisarg
& N_VFP
) != 0)
13977 enum neon_shape_el regshape
;
13978 unsigned regwidth
, match
;
13980 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13983 first_error (_("invalid instruction shape"));
13986 regshape
= neon_shape_tab
[ns
].el
[i
];
13987 regwidth
= neon_shape_el_size
[regshape
];
13989 /* In VFP mode, operands must match register widths. If we
13990 have a key operand, use its width, else use the width of
13991 the current operand. */
13997 /* FP16 will use a single precision register. */
13998 if (regwidth
== 32 && match
== 16)
14000 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14004 inst
.error
= _(BAD_FP16
);
14009 if (regwidth
!= match
)
14011 first_error (_("operand size must match register width"));
14016 if ((thisarg
& N_EQK
) == 0)
14018 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14020 if ((given_type
& types_allowed
) == 0)
14022 first_error (_("bad type in Neon instruction"));
14028 enum neon_el_type mod_k_type
= k_type
;
14029 unsigned mod_k_size
= k_size
;
14030 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14031 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14033 first_error (_("inconsistent types in Neon instruction"));
14041 return inst
.vectype
.el
[key_el
];
14044 /* Neon-style VFP instruction forwarding. */
14046 /* Thumb VFP instructions have 0xE in the condition field. */
14049 do_vfp_cond_or_thumb (void)
14054 inst
.instruction
|= 0xe0000000;
14056 inst
.instruction
|= inst
.cond
<< 28;
14059 /* Look up and encode a simple mnemonic, for use as a helper function for the
14060 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14061 etc. It is assumed that operand parsing has already been done, and that the
14062 operands are in the form expected by the given opcode (this isn't necessarily
14063 the same as the form in which they were parsed, hence some massaging must
14064 take place before this function is called).
14065 Checks current arch version against that in the looked-up opcode. */
14068 do_vfp_nsyn_opcode (const char *opname
)
14070 const struct asm_opcode
*opcode
;
14072 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14077 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14078 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14085 inst
.instruction
= opcode
->tvalue
;
14086 opcode
->tencode ();
14090 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14091 opcode
->aencode ();
14096 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14098 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14100 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14103 do_vfp_nsyn_opcode ("fadds");
14105 do_vfp_nsyn_opcode ("fsubs");
14107 /* ARMv8.2 fp16 instruction. */
14109 do_scalar_fp16_v82_encode ();
14114 do_vfp_nsyn_opcode ("faddd");
14116 do_vfp_nsyn_opcode ("fsubd");
14120 /* Check operand types to see if this is a VFP instruction, and if so call
14124 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14126 enum neon_shape rs
;
14127 struct neon_type_el et
;
14132 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14133 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14137 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14138 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14139 N_F_ALL
| N_KEY
| N_VFP
);
14146 if (et
.type
!= NT_invtype
)
14157 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14159 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14161 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14164 do_vfp_nsyn_opcode ("fmacs");
14166 do_vfp_nsyn_opcode ("fnmacs");
14168 /* ARMv8.2 fp16 instruction. */
14170 do_scalar_fp16_v82_encode ();
14175 do_vfp_nsyn_opcode ("fmacd");
14177 do_vfp_nsyn_opcode ("fnmacd");
14182 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14184 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14186 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14189 do_vfp_nsyn_opcode ("ffmas");
14191 do_vfp_nsyn_opcode ("ffnmas");
14193 /* ARMv8.2 fp16 instruction. */
14195 do_scalar_fp16_v82_encode ();
14200 do_vfp_nsyn_opcode ("ffmad");
14202 do_vfp_nsyn_opcode ("ffnmad");
14207 do_vfp_nsyn_mul (enum neon_shape rs
)
14209 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14211 do_vfp_nsyn_opcode ("fmuls");
14213 /* ARMv8.2 fp16 instruction. */
14215 do_scalar_fp16_v82_encode ();
14218 do_vfp_nsyn_opcode ("fmuld");
14222 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14224 int is_neg
= (inst
.instruction
& 0x80) != 0;
14225 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14227 if (rs
== NS_FF
|| rs
== NS_HH
)
14230 do_vfp_nsyn_opcode ("fnegs");
14232 do_vfp_nsyn_opcode ("fabss");
14234 /* ARMv8.2 fp16 instruction. */
14236 do_scalar_fp16_v82_encode ();
14241 do_vfp_nsyn_opcode ("fnegd");
14243 do_vfp_nsyn_opcode ("fabsd");
14247 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14248 insns belong to Neon, and are handled elsewhere. */
14251 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14253 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14257 do_vfp_nsyn_opcode ("fldmdbs");
14259 do_vfp_nsyn_opcode ("fldmias");
14264 do_vfp_nsyn_opcode ("fstmdbs");
14266 do_vfp_nsyn_opcode ("fstmias");
14271 do_vfp_nsyn_sqrt (void)
14273 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14274 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14276 if (rs
== NS_FF
|| rs
== NS_HH
)
14278 do_vfp_nsyn_opcode ("fsqrts");
14280 /* ARMv8.2 fp16 instruction. */
14282 do_scalar_fp16_v82_encode ();
14285 do_vfp_nsyn_opcode ("fsqrtd");
14289 do_vfp_nsyn_div (void)
14291 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14292 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14293 N_F_ALL
| N_KEY
| N_VFP
);
14295 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14297 do_vfp_nsyn_opcode ("fdivs");
14299 /* ARMv8.2 fp16 instruction. */
14301 do_scalar_fp16_v82_encode ();
14304 do_vfp_nsyn_opcode ("fdivd");
14308 do_vfp_nsyn_nmul (void)
14310 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14311 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14312 N_F_ALL
| N_KEY
| N_VFP
);
14314 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14316 NEON_ENCODE (SINGLE
, inst
);
14317 do_vfp_sp_dyadic ();
14319 /* ARMv8.2 fp16 instruction. */
14321 do_scalar_fp16_v82_encode ();
14325 NEON_ENCODE (DOUBLE
, inst
);
14326 do_vfp_dp_rd_rn_rm ();
14328 do_vfp_cond_or_thumb ();
14333 do_vfp_nsyn_cmp (void)
14335 enum neon_shape rs
;
14336 if (inst
.operands
[1].isreg
)
14338 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14339 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14341 if (rs
== NS_FF
|| rs
== NS_HH
)
14343 NEON_ENCODE (SINGLE
, inst
);
14344 do_vfp_sp_monadic ();
14348 NEON_ENCODE (DOUBLE
, inst
);
14349 do_vfp_dp_rd_rm ();
14354 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14355 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14357 switch (inst
.instruction
& 0x0fffffff)
14360 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14363 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14369 if (rs
== NS_FI
|| rs
== NS_HI
)
14371 NEON_ENCODE (SINGLE
, inst
);
14372 do_vfp_sp_compare_z ();
14376 NEON_ENCODE (DOUBLE
, inst
);
14380 do_vfp_cond_or_thumb ();
14382 /* ARMv8.2 fp16 instruction. */
14383 if (rs
== NS_HI
|| rs
== NS_HH
)
14384 do_scalar_fp16_v82_encode ();
14388 nsyn_insert_sp (void)
14390 inst
.operands
[1] = inst
.operands
[0];
14391 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14392 inst
.operands
[0].reg
= REG_SP
;
14393 inst
.operands
[0].isreg
= 1;
14394 inst
.operands
[0].writeback
= 1;
14395 inst
.operands
[0].present
= 1;
14399 do_vfp_nsyn_push (void)
14403 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14404 _("register list must contain at least 1 and at most 16 "
14407 if (inst
.operands
[1].issingle
)
14408 do_vfp_nsyn_opcode ("fstmdbs");
14410 do_vfp_nsyn_opcode ("fstmdbd");
14414 do_vfp_nsyn_pop (void)
14418 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14419 _("register list must contain at least 1 and at most 16 "
14422 if (inst
.operands
[1].issingle
)
14423 do_vfp_nsyn_opcode ("fldmias");
14425 do_vfp_nsyn_opcode ("fldmiad");
14428 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14429 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14432 neon_dp_fixup (struct arm_it
* insn
)
14434 unsigned int i
= insn
->instruction
;
14439 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14450 insn
->instruction
= i
;
14453 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14457 neon_logbits (unsigned x
)
14459 return ffs (x
) - 4;
14462 #define LOW4(R) ((R) & 0xf)
14463 #define HI1(R) (((R) >> 4) & 1)
14465 /* Encode insns with bit pattern:
14467 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14468 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14470 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14471 different meaning for some instruction. */
14474 neon_three_same (int isquad
, int ubit
, int size
)
14476 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14477 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14478 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14479 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14480 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14481 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14482 inst
.instruction
|= (isquad
!= 0) << 6;
14483 inst
.instruction
|= (ubit
!= 0) << 24;
14485 inst
.instruction
|= neon_logbits (size
) << 20;
14487 neon_dp_fixup (&inst
);
14490 /* Encode instructions of the form:
14492 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14493 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14495 Don't write size if SIZE == -1. */
14498 neon_two_same (int qbit
, int ubit
, int size
)
14500 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14501 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14502 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14503 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14504 inst
.instruction
|= (qbit
!= 0) << 6;
14505 inst
.instruction
|= (ubit
!= 0) << 24;
14508 inst
.instruction
|= neon_logbits (size
) << 18;
14510 neon_dp_fixup (&inst
);
14513 /* Neon instruction encoders, in approximate order of appearance. */
14516 do_neon_dyadic_i_su (void)
14518 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14519 struct neon_type_el et
= neon_check_type (3, rs
,
14520 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14521 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14525 do_neon_dyadic_i64_su (void)
14527 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14528 struct neon_type_el et
= neon_check_type (3, rs
,
14529 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14530 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14534 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14537 unsigned size
= et
.size
>> 3;
14538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14540 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14541 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14542 inst
.instruction
|= (isquad
!= 0) << 6;
14543 inst
.instruction
|= immbits
<< 16;
14544 inst
.instruction
|= (size
>> 3) << 7;
14545 inst
.instruction
|= (size
& 0x7) << 19;
14547 inst
.instruction
|= (uval
!= 0) << 24;
14549 neon_dp_fixup (&inst
);
14553 do_neon_shl_imm (void)
14555 if (!inst
.operands
[2].isreg
)
14557 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14558 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14559 int imm
= inst
.operands
[2].imm
;
14561 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14562 _("immediate out of range for shift"));
14563 NEON_ENCODE (IMMED
, inst
);
14564 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14568 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14569 struct neon_type_el et
= neon_check_type (3, rs
,
14570 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14573 /* VSHL/VQSHL 3-register variants have syntax such as:
14575 whereas other 3-register operations encoded by neon_three_same have
14578 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14580 tmp
= inst
.operands
[2].reg
;
14581 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14582 inst
.operands
[1].reg
= tmp
;
14583 NEON_ENCODE (INTEGER
, inst
);
14584 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14589 do_neon_qshl_imm (void)
14591 if (!inst
.operands
[2].isreg
)
14593 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14594 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14595 int imm
= inst
.operands
[2].imm
;
14597 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14598 _("immediate out of range for shift"));
14599 NEON_ENCODE (IMMED
, inst
);
14600 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14604 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14605 struct neon_type_el et
= neon_check_type (3, rs
,
14606 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14609 /* See note in do_neon_shl_imm. */
14610 tmp
= inst
.operands
[2].reg
;
14611 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14612 inst
.operands
[1].reg
= tmp
;
14613 NEON_ENCODE (INTEGER
, inst
);
14614 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14619 do_neon_rshl (void)
14621 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14622 struct neon_type_el et
= neon_check_type (3, rs
,
14623 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14626 tmp
= inst
.operands
[2].reg
;
14627 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14628 inst
.operands
[1].reg
= tmp
;
14629 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14633 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14635 /* Handle .I8 pseudo-instructions. */
14638 /* Unfortunately, this will make everything apart from zero out-of-range.
14639 FIXME is this the intended semantics? There doesn't seem much point in
14640 accepting .I8 if so. */
14641 immediate
|= immediate
<< 8;
14647 if (immediate
== (immediate
& 0x000000ff))
14649 *immbits
= immediate
;
14652 else if (immediate
== (immediate
& 0x0000ff00))
14654 *immbits
= immediate
>> 8;
14657 else if (immediate
== (immediate
& 0x00ff0000))
14659 *immbits
= immediate
>> 16;
14662 else if (immediate
== (immediate
& 0xff000000))
14664 *immbits
= immediate
>> 24;
14667 if ((immediate
& 0xffff) != (immediate
>> 16))
14668 goto bad_immediate
;
14669 immediate
&= 0xffff;
14672 if (immediate
== (immediate
& 0x000000ff))
14674 *immbits
= immediate
;
14677 else if (immediate
== (immediate
& 0x0000ff00))
14679 *immbits
= immediate
>> 8;
14684 first_error (_("immediate value out of range"));
14689 do_neon_logic (void)
14691 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14693 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14694 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14695 /* U bit and size field were set as part of the bitmask. */
14696 NEON_ENCODE (INTEGER
, inst
);
14697 neon_three_same (neon_quad (rs
), 0, -1);
14701 const int three_ops_form
= (inst
.operands
[2].present
14702 && !inst
.operands
[2].isreg
);
14703 const int immoperand
= (three_ops_form
? 2 : 1);
14704 enum neon_shape rs
= (three_ops_form
14705 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14706 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14707 struct neon_type_el et
= neon_check_type (2, rs
,
14708 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14709 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14713 if (et
.type
== NT_invtype
)
14716 if (three_ops_form
)
14717 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14718 _("first and second operands shall be the same register"));
14720 NEON_ENCODE (IMMED
, inst
);
14722 immbits
= inst
.operands
[immoperand
].imm
;
14725 /* .i64 is a pseudo-op, so the immediate must be a repeating
14727 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14728 inst
.operands
[immoperand
].reg
: 0))
14730 /* Set immbits to an invalid constant. */
14731 immbits
= 0xdeadbeef;
14738 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14742 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14746 /* Pseudo-instruction for VBIC. */
14747 neon_invert_size (&immbits
, 0, et
.size
);
14748 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14752 /* Pseudo-instruction for VORR. */
14753 neon_invert_size (&immbits
, 0, et
.size
);
14754 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14764 inst
.instruction
|= neon_quad (rs
) << 6;
14765 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14766 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14767 inst
.instruction
|= cmode
<< 8;
14768 neon_write_immbits (immbits
);
14770 neon_dp_fixup (&inst
);
14775 do_neon_bitfield (void)
14777 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14778 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14779 neon_three_same (neon_quad (rs
), 0, -1);
14783 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14786 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14787 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14789 if (et
.type
== NT_float
)
14791 NEON_ENCODE (FLOAT
, inst
);
14792 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14796 NEON_ENCODE (INTEGER
, inst
);
14797 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14802 do_neon_dyadic_if_su (void)
14804 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14808 do_neon_dyadic_if_su_d (void)
14810 /* This version only allow D registers, but that constraint is enforced during
14811 operand parsing so we don't need to do anything extra here. */
14812 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14816 do_neon_dyadic_if_i_d (void)
14818 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14819 affected if we specify unsigned args. */
14820 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14823 enum vfp_or_neon_is_neon_bits
14826 NEON_CHECK_ARCH
= 2,
14827 NEON_CHECK_ARCH8
= 4
14830 /* Call this function if an instruction which may have belonged to the VFP or
14831 Neon instruction sets, but turned out to be a Neon instruction (due to the
14832 operand types involved, etc.). We have to check and/or fix-up a couple of
14835 - Make sure the user hasn't attempted to make a Neon instruction
14837 - Alter the value in the condition code field if necessary.
14838 - Make sure that the arch supports Neon instructions.
14840 Which of these operations take place depends on bits from enum
14841 vfp_or_neon_is_neon_bits.
14843 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14844 current instruction's condition is COND_ALWAYS, the condition field is
14845 changed to inst.uncond_value. This is necessary because instructions shared
14846 between VFP and Neon may be conditional for the VFP variants only, and the
14847 unconditional Neon version must have, e.g., 0xF in the condition field. */
14850 vfp_or_neon_is_neon (unsigned check
)
14852 /* Conditions are always legal in Thumb mode (IT blocks). */
14853 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14855 if (inst
.cond
!= COND_ALWAYS
)
14857 first_error (_(BAD_COND
));
14860 if (inst
.uncond_value
!= -1)
14861 inst
.instruction
|= inst
.uncond_value
<< 28;
14864 if ((check
& NEON_CHECK_ARCH
)
14865 && !mark_feature_used (&fpu_neon_ext_v1
))
14867 first_error (_(BAD_FPU
));
14871 if ((check
& NEON_CHECK_ARCH8
)
14872 && !mark_feature_used (&fpu_neon_ext_armv8
))
14874 first_error (_(BAD_FPU
));
14882 do_neon_addsub_if_i (void)
14884 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14887 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14890 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14891 affected if we specify unsigned args. */
14892 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14895 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14897 V<op> A,B (A is operand 0, B is operand 2)
14902 so handle that case specially. */
14905 neon_exchange_operands (void)
14907 if (inst
.operands
[1].present
)
14909 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14911 /* Swap operands[1] and operands[2]. */
14912 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14913 inst
.operands
[1] = inst
.operands
[2];
14914 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14919 inst
.operands
[1] = inst
.operands
[2];
14920 inst
.operands
[2] = inst
.operands
[0];
14925 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14927 if (inst
.operands
[2].isreg
)
14930 neon_exchange_operands ();
14931 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14935 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14936 struct neon_type_el et
= neon_check_type (2, rs
,
14937 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14939 NEON_ENCODE (IMMED
, inst
);
14940 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14941 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14943 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14944 inst
.instruction
|= neon_quad (rs
) << 6;
14945 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14946 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14948 neon_dp_fixup (&inst
);
14955 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14959 do_neon_cmp_inv (void)
14961 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14967 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14970 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14971 scalars, which are encoded in 5 bits, M : Rm.
14972 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14973 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14977 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14979 unsigned regno
= NEON_SCALAR_REG (scalar
);
14980 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14985 if (regno
> 7 || elno
> 3)
14987 return regno
| (elno
<< 3);
14990 if (regno
> 15 || elno
> 1)
14992 return regno
| (elno
<< 4);
14996 first_error (_("scalar out of range for multiply instruction"));
15002 /* Encode multiply / multiply-accumulate scalar instructions. */
15005 neon_mul_mac (struct neon_type_el et
, int ubit
)
15009 /* Give a more helpful error message if we have an invalid type. */
15010 if (et
.type
== NT_invtype
)
15013 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15016 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15017 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15018 inst
.instruction
|= LOW4 (scalar
);
15019 inst
.instruction
|= HI1 (scalar
) << 5;
15020 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15021 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15022 inst
.instruction
|= (ubit
!= 0) << 24;
15024 neon_dp_fixup (&inst
);
15028 do_neon_mac_maybe_scalar (void)
15030 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15033 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15036 if (inst
.operands
[2].isscalar
)
15038 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15039 struct neon_type_el et
= neon_check_type (3, rs
,
15040 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15041 NEON_ENCODE (SCALAR
, inst
);
15042 neon_mul_mac (et
, neon_quad (rs
));
15046 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15047 affected if we specify unsigned args. */
15048 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15053 do_neon_fmac (void)
15055 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15058 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15061 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15067 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15068 struct neon_type_el et
= neon_check_type (3, rs
,
15069 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15070 neon_three_same (neon_quad (rs
), 0, et
.size
);
15073 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15074 same types as the MAC equivalents. The polynomial type for this instruction
15075 is encoded the same as the integer type. */
15080 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15083 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15086 if (inst
.operands
[2].isscalar
)
15087 do_neon_mac_maybe_scalar ();
15089 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15093 do_neon_qdmulh (void)
15095 if (inst
.operands
[2].isscalar
)
15097 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15098 struct neon_type_el et
= neon_check_type (3, rs
,
15099 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15100 NEON_ENCODE (SCALAR
, inst
);
15101 neon_mul_mac (et
, neon_quad (rs
));
15105 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15106 struct neon_type_el et
= neon_check_type (3, rs
,
15107 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15108 NEON_ENCODE (INTEGER
, inst
);
15109 /* The U bit (rounding) comes from bit mask. */
15110 neon_three_same (neon_quad (rs
), 0, et
.size
);
15115 do_neon_qrdmlah (void)
15117 /* Check we're on the correct architecture. */
15118 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15120 _("instruction form not available on this architecture.");
15121 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15123 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15124 record_feature_use (&fpu_neon_ext_v8_1
);
15127 if (inst
.operands
[2].isscalar
)
15129 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15130 struct neon_type_el et
= neon_check_type (3, rs
,
15131 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15132 NEON_ENCODE (SCALAR
, inst
);
15133 neon_mul_mac (et
, neon_quad (rs
));
15137 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15138 struct neon_type_el et
= neon_check_type (3, rs
,
15139 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15140 NEON_ENCODE (INTEGER
, inst
);
15141 /* The U bit (rounding) comes from bit mask. */
15142 neon_three_same (neon_quad (rs
), 0, et
.size
);
15147 do_neon_fcmp_absolute (void)
15149 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15150 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15151 N_F_16_32
| N_KEY
);
15152 /* Size field comes from bit mask. */
15153 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15157 do_neon_fcmp_absolute_inv (void)
15159 neon_exchange_operands ();
15160 do_neon_fcmp_absolute ();
15164 do_neon_step (void)
15166 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15167 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15168 N_F_16_32
| N_KEY
);
15169 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15173 do_neon_abs_neg (void)
15175 enum neon_shape rs
;
15176 struct neon_type_el et
;
15178 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15181 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15184 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15185 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15188 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15189 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15190 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15191 inst
.instruction
|= neon_quad (rs
) << 6;
15192 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15193 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15195 neon_dp_fixup (&inst
);
15201 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15202 struct neon_type_el et
= neon_check_type (2, rs
,
15203 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15204 int imm
= inst
.operands
[2].imm
;
15205 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15206 _("immediate out of range for insert"));
15207 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15213 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15214 struct neon_type_el et
= neon_check_type (2, rs
,
15215 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15216 int imm
= inst
.operands
[2].imm
;
15217 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15218 _("immediate out of range for insert"));
15219 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15223 do_neon_qshlu_imm (void)
15225 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15226 struct neon_type_el et
= neon_check_type (2, rs
,
15227 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15228 int imm
= inst
.operands
[2].imm
;
15229 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15230 _("immediate out of range for shift"));
15231 /* Only encodes the 'U present' variant of the instruction.
15232 In this case, signed types have OP (bit 8) set to 0.
15233 Unsigned types have OP set to 1. */
15234 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15235 /* The rest of the bits are the same as other immediate shifts. */
15236 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15240 do_neon_qmovn (void)
15242 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15243 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15244 /* Saturating move where operands can be signed or unsigned, and the
15245 destination has the same signedness. */
15246 NEON_ENCODE (INTEGER
, inst
);
15247 if (et
.type
== NT_unsigned
)
15248 inst
.instruction
|= 0xc0;
15250 inst
.instruction
|= 0x80;
15251 neon_two_same (0, 1, et
.size
/ 2);
15255 do_neon_qmovun (void)
15257 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15258 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15259 /* Saturating move with unsigned results. Operands must be signed. */
15260 NEON_ENCODE (INTEGER
, inst
);
15261 neon_two_same (0, 1, et
.size
/ 2);
15265 do_neon_rshift_sat_narrow (void)
15267 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15268 or unsigned. If operands are unsigned, results must also be unsigned. */
15269 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15270 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15271 int imm
= inst
.operands
[2].imm
;
15272 /* This gets the bounds check, size encoding and immediate bits calculation
15276 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15277 VQMOVN.I<size> <Dd>, <Qm>. */
15280 inst
.operands
[2].present
= 0;
15281 inst
.instruction
= N_MNEM_vqmovn
;
15286 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15287 _("immediate out of range"));
15288 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15292 do_neon_rshift_sat_narrow_u (void)
15294 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15295 or unsigned. If operands are unsigned, results must also be unsigned. */
15296 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15297 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15298 int imm
= inst
.operands
[2].imm
;
15299 /* This gets the bounds check, size encoding and immediate bits calculation
15303 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15304 VQMOVUN.I<size> <Dd>, <Qm>. */
15307 inst
.operands
[2].present
= 0;
15308 inst
.instruction
= N_MNEM_vqmovun
;
15313 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15314 _("immediate out of range"));
15315 /* FIXME: The manual is kind of unclear about what value U should have in
15316 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15318 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15322 do_neon_movn (void)
15324 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15325 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15326 NEON_ENCODE (INTEGER
, inst
);
15327 neon_two_same (0, 1, et
.size
/ 2);
15331 do_neon_rshift_narrow (void)
15333 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15334 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15335 int imm
= inst
.operands
[2].imm
;
15336 /* This gets the bounds check, size encoding and immediate bits calculation
15340 /* If immediate is zero then we are a pseudo-instruction for
15341 VMOVN.I<size> <Dd>, <Qm> */
15344 inst
.operands
[2].present
= 0;
15345 inst
.instruction
= N_MNEM_vmovn
;
15350 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15351 _("immediate out of range for narrowing operation"));
15352 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15356 do_neon_shll (void)
15358 /* FIXME: Type checking when lengthening. */
15359 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15360 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15361 unsigned imm
= inst
.operands
[2].imm
;
15363 if (imm
== et
.size
)
15365 /* Maximum shift variant. */
15366 NEON_ENCODE (INTEGER
, inst
);
15367 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15368 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15369 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15370 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15371 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15373 neon_dp_fixup (&inst
);
15377 /* A more-specific type check for non-max versions. */
15378 et
= neon_check_type (2, NS_QDI
,
15379 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15380 NEON_ENCODE (IMMED
, inst
);
15381 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15385 /* Check the various types for the VCVT instruction, and return which version
15386 the current instruction is. */
15388 #define CVT_FLAVOUR_VAR \
15389 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15390 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15391 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15392 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15393 /* Half-precision conversions. */ \
15394 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15395 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15396 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15397 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15398 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15399 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15400 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15401 Compared with single/double precision variants, only the co-processor \
15402 field is different, so the encoding flow is reused here. */ \
15403 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15404 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15405 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15406 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15407 /* VFP instructions. */ \
15408 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15409 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15410 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15411 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15412 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15413 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15414 /* VFP instructions with bitshift. */ \
15415 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15416 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15417 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15418 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15419 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15420 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15421 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15422 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15424 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15425 neon_cvt_flavour_##C,
15427 /* The different types of conversions we can do. */
15428 enum neon_cvt_flavour
15431 neon_cvt_flavour_invalid
,
15432 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15437 static enum neon_cvt_flavour
15438 get_neon_cvt_flavour (enum neon_shape rs
)
15440 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15441 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15442 if (et.type != NT_invtype) \
15444 inst.error = NULL; \
15445 return (neon_cvt_flavour_##C); \
15448 struct neon_type_el et
;
15449 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15450 || rs
== NS_FF
) ? N_VFP
: 0;
15451 /* The instruction versions which take an immediate take one register
15452 argument, which is extended to the width of the full register. Thus the
15453 "source" and "destination" registers must have the same width. Hack that
15454 here by making the size equal to the key (wider, in this case) operand. */
15455 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15459 return neon_cvt_flavour_invalid
;
15474 /* Neon-syntax VFP conversions. */
15477 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15479 const char *opname
= 0;
15481 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15482 || rs
== NS_FHI
|| rs
== NS_HFI
)
15484 /* Conversions with immediate bitshift. */
15485 const char *enc
[] =
15487 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15493 if (flavour
< (int) ARRAY_SIZE (enc
))
15495 opname
= enc
[flavour
];
15496 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15497 _("operands 0 and 1 must be the same register"));
15498 inst
.operands
[1] = inst
.operands
[2];
15499 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15504 /* Conversions without bitshift. */
15505 const char *enc
[] =
15507 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15513 if (flavour
< (int) ARRAY_SIZE (enc
))
15514 opname
= enc
[flavour
];
15518 do_vfp_nsyn_opcode (opname
);
15520 /* ARMv8.2 fp16 VCVT instruction. */
15521 if (flavour
== neon_cvt_flavour_s32_f16
15522 || flavour
== neon_cvt_flavour_u32_f16
15523 || flavour
== neon_cvt_flavour_f16_u32
15524 || flavour
== neon_cvt_flavour_f16_s32
)
15525 do_scalar_fp16_v82_encode ();
15529 do_vfp_nsyn_cvtz (void)
15531 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15532 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15533 const char *enc
[] =
15535 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15541 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15542 do_vfp_nsyn_opcode (enc
[flavour
]);
15546 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15547 enum neon_cvt_mode mode
)
15552 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15553 D register operands. */
15554 if (flavour
== neon_cvt_flavour_s32_f64
15555 || flavour
== neon_cvt_flavour_u32_f64
)
15556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15559 if (flavour
== neon_cvt_flavour_s32_f16
15560 || flavour
== neon_cvt_flavour_u32_f16
)
15561 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15564 set_it_insn_type (OUTSIDE_IT_INSN
);
15568 case neon_cvt_flavour_s32_f64
:
15572 case neon_cvt_flavour_s32_f32
:
15576 case neon_cvt_flavour_s32_f16
:
15580 case neon_cvt_flavour_u32_f64
:
15584 case neon_cvt_flavour_u32_f32
:
15588 case neon_cvt_flavour_u32_f16
:
15593 first_error (_("invalid instruction shape"));
15599 case neon_cvt_mode_a
: rm
= 0; break;
15600 case neon_cvt_mode_n
: rm
= 1; break;
15601 case neon_cvt_mode_p
: rm
= 2; break;
15602 case neon_cvt_mode_m
: rm
= 3; break;
15603 default: first_error (_("invalid rounding mode")); return;
15606 NEON_ENCODE (FPV8
, inst
);
15607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15608 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15609 inst
.instruction
|= sz
<< 8;
15611 /* ARMv8.2 fp16 VCVT instruction. */
15612 if (flavour
== neon_cvt_flavour_s32_f16
15613 ||flavour
== neon_cvt_flavour_u32_f16
)
15614 do_scalar_fp16_v82_encode ();
15615 inst
.instruction
|= op
<< 7;
15616 inst
.instruction
|= rm
<< 16;
15617 inst
.instruction
|= 0xf0000000;
15618 inst
.is_neon
= TRUE
;
15622 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15624 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15625 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15626 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15628 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15630 if (flavour
== neon_cvt_flavour_invalid
)
15633 /* PR11109: Handle round-to-zero for VCVT conversions. */
15634 if (mode
== neon_cvt_mode_z
15635 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15636 && (flavour
== neon_cvt_flavour_s16_f16
15637 || flavour
== neon_cvt_flavour_u16_f16
15638 || flavour
== neon_cvt_flavour_s32_f32
15639 || flavour
== neon_cvt_flavour_u32_f32
15640 || flavour
== neon_cvt_flavour_s32_f64
15641 || flavour
== neon_cvt_flavour_u32_f64
)
15642 && (rs
== NS_FD
|| rs
== NS_FF
))
15644 do_vfp_nsyn_cvtz ();
15648 /* ARMv8.2 fp16 VCVT conversions. */
15649 if (mode
== neon_cvt_mode_z
15650 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15651 && (flavour
== neon_cvt_flavour_s32_f16
15652 || flavour
== neon_cvt_flavour_u32_f16
)
15655 do_vfp_nsyn_cvtz ();
15656 do_scalar_fp16_v82_encode ();
15660 /* VFP rather than Neon conversions. */
15661 if (flavour
>= neon_cvt_flavour_first_fp
)
15663 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15664 do_vfp_nsyn_cvt (rs
, flavour
);
15666 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15677 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15678 0x0000100, 0x1000100, 0x0, 0x1000000};
15680 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15683 /* Fixed-point conversion with #0 immediate is encoded as an
15684 integer conversion. */
15685 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15687 NEON_ENCODE (IMMED
, inst
);
15688 if (flavour
!= neon_cvt_flavour_invalid
)
15689 inst
.instruction
|= enctab
[flavour
];
15690 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15691 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15694 inst
.instruction
|= neon_quad (rs
) << 6;
15695 inst
.instruction
|= 1 << 21;
15696 if (flavour
< neon_cvt_flavour_s16_f16
)
15698 inst
.instruction
|= 1 << 21;
15699 immbits
= 32 - inst
.operands
[2].imm
;
15700 inst
.instruction
|= immbits
<< 16;
15704 inst
.instruction
|= 3 << 20;
15705 immbits
= 16 - inst
.operands
[2].imm
;
15706 inst
.instruction
|= immbits
<< 16;
15707 inst
.instruction
&= ~(1 << 9);
15710 neon_dp_fixup (&inst
);
15716 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15718 NEON_ENCODE (FLOAT
, inst
);
15719 set_it_insn_type (OUTSIDE_IT_INSN
);
15721 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15724 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15725 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15726 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15727 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15728 inst
.instruction
|= neon_quad (rs
) << 6;
15729 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15730 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15731 inst
.instruction
|= mode
<< 8;
15732 if (flavour
== neon_cvt_flavour_u16_f16
15733 || flavour
== neon_cvt_flavour_s16_f16
)
15734 /* Mask off the original size bits and reencode them. */
15735 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15738 inst
.instruction
|= 0xfc000000;
15740 inst
.instruction
|= 0xf0000000;
15746 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15747 0x100, 0x180, 0x0, 0x080};
15749 NEON_ENCODE (INTEGER
, inst
);
15751 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15754 if (flavour
!= neon_cvt_flavour_invalid
)
15755 inst
.instruction
|= enctab
[flavour
];
15757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15761 inst
.instruction
|= neon_quad (rs
) << 6;
15762 if (flavour
>= neon_cvt_flavour_s16_f16
15763 && flavour
<= neon_cvt_flavour_f16_u16
)
15764 /* Half precision. */
15765 inst
.instruction
|= 1 << 18;
15767 inst
.instruction
|= 2 << 18;
15769 neon_dp_fixup (&inst
);
15774 /* Half-precision conversions for Advanced SIMD -- neon. */
15779 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15781 as_bad (_("operand size must match register width"));
15786 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15788 as_bad (_("operand size must match register width"));
15793 inst
.instruction
= 0x3b60600;
15795 inst
.instruction
= 0x3b60700;
15797 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15799 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15800 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15801 neon_dp_fixup (&inst
);
15805 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15806 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15807 do_vfp_nsyn_cvt (rs
, flavour
);
15809 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15814 do_neon_cvtr (void)
15816 do_neon_cvt_1 (neon_cvt_mode_x
);
15822 do_neon_cvt_1 (neon_cvt_mode_z
);
15826 do_neon_cvta (void)
15828 do_neon_cvt_1 (neon_cvt_mode_a
);
15832 do_neon_cvtn (void)
15834 do_neon_cvt_1 (neon_cvt_mode_n
);
15838 do_neon_cvtp (void)
15840 do_neon_cvt_1 (neon_cvt_mode_p
);
15844 do_neon_cvtm (void)
15846 do_neon_cvt_1 (neon_cvt_mode_m
);
15850 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15853 mark_feature_used (&fpu_vfp_ext_armv8
);
15855 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15856 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15857 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15858 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15859 inst
.instruction
|= to
? 0x10000 : 0;
15860 inst
.instruction
|= t
? 0x80 : 0;
15861 inst
.instruction
|= is_double
? 0x100 : 0;
15862 do_vfp_cond_or_thumb ();
15866 do_neon_cvttb_1 (bfd_boolean t
)
15868 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15869 NS_DF
, NS_DH
, NS_NULL
);
15873 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15876 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15878 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15881 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15883 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15885 /* The VCVTB and VCVTT instructions with D-register operands
15886 don't work for SP only targets. */
15887 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15891 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15893 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15895 /* The VCVTB and VCVTT instructions with D-register operands
15896 don't work for SP only targets. */
15897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15901 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15908 do_neon_cvtb (void)
15910 do_neon_cvttb_1 (FALSE
);
15915 do_neon_cvtt (void)
15917 do_neon_cvttb_1 (TRUE
);
15921 neon_move_immediate (void)
15923 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15924 struct neon_type_el et
= neon_check_type (2, rs
,
15925 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15926 unsigned immlo
, immhi
= 0, immbits
;
15927 int op
, cmode
, float_p
;
15929 constraint (et
.type
== NT_invtype
,
15930 _("operand size must be specified for immediate VMOV"));
15932 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15933 op
= (inst
.instruction
& (1 << 5)) != 0;
15935 immlo
= inst
.operands
[1].imm
;
15936 if (inst
.operands
[1].regisimm
)
15937 immhi
= inst
.operands
[1].reg
;
15939 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15940 _("immediate has bits set outside the operand size"));
15942 float_p
= inst
.operands
[1].immisfloat
;
15944 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15945 et
.size
, et
.type
)) == FAIL
)
15947 /* Invert relevant bits only. */
15948 neon_invert_size (&immlo
, &immhi
, et
.size
);
15949 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15950 with one or the other; those cases are caught by
15951 neon_cmode_for_move_imm. */
15953 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15954 &op
, et
.size
, et
.type
)) == FAIL
)
15956 first_error (_("immediate out of range"));
15961 inst
.instruction
&= ~(1 << 5);
15962 inst
.instruction
|= op
<< 5;
15964 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15965 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15966 inst
.instruction
|= neon_quad (rs
) << 6;
15967 inst
.instruction
|= cmode
<< 8;
15969 neon_write_immbits (immbits
);
15975 if (inst
.operands
[1].isreg
)
15977 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15979 NEON_ENCODE (INTEGER
, inst
);
15980 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15981 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15982 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15983 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15984 inst
.instruction
|= neon_quad (rs
) << 6;
15988 NEON_ENCODE (IMMED
, inst
);
15989 neon_move_immediate ();
15992 neon_dp_fixup (&inst
);
15995 /* Encode instructions of form:
15997 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15998 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16001 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16003 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16004 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16005 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16006 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16007 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16008 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16009 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16010 inst
.instruction
|= neon_logbits (size
) << 20;
16012 neon_dp_fixup (&inst
);
16016 do_neon_dyadic_long (void)
16018 /* FIXME: Type checking for lengthening op. */
16019 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16020 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16021 neon_mixed_length (et
, et
.size
);
16025 do_neon_abal (void)
16027 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16028 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16029 neon_mixed_length (et
, et
.size
);
16033 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16035 if (inst
.operands
[2].isscalar
)
16037 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16038 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16039 NEON_ENCODE (SCALAR
, inst
);
16040 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16044 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16045 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16046 NEON_ENCODE (INTEGER
, inst
);
16047 neon_mixed_length (et
, et
.size
);
16052 do_neon_mac_maybe_scalar_long (void)
16054 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16058 do_neon_dyadic_wide (void)
16060 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16061 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16062 neon_mixed_length (et
, et
.size
);
16066 do_neon_dyadic_narrow (void)
16068 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16069 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16070 /* Operand sign is unimportant, and the U bit is part of the opcode,
16071 so force the operand type to integer. */
16072 et
.type
= NT_integer
;
16073 neon_mixed_length (et
, et
.size
/ 2);
16077 do_neon_mul_sat_scalar_long (void)
16079 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16083 do_neon_vmull (void)
16085 if (inst
.operands
[2].isscalar
)
16086 do_neon_mac_maybe_scalar_long ();
16089 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16090 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16092 if (et
.type
== NT_poly
)
16093 NEON_ENCODE (POLY
, inst
);
16095 NEON_ENCODE (INTEGER
, inst
);
16097 /* For polynomial encoding the U bit must be zero, and the size must
16098 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16099 obviously, as 0b10). */
16102 /* Check we're on the correct architecture. */
16103 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16105 _("Instruction form not available on this architecture.");
16110 neon_mixed_length (et
, et
.size
);
16117 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16118 struct neon_type_el et
= neon_check_type (3, rs
,
16119 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16120 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16122 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16123 _("shift out of range"));
16124 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16125 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16126 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16127 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16128 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16129 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16130 inst
.instruction
|= neon_quad (rs
) << 6;
16131 inst
.instruction
|= imm
<< 8;
16133 neon_dp_fixup (&inst
);
16139 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16140 struct neon_type_el et
= neon_check_type (2, rs
,
16141 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16142 unsigned op
= (inst
.instruction
>> 7) & 3;
16143 /* N (width of reversed regions) is encoded as part of the bitmask. We
16144 extract it here to check the elements to be reversed are smaller.
16145 Otherwise we'd get a reserved instruction. */
16146 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16147 gas_assert (elsize
!= 0);
16148 constraint (et
.size
>= elsize
,
16149 _("elements must be smaller than reversal region"));
16150 neon_two_same (neon_quad (rs
), 1, et
.size
);
16156 if (inst
.operands
[1].isscalar
)
16158 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16159 struct neon_type_el et
= neon_check_type (2, rs
,
16160 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16161 unsigned sizebits
= et
.size
>> 3;
16162 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16163 int logsize
= neon_logbits (et
.size
);
16164 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16166 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16169 NEON_ENCODE (SCALAR
, inst
);
16170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16172 inst
.instruction
|= LOW4 (dm
);
16173 inst
.instruction
|= HI1 (dm
) << 5;
16174 inst
.instruction
|= neon_quad (rs
) << 6;
16175 inst
.instruction
|= x
<< 17;
16176 inst
.instruction
|= sizebits
<< 16;
16178 neon_dp_fixup (&inst
);
16182 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16183 struct neon_type_el et
= neon_check_type (2, rs
,
16184 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16185 /* Duplicate ARM register to lanes of vector. */
16186 NEON_ENCODE (ARMREG
, inst
);
16189 case 8: inst
.instruction
|= 0x400000; break;
16190 case 16: inst
.instruction
|= 0x000020; break;
16191 case 32: inst
.instruction
|= 0x000000; break;
16194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16195 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16196 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16197 inst
.instruction
|= neon_quad (rs
) << 21;
16198 /* The encoding for this instruction is identical for the ARM and Thumb
16199 variants, except for the condition field. */
16200 do_vfp_cond_or_thumb ();
16204 /* VMOV has particularly many variations. It can be one of:
16205 0. VMOV<c><q> <Qd>, <Qm>
16206 1. VMOV<c><q> <Dd>, <Dm>
16207 (Register operations, which are VORR with Rm = Rn.)
16208 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16209 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16211 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16212 (ARM register to scalar.)
16213 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16214 (Two ARM registers to vector.)
16215 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16216 (Scalar to ARM register.)
16217 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16218 (Vector to two ARM registers.)
16219 8. VMOV.F32 <Sd>, <Sm>
16220 9. VMOV.F64 <Dd>, <Dm>
16221 (VFP register moves.)
16222 10. VMOV.F32 <Sd>, #imm
16223 11. VMOV.F64 <Dd>, #imm
16224 (VFP float immediate load.)
16225 12. VMOV <Rd>, <Sm>
16226 (VFP single to ARM reg.)
16227 13. VMOV <Sd>, <Rm>
16228 (ARM reg to VFP single.)
16229 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16230 (Two ARM regs to two VFP singles.)
16231 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16232 (Two VFP singles to two ARM regs.)
16234 These cases can be disambiguated using neon_select_shape, except cases 1/9
16235 and 3/11 which depend on the operand type too.
16237 All the encoded bits are hardcoded by this function.
16239 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16240 Cases 5, 7 may be used with VFPv2 and above.
16242 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16243 can specify a type where it doesn't make sense to, and is ignored). */
16248 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16249 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16250 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16251 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16252 struct neon_type_el et
;
16253 const char *ldconst
= 0;
16257 case NS_DD
: /* case 1/9. */
16258 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16259 /* It is not an error here if no type is given. */
16261 if (et
.type
== NT_float
&& et
.size
== 64)
16263 do_vfp_nsyn_opcode ("fcpyd");
16266 /* fall through. */
16268 case NS_QQ
: /* case 0/1. */
16270 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16272 /* The architecture manual I have doesn't explicitly state which
16273 value the U bit should have for register->register moves, but
16274 the equivalent VORR instruction has U = 0, so do that. */
16275 inst
.instruction
= 0x0200110;
16276 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16277 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16278 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16279 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16280 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16281 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16282 inst
.instruction
|= neon_quad (rs
) << 6;
16284 neon_dp_fixup (&inst
);
16288 case NS_DI
: /* case 3/11. */
16289 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16291 if (et
.type
== NT_float
&& et
.size
== 64)
16293 /* case 11 (fconstd). */
16294 ldconst
= "fconstd";
16295 goto encode_fconstd
;
16297 /* fall through. */
16299 case NS_QI
: /* case 2/3. */
16300 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16302 inst
.instruction
= 0x0800010;
16303 neon_move_immediate ();
16304 neon_dp_fixup (&inst
);
16307 case NS_SR
: /* case 4. */
16309 unsigned bcdebits
= 0;
16311 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16312 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16314 /* .<size> is optional here, defaulting to .32. */
16315 if (inst
.vectype
.elems
== 0
16316 && inst
.operands
[0].vectype
.type
== NT_invtype
16317 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16319 inst
.vectype
.el
[0].type
= NT_untyped
;
16320 inst
.vectype
.el
[0].size
= 32;
16321 inst
.vectype
.elems
= 1;
16324 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16325 logsize
= neon_logbits (et
.size
);
16327 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16330 && et
.size
!= 32, _(BAD_FPU
));
16331 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16332 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16336 case 8: bcdebits
= 0x8; break;
16337 case 16: bcdebits
= 0x1; break;
16338 case 32: bcdebits
= 0x0; break;
16342 bcdebits
|= x
<< logsize
;
16344 inst
.instruction
= 0xe000b10;
16345 do_vfp_cond_or_thumb ();
16346 inst
.instruction
|= LOW4 (dn
) << 16;
16347 inst
.instruction
|= HI1 (dn
) << 7;
16348 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16349 inst
.instruction
|= (bcdebits
& 3) << 5;
16350 inst
.instruction
|= (bcdebits
>> 2) << 21;
16354 case NS_DRR
: /* case 5 (fmdrr). */
16355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16358 inst
.instruction
= 0xc400b10;
16359 do_vfp_cond_or_thumb ();
16360 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16361 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16362 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16363 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16366 case NS_RS
: /* case 6. */
16369 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16370 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16371 unsigned abcdebits
= 0;
16373 /* .<dt> is optional here, defaulting to .32. */
16374 if (inst
.vectype
.elems
== 0
16375 && inst
.operands
[0].vectype
.type
== NT_invtype
16376 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16378 inst
.vectype
.el
[0].type
= NT_untyped
;
16379 inst
.vectype
.el
[0].size
= 32;
16380 inst
.vectype
.elems
= 1;
16383 et
= neon_check_type (2, NS_NULL
,
16384 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16385 logsize
= neon_logbits (et
.size
);
16387 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16389 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16390 && et
.size
!= 32, _(BAD_FPU
));
16391 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16392 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16396 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16397 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16398 case 32: abcdebits
= 0x00; break;
16402 abcdebits
|= x
<< logsize
;
16403 inst
.instruction
= 0xe100b10;
16404 do_vfp_cond_or_thumb ();
16405 inst
.instruction
|= LOW4 (dn
) << 16;
16406 inst
.instruction
|= HI1 (dn
) << 7;
16407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16408 inst
.instruction
|= (abcdebits
& 3) << 5;
16409 inst
.instruction
|= (abcdebits
>> 2) << 21;
16413 case NS_RRD
: /* case 7 (fmrrd). */
16414 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16417 inst
.instruction
= 0xc500b10;
16418 do_vfp_cond_or_thumb ();
16419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16420 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16421 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16422 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16425 case NS_FF
: /* case 8 (fcpys). */
16426 do_vfp_nsyn_opcode ("fcpys");
16430 case NS_FI
: /* case 10 (fconsts). */
16431 ldconst
= "fconsts";
16433 if (is_quarter_float (inst
.operands
[1].imm
))
16435 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16436 do_vfp_nsyn_opcode (ldconst
);
16438 /* ARMv8.2 fp16 vmov.f16 instruction. */
16440 do_scalar_fp16_v82_encode ();
16443 first_error (_("immediate out of range"));
16447 case NS_RF
: /* case 12 (fmrs). */
16448 do_vfp_nsyn_opcode ("fmrs");
16449 /* ARMv8.2 fp16 vmov.f16 instruction. */
16451 do_scalar_fp16_v82_encode ();
16455 case NS_FR
: /* case 13 (fmsr). */
16456 do_vfp_nsyn_opcode ("fmsr");
16457 /* ARMv8.2 fp16 vmov.f16 instruction. */
16459 do_scalar_fp16_v82_encode ();
16462 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16463 (one of which is a list), but we have parsed four. Do some fiddling to
16464 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16466 case NS_RRFF
: /* case 14 (fmrrs). */
16467 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16468 _("VFP registers must be adjacent"));
16469 inst
.operands
[2].imm
= 2;
16470 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16471 do_vfp_nsyn_opcode ("fmrrs");
16474 case NS_FFRR
: /* case 15 (fmsrr). */
16475 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16476 _("VFP registers must be adjacent"));
16477 inst
.operands
[1] = inst
.operands
[2];
16478 inst
.operands
[2] = inst
.operands
[3];
16479 inst
.operands
[0].imm
= 2;
16480 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16481 do_vfp_nsyn_opcode ("fmsrr");
16485 /* neon_select_shape has determined that the instruction
16486 shape is wrong and has already set the error message. */
16495 do_neon_rshift_round_imm (void)
16497 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16498 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16499 int imm
= inst
.operands
[2].imm
;
16501 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16504 inst
.operands
[2].present
= 0;
16509 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16510 _("immediate out of range for shift"));
16511 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16516 do_neon_movhf (void)
16518 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16519 constraint (rs
!= NS_HH
, _("invalid suffix"));
16521 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16524 do_vfp_sp_monadic ();
16527 inst
.instruction
|= 0xf0000000;
16531 do_neon_movl (void)
16533 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16534 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16535 unsigned sizebits
= et
.size
>> 3;
16536 inst
.instruction
|= sizebits
<< 19;
16537 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16543 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16544 struct neon_type_el et
= neon_check_type (2, rs
,
16545 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16546 NEON_ENCODE (INTEGER
, inst
);
16547 neon_two_same (neon_quad (rs
), 1, et
.size
);
16551 do_neon_zip_uzp (void)
16553 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16554 struct neon_type_el et
= neon_check_type (2, rs
,
16555 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16556 if (rs
== NS_DD
&& et
.size
== 32)
16558 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16559 inst
.instruction
= N_MNEM_vtrn
;
16563 neon_two_same (neon_quad (rs
), 1, et
.size
);
16567 do_neon_sat_abs_neg (void)
16569 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16570 struct neon_type_el et
= neon_check_type (2, rs
,
16571 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16572 neon_two_same (neon_quad (rs
), 1, et
.size
);
16576 do_neon_pair_long (void)
16578 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16579 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16580 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16581 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16582 neon_two_same (neon_quad (rs
), 1, et
.size
);
16586 do_neon_recip_est (void)
16588 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16589 struct neon_type_el et
= neon_check_type (2, rs
,
16590 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16591 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16592 neon_two_same (neon_quad (rs
), 1, et
.size
);
16598 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16599 struct neon_type_el et
= neon_check_type (2, rs
,
16600 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16601 neon_two_same (neon_quad (rs
), 1, et
.size
);
16607 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16608 struct neon_type_el et
= neon_check_type (2, rs
,
16609 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16610 neon_two_same (neon_quad (rs
), 1, et
.size
);
16616 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16617 struct neon_type_el et
= neon_check_type (2, rs
,
16618 N_EQK
| N_INT
, N_8
| N_KEY
);
16619 neon_two_same (neon_quad (rs
), 1, et
.size
);
16625 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16626 neon_two_same (neon_quad (rs
), 1, -1);
16630 do_neon_tbl_tbx (void)
16632 unsigned listlenbits
;
16633 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16635 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16637 first_error (_("bad list length for table lookup"));
16641 listlenbits
= inst
.operands
[1].imm
- 1;
16642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16643 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16644 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16645 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16646 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16647 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16648 inst
.instruction
|= listlenbits
<< 8;
16650 neon_dp_fixup (&inst
);
16654 do_neon_ldm_stm (void)
16656 /* P, U and L bits are part of bitmask. */
16657 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16658 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16660 if (inst
.operands
[1].issingle
)
16662 do_vfp_nsyn_ldm_stm (is_dbmode
);
16666 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16667 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16669 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16670 _("register list must contain at least 1 and at most 16 "
16673 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16674 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16675 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16676 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16678 inst
.instruction
|= offsetbits
;
16680 do_vfp_cond_or_thumb ();
16684 do_neon_ldr_str (void)
16686 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16688 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16689 And is UNPREDICTABLE in thumb mode. */
16691 && inst
.operands
[1].reg
== REG_PC
16692 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16695 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16696 else if (warn_on_deprecated
)
16697 as_tsktsk (_("Use of PC here is deprecated"));
16700 if (inst
.operands
[0].issingle
)
16703 do_vfp_nsyn_opcode ("flds");
16705 do_vfp_nsyn_opcode ("fsts");
16707 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16708 if (inst
.vectype
.el
[0].size
== 16)
16709 do_scalar_fp16_v82_encode ();
16714 do_vfp_nsyn_opcode ("fldd");
16716 do_vfp_nsyn_opcode ("fstd");
16720 /* "interleave" version also handles non-interleaving register VLD1/VST1
16724 do_neon_ld_st_interleave (void)
16726 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16727 N_8
| N_16
| N_32
| N_64
);
16728 unsigned alignbits
= 0;
16730 /* The bits in this table go:
16731 0: register stride of one (0) or two (1)
16732 1,2: register list length, minus one (1, 2, 3, 4).
16733 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16734 We use -1 for invalid entries. */
16735 const int typetable
[] =
16737 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16738 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16739 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16740 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16744 if (et
.type
== NT_invtype
)
16747 if (inst
.operands
[1].immisalign
)
16748 switch (inst
.operands
[1].imm
>> 8)
16750 case 64: alignbits
= 1; break;
16752 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16753 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16754 goto bad_alignment
;
16758 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16759 goto bad_alignment
;
16764 first_error (_("bad alignment"));
16768 inst
.instruction
|= alignbits
<< 4;
16769 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16771 /* Bits [4:6] of the immediate in a list specifier encode register stride
16772 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16773 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16774 up the right value for "type" in a table based on this value and the given
16775 list style, then stick it back. */
16776 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16777 | (((inst
.instruction
>> 8) & 3) << 3);
16779 typebits
= typetable
[idx
];
16781 constraint (typebits
== -1, _("bad list type for instruction"));
16782 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16783 _("bad element type for instruction"));
16785 inst
.instruction
&= ~0xf00;
16786 inst
.instruction
|= typebits
<< 8;
16789 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16790 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16791 otherwise. The variable arguments are a list of pairs of legal (size, align)
16792 values, terminated with -1. */
16795 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16798 int result
= FAIL
, thissize
, thisalign
;
16800 if (!inst
.operands
[1].immisalign
)
16806 va_start (ap
, do_alignment
);
16810 thissize
= va_arg (ap
, int);
16811 if (thissize
== -1)
16813 thisalign
= va_arg (ap
, int);
16815 if (size
== thissize
&& align
== thisalign
)
16818 while (result
!= SUCCESS
);
16822 if (result
== SUCCESS
)
16825 first_error (_("unsupported alignment for instruction"));
16831 do_neon_ld_st_lane (void)
16833 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16834 int align_good
, do_alignment
= 0;
16835 int logsize
= neon_logbits (et
.size
);
16836 int align
= inst
.operands
[1].imm
>> 8;
16837 int n
= (inst
.instruction
>> 8) & 3;
16838 int max_el
= 64 / et
.size
;
16840 if (et
.type
== NT_invtype
)
16843 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16844 _("bad list length"));
16845 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16846 _("scalar index out of range"));
16847 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16849 _("stride of 2 unavailable when element size is 8"));
16853 case 0: /* VLD1 / VST1. */
16854 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16856 if (align_good
== FAIL
)
16860 unsigned alignbits
= 0;
16863 case 16: alignbits
= 0x1; break;
16864 case 32: alignbits
= 0x3; break;
16867 inst
.instruction
|= alignbits
<< 4;
16871 case 1: /* VLD2 / VST2. */
16872 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16873 16, 32, 32, 64, -1);
16874 if (align_good
== FAIL
)
16877 inst
.instruction
|= 1 << 4;
16880 case 2: /* VLD3 / VST3. */
16881 constraint (inst
.operands
[1].immisalign
,
16882 _("can't use alignment with this instruction"));
16885 case 3: /* VLD4 / VST4. */
16886 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16887 16, 64, 32, 64, 32, 128, -1);
16888 if (align_good
== FAIL
)
16892 unsigned alignbits
= 0;
16895 case 8: alignbits
= 0x1; break;
16896 case 16: alignbits
= 0x1; break;
16897 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16900 inst
.instruction
|= alignbits
<< 4;
16907 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16908 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16909 inst
.instruction
|= 1 << (4 + logsize
);
16911 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16912 inst
.instruction
|= logsize
<< 10;
16915 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16918 do_neon_ld_dup (void)
16920 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16921 int align_good
, do_alignment
= 0;
16923 if (et
.type
== NT_invtype
)
16926 switch ((inst
.instruction
>> 8) & 3)
16928 case 0: /* VLD1. */
16929 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16930 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16931 &do_alignment
, 16, 16, 32, 32, -1);
16932 if (align_good
== FAIL
)
16934 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16937 case 2: inst
.instruction
|= 1 << 5; break;
16938 default: first_error (_("bad list length")); return;
16940 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16943 case 1: /* VLD2. */
16944 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16945 &do_alignment
, 8, 16, 16, 32, 32, 64,
16947 if (align_good
== FAIL
)
16949 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16950 _("bad list length"));
16951 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16952 inst
.instruction
|= 1 << 5;
16953 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16956 case 2: /* VLD3. */
16957 constraint (inst
.operands
[1].immisalign
,
16958 _("can't use alignment with this instruction"));
16959 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16960 _("bad list length"));
16961 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16962 inst
.instruction
|= 1 << 5;
16963 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16966 case 3: /* VLD4. */
16968 int align
= inst
.operands
[1].imm
>> 8;
16969 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16970 16, 64, 32, 64, 32, 128, -1);
16971 if (align_good
== FAIL
)
16973 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16974 _("bad list length"));
16975 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16976 inst
.instruction
|= 1 << 5;
16977 if (et
.size
== 32 && align
== 128)
16978 inst
.instruction
|= 0x3 << 6;
16980 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16987 inst
.instruction
|= do_alignment
<< 4;
16990 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16991 apart from bits [11:4]. */
16994 do_neon_ldx_stx (void)
16996 if (inst
.operands
[1].isreg
)
16997 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16999 switch (NEON_LANE (inst
.operands
[0].imm
))
17001 case NEON_INTERLEAVE_LANES
:
17002 NEON_ENCODE (INTERLV
, inst
);
17003 do_neon_ld_st_interleave ();
17006 case NEON_ALL_LANES
:
17007 NEON_ENCODE (DUP
, inst
);
17008 if (inst
.instruction
== N_INV
)
17010 first_error ("only loads support such operands");
17017 NEON_ENCODE (LANE
, inst
);
17018 do_neon_ld_st_lane ();
17021 /* L bit comes from bit mask. */
17022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17026 if (inst
.operands
[1].postind
)
17028 int postreg
= inst
.operands
[1].imm
& 0xf;
17029 constraint (!inst
.operands
[1].immisreg
,
17030 _("post-index must be a register"));
17031 constraint (postreg
== 0xd || postreg
== 0xf,
17032 _("bad register for post-index"));
17033 inst
.instruction
|= postreg
;
17037 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17038 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17039 || inst
.reloc
.exp
.X_add_number
!= 0,
17042 if (inst
.operands
[1].writeback
)
17044 inst
.instruction
|= 0xd;
17047 inst
.instruction
|= 0xf;
17051 inst
.instruction
|= 0xf9000000;
17053 inst
.instruction
|= 0xf4000000;
17058 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17060 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17061 D register operands. */
17062 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17063 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17066 NEON_ENCODE (FPV8
, inst
);
17068 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17070 do_vfp_sp_dyadic ();
17072 /* ARMv8.2 fp16 instruction. */
17074 do_scalar_fp16_v82_encode ();
17077 do_vfp_dp_rd_rn_rm ();
17080 inst
.instruction
|= 0x100;
17082 inst
.instruction
|= 0xf0000000;
17088 set_it_insn_type (OUTSIDE_IT_INSN
);
17090 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17091 first_error (_("invalid instruction shape"));
17097 set_it_insn_type (OUTSIDE_IT_INSN
);
17099 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17102 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17105 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17109 do_vrint_1 (enum neon_cvt_mode mode
)
17111 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17112 struct neon_type_el et
;
17117 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17118 D register operands. */
17119 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17120 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17123 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17125 if (et
.type
!= NT_invtype
)
17127 /* VFP encodings. */
17128 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17129 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17130 set_it_insn_type (OUTSIDE_IT_INSN
);
17132 NEON_ENCODE (FPV8
, inst
);
17133 if (rs
== NS_FF
|| rs
== NS_HH
)
17134 do_vfp_sp_monadic ();
17136 do_vfp_dp_rd_rm ();
17140 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17141 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17142 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17143 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17144 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17145 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17146 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17150 inst
.instruction
|= (rs
== NS_DD
) << 8;
17151 do_vfp_cond_or_thumb ();
17153 /* ARMv8.2 fp16 vrint instruction. */
17155 do_scalar_fp16_v82_encode ();
17159 /* Neon encodings (or something broken...). */
17161 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17163 if (et
.type
== NT_invtype
)
17166 set_it_insn_type (OUTSIDE_IT_INSN
);
17167 NEON_ENCODE (FLOAT
, inst
);
17169 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17173 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17174 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17175 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17176 inst
.instruction
|= neon_quad (rs
) << 6;
17177 /* Mask off the original size bits and reencode them. */
17178 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17179 | neon_logbits (et
.size
) << 18);
17183 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17184 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17185 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17186 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17187 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17188 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17189 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17194 inst
.instruction
|= 0xfc000000;
17196 inst
.instruction
|= 0xf0000000;
17203 do_vrint_1 (neon_cvt_mode_x
);
17209 do_vrint_1 (neon_cvt_mode_z
);
17215 do_vrint_1 (neon_cvt_mode_r
);
17221 do_vrint_1 (neon_cvt_mode_a
);
17227 do_vrint_1 (neon_cvt_mode_n
);
17233 do_vrint_1 (neon_cvt_mode_p
);
17239 do_vrint_1 (neon_cvt_mode_m
);
17242 /* Crypto v1 instructions. */
17244 do_crypto_2op_1 (unsigned elttype
, int op
)
17246 set_it_insn_type (OUTSIDE_IT_INSN
);
17248 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17254 NEON_ENCODE (INTEGER
, inst
);
17255 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17256 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17257 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17258 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17260 inst
.instruction
|= op
<< 6;
17263 inst
.instruction
|= 0xfc000000;
17265 inst
.instruction
|= 0xf0000000;
17269 do_crypto_3op_1 (int u
, int op
)
17271 set_it_insn_type (OUTSIDE_IT_INSN
);
17273 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17274 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17279 NEON_ENCODE (INTEGER
, inst
);
17280 neon_three_same (1, u
, 8 << op
);
17286 do_crypto_2op_1 (N_8
, 0);
17292 do_crypto_2op_1 (N_8
, 1);
17298 do_crypto_2op_1 (N_8
, 2);
17304 do_crypto_2op_1 (N_8
, 3);
17310 do_crypto_3op_1 (0, 0);
17316 do_crypto_3op_1 (0, 1);
17322 do_crypto_3op_1 (0, 2);
17328 do_crypto_3op_1 (0, 3);
17334 do_crypto_3op_1 (1, 0);
17340 do_crypto_3op_1 (1, 1);
17344 do_sha256su1 (void)
17346 do_crypto_3op_1 (1, 2);
17352 do_crypto_2op_1 (N_32
, -1);
17358 do_crypto_2op_1 (N_32
, 0);
17362 do_sha256su0 (void)
17364 do_crypto_2op_1 (N_32
, 1);
17368 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17370 unsigned int Rd
= inst
.operands
[0].reg
;
17371 unsigned int Rn
= inst
.operands
[1].reg
;
17372 unsigned int Rm
= inst
.operands
[2].reg
;
17374 set_it_insn_type (OUTSIDE_IT_INSN
);
17375 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17376 inst
.instruction
|= LOW4 (Rn
) << 16;
17377 inst
.instruction
|= LOW4 (Rm
);
17378 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17379 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17381 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17382 as_warn (UNPRED_REG ("r15"));
17383 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17384 as_warn (UNPRED_REG ("r13"));
17424 /* Overall per-instruction processing. */
17426 /* We need to be able to fix up arbitrary expressions in some statements.
17427 This is so that we can handle symbols that are an arbitrary distance from
17428 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17429 which returns part of an address in a form which will be valid for
17430 a data instruction. We do this by pushing the expression into a symbol
17431 in the expr_section, and creating a fix for that. */
17434 fix_new_arm (fragS
* frag
,
17448 /* Create an absolute valued symbol, so we have something to
17449 refer to in the object file. Unfortunately for us, gas's
17450 generic expression parsing will already have folded out
17451 any use of .set foo/.type foo %function that may have
17452 been used to set type information of the target location,
17453 that's being specified symbolically. We have to presume
17454 the user knows what they are doing. */
17458 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17460 symbol
= symbol_find_or_make (name
);
17461 S_SET_SEGMENT (symbol
, absolute_section
);
17462 symbol_set_frag (symbol
, &zero_address_frag
);
17463 S_SET_VALUE (symbol
, exp
->X_add_number
);
17464 exp
->X_op
= O_symbol
;
17465 exp
->X_add_symbol
= symbol
;
17466 exp
->X_add_number
= 0;
17472 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17473 (enum bfd_reloc_code_real
) reloc
);
17477 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17478 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17482 /* Mark whether the fix is to a THUMB instruction, or an ARM
17484 new_fix
->tc_fix_data
= thumb_mode
;
17487 /* Create a frg for an instruction requiring relaxation. */
17489 output_relax_insn (void)
17495 /* The size of the instruction is unknown, so tie the debug info to the
17496 start of the instruction. */
17497 dwarf2_emit_insn (0);
17499 switch (inst
.reloc
.exp
.X_op
)
17502 sym
= inst
.reloc
.exp
.X_add_symbol
;
17503 offset
= inst
.reloc
.exp
.X_add_number
;
17507 offset
= inst
.reloc
.exp
.X_add_number
;
17510 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17514 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17515 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17516 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17519 /* Write a 32-bit thumb instruction to buf. */
17521 put_thumb32_insn (char * buf
, unsigned long insn
)
17523 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17524 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17528 output_inst (const char * str
)
17534 as_bad ("%s -- `%s'", inst
.error
, str
);
17539 output_relax_insn ();
17542 if (inst
.size
== 0)
17545 to
= frag_more (inst
.size
);
17546 /* PR 9814: Record the thumb mode into the current frag so that we know
17547 what type of NOP padding to use, if necessary. We override any previous
17548 setting so that if the mode has changed then the NOPS that we use will
17549 match the encoding of the last instruction in the frag. */
17550 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17552 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17554 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17555 put_thumb32_insn (to
, inst
.instruction
);
17557 else if (inst
.size
> INSN_SIZE
)
17559 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17560 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17561 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17564 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17566 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17567 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17568 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17571 dwarf2_emit_insn (inst
.size
);
17575 output_it_inst (int cond
, int mask
, char * to
)
17577 unsigned long instruction
= 0xbf00;
17580 instruction
|= mask
;
17581 instruction
|= cond
<< 4;
17585 to
= frag_more (2);
17587 dwarf2_emit_insn (2);
17591 md_number_to_chars (to
, instruction
, 2);
17596 /* Tag values used in struct asm_opcode's tag field. */
17599 OT_unconditional
, /* Instruction cannot be conditionalized.
17600 The ARM condition field is still 0xE. */
17601 OT_unconditionalF
, /* Instruction cannot be conditionalized
17602 and carries 0xF in its ARM condition field. */
17603 OT_csuffix
, /* Instruction takes a conditional suffix. */
17604 OT_csuffixF
, /* Some forms of the instruction take a conditional
17605 suffix, others place 0xF where the condition field
17607 OT_cinfix3
, /* Instruction takes a conditional infix,
17608 beginning at character index 3. (In
17609 unified mode, it becomes a suffix.) */
17610 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17611 tsts, cmps, cmns, and teqs. */
17612 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17613 character index 3, even in unified mode. Used for
17614 legacy instructions where suffix and infix forms
17615 may be ambiguous. */
17616 OT_csuf_or_in3
, /* Instruction takes either a conditional
17617 suffix or an infix at character index 3. */
17618 OT_odd_infix_unc
, /* This is the unconditional variant of an
17619 instruction that takes a conditional infix
17620 at an unusual position. In unified mode,
17621 this variant will accept a suffix. */
17622 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17623 are the conditional variants of instructions that
17624 take conditional infixes in unusual positions.
17625 The infix appears at character index
17626 (tag - OT_odd_infix_0). These are not accepted
17627 in unified mode. */
17630 /* Subroutine of md_assemble, responsible for looking up the primary
17631 opcode from the mnemonic the user wrote. STR points to the
17632 beginning of the mnemonic.
17634 This is not simply a hash table lookup, because of conditional
17635 variants. Most instructions have conditional variants, which are
17636 expressed with a _conditional affix_ to the mnemonic. If we were
17637 to encode each conditional variant as a literal string in the opcode
17638 table, it would have approximately 20,000 entries.
17640 Most mnemonics take this affix as a suffix, and in unified syntax,
17641 'most' is upgraded to 'all'. However, in the divided syntax, some
17642 instructions take the affix as an infix, notably the s-variants of
17643 the arithmetic instructions. Of those instructions, all but six
17644 have the infix appear after the third character of the mnemonic.
17646 Accordingly, the algorithm for looking up primary opcodes given
17649 1. Look up the identifier in the opcode table.
17650 If we find a match, go to step U.
17652 2. Look up the last two characters of the identifier in the
17653 conditions table. If we find a match, look up the first N-2
17654 characters of the identifier in the opcode table. If we
17655 find a match, go to step CE.
17657 3. Look up the fourth and fifth characters of the identifier in
17658 the conditions table. If we find a match, extract those
17659 characters from the identifier, and look up the remaining
17660 characters in the opcode table. If we find a match, go
17665 U. Examine the tag field of the opcode structure, in case this is
17666 one of the six instructions with its conditional infix in an
17667 unusual place. If it is, the tag tells us where to find the
17668 infix; look it up in the conditions table and set inst.cond
17669 accordingly. Otherwise, this is an unconditional instruction.
17670 Again set inst.cond accordingly. Return the opcode structure.
17672 CE. Examine the tag field to make sure this is an instruction that
17673 should receive a conditional suffix. If it is not, fail.
17674 Otherwise, set inst.cond from the suffix we already looked up,
17675 and return the opcode structure.
17677 CM. Examine the tag field to make sure this is an instruction that
17678 should receive a conditional infix after the third character.
17679 If it is not, fail. Otherwise, undo the edits to the current
17680 line of input and proceed as for case CE. */
17682 static const struct asm_opcode
*
17683 opcode_lookup (char **str
)
17687 const struct asm_opcode
*opcode
;
17688 const struct asm_cond
*cond
;
17691 /* Scan up to the end of the mnemonic, which must end in white space,
17692 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17693 for (base
= end
= *str
; *end
!= '\0'; end
++)
17694 if (*end
== ' ' || *end
== '.')
17700 /* Handle a possible width suffix and/or Neon type suffix. */
17705 /* The .w and .n suffixes are only valid if the unified syntax is in
17707 if (unified_syntax
&& end
[1] == 'w')
17709 else if (unified_syntax
&& end
[1] == 'n')
17714 inst
.vectype
.elems
= 0;
17716 *str
= end
+ offset
;
17718 if (end
[offset
] == '.')
17720 /* See if we have a Neon type suffix (possible in either unified or
17721 non-unified ARM syntax mode). */
17722 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17725 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17731 /* Look for unaffixed or special-case affixed mnemonic. */
17732 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17737 if (opcode
->tag
< OT_odd_infix_0
)
17739 inst
.cond
= COND_ALWAYS
;
17743 if (warn_on_deprecated
&& unified_syntax
)
17744 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17745 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17746 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17749 inst
.cond
= cond
->value
;
17753 /* Cannot have a conditional suffix on a mnemonic of less than two
17755 if (end
- base
< 3)
17758 /* Look for suffixed mnemonic. */
17760 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17761 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17763 if (opcode
&& cond
)
17766 switch (opcode
->tag
)
17768 case OT_cinfix3_legacy
:
17769 /* Ignore conditional suffixes matched on infix only mnemonics. */
17773 case OT_cinfix3_deprecated
:
17774 case OT_odd_infix_unc
:
17775 if (!unified_syntax
)
17777 /* Fall through. */
17781 case OT_csuf_or_in3
:
17782 inst
.cond
= cond
->value
;
17785 case OT_unconditional
:
17786 case OT_unconditionalF
:
17788 inst
.cond
= cond
->value
;
17791 /* Delayed diagnostic. */
17792 inst
.error
= BAD_COND
;
17793 inst
.cond
= COND_ALWAYS
;
17802 /* Cannot have a usual-position infix on a mnemonic of less than
17803 six characters (five would be a suffix). */
17804 if (end
- base
< 6)
17807 /* Look for infixed mnemonic in the usual position. */
17809 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17813 memcpy (save
, affix
, 2);
17814 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17815 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17817 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17818 memcpy (affix
, save
, 2);
17821 && (opcode
->tag
== OT_cinfix3
17822 || opcode
->tag
== OT_cinfix3_deprecated
17823 || opcode
->tag
== OT_csuf_or_in3
17824 || opcode
->tag
== OT_cinfix3_legacy
))
17827 if (warn_on_deprecated
&& unified_syntax
17828 && (opcode
->tag
== OT_cinfix3
17829 || opcode
->tag
== OT_cinfix3_deprecated
))
17830 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17832 inst
.cond
= cond
->value
;
17839 /* This function generates an initial IT instruction, leaving its block
17840 virtually open for the new instructions. Eventually,
17841 the mask will be updated by now_it_add_mask () each time
17842 a new instruction needs to be included in the IT block.
17843 Finally, the block is closed with close_automatic_it_block ().
17844 The block closure can be requested either from md_assemble (),
17845 a tencode (), or due to a label hook. */
17848 new_automatic_it_block (int cond
)
17850 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17851 now_it
.mask
= 0x18;
17853 now_it
.block_length
= 1;
17854 mapping_state (MAP_THUMB
);
17855 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17856 now_it
.warn_deprecated
= FALSE
;
17857 now_it
.insn_cond
= TRUE
;
17860 /* Close an automatic IT block.
17861 See comments in new_automatic_it_block (). */
17864 close_automatic_it_block (void)
17866 now_it
.mask
= 0x10;
17867 now_it
.block_length
= 0;
17870 /* Update the mask of the current automatically-generated IT
17871 instruction. See comments in new_automatic_it_block (). */
17874 now_it_add_mask (int cond
)
17876 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17877 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17878 | ((bitvalue) << (nbit)))
17879 const int resulting_bit
= (cond
& 1);
17881 now_it
.mask
&= 0xf;
17882 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17884 (5 - now_it
.block_length
));
17885 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17887 ((5 - now_it
.block_length
) - 1) );
17888 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17891 #undef SET_BIT_VALUE
17894 /* The IT blocks handling machinery is accessed through the these functions:
17895 it_fsm_pre_encode () from md_assemble ()
17896 set_it_insn_type () optional, from the tencode functions
17897 set_it_insn_type_last () ditto
17898 in_it_block () ditto
17899 it_fsm_post_encode () from md_assemble ()
17900 force_automatic_it_block_close () from label habdling functions
17903 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17904 initializing the IT insn type with a generic initial value depending
17905 on the inst.condition.
17906 2) During the tencode function, two things may happen:
17907 a) The tencode function overrides the IT insn type by
17908 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17909 b) The tencode function queries the IT block state by
17910 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17912 Both set_it_insn_type and in_it_block run the internal FSM state
17913 handling function (handle_it_state), because: a) setting the IT insn
17914 type may incur in an invalid state (exiting the function),
17915 and b) querying the state requires the FSM to be updated.
17916 Specifically we want to avoid creating an IT block for conditional
17917 branches, so it_fsm_pre_encode is actually a guess and we can't
17918 determine whether an IT block is required until the tencode () routine
17919 has decided what type of instruction this actually it.
17920 Because of this, if set_it_insn_type and in_it_block have to be used,
17921 set_it_insn_type has to be called first.
17923 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17924 determines the insn IT type depending on the inst.cond code.
17925 When a tencode () routine encodes an instruction that can be
17926 either outside an IT block, or, in the case of being inside, has to be
17927 the last one, set_it_insn_type_last () will determine the proper
17928 IT instruction type based on the inst.cond code. Otherwise,
17929 set_it_insn_type can be called for overriding that logic or
17930 for covering other cases.
17932 Calling handle_it_state () may not transition the IT block state to
17933 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17934 still queried. Instead, if the FSM determines that the state should
17935 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17936 after the tencode () function: that's what it_fsm_post_encode () does.
17938 Since in_it_block () calls the state handling function to get an
17939 updated state, an error may occur (due to invalid insns combination).
17940 In that case, inst.error is set.
17941 Therefore, inst.error has to be checked after the execution of
17942 the tencode () routine.
17944 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17945 any pending state change (if any) that didn't take place in
17946 handle_it_state () as explained above. */
17949 it_fsm_pre_encode (void)
17951 if (inst
.cond
!= COND_ALWAYS
)
17952 inst
.it_insn_type
= INSIDE_IT_INSN
;
17954 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17956 now_it
.state_handled
= 0;
17959 /* IT state FSM handling function. */
17962 handle_it_state (void)
17964 now_it
.state_handled
= 1;
17965 now_it
.insn_cond
= FALSE
;
17967 switch (now_it
.state
)
17969 case OUTSIDE_IT_BLOCK
:
17970 switch (inst
.it_insn_type
)
17972 case OUTSIDE_IT_INSN
:
17975 case INSIDE_IT_INSN
:
17976 case INSIDE_IT_LAST_INSN
:
17977 if (thumb_mode
== 0)
17980 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17981 as_tsktsk (_("Warning: conditional outside an IT block"\
17986 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17987 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17989 /* Automatically generate the IT instruction. */
17990 new_automatic_it_block (inst
.cond
);
17991 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17992 close_automatic_it_block ();
17996 inst
.error
= BAD_OUT_IT
;
18002 case IF_INSIDE_IT_LAST_INSN
:
18003 case NEUTRAL_IT_INSN
:
18007 now_it
.state
= MANUAL_IT_BLOCK
;
18008 now_it
.block_length
= 0;
18013 case AUTOMATIC_IT_BLOCK
:
18014 /* Three things may happen now:
18015 a) We should increment current it block size;
18016 b) We should close current it block (closing insn or 4 insns);
18017 c) We should close current it block and start a new one (due
18018 to incompatible conditions or
18019 4 insns-length block reached). */
18021 switch (inst
.it_insn_type
)
18023 case OUTSIDE_IT_INSN
:
18024 /* The closure of the block shall happen immediatelly,
18025 so any in_it_block () call reports the block as closed. */
18026 force_automatic_it_block_close ();
18029 case INSIDE_IT_INSN
:
18030 case INSIDE_IT_LAST_INSN
:
18031 case IF_INSIDE_IT_LAST_INSN
:
18032 now_it
.block_length
++;
18034 if (now_it
.block_length
> 4
18035 || !now_it_compatible (inst
.cond
))
18037 force_automatic_it_block_close ();
18038 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18039 new_automatic_it_block (inst
.cond
);
18043 now_it
.insn_cond
= TRUE
;
18044 now_it_add_mask (inst
.cond
);
18047 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18048 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18049 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18050 close_automatic_it_block ();
18053 case NEUTRAL_IT_INSN
:
18054 now_it
.block_length
++;
18055 now_it
.insn_cond
= TRUE
;
18057 if (now_it
.block_length
> 4)
18058 force_automatic_it_block_close ();
18060 now_it_add_mask (now_it
.cc
& 1);
18064 close_automatic_it_block ();
18065 now_it
.state
= MANUAL_IT_BLOCK
;
18070 case MANUAL_IT_BLOCK
:
18072 /* Check conditional suffixes. */
18073 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18076 now_it
.mask
&= 0x1f;
18077 is_last
= (now_it
.mask
== 0x10);
18078 now_it
.insn_cond
= TRUE
;
18080 switch (inst
.it_insn_type
)
18082 case OUTSIDE_IT_INSN
:
18083 inst
.error
= BAD_NOT_IT
;
18086 case INSIDE_IT_INSN
:
18087 if (cond
!= inst
.cond
)
18089 inst
.error
= BAD_IT_COND
;
18094 case INSIDE_IT_LAST_INSN
:
18095 case IF_INSIDE_IT_LAST_INSN
:
18096 if (cond
!= inst
.cond
)
18098 inst
.error
= BAD_IT_COND
;
18103 inst
.error
= BAD_BRANCH
;
18108 case NEUTRAL_IT_INSN
:
18109 /* The BKPT instruction is unconditional even in an IT block. */
18113 inst
.error
= BAD_IT_IT
;
18123 struct depr_insn_mask
18125 unsigned long pattern
;
18126 unsigned long mask
;
18127 const char* description
;
18130 /* List of 16-bit instruction patterns deprecated in an IT block in
18132 static const struct depr_insn_mask depr_it_insns
[] = {
18133 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18134 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18135 { 0xa000, 0xb800, N_("ADR") },
18136 { 0x4800, 0xf800, N_("Literal loads") },
18137 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18138 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18139 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18140 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18141 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18146 it_fsm_post_encode (void)
18150 if (!now_it
.state_handled
)
18151 handle_it_state ();
18153 if (now_it
.insn_cond
18154 && !now_it
.warn_deprecated
18155 && warn_on_deprecated
18156 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18158 if (inst
.instruction
>= 0x10000)
18160 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18161 "deprecated in ARMv8"));
18162 now_it
.warn_deprecated
= TRUE
;
18166 const struct depr_insn_mask
*p
= depr_it_insns
;
18168 while (p
->mask
!= 0)
18170 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18172 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18173 "of the following class are deprecated in ARMv8: "
18174 "%s"), p
->description
);
18175 now_it
.warn_deprecated
= TRUE
;
18183 if (now_it
.block_length
> 1)
18185 as_tsktsk (_("IT blocks containing more than one conditional "
18186 "instruction are deprecated in ARMv8"));
18187 now_it
.warn_deprecated
= TRUE
;
18191 is_last
= (now_it
.mask
== 0x10);
18194 now_it
.state
= OUTSIDE_IT_BLOCK
;
18200 force_automatic_it_block_close (void)
18202 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18204 close_automatic_it_block ();
18205 now_it
.state
= OUTSIDE_IT_BLOCK
;
18213 if (!now_it
.state_handled
)
18214 handle_it_state ();
18216 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18219 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18220 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18221 here, hence the "known" in the function name. */
18224 known_t32_only_insn (const struct asm_opcode
*opcode
)
18226 /* Original Thumb-1 wide instruction. */
18227 if (opcode
->tencode
== do_t_blx
18228 || opcode
->tencode
== do_t_branch23
18229 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18230 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18233 /* Wide-only instruction added to ARMv8-M Baseline. */
18234 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18235 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18236 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18237 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18243 /* Whether wide instruction variant can be used if available for a valid OPCODE
18247 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18249 if (known_t32_only_insn (opcode
))
18252 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18253 of variant T3 of B.W is checked in do_t_branch. */
18254 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18255 && opcode
->tencode
== do_t_branch
)
18258 /* Wide instruction variants of all instructions with narrow *and* wide
18259 variants become available with ARMv6t2. Other opcodes are either
18260 narrow-only or wide-only and are thus available if OPCODE is valid. */
18261 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18264 /* OPCODE with narrow only instruction variant or wide variant not
18270 md_assemble (char *str
)
18273 const struct asm_opcode
* opcode
;
18275 /* Align the previous label if needed. */
18276 if (last_label_seen
!= NULL
)
18278 symbol_set_frag (last_label_seen
, frag_now
);
18279 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18280 S_SET_SEGMENT (last_label_seen
, now_seg
);
18283 memset (&inst
, '\0', sizeof (inst
));
18284 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18286 opcode
= opcode_lookup (&p
);
18289 /* It wasn't an instruction, but it might be a register alias of
18290 the form alias .req reg, or a Neon .dn/.qn directive. */
18291 if (! create_register_alias (str
, p
)
18292 && ! create_neon_reg_alias (str
, p
))
18293 as_bad (_("bad instruction `%s'"), str
);
18298 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18299 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18301 /* The value which unconditional instructions should have in place of the
18302 condition field. */
18303 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18307 arm_feature_set variant
;
18309 variant
= cpu_variant
;
18310 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18311 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18312 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18313 /* Check that this instruction is supported for this CPU. */
18314 if (!opcode
->tvariant
18315 || (thumb_mode
== 1
18316 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18318 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18321 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18322 && opcode
->tencode
!= do_t_branch
)
18324 as_bad (_("Thumb does not support conditional execution"));
18328 /* Two things are addressed here:
18329 1) Implicit require narrow instructions on Thumb-1.
18330 This avoids relaxation accidentally introducing Thumb-2
18332 2) Reject wide instructions in non Thumb-2 cores.
18334 Only instructions with narrow and wide variants need to be handled
18335 but selecting all non wide-only instructions is easier. */
18336 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18337 && !t32_insn_ok (variant
, opcode
))
18339 if (inst
.size_req
== 0)
18341 else if (inst
.size_req
== 4)
18343 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18344 as_bad (_("selected processor does not support 32bit wide "
18345 "variant of instruction `%s'"), str
);
18347 as_bad (_("selected processor does not support `%s' in "
18348 "Thumb-2 mode"), str
);
18353 inst
.instruction
= opcode
->tvalue
;
18355 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18357 /* Prepare the it_insn_type for those encodings that don't set
18359 it_fsm_pre_encode ();
18361 opcode
->tencode ();
18363 it_fsm_post_encode ();
18366 if (!(inst
.error
|| inst
.relax
))
18368 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18369 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18370 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18372 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18377 /* Something has gone badly wrong if we try to relax a fixed size
18379 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18381 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18382 *opcode
->tvariant
);
18383 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18384 set those bits when Thumb-2 32-bit instructions are seen. The impact
18385 of relaxable instructions will be considered later after we finish all
18387 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18388 variant
= arm_arch_none
;
18390 variant
= cpu_variant
;
18391 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18392 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18395 check_neon_suffixes
;
18399 mapping_state (MAP_THUMB
);
18402 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18406 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18407 is_bx
= (opcode
->aencode
== do_bx
);
18409 /* Check that this instruction is supported for this CPU. */
18410 if (!(is_bx
&& fix_v4bx
)
18411 && !(opcode
->avariant
&&
18412 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18414 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18419 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18423 inst
.instruction
= opcode
->avalue
;
18424 if (opcode
->tag
== OT_unconditionalF
)
18425 inst
.instruction
|= 0xFU
<< 28;
18427 inst
.instruction
|= inst
.cond
<< 28;
18428 inst
.size
= INSN_SIZE
;
18429 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18431 it_fsm_pre_encode ();
18432 opcode
->aencode ();
18433 it_fsm_post_encode ();
18435 /* Arm mode bx is marked as both v4T and v5 because it's still required
18436 on a hypothetical non-thumb v5 core. */
18438 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18440 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18441 *opcode
->avariant
);
18443 check_neon_suffixes
;
18447 mapping_state (MAP_ARM
);
18452 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18460 check_it_blocks_finished (void)
18465 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18466 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18467 == MANUAL_IT_BLOCK
)
18469 as_warn (_("section '%s' finished with an open IT block."),
18473 if (now_it
.state
== MANUAL_IT_BLOCK
)
18474 as_warn (_("file finished with an open IT block."));
18478 /* Various frobbings of labels and their addresses. */
18481 arm_start_line_hook (void)
18483 last_label_seen
= NULL
;
18487 arm_frob_label (symbolS
* sym
)
18489 last_label_seen
= sym
;
18491 ARM_SET_THUMB (sym
, thumb_mode
);
18493 #if defined OBJ_COFF || defined OBJ_ELF
18494 ARM_SET_INTERWORK (sym
, support_interwork
);
18497 force_automatic_it_block_close ();
18499 /* Note - do not allow local symbols (.Lxxx) to be labelled
18500 as Thumb functions. This is because these labels, whilst
18501 they exist inside Thumb code, are not the entry points for
18502 possible ARM->Thumb calls. Also, these labels can be used
18503 as part of a computed goto or switch statement. eg gcc
18504 can generate code that looks like this:
18506 ldr r2, [pc, .Laaa]
18516 The first instruction loads the address of the jump table.
18517 The second instruction converts a table index into a byte offset.
18518 The third instruction gets the jump address out of the table.
18519 The fourth instruction performs the jump.
18521 If the address stored at .Laaa is that of a symbol which has the
18522 Thumb_Func bit set, then the linker will arrange for this address
18523 to have the bottom bit set, which in turn would mean that the
18524 address computation performed by the third instruction would end
18525 up with the bottom bit set. Since the ARM is capable of unaligned
18526 word loads, the instruction would then load the incorrect address
18527 out of the jump table, and chaos would ensue. */
18528 if (label_is_thumb_function_name
18529 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18530 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18532 /* When the address of a Thumb function is taken the bottom
18533 bit of that address should be set. This will allow
18534 interworking between Arm and Thumb functions to work
18537 THUMB_SET_FUNC (sym
, 1);
18539 label_is_thumb_function_name
= FALSE
;
18542 dwarf2_emit_label (sym
);
18546 arm_data_in_code (void)
18548 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18550 *input_line_pointer
= '/';
18551 input_line_pointer
+= 5;
18552 *input_line_pointer
= 0;
18560 arm_canonicalize_symbol_name (char * name
)
18564 if (thumb_mode
&& (len
= strlen (name
)) > 5
18565 && streq (name
+ len
- 5, "/data"))
18566 *(name
+ len
- 5) = 0;
18571 /* Table of all register names defined by default. The user can
18572 define additional names with .req. Note that all register names
18573 should appear in both upper and lowercase variants. Some registers
18574 also have mixed-case names. */
18576 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18577 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18578 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18579 #define REGSET(p,t) \
18580 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18581 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18582 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18583 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18584 #define REGSETH(p,t) \
18585 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18586 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18587 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18588 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18589 #define REGSET2(p,t) \
18590 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18591 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18592 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18593 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18594 #define SPLRBANK(base,bank,t) \
18595 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18596 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18597 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18598 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18599 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18600 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18602 static const struct reg_entry reg_names
[] =
18604 /* ARM integer registers. */
18605 REGSET(r
, RN
), REGSET(R
, RN
),
18607 /* ATPCS synonyms. */
18608 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18609 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18610 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18612 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18613 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18614 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18616 /* Well-known aliases. */
18617 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18618 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18620 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18621 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18623 /* Coprocessor numbers. */
18624 REGSET(p
, CP
), REGSET(P
, CP
),
18626 /* Coprocessor register numbers. The "cr" variants are for backward
18628 REGSET(c
, CN
), REGSET(C
, CN
),
18629 REGSET(cr
, CN
), REGSET(CR
, CN
),
18631 /* ARM banked registers. */
18632 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18633 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18634 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18635 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18636 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18637 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18638 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18640 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18641 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18642 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18643 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18644 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18645 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18646 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18647 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18649 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18650 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18651 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18652 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18653 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18654 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18655 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18656 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18657 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18659 /* FPA registers. */
18660 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18661 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18663 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18664 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18666 /* VFP SP registers. */
18667 REGSET(s
,VFS
), REGSET(S
,VFS
),
18668 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18670 /* VFP DP Registers. */
18671 REGSET(d
,VFD
), REGSET(D
,VFD
),
18672 /* Extra Neon DP registers. */
18673 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18675 /* Neon QP registers. */
18676 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18678 /* VFP control registers. */
18679 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18680 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18681 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18682 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18683 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18684 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18686 /* Maverick DSP coprocessor registers. */
18687 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18688 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18690 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18691 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18692 REGDEF(dspsc
,0,DSPSC
),
18694 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18695 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18696 REGDEF(DSPSC
,0,DSPSC
),
18698 /* iWMMXt data registers - p0, c0-15. */
18699 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18701 /* iWMMXt control registers - p1, c0-3. */
18702 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18703 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18704 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18705 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18707 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18708 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18709 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18710 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18711 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18713 /* XScale accumulator registers. */
18714 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18720 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18721 within psr_required_here. */
18722 static const struct asm_psr psrs
[] =
18724 /* Backward compatibility notation. Note that "all" is no longer
18725 truly all possible PSR bits. */
18726 {"all", PSR_c
| PSR_f
},
18730 /* Individual flags. */
18736 /* Combinations of flags. */
18737 {"fs", PSR_f
| PSR_s
},
18738 {"fx", PSR_f
| PSR_x
},
18739 {"fc", PSR_f
| PSR_c
},
18740 {"sf", PSR_s
| PSR_f
},
18741 {"sx", PSR_s
| PSR_x
},
18742 {"sc", PSR_s
| PSR_c
},
18743 {"xf", PSR_x
| PSR_f
},
18744 {"xs", PSR_x
| PSR_s
},
18745 {"xc", PSR_x
| PSR_c
},
18746 {"cf", PSR_c
| PSR_f
},
18747 {"cs", PSR_c
| PSR_s
},
18748 {"cx", PSR_c
| PSR_x
},
18749 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18750 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18751 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18752 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18753 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18754 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18755 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18756 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18757 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18758 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18759 {"scf", PSR_s
| PSR_c
| PSR_f
},
18760 {"scx", PSR_s
| PSR_c
| PSR_x
},
18761 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18762 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18763 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18764 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18765 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18766 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18767 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18768 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18769 {"csf", PSR_c
| PSR_s
| PSR_f
},
18770 {"csx", PSR_c
| PSR_s
| PSR_x
},
18771 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18772 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18773 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18774 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18775 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18776 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18777 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18778 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18779 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18780 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18781 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18782 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18783 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18784 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18785 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18786 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18787 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18788 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18789 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18790 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18791 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18792 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18793 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18794 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18795 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18796 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18799 /* Table of V7M psr names. */
18800 static const struct asm_psr v7m_psrs
[] =
18802 {"apsr", 0x0 }, {"APSR", 0x0 },
18803 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18804 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18805 {"psr", 0x3 }, {"PSR", 0x3 },
18806 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18807 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18808 {"epsr", 0x6 }, {"EPSR", 0x6 },
18809 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18810 {"msp", 0x8 }, {"MSP", 0x8 },
18811 {"psp", 0x9 }, {"PSP", 0x9 },
18812 {"msplim", 0xa }, {"MSPLIM", 0xa },
18813 {"psplim", 0xb }, {"PSPLIM", 0xb },
18814 {"primask", 0x10}, {"PRIMASK", 0x10},
18815 {"basepri", 0x11}, {"BASEPRI", 0x11},
18816 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18817 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18818 {"control", 0x14}, {"CONTROL", 0x14},
18819 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18820 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18821 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18822 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18823 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18824 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18825 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18826 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18827 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18830 /* Table of all shift-in-operand names. */
18831 static const struct asm_shift_name shift_names
[] =
18833 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18834 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18835 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18836 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18837 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18838 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18841 /* Table of all explicit relocation names. */
18843 static struct reloc_entry reloc_names
[] =
18845 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18846 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18847 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18848 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18849 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18850 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18851 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18852 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18853 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18854 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18855 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18856 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18857 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18858 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18859 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18860 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18861 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18862 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18866 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18867 static const struct asm_cond conds
[] =
18871 {"cs", 0x2}, {"hs", 0x2},
18872 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18886 #define UL_BARRIER(L,U,CODE,FEAT) \
18887 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18888 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18890 static struct asm_barrier_opt barrier_opt_names
[] =
18892 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18893 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18894 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18895 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18896 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18897 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18898 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18899 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18900 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18901 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18902 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18903 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18904 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18905 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18906 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18907 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18912 /* Table of ARM-format instructions. */
18914 /* Macros for gluing together operand strings. N.B. In all cases
18915 other than OPS0, the trailing OP_stop comes from default
18916 zero-initialization of the unspecified elements of the array. */
18917 #define OPS0() { OP_stop, }
18918 #define OPS1(a) { OP_##a, }
18919 #define OPS2(a,b) { OP_##a,OP_##b, }
18920 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18921 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18922 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18923 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18925 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18926 This is useful when mixing operands for ARM and THUMB, i.e. using the
18927 MIX_ARM_THUMB_OPERANDS macro.
18928 In order to use these macros, prefix the number of operands with _
18930 #define OPS_1(a) { a, }
18931 #define OPS_2(a,b) { a,b, }
18932 #define OPS_3(a,b,c) { a,b,c, }
18933 #define OPS_4(a,b,c,d) { a,b,c,d, }
18934 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18935 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18937 /* These macros abstract out the exact format of the mnemonic table and
18938 save some repeated characters. */
18940 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18941 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18942 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18943 THUMB_VARIANT, do_##ae, do_##te }
18945 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18946 a T_MNEM_xyz enumerator. */
18947 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18948 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18949 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18950 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18952 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18953 infix after the third character. */
18954 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18955 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18956 THUMB_VARIANT, do_##ae, do_##te }
18957 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18958 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18959 THUMB_VARIANT, do_##ae, do_##te }
18960 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18961 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18962 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18963 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18964 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18965 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18966 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18967 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18969 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18970 field is still 0xE. Many of the Thumb variants can be executed
18971 conditionally, so this is checked separately. */
18972 #define TUE(mnem, op, top, nops, ops, ae, te) \
18973 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18974 THUMB_VARIANT, do_##ae, do_##te }
18976 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18977 Used by mnemonics that have very minimal differences in the encoding for
18978 ARM and Thumb variants and can be handled in a common function. */
18979 #define TUEc(mnem, op, top, nops, ops, en) \
18980 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18981 THUMB_VARIANT, do_##en, do_##en }
18983 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18984 condition code field. */
18985 #define TUF(mnem, op, top, nops, ops, ae, te) \
18986 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18987 THUMB_VARIANT, do_##ae, do_##te }
18989 /* ARM-only variants of all the above. */
18990 #define CE(mnem, op, nops, ops, ae) \
18991 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18993 #define C3(mnem, op, nops, ops, ae) \
18994 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18996 /* Legacy mnemonics that always have conditional infix after the third
18998 #define CL(mnem, op, nops, ops, ae) \
18999 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19000 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19002 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19003 #define cCE(mnem, op, nops, ops, ae) \
19004 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19006 /* Legacy coprocessor instructions where conditional infix and conditional
19007 suffix are ambiguous. For consistency this includes all FPA instructions,
19008 not just the potentially ambiguous ones. */
19009 #define cCL(mnem, op, nops, ops, ae) \
19010 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19011 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19013 /* Coprocessor, takes either a suffix or a position-3 infix
19014 (for an FPA corner case). */
19015 #define C3E(mnem, op, nops, ops, ae) \
19016 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19017 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19019 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19020 { m1 #m2 m3, OPS##nops ops, \
19021 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19022 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19024 #define CM(m1, m2, op, nops, ops, ae) \
19025 xCM_ (m1, , m2, op, nops, ops, ae), \
19026 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19027 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19028 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19029 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19030 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19031 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19032 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19033 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19034 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19035 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19036 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19037 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19038 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19039 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19040 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19041 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19042 xCM_ (m1, le, m2, op, nops, ops, ae), \
19043 xCM_ (m1, al, m2, op, nops, ops, ae)
19045 #define UE(mnem, op, nops, ops, ae) \
19046 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19048 #define UF(mnem, op, nops, ops, ae) \
19049 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19051 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19052 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19053 use the same encoding function for each. */
19054 #define NUF(mnem, op, nops, ops, enc) \
19055 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19056 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19058 /* Neon data processing, version which indirects through neon_enc_tab for
19059 the various overloaded versions of opcodes. */
19060 #define nUF(mnem, op, nops, ops, enc) \
19061 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19062 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19064 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19066 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19067 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19068 THUMB_VARIANT, do_##enc, do_##enc }
19070 #define NCE(mnem, op, nops, ops, enc) \
19071 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19073 #define NCEF(mnem, op, nops, ops, enc) \
19074 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19076 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19077 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19078 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19079 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19081 #define nCE(mnem, op, nops, ops, enc) \
19082 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19084 #define nCEF(mnem, op, nops, ops, enc) \
19085 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19089 static const struct asm_opcode insns
[] =
19091 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19092 #define THUMB_VARIANT & arm_ext_v4t
19093 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19094 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19095 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19096 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19097 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19098 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19099 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19100 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19101 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19102 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19103 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19104 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19105 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19106 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19107 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19108 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19110 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19111 for setting PSR flag bits. They are obsolete in V6 and do not
19112 have Thumb equivalents. */
19113 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19114 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19115 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19116 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19117 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19118 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19119 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19120 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19121 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19123 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19124 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19125 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19126 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19128 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19129 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19130 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19132 OP_ADDRGLDR
),ldst
, t_ldst
),
19133 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19135 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19136 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19137 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19138 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19139 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19140 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19142 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19143 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19144 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19145 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19148 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19149 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19150 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19151 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19153 /* Thumb-compatibility pseudo ops. */
19154 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19155 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19156 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19157 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19158 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19159 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19160 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19161 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19162 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19163 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19164 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19165 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19167 /* These may simplify to neg. */
19168 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19169 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19171 #undef THUMB_VARIANT
19172 #define THUMB_VARIANT & arm_ext_v6
19174 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19176 /* V1 instructions with no Thumb analogue prior to V6T2. */
19177 #undef THUMB_VARIANT
19178 #define THUMB_VARIANT & arm_ext_v6t2
19180 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19181 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19182 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19184 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19185 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19186 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19187 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19189 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19190 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19192 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19193 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19195 /* V1 instructions with no Thumb analogue at all. */
19196 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19197 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19199 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19200 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19201 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19202 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19203 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19204 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19205 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19206 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19209 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19210 #undef THUMB_VARIANT
19211 #define THUMB_VARIANT & arm_ext_v4t
19213 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19214 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19216 #undef THUMB_VARIANT
19217 #define THUMB_VARIANT & arm_ext_v6t2
19219 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19220 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19222 /* Generic coprocessor instructions. */
19223 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19224 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19225 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19226 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19227 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19228 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19229 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19232 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19234 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19235 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19238 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19239 #undef THUMB_VARIANT
19240 #define THUMB_VARIANT & arm_ext_msr
19242 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19243 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19246 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19247 #undef THUMB_VARIANT
19248 #define THUMB_VARIANT & arm_ext_v6t2
19250 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19251 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19252 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19253 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19254 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19255 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19256 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19257 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19260 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19261 #undef THUMB_VARIANT
19262 #define THUMB_VARIANT & arm_ext_v4t
19264 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19265 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19266 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19267 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19268 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19269 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19272 #define ARM_VARIANT & arm_ext_v4t_5
19274 /* ARM Architecture 4T. */
19275 /* Note: bx (and blx) are required on V5, even if the processor does
19276 not support Thumb. */
19277 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19280 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19281 #undef THUMB_VARIANT
19282 #define THUMB_VARIANT & arm_ext_v5t
19284 /* Note: blx has 2 variants; the .value coded here is for
19285 BLX(2). Only this variant has conditional execution. */
19286 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19287 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19289 #undef THUMB_VARIANT
19290 #define THUMB_VARIANT & arm_ext_v6t2
19292 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19293 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19294 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19295 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19296 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19297 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19298 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19299 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19302 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19303 #undef THUMB_VARIANT
19304 #define THUMB_VARIANT & arm_ext_v5exp
19306 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19307 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19308 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19309 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19311 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19312 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19314 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19315 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19316 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19317 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19319 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19320 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19321 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19322 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19324 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19325 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19327 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19328 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19329 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19330 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19333 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19334 #undef THUMB_VARIANT
19335 #define THUMB_VARIANT & arm_ext_v6t2
19337 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19338 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19340 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19341 ADDRGLDRS
), ldrd
, t_ldstd
),
19343 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19344 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19347 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19349 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19352 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19353 #undef THUMB_VARIANT
19354 #define THUMB_VARIANT & arm_ext_v6
19356 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19357 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19358 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19359 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19360 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19361 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19362 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19363 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19364 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19365 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19367 #undef THUMB_VARIANT
19368 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19370 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19371 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19373 #undef THUMB_VARIANT
19374 #define THUMB_VARIANT & arm_ext_v6t2
19376 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19377 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19379 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19380 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19382 /* ARM V6 not included in V7M. */
19383 #undef THUMB_VARIANT
19384 #define THUMB_VARIANT & arm_ext_v6_notm
19385 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19386 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19387 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19388 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19389 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19390 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19391 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19392 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19393 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19394 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19395 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19396 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19397 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19398 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19399 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19400 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19401 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19402 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19403 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19405 /* ARM V6 not included in V7M (eg. integer SIMD). */
19406 #undef THUMB_VARIANT
19407 #define THUMB_VARIANT & arm_ext_v6_dsp
19408 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19409 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19410 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19411 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19412 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19413 /* Old name for QASX. */
19414 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19416 /* Old name for QSAX. */
19417 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19418 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19419 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19420 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19421 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19422 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19423 /* Old name for SASX. */
19424 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19425 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19426 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19427 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 /* Old name for SHASX. */
19429 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19430 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19431 /* Old name for SHSAX. */
19432 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19433 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19434 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19435 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19436 /* Old name for SSAX. */
19437 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19438 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19439 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19440 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19441 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19442 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19443 /* Old name for UASX. */
19444 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19445 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19446 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19447 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19448 /* Old name for UHASX. */
19449 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19450 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19451 /* Old name for UHSAX. */
19452 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19453 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19454 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19455 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19456 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19457 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19458 /* Old name for UQASX. */
19459 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19460 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19461 /* Old name for UQSAX. */
19462 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19463 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19464 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19465 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19466 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19467 /* Old name for USAX. */
19468 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19469 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19470 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19471 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19472 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19473 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19474 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19475 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19476 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19477 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19478 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19479 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19480 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19481 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19482 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19483 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19484 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19485 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19486 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19487 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19488 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19489 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19490 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19491 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19492 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19493 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19494 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19495 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19496 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19497 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19498 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19499 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19500 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19501 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19504 #define ARM_VARIANT & arm_ext_v6k
19505 #undef THUMB_VARIANT
19506 #define THUMB_VARIANT & arm_ext_v6k
19508 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19509 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19510 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19511 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19513 #undef THUMB_VARIANT
19514 #define THUMB_VARIANT & arm_ext_v6_notm
19515 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19517 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19518 RRnpcb
), strexd
, t_strexd
),
19520 #undef THUMB_VARIANT
19521 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19522 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19524 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19526 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19528 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19530 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19533 #define ARM_VARIANT & arm_ext_sec
19534 #undef THUMB_VARIANT
19535 #define THUMB_VARIANT & arm_ext_sec
19537 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19540 #define ARM_VARIANT & arm_ext_virt
19541 #undef THUMB_VARIANT
19542 #define THUMB_VARIANT & arm_ext_virt
19544 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19545 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19548 #define ARM_VARIANT & arm_ext_pan
19549 #undef THUMB_VARIANT
19550 #define THUMB_VARIANT & arm_ext_pan
19552 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19555 #define ARM_VARIANT & arm_ext_v6t2
19556 #undef THUMB_VARIANT
19557 #define THUMB_VARIANT & arm_ext_v6t2
19559 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19560 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19561 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19562 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19564 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19565 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19567 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19568 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19569 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19570 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19572 #undef THUMB_VARIANT
19573 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19574 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19575 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19577 /* Thumb-only instructions. */
19579 #define ARM_VARIANT NULL
19580 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19581 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19583 /* ARM does not really have an IT instruction, so always allow it.
19584 The opcode is copied from Thumb in order to allow warnings in
19585 -mimplicit-it=[never | arm] modes. */
19587 #define ARM_VARIANT & arm_ext_v1
19588 #undef THUMB_VARIANT
19589 #define THUMB_VARIANT & arm_ext_v6t2
19591 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19592 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19593 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19594 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19595 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19596 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19597 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19598 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19599 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19600 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19601 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19602 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19603 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19604 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19605 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19606 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19607 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19608 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19610 /* Thumb2 only instructions. */
19612 #define ARM_VARIANT NULL
19614 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19615 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19616 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19617 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19618 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19619 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19621 /* Hardware division instructions. */
19623 #define ARM_VARIANT & arm_ext_adiv
19624 #undef THUMB_VARIANT
19625 #define THUMB_VARIANT & arm_ext_div
19627 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19628 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19630 /* ARM V6M/V7 instructions. */
19632 #define ARM_VARIANT & arm_ext_barrier
19633 #undef THUMB_VARIANT
19634 #define THUMB_VARIANT & arm_ext_barrier
19636 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19637 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19638 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19640 /* ARM V7 instructions. */
19642 #define ARM_VARIANT & arm_ext_v7
19643 #undef THUMB_VARIANT
19644 #define THUMB_VARIANT & arm_ext_v7
19646 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19647 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19650 #define ARM_VARIANT & arm_ext_mp
19651 #undef THUMB_VARIANT
19652 #define THUMB_VARIANT & arm_ext_mp
19654 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19656 /* AArchv8 instructions. */
19658 #define ARM_VARIANT & arm_ext_v8
19660 /* Instructions shared between armv8-a and armv8-m. */
19661 #undef THUMB_VARIANT
19662 #define THUMB_VARIANT & arm_ext_atomics
19664 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19665 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19666 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19667 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19668 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19669 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19670 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19671 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19672 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19673 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19675 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19677 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19679 #undef THUMB_VARIANT
19680 #define THUMB_VARIANT & arm_ext_v8
19682 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19683 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19684 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19686 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19688 /* ARMv8 T32 only. */
19690 #define ARM_VARIANT NULL
19691 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19692 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19693 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19695 /* FP for ARMv8. */
19697 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19698 #undef THUMB_VARIANT
19699 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19701 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19702 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19703 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19704 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19705 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19706 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19707 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19708 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19709 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19710 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19711 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19712 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19713 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19714 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19715 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19716 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19717 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19719 /* Crypto v1 extensions. */
19721 #define ARM_VARIANT & fpu_crypto_ext_armv8
19722 #undef THUMB_VARIANT
19723 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19725 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19726 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19727 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19728 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19729 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19730 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19731 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19732 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19733 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19734 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19735 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19736 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19737 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19738 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19741 #define ARM_VARIANT & crc_ext_armv8
19742 #undef THUMB_VARIANT
19743 #define THUMB_VARIANT & crc_ext_armv8
19744 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19745 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19746 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19747 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19748 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19749 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19751 /* ARMv8.2 RAS extension. */
19753 #define ARM_VARIANT & arm_ext_ras
19754 #undef THUMB_VARIANT
19755 #define THUMB_VARIANT & arm_ext_ras
19756 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19759 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19760 #undef THUMB_VARIANT
19761 #define THUMB_VARIANT NULL
19763 cCE("wfs", e200110
, 1, (RR
), rd
),
19764 cCE("rfs", e300110
, 1, (RR
), rd
),
19765 cCE("wfc", e400110
, 1, (RR
), rd
),
19766 cCE("rfc", e500110
, 1, (RR
), rd
),
19768 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19769 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19770 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19771 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19773 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19774 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19775 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19776 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19778 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19958 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19971 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19984 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20104 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20108 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20121 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20123 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20127 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20130 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20134 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20136 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20140 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20153 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20156 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20157 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20158 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20160 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20161 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20162 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20163 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20164 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20165 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20166 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20167 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20168 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20169 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20170 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20171 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20173 /* The implementation of the FIX instruction is broken on some
20174 assemblers, in that it accepts a precision specifier as well as a
20175 rounding specifier, despite the fact that this is meaningless.
20176 To be more compatible, we accept it as well, though of course it
20177 does not set any bits. */
20178 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20179 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20180 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20181 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20182 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20183 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20184 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20185 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20186 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20187 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20188 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20189 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20190 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20192 /* Instructions that were new with the real FPA, call them V2. */
20194 #define ARM_VARIANT & fpu_fpa_ext_v2
20196 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20197 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20198 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20199 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20200 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20201 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20204 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20206 /* Moves and type conversions. */
20207 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20208 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20209 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20210 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20211 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20212 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20213 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20214 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20215 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20216 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20217 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20218 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20219 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20220 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20222 /* Memory operations. */
20223 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20224 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20225 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20226 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20227 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20228 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20229 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20230 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20231 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20232 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20233 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20234 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20235 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20236 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20237 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20238 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20239 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20240 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20242 /* Monadic operations. */
20243 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20244 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20245 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20247 /* Dyadic operations. */
20248 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20249 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20250 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20251 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20252 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20253 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20254 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20255 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20256 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20259 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20260 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20261 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20262 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20264 /* Double precision load/store are still present on single precision
20265 implementations. */
20266 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20267 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20268 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20269 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20270 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20271 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20272 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20273 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20274 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20275 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20278 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20280 /* Moves and type conversions. */
20281 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20282 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20283 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20284 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20285 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20286 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20287 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20288 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20289 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20290 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20291 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20292 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20293 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20295 /* Monadic operations. */
20296 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20297 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20298 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20300 /* Dyadic operations. */
20301 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20302 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20303 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20304 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20305 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20306 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20307 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20308 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20309 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20312 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20313 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20314 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20315 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20318 #define ARM_VARIANT & fpu_vfp_ext_v2
20320 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20321 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20322 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20323 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20325 /* Instructions which may belong to either the Neon or VFP instruction sets.
20326 Individual encoder functions perform additional architecture checks. */
20328 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20329 #undef THUMB_VARIANT
20330 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20332 /* These mnemonics are unique to VFP. */
20333 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20334 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20335 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20336 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20337 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20338 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20339 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20340 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20341 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20342 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20344 /* Mnemonics shared by Neon and VFP. */
20345 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20346 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20347 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20349 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20350 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20352 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20353 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20355 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20356 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20357 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20358 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20359 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20360 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20361 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20362 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20364 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20365 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20366 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20367 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20370 /* NOTE: All VMOV encoding is special-cased! */
20371 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20372 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20375 #define ARM_VARIANT & arm_ext_fp16
20376 #undef THUMB_VARIANT
20377 #define THUMB_VARIANT & arm_ext_fp16
20378 /* New instructions added from v8.2, allowing the extraction and insertion of
20379 the upper 16 bits of a 32-bit vector register. */
20380 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20381 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20383 #undef THUMB_VARIANT
20384 #define THUMB_VARIANT & fpu_neon_ext_v1
20386 #define ARM_VARIANT & fpu_neon_ext_v1
20388 /* Data processing with three registers of the same length. */
20389 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20390 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20391 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20392 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20393 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20394 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20395 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20396 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20397 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20398 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20399 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20400 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20401 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20402 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20403 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20404 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20405 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20406 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20407 /* If not immediate, fall back to neon_dyadic_i64_su.
20408 shl_imm should accept I8 I16 I32 I64,
20409 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20410 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20411 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20412 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20413 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20414 /* Logic ops, types optional & ignored. */
20415 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20416 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20417 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20418 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20419 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20420 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20421 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20422 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20423 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20424 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20425 /* Bitfield ops, untyped. */
20426 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20427 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20428 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20429 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20430 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20431 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20432 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20433 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20434 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20435 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20436 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20437 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20438 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20439 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20440 back to neon_dyadic_if_su. */
20441 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20442 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20443 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20444 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20445 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20446 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20447 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20448 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20449 /* Comparison. Type I8 I16 I32 F32. */
20450 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20451 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20452 /* As above, D registers only. */
20453 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20454 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20455 /* Int and float variants, signedness unimportant. */
20456 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20457 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20458 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20459 /* Add/sub take types I8 I16 I32 I64 F32. */
20460 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20461 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20462 /* vtst takes sizes 8, 16, 32. */
20463 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20464 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20465 /* VMUL takes I8 I16 I32 F32 P8. */
20466 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20467 /* VQD{R}MULH takes S16 S32. */
20468 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20469 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20470 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20471 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20472 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20473 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20474 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20475 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20476 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20477 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20478 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20479 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20480 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20481 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20482 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20483 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20484 /* ARM v8.1 extension. */
20485 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20486 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20487 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20488 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20490 /* Two address, int/float. Types S8 S16 S32 F32. */
20491 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20492 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20494 /* Data processing with two registers and a shift amount. */
20495 /* Right shifts, and variants with rounding.
20496 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20497 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20498 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20499 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20500 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20501 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20502 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20503 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20504 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20505 /* Shift and insert. Sizes accepted 8 16 32 64. */
20506 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20507 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20508 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20509 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20510 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20511 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20512 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20513 /* Right shift immediate, saturating & narrowing, with rounding variants.
20514 Types accepted S16 S32 S64 U16 U32 U64. */
20515 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20516 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20517 /* As above, unsigned. Types accepted S16 S32 S64. */
20518 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20519 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20520 /* Right shift narrowing. Types accepted I16 I32 I64. */
20521 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20522 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20523 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20524 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20525 /* CVT with optional immediate for fixed-point variant. */
20526 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20528 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20529 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20531 /* Data processing, three registers of different lengths. */
20532 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20533 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20534 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20535 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20536 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20537 /* If not scalar, fall back to neon_dyadic_long.
20538 Vector types as above, scalar types S16 S32 U16 U32. */
20539 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20540 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20541 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20542 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20543 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20544 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20545 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20546 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20547 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20548 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20549 /* Saturating doubling multiplies. Types S16 S32. */
20550 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20551 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20552 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20553 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20554 S16 S32 U16 U32. */
20555 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20557 /* Extract. Size 8. */
20558 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20559 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20561 /* Two registers, miscellaneous. */
20562 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20563 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20564 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20565 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20566 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20567 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20568 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20569 /* Vector replicate. Sizes 8 16 32. */
20570 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20571 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20572 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20573 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20574 /* VMOVN. Types I16 I32 I64. */
20575 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20576 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20577 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20578 /* VQMOVUN. Types S16 S32 S64. */
20579 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20580 /* VZIP / VUZP. Sizes 8 16 32. */
20581 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20582 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20583 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20584 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20585 /* VQABS / VQNEG. Types S8 S16 S32. */
20586 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20587 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20588 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20589 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20590 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20591 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20592 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20593 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20594 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20595 /* Reciprocal estimates. Types U32 F16 F32. */
20596 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20597 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20598 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20599 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20600 /* VCLS. Types S8 S16 S32. */
20601 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20602 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20603 /* VCLZ. Types I8 I16 I32. */
20604 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20605 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20606 /* VCNT. Size 8. */
20607 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20608 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20609 /* Two address, untyped. */
20610 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20611 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20612 /* VTRN. Sizes 8 16 32. */
20613 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20614 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20616 /* Table lookup. Size 8. */
20617 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20618 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20620 #undef THUMB_VARIANT
20621 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20623 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20625 /* Neon element/structure load/store. */
20626 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20627 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20628 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20629 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20630 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20631 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20632 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20633 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20635 #undef THUMB_VARIANT
20636 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20638 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20639 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20640 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20641 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20642 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20643 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20644 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20645 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20646 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20647 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20649 #undef THUMB_VARIANT
20650 #define THUMB_VARIANT & fpu_vfp_ext_v3
20652 #define ARM_VARIANT & fpu_vfp_ext_v3
20654 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20655 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20656 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20657 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20658 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20659 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20660 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20661 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20662 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20665 #define ARM_VARIANT & fpu_vfp_ext_fma
20666 #undef THUMB_VARIANT
20667 #define THUMB_VARIANT & fpu_vfp_ext_fma
20668 /* Mnemonics shared by Neon and VFP. These are included in the
20669 VFP FMA variant; NEON and VFP FMA always includes the NEON
20670 FMA instructions. */
20671 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20672 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20673 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20674 the v form should always be used. */
20675 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20676 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20677 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20678 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20679 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20680 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20682 #undef THUMB_VARIANT
20684 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20686 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20687 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20688 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20689 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20690 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20691 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20692 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20693 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20696 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20698 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20699 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20700 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20701 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20702 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20703 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20704 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20705 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20706 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20707 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20708 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20709 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20710 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20711 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20712 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20713 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20714 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20715 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20716 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20717 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20718 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20719 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20720 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20721 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20722 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20723 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20724 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20725 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20726 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20727 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20728 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20729 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20730 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20731 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20732 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20733 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20734 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20735 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20736 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20738 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20745 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20748 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20749 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20750 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20760 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20765 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20766 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20767 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20768 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20776 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20777 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20780 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20787 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20789 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20790 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20791 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20799 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20800 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20801 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20802 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20803 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20804 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20809 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20810 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20811 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20812 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20813 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20814 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20815 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20816 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20817 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20818 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20819 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20820 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20821 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20822 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20823 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20824 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20825 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20826 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20827 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20828 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20829 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20830 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20831 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20832 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20833 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20834 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20841 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20842 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20843 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20844 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20845 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20846 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20850 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20851 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20852 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20853 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20854 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20855 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20858 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20862 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20864 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20865 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20866 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20867 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20868 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20869 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20870 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20885 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20891 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20894 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20895 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20897 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20916 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20925 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20926 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20927 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20928 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20929 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20930 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20931 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20932 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20933 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20934 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20935 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20936 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20937 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20938 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20939 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20940 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20941 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20942 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20943 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20944 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20945 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20946 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20947 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20948 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20949 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20950 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20951 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20952 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20953 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20954 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20955 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20956 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20957 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20958 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20959 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20960 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20961 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20962 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20963 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20964 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20965 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20966 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20967 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20968 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20969 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20970 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20971 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20972 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20973 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20974 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20975 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20976 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20977 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20978 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20979 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20980 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20981 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20982 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20983 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20984 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20985 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20986 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20987 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20988 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20989 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20990 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20991 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20992 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20993 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20994 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20995 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20996 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20997 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20998 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20999 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21000 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21002 /* ARMv8-M instructions. */
21004 #define ARM_VARIANT NULL
21005 #undef THUMB_VARIANT
21006 #define THUMB_VARIANT & arm_ext_v8m
21007 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21008 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21009 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21010 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21011 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21012 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21013 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21015 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21016 instructions behave as nop if no VFP is present. */
21017 #undef THUMB_VARIANT
21018 #define THUMB_VARIANT & arm_ext_v8m_main
21019 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21020 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21023 #undef THUMB_VARIANT
21049 /* MD interface: bits in the object file. */
21051 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21052 for use in the a.out file, and stores them in the array pointed to by buf.
21053 This knows about the endian-ness of the target machine and does
21054 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21055 2 (short) and 4 (long) Floating numbers are put out as a series of
21056 LITTLENUMS (shorts, here at least). */
21059 md_number_to_chars (char * buf
, valueT val
, int n
)
21061 if (target_big_endian
)
21062 number_to_chars_bigendian (buf
, val
, n
);
21064 number_to_chars_littleendian (buf
, val
, n
);
21068 md_chars_to_number (char * buf
, int n
)
21071 unsigned char * where
= (unsigned char *) buf
;
21073 if (target_big_endian
)
21078 result
|= (*where
++ & 255);
21086 result
|= (where
[n
] & 255);
21093 /* MD interface: Sections. */
21095 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21096 that an rs_machine_dependent frag may reach. */
21099 arm_frag_max_var (fragS
*fragp
)
21101 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21102 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21104 Note that we generate relaxable instructions even for cases that don't
21105 really need it, like an immediate that's a trivial constant. So we're
21106 overestimating the instruction size for some of those cases. Rather
21107 than putting more intelligence here, it would probably be better to
21108 avoid generating a relaxation frag in the first place when it can be
21109 determined up front that a short instruction will suffice. */
21111 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21115 /* Estimate the size of a frag before relaxing. Assume everything fits in
21119 md_estimate_size_before_relax (fragS
* fragp
,
21120 segT segtype ATTRIBUTE_UNUSED
)
21126 /* Convert a machine dependent frag. */
21129 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21131 unsigned long insn
;
21132 unsigned long old_op
;
21140 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21142 old_op
= bfd_get_16(abfd
, buf
);
21143 if (fragp
->fr_symbol
)
21145 exp
.X_op
= O_symbol
;
21146 exp
.X_add_symbol
= fragp
->fr_symbol
;
21150 exp
.X_op
= O_constant
;
21152 exp
.X_add_number
= fragp
->fr_offset
;
21153 opcode
= fragp
->fr_subtype
;
21156 case T_MNEM_ldr_pc
:
21157 case T_MNEM_ldr_pc2
:
21158 case T_MNEM_ldr_sp
:
21159 case T_MNEM_str_sp
:
21166 if (fragp
->fr_var
== 4)
21168 insn
= THUMB_OP32 (opcode
);
21169 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21171 insn
|= (old_op
& 0x700) << 4;
21175 insn
|= (old_op
& 7) << 12;
21176 insn
|= (old_op
& 0x38) << 13;
21178 insn
|= 0x00000c00;
21179 put_thumb32_insn (buf
, insn
);
21180 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21184 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21186 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21189 if (fragp
->fr_var
== 4)
21191 insn
= THUMB_OP32 (opcode
);
21192 insn
|= (old_op
& 0xf0) << 4;
21193 put_thumb32_insn (buf
, insn
);
21194 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21198 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21199 exp
.X_add_number
-= 4;
21207 if (fragp
->fr_var
== 4)
21209 int r0off
= (opcode
== T_MNEM_mov
21210 || opcode
== T_MNEM_movs
) ? 0 : 8;
21211 insn
= THUMB_OP32 (opcode
);
21212 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21213 insn
|= (old_op
& 0x700) << r0off
;
21214 put_thumb32_insn (buf
, insn
);
21215 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21219 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21224 if (fragp
->fr_var
== 4)
21226 insn
= THUMB_OP32(opcode
);
21227 put_thumb32_insn (buf
, insn
);
21228 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21231 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21235 if (fragp
->fr_var
== 4)
21237 insn
= THUMB_OP32(opcode
);
21238 insn
|= (old_op
& 0xf00) << 14;
21239 put_thumb32_insn (buf
, insn
);
21240 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21243 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21246 case T_MNEM_add_sp
:
21247 case T_MNEM_add_pc
:
21248 case T_MNEM_inc_sp
:
21249 case T_MNEM_dec_sp
:
21250 if (fragp
->fr_var
== 4)
21252 /* ??? Choose between add and addw. */
21253 insn
= THUMB_OP32 (opcode
);
21254 insn
|= (old_op
& 0xf0) << 4;
21255 put_thumb32_insn (buf
, insn
);
21256 if (opcode
== T_MNEM_add_pc
)
21257 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21259 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21262 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21270 if (fragp
->fr_var
== 4)
21272 insn
= THUMB_OP32 (opcode
);
21273 insn
|= (old_op
& 0xf0) << 4;
21274 insn
|= (old_op
& 0xf) << 16;
21275 put_thumb32_insn (buf
, insn
);
21276 if (insn
& (1 << 20))
21277 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21279 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21282 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21288 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21289 (enum bfd_reloc_code_real
) reloc_type
);
21290 fixp
->fx_file
= fragp
->fr_file
;
21291 fixp
->fx_line
= fragp
->fr_line
;
21292 fragp
->fr_fix
+= fragp
->fr_var
;
21294 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21295 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21296 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21297 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21300 /* Return the size of a relaxable immediate operand instruction.
21301 SHIFT and SIZE specify the form of the allowable immediate. */
21303 relax_immediate (fragS
*fragp
, int size
, int shift
)
21309 /* ??? Should be able to do better than this. */
21310 if (fragp
->fr_symbol
)
21313 low
= (1 << shift
) - 1;
21314 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21315 offset
= fragp
->fr_offset
;
21316 /* Force misaligned offsets to 32-bit variant. */
21319 if (offset
& ~mask
)
21324 /* Get the address of a symbol during relaxation. */
21326 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21332 sym
= fragp
->fr_symbol
;
21333 sym_frag
= symbol_get_frag (sym
);
21334 know (S_GET_SEGMENT (sym
) != absolute_section
21335 || sym_frag
== &zero_address_frag
);
21336 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21338 /* If frag has yet to be reached on this pass, assume it will
21339 move by STRETCH just as we did. If this is not so, it will
21340 be because some frag between grows, and that will force
21344 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21348 /* Adjust stretch for any alignment frag. Note that if have
21349 been expanding the earlier code, the symbol may be
21350 defined in what appears to be an earlier frag. FIXME:
21351 This doesn't handle the fr_subtype field, which specifies
21352 a maximum number of bytes to skip when doing an
21354 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21356 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21359 stretch
= - ((- stretch
)
21360 & ~ ((1 << (int) f
->fr_offset
) - 1));
21362 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21374 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21377 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21382 /* Assume worst case for symbols not known to be in the same section. */
21383 if (fragp
->fr_symbol
== NULL
21384 || !S_IS_DEFINED (fragp
->fr_symbol
)
21385 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21386 || S_IS_WEAK (fragp
->fr_symbol
))
21389 val
= relaxed_symbol_addr (fragp
, stretch
);
21390 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21391 addr
= (addr
+ 4) & ~3;
21392 /* Force misaligned targets to 32-bit variant. */
21396 if (val
< 0 || val
> 1020)
21401 /* Return the size of a relaxable add/sub immediate instruction. */
21403 relax_addsub (fragS
*fragp
, asection
*sec
)
21408 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21409 op
= bfd_get_16(sec
->owner
, buf
);
21410 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21411 return relax_immediate (fragp
, 8, 0);
21413 return relax_immediate (fragp
, 3, 0);
21416 /* Return TRUE iff the definition of symbol S could be pre-empted
21417 (overridden) at link or load time. */
21419 symbol_preemptible (symbolS
*s
)
21421 /* Weak symbols can always be pre-empted. */
21425 /* Non-global symbols cannot be pre-empted. */
21426 if (! S_IS_EXTERNAL (s
))
21430 /* In ELF, a global symbol can be marked protected, or private. In that
21431 case it can't be pre-empted (other definitions in the same link unit
21432 would violate the ODR). */
21433 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21437 /* Other global symbols might be pre-empted. */
21441 /* Return the size of a relaxable branch instruction. BITS is the
21442 size of the offset field in the narrow instruction. */
21445 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21451 /* Assume worst case for symbols not known to be in the same section. */
21452 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21453 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21454 || S_IS_WEAK (fragp
->fr_symbol
))
21458 /* A branch to a function in ARM state will require interworking. */
21459 if (S_IS_DEFINED (fragp
->fr_symbol
)
21460 && ARM_IS_FUNC (fragp
->fr_symbol
))
21464 if (symbol_preemptible (fragp
->fr_symbol
))
21467 val
= relaxed_symbol_addr (fragp
, stretch
);
21468 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21471 /* Offset is a signed value *2 */
21473 if (val
>= limit
|| val
< -limit
)
21479 /* Relax a machine dependent frag. This returns the amount by which
21480 the current size of the frag should change. */
21483 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21488 oldsize
= fragp
->fr_var
;
21489 switch (fragp
->fr_subtype
)
21491 case T_MNEM_ldr_pc2
:
21492 newsize
= relax_adr (fragp
, sec
, stretch
);
21494 case T_MNEM_ldr_pc
:
21495 case T_MNEM_ldr_sp
:
21496 case T_MNEM_str_sp
:
21497 newsize
= relax_immediate (fragp
, 8, 2);
21501 newsize
= relax_immediate (fragp
, 5, 2);
21505 newsize
= relax_immediate (fragp
, 5, 1);
21509 newsize
= relax_immediate (fragp
, 5, 0);
21512 newsize
= relax_adr (fragp
, sec
, stretch
);
21518 newsize
= relax_immediate (fragp
, 8, 0);
21521 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21524 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21526 case T_MNEM_add_sp
:
21527 case T_MNEM_add_pc
:
21528 newsize
= relax_immediate (fragp
, 8, 2);
21530 case T_MNEM_inc_sp
:
21531 case T_MNEM_dec_sp
:
21532 newsize
= relax_immediate (fragp
, 7, 2);
21538 newsize
= relax_addsub (fragp
, sec
);
21544 fragp
->fr_var
= newsize
;
21545 /* Freeze wide instructions that are at or before the same location as
21546 in the previous pass. This avoids infinite loops.
21547 Don't freeze them unconditionally because targets may be artificially
21548 misaligned by the expansion of preceding frags. */
21549 if (stretch
<= 0 && newsize
> 2)
21551 md_convert_frag (sec
->owner
, sec
, fragp
);
21555 return newsize
- oldsize
;
21558 /* Round up a section size to the appropriate boundary. */
21561 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21564 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21565 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21567 /* For a.out, force the section size to be aligned. If we don't do
21568 this, BFD will align it for us, but it will not write out the
21569 final bytes of the section. This may be a bug in BFD, but it is
21570 easier to fix it here since that is how the other a.out targets
21574 align
= bfd_get_section_alignment (stdoutput
, segment
);
21575 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21582 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21583 of an rs_align_code fragment. */
21586 arm_handle_align (fragS
* fragP
)
21588 static unsigned char const arm_noop
[2][2][4] =
21591 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21592 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21595 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21596 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21599 static unsigned char const thumb_noop
[2][2][2] =
21602 {0xc0, 0x46}, /* LE */
21603 {0x46, 0xc0}, /* BE */
21606 {0x00, 0xbf}, /* LE */
21607 {0xbf, 0x00} /* BE */
21610 static unsigned char const wide_thumb_noop
[2][4] =
21611 { /* Wide Thumb-2 */
21612 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21613 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21616 unsigned bytes
, fix
, noop_size
;
21618 const unsigned char * noop
;
21619 const unsigned char *narrow_noop
= NULL
;
21624 if (fragP
->fr_type
!= rs_align_code
)
21627 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21628 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21631 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21632 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21634 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21636 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21638 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21639 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21641 narrow_noop
= thumb_noop
[1][target_big_endian
];
21642 noop
= wide_thumb_noop
[target_big_endian
];
21645 noop
= thumb_noop
[0][target_big_endian
];
21653 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21654 ? selected_cpu
: arm_arch_none
,
21656 [target_big_endian
];
21663 fragP
->fr_var
= noop_size
;
21665 if (bytes
& (noop_size
- 1))
21667 fix
= bytes
& (noop_size
- 1);
21669 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21671 memset (p
, 0, fix
);
21678 if (bytes
& noop_size
)
21680 /* Insert a narrow noop. */
21681 memcpy (p
, narrow_noop
, noop_size
);
21683 bytes
-= noop_size
;
21687 /* Use wide noops for the remainder */
21691 while (bytes
>= noop_size
)
21693 memcpy (p
, noop
, noop_size
);
21695 bytes
-= noop_size
;
21699 fragP
->fr_fix
+= fix
;
21702 /* Called from md_do_align. Used to create an alignment
21703 frag in a code section. */
21706 arm_frag_align_code (int n
, int max
)
21710 /* We assume that there will never be a requirement
21711 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21712 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21717 _("alignments greater than %d bytes not supported in .text sections."),
21718 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21719 as_fatal ("%s", err_msg
);
21722 p
= frag_var (rs_align_code
,
21723 MAX_MEM_FOR_RS_ALIGN_CODE
,
21725 (relax_substateT
) max
,
21732 /* Perform target specific initialisation of a frag.
21733 Note - despite the name this initialisation is not done when the frag
21734 is created, but only when its type is assigned. A frag can be created
21735 and used a long time before its type is set, so beware of assuming that
21736 this initialisationis performed first. */
21740 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21742 /* Record whether this frag is in an ARM or a THUMB area. */
21743 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21746 #else /* OBJ_ELF is defined. */
21748 arm_init_frag (fragS
* fragP
, int max_chars
)
21750 int frag_thumb_mode
;
21752 /* If the current ARM vs THUMB mode has not already
21753 been recorded into this frag then do so now. */
21754 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21755 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21757 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21759 /* Record a mapping symbol for alignment frags. We will delete this
21760 later if the alignment ends up empty. */
21761 switch (fragP
->fr_type
)
21764 case rs_align_test
:
21766 mapping_state_2 (MAP_DATA
, max_chars
);
21768 case rs_align_code
:
21769 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21776 /* When we change sections we need to issue a new mapping symbol. */
21779 arm_elf_change_section (void)
21781 /* Link an unlinked unwind index table section to the .text section. */
21782 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21783 && elf_linked_to_section (now_seg
) == NULL
)
21784 elf_linked_to_section (now_seg
) = text_section
;
21788 arm_elf_section_type (const char * str
, size_t len
)
21790 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21791 return SHT_ARM_EXIDX
;
21796 /* Code to deal with unwinding tables. */
21798 static void add_unwind_adjustsp (offsetT
);
21800 /* Generate any deferred unwind frame offset. */
21803 flush_pending_unwind (void)
21807 offset
= unwind
.pending_offset
;
21808 unwind
.pending_offset
= 0;
21810 add_unwind_adjustsp (offset
);
21813 /* Add an opcode to this list for this function. Two-byte opcodes should
21814 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21818 add_unwind_opcode (valueT op
, int length
)
21820 /* Add any deferred stack adjustment. */
21821 if (unwind
.pending_offset
)
21822 flush_pending_unwind ();
21824 unwind
.sp_restored
= 0;
21826 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21828 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21829 if (unwind
.opcodes
)
21830 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21831 unwind
.opcode_alloc
);
21833 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21838 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21840 unwind
.opcode_count
++;
21844 /* Add unwind opcodes to adjust the stack pointer. */
21847 add_unwind_adjustsp (offsetT offset
)
21851 if (offset
> 0x200)
21853 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21858 /* Long form: 0xb2, uleb128. */
21859 /* This might not fit in a word so add the individual bytes,
21860 remembering the list is built in reverse order. */
21861 o
= (valueT
) ((offset
- 0x204) >> 2);
21863 add_unwind_opcode (0, 1);
21865 /* Calculate the uleb128 encoding of the offset. */
21869 bytes
[n
] = o
& 0x7f;
21875 /* Add the insn. */
21877 add_unwind_opcode (bytes
[n
- 1], 1);
21878 add_unwind_opcode (0xb2, 1);
21880 else if (offset
> 0x100)
21882 /* Two short opcodes. */
21883 add_unwind_opcode (0x3f, 1);
21884 op
= (offset
- 0x104) >> 2;
21885 add_unwind_opcode (op
, 1);
21887 else if (offset
> 0)
21889 /* Short opcode. */
21890 op
= (offset
- 4) >> 2;
21891 add_unwind_opcode (op
, 1);
21893 else if (offset
< 0)
21896 while (offset
> 0x100)
21898 add_unwind_opcode (0x7f, 1);
21901 op
= ((offset
- 4) >> 2) | 0x40;
21902 add_unwind_opcode (op
, 1);
21906 /* Finish the list of unwind opcodes for this function. */
21908 finish_unwind_opcodes (void)
21912 if (unwind
.fp_used
)
21914 /* Adjust sp as necessary. */
21915 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21916 flush_pending_unwind ();
21918 /* After restoring sp from the frame pointer. */
21919 op
= 0x90 | unwind
.fp_reg
;
21920 add_unwind_opcode (op
, 1);
21923 flush_pending_unwind ();
21927 /* Start an exception table entry. If idx is nonzero this is an index table
21931 start_unwind_section (const segT text_seg
, int idx
)
21933 const char * text_name
;
21934 const char * prefix
;
21935 const char * prefix_once
;
21936 const char * group_name
;
21944 prefix
= ELF_STRING_ARM_unwind
;
21945 prefix_once
= ELF_STRING_ARM_unwind_once
;
21946 type
= SHT_ARM_EXIDX
;
21950 prefix
= ELF_STRING_ARM_unwind_info
;
21951 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21952 type
= SHT_PROGBITS
;
21955 text_name
= segment_name (text_seg
);
21956 if (streq (text_name
, ".text"))
21959 if (strncmp (text_name
, ".gnu.linkonce.t.",
21960 strlen (".gnu.linkonce.t.")) == 0)
21962 prefix
= prefix_once
;
21963 text_name
+= strlen (".gnu.linkonce.t.");
21966 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
21972 /* Handle COMDAT group. */
21973 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21975 group_name
= elf_group_name (text_seg
);
21976 if (group_name
== NULL
)
21978 as_bad (_("Group section `%s' has no group signature"),
21979 segment_name (text_seg
));
21980 ignore_rest_of_line ();
21983 flags
|= SHF_GROUP
;
21987 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21989 /* Set the section link for index tables. */
21991 elf_linked_to_section (now_seg
) = text_seg
;
21995 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21996 personality routine data. Returns zero, or the index table value for
21997 an inline entry. */
22000 create_unwind_entry (int have_data
)
22005 /* The current word of data. */
22007 /* The number of bytes left in this word. */
22010 finish_unwind_opcodes ();
22012 /* Remember the current text section. */
22013 unwind
.saved_seg
= now_seg
;
22014 unwind
.saved_subseg
= now_subseg
;
22016 start_unwind_section (now_seg
, 0);
22018 if (unwind
.personality_routine
== NULL
)
22020 if (unwind
.personality_index
== -2)
22023 as_bad (_("handlerdata in cantunwind frame"));
22024 return 1; /* EXIDX_CANTUNWIND. */
22027 /* Use a default personality routine if none is specified. */
22028 if (unwind
.personality_index
== -1)
22030 if (unwind
.opcode_count
> 3)
22031 unwind
.personality_index
= 1;
22033 unwind
.personality_index
= 0;
22036 /* Space for the personality routine entry. */
22037 if (unwind
.personality_index
== 0)
22039 if (unwind
.opcode_count
> 3)
22040 as_bad (_("too many unwind opcodes for personality routine 0"));
22044 /* All the data is inline in the index table. */
22047 while (unwind
.opcode_count
> 0)
22049 unwind
.opcode_count
--;
22050 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22054 /* Pad with "finish" opcodes. */
22056 data
= (data
<< 8) | 0xb0;
22063 /* We get two opcodes "free" in the first word. */
22064 size
= unwind
.opcode_count
- 2;
22068 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22069 if (unwind
.personality_index
!= -1)
22071 as_bad (_("attempt to recreate an unwind entry"));
22075 /* An extra byte is required for the opcode count. */
22076 size
= unwind
.opcode_count
+ 1;
22079 size
= (size
+ 3) >> 2;
22081 as_bad (_("too many unwind opcodes"));
22083 frag_align (2, 0, 0);
22084 record_alignment (now_seg
, 2);
22085 unwind
.table_entry
= expr_build_dot ();
22087 /* Allocate the table entry. */
22088 ptr
= frag_more ((size
<< 2) + 4);
22089 /* PR 13449: Zero the table entries in case some of them are not used. */
22090 memset (ptr
, 0, (size
<< 2) + 4);
22091 where
= frag_now_fix () - ((size
<< 2) + 4);
22093 switch (unwind
.personality_index
)
22096 /* ??? Should this be a PLT generating relocation? */
22097 /* Custom personality routine. */
22098 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22099 BFD_RELOC_ARM_PREL31
);
22104 /* Set the first byte to the number of additional words. */
22105 data
= size
> 0 ? size
- 1 : 0;
22109 /* ABI defined personality routines. */
22111 /* Three opcodes bytes are packed into the first word. */
22118 /* The size and first two opcode bytes go in the first word. */
22119 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22124 /* Should never happen. */
22128 /* Pack the opcodes into words (MSB first), reversing the list at the same
22130 while (unwind
.opcode_count
> 0)
22134 md_number_to_chars (ptr
, data
, 4);
22139 unwind
.opcode_count
--;
22141 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22144 /* Finish off the last word. */
22147 /* Pad with "finish" opcodes. */
22149 data
= (data
<< 8) | 0xb0;
22151 md_number_to_chars (ptr
, data
, 4);
22156 /* Add an empty descriptor if there is no user-specified data. */
22157 ptr
= frag_more (4);
22158 md_number_to_chars (ptr
, 0, 4);
22165 /* Initialize the DWARF-2 unwind information for this procedure. */
22168 tc_arm_frame_initial_instructions (void)
22170 cfi_add_CFA_def_cfa (REG_SP
, 0);
22172 #endif /* OBJ_ELF */
22174 /* Convert REGNAME to a DWARF-2 register number. */
22177 tc_arm_regname_to_dw2regnum (char *regname
)
22179 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22183 /* PR 16694: Allow VFP registers as well. */
22184 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22188 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22197 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22201 exp
.X_op
= O_secrel
;
22202 exp
.X_add_symbol
= symbol
;
22203 exp
.X_add_number
= 0;
22204 emit_expr (&exp
, size
);
22208 /* MD interface: Symbol and relocation handling. */
22210 /* Return the address within the segment that a PC-relative fixup is
22211 relative to. For ARM, PC-relative fixups applied to instructions
22212 are generally relative to the location of the fixup plus 8 bytes.
22213 Thumb branches are offset by 4, and Thumb loads relative to PC
22214 require special handling. */
22217 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22219 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22221 /* If this is pc-relative and we are going to emit a relocation
22222 then we just want to put out any pipeline compensation that the linker
22223 will need. Otherwise we want to use the calculated base.
22224 For WinCE we skip the bias for externals as well, since this
22225 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22227 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22228 || (arm_force_relocation (fixP
)
22230 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22236 switch (fixP
->fx_r_type
)
22238 /* PC relative addressing on the Thumb is slightly odd as the
22239 bottom two bits of the PC are forced to zero for the
22240 calculation. This happens *after* application of the
22241 pipeline offset. However, Thumb adrl already adjusts for
22242 this, so we need not do it again. */
22243 case BFD_RELOC_ARM_THUMB_ADD
:
22246 case BFD_RELOC_ARM_THUMB_OFFSET
:
22247 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22248 case BFD_RELOC_ARM_T32_ADD_PC12
:
22249 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22250 return (base
+ 4) & ~3;
22252 /* Thumb branches are simply offset by +4. */
22253 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22254 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22255 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22256 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22257 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22260 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22262 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22263 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22264 && ARM_IS_FUNC (fixP
->fx_addsy
)
22265 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22266 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22269 /* BLX is like branches above, but forces the low two bits of PC to
22271 case BFD_RELOC_THUMB_PCREL_BLX
:
22273 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22274 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22275 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22276 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22277 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22278 return (base
+ 4) & ~3;
22280 /* ARM mode branches are offset by +8. However, the Windows CE
22281 loader expects the relocation not to take this into account. */
22282 case BFD_RELOC_ARM_PCREL_BLX
:
22284 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22285 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22286 && ARM_IS_FUNC (fixP
->fx_addsy
)
22287 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22288 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22291 case BFD_RELOC_ARM_PCREL_CALL
:
22293 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22294 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22295 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22296 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22297 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22300 case BFD_RELOC_ARM_PCREL_BRANCH
:
22301 case BFD_RELOC_ARM_PCREL_JUMP
:
22302 case BFD_RELOC_ARM_PLT32
:
22304 /* When handling fixups immediately, because we have already
22305 discovered the value of a symbol, or the address of the frag involved
22306 we must account for the offset by +8, as the OS loader will never see the reloc.
22307 see fixup_segment() in write.c
22308 The S_IS_EXTERNAL test handles the case of global symbols.
22309 Those need the calculated base, not just the pipe compensation the linker will need. */
22311 && fixP
->fx_addsy
!= NULL
22312 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22313 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22321 /* ARM mode loads relative to PC are also offset by +8. Unlike
22322 branches, the Windows CE loader *does* expect the relocation
22323 to take this into account. */
22324 case BFD_RELOC_ARM_OFFSET_IMM
:
22325 case BFD_RELOC_ARM_OFFSET_IMM8
:
22326 case BFD_RELOC_ARM_HWLITERAL
:
22327 case BFD_RELOC_ARM_LITERAL
:
22328 case BFD_RELOC_ARM_CP_OFF_IMM
:
22332 /* Other PC-relative relocations are un-offset. */
22338 static bfd_boolean flag_warn_syms
= TRUE
;
22341 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22343 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22344 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22345 does mean that the resulting code might be very confusing to the reader.
22346 Also this warning can be triggered if the user omits an operand before
22347 an immediate address, eg:
22351 GAS treats this as an assignment of the value of the symbol foo to a
22352 symbol LDR, and so (without this code) it will not issue any kind of
22353 warning or error message.
22355 Note - ARM instructions are case-insensitive but the strings in the hash
22356 table are all stored in lower case, so we must first ensure that name is
22358 if (flag_warn_syms
&& arm_ops_hsh
)
22360 char * nbuf
= strdup (name
);
22363 for (p
= nbuf
; *p
; p
++)
22365 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22367 static struct hash_control
* already_warned
= NULL
;
22369 if (already_warned
== NULL
)
22370 already_warned
= hash_new ();
22371 /* Only warn about the symbol once. To keep the code
22372 simple we let hash_insert do the lookup for us. */
22373 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22374 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22383 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22384 Otherwise we have no need to default values of symbols. */
22387 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22390 if (name
[0] == '_' && name
[1] == 'G'
22391 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22395 if (symbol_find (name
))
22396 as_bad (_("GOT already in the symbol table"));
22398 GOT_symbol
= symbol_new (name
, undefined_section
,
22399 (valueT
) 0, & zero_address_frag
);
22409 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22410 computed as two separate immediate values, added together. We
22411 already know that this value cannot be computed by just one ARM
22414 static unsigned int
22415 validate_immediate_twopart (unsigned int val
,
22416 unsigned int * highpart
)
22421 for (i
= 0; i
< 32; i
+= 2)
22422 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22428 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22430 else if (a
& 0xff0000)
22432 if (a
& 0xff000000)
22434 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22438 gas_assert (a
& 0xff000000);
22439 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22442 return (a
& 0xff) | (i
<< 7);
22449 validate_offset_imm (unsigned int val
, int hwse
)
22451 if ((hwse
&& val
> 255) || val
> 4095)
22456 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22457 negative immediate constant by altering the instruction. A bit of
22462 by inverting the second operand, and
22465 by negating the second operand. */
22468 negate_data_op (unsigned long * instruction
,
22469 unsigned long value
)
22472 unsigned long negated
, inverted
;
22474 negated
= encode_arm_immediate (-value
);
22475 inverted
= encode_arm_immediate (~value
);
22477 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22480 /* First negates. */
22481 case OPCODE_SUB
: /* ADD <-> SUB */
22482 new_inst
= OPCODE_ADD
;
22487 new_inst
= OPCODE_SUB
;
22491 case OPCODE_CMP
: /* CMP <-> CMN */
22492 new_inst
= OPCODE_CMN
;
22497 new_inst
= OPCODE_CMP
;
22501 /* Now Inverted ops. */
22502 case OPCODE_MOV
: /* MOV <-> MVN */
22503 new_inst
= OPCODE_MVN
;
22508 new_inst
= OPCODE_MOV
;
22512 case OPCODE_AND
: /* AND <-> BIC */
22513 new_inst
= OPCODE_BIC
;
22518 new_inst
= OPCODE_AND
;
22522 case OPCODE_ADC
: /* ADC <-> SBC */
22523 new_inst
= OPCODE_SBC
;
22528 new_inst
= OPCODE_ADC
;
22532 /* We cannot do anything. */
22537 if (value
== (unsigned) FAIL
)
22540 *instruction
&= OPCODE_MASK
;
22541 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22545 /* Like negate_data_op, but for Thumb-2. */
22547 static unsigned int
22548 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22552 unsigned int negated
, inverted
;
22554 negated
= encode_thumb32_immediate (-value
);
22555 inverted
= encode_thumb32_immediate (~value
);
22557 rd
= (*instruction
>> 8) & 0xf;
22558 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22561 /* ADD <-> SUB. Includes CMP <-> CMN. */
22562 case T2_OPCODE_SUB
:
22563 new_inst
= T2_OPCODE_ADD
;
22567 case T2_OPCODE_ADD
:
22568 new_inst
= T2_OPCODE_SUB
;
22572 /* ORR <-> ORN. Includes MOV <-> MVN. */
22573 case T2_OPCODE_ORR
:
22574 new_inst
= T2_OPCODE_ORN
;
22578 case T2_OPCODE_ORN
:
22579 new_inst
= T2_OPCODE_ORR
;
22583 /* AND <-> BIC. TST has no inverted equivalent. */
22584 case T2_OPCODE_AND
:
22585 new_inst
= T2_OPCODE_BIC
;
22592 case T2_OPCODE_BIC
:
22593 new_inst
= T2_OPCODE_AND
;
22598 case T2_OPCODE_ADC
:
22599 new_inst
= T2_OPCODE_SBC
;
22603 case T2_OPCODE_SBC
:
22604 new_inst
= T2_OPCODE_ADC
;
22608 /* We cannot do anything. */
22613 if (value
== (unsigned int)FAIL
)
22616 *instruction
&= T2_OPCODE_MASK
;
22617 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22621 /* Read a 32-bit thumb instruction from buf. */
22622 static unsigned long
22623 get_thumb32_insn (char * buf
)
22625 unsigned long insn
;
22626 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22627 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22633 /* We usually want to set the low bit on the address of thumb function
22634 symbols. In particular .word foo - . should have the low bit set.
22635 Generic code tries to fold the difference of two symbols to
22636 a constant. Prevent this and force a relocation when the first symbols
22637 is a thumb function. */
22640 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22642 if (op
== O_subtract
22643 && l
->X_op
== O_symbol
22644 && r
->X_op
== O_symbol
22645 && THUMB_IS_FUNC (l
->X_add_symbol
))
22647 l
->X_op
= O_subtract
;
22648 l
->X_op_symbol
= r
->X_add_symbol
;
22649 l
->X_add_number
-= r
->X_add_number
;
22653 /* Process as normal. */
22657 /* Encode Thumb2 unconditional branches and calls. The encoding
22658 for the 2 are identical for the immediate values. */
22661 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22663 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22666 addressT S
, I1
, I2
, lo
, hi
;
22668 S
= (value
>> 24) & 0x01;
22669 I1
= (value
>> 23) & 0x01;
22670 I2
= (value
>> 22) & 0x01;
22671 hi
= (value
>> 12) & 0x3ff;
22672 lo
= (value
>> 1) & 0x7ff;
22673 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22674 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22675 newval
|= (S
<< 10) | hi
;
22676 newval2
&= ~T2I1I2MASK
;
22677 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22678 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22679 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22683 md_apply_fix (fixS
* fixP
,
22687 offsetT value
= * valP
;
22689 unsigned int newimm
;
22690 unsigned long temp
;
22692 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22694 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22696 /* Note whether this will delete the relocation. */
22698 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22701 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22702 consistency with the behaviour on 32-bit hosts. Remember value
22704 value
&= 0xffffffff;
22705 value
^= 0x80000000;
22706 value
-= 0x80000000;
22709 fixP
->fx_addnumber
= value
;
22711 /* Same treatment for fixP->fx_offset. */
22712 fixP
->fx_offset
&= 0xffffffff;
22713 fixP
->fx_offset
^= 0x80000000;
22714 fixP
->fx_offset
-= 0x80000000;
22716 switch (fixP
->fx_r_type
)
22718 case BFD_RELOC_NONE
:
22719 /* This will need to go in the object file. */
22723 case BFD_RELOC_ARM_IMMEDIATE
:
22724 /* We claim that this fixup has been processed here,
22725 even if in fact we generate an error because we do
22726 not have a reloc for it, so tc_gen_reloc will reject it. */
22729 if (fixP
->fx_addsy
)
22731 const char *msg
= 0;
22733 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22734 msg
= _("undefined symbol %s used as an immediate value");
22735 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22736 msg
= _("symbol %s is in a different section");
22737 else if (S_IS_WEAK (fixP
->fx_addsy
))
22738 msg
= _("symbol %s is weak and may be overridden later");
22742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22743 msg
, S_GET_NAME (fixP
->fx_addsy
));
22748 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22750 /* If the offset is negative, we should use encoding A2 for ADR. */
22751 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22752 newimm
= negate_data_op (&temp
, value
);
22755 newimm
= encode_arm_immediate (value
);
22757 /* If the instruction will fail, see if we can fix things up by
22758 changing the opcode. */
22759 if (newimm
== (unsigned int) FAIL
)
22760 newimm
= negate_data_op (&temp
, value
);
22763 if (newimm
== (unsigned int) FAIL
)
22765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22766 _("invalid constant (%lx) after fixup"),
22767 (unsigned long) value
);
22771 newimm
|= (temp
& 0xfffff000);
22772 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22775 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22777 unsigned int highpart
= 0;
22778 unsigned int newinsn
= 0xe1a00000; /* nop. */
22780 if (fixP
->fx_addsy
)
22782 const char *msg
= 0;
22784 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22785 msg
= _("undefined symbol %s used as an immediate value");
22786 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22787 msg
= _("symbol %s is in a different section");
22788 else if (S_IS_WEAK (fixP
->fx_addsy
))
22789 msg
= _("symbol %s is weak and may be overridden later");
22793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22794 msg
, S_GET_NAME (fixP
->fx_addsy
));
22799 newimm
= encode_arm_immediate (value
);
22800 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22802 /* If the instruction will fail, see if we can fix things up by
22803 changing the opcode. */
22804 if (newimm
== (unsigned int) FAIL
22805 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22807 /* No ? OK - try using two ADD instructions to generate
22809 newimm
= validate_immediate_twopart (value
, & highpart
);
22811 /* Yes - then make sure that the second instruction is
22813 if (newimm
!= (unsigned int) FAIL
)
22815 /* Still No ? Try using a negated value. */
22816 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22817 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22818 /* Otherwise - give up. */
22821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22822 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22827 /* Replace the first operand in the 2nd instruction (which
22828 is the PC) with the destination register. We have
22829 already added in the PC in the first instruction and we
22830 do not want to do it again. */
22831 newinsn
&= ~ 0xf0000;
22832 newinsn
|= ((newinsn
& 0x0f000) << 4);
22835 newimm
|= (temp
& 0xfffff000);
22836 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22838 highpart
|= (newinsn
& 0xfffff000);
22839 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22843 case BFD_RELOC_ARM_OFFSET_IMM
:
22844 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22846 /* Fall through. */
22848 case BFD_RELOC_ARM_LITERAL
:
22854 if (validate_offset_imm (value
, 0) == FAIL
)
22856 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22858 _("invalid literal constant: pool needs to be closer"));
22860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22861 _("bad immediate value for offset (%ld)"),
22866 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22868 newval
&= 0xfffff000;
22871 newval
&= 0xff7ff000;
22872 newval
|= value
| (sign
? INDEX_UP
: 0);
22874 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22877 case BFD_RELOC_ARM_OFFSET_IMM8
:
22878 case BFD_RELOC_ARM_HWLITERAL
:
22884 if (validate_offset_imm (value
, 1) == FAIL
)
22886 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22888 _("invalid literal constant: pool needs to be closer"));
22890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22891 _("bad immediate value for 8-bit offset (%ld)"),
22896 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22898 newval
&= 0xfffff0f0;
22901 newval
&= 0xff7ff0f0;
22902 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22904 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22907 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22908 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22910 _("bad immediate value for offset (%ld)"), (long) value
);
22913 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22915 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22918 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22919 /* This is a complicated relocation used for all varieties of Thumb32
22920 load/store instruction with immediate offset:
22922 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22923 *4, optional writeback(W)
22924 (doubleword load/store)
22926 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22927 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22928 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22929 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22930 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22932 Uppercase letters indicate bits that are already encoded at
22933 this point. Lowercase letters are our problem. For the
22934 second block of instructions, the secondary opcode nybble
22935 (bits 8..11) is present, and bit 23 is zero, even if this is
22936 a PC-relative operation. */
22937 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22939 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22941 if ((newval
& 0xf0000000) == 0xe0000000)
22943 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22945 newval
|= (1 << 23);
22948 if (value
% 4 != 0)
22950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22951 _("offset not a multiple of 4"));
22957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22958 _("offset out of range"));
22963 else if ((newval
& 0x000f0000) == 0x000f0000)
22965 /* PC-relative, 12-bit offset. */
22967 newval
|= (1 << 23);
22972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22973 _("offset out of range"));
22978 else if ((newval
& 0x00000100) == 0x00000100)
22980 /* Writeback: 8-bit, +/- offset. */
22982 newval
|= (1 << 9);
22987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22988 _("offset out of range"));
22993 else if ((newval
& 0x00000f00) == 0x00000e00)
22995 /* T-instruction: positive 8-bit offset. */
22996 if (value
< 0 || value
> 0xff)
22998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22999 _("offset out of range"));
23007 /* Positive 12-bit or negative 8-bit offset. */
23011 newval
|= (1 << 23);
23021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23022 _("offset out of range"));
23029 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23030 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23033 case BFD_RELOC_ARM_SHIFT_IMM
:
23034 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23035 if (((unsigned long) value
) > 32
23037 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23040 _("shift expression is too large"));
23045 /* Shifts of zero must be done as lsl. */
23047 else if (value
== 32)
23049 newval
&= 0xfffff07f;
23050 newval
|= (value
& 0x1f) << 7;
23051 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23054 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23055 case BFD_RELOC_ARM_T32_ADD_IMM
:
23056 case BFD_RELOC_ARM_T32_IMM12
:
23057 case BFD_RELOC_ARM_T32_ADD_PC12
:
23058 /* We claim that this fixup has been processed here,
23059 even if in fact we generate an error because we do
23060 not have a reloc for it, so tc_gen_reloc will reject it. */
23064 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23067 _("undefined symbol %s used as an immediate value"),
23068 S_GET_NAME (fixP
->fx_addsy
));
23072 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23074 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23077 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23078 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23080 newimm
= encode_thumb32_immediate (value
);
23081 if (newimm
== (unsigned int) FAIL
)
23082 newimm
= thumb32_negate_data_op (&newval
, value
);
23084 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23085 && newimm
== (unsigned int) FAIL
)
23087 /* Turn add/sum into addw/subw. */
23088 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23089 newval
= (newval
& 0xfeffffff) | 0x02000000;
23090 /* No flat 12-bit imm encoding for addsw/subsw. */
23091 if ((newval
& 0x00100000) == 0)
23093 /* 12 bit immediate for addw/subw. */
23097 newval
^= 0x00a00000;
23100 newimm
= (unsigned int) FAIL
;
23106 if (newimm
== (unsigned int)FAIL
)
23108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23109 _("invalid constant (%lx) after fixup"),
23110 (unsigned long) value
);
23114 newval
|= (newimm
& 0x800) << 15;
23115 newval
|= (newimm
& 0x700) << 4;
23116 newval
|= (newimm
& 0x0ff);
23118 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23119 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23122 case BFD_RELOC_ARM_SMC
:
23123 if (((unsigned long) value
) > 0xffff)
23124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23125 _("invalid smc expression"));
23126 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23127 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23128 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23131 case BFD_RELOC_ARM_HVC
:
23132 if (((unsigned long) value
) > 0xffff)
23133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23134 _("invalid hvc expression"));
23135 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23136 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23137 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23140 case BFD_RELOC_ARM_SWI
:
23141 if (fixP
->tc_fix_data
!= 0)
23143 if (((unsigned long) value
) > 0xff)
23144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23145 _("invalid swi expression"));
23146 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23148 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23152 if (((unsigned long) value
) > 0x00ffffff)
23153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23154 _("invalid swi expression"));
23155 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23157 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23161 case BFD_RELOC_ARM_MULTI
:
23162 if (((unsigned long) value
) > 0xffff)
23163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23164 _("invalid expression in load/store multiple"));
23165 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23166 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23170 case BFD_RELOC_ARM_PCREL_CALL
:
23172 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23174 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23175 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23176 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23177 /* Flip the bl to blx. This is a simple flip
23178 bit here because we generate PCREL_CALL for
23179 unconditional bls. */
23181 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23182 newval
= newval
| 0x10000000;
23183 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23189 goto arm_branch_common
;
23191 case BFD_RELOC_ARM_PCREL_JUMP
:
23192 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23194 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23195 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23196 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23198 /* This would map to a bl<cond>, b<cond>,
23199 b<always> to a Thumb function. We
23200 need to force a relocation for this particular
23202 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23205 /* Fall through. */
23207 case BFD_RELOC_ARM_PLT32
:
23209 case BFD_RELOC_ARM_PCREL_BRANCH
:
23211 goto arm_branch_common
;
23213 case BFD_RELOC_ARM_PCREL_BLX
:
23216 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23218 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23219 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23220 && ARM_IS_FUNC (fixP
->fx_addsy
))
23222 /* Flip the blx to a bl and warn. */
23223 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23224 newval
= 0xeb000000;
23225 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23226 _("blx to '%s' an ARM ISA state function changed to bl"),
23228 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23234 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23235 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23239 /* We are going to store value (shifted right by two) in the
23240 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23241 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23242 also be be clear. */
23244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23245 _("misaligned branch destination"));
23246 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23247 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23250 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23252 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23253 newval
|= (value
>> 2) & 0x00ffffff;
23254 /* Set the H bit on BLX instructions. */
23258 newval
|= 0x01000000;
23260 newval
&= ~0x01000000;
23262 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23266 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23267 /* CBZ can only branch forward. */
23269 /* Attempts to use CBZ to branch to the next instruction
23270 (which, strictly speaking, are prohibited) will be turned into
23273 FIXME: It may be better to remove the instruction completely and
23274 perform relaxation. */
23277 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23278 newval
= 0xbf00; /* NOP encoding T1 */
23279 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23286 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23288 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23289 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23290 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23295 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23296 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23299 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23301 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23302 newval
|= (value
& 0x1ff) >> 1;
23303 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23307 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23308 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23311 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23313 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23314 newval
|= (value
& 0xfff) >> 1;
23315 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23319 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23321 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23322 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23323 && ARM_IS_FUNC (fixP
->fx_addsy
)
23324 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23326 /* Force a relocation for a branch 20 bits wide. */
23329 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23331 _("conditional branch out of range"));
23333 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23336 addressT S
, J1
, J2
, lo
, hi
;
23338 S
= (value
& 0x00100000) >> 20;
23339 J2
= (value
& 0x00080000) >> 19;
23340 J1
= (value
& 0x00040000) >> 18;
23341 hi
= (value
& 0x0003f000) >> 12;
23342 lo
= (value
& 0x00000ffe) >> 1;
23344 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23345 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23346 newval
|= (S
<< 10) | hi
;
23347 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23348 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23349 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23353 case BFD_RELOC_THUMB_PCREL_BLX
:
23354 /* If there is a blx from a thumb state function to
23355 another thumb function flip this to a bl and warn
23359 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23360 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23361 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23363 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23364 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23365 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23367 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23368 newval
= newval
| 0x1000;
23369 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23370 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23375 goto thumb_bl_common
;
23377 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23378 /* A bl from Thumb state ISA to an internal ARM state function
23379 is converted to a blx. */
23381 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23382 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23383 && ARM_IS_FUNC (fixP
->fx_addsy
)
23384 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23386 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23387 newval
= newval
& ~0x1000;
23388 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23389 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23395 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23396 /* For a BLX instruction, make sure that the relocation is rounded up
23397 to a word boundary. This follows the semantics of the instruction
23398 which specifies that bit 1 of the target address will come from bit
23399 1 of the base address. */
23400 value
= (value
+ 3) & ~ 3;
23403 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23404 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23405 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23408 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23410 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23412 else if ((value
& ~0x1ffffff)
23413 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23415 _("Thumb2 branch out of range"));
23418 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23419 encode_thumb2_b_bl_offset (buf
, value
);
23423 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23424 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23427 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23428 encode_thumb2_b_bl_offset (buf
, value
);
23433 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23438 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23439 md_number_to_chars (buf
, value
, 2);
23443 case BFD_RELOC_ARM_TLS_CALL
:
23444 case BFD_RELOC_ARM_THM_TLS_CALL
:
23445 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23446 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23447 case BFD_RELOC_ARM_TLS_GOTDESC
:
23448 case BFD_RELOC_ARM_TLS_GD32
:
23449 case BFD_RELOC_ARM_TLS_LE32
:
23450 case BFD_RELOC_ARM_TLS_IE32
:
23451 case BFD_RELOC_ARM_TLS_LDM32
:
23452 case BFD_RELOC_ARM_TLS_LDO32
:
23453 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23456 case BFD_RELOC_ARM_GOT32
:
23457 case BFD_RELOC_ARM_GOTOFF
:
23460 case BFD_RELOC_ARM_GOT_PREL
:
23461 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23462 md_number_to_chars (buf
, value
, 4);
23465 case BFD_RELOC_ARM_TARGET2
:
23466 /* TARGET2 is not partial-inplace, so we need to write the
23467 addend here for REL targets, because it won't be written out
23468 during reloc processing later. */
23469 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23470 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23474 case BFD_RELOC_RVA
:
23476 case BFD_RELOC_ARM_TARGET1
:
23477 case BFD_RELOC_ARM_ROSEGREL32
:
23478 case BFD_RELOC_ARM_SBREL32
:
23479 case BFD_RELOC_32_PCREL
:
23481 case BFD_RELOC_32_SECREL
:
23483 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23485 /* For WinCE we only do this for pcrel fixups. */
23486 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23488 md_number_to_chars (buf
, value
, 4);
23492 case BFD_RELOC_ARM_PREL31
:
23493 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23495 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23496 if ((value
^ (value
>> 1)) & 0x40000000)
23498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23499 _("rel31 relocation overflow"));
23501 newval
|= value
& 0x7fffffff;
23502 md_number_to_chars (buf
, newval
, 4);
23507 case BFD_RELOC_ARM_CP_OFF_IMM
:
23508 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23509 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23510 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23512 newval
= get_thumb32_insn (buf
);
23513 if ((newval
& 0x0f200f00) == 0x0d000900)
23515 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23516 has permitted values that are multiples of 2, in the range 0
23518 if (value
< -510 || value
> 510 || (value
& 1))
23519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23520 _("co-processor offset out of range"));
23522 else if (value
< -1023 || value
> 1023 || (value
& 3))
23523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23524 _("co-processor offset out of range"));
23529 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23530 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23531 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23533 newval
= get_thumb32_insn (buf
);
23535 newval
&= 0xffffff00;
23538 newval
&= 0xff7fff00;
23539 if ((newval
& 0x0f200f00) == 0x0d000900)
23541 /* This is a fp16 vstr/vldr.
23543 It requires the immediate offset in the instruction is shifted
23544 left by 1 to be a half-word offset.
23546 Here, left shift by 1 first, and later right shift by 2
23547 should get the right offset. */
23550 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23552 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23553 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23554 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23556 put_thumb32_insn (buf
, newval
);
23559 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23560 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23561 if (value
< -255 || value
> 255)
23562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23563 _("co-processor offset out of range"));
23565 goto cp_off_common
;
23567 case BFD_RELOC_ARM_THUMB_OFFSET
:
23568 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23569 /* Exactly what ranges, and where the offset is inserted depends
23570 on the type of instruction, we can establish this from the
23572 switch (newval
>> 12)
23574 case 4: /* PC load. */
23575 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23576 forced to zero for these loads; md_pcrel_from has already
23577 compensated for this. */
23579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23580 _("invalid offset, target not word aligned (0x%08lX)"),
23581 (((unsigned long) fixP
->fx_frag
->fr_address
23582 + (unsigned long) fixP
->fx_where
) & ~3)
23583 + (unsigned long) value
);
23585 if (value
& ~0x3fc)
23586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23587 _("invalid offset, value too big (0x%08lX)"),
23590 newval
|= value
>> 2;
23593 case 9: /* SP load/store. */
23594 if (value
& ~0x3fc)
23595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23596 _("invalid offset, value too big (0x%08lX)"),
23598 newval
|= value
>> 2;
23601 case 6: /* Word load/store. */
23603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23604 _("invalid offset, value too big (0x%08lX)"),
23606 newval
|= value
<< 4; /* 6 - 2. */
23609 case 7: /* Byte load/store. */
23611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23612 _("invalid offset, value too big (0x%08lX)"),
23614 newval
|= value
<< 6;
23617 case 8: /* Halfword load/store. */
23619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23620 _("invalid offset, value too big (0x%08lX)"),
23622 newval
|= value
<< 5; /* 6 - 1. */
23626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23627 "Unable to process relocation for thumb opcode: %lx",
23628 (unsigned long) newval
);
23631 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23634 case BFD_RELOC_ARM_THUMB_ADD
:
23635 /* This is a complicated relocation, since we use it for all of
23636 the following immediate relocations:
23640 9bit ADD/SUB SP word-aligned
23641 10bit ADD PC/SP word-aligned
23643 The type of instruction being processed is encoded in the
23650 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23652 int rd
= (newval
>> 4) & 0xf;
23653 int rs
= newval
& 0xf;
23654 int subtract
= !!(newval
& 0x8000);
23656 /* Check for HI regs, only very restricted cases allowed:
23657 Adjusting SP, and using PC or SP to get an address. */
23658 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23659 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23661 _("invalid Hi register with immediate"));
23663 /* If value is negative, choose the opposite instruction. */
23667 subtract
= !subtract
;
23669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23670 _("immediate value out of range"));
23675 if (value
& ~0x1fc)
23676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23677 _("invalid immediate for stack address calculation"));
23678 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23679 newval
|= value
>> 2;
23681 else if (rs
== REG_PC
|| rs
== REG_SP
)
23683 /* PR gas/18541. If the addition is for a defined symbol
23684 within range of an ADR instruction then accept it. */
23687 && fixP
->fx_addsy
!= NULL
)
23691 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23692 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23693 || S_IS_WEAK (fixP
->fx_addsy
))
23695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23696 _("address calculation needs a strongly defined nearby symbol"));
23700 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23702 /* Round up to the next 4-byte boundary. */
23707 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23712 _("symbol too far away"));
23722 if (subtract
|| value
& ~0x3fc)
23723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23724 _("invalid immediate for address calculation (value = 0x%08lX)"),
23725 (unsigned long) (subtract
? - value
: value
));
23726 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23728 newval
|= value
>> 2;
23733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23734 _("immediate value out of range"));
23735 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23736 newval
|= (rd
<< 8) | value
;
23741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23742 _("immediate value out of range"));
23743 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23744 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23747 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23750 case BFD_RELOC_ARM_THUMB_IMM
:
23751 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23752 if (value
< 0 || value
> 255)
23753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23754 _("invalid immediate: %ld is out of range"),
23757 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23760 case BFD_RELOC_ARM_THUMB_SHIFT
:
23761 /* 5bit shift value (0..32). LSL cannot take 32. */
23762 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23763 temp
= newval
& 0xf800;
23764 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23766 _("invalid shift value: %ld"), (long) value
);
23767 /* Shifts of zero must be encoded as LSL. */
23769 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23770 /* Shifts of 32 are encoded as zero. */
23771 else if (value
== 32)
23773 newval
|= value
<< 6;
23774 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23777 case BFD_RELOC_VTABLE_INHERIT
:
23778 case BFD_RELOC_VTABLE_ENTRY
:
23782 case BFD_RELOC_ARM_MOVW
:
23783 case BFD_RELOC_ARM_MOVT
:
23784 case BFD_RELOC_ARM_THUMB_MOVW
:
23785 case BFD_RELOC_ARM_THUMB_MOVT
:
23786 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23788 /* REL format relocations are limited to a 16-bit addend. */
23789 if (!fixP
->fx_done
)
23791 if (value
< -0x8000 || value
> 0x7fff)
23792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23793 _("offset out of range"));
23795 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23796 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23801 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23802 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23804 newval
= get_thumb32_insn (buf
);
23805 newval
&= 0xfbf08f00;
23806 newval
|= (value
& 0xf000) << 4;
23807 newval
|= (value
& 0x0800) << 15;
23808 newval
|= (value
& 0x0700) << 4;
23809 newval
|= (value
& 0x00ff);
23810 put_thumb32_insn (buf
, newval
);
23814 newval
= md_chars_to_number (buf
, 4);
23815 newval
&= 0xfff0f000;
23816 newval
|= value
& 0x0fff;
23817 newval
|= (value
& 0xf000) << 4;
23818 md_number_to_chars (buf
, newval
, 4);
23823 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23824 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23825 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23826 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23827 gas_assert (!fixP
->fx_done
);
23830 bfd_boolean is_mov
;
23831 bfd_vma encoded_addend
= value
;
23833 /* Check that addend can be encoded in instruction. */
23834 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23836 _("the offset 0x%08lX is not representable"),
23837 (unsigned long) encoded_addend
);
23839 /* Extract the instruction. */
23840 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23841 is_mov
= (insn
& 0xf800) == 0x2000;
23846 if (!seg
->use_rela_p
)
23847 insn
|= encoded_addend
;
23853 /* Extract the instruction. */
23854 /* Encoding is the following
23859 /* The following conditions must be true :
23864 rd
= (insn
>> 4) & 0xf;
23866 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23868 _("Unable to process relocation for thumb opcode: %lx"),
23869 (unsigned long) insn
);
23871 /* Encode as ADD immediate8 thumb 1 code. */
23872 insn
= 0x3000 | (rd
<< 8);
23874 /* Place the encoded addend into the first 8 bits of the
23876 if (!seg
->use_rela_p
)
23877 insn
|= encoded_addend
;
23880 /* Update the instruction. */
23881 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23885 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23886 case BFD_RELOC_ARM_ALU_PC_G0
:
23887 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23888 case BFD_RELOC_ARM_ALU_PC_G1
:
23889 case BFD_RELOC_ARM_ALU_PC_G2
:
23890 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23891 case BFD_RELOC_ARM_ALU_SB_G0
:
23892 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23893 case BFD_RELOC_ARM_ALU_SB_G1
:
23894 case BFD_RELOC_ARM_ALU_SB_G2
:
23895 gas_assert (!fixP
->fx_done
);
23896 if (!seg
->use_rela_p
)
23899 bfd_vma encoded_addend
;
23900 bfd_vma addend_abs
= abs (value
);
23902 /* Check that the absolute value of the addend can be
23903 expressed as an 8-bit constant plus a rotation. */
23904 encoded_addend
= encode_arm_immediate (addend_abs
);
23905 if (encoded_addend
== (unsigned int) FAIL
)
23906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23907 _("the offset 0x%08lX is not representable"),
23908 (unsigned long) addend_abs
);
23910 /* Extract the instruction. */
23911 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23913 /* If the addend is positive, use an ADD instruction.
23914 Otherwise use a SUB. Take care not to destroy the S bit. */
23915 insn
&= 0xff1fffff;
23921 /* Place the encoded addend into the first 12 bits of the
23923 insn
&= 0xfffff000;
23924 insn
|= encoded_addend
;
23926 /* Update the instruction. */
23927 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23931 case BFD_RELOC_ARM_LDR_PC_G0
:
23932 case BFD_RELOC_ARM_LDR_PC_G1
:
23933 case BFD_RELOC_ARM_LDR_PC_G2
:
23934 case BFD_RELOC_ARM_LDR_SB_G0
:
23935 case BFD_RELOC_ARM_LDR_SB_G1
:
23936 case BFD_RELOC_ARM_LDR_SB_G2
:
23937 gas_assert (!fixP
->fx_done
);
23938 if (!seg
->use_rela_p
)
23941 bfd_vma addend_abs
= abs (value
);
23943 /* Check that the absolute value of the addend can be
23944 encoded in 12 bits. */
23945 if (addend_abs
>= 0x1000)
23946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23947 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23948 (unsigned long) addend_abs
);
23950 /* Extract the instruction. */
23951 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23953 /* If the addend is negative, clear bit 23 of the instruction.
23954 Otherwise set it. */
23956 insn
&= ~(1 << 23);
23960 /* Place the absolute value of the addend into the first 12 bits
23961 of the instruction. */
23962 insn
&= 0xfffff000;
23963 insn
|= addend_abs
;
23965 /* Update the instruction. */
23966 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23970 case BFD_RELOC_ARM_LDRS_PC_G0
:
23971 case BFD_RELOC_ARM_LDRS_PC_G1
:
23972 case BFD_RELOC_ARM_LDRS_PC_G2
:
23973 case BFD_RELOC_ARM_LDRS_SB_G0
:
23974 case BFD_RELOC_ARM_LDRS_SB_G1
:
23975 case BFD_RELOC_ARM_LDRS_SB_G2
:
23976 gas_assert (!fixP
->fx_done
);
23977 if (!seg
->use_rela_p
)
23980 bfd_vma addend_abs
= abs (value
);
23982 /* Check that the absolute value of the addend can be
23983 encoded in 8 bits. */
23984 if (addend_abs
>= 0x100)
23985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23986 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23987 (unsigned long) addend_abs
);
23989 /* Extract the instruction. */
23990 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23992 /* If the addend is negative, clear bit 23 of the instruction.
23993 Otherwise set it. */
23995 insn
&= ~(1 << 23);
23999 /* Place the first four bits of the absolute value of the addend
24000 into the first 4 bits of the instruction, and the remaining
24001 four into bits 8 .. 11. */
24002 insn
&= 0xfffff0f0;
24003 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24005 /* Update the instruction. */
24006 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24010 case BFD_RELOC_ARM_LDC_PC_G0
:
24011 case BFD_RELOC_ARM_LDC_PC_G1
:
24012 case BFD_RELOC_ARM_LDC_PC_G2
:
24013 case BFD_RELOC_ARM_LDC_SB_G0
:
24014 case BFD_RELOC_ARM_LDC_SB_G1
:
24015 case BFD_RELOC_ARM_LDC_SB_G2
:
24016 gas_assert (!fixP
->fx_done
);
24017 if (!seg
->use_rela_p
)
24020 bfd_vma addend_abs
= abs (value
);
24022 /* Check that the absolute value of the addend is a multiple of
24023 four and, when divided by four, fits in 8 bits. */
24024 if (addend_abs
& 0x3)
24025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24026 _("bad offset 0x%08lX (must be word-aligned)"),
24027 (unsigned long) addend_abs
);
24029 if ((addend_abs
>> 2) > 0xff)
24030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24031 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24032 (unsigned long) addend_abs
);
24034 /* Extract the instruction. */
24035 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24037 /* If the addend is negative, clear bit 23 of the instruction.
24038 Otherwise set it. */
24040 insn
&= ~(1 << 23);
24044 /* Place the addend (divided by four) into the first eight
24045 bits of the instruction. */
24046 insn
&= 0xfffffff0;
24047 insn
|= addend_abs
>> 2;
24049 /* Update the instruction. */
24050 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24054 case BFD_RELOC_ARM_V4BX
:
24055 /* This will need to go in the object file. */
24059 case BFD_RELOC_UNUSED
:
24061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24062 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24066 /* Translate internal representation of relocation info to BFD target
24070 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24073 bfd_reloc_code_real_type code
;
24075 reloc
= XNEW (arelent
);
24077 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24078 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24079 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24081 if (fixp
->fx_pcrel
)
24083 if (section
->use_rela_p
)
24084 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24086 fixp
->fx_offset
= reloc
->address
;
24088 reloc
->addend
= fixp
->fx_offset
;
24090 switch (fixp
->fx_r_type
)
24093 if (fixp
->fx_pcrel
)
24095 code
= BFD_RELOC_8_PCREL
;
24098 /* Fall through. */
24101 if (fixp
->fx_pcrel
)
24103 code
= BFD_RELOC_16_PCREL
;
24106 /* Fall through. */
24109 if (fixp
->fx_pcrel
)
24111 code
= BFD_RELOC_32_PCREL
;
24114 /* Fall through. */
24116 case BFD_RELOC_ARM_MOVW
:
24117 if (fixp
->fx_pcrel
)
24119 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24122 /* Fall through. */
24124 case BFD_RELOC_ARM_MOVT
:
24125 if (fixp
->fx_pcrel
)
24127 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24130 /* Fall through. */
24132 case BFD_RELOC_ARM_THUMB_MOVW
:
24133 if (fixp
->fx_pcrel
)
24135 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24138 /* Fall through. */
24140 case BFD_RELOC_ARM_THUMB_MOVT
:
24141 if (fixp
->fx_pcrel
)
24143 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24146 /* Fall through. */
24148 case BFD_RELOC_NONE
:
24149 case BFD_RELOC_ARM_PCREL_BRANCH
:
24150 case BFD_RELOC_ARM_PCREL_BLX
:
24151 case BFD_RELOC_RVA
:
24152 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24153 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24154 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24155 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24156 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24157 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24158 case BFD_RELOC_VTABLE_ENTRY
:
24159 case BFD_RELOC_VTABLE_INHERIT
:
24161 case BFD_RELOC_32_SECREL
:
24163 code
= fixp
->fx_r_type
;
24166 case BFD_RELOC_THUMB_PCREL_BLX
:
24168 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24169 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24172 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24175 case BFD_RELOC_ARM_LITERAL
:
24176 case BFD_RELOC_ARM_HWLITERAL
:
24177 /* If this is called then the a literal has
24178 been referenced across a section boundary. */
24179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24180 _("literal referenced across section boundary"));
24184 case BFD_RELOC_ARM_TLS_CALL
:
24185 case BFD_RELOC_ARM_THM_TLS_CALL
:
24186 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24187 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24188 case BFD_RELOC_ARM_GOT32
:
24189 case BFD_RELOC_ARM_GOTOFF
:
24190 case BFD_RELOC_ARM_GOT_PREL
:
24191 case BFD_RELOC_ARM_PLT32
:
24192 case BFD_RELOC_ARM_TARGET1
:
24193 case BFD_RELOC_ARM_ROSEGREL32
:
24194 case BFD_RELOC_ARM_SBREL32
:
24195 case BFD_RELOC_ARM_PREL31
:
24196 case BFD_RELOC_ARM_TARGET2
:
24197 case BFD_RELOC_ARM_TLS_LDO32
:
24198 case BFD_RELOC_ARM_PCREL_CALL
:
24199 case BFD_RELOC_ARM_PCREL_JUMP
:
24200 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24201 case BFD_RELOC_ARM_ALU_PC_G0
:
24202 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24203 case BFD_RELOC_ARM_ALU_PC_G1
:
24204 case BFD_RELOC_ARM_ALU_PC_G2
:
24205 case BFD_RELOC_ARM_LDR_PC_G0
:
24206 case BFD_RELOC_ARM_LDR_PC_G1
:
24207 case BFD_RELOC_ARM_LDR_PC_G2
:
24208 case BFD_RELOC_ARM_LDRS_PC_G0
:
24209 case BFD_RELOC_ARM_LDRS_PC_G1
:
24210 case BFD_RELOC_ARM_LDRS_PC_G2
:
24211 case BFD_RELOC_ARM_LDC_PC_G0
:
24212 case BFD_RELOC_ARM_LDC_PC_G1
:
24213 case BFD_RELOC_ARM_LDC_PC_G2
:
24214 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24215 case BFD_RELOC_ARM_ALU_SB_G0
:
24216 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24217 case BFD_RELOC_ARM_ALU_SB_G1
:
24218 case BFD_RELOC_ARM_ALU_SB_G2
:
24219 case BFD_RELOC_ARM_LDR_SB_G0
:
24220 case BFD_RELOC_ARM_LDR_SB_G1
:
24221 case BFD_RELOC_ARM_LDR_SB_G2
:
24222 case BFD_RELOC_ARM_LDRS_SB_G0
:
24223 case BFD_RELOC_ARM_LDRS_SB_G1
:
24224 case BFD_RELOC_ARM_LDRS_SB_G2
:
24225 case BFD_RELOC_ARM_LDC_SB_G0
:
24226 case BFD_RELOC_ARM_LDC_SB_G1
:
24227 case BFD_RELOC_ARM_LDC_SB_G2
:
24228 case BFD_RELOC_ARM_V4BX
:
24229 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24230 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24231 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24232 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24233 code
= fixp
->fx_r_type
;
24236 case BFD_RELOC_ARM_TLS_GOTDESC
:
24237 case BFD_RELOC_ARM_TLS_GD32
:
24238 case BFD_RELOC_ARM_TLS_LE32
:
24239 case BFD_RELOC_ARM_TLS_IE32
:
24240 case BFD_RELOC_ARM_TLS_LDM32
:
24241 /* BFD will include the symbol's address in the addend.
24242 But we don't want that, so subtract it out again here. */
24243 if (!S_IS_COMMON (fixp
->fx_addsy
))
24244 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24245 code
= fixp
->fx_r_type
;
24249 case BFD_RELOC_ARM_IMMEDIATE
:
24250 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24251 _("internal relocation (type: IMMEDIATE) not fixed up"));
24254 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24255 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24256 _("ADRL used for a symbol not defined in the same file"));
24259 case BFD_RELOC_ARM_OFFSET_IMM
:
24260 if (section
->use_rela_p
)
24262 code
= fixp
->fx_r_type
;
24266 if (fixp
->fx_addsy
!= NULL
24267 && !S_IS_DEFINED (fixp
->fx_addsy
)
24268 && S_IS_LOCAL (fixp
->fx_addsy
))
24270 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24271 _("undefined local label `%s'"),
24272 S_GET_NAME (fixp
->fx_addsy
));
24276 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24277 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24284 switch (fixp
->fx_r_type
)
24286 case BFD_RELOC_NONE
: type
= "NONE"; break;
24287 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24288 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24289 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24290 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24291 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24292 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24293 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24294 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24295 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24296 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24297 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24298 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24299 default: type
= _("<unknown>"); break;
24301 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24302 _("cannot represent %s relocation in this object file format"),
24309 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24311 && fixp
->fx_addsy
== GOT_symbol
)
24313 code
= BFD_RELOC_ARM_GOTPC
;
24314 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24318 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24320 if (reloc
->howto
== NULL
)
24322 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24323 _("cannot represent %s relocation in this object file format"),
24324 bfd_get_reloc_code_name (code
));
24328 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24329 vtable entry to be used in the relocation's section offset. */
24330 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24331 reloc
->address
= fixp
->fx_offset
;
24336 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24339 cons_fix_new_arm (fragS
* frag
,
24343 bfd_reloc_code_real_type reloc
)
24348 FIXME: @@ Should look at CPU word size. */
24352 reloc
= BFD_RELOC_8
;
24355 reloc
= BFD_RELOC_16
;
24359 reloc
= BFD_RELOC_32
;
24362 reloc
= BFD_RELOC_64
;
24367 if (exp
->X_op
== O_secrel
)
24369 exp
->X_op
= O_symbol
;
24370 reloc
= BFD_RELOC_32_SECREL
;
24374 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24377 #if defined (OBJ_COFF)
24379 arm_validate_fix (fixS
* fixP
)
24381 /* If the destination of the branch is a defined symbol which does not have
24382 the THUMB_FUNC attribute, then we must be calling a function which has
24383 the (interfacearm) attribute. We look for the Thumb entry point to that
24384 function and change the branch to refer to that function instead. */
24385 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24386 && fixP
->fx_addsy
!= NULL
24387 && S_IS_DEFINED (fixP
->fx_addsy
)
24388 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24390 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24397 arm_force_relocation (struct fix
* fixp
)
24399 #if defined (OBJ_COFF) && defined (TE_PE)
24400 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24404 /* In case we have a call or a branch to a function in ARM ISA mode from
24405 a thumb function or vice-versa force the relocation. These relocations
24406 are cleared off for some cores that might have blx and simple transformations
24410 switch (fixp
->fx_r_type
)
24412 case BFD_RELOC_ARM_PCREL_JUMP
:
24413 case BFD_RELOC_ARM_PCREL_CALL
:
24414 case BFD_RELOC_THUMB_PCREL_BLX
:
24415 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24419 case BFD_RELOC_ARM_PCREL_BLX
:
24420 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24421 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24422 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24423 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24432 /* Resolve these relocations even if the symbol is extern or weak.
24433 Technically this is probably wrong due to symbol preemption.
24434 In practice these relocations do not have enough range to be useful
24435 at dynamic link time, and some code (e.g. in the Linux kernel)
24436 expects these references to be resolved. */
24437 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24438 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24439 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24440 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24441 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24442 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24443 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24444 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24445 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24446 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24447 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24448 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24449 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24450 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24453 /* Always leave these relocations for the linker. */
24454 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24455 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24456 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24459 /* Always generate relocations against function symbols. */
24460 if (fixp
->fx_r_type
== BFD_RELOC_32
24462 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24465 return generic_force_reloc (fixp
);
24468 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24469 /* Relocations against function names must be left unadjusted,
24470 so that the linker can use this information to generate interworking
24471 stubs. The MIPS version of this function
24472 also prevents relocations that are mips-16 specific, but I do not
24473 know why it does this.
24476 There is one other problem that ought to be addressed here, but
24477 which currently is not: Taking the address of a label (rather
24478 than a function) and then later jumping to that address. Such
24479 addresses also ought to have their bottom bit set (assuming that
24480 they reside in Thumb code), but at the moment they will not. */
24483 arm_fix_adjustable (fixS
* fixP
)
24485 if (fixP
->fx_addsy
== NULL
)
24488 /* Preserve relocations against symbols with function type. */
24489 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24492 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24493 && fixP
->fx_subsy
== NULL
)
24496 /* We need the symbol name for the VTABLE entries. */
24497 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24498 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24501 /* Don't allow symbols to be discarded on GOT related relocs. */
24502 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24503 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24504 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24505 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24506 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24507 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24508 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24509 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24510 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24511 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24512 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24513 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24514 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24515 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24518 /* Similarly for group relocations. */
24519 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24520 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24521 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24524 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24525 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24526 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24527 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24528 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24529 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24530 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24531 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24532 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24535 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24536 offsets, so keep these symbols. */
24537 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24538 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24543 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24547 elf32_arm_target_format (void)
24550 return (target_big_endian
24551 ? "elf32-bigarm-symbian"
24552 : "elf32-littlearm-symbian");
24553 #elif defined (TE_VXWORKS)
24554 return (target_big_endian
24555 ? "elf32-bigarm-vxworks"
24556 : "elf32-littlearm-vxworks");
24557 #elif defined (TE_NACL)
24558 return (target_big_endian
24559 ? "elf32-bigarm-nacl"
24560 : "elf32-littlearm-nacl");
24562 if (target_big_endian
)
24563 return "elf32-bigarm";
24565 return "elf32-littlearm";
24570 armelf_frob_symbol (symbolS
* symp
,
24573 elf_frob_symbol (symp
, puntp
);
24577 /* MD interface: Finalization. */
24582 literal_pool
* pool
;
24584 /* Ensure that all the IT blocks are properly closed. */
24585 check_it_blocks_finished ();
24587 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24589 /* Put it at the end of the relevant section. */
24590 subseg_set (pool
->section
, pool
->sub_section
);
24592 arm_elf_change_section ();
24599 /* Remove any excess mapping symbols generated for alignment frags in
24600 SEC. We may have created a mapping symbol before a zero byte
24601 alignment; remove it if there's a mapping symbol after the
24604 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24605 void *dummy ATTRIBUTE_UNUSED
)
24607 segment_info_type
*seginfo
= seg_info (sec
);
24610 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24613 for (fragp
= seginfo
->frchainP
->frch_root
;
24615 fragp
= fragp
->fr_next
)
24617 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24618 fragS
*next
= fragp
->fr_next
;
24620 /* Variable-sized frags have been converted to fixed size by
24621 this point. But if this was variable-sized to start with,
24622 there will be a fixed-size frag after it. So don't handle
24624 if (sym
== NULL
|| next
== NULL
)
24627 if (S_GET_VALUE (sym
) < next
->fr_address
)
24628 /* Not at the end of this frag. */
24630 know (S_GET_VALUE (sym
) == next
->fr_address
);
24634 if (next
->tc_frag_data
.first_map
!= NULL
)
24636 /* Next frag starts with a mapping symbol. Discard this
24638 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24642 if (next
->fr_next
== NULL
)
24644 /* This mapping symbol is at the end of the section. Discard
24646 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24647 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24651 /* As long as we have empty frags without any mapping symbols,
24653 /* If the next frag is non-empty and does not start with a
24654 mapping symbol, then this mapping symbol is required. */
24655 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24658 next
= next
->fr_next
;
24660 while (next
!= NULL
);
24665 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24669 arm_adjust_symtab (void)
24674 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24676 if (ARM_IS_THUMB (sym
))
24678 if (THUMB_IS_FUNC (sym
))
24680 /* Mark the symbol as a Thumb function. */
24681 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24682 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24683 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24685 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24686 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24688 as_bad (_("%s: unexpected function type: %d"),
24689 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24691 else switch (S_GET_STORAGE_CLASS (sym
))
24694 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24697 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24700 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24708 if (ARM_IS_INTERWORK (sym
))
24709 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24716 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24718 if (ARM_IS_THUMB (sym
))
24720 elf_symbol_type
* elf_sym
;
24722 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24723 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24725 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24726 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24728 /* If it's a .thumb_func, declare it as so,
24729 otherwise tag label as .code 16. */
24730 if (THUMB_IS_FUNC (sym
))
24731 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24732 ST_BRANCH_TO_THUMB
);
24733 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24734 elf_sym
->internal_elf_sym
.st_info
=
24735 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24740 /* Remove any overlapping mapping symbols generated by alignment frags. */
24741 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24742 /* Now do generic ELF adjustments. */
24743 elf_adjust_symtab ();
24747 /* MD interface: Initialization. */
24750 set_constant_flonums (void)
24754 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24755 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24759 /* Auto-select Thumb mode if it's the only available instruction set for the
24760 given architecture. */
24763 autoselect_thumb_from_cpu_variant (void)
24765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24766 opcode_select (16);
24775 if ( (arm_ops_hsh
= hash_new ()) == NULL
24776 || (arm_cond_hsh
= hash_new ()) == NULL
24777 || (arm_shift_hsh
= hash_new ()) == NULL
24778 || (arm_psr_hsh
= hash_new ()) == NULL
24779 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24780 || (arm_reg_hsh
= hash_new ()) == NULL
24781 || (arm_reloc_hsh
= hash_new ()) == NULL
24782 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24783 as_fatal (_("virtual memory exhausted"));
24785 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24786 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24787 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24788 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24789 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24790 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24791 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24792 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24793 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24794 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24795 (void *) (v7m_psrs
+ i
));
24796 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24797 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24799 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24801 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24802 (void *) (barrier_opt_names
+ i
));
24804 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24806 struct reloc_entry
* entry
= reloc_names
+ i
;
24808 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24809 /* This makes encode_branch() use the EABI versions of this relocation. */
24810 entry
->reloc
= BFD_RELOC_UNUSED
;
24812 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24816 set_constant_flonums ();
24818 /* Set the cpu variant based on the command-line options. We prefer
24819 -mcpu= over -march= if both are set (as for GCC); and we prefer
24820 -mfpu= over any other way of setting the floating point unit.
24821 Use of legacy options with new options are faulted. */
24824 if (mcpu_cpu_opt
|| march_cpu_opt
)
24825 as_bad (_("use of old and new-style options to set CPU type"));
24827 mcpu_cpu_opt
= legacy_cpu
;
24829 else if (!mcpu_cpu_opt
)
24830 mcpu_cpu_opt
= march_cpu_opt
;
24835 as_bad (_("use of old and new-style options to set FPU type"));
24837 mfpu_opt
= legacy_fpu
;
24839 else if (!mfpu_opt
)
24841 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24842 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24843 /* Some environments specify a default FPU. If they don't, infer it
24844 from the processor. */
24846 mfpu_opt
= mcpu_fpu_opt
;
24848 mfpu_opt
= march_fpu_opt
;
24850 mfpu_opt
= &fpu_default
;
24856 if (mcpu_cpu_opt
!= NULL
)
24857 mfpu_opt
= &fpu_default
;
24858 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24859 mfpu_opt
= &fpu_arch_vfp_v2
;
24861 mfpu_opt
= &fpu_arch_fpa
;
24867 mcpu_cpu_opt
= &cpu_default
;
24868 selected_cpu
= cpu_default
;
24870 else if (no_cpu_selected ())
24871 selected_cpu
= cpu_default
;
24874 selected_cpu
= *mcpu_cpu_opt
;
24876 mcpu_cpu_opt
= &arm_arch_any
;
24879 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24881 autoselect_thumb_from_cpu_variant ();
24883 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24885 #if defined OBJ_COFF || defined OBJ_ELF
24887 unsigned int flags
= 0;
24889 #if defined OBJ_ELF
24890 flags
= meabi_flags
;
24892 switch (meabi_flags
)
24894 case EF_ARM_EABI_UNKNOWN
:
24896 /* Set the flags in the private structure. */
24897 if (uses_apcs_26
) flags
|= F_APCS26
;
24898 if (support_interwork
) flags
|= F_INTERWORK
;
24899 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24900 if (pic_code
) flags
|= F_PIC
;
24901 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24902 flags
|= F_SOFT_FLOAT
;
24904 switch (mfloat_abi_opt
)
24906 case ARM_FLOAT_ABI_SOFT
:
24907 case ARM_FLOAT_ABI_SOFTFP
:
24908 flags
|= F_SOFT_FLOAT
;
24911 case ARM_FLOAT_ABI_HARD
:
24912 if (flags
& F_SOFT_FLOAT
)
24913 as_bad (_("hard-float conflicts with specified fpu"));
24917 /* Using pure-endian doubles (even if soft-float). */
24918 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24919 flags
|= F_VFP_FLOAT
;
24921 #if defined OBJ_ELF
24922 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24923 flags
|= EF_ARM_MAVERICK_FLOAT
;
24926 case EF_ARM_EABI_VER4
:
24927 case EF_ARM_EABI_VER5
:
24928 /* No additional flags to set. */
24935 bfd_set_private_flags (stdoutput
, flags
);
24937 /* We have run out flags in the COFF header to encode the
24938 status of ATPCS support, so instead we create a dummy,
24939 empty, debug section called .arm.atpcs. */
24944 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24948 bfd_set_section_flags
24949 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24950 bfd_set_section_size (stdoutput
, sec
, 0);
24951 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24957 /* Record the CPU type as well. */
24958 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24959 mach
= bfd_mach_arm_iWMMXt2
;
24960 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24961 mach
= bfd_mach_arm_iWMMXt
;
24962 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24963 mach
= bfd_mach_arm_XScale
;
24964 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24965 mach
= bfd_mach_arm_ep9312
;
24966 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24967 mach
= bfd_mach_arm_5TE
;
24968 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24970 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24971 mach
= bfd_mach_arm_5T
;
24973 mach
= bfd_mach_arm_5
;
24975 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24977 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24978 mach
= bfd_mach_arm_4T
;
24980 mach
= bfd_mach_arm_4
;
24982 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24983 mach
= bfd_mach_arm_3M
;
24984 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24985 mach
= bfd_mach_arm_3
;
24986 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24987 mach
= bfd_mach_arm_2a
;
24988 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24989 mach
= bfd_mach_arm_2
;
24991 mach
= bfd_mach_arm_unknown
;
24993 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24996 /* Command line processing. */
24999 Invocation line includes a switch not recognized by the base assembler.
25000 See if it's a processor-specific option.
25002 This routine is somewhat complicated by the need for backwards
25003 compatibility (since older releases of gcc can't be changed).
25004 The new options try to make the interface as compatible as
25007 New options (supported) are:
25009 -mcpu=<cpu name> Assemble for selected processor
25010 -march=<architecture name> Assemble for selected architecture
25011 -mfpu=<fpu architecture> Assemble for selected FPU.
25012 -EB/-mbig-endian Big-endian
25013 -EL/-mlittle-endian Little-endian
25014 -k Generate PIC code
25015 -mthumb Start in Thumb mode
25016 -mthumb-interwork Code supports ARM/Thumb interworking
25018 -m[no-]warn-deprecated Warn about deprecated features
25019 -m[no-]warn-syms Warn when symbols match instructions
25021 For now we will also provide support for:
25023 -mapcs-32 32-bit Program counter
25024 -mapcs-26 26-bit Program counter
25025 -macps-float Floats passed in FP registers
25026 -mapcs-reentrant Reentrant code
25028 (sometime these will probably be replaced with -mapcs=<list of options>
25029 and -matpcs=<list of options>)
25031 The remaining options are only supported for back-wards compatibility.
25032 Cpu variants, the arm part is optional:
25033 -m[arm]1 Currently not supported.
25034 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25035 -m[arm]3 Arm 3 processor
25036 -m[arm]6[xx], Arm 6 processors
25037 -m[arm]7[xx][t][[d]m] Arm 7 processors
25038 -m[arm]8[10] Arm 8 processors
25039 -m[arm]9[20][tdmi] Arm 9 processors
25040 -mstrongarm[110[0]] StrongARM processors
25041 -mxscale XScale processors
25042 -m[arm]v[2345[t[e]]] Arm architectures
25043 -mall All (except the ARM1)
25045 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25046 -mfpe-old (No float load/store multiples)
25047 -mvfpxd VFP Single precision
25049 -mno-fpu Disable all floating point instructions
25051 The following CPU names are recognized:
25052 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25053 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25054 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25055 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25056 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25057 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25058 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25062 const char * md_shortopts
= "m:k";
25064 #ifdef ARM_BI_ENDIAN
25065 #define OPTION_EB (OPTION_MD_BASE + 0)
25066 #define OPTION_EL (OPTION_MD_BASE + 1)
25068 #if TARGET_BYTES_BIG_ENDIAN
25069 #define OPTION_EB (OPTION_MD_BASE + 0)
25071 #define OPTION_EL (OPTION_MD_BASE + 1)
25074 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25076 struct option md_longopts
[] =
25079 {"EB", no_argument
, NULL
, OPTION_EB
},
25082 {"EL", no_argument
, NULL
, OPTION_EL
},
25084 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25085 {NULL
, no_argument
, NULL
, 0}
25089 size_t md_longopts_size
= sizeof (md_longopts
);
25091 struct arm_option_table
25093 const char *option
; /* Option name to match. */
25094 const char *help
; /* Help information. */
25095 int *var
; /* Variable to change. */
25096 int value
; /* What to change it to. */
25097 const char *deprecated
; /* If non-null, print this message. */
25100 struct arm_option_table arm_opts
[] =
25102 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25103 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25104 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25105 &support_interwork
, 1, NULL
},
25106 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25107 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25108 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25110 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25111 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25112 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25113 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25116 /* These are recognized by the assembler, but have no affect on code. */
25117 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25118 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25120 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25121 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25122 &warn_on_deprecated
, 0, NULL
},
25123 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25124 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25125 {NULL
, NULL
, NULL
, 0, NULL
}
25128 struct arm_legacy_option_table
25130 const char *option
; /* Option name to match. */
25131 const arm_feature_set
**var
; /* Variable to change. */
25132 const arm_feature_set value
; /* What to change it to. */
25133 const char *deprecated
; /* If non-null, print this message. */
25136 const struct arm_legacy_option_table arm_legacy_opts
[] =
25138 /* DON'T add any new processors to this list -- we want the whole list
25139 to go away... Add them to the processors table instead. */
25140 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25141 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25142 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25143 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25144 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25145 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25146 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25147 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25148 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25149 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25150 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25151 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25152 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25153 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25154 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25155 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25156 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25157 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25158 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25159 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25160 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25161 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25162 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25163 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25164 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25165 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25166 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25167 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25168 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25169 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25170 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25171 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25172 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25173 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25174 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25175 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25176 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25177 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25178 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25179 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25180 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25181 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25182 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25183 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25184 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25185 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25186 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25187 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25188 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25189 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25190 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25191 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25192 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25193 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25194 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25195 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25196 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25197 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25198 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25199 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25200 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25201 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25202 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25203 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25204 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25205 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25206 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25207 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25208 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25209 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25210 N_("use -mcpu=strongarm110")},
25211 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25212 N_("use -mcpu=strongarm1100")},
25213 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25214 N_("use -mcpu=strongarm1110")},
25215 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25216 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25217 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25219 /* Architecture variants -- don't add any more to this list either. */
25220 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25221 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25222 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25223 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25224 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25225 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25226 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25227 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25228 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25229 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25230 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25231 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25232 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25233 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25234 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25235 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25236 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25237 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25239 /* Floating point variants -- don't add any more to this list either. */
25240 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25241 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25242 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25243 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25244 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25246 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25249 struct arm_cpu_option_table
25253 const arm_feature_set value
;
25254 /* For some CPUs we assume an FPU unless the user explicitly sets
25256 const arm_feature_set default_fpu
;
25257 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25259 const char *canonical_name
;
25262 /* This list should, at a minimum, contain all the cpu names
25263 recognized by GCC. */
25264 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25265 static const struct arm_cpu_option_table arm_cpus
[] =
25267 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25268 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25269 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25270 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25271 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25272 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25273 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25274 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25275 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25276 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25277 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25278 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25279 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25280 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25281 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25282 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25283 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25284 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25285 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25286 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25287 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25288 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25289 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25290 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25291 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25292 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25293 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25294 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25295 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25296 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25297 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25298 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25299 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25300 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25301 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25302 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25303 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25304 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25305 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25306 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25307 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25308 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25309 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25310 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25311 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25312 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25313 /* For V5 or later processors we default to using VFP; but the user
25314 should really set the FPU type explicitly. */
25315 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25316 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25317 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25318 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25319 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25320 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25321 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25322 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25323 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25324 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25325 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25326 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25327 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25328 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25329 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25330 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25331 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25332 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25333 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25334 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25336 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25337 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25338 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25339 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25340 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25341 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25342 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25343 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25344 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25346 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25347 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25348 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25349 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25350 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25351 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25352 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25353 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25354 FPU_NONE
, "Cortex-A5"),
25355 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25357 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25358 ARM_FEATURE_COPROC (FPU_VFP_V3
25359 | FPU_NEON_EXT_V1
),
25361 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25362 ARM_FEATURE_COPROC (FPU_VFP_V3
25363 | FPU_NEON_EXT_V1
),
25365 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25367 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25369 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25371 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25373 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25375 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25377 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25379 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25381 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25383 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25384 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25386 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25387 FPU_NONE
, "Cortex-R5"),
25388 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25389 FPU_ARCH_VFP_V3D16
,
25391 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25392 FPU_ARCH_VFP_V3D16
,
25394 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25395 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25396 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25397 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25398 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25399 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25400 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25403 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25407 /* ??? XSCALE is really an architecture. */
25408 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25409 /* ??? iwmmxt is not a processor. */
25410 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25411 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25412 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25414 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25415 FPU_ARCH_MAVERICK
, "ARM920T"),
25416 /* Marvell processors. */
25417 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25419 ARM_EXT2_V6T2_V8M
),
25420 FPU_ARCH_VFP_V3D16
, NULL
),
25421 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25423 ARM_EXT2_V6T2_V8M
),
25424 FPU_ARCH_NEON_VFP_V4
, NULL
),
25425 /* APM X-Gene family. */
25426 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25428 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25431 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25435 struct arm_arch_option_table
25439 const arm_feature_set value
;
25440 const arm_feature_set default_fpu
;
25443 /* This list should, at a minimum, contain all the architecture names
25444 recognized by GCC. */
25445 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25446 static const struct arm_arch_option_table arm_archs
[] =
25448 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25449 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25450 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25451 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25452 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25453 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25454 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25455 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25456 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25457 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25458 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25459 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25460 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25461 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25462 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25463 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25464 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25465 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25466 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25467 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25468 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25469 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25470 kept to preserve existing behaviour. */
25471 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25472 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25473 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25474 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25475 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25476 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25477 kept to preserve existing behaviour. */
25478 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25479 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25480 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25481 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25482 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25483 /* The official spelling of the ARMv7 profile variants is the dashed form.
25484 Accept the non-dashed form for compatibility with old toolchains. */
25485 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25486 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25487 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25488 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25489 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25490 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25491 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25492 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25493 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25494 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25495 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25496 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25497 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25498 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25499 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25500 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25501 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25503 #undef ARM_ARCH_OPT
25505 /* ISA extensions in the co-processor and main instruction set space. */
25506 struct arm_option_extension_value_table
25510 const arm_feature_set merge_value
;
25511 const arm_feature_set clear_value
;
25512 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25513 indicates that an extension is available for all architectures while
25514 ARM_ANY marks an empty entry. */
25515 const arm_feature_set allowed_archs
[2];
25518 /* The following table must be in alphabetical order with a NULL last entry.
25520 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25521 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25522 static const struct arm_option_extension_value_table arm_extensions
[] =
25524 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25525 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25526 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25527 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25528 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25529 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25530 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25531 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25532 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25533 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25534 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25535 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25537 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25538 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25539 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25540 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25541 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25542 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25543 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25544 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25545 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25546 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25547 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25548 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25549 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25550 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25551 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25552 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25553 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25554 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25555 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25556 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25557 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25558 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25559 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25560 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25561 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25562 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25563 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25564 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25565 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25566 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25567 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25568 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25570 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25572 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25573 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25574 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25575 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25576 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25580 /* ISA floating-point and Advanced SIMD extensions. */
25581 struct arm_option_fpu_value_table
25584 const arm_feature_set value
;
25587 /* This list should, at a minimum, contain all the fpu names
25588 recognized by GCC. */
25589 static const struct arm_option_fpu_value_table arm_fpus
[] =
25591 {"softfpa", FPU_NONE
},
25592 {"fpe", FPU_ARCH_FPE
},
25593 {"fpe2", FPU_ARCH_FPE
},
25594 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25595 {"fpa", FPU_ARCH_FPA
},
25596 {"fpa10", FPU_ARCH_FPA
},
25597 {"fpa11", FPU_ARCH_FPA
},
25598 {"arm7500fe", FPU_ARCH_FPA
},
25599 {"softvfp", FPU_ARCH_VFP
},
25600 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25601 {"vfp", FPU_ARCH_VFP_V2
},
25602 {"vfp9", FPU_ARCH_VFP_V2
},
25603 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25604 {"vfp10", FPU_ARCH_VFP_V2
},
25605 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25606 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25607 {"vfpv2", FPU_ARCH_VFP_V2
},
25608 {"vfpv3", FPU_ARCH_VFP_V3
},
25609 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25610 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25611 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25612 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25613 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25614 {"arm1020t", FPU_ARCH_VFP_V1
},
25615 {"arm1020e", FPU_ARCH_VFP_V2
},
25616 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25617 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25618 {"maverick", FPU_ARCH_MAVERICK
},
25619 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25620 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25621 {"vfpv4", FPU_ARCH_VFP_V4
},
25622 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25623 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25624 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25625 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25626 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25627 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25628 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25629 {"crypto-neon-fp-armv8",
25630 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25631 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25632 {"crypto-neon-fp-armv8.1",
25633 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25634 {NULL
, ARM_ARCH_NONE
}
25637 struct arm_option_value_table
25643 static const struct arm_option_value_table arm_float_abis
[] =
25645 {"hard", ARM_FLOAT_ABI_HARD
},
25646 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25647 {"soft", ARM_FLOAT_ABI_SOFT
},
25652 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25653 static const struct arm_option_value_table arm_eabis
[] =
25655 {"gnu", EF_ARM_EABI_UNKNOWN
},
25656 {"4", EF_ARM_EABI_VER4
},
25657 {"5", EF_ARM_EABI_VER5
},
25662 struct arm_long_option_table
25664 const char * option
; /* Substring to match. */
25665 const char * help
; /* Help information. */
25666 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25667 const char * deprecated
; /* If non-null, print this message. */
25671 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25673 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25675 /* We insist on extensions being specified in alphabetical order, and with
25676 extensions being added before being removed. We achieve this by having
25677 the global ARM_EXTENSIONS table in alphabetical order, and using the
25678 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25679 or removing it (0) and only allowing it to change in the order
25681 const struct arm_option_extension_value_table
* opt
= NULL
;
25682 const arm_feature_set arm_any
= ARM_ANY
;
25683 int adding_value
= -1;
25685 /* Copy the feature set, so that we can modify it. */
25686 *ext_set
= **opt_p
;
25689 while (str
!= NULL
&& *str
!= 0)
25696 as_bad (_("invalid architectural extension"));
25701 ext
= strchr (str
, '+');
25706 len
= strlen (str
);
25708 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25710 if (adding_value
!= 0)
25713 opt
= arm_extensions
;
25721 if (adding_value
== -1)
25724 opt
= arm_extensions
;
25726 else if (adding_value
!= 1)
25728 as_bad (_("must specify extensions to add before specifying "
25729 "those to remove"));
25736 as_bad (_("missing architectural extension"));
25740 gas_assert (adding_value
!= -1);
25741 gas_assert (opt
!= NULL
);
25743 /* Scan over the options table trying to find an exact match. */
25744 for (; opt
->name
!= NULL
; opt
++)
25745 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25747 int i
, nb_allowed_archs
=
25748 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25749 /* Check we can apply the extension to this architecture. */
25750 for (i
= 0; i
< nb_allowed_archs
; i
++)
25753 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25755 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25758 if (i
== nb_allowed_archs
)
25760 as_bad (_("extension does not apply to the base architecture"));
25764 /* Add or remove the extension. */
25766 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25768 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25773 if (opt
->name
== NULL
)
25775 /* Did we fail to find an extension because it wasn't specified in
25776 alphabetical order, or because it does not exist? */
25778 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25779 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25782 if (opt
->name
== NULL
)
25783 as_bad (_("unknown architectural extension `%s'"), str
);
25785 as_bad (_("architectural extensions must be specified in "
25786 "alphabetical order"));
25792 /* We should skip the extension we've just matched the next time
25804 arm_parse_cpu (const char *str
)
25806 const struct arm_cpu_option_table
*opt
;
25807 const char *ext
= strchr (str
, '+');
25813 len
= strlen (str
);
25817 as_bad (_("missing cpu name `%s'"), str
);
25821 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25822 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25824 mcpu_cpu_opt
= &opt
->value
;
25825 mcpu_fpu_opt
= &opt
->default_fpu
;
25826 if (opt
->canonical_name
)
25828 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25829 strcpy (selected_cpu_name
, opt
->canonical_name
);
25835 if (len
>= sizeof selected_cpu_name
)
25836 len
= (sizeof selected_cpu_name
) - 1;
25838 for (i
= 0; i
< len
; i
++)
25839 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25840 selected_cpu_name
[i
] = 0;
25844 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25849 as_bad (_("unknown cpu `%s'"), str
);
25854 arm_parse_arch (const char *str
)
25856 const struct arm_arch_option_table
*opt
;
25857 const char *ext
= strchr (str
, '+');
25863 len
= strlen (str
);
25867 as_bad (_("missing architecture name `%s'"), str
);
25871 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25872 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25874 march_cpu_opt
= &opt
->value
;
25875 march_fpu_opt
= &opt
->default_fpu
;
25876 strcpy (selected_cpu_name
, opt
->name
);
25879 return arm_parse_extension (ext
, &march_cpu_opt
);
25884 as_bad (_("unknown architecture `%s'\n"), str
);
25889 arm_parse_fpu (const char * str
)
25891 const struct arm_option_fpu_value_table
* opt
;
25893 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25894 if (streq (opt
->name
, str
))
25896 mfpu_opt
= &opt
->value
;
25900 as_bad (_("unknown floating point format `%s'\n"), str
);
25905 arm_parse_float_abi (const char * str
)
25907 const struct arm_option_value_table
* opt
;
25909 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25910 if (streq (opt
->name
, str
))
25912 mfloat_abi_opt
= opt
->value
;
25916 as_bad (_("unknown floating point abi `%s'\n"), str
);
25922 arm_parse_eabi (const char * str
)
25924 const struct arm_option_value_table
*opt
;
25926 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25927 if (streq (opt
->name
, str
))
25929 meabi_flags
= opt
->value
;
25932 as_bad (_("unknown EABI `%s'\n"), str
);
25938 arm_parse_it_mode (const char * str
)
25940 bfd_boolean ret
= TRUE
;
25942 if (streq ("arm", str
))
25943 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25944 else if (streq ("thumb", str
))
25945 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25946 else if (streq ("always", str
))
25947 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25948 else if (streq ("never", str
))
25949 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25952 as_bad (_("unknown implicit IT mode `%s', should be "\
25953 "arm, thumb, always, or never."), str
);
25961 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25963 codecomposer_syntax
= TRUE
;
25964 arm_comment_chars
[0] = ';';
25965 arm_line_separator_chars
[0] = 0;
25969 struct arm_long_option_table arm_long_opts
[] =
25971 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25972 arm_parse_cpu
, NULL
},
25973 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25974 arm_parse_arch
, NULL
},
25975 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25976 arm_parse_fpu
, NULL
},
25977 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25978 arm_parse_float_abi
, NULL
},
25980 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25981 arm_parse_eabi
, NULL
},
25983 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25984 arm_parse_it_mode
, NULL
},
25985 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25986 arm_ccs_mode
, NULL
},
25987 {NULL
, NULL
, 0, NULL
}
25991 md_parse_option (int c
, const char * arg
)
25993 struct arm_option_table
*opt
;
25994 const struct arm_legacy_option_table
*fopt
;
25995 struct arm_long_option_table
*lopt
;
26001 target_big_endian
= 1;
26007 target_big_endian
= 0;
26011 case OPTION_FIX_V4BX
:
26016 /* Listing option. Just ignore these, we don't support additional
26021 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26023 if (c
== opt
->option
[0]
26024 && ((arg
== NULL
&& opt
->option
[1] == 0)
26025 || streq (arg
, opt
->option
+ 1)))
26027 /* If the option is deprecated, tell the user. */
26028 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26029 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26030 arg
? arg
: "", _(opt
->deprecated
));
26032 if (opt
->var
!= NULL
)
26033 *opt
->var
= opt
->value
;
26039 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26041 if (c
== fopt
->option
[0]
26042 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26043 || streq (arg
, fopt
->option
+ 1)))
26045 /* If the option is deprecated, tell the user. */
26046 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26047 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26048 arg
? arg
: "", _(fopt
->deprecated
));
26050 if (fopt
->var
!= NULL
)
26051 *fopt
->var
= &fopt
->value
;
26057 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26059 /* These options are expected to have an argument. */
26060 if (c
== lopt
->option
[0]
26062 && strncmp (arg
, lopt
->option
+ 1,
26063 strlen (lopt
->option
+ 1)) == 0)
26065 /* If the option is deprecated, tell the user. */
26066 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26067 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26068 _(lopt
->deprecated
));
26070 /* Call the sup-option parser. */
26071 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26082 md_show_usage (FILE * fp
)
26084 struct arm_option_table
*opt
;
26085 struct arm_long_option_table
*lopt
;
26087 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26089 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26090 if (opt
->help
!= NULL
)
26091 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26093 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26094 if (lopt
->help
!= NULL
)
26095 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26099 -EB assemble code for a big-endian cpu\n"));
26104 -EL assemble code for a little-endian cpu\n"));
26108 --fix-v4bx Allow BX in ARMv4 code\n"));
26116 arm_feature_set flags
;
26117 } cpu_arch_ver_table
;
26119 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26120 must be sorted least features first but some reordering is needed, eg. for
26121 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26122 static const cpu_arch_ver_table cpu_arch_ver
[] =
26128 {4, ARM_ARCH_V5TE
},
26129 {5, ARM_ARCH_V5TEJ
},
26133 {11, ARM_ARCH_V6M
},
26134 {12, ARM_ARCH_V6SM
},
26135 {8, ARM_ARCH_V6T2
},
26136 {10, ARM_ARCH_V7VE
},
26137 {10, ARM_ARCH_V7R
},
26138 {10, ARM_ARCH_V7M
},
26139 {14, ARM_ARCH_V8A
},
26140 {16, ARM_ARCH_V8M_BASE
},
26141 {17, ARM_ARCH_V8M_MAIN
},
26145 /* Set an attribute if it has not already been set by the user. */
26147 aeabi_set_attribute_int (int tag
, int value
)
26150 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26151 || !attributes_set_explicitly
[tag
])
26152 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26156 aeabi_set_attribute_string (int tag
, const char *value
)
26159 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26160 || !attributes_set_explicitly
[tag
])
26161 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26164 /* Set the public EABI object attributes. */
26166 aeabi_set_public_attributes (void)
26171 int fp16_optional
= 0;
26172 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26173 arm_feature_set flags
;
26174 arm_feature_set tmp
;
26175 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26176 const cpu_arch_ver_table
*p
;
26178 /* Choose the architecture based on the capabilities of the requested cpu
26179 (if any) and/or the instructions actually used. */
26180 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26181 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26182 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26184 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26185 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26187 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26188 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26190 selected_cpu
= flags
;
26192 /* Allow the user to override the reported architecture. */
26195 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26196 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26199 /* We need to make sure that the attributes do not identify us as v6S-M
26200 when the only v6S-M feature in use is the Operating System Extensions. */
26201 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26202 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26203 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26207 for (p
= cpu_arch_ver
; p
->val
; p
++)
26209 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26212 arm_arch
= p
->flags
;
26213 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26217 /* The table lookup above finds the last architecture to contribute
26218 a new feature. Unfortunately, Tag13 is a subset of the union of
26219 v6T2 and v7-M, so it is never seen as contributing a new feature.
26220 We can not search for the last entry which is entirely used,
26221 because if no CPU is specified we build up only those flags
26222 actually used. Perhaps we should separate out the specified
26223 and implicit cases. Avoid taking this path for -march=all by
26224 checking for contradictory v7-A / v7-M features. */
26225 if (arch
== TAG_CPU_ARCH_V7
26226 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26227 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26228 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26230 arch
= TAG_CPU_ARCH_V7E_M
;
26231 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26234 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26235 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26237 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26238 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26241 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26242 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26243 ARMv8-M, -march=all must be detected as ARMv8-A. */
26244 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26245 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26247 arch
= TAG_CPU_ARCH_V8
;
26248 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26251 /* Tag_CPU_name. */
26252 if (selected_cpu_name
[0])
26256 q
= selected_cpu_name
;
26257 if (strncmp (q
, "armv", 4) == 0)
26262 for (i
= 0; q
[i
]; i
++)
26263 q
[i
] = TOUPPER (q
[i
]);
26265 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26268 /* Tag_CPU_arch. */
26269 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26271 /* Tag_CPU_arch_profile. */
26272 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26273 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26274 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26275 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26277 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26279 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26284 if (profile
!= '\0')
26285 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26287 /* Tag_DSP_extension. */
26288 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26290 arm_feature_set ext
;
26292 /* DSP instructions not in architecture. */
26293 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26294 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26295 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26298 /* Tag_ARM_ISA_use. */
26299 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26301 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26303 /* Tag_THUMB_ISA_use. */
26304 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26309 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26310 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26312 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26316 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26319 /* Tag_VFP_arch. */
26320 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26321 aeabi_set_attribute_int (Tag_VFP_arch
,
26322 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26324 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26325 aeabi_set_attribute_int (Tag_VFP_arch
,
26326 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26328 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26331 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26333 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26335 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26338 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26339 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26340 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26341 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26342 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26344 /* Tag_ABI_HardFP_use. */
26345 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26346 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26347 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26349 /* Tag_WMMX_arch. */
26350 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26351 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26352 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26353 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26355 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26356 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26357 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26358 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26359 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26360 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26362 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26364 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26368 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26373 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26374 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26375 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26379 We set Tag_DIV_use to two when integer divide instructions have been used
26380 in ARM state, or when Thumb integer divide instructions have been used,
26381 but we have no architecture profile set, nor have we any ARM instructions.
26383 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26384 by the base architecture.
26386 For new architectures we will have to check these tests. */
26387 gas_assert (arch
<= TAG_CPU_ARCH_V8
26388 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26389 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26390 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26391 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26392 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26393 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26394 || (profile
== '\0'
26395 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26396 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26397 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26399 /* Tag_MP_extension_use. */
26400 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26401 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26403 /* Tag Virtualization_use. */
26404 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26406 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26409 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26412 /* Add the default contents for the .ARM.attributes section. */
26416 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26419 aeabi_set_public_attributes ();
26421 #endif /* OBJ_ELF */
26424 /* Parse a .cpu directive. */
26427 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26429 const struct arm_cpu_option_table
*opt
;
26433 name
= input_line_pointer
;
26434 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26435 input_line_pointer
++;
26436 saved_char
= *input_line_pointer
;
26437 *input_line_pointer
= 0;
26439 /* Skip the first "all" entry. */
26440 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26441 if (streq (opt
->name
, name
))
26443 mcpu_cpu_opt
= &opt
->value
;
26444 selected_cpu
= opt
->value
;
26445 if (opt
->canonical_name
)
26446 strcpy (selected_cpu_name
, opt
->canonical_name
);
26450 for (i
= 0; opt
->name
[i
]; i
++)
26451 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26453 selected_cpu_name
[i
] = 0;
26455 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26456 *input_line_pointer
= saved_char
;
26457 demand_empty_rest_of_line ();
26460 as_bad (_("unknown cpu `%s'"), name
);
26461 *input_line_pointer
= saved_char
;
26462 ignore_rest_of_line ();
26466 /* Parse a .arch directive. */
26469 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26471 const struct arm_arch_option_table
*opt
;
26475 name
= input_line_pointer
;
26476 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26477 input_line_pointer
++;
26478 saved_char
= *input_line_pointer
;
26479 *input_line_pointer
= 0;
26481 /* Skip the first "all" entry. */
26482 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26483 if (streq (opt
->name
, name
))
26485 mcpu_cpu_opt
= &opt
->value
;
26486 selected_cpu
= opt
->value
;
26487 strcpy (selected_cpu_name
, opt
->name
);
26488 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26489 *input_line_pointer
= saved_char
;
26490 demand_empty_rest_of_line ();
26494 as_bad (_("unknown architecture `%s'\n"), name
);
26495 *input_line_pointer
= saved_char
;
26496 ignore_rest_of_line ();
26500 /* Parse a .object_arch directive. */
26503 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26505 const struct arm_arch_option_table
*opt
;
26509 name
= input_line_pointer
;
26510 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26511 input_line_pointer
++;
26512 saved_char
= *input_line_pointer
;
26513 *input_line_pointer
= 0;
26515 /* Skip the first "all" entry. */
26516 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26517 if (streq (opt
->name
, name
))
26519 object_arch
= &opt
->value
;
26520 *input_line_pointer
= saved_char
;
26521 demand_empty_rest_of_line ();
26525 as_bad (_("unknown architecture `%s'\n"), name
);
26526 *input_line_pointer
= saved_char
;
26527 ignore_rest_of_line ();
26530 /* Parse a .arch_extension directive. */
26533 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26535 const struct arm_option_extension_value_table
*opt
;
26536 const arm_feature_set arm_any
= ARM_ANY
;
26539 int adding_value
= 1;
26541 name
= input_line_pointer
;
26542 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26543 input_line_pointer
++;
26544 saved_char
= *input_line_pointer
;
26545 *input_line_pointer
= 0;
26547 if (strlen (name
) >= 2
26548 && strncmp (name
, "no", 2) == 0)
26554 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26555 if (streq (opt
->name
, name
))
26557 int i
, nb_allowed_archs
=
26558 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26559 for (i
= 0; i
< nb_allowed_archs
; i
++)
26562 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26564 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26568 if (i
== nb_allowed_archs
)
26570 as_bad (_("architectural extension `%s' is not allowed for the "
26571 "current base architecture"), name
);
26576 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26579 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26581 mcpu_cpu_opt
= &selected_cpu
;
26582 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26583 *input_line_pointer
= saved_char
;
26584 demand_empty_rest_of_line ();
26588 if (opt
->name
== NULL
)
26589 as_bad (_("unknown architecture extension `%s'\n"), name
);
26591 *input_line_pointer
= saved_char
;
26592 ignore_rest_of_line ();
26595 /* Parse a .fpu directive. */
26598 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26600 const struct arm_option_fpu_value_table
*opt
;
26604 name
= input_line_pointer
;
26605 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26606 input_line_pointer
++;
26607 saved_char
= *input_line_pointer
;
26608 *input_line_pointer
= 0;
26610 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26611 if (streq (opt
->name
, name
))
26613 mfpu_opt
= &opt
->value
;
26614 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26615 *input_line_pointer
= saved_char
;
26616 demand_empty_rest_of_line ();
26620 as_bad (_("unknown floating point format `%s'\n"), name
);
26621 *input_line_pointer
= saved_char
;
26622 ignore_rest_of_line ();
26625 /* Copy symbol information. */
26628 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26630 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26634 /* Given a symbolic attribute NAME, return the proper integer value.
26635 Returns -1 if the attribute is not known. */
26638 arm_convert_symbolic_attribute (const char *name
)
26640 static const struct
26645 attribute_table
[] =
26647 /* When you modify this table you should
26648 also modify the list in doc/c-arm.texi. */
26649 #define T(tag) {#tag, tag}
26650 T (Tag_CPU_raw_name
),
26653 T (Tag_CPU_arch_profile
),
26654 T (Tag_ARM_ISA_use
),
26655 T (Tag_THUMB_ISA_use
),
26659 T (Tag_Advanced_SIMD_arch
),
26660 T (Tag_PCS_config
),
26661 T (Tag_ABI_PCS_R9_use
),
26662 T (Tag_ABI_PCS_RW_data
),
26663 T (Tag_ABI_PCS_RO_data
),
26664 T (Tag_ABI_PCS_GOT_use
),
26665 T (Tag_ABI_PCS_wchar_t
),
26666 T (Tag_ABI_FP_rounding
),
26667 T (Tag_ABI_FP_denormal
),
26668 T (Tag_ABI_FP_exceptions
),
26669 T (Tag_ABI_FP_user_exceptions
),
26670 T (Tag_ABI_FP_number_model
),
26671 T (Tag_ABI_align_needed
),
26672 T (Tag_ABI_align8_needed
),
26673 T (Tag_ABI_align_preserved
),
26674 T (Tag_ABI_align8_preserved
),
26675 T (Tag_ABI_enum_size
),
26676 T (Tag_ABI_HardFP_use
),
26677 T (Tag_ABI_VFP_args
),
26678 T (Tag_ABI_WMMX_args
),
26679 T (Tag_ABI_optimization_goals
),
26680 T (Tag_ABI_FP_optimization_goals
),
26681 T (Tag_compatibility
),
26682 T (Tag_CPU_unaligned_access
),
26683 T (Tag_FP_HP_extension
),
26684 T (Tag_VFP_HP_extension
),
26685 T (Tag_ABI_FP_16bit_format
),
26686 T (Tag_MPextension_use
),
26688 T (Tag_nodefaults
),
26689 T (Tag_also_compatible_with
),
26690 T (Tag_conformance
),
26692 T (Tag_Virtualization_use
),
26693 T (Tag_DSP_extension
),
26694 /* We deliberately do not include Tag_MPextension_use_legacy. */
26702 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26703 if (streq (name
, attribute_table
[i
].name
))
26704 return attribute_table
[i
].tag
;
26710 /* Apply sym value for relocations only in the case that they are for
26711 local symbols in the same segment as the fixup and you have the
26712 respective architectural feature for blx and simple switches. */
26714 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26717 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26718 /* PR 17444: If the local symbol is in a different section then a reloc
26719 will always be generated for it, so applying the symbol value now
26720 will result in a double offset being stored in the relocation. */
26721 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26722 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26724 switch (fixP
->fx_r_type
)
26726 case BFD_RELOC_ARM_PCREL_BLX
:
26727 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26728 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26732 case BFD_RELOC_ARM_PCREL_CALL
:
26733 case BFD_RELOC_THUMB_PCREL_BLX
:
26734 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26745 #endif /* OBJ_ELF */