1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
306 static const arm_feature_set fpu_vfp_fp16
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
308 static const arm_feature_set fpu_neon_ext_fma
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
311 static const arm_feature_set fpu_vfp_ext_fma
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
313 static const arm_feature_set fpu_vfp_ext_armv8
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
315 static const arm_feature_set fpu_vfp_ext_armv8xd
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
317 static const arm_feature_set fpu_neon_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
319 static const arm_feature_set fpu_crypto_ext_armv8
=
320 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
321 static const arm_feature_set crc_ext_armv8
=
322 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
323 static const arm_feature_set fpu_neon_ext_v8_1
=
324 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
325 static const arm_feature_set fpu_neon_ext_dotprod
=
326 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
328 static int mfloat_abi_opt
= -1;
329 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
331 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
332 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
334 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
335 /* Feature bits selected by the last -mcpu/-march or by the combination of the
336 last .cpu/.arch directive .arch_extension directives since that
338 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
339 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
340 static arm_feature_set selected_fpu
= FPU_NONE
;
341 /* Feature bits selected by the last .object_arch directive. */
342 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
343 /* Must be long enough to hold any of the names in arm_cpus. */
344 static char selected_cpu_name
[20];
346 extern FLONUM_TYPE generic_floating_point_number
;
348 /* Return if no cpu was selected on command-line. */
350 no_cpu_selected (void)
352 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
357 static int meabi_flags
= EABI_DEFAULT
;
359 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
362 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
367 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
372 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
373 symbolS
* GOT_symbol
;
376 /* 0: assemble for ARM,
377 1: assemble for Thumb,
378 2: assemble for Thumb even though target CPU does not support thumb
380 static int thumb_mode
= 0;
381 /* A value distinct from the possible values for thumb_mode that we
382 can use to record whether thumb_mode has been copied into the
383 tc_frag_data field of a frag. */
384 #define MODE_RECORDED (1 << 4)
386 /* Specifies the intrinsic IT insn behavior mode. */
387 enum implicit_it_mode
389 IMPLICIT_IT_MODE_NEVER
= 0x00,
390 IMPLICIT_IT_MODE_ARM
= 0x01,
391 IMPLICIT_IT_MODE_THUMB
= 0x02,
392 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
394 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
396 /* If unified_syntax is true, we are processing the new unified
397 ARM/Thumb syntax. Important differences from the old ARM mode:
399 - Immediate operands do not require a # prefix.
400 - Conditional affixes always appear at the end of the
401 instruction. (For backward compatibility, those instructions
402 that formerly had them in the middle, continue to accept them
404 - The IT instruction may appear, and if it does is validated
405 against subsequent conditional affixes. It does not generate
408 Important differences from the old Thumb mode:
410 - Immediate operands do not require a # prefix.
411 - Most of the V6T2 instructions are only available in unified mode.
412 - The .N and .W suffixes are recognized and honored (it is an error
413 if they cannot be honored).
414 - All instructions set the flags if and only if they have an 's' affix.
415 - Conditional affixes may be used. They are validated against
416 preceding IT instructions. Unlike ARM mode, you cannot use a
417 conditional affix except in the scope of an IT instruction. */
419 static bfd_boolean unified_syntax
= FALSE
;
421 /* An immediate operand can start with #, and ld*, st*, pld operands
422 can contain [ and ]. We need to tell APP not to elide whitespace
423 before a [, which can appear as the first operand for pld.
424 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
425 const char arm_symbol_chars
[] = "#[]{}";
440 enum neon_el_type type
;
444 #define NEON_MAX_TYPE_ELS 4
448 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
452 enum it_instruction_type
457 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
458 if inside, should be the last one. */
459 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
460 i.e. BKPT and NOP. */
461 IT_INSN
/* The IT insn has been parsed. */
464 /* The maximum number of operands we need. */
465 #define ARM_IT_MAX_OPERANDS 6
466 #define ARM_IT_MAX_RELOCS 3
471 unsigned long instruction
;
475 /* "uncond_value" is set to the value in place of the conditional field in
476 unconditional versions of the instruction, or -1 if nothing is
479 struct neon_type vectype
;
480 /* This does not indicate an actual NEON instruction, only that
481 the mnemonic accepts neon-style type suffixes. */
483 /* Set to the opcode if the instruction needs relaxation.
484 Zero if the instruction is not relaxed. */
488 bfd_reloc_code_real_type type
;
491 } relocs
[ARM_IT_MAX_RELOCS
];
493 enum it_instruction_type it_insn_type
;
499 struct neon_type_el vectype
;
500 unsigned present
: 1; /* Operand present. */
501 unsigned isreg
: 1; /* Operand was a register. */
502 unsigned immisreg
: 1; /* .imm field is a second register. */
503 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
504 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
505 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
506 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
507 instructions. This allows us to disambiguate ARM <-> vector insns. */
508 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
509 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
510 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
511 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
512 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
513 unsigned writeback
: 1; /* Operand has trailing ! */
514 unsigned preind
: 1; /* Preindexed address. */
515 unsigned postind
: 1; /* Postindexed address. */
516 unsigned negative
: 1; /* Index register was negated. */
517 unsigned shifted
: 1; /* Shift applied to operation. */
518 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
519 } operands
[ARM_IT_MAX_OPERANDS
];
522 static struct arm_it inst
;
524 #define NUM_FLOAT_VALS 8
526 const char * fp_const
[] =
528 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
531 /* Number of littlenums required to hold an extended precision number. */
532 #define MAX_LITTLENUMS 6
534 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
544 #define CP_T_X 0x00008000
545 #define CP_T_Y 0x00400000
547 #define CONDS_BIT 0x00100000
548 #define LOAD_BIT 0x00100000
550 #define DOUBLE_LOAD_FLAG 0x00000001
554 const char * template_name
;
558 #define COND_ALWAYS 0xE
562 const char * template_name
;
566 struct asm_barrier_opt
568 const char * template_name
;
570 const arm_feature_set arch
;
573 /* The bit that distinguishes CPSR and SPSR. */
574 #define SPSR_BIT (1 << 22)
576 /* The individual PSR flag bits. */
577 #define PSR_c (1 << 16)
578 #define PSR_x (1 << 17)
579 #define PSR_s (1 << 18)
580 #define PSR_f (1 << 19)
585 bfd_reloc_code_real_type reloc
;
590 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
591 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
596 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
599 /* Bits for DEFINED field in neon_typed_alias. */
600 #define NTA_HASTYPE 1
601 #define NTA_HASINDEX 2
603 struct neon_typed_alias
605 unsigned char defined
;
607 struct neon_type_el eltype
;
610 /* ARM register categories. This includes coprocessor numbers and various
611 architecture extensions' registers. Each entry should have an error message
612 in reg_expected_msgs below. */
640 /* Structure for a hash table entry for a register.
641 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
642 information which states whether a vector type or index is specified (for a
643 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
649 unsigned char builtin
;
650 struct neon_typed_alias
* neon
;
653 /* Diagnostics used when we don't get a register of the expected type. */
654 const char * const reg_expected_msgs
[] =
656 [REG_TYPE_RN
] = N_("ARM register expected"),
657 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
658 [REG_TYPE_CN
] = N_("co-processor register expected"),
659 [REG_TYPE_FN
] = N_("FPA register expected"),
660 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
661 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
662 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
663 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
664 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
665 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
666 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
668 [REG_TYPE_VFC
] = N_("VFP system register expected"),
669 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
670 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
671 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
672 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
673 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
674 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
675 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
676 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
677 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
678 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
679 [REG_TYPE_RNB
] = N_("")
682 /* Some well known registers that we refer to directly elsewhere. */
688 /* ARM instructions take 4bytes in the object file, Thumb instructions
694 /* Basic string to match. */
695 const char * template_name
;
697 /* Parameters to instruction. */
698 unsigned int operands
[8];
700 /* Conditional tag - see opcode_lookup. */
701 unsigned int tag
: 4;
703 /* Basic instruction code. */
704 unsigned int avalue
: 28;
706 /* Thumb-format instruction code. */
709 /* Which architecture variant provides this instruction. */
710 const arm_feature_set
* avariant
;
711 const arm_feature_set
* tvariant
;
713 /* Function to call to encode instruction in ARM format. */
714 void (* aencode
) (void);
716 /* Function to call to encode instruction in Thumb format. */
717 void (* tencode
) (void);
720 /* Defines for various bits that we will want to toggle. */
721 #define INST_IMMEDIATE 0x02000000
722 #define OFFSET_REG 0x02000000
723 #define HWOFFSET_IMM 0x00400000
724 #define SHIFT_BY_REG 0x00000010
725 #define PRE_INDEX 0x01000000
726 #define INDEX_UP 0x00800000
727 #define WRITE_BACK 0x00200000
728 #define LDM_TYPE_2_OR_3 0x00400000
729 #define CPSI_MMOD 0x00020000
731 #define LITERAL_MASK 0xf000f000
732 #define OPCODE_MASK 0xfe1fffff
733 #define V4_STR_BIT 0x00000020
734 #define VLDR_VMOV_SAME 0x0040f000
736 #define T2_SUBS_PC_LR 0xf3de8f00
738 #define DATA_OP_SHIFT 21
739 #define SBIT_SHIFT 20
741 #define T2_OPCODE_MASK 0xfe1fffff
742 #define T2_DATA_OP_SHIFT 21
743 #define T2_SBIT_SHIFT 20
745 #define A_COND_MASK 0xf0000000
746 #define A_PUSH_POP_OP_MASK 0x0fff0000
748 /* Opcodes for pushing/poping registers to/from the stack. */
749 #define A1_OPCODE_PUSH 0x092d0000
750 #define A2_OPCODE_PUSH 0x052d0004
751 #define A2_OPCODE_POP 0x049d0004
753 /* Codes to distinguish the arithmetic instructions. */
764 #define OPCODE_CMP 10
765 #define OPCODE_CMN 11
766 #define OPCODE_ORR 12
767 #define OPCODE_MOV 13
768 #define OPCODE_BIC 14
769 #define OPCODE_MVN 15
771 #define T2_OPCODE_AND 0
772 #define T2_OPCODE_BIC 1
773 #define T2_OPCODE_ORR 2
774 #define T2_OPCODE_ORN 3
775 #define T2_OPCODE_EOR 4
776 #define T2_OPCODE_ADD 8
777 #define T2_OPCODE_ADC 10
778 #define T2_OPCODE_SBC 11
779 #define T2_OPCODE_SUB 13
780 #define T2_OPCODE_RSB 14
782 #define T_OPCODE_MUL 0x4340
783 #define T_OPCODE_TST 0x4200
784 #define T_OPCODE_CMN 0x42c0
785 #define T_OPCODE_NEG 0x4240
786 #define T_OPCODE_MVN 0x43c0
788 #define T_OPCODE_ADD_R3 0x1800
789 #define T_OPCODE_SUB_R3 0x1a00
790 #define T_OPCODE_ADD_HI 0x4400
791 #define T_OPCODE_ADD_ST 0xb000
792 #define T_OPCODE_SUB_ST 0xb080
793 #define T_OPCODE_ADD_SP 0xa800
794 #define T_OPCODE_ADD_PC 0xa000
795 #define T_OPCODE_ADD_I8 0x3000
796 #define T_OPCODE_SUB_I8 0x3800
797 #define T_OPCODE_ADD_I3 0x1c00
798 #define T_OPCODE_SUB_I3 0x1e00
800 #define T_OPCODE_ASR_R 0x4100
801 #define T_OPCODE_LSL_R 0x4080
802 #define T_OPCODE_LSR_R 0x40c0
803 #define T_OPCODE_ROR_R 0x41c0
804 #define T_OPCODE_ASR_I 0x1000
805 #define T_OPCODE_LSL_I 0x0000
806 #define T_OPCODE_LSR_I 0x0800
808 #define T_OPCODE_MOV_I8 0x2000
809 #define T_OPCODE_CMP_I8 0x2800
810 #define T_OPCODE_CMP_LR 0x4280
811 #define T_OPCODE_MOV_HR 0x4600
812 #define T_OPCODE_CMP_HR 0x4500
814 #define T_OPCODE_LDR_PC 0x4800
815 #define T_OPCODE_LDR_SP 0x9800
816 #define T_OPCODE_STR_SP 0x9000
817 #define T_OPCODE_LDR_IW 0x6800
818 #define T_OPCODE_STR_IW 0x6000
819 #define T_OPCODE_LDR_IH 0x8800
820 #define T_OPCODE_STR_IH 0x8000
821 #define T_OPCODE_LDR_IB 0x7800
822 #define T_OPCODE_STR_IB 0x7000
823 #define T_OPCODE_LDR_RW 0x5800
824 #define T_OPCODE_STR_RW 0x5000
825 #define T_OPCODE_LDR_RH 0x5a00
826 #define T_OPCODE_STR_RH 0x5200
827 #define T_OPCODE_LDR_RB 0x5c00
828 #define T_OPCODE_STR_RB 0x5400
830 #define T_OPCODE_PUSH 0xb400
831 #define T_OPCODE_POP 0xbc00
833 #define T_OPCODE_BRANCH 0xe000
835 #define THUMB_SIZE 2 /* Size of thumb instruction. */
836 #define THUMB_PP_PC_LR 0x0100
837 #define THUMB_LOAD_BIT 0x0800
838 #define THUMB2_LOAD_BIT 0x00100000
840 #define BAD_ARGS _("bad arguments to instruction")
841 #define BAD_SP _("r13 not allowed here")
842 #define BAD_PC _("r15 not allowed here")
843 #define BAD_COND _("instruction cannot be conditional")
844 #define BAD_OVERLAP _("registers may not be the same")
845 #define BAD_HIREG _("lo register required")
846 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
847 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
848 #define BAD_BRANCH _("branch must be last instruction in IT block")
849 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
850 #define BAD_NOT_IT _("instruction not allowed in IT block")
851 #define BAD_FPU _("selected FPU does not support instruction")
852 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
853 #define BAD_IT_COND _("incorrect condition in IT block")
854 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
855 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
856 #define BAD_PC_ADDRESSING \
857 _("cannot use register index with PC-relative addressing")
858 #define BAD_PC_WRITEBACK \
859 _("cannot use writeback with PC-relative addressing")
860 #define BAD_RANGE _("branch out of range")
861 #define BAD_FP16 _("selected processor does not support fp16 instruction")
862 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
863 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
865 static struct hash_control
* arm_ops_hsh
;
866 static struct hash_control
* arm_cond_hsh
;
867 static struct hash_control
* arm_shift_hsh
;
868 static struct hash_control
* arm_psr_hsh
;
869 static struct hash_control
* arm_v7m_psr_hsh
;
870 static struct hash_control
* arm_reg_hsh
;
871 static struct hash_control
* arm_reloc_hsh
;
872 static struct hash_control
* arm_barrier_opt_hsh
;
874 /* Stuff needed to resolve the label ambiguity
883 symbolS
* last_label_seen
;
884 static int label_is_thumb_function_name
= FALSE
;
886 /* Literal pool structure. Held on a per-section
887 and per-sub-section basis. */
889 #define MAX_LITERAL_POOL_SIZE 1024
890 typedef struct literal_pool
892 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
893 unsigned int next_free_entry
;
899 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
901 struct literal_pool
* next
;
902 unsigned int alignment
;
905 /* Pointer to a linked list of literal pools. */
906 literal_pool
* list_of_pools
= NULL
;
908 typedef enum asmfunc_states
911 WAITING_ASMFUNC_NAME
,
915 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
918 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
920 static struct current_it now_it
;
924 now_it_compatible (int cond
)
926 return (cond
& ~1) == (now_it
.cc
& ~1);
930 conditional_insn (void)
932 return inst
.cond
!= COND_ALWAYS
;
935 static int in_it_block (void);
937 static int handle_it_state (void);
939 static void force_automatic_it_block_close (void);
941 static void it_fsm_post_encode (void);
943 #define set_it_insn_type(type) \
946 inst.it_insn_type = type; \
947 if (handle_it_state () == FAIL) \
952 #define set_it_insn_type_nonvoid(type, failret) \
955 inst.it_insn_type = type; \
956 if (handle_it_state () == FAIL) \
961 #define set_it_insn_type_last() \
964 if (inst.cond == COND_ALWAYS) \
965 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
967 set_it_insn_type (INSIDE_IT_LAST_INSN); \
973 /* This array holds the chars that always start a comment. If the
974 pre-processor is disabled, these aren't very useful. */
975 char arm_comment_chars
[] = "@";
977 /* This array holds the chars that only start a comment at the beginning of
978 a line. If the line seems to have the form '# 123 filename'
979 .line and .file directives will appear in the pre-processed output. */
980 /* Note that input_file.c hand checks for '#' at the beginning of the
981 first line of the input file. This is because the compiler outputs
982 #NO_APP at the beginning of its output. */
983 /* Also note that comments like this one will always work. */
984 const char line_comment_chars
[] = "#";
986 char arm_line_separator_chars
[] = ";";
988 /* Chars that can be used to separate mant
989 from exp in floating point numbers. */
990 const char EXP_CHARS
[] = "eE";
992 /* Chars that mean this number is a floating point constant. */
996 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
998 /* Prefix characters that indicate the start of an immediate
1000 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1002 /* Separator character handling. */
1004 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1007 skip_past_char (char ** str
, char c
)
1009 /* PR gas/14987: Allow for whitespace before the expected character. */
1010 skip_whitespace (*str
);
1021 #define skip_past_comma(str) skip_past_char (str, ',')
1023 /* Arithmetic expressions (possibly involving symbols). */
1025 /* Return TRUE if anything in the expression is a bignum. */
1028 walk_no_bignums (symbolS
* sp
)
1030 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1033 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1035 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1036 || (symbol_get_value_expression (sp
)->X_op_symbol
1037 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1043 static bfd_boolean in_my_get_expression
= FALSE
;
1045 /* Third argument to my_get_expression. */
1046 #define GE_NO_PREFIX 0
1047 #define GE_IMM_PREFIX 1
1048 #define GE_OPT_PREFIX 2
1049 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1050 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1051 #define GE_OPT_PREFIX_BIG 3
1054 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1058 /* In unified syntax, all prefixes are optional. */
1060 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1063 switch (prefix_mode
)
1065 case GE_NO_PREFIX
: break;
1067 if (!is_immediate_prefix (**str
))
1069 inst
.error
= _("immediate expression requires a # prefix");
1075 case GE_OPT_PREFIX_BIG
:
1076 if (is_immediate_prefix (**str
))
1083 memset (ep
, 0, sizeof (expressionS
));
1085 save_in
= input_line_pointer
;
1086 input_line_pointer
= *str
;
1087 in_my_get_expression
= TRUE
;
1089 in_my_get_expression
= FALSE
;
1091 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1093 /* We found a bad or missing expression in md_operand(). */
1094 *str
= input_line_pointer
;
1095 input_line_pointer
= save_in
;
1096 if (inst
.error
== NULL
)
1097 inst
.error
= (ep
->X_op
== O_absent
1098 ? _("missing expression") :_("bad expression"));
1102 /* Get rid of any bignums now, so that we don't generate an error for which
1103 we can't establish a line number later on. Big numbers are never valid
1104 in instructions, which is where this routine is always called. */
1105 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1106 && (ep
->X_op
== O_big
1107 || (ep
->X_add_symbol
1108 && (walk_no_bignums (ep
->X_add_symbol
)
1110 && walk_no_bignums (ep
->X_op_symbol
))))))
1112 inst
.error
= _("invalid constant");
1113 *str
= input_line_pointer
;
1114 input_line_pointer
= save_in
;
1118 *str
= input_line_pointer
;
1119 input_line_pointer
= save_in
;
1123 /* Turn a string in input_line_pointer into a floating point constant
1124 of type TYPE, and store the appropriate bytes in *LITP. The number
1125 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1126 returned, or NULL on OK.
1128 Note that fp constants aren't represent in the normal way on the ARM.
1129 In big endian mode, things are as expected. However, in little endian
1130 mode fp constants are big-endian word-wise, and little-endian byte-wise
1131 within the words. For example, (double) 1.1 in big endian mode is
1132 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1133 the byte sequence 99 99 f1 3f 9a 99 99 99.
1135 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1138 md_atof (int type
, char * litP
, int * sizeP
)
1141 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1173 return _("Unrecognized or unsupported floating point constant");
1176 t
= atof_ieee (input_line_pointer
, type
, words
);
1178 input_line_pointer
= t
;
1179 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1181 if (target_big_endian
)
1183 for (i
= 0; i
< prec
; i
++)
1185 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1186 litP
+= sizeof (LITTLENUM_TYPE
);
1191 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1192 for (i
= prec
- 1; i
>= 0; i
--)
1194 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= sizeof (LITTLENUM_TYPE
);
1198 /* For a 4 byte float the order of elements in `words' is 1 0.
1199 For an 8 byte float the order is 1 0 3 2. */
1200 for (i
= 0; i
< prec
; i
+= 2)
1202 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1203 sizeof (LITTLENUM_TYPE
));
1204 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1205 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1206 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1213 /* We handle all bad expressions here, so that we can report the faulty
1214 instruction in the error message. */
1217 md_operand (expressionS
* exp
)
1219 if (in_my_get_expression
)
1220 exp
->X_op
= O_illegal
;
1223 /* Immediate values. */
1226 /* Generic immediate-value read function for use in directives.
1227 Accepts anything that 'expression' can fold to a constant.
1228 *val receives the number. */
1231 immediate_for_directive (int *val
)
1234 exp
.X_op
= O_illegal
;
1236 if (is_immediate_prefix (*input_line_pointer
))
1238 input_line_pointer
++;
1242 if (exp
.X_op
!= O_constant
)
1244 as_bad (_("expected #constant"));
1245 ignore_rest_of_line ();
1248 *val
= exp
.X_add_number
;
1253 /* Register parsing. */
1255 /* Generic register parser. CCP points to what should be the
1256 beginning of a register name. If it is indeed a valid register
1257 name, advance CCP over it and return the reg_entry structure;
1258 otherwise return NULL. Does not issue diagnostics. */
1260 static struct reg_entry
*
1261 arm_reg_parse_multi (char **ccp
)
1265 struct reg_entry
*reg
;
1267 skip_whitespace (start
);
1269 #ifdef REGISTER_PREFIX
1270 if (*start
!= REGISTER_PREFIX
)
1274 #ifdef OPTIONAL_REGISTER_PREFIX
1275 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1280 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1285 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1287 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1297 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1298 enum arm_reg_type type
)
1300 /* Alternative syntaxes are accepted for a few register classes. */
1307 /* Generic coprocessor register names are allowed for these. */
1308 if (reg
&& reg
->type
== REG_TYPE_CN
)
1313 /* For backward compatibility, a bare number is valid here. */
1315 unsigned long processor
= strtoul (start
, ccp
, 10);
1316 if (*ccp
!= start
&& processor
<= 15)
1321 case REG_TYPE_MMXWC
:
1322 /* WC includes WCG. ??? I'm not sure this is true for all
1323 instructions that take WC registers. */
1324 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1335 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1336 return value is the register number or FAIL. */
1339 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1345 /* Do not allow a scalar (reg+index) to parse as a register. */
1346 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1349 if (reg
&& reg
->type
== type
)
1352 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1359 /* Parse a Neon type specifier. *STR should point at the leading '.'
1360 character. Does no verification at this stage that the type fits the opcode
1367 Can all be legally parsed by this function.
1369 Fills in neon_type struct pointer with parsed information, and updates STR
1370 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1371 type, FAIL if not. */
1374 parse_neon_type (struct neon_type
*type
, char **str
)
1381 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1383 enum neon_el_type thistype
= NT_untyped
;
1384 unsigned thissize
= -1u;
1391 /* Just a size without an explicit type. */
1395 switch (TOLOWER (*ptr
))
1397 case 'i': thistype
= NT_integer
; break;
1398 case 'f': thistype
= NT_float
; break;
1399 case 'p': thistype
= NT_poly
; break;
1400 case 's': thistype
= NT_signed
; break;
1401 case 'u': thistype
= NT_unsigned
; break;
1403 thistype
= NT_float
;
1408 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1414 /* .f is an abbreviation for .f32. */
1415 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1420 thissize
= strtoul (ptr
, &ptr
, 10);
1422 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1425 as_bad (_("bad size %d in type specifier"), thissize
);
1433 type
->el
[type
->elems
].type
= thistype
;
1434 type
->el
[type
->elems
].size
= thissize
;
1439 /* Empty/missing type is not a successful parse. */
1440 if (type
->elems
== 0)
1448 /* Errors may be set multiple times during parsing or bit encoding
1449 (particularly in the Neon bits), but usually the earliest error which is set
1450 will be the most meaningful. Avoid overwriting it with later (cascading)
1451 errors by calling this function. */
1454 first_error (const char *err
)
1460 /* Parse a single type, e.g. ".s32", leading period included. */
1462 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1465 struct neon_type optype
;
1469 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1471 if (optype
.elems
== 1)
1472 *vectype
= optype
.el
[0];
1475 first_error (_("only one type should be specified for operand"));
1481 first_error (_("vector type expected"));
1493 /* Special meanings for indices (which have a range of 0-7), which will fit into
1496 #define NEON_ALL_LANES 15
1497 #define NEON_INTERLEAVE_LANES 14
1499 /* Parse either a register or a scalar, with an optional type. Return the
1500 register number, and optionally fill in the actual type of the register
1501 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1502 type/index information in *TYPEINFO. */
1505 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1506 enum arm_reg_type
*rtype
,
1507 struct neon_typed_alias
*typeinfo
)
1510 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1511 struct neon_typed_alias atype
;
1512 struct neon_type_el parsetype
;
1516 atype
.eltype
.type
= NT_invtype
;
1517 atype
.eltype
.size
= -1;
1519 /* Try alternate syntax for some types of register. Note these are mutually
1520 exclusive with the Neon syntax extensions. */
1523 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1531 /* Undo polymorphism when a set of register types may be accepted. */
1532 if ((type
== REG_TYPE_NDQ
1533 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1534 || (type
== REG_TYPE_VFSD
1535 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1536 || (type
== REG_TYPE_NSDQ
1537 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1538 || reg
->type
== REG_TYPE_NQ
))
1539 || (type
== REG_TYPE_NSD
1540 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1541 || (type
== REG_TYPE_MMXWC
1542 && (reg
->type
== REG_TYPE_MMXWCG
)))
1543 type
= (enum arm_reg_type
) reg
->type
;
1545 if (type
!= reg
->type
)
1551 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1553 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1555 first_error (_("can't redefine type for operand"));
1558 atype
.defined
|= NTA_HASTYPE
;
1559 atype
.eltype
= parsetype
;
1562 if (skip_past_char (&str
, '[') == SUCCESS
)
1564 if (type
!= REG_TYPE_VFD
1565 && !(type
== REG_TYPE_VFS
1566 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1568 first_error (_("only D registers may be indexed"));
1572 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1574 first_error (_("can't change index for operand"));
1578 atype
.defined
|= NTA_HASINDEX
;
1580 if (skip_past_char (&str
, ']') == SUCCESS
)
1581 atype
.index
= NEON_ALL_LANES
;
1586 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1588 if (exp
.X_op
!= O_constant
)
1590 first_error (_("constant expression required"));
1594 if (skip_past_char (&str
, ']') == FAIL
)
1597 atype
.index
= exp
.X_add_number
;
1612 /* Like arm_reg_parse, but allow allow the following extra features:
1613 - If RTYPE is non-zero, return the (possibly restricted) type of the
1614 register (e.g. Neon double or quad reg when either has been requested).
1615 - If this is a Neon vector type with additional type information, fill
1616 in the struct pointed to by VECTYPE (if non-NULL).
1617 This function will fault on encountering a scalar. */
1620 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1621 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1623 struct neon_typed_alias atype
;
1625 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1630 /* Do not allow regname(... to parse as a register. */
1634 /* Do not allow a scalar (reg+index) to parse as a register. */
1635 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1637 first_error (_("register operand expected, but got scalar"));
1642 *vectype
= atype
.eltype
;
1649 #define NEON_SCALAR_REG(X) ((X) >> 4)
1650 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1652 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1653 have enough information to be able to do a good job bounds-checking. So, we
1654 just do easy checks here, and do further checks later. */
1657 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1661 struct neon_typed_alias atype
;
1662 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1665 reg_type
= REG_TYPE_VFS
;
1667 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1669 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1672 if (atype
.index
== NEON_ALL_LANES
)
1674 first_error (_("scalar must have an index"));
1677 else if (atype
.index
>= 64 / elsize
)
1679 first_error (_("scalar index out of range"));
1684 *type
= atype
.eltype
;
1688 return reg
* 16 + atype
.index
;
1691 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1694 parse_reg_list (char ** strp
)
1696 char * str
= * strp
;
1700 /* We come back here if we get ranges concatenated by '+' or '|'. */
1703 skip_whitespace (str
);
1717 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1719 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1729 first_error (_("bad range in register list"));
1733 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1735 if (range
& (1 << i
))
1737 (_("Warning: duplicated register (r%d) in register list"),
1745 if (range
& (1 << reg
))
1746 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1748 else if (reg
<= cur_reg
)
1749 as_tsktsk (_("Warning: register range not in ascending order"));
1754 while (skip_past_comma (&str
) != FAIL
1755 || (in_range
= 1, *str
++ == '-'));
1758 if (skip_past_char (&str
, '}') == FAIL
)
1760 first_error (_("missing `}'"));
1768 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1771 if (exp
.X_op
== O_constant
)
1773 if (exp
.X_add_number
1774 != (exp
.X_add_number
& 0x0000ffff))
1776 inst
.error
= _("invalid register mask");
1780 if ((range
& exp
.X_add_number
) != 0)
1782 int regno
= range
& exp
.X_add_number
;
1785 regno
= (1 << regno
) - 1;
1787 (_("Warning: duplicated register (r%d) in register list"),
1791 range
|= exp
.X_add_number
;
1795 if (inst
.relocs
[0].type
!= 0)
1797 inst
.error
= _("expression too complex");
1801 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1802 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1803 inst
.relocs
[0].pc_rel
= 0;
1807 if (*str
== '|' || *str
== '+')
1813 while (another_range
);
1819 /* Types of registers in a list. */
1828 /* Parse a VFP register list. If the string is invalid return FAIL.
1829 Otherwise return the number of registers, and set PBASE to the first
1830 register. Parses registers of type ETYPE.
1831 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1832 - Q registers can be used to specify pairs of D registers
1833 - { } can be omitted from around a singleton register list
1834 FIXME: This is not implemented, as it would require backtracking in
1837 This could be done (the meaning isn't really ambiguous), but doesn't
1838 fit in well with the current parsing framework.
1839 - 32 D registers may be used (also true for VFPv3).
1840 FIXME: Types are ignored in these register lists, which is probably a
1844 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1849 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1853 unsigned long mask
= 0;
1856 if (skip_past_char (&str
, '{') == FAIL
)
1858 inst
.error
= _("expecting {");
1865 regtype
= REG_TYPE_VFS
;
1870 regtype
= REG_TYPE_VFD
;
1873 case REGLIST_NEON_D
:
1874 regtype
= REG_TYPE_NDQ
;
1878 if (etype
!= REGLIST_VFP_S
)
1880 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1885 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1888 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1895 base_reg
= max_regs
;
1899 int setmask
= 1, addregs
= 1;
1901 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1903 if (new_base
== FAIL
)
1905 first_error (_(reg_expected_msgs
[regtype
]));
1909 if (new_base
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 /* Note: a value of 2 * n is returned for the register Q<n>. */
1916 if (regtype
== REG_TYPE_NQ
)
1922 if (new_base
< base_reg
)
1923 base_reg
= new_base
;
1925 if (mask
& (setmask
<< new_base
))
1927 first_error (_("invalid register list"));
1931 if ((mask
>> new_base
) != 0 && ! warned
)
1933 as_tsktsk (_("register list not in ascending order"));
1937 mask
|= setmask
<< new_base
;
1940 if (*str
== '-') /* We have the start of a range expression */
1946 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1949 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1953 if (high_range
>= max_regs
)
1955 first_error (_("register out of range in list"));
1959 if (regtype
== REG_TYPE_NQ
)
1960 high_range
= high_range
+ 1;
1962 if (high_range
<= new_base
)
1964 inst
.error
= _("register range not in ascending order");
1968 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1970 if (mask
& (setmask
<< new_base
))
1972 inst
.error
= _("invalid register list");
1976 mask
|= setmask
<< new_base
;
1981 while (skip_past_comma (&str
) != FAIL
);
1985 /* Sanity check -- should have raised a parse error above. */
1986 if (count
== 0 || count
> max_regs
)
1991 /* Final test -- the registers must be consecutive. */
1993 for (i
= 0; i
< count
; i
++)
1995 if ((mask
& (1u << i
)) == 0)
1997 inst
.error
= _("non-contiguous register range");
2007 /* True if two alias types are the same. */
2010 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2018 if (a
->defined
!= b
->defined
)
2021 if ((a
->defined
& NTA_HASTYPE
) != 0
2022 && (a
->eltype
.type
!= b
->eltype
.type
2023 || a
->eltype
.size
!= b
->eltype
.size
))
2026 if ((a
->defined
& NTA_HASINDEX
) != 0
2027 && (a
->index
!= b
->index
))
2033 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2034 The base register is put in *PBASE.
2035 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2037 The register stride (minus one) is put in bit 4 of the return value.
2038 Bits [6:5] encode the list length (minus one).
2039 The type of the list elements is put in *ELTYPE, if non-NULL. */
2041 #define NEON_LANE(X) ((X) & 0xf)
2042 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2043 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2046 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2047 struct neon_type_el
*eltype
)
2054 int leading_brace
= 0;
2055 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2056 const char *const incr_error
= _("register stride must be 1 or 2");
2057 const char *const type_error
= _("mismatched element/structure types in list");
2058 struct neon_typed_alias firsttype
;
2059 firsttype
.defined
= 0;
2060 firsttype
.eltype
.type
= NT_invtype
;
2061 firsttype
.eltype
.size
= -1;
2062 firsttype
.index
= -1;
2064 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2069 struct neon_typed_alias atype
;
2070 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2074 first_error (_(reg_expected_msgs
[rtype
]));
2081 if (rtype
== REG_TYPE_NQ
)
2087 else if (reg_incr
== -1)
2089 reg_incr
= getreg
- base_reg
;
2090 if (reg_incr
< 1 || reg_incr
> 2)
2092 first_error (_(incr_error
));
2096 else if (getreg
!= base_reg
+ reg_incr
* count
)
2098 first_error (_(incr_error
));
2102 if (! neon_alias_types_same (&atype
, &firsttype
))
2104 first_error (_(type_error
));
2108 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2112 struct neon_typed_alias htype
;
2113 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2115 lane
= NEON_INTERLEAVE_LANES
;
2116 else if (lane
!= NEON_INTERLEAVE_LANES
)
2118 first_error (_(type_error
));
2123 else if (reg_incr
!= 1)
2125 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2129 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2132 first_error (_(reg_expected_msgs
[rtype
]));
2135 if (! neon_alias_types_same (&htype
, &firsttype
))
2137 first_error (_(type_error
));
2140 count
+= hireg
+ dregs
- getreg
;
2144 /* If we're using Q registers, we can't use [] or [n] syntax. */
2145 if (rtype
== REG_TYPE_NQ
)
2151 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2155 else if (lane
!= atype
.index
)
2157 first_error (_(type_error
));
2161 else if (lane
== -1)
2162 lane
= NEON_INTERLEAVE_LANES
;
2163 else if (lane
!= NEON_INTERLEAVE_LANES
)
2165 first_error (_(type_error
));
2170 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2172 /* No lane set by [x]. We must be interleaving structures. */
2174 lane
= NEON_INTERLEAVE_LANES
;
2177 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2178 || (count
> 1 && reg_incr
== -1))
2180 first_error (_("error parsing element/structure list"));
2184 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2186 first_error (_("expected }"));
2194 *eltype
= firsttype
.eltype
;
2199 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2202 /* Parse an explicit relocation suffix on an expression. This is
2203 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2204 arm_reloc_hsh contains no entries, so this function can only
2205 succeed if there is no () after the word. Returns -1 on error,
2206 BFD_RELOC_UNUSED if there wasn't any suffix. */
2209 parse_reloc (char **str
)
2211 struct reloc_entry
*r
;
2215 return BFD_RELOC_UNUSED
;
2220 while (*q
&& *q
!= ')' && *q
!= ',')
2225 if ((r
= (struct reloc_entry
*)
2226 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2233 /* Directives: register aliases. */
2235 static struct reg_entry
*
2236 insert_reg_alias (char *str
, unsigned number
, int type
)
2238 struct reg_entry
*new_reg
;
2241 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2243 if (new_reg
->builtin
)
2244 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2246 /* Only warn about a redefinition if it's not defined as the
2248 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2249 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2254 name
= xstrdup (str
);
2255 new_reg
= XNEW (struct reg_entry
);
2257 new_reg
->name
= name
;
2258 new_reg
->number
= number
;
2259 new_reg
->type
= type
;
2260 new_reg
->builtin
= FALSE
;
2261 new_reg
->neon
= NULL
;
2263 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2270 insert_neon_reg_alias (char *str
, int number
, int type
,
2271 struct neon_typed_alias
*atype
)
2273 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2277 first_error (_("attempt to redefine typed alias"));
2283 reg
->neon
= XNEW (struct neon_typed_alias
);
2284 *reg
->neon
= *atype
;
2288 /* Look for the .req directive. This is of the form:
2290 new_register_name .req existing_register_name
2292 If we find one, or if it looks sufficiently like one that we want to
2293 handle any error here, return TRUE. Otherwise return FALSE. */
2296 create_register_alias (char * newname
, char *p
)
2298 struct reg_entry
*old
;
2299 char *oldname
, *nbuf
;
2302 /* The input scrubber ensures that whitespace after the mnemonic is
2303 collapsed to single spaces. */
2305 if (strncmp (oldname
, " .req ", 6) != 0)
2309 if (*oldname
== '\0')
2312 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2315 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2319 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2320 the desired alias name, and p points to its end. If not, then
2321 the desired alias name is in the global original_case_string. */
2322 #ifdef TC_CASE_SENSITIVE
2325 newname
= original_case_string
;
2326 nlen
= strlen (newname
);
2329 nbuf
= xmemdup0 (newname
, nlen
);
2331 /* Create aliases under the new name as stated; an all-lowercase
2332 version of the new name; and an all-uppercase version of the new
2334 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2336 for (p
= nbuf
; *p
; p
++)
2339 if (strncmp (nbuf
, newname
, nlen
))
2341 /* If this attempt to create an additional alias fails, do not bother
2342 trying to create the all-lower case alias. We will fail and issue
2343 a second, duplicate error message. This situation arises when the
2344 programmer does something like:
2347 The second .req creates the "Foo" alias but then fails to create
2348 the artificial FOO alias because it has already been created by the
2350 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2357 for (p
= nbuf
; *p
; p
++)
2360 if (strncmp (nbuf
, newname
, nlen
))
2361 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2368 /* Create a Neon typed/indexed register alias using directives, e.g.:
2373 These typed registers can be used instead of the types specified after the
2374 Neon mnemonic, so long as all operands given have types. Types can also be
2375 specified directly, e.g.:
2376 vadd d0.s32, d1.s32, d2.s32 */
2379 create_neon_reg_alias (char *newname
, char *p
)
2381 enum arm_reg_type basetype
;
2382 struct reg_entry
*basereg
;
2383 struct reg_entry mybasereg
;
2384 struct neon_type ntype
;
2385 struct neon_typed_alias typeinfo
;
2386 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2389 typeinfo
.defined
= 0;
2390 typeinfo
.eltype
.type
= NT_invtype
;
2391 typeinfo
.eltype
.size
= -1;
2392 typeinfo
.index
= -1;
2396 if (strncmp (p
, " .dn ", 5) == 0)
2397 basetype
= REG_TYPE_VFD
;
2398 else if (strncmp (p
, " .qn ", 5) == 0)
2399 basetype
= REG_TYPE_NQ
;
2408 basereg
= arm_reg_parse_multi (&p
);
2410 if (basereg
&& basereg
->type
!= basetype
)
2412 as_bad (_("bad type for register"));
2416 if (basereg
== NULL
)
2419 /* Try parsing as an integer. */
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2421 if (exp
.X_op
!= O_constant
)
2423 as_bad (_("expression must be constant"));
2426 basereg
= &mybasereg
;
2427 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2433 typeinfo
= *basereg
->neon
;
2435 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2437 /* We got a type. */
2438 if (typeinfo
.defined
& NTA_HASTYPE
)
2440 as_bad (_("can't redefine the type of a register alias"));
2444 typeinfo
.defined
|= NTA_HASTYPE
;
2445 if (ntype
.elems
!= 1)
2447 as_bad (_("you must specify a single type only"));
2450 typeinfo
.eltype
= ntype
.el
[0];
2453 if (skip_past_char (&p
, '[') == SUCCESS
)
2456 /* We got a scalar index. */
2458 if (typeinfo
.defined
& NTA_HASINDEX
)
2460 as_bad (_("can't redefine the index of a scalar alias"));
2464 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2466 if (exp
.X_op
!= O_constant
)
2468 as_bad (_("scalar index must be constant"));
2472 typeinfo
.defined
|= NTA_HASINDEX
;
2473 typeinfo
.index
= exp
.X_add_number
;
2475 if (skip_past_char (&p
, ']') == FAIL
)
2477 as_bad (_("expecting ]"));
2482 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2483 the desired alias name, and p points to its end. If not, then
2484 the desired alias name is in the global original_case_string. */
2485 #ifdef TC_CASE_SENSITIVE
2486 namelen
= nameend
- newname
;
2488 newname
= original_case_string
;
2489 namelen
= strlen (newname
);
2492 namebuf
= xmemdup0 (newname
, namelen
);
2494 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2495 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2497 /* Insert name in all uppercase. */
2498 for (p
= namebuf
; *p
; p
++)
2501 if (strncmp (namebuf
, newname
, namelen
))
2502 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2503 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2505 /* Insert name in all lowercase. */
2506 for (p
= namebuf
; *p
; p
++)
2509 if (strncmp (namebuf
, newname
, namelen
))
2510 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2511 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2517 /* Should never be called, as .req goes between the alias and the
2518 register name, not at the beginning of the line. */
2521 s_req (int a ATTRIBUTE_UNUSED
)
2523 as_bad (_("invalid syntax for .req directive"));
2527 s_dn (int a ATTRIBUTE_UNUSED
)
2529 as_bad (_("invalid syntax for .dn directive"));
2533 s_qn (int a ATTRIBUTE_UNUSED
)
2535 as_bad (_("invalid syntax for .qn directive"));
2538 /* The .unreq directive deletes an alias which was previously defined
2539 by .req. For example:
2545 s_unreq (int a ATTRIBUTE_UNUSED
)
2550 name
= input_line_pointer
;
2552 while (*input_line_pointer
!= 0
2553 && *input_line_pointer
!= ' '
2554 && *input_line_pointer
!= '\n')
2555 ++input_line_pointer
;
2557 saved_char
= *input_line_pointer
;
2558 *input_line_pointer
= 0;
2561 as_bad (_("invalid syntax for .unreq directive"));
2564 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2568 as_bad (_("unknown register alias '%s'"), name
);
2569 else if (reg
->builtin
)
2570 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2577 hash_delete (arm_reg_hsh
, name
, FALSE
);
2578 free ((char *) reg
->name
);
2583 /* Also locate the all upper case and all lower case versions.
2584 Do not complain if we cannot find one or the other as it
2585 was probably deleted above. */
2587 nbuf
= strdup (name
);
2588 for (p
= nbuf
; *p
; p
++)
2590 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2593 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2594 free ((char *) reg
->name
);
2600 for (p
= nbuf
; *p
; p
++)
2602 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2605 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2606 free ((char *) reg
->name
);
2616 *input_line_pointer
= saved_char
;
2617 demand_empty_rest_of_line ();
2620 /* Directives: Instruction set selection. */
2623 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2624 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2625 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2626 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2628 /* Create a new mapping symbol for the transition to STATE. */
2631 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2634 const char * symname
;
2641 type
= BSF_NO_FLAGS
;
2645 type
= BSF_NO_FLAGS
;
2649 type
= BSF_NO_FLAGS
;
2655 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2656 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2661 THUMB_SET_FUNC (symbolP
, 0);
2662 ARM_SET_THUMB (symbolP
, 0);
2663 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2667 THUMB_SET_FUNC (symbolP
, 1);
2668 ARM_SET_THUMB (symbolP
, 1);
2669 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2677 /* Save the mapping symbols for future reference. Also check that
2678 we do not place two mapping symbols at the same offset within a
2679 frag. We'll handle overlap between frags in
2680 check_mapping_symbols.
2682 If .fill or other data filling directive generates zero sized data,
2683 the mapping symbol for the following code will have the same value
2684 as the one generated for the data filling directive. In this case,
2685 we replace the old symbol with the new one at the same address. */
2688 if (frag
->tc_frag_data
.first_map
!= NULL
)
2690 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2691 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2693 frag
->tc_frag_data
.first_map
= symbolP
;
2695 if (frag
->tc_frag_data
.last_map
!= NULL
)
2697 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2698 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2699 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2701 frag
->tc_frag_data
.last_map
= symbolP
;
2704 /* We must sometimes convert a region marked as code to data during
2705 code alignment, if an odd number of bytes have to be padded. The
2706 code mapping symbol is pushed to an aligned address. */
2709 insert_data_mapping_symbol (enum mstate state
,
2710 valueT value
, fragS
*frag
, offsetT bytes
)
2712 /* If there was already a mapping symbol, remove it. */
2713 if (frag
->tc_frag_data
.last_map
!= NULL
2714 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2716 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2720 know (frag
->tc_frag_data
.first_map
== symp
);
2721 frag
->tc_frag_data
.first_map
= NULL
;
2723 frag
->tc_frag_data
.last_map
= NULL
;
2724 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2727 make_mapping_symbol (MAP_DATA
, value
, frag
);
2728 make_mapping_symbol (state
, value
+ bytes
, frag
);
2731 static void mapping_state_2 (enum mstate state
, int max_chars
);
2733 /* Set the mapping state to STATE. Only call this when about to
2734 emit some STATE bytes to the file. */
2736 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2738 mapping_state (enum mstate state
)
2740 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2742 if (mapstate
== state
)
2743 /* The mapping symbol has already been emitted.
2744 There is nothing else to do. */
2747 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2749 All ARM instructions require 4-byte alignment.
2750 (Almost) all Thumb instructions require 2-byte alignment.
2752 When emitting instructions into any section, mark the section
2755 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2756 but themselves require 2-byte alignment; this applies to some
2757 PC- relative forms. However, these cases will involve implicit
2758 literal pool generation or an explicit .align >=2, both of
2759 which will cause the section to me marked with sufficient
2760 alignment. Thus, we don't handle those cases here. */
2761 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2763 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2764 /* This case will be evaluated later. */
2767 mapping_state_2 (state
, 0);
2770 /* Same as mapping_state, but MAX_CHARS bytes have already been
2771 allocated. Put the mapping symbol that far back. */
2774 mapping_state_2 (enum mstate state
, int max_chars
)
2776 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2778 if (!SEG_NORMAL (now_seg
))
2781 if (mapstate
== state
)
2782 /* The mapping symbol has already been emitted.
2783 There is nothing else to do. */
2786 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2787 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2789 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2790 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2793 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2796 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2797 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2801 #define mapping_state(x) ((void)0)
2802 #define mapping_state_2(x, y) ((void)0)
2805 /* Find the real, Thumb encoded start of a Thumb function. */
2809 find_real_start (symbolS
* symbolP
)
2812 const char * name
= S_GET_NAME (symbolP
);
2813 symbolS
* new_target
;
2815 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2816 #define STUB_NAME ".real_start_of"
2821 /* The compiler may generate BL instructions to local labels because
2822 it needs to perform a branch to a far away location. These labels
2823 do not have a corresponding ".real_start_of" label. We check
2824 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2825 the ".real_start_of" convention for nonlocal branches. */
2826 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2829 real_start
= concat (STUB_NAME
, name
, NULL
);
2830 new_target
= symbol_find (real_start
);
2833 if (new_target
== NULL
)
2835 as_warn (_("Failed to find real start of function: %s\n"), name
);
2836 new_target
= symbolP
;
2844 opcode_select (int width
)
2851 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2852 as_bad (_("selected processor does not support THUMB opcodes"));
2855 /* No need to force the alignment, since we will have been
2856 coming from ARM mode, which is word-aligned. */
2857 record_alignment (now_seg
, 1);
2864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2865 as_bad (_("selected processor does not support ARM opcodes"));
2870 frag_align (2, 0, 0);
2872 record_alignment (now_seg
, 1);
2877 as_bad (_("invalid instruction size selected (%d)"), width
);
2882 s_arm (int ignore ATTRIBUTE_UNUSED
)
2885 demand_empty_rest_of_line ();
2889 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2892 demand_empty_rest_of_line ();
2896 s_code (int unused ATTRIBUTE_UNUSED
)
2900 temp
= get_absolute_expression ();
2905 opcode_select (temp
);
2909 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2914 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2916 /* If we are not already in thumb mode go into it, EVEN if
2917 the target processor does not support thumb instructions.
2918 This is used by gcc/config/arm/lib1funcs.asm for example
2919 to compile interworking support functions even if the
2920 target processor should not support interworking. */
2924 record_alignment (now_seg
, 1);
2927 demand_empty_rest_of_line ();
2931 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2935 /* The following label is the name/address of the start of a Thumb function.
2936 We need to know this for the interworking support. */
2937 label_is_thumb_function_name
= TRUE
;
2940 /* Perform a .set directive, but also mark the alias as
2941 being a thumb function. */
2944 s_thumb_set (int equiv
)
2946 /* XXX the following is a duplicate of the code for s_set() in read.c
2947 We cannot just call that code as we need to get at the symbol that
2954 /* Especial apologies for the random logic:
2955 This just grew, and could be parsed much more simply!
2957 delim
= get_symbol_name (& name
);
2958 end_name
= input_line_pointer
;
2959 (void) restore_line_pointer (delim
);
2961 if (*input_line_pointer
!= ',')
2964 as_bad (_("expected comma after name \"%s\""), name
);
2966 ignore_rest_of_line ();
2970 input_line_pointer
++;
2973 if (name
[0] == '.' && name
[1] == '\0')
2975 /* XXX - this should not happen to .thumb_set. */
2979 if ((symbolP
= symbol_find (name
)) == NULL
2980 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2983 /* When doing symbol listings, play games with dummy fragments living
2984 outside the normal fragment chain to record the file and line info
2986 if (listing
& LISTING_SYMBOLS
)
2988 extern struct list_info_struct
* listing_tail
;
2989 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2991 memset (dummy_frag
, 0, sizeof (fragS
));
2992 dummy_frag
->fr_type
= rs_fill
;
2993 dummy_frag
->line
= listing_tail
;
2994 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2995 dummy_frag
->fr_symbol
= symbolP
;
2999 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3002 /* "set" symbols are local unless otherwise specified. */
3003 SF_SET_LOCAL (symbolP
);
3004 #endif /* OBJ_COFF */
3005 } /* Make a new symbol. */
3007 symbol_table_insert (symbolP
);
3012 && S_IS_DEFINED (symbolP
)
3013 && S_GET_SEGMENT (symbolP
) != reg_section
)
3014 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3016 pseudo_set (symbolP
);
3018 demand_empty_rest_of_line ();
3020 /* XXX Now we come to the Thumb specific bit of code. */
3022 THUMB_SET_FUNC (symbolP
, 1);
3023 ARM_SET_THUMB (symbolP
, 1);
3024 #if defined OBJ_ELF || defined OBJ_COFF
3025 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3029 /* Directives: Mode selection. */
3031 /* .syntax [unified|divided] - choose the new unified syntax
3032 (same for Arm and Thumb encoding, modulo slight differences in what
3033 can be represented) or the old divergent syntax for each mode. */
3035 s_syntax (int unused ATTRIBUTE_UNUSED
)
3039 delim
= get_symbol_name (& name
);
3041 if (!strcasecmp (name
, "unified"))
3042 unified_syntax
= TRUE
;
3043 else if (!strcasecmp (name
, "divided"))
3044 unified_syntax
= FALSE
;
3047 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3050 (void) restore_line_pointer (delim
);
3051 demand_empty_rest_of_line ();
3054 /* Directives: sectioning and alignment. */
3057 s_bss (int ignore ATTRIBUTE_UNUSED
)
3059 /* We don't support putting frags in the BSS segment, we fake it by
3060 marking in_bss, then looking at s_skip for clues. */
3061 subseg_set (bss_section
, 0);
3062 demand_empty_rest_of_line ();
3064 #ifdef md_elf_section_change_hook
3065 md_elf_section_change_hook ();
3070 s_even (int ignore ATTRIBUTE_UNUSED
)
3072 /* Never make frag if expect extra pass. */
3074 frag_align (1, 0, 0);
3076 record_alignment (now_seg
, 1);
3078 demand_empty_rest_of_line ();
3081 /* Directives: CodeComposer Studio. */
3083 /* .ref (for CodeComposer Studio syntax only). */
3085 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3087 if (codecomposer_syntax
)
3088 ignore_rest_of_line ();
3090 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3093 /* If name is not NULL, then it is used for marking the beginning of a
3094 function, whereas if it is NULL then it means the function end. */
3096 asmfunc_debug (const char * name
)
3098 static const char * last_name
= NULL
;
3102 gas_assert (last_name
== NULL
);
3105 if (debug_type
== DEBUG_STABS
)
3106 stabs_generate_asm_func (name
, name
);
3110 gas_assert (last_name
!= NULL
);
3112 if (debug_type
== DEBUG_STABS
)
3113 stabs_generate_asm_endfunc (last_name
, last_name
);
3120 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3122 if (codecomposer_syntax
)
3124 switch (asmfunc_state
)
3126 case OUTSIDE_ASMFUNC
:
3127 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3130 case WAITING_ASMFUNC_NAME
:
3131 as_bad (_(".asmfunc repeated."));
3134 case WAITING_ENDASMFUNC
:
3135 as_bad (_(".asmfunc without function."));
3138 demand_empty_rest_of_line ();
3141 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3145 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3147 if (codecomposer_syntax
)
3149 switch (asmfunc_state
)
3151 case OUTSIDE_ASMFUNC
:
3152 as_bad (_(".endasmfunc without a .asmfunc."));
3155 case WAITING_ASMFUNC_NAME
:
3156 as_bad (_(".endasmfunc without function."));
3159 case WAITING_ENDASMFUNC
:
3160 asmfunc_state
= OUTSIDE_ASMFUNC
;
3161 asmfunc_debug (NULL
);
3164 demand_empty_rest_of_line ();
3167 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3171 s_ccs_def (int name
)
3173 if (codecomposer_syntax
)
3176 as_bad (_(".def pseudo-op only available with -mccs flag."));
3179 /* Directives: Literal pools. */
3181 static literal_pool
*
3182 find_literal_pool (void)
3184 literal_pool
* pool
;
3186 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3188 if (pool
->section
== now_seg
3189 && pool
->sub_section
== now_subseg
)
3196 static literal_pool
*
3197 find_or_make_literal_pool (void)
3199 /* Next literal pool ID number. */
3200 static unsigned int latest_pool_num
= 1;
3201 literal_pool
* pool
;
3203 pool
= find_literal_pool ();
3207 /* Create a new pool. */
3208 pool
= XNEW (literal_pool
);
3212 pool
->next_free_entry
= 0;
3213 pool
->section
= now_seg
;
3214 pool
->sub_section
= now_subseg
;
3215 pool
->next
= list_of_pools
;
3216 pool
->symbol
= NULL
;
3217 pool
->alignment
= 2;
3219 /* Add it to the list. */
3220 list_of_pools
= pool
;
3223 /* New pools, and emptied pools, will have a NULL symbol. */
3224 if (pool
->symbol
== NULL
)
3226 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3227 (valueT
) 0, &zero_address_frag
);
3228 pool
->id
= latest_pool_num
++;
3235 /* Add the literal in the global 'inst'
3236 structure to the relevant literal pool. */
3239 add_to_lit_pool (unsigned int nbytes
)
3241 #define PADDING_SLOT 0x1
3242 #define LIT_ENTRY_SIZE_MASK 0xFF
3243 literal_pool
* pool
;
3244 unsigned int entry
, pool_size
= 0;
3245 bfd_boolean padding_slot_p
= FALSE
;
3251 imm1
= inst
.operands
[1].imm
;
3252 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3253 : inst
.relocs
[0].exp
.X_unsigned
? 0
3254 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3255 if (target_big_endian
)
3258 imm2
= inst
.operands
[1].imm
;
3262 pool
= find_or_make_literal_pool ();
3264 /* Check if this literal value is already in the pool. */
3265 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3269 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3270 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3271 && (pool
->literals
[entry
].X_add_number
3272 == inst
.relocs
[0].exp
.X_add_number
)
3273 && (pool
->literals
[entry
].X_md
== nbytes
)
3274 && (pool
->literals
[entry
].X_unsigned
3275 == inst
.relocs
[0].exp
.X_unsigned
))
3278 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3279 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3280 && (pool
->literals
[entry
].X_add_number
3281 == inst
.relocs
[0].exp
.X_add_number
)
3282 && (pool
->literals
[entry
].X_add_symbol
3283 == inst
.relocs
[0].exp
.X_add_symbol
)
3284 && (pool
->literals
[entry
].X_op_symbol
3285 == inst
.relocs
[0].exp
.X_op_symbol
)
3286 && (pool
->literals
[entry
].X_md
== nbytes
))
3289 else if ((nbytes
== 8)
3290 && !(pool_size
& 0x7)
3291 && ((entry
+ 1) != pool
->next_free_entry
)
3292 && (pool
->literals
[entry
].X_op
== O_constant
)
3293 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3294 && (pool
->literals
[entry
].X_unsigned
3295 == inst
.relocs
[0].exp
.X_unsigned
)
3296 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3297 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3298 && (pool
->literals
[entry
+ 1].X_unsigned
3299 == inst
.relocs
[0].exp
.X_unsigned
))
3302 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3303 if (padding_slot_p
&& (nbytes
== 4))
3309 /* Do we need to create a new entry? */
3310 if (entry
== pool
->next_free_entry
)
3312 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3314 inst
.error
= _("literal pool overflow");
3320 /* For 8-byte entries, we align to an 8-byte boundary,
3321 and split it into two 4-byte entries, because on 32-bit
3322 host, 8-byte constants are treated as big num, thus
3323 saved in "generic_bignum" which will be overwritten
3324 by later assignments.
3326 We also need to make sure there is enough space for
3329 We also check to make sure the literal operand is a
3331 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3332 || inst
.relocs
[0].exp
.X_op
== O_big
))
3334 inst
.error
= _("invalid type for literal pool");
3337 else if (pool_size
& 0x7)
3339 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3341 inst
.error
= _("literal pool overflow");
3345 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3346 pool
->literals
[entry
].X_op
= O_constant
;
3347 pool
->literals
[entry
].X_add_number
= 0;
3348 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3349 pool
->next_free_entry
+= 1;
3352 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3354 inst
.error
= _("literal pool overflow");
3358 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3359 pool
->literals
[entry
].X_op
= O_constant
;
3360 pool
->literals
[entry
].X_add_number
= imm1
;
3361 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3362 pool
->literals
[entry
++].X_md
= 4;
3363 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3364 pool
->literals
[entry
].X_op
= O_constant
;
3365 pool
->literals
[entry
].X_add_number
= imm2
;
3366 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3367 pool
->literals
[entry
].X_md
= 4;
3368 pool
->alignment
= 3;
3369 pool
->next_free_entry
+= 1;
3373 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3374 pool
->literals
[entry
].X_md
= 4;
3378 /* PR ld/12974: Record the location of the first source line to reference
3379 this entry in the literal pool. If it turns out during linking that the
3380 symbol does not exist we will be able to give an accurate line number for
3381 the (first use of the) missing reference. */
3382 if (debug_type
== DEBUG_DWARF2
)
3383 dwarf2_where (pool
->locs
+ entry
);
3385 pool
->next_free_entry
+= 1;
3387 else if (padding_slot_p
)
3389 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3390 pool
->literals
[entry
].X_md
= nbytes
;
3393 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3394 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3395 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3401 tc_start_label_without_colon (void)
3403 bfd_boolean ret
= TRUE
;
3405 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3407 const char *label
= input_line_pointer
;
3409 while (!is_end_of_line
[(int) label
[-1]])
3414 as_bad (_("Invalid label '%s'"), label
);
3418 asmfunc_debug (label
);
3420 asmfunc_state
= WAITING_ENDASMFUNC
;
3426 /* Can't use symbol_new here, so have to create a symbol and then at
3427 a later date assign it a value. That's what these functions do. */
3430 symbol_locate (symbolS
* symbolP
,
3431 const char * name
, /* It is copied, the caller can modify. */
3432 segT segment
, /* Segment identifier (SEG_<something>). */
3433 valueT valu
, /* Symbol value. */
3434 fragS
* frag
) /* Associated fragment. */
3437 char * preserved_copy_of_name
;
3439 name_length
= strlen (name
) + 1; /* +1 for \0. */
3440 obstack_grow (¬es
, name
, name_length
);
3441 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3443 #ifdef tc_canonicalize_symbol_name
3444 preserved_copy_of_name
=
3445 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3448 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3450 S_SET_SEGMENT (symbolP
, segment
);
3451 S_SET_VALUE (symbolP
, valu
);
3452 symbol_clear_list_pointers (symbolP
);
3454 symbol_set_frag (symbolP
, frag
);
3456 /* Link to end of symbol chain. */
3458 extern int symbol_table_frozen
;
3460 if (symbol_table_frozen
)
3464 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3466 obj_symbol_new_hook (symbolP
);
3468 #ifdef tc_symbol_new_hook
3469 tc_symbol_new_hook (symbolP
);
3473 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3474 #endif /* DEBUG_SYMS */
3478 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3481 literal_pool
* pool
;
3484 pool
= find_literal_pool ();
3486 || pool
->symbol
== NULL
3487 || pool
->next_free_entry
== 0)
3490 /* Align pool as you have word accesses.
3491 Only make a frag if we have to. */
3493 frag_align (pool
->alignment
, 0, 0);
3495 record_alignment (now_seg
, 2);
3498 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3499 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3501 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3503 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3504 (valueT
) frag_now_fix (), frag_now
);
3505 symbol_table_insert (pool
->symbol
);
3507 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3509 #if defined OBJ_COFF || defined OBJ_ELF
3510 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3513 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3516 if (debug_type
== DEBUG_DWARF2
)
3517 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3519 /* First output the expression in the instruction to the pool. */
3520 emit_expr (&(pool
->literals
[entry
]),
3521 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3524 /* Mark the pool as empty. */
3525 pool
->next_free_entry
= 0;
3526 pool
->symbol
= NULL
;
3530 /* Forward declarations for functions below, in the MD interface
3532 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3533 static valueT
create_unwind_entry (int);
3534 static void start_unwind_section (const segT
, int);
3535 static void add_unwind_opcode (valueT
, int);
3536 static void flush_pending_unwind (void);
3538 /* Directives: Data. */
3541 s_arm_elf_cons (int nbytes
)
3545 #ifdef md_flush_pending_output
3546 md_flush_pending_output ();
3549 if (is_it_end_of_statement ())
3551 demand_empty_rest_of_line ();
3555 #ifdef md_cons_align
3556 md_cons_align (nbytes
);
3559 mapping_state (MAP_DATA
);
3563 char *base
= input_line_pointer
;
3567 if (exp
.X_op
!= O_symbol
)
3568 emit_expr (&exp
, (unsigned int) nbytes
);
3571 char *before_reloc
= input_line_pointer
;
3572 reloc
= parse_reloc (&input_line_pointer
);
3575 as_bad (_("unrecognized relocation suffix"));
3576 ignore_rest_of_line ();
3579 else if (reloc
== BFD_RELOC_UNUSED
)
3580 emit_expr (&exp
, (unsigned int) nbytes
);
3583 reloc_howto_type
*howto
= (reloc_howto_type
*)
3584 bfd_reloc_type_lookup (stdoutput
,
3585 (bfd_reloc_code_real_type
) reloc
);
3586 int size
= bfd_get_reloc_size (howto
);
3588 if (reloc
== BFD_RELOC_ARM_PLT32
)
3590 as_bad (_("(plt) is only valid on branch targets"));
3591 reloc
= BFD_RELOC_UNUSED
;
3596 as_bad (ngettext ("%s relocations do not fit in %d byte",
3597 "%s relocations do not fit in %d bytes",
3599 howto
->name
, nbytes
);
3602 /* We've parsed an expression stopping at O_symbol.
3603 But there may be more expression left now that we
3604 have parsed the relocation marker. Parse it again.
3605 XXX Surely there is a cleaner way to do this. */
3606 char *p
= input_line_pointer
;
3608 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3610 memcpy (save_buf
, base
, input_line_pointer
- base
);
3611 memmove (base
+ (input_line_pointer
- before_reloc
),
3612 base
, before_reloc
- base
);
3614 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3616 memcpy (base
, save_buf
, p
- base
);
3618 offset
= nbytes
- size
;
3619 p
= frag_more (nbytes
);
3620 memset (p
, 0, nbytes
);
3621 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3622 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3628 while (*input_line_pointer
++ == ',');
3630 /* Put terminator back into stream. */
3631 input_line_pointer
--;
3632 demand_empty_rest_of_line ();
3635 /* Emit an expression containing a 32-bit thumb instruction.
3636 Implementation based on put_thumb32_insn. */
3639 emit_thumb32_expr (expressionS
* exp
)
3641 expressionS exp_high
= *exp
;
3643 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3644 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3645 exp
->X_add_number
&= 0xffff;
3646 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3649 /* Guess the instruction size based on the opcode. */
3652 thumb_insn_size (int opcode
)
3654 if ((unsigned int) opcode
< 0xe800u
)
3656 else if ((unsigned int) opcode
>= 0xe8000000u
)
3663 emit_insn (expressionS
*exp
, int nbytes
)
3667 if (exp
->X_op
== O_constant
)
3672 size
= thumb_insn_size (exp
->X_add_number
);
3676 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3678 as_bad (_(".inst.n operand too big. "\
3679 "Use .inst.w instead"));
3684 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3685 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3687 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3689 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3690 emit_thumb32_expr (exp
);
3692 emit_expr (exp
, (unsigned int) size
);
3694 it_fsm_post_encode ();
3698 as_bad (_("cannot determine Thumb instruction size. " \
3699 "Use .inst.n/.inst.w instead"));
3702 as_bad (_("constant expression required"));
3707 /* Like s_arm_elf_cons but do not use md_cons_align and
3708 set the mapping state to MAP_ARM/MAP_THUMB. */
3711 s_arm_elf_inst (int nbytes
)
3713 if (is_it_end_of_statement ())
3715 demand_empty_rest_of_line ();
3719 /* Calling mapping_state () here will not change ARM/THUMB,
3720 but will ensure not to be in DATA state. */
3723 mapping_state (MAP_THUMB
);
3728 as_bad (_("width suffixes are invalid in ARM mode"));
3729 ignore_rest_of_line ();
3735 mapping_state (MAP_ARM
);
3744 if (! emit_insn (& exp
, nbytes
))
3746 ignore_rest_of_line ();
3750 while (*input_line_pointer
++ == ',');
3752 /* Put terminator back into stream. */
3753 input_line_pointer
--;
3754 demand_empty_rest_of_line ();
3757 /* Parse a .rel31 directive. */
3760 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3767 if (*input_line_pointer
== '1')
3768 highbit
= 0x80000000;
3769 else if (*input_line_pointer
!= '0')
3770 as_bad (_("expected 0 or 1"));
3772 input_line_pointer
++;
3773 if (*input_line_pointer
!= ',')
3774 as_bad (_("missing comma"));
3775 input_line_pointer
++;
3777 #ifdef md_flush_pending_output
3778 md_flush_pending_output ();
3781 #ifdef md_cons_align
3785 mapping_state (MAP_DATA
);
3790 md_number_to_chars (p
, highbit
, 4);
3791 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3792 BFD_RELOC_ARM_PREL31
);
3794 demand_empty_rest_of_line ();
3797 /* Directives: AEABI stack-unwind tables. */
3799 /* Parse an unwind_fnstart directive. Simply records the current location. */
3802 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3804 demand_empty_rest_of_line ();
3805 if (unwind
.proc_start
)
3807 as_bad (_("duplicate .fnstart directive"));
3811 /* Mark the start of the function. */
3812 unwind
.proc_start
= expr_build_dot ();
3814 /* Reset the rest of the unwind info. */
3815 unwind
.opcode_count
= 0;
3816 unwind
.table_entry
= NULL
;
3817 unwind
.personality_routine
= NULL
;
3818 unwind
.personality_index
= -1;
3819 unwind
.frame_size
= 0;
3820 unwind
.fp_offset
= 0;
3821 unwind
.fp_reg
= REG_SP
;
3823 unwind
.sp_restored
= 0;
3827 /* Parse a handlerdata directive. Creates the exception handling table entry
3828 for the function. */
3831 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3833 demand_empty_rest_of_line ();
3834 if (!unwind
.proc_start
)
3835 as_bad (MISSING_FNSTART
);
3837 if (unwind
.table_entry
)
3838 as_bad (_("duplicate .handlerdata directive"));
3840 create_unwind_entry (1);
3843 /* Parse an unwind_fnend directive. Generates the index table entry. */
3846 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3851 unsigned int marked_pr_dependency
;
3853 demand_empty_rest_of_line ();
3855 if (!unwind
.proc_start
)
3857 as_bad (_(".fnend directive without .fnstart"));
3861 /* Add eh table entry. */
3862 if (unwind
.table_entry
== NULL
)
3863 val
= create_unwind_entry (0);
3867 /* Add index table entry. This is two words. */
3868 start_unwind_section (unwind
.saved_seg
, 1);
3869 frag_align (2, 0, 0);
3870 record_alignment (now_seg
, 2);
3872 ptr
= frag_more (8);
3874 where
= frag_now_fix () - 8;
3876 /* Self relative offset of the function start. */
3877 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3878 BFD_RELOC_ARM_PREL31
);
3880 /* Indicate dependency on EHABI-defined personality routines to the
3881 linker, if it hasn't been done already. */
3882 marked_pr_dependency
3883 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3884 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3885 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3887 static const char *const name
[] =
3889 "__aeabi_unwind_cpp_pr0",
3890 "__aeabi_unwind_cpp_pr1",
3891 "__aeabi_unwind_cpp_pr2"
3893 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3894 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3895 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3896 |= 1 << unwind
.personality_index
;
3900 /* Inline exception table entry. */
3901 md_number_to_chars (ptr
+ 4, val
, 4);
3903 /* Self relative offset of the table entry. */
3904 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3905 BFD_RELOC_ARM_PREL31
);
3907 /* Restore the original section. */
3908 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3910 unwind
.proc_start
= NULL
;
3914 /* Parse an unwind_cantunwind directive. */
3917 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3919 demand_empty_rest_of_line ();
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("personality routine specified for cantunwind frame"));
3926 unwind
.personality_index
= -2;
3930 /* Parse a personalityindex directive. */
3933 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3937 if (!unwind
.proc_start
)
3938 as_bad (MISSING_FNSTART
);
3940 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3941 as_bad (_("duplicate .personalityindex directive"));
3945 if (exp
.X_op
!= O_constant
3946 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3948 as_bad (_("bad personality routine number"));
3949 ignore_rest_of_line ();
3953 unwind
.personality_index
= exp
.X_add_number
;
3955 demand_empty_rest_of_line ();
3959 /* Parse a personality directive. */
3962 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3966 if (!unwind
.proc_start
)
3967 as_bad (MISSING_FNSTART
);
3969 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3970 as_bad (_("duplicate .personality directive"));
3972 c
= get_symbol_name (& name
);
3973 p
= input_line_pointer
;
3975 ++ input_line_pointer
;
3976 unwind
.personality_routine
= symbol_find_or_make (name
);
3978 demand_empty_rest_of_line ();
3982 /* Parse a directive saving core registers. */
3985 s_arm_unwind_save_core (void)
3991 range
= parse_reg_list (&input_line_pointer
);
3994 as_bad (_("expected register list"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4001 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4002 into .unwind_save {..., sp...}. We aren't bothered about the value of
4003 ip because it is clobbered by calls. */
4004 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4005 && (range
& 0x3000) == 0x1000)
4007 unwind
.opcode_count
--;
4008 unwind
.sp_restored
= 0;
4009 range
= (range
| 0x2000) & ~0x1000;
4010 unwind
.pending_offset
= 0;
4016 /* See if we can use the short opcodes. These pop a block of up to 8
4017 registers starting with r4, plus maybe r14. */
4018 for (n
= 0; n
< 8; n
++)
4020 /* Break at the first non-saved register. */
4021 if ((range
& (1 << (n
+ 4))) == 0)
4024 /* See if there are any other bits set. */
4025 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4027 /* Use the long form. */
4028 op
= 0x8000 | ((range
>> 4) & 0xfff);
4029 add_unwind_opcode (op
, 2);
4033 /* Use the short form. */
4035 op
= 0xa8; /* Pop r14. */
4037 op
= 0xa0; /* Do not pop r14. */
4039 add_unwind_opcode (op
, 1);
4046 op
= 0xb100 | (range
& 0xf);
4047 add_unwind_opcode (op
, 2);
4050 /* Record the number of bytes pushed. */
4051 for (n
= 0; n
< 16; n
++)
4053 if (range
& (1 << n
))
4054 unwind
.frame_size
+= 4;
4059 /* Parse a directive saving FPA registers. */
4062 s_arm_unwind_save_fpa (int reg
)
4068 /* Get Number of registers to transfer. */
4069 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4072 exp
.X_op
= O_illegal
;
4074 if (exp
.X_op
!= O_constant
)
4076 as_bad (_("expected , <constant>"));
4077 ignore_rest_of_line ();
4081 num_regs
= exp
.X_add_number
;
4083 if (num_regs
< 1 || num_regs
> 4)
4085 as_bad (_("number of registers must be in the range [1:4]"));
4086 ignore_rest_of_line ();
4090 demand_empty_rest_of_line ();
4095 op
= 0xb4 | (num_regs
- 1);
4096 add_unwind_opcode (op
, 1);
4101 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4102 add_unwind_opcode (op
, 2);
4104 unwind
.frame_size
+= num_regs
* 12;
4108 /* Parse a directive saving VFP registers for ARMv6 and above. */
4111 s_arm_unwind_save_vfp_armv6 (void)
4116 int num_vfpv3_regs
= 0;
4117 int num_regs_below_16
;
4119 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4122 as_bad (_("expected register list"));
4123 ignore_rest_of_line ();
4127 demand_empty_rest_of_line ();
4129 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4130 than FSTMX/FLDMX-style ones). */
4132 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4134 num_vfpv3_regs
= count
;
4135 else if (start
+ count
> 16)
4136 num_vfpv3_regs
= start
+ count
- 16;
4138 if (num_vfpv3_regs
> 0)
4140 int start_offset
= start
> 16 ? start
- 16 : 0;
4141 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4142 add_unwind_opcode (op
, 2);
4145 /* Generate opcode for registers numbered in the range 0 .. 15. */
4146 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4147 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4148 if (num_regs_below_16
> 0)
4150 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4151 add_unwind_opcode (op
, 2);
4154 unwind
.frame_size
+= count
* 8;
4158 /* Parse a directive saving VFP registers for pre-ARMv6. */
4161 s_arm_unwind_save_vfp (void)
4167 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4170 as_bad (_("expected register list"));
4171 ignore_rest_of_line ();
4175 demand_empty_rest_of_line ();
4180 op
= 0xb8 | (count
- 1);
4181 add_unwind_opcode (op
, 1);
4186 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4187 add_unwind_opcode (op
, 2);
4189 unwind
.frame_size
+= count
* 8 + 4;
4193 /* Parse a directive saving iWMMXt data registers. */
4196 s_arm_unwind_save_mmxwr (void)
4204 if (*input_line_pointer
== '{')
4205 input_line_pointer
++;
4209 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4213 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4218 as_tsktsk (_("register list not in ascending order"));
4221 if (*input_line_pointer
== '-')
4223 input_line_pointer
++;
4224 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4227 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4230 else if (reg
>= hi_reg
)
4232 as_bad (_("bad register range"));
4235 for (; reg
< hi_reg
; reg
++)
4239 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4241 skip_past_char (&input_line_pointer
, '}');
4243 demand_empty_rest_of_line ();
4245 /* Generate any deferred opcodes because we're going to be looking at
4247 flush_pending_unwind ();
4249 for (i
= 0; i
< 16; i
++)
4251 if (mask
& (1 << i
))
4252 unwind
.frame_size
+= 8;
4255 /* Attempt to combine with a previous opcode. We do this because gcc
4256 likes to output separate unwind directives for a single block of
4258 if (unwind
.opcode_count
> 0)
4260 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4261 if ((i
& 0xf8) == 0xc0)
4264 /* Only merge if the blocks are contiguous. */
4267 if ((mask
& 0xfe00) == (1 << 9))
4269 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4270 unwind
.opcode_count
--;
4273 else if (i
== 6 && unwind
.opcode_count
>= 2)
4275 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4279 op
= 0xffff << (reg
- 1);
4281 && ((mask
& op
) == (1u << (reg
- 1))))
4283 op
= (1 << (reg
+ i
+ 1)) - 1;
4284 op
&= ~((1 << reg
) - 1);
4286 unwind
.opcode_count
-= 2;
4293 /* We want to generate opcodes in the order the registers have been
4294 saved, ie. descending order. */
4295 for (reg
= 15; reg
>= -1; reg
--)
4297 /* Save registers in blocks. */
4299 || !(mask
& (1 << reg
)))
4301 /* We found an unsaved reg. Generate opcodes to save the
4308 op
= 0xc0 | (hi_reg
- 10);
4309 add_unwind_opcode (op
, 1);
4314 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4315 add_unwind_opcode (op
, 2);
4324 ignore_rest_of_line ();
4328 s_arm_unwind_save_mmxwcg (void)
4335 if (*input_line_pointer
== '{')
4336 input_line_pointer
++;
4338 skip_whitespace (input_line_pointer
);
4342 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4346 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4352 as_tsktsk (_("register list not in ascending order"));
4355 if (*input_line_pointer
== '-')
4357 input_line_pointer
++;
4358 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4361 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4364 else if (reg
>= hi_reg
)
4366 as_bad (_("bad register range"));
4369 for (; reg
< hi_reg
; reg
++)
4373 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4375 skip_past_char (&input_line_pointer
, '}');
4377 demand_empty_rest_of_line ();
4379 /* Generate any deferred opcodes because we're going to be looking at
4381 flush_pending_unwind ();
4383 for (reg
= 0; reg
< 16; reg
++)
4385 if (mask
& (1 << reg
))
4386 unwind
.frame_size
+= 4;
4389 add_unwind_opcode (op
, 2);
4392 ignore_rest_of_line ();
4396 /* Parse an unwind_save directive.
4397 If the argument is non-zero, this is a .vsave directive. */
4400 s_arm_unwind_save (int arch_v6
)
4403 struct reg_entry
*reg
;
4404 bfd_boolean had_brace
= FALSE
;
4406 if (!unwind
.proc_start
)
4407 as_bad (MISSING_FNSTART
);
4409 /* Figure out what sort of save we have. */
4410 peek
= input_line_pointer
;
4418 reg
= arm_reg_parse_multi (&peek
);
4422 as_bad (_("register expected"));
4423 ignore_rest_of_line ();
4432 as_bad (_("FPA .unwind_save does not take a register list"));
4433 ignore_rest_of_line ();
4436 input_line_pointer
= peek
;
4437 s_arm_unwind_save_fpa (reg
->number
);
4441 s_arm_unwind_save_core ();
4446 s_arm_unwind_save_vfp_armv6 ();
4448 s_arm_unwind_save_vfp ();
4451 case REG_TYPE_MMXWR
:
4452 s_arm_unwind_save_mmxwr ();
4455 case REG_TYPE_MMXWCG
:
4456 s_arm_unwind_save_mmxwcg ();
4460 as_bad (_(".unwind_save does not support this kind of register"));
4461 ignore_rest_of_line ();
4466 /* Parse an unwind_movsp directive. */
4469 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4475 if (!unwind
.proc_start
)
4476 as_bad (MISSING_FNSTART
);
4478 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4481 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4482 ignore_rest_of_line ();
4486 /* Optional constant. */
4487 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4489 if (immediate_for_directive (&offset
) == FAIL
)
4495 demand_empty_rest_of_line ();
4497 if (reg
== REG_SP
|| reg
== REG_PC
)
4499 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4503 if (unwind
.fp_reg
!= REG_SP
)
4504 as_bad (_("unexpected .unwind_movsp directive"));
4506 /* Generate opcode to restore the value. */
4508 add_unwind_opcode (op
, 1);
4510 /* Record the information for later. */
4511 unwind
.fp_reg
= reg
;
4512 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4513 unwind
.sp_restored
= 1;
4516 /* Parse an unwind_pad directive. */
4519 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4523 if (!unwind
.proc_start
)
4524 as_bad (MISSING_FNSTART
);
4526 if (immediate_for_directive (&offset
) == FAIL
)
4531 as_bad (_("stack increment must be multiple of 4"));
4532 ignore_rest_of_line ();
4536 /* Don't generate any opcodes, just record the details for later. */
4537 unwind
.frame_size
+= offset
;
4538 unwind
.pending_offset
+= offset
;
4540 demand_empty_rest_of_line ();
4543 /* Parse an unwind_setfp directive. */
4546 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4552 if (!unwind
.proc_start
)
4553 as_bad (MISSING_FNSTART
);
4555 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4556 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4561 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4563 as_bad (_("expected <reg>, <reg>"));
4564 ignore_rest_of_line ();
4568 /* Optional constant. */
4569 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4571 if (immediate_for_directive (&offset
) == FAIL
)
4577 demand_empty_rest_of_line ();
4579 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4581 as_bad (_("register must be either sp or set by a previous"
4582 "unwind_movsp directive"));
4586 /* Don't generate any opcodes, just record the information for later. */
4587 unwind
.fp_reg
= fp_reg
;
4589 if (sp_reg
== REG_SP
)
4590 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4592 unwind
.fp_offset
-= offset
;
4595 /* Parse an unwind_raw directive. */
4598 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4601 /* This is an arbitrary limit. */
4602 unsigned char op
[16];
4605 if (!unwind
.proc_start
)
4606 as_bad (MISSING_FNSTART
);
4609 if (exp
.X_op
== O_constant
4610 && skip_past_comma (&input_line_pointer
) != FAIL
)
4612 unwind
.frame_size
+= exp
.X_add_number
;
4616 exp
.X_op
= O_illegal
;
4618 if (exp
.X_op
!= O_constant
)
4620 as_bad (_("expected <offset>, <opcode>"));
4621 ignore_rest_of_line ();
4627 /* Parse the opcode. */
4632 as_bad (_("unwind opcode too long"));
4633 ignore_rest_of_line ();
4635 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4637 as_bad (_("invalid unwind opcode"));
4638 ignore_rest_of_line ();
4641 op
[count
++] = exp
.X_add_number
;
4643 /* Parse the next byte. */
4644 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4650 /* Add the opcode bytes in reverse order. */
4652 add_unwind_opcode (op
[count
], 1);
4654 demand_empty_rest_of_line ();
4658 /* Parse a .eabi_attribute directive. */
4661 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4663 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4665 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4666 attributes_set_explicitly
[tag
] = 1;
4669 /* Emit a tls fix for the symbol. */
4672 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4676 #ifdef md_flush_pending_output
4677 md_flush_pending_output ();
4680 #ifdef md_cons_align
4684 /* Since we're just labelling the code, there's no need to define a
4687 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4688 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4689 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4690 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4692 #endif /* OBJ_ELF */
4694 static void s_arm_arch (int);
4695 static void s_arm_object_arch (int);
4696 static void s_arm_cpu (int);
4697 static void s_arm_fpu (int);
4698 static void s_arm_arch_extension (int);
4703 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4710 if (exp
.X_op
== O_symbol
)
4711 exp
.X_op
= O_secrel
;
4713 emit_expr (&exp
, 4);
4715 while (*input_line_pointer
++ == ',');
4717 input_line_pointer
--;
4718 demand_empty_rest_of_line ();
4722 /* This table describes all the machine specific pseudo-ops the assembler
4723 has to support. The fields are:
4724 pseudo-op name without dot
4725 function to call to execute this pseudo-op
4726 Integer arg to pass to the function. */
4728 const pseudo_typeS md_pseudo_table
[] =
4730 /* Never called because '.req' does not start a line. */
4731 { "req", s_req
, 0 },
4732 /* Following two are likewise never called. */
4735 { "unreq", s_unreq
, 0 },
4736 { "bss", s_bss
, 0 },
4737 { "align", s_align_ptwo
, 2 },
4738 { "arm", s_arm
, 0 },
4739 { "thumb", s_thumb
, 0 },
4740 { "code", s_code
, 0 },
4741 { "force_thumb", s_force_thumb
, 0 },
4742 { "thumb_func", s_thumb_func
, 0 },
4743 { "thumb_set", s_thumb_set
, 0 },
4744 { "even", s_even
, 0 },
4745 { "ltorg", s_ltorg
, 0 },
4746 { "pool", s_ltorg
, 0 },
4747 { "syntax", s_syntax
, 0 },
4748 { "cpu", s_arm_cpu
, 0 },
4749 { "arch", s_arm_arch
, 0 },
4750 { "object_arch", s_arm_object_arch
, 0 },
4751 { "fpu", s_arm_fpu
, 0 },
4752 { "arch_extension", s_arm_arch_extension
, 0 },
4754 { "word", s_arm_elf_cons
, 4 },
4755 { "long", s_arm_elf_cons
, 4 },
4756 { "inst.n", s_arm_elf_inst
, 2 },
4757 { "inst.w", s_arm_elf_inst
, 4 },
4758 { "inst", s_arm_elf_inst
, 0 },
4759 { "rel31", s_arm_rel31
, 0 },
4760 { "fnstart", s_arm_unwind_fnstart
, 0 },
4761 { "fnend", s_arm_unwind_fnend
, 0 },
4762 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4763 { "personality", s_arm_unwind_personality
, 0 },
4764 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4765 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4766 { "save", s_arm_unwind_save
, 0 },
4767 { "vsave", s_arm_unwind_save
, 1 },
4768 { "movsp", s_arm_unwind_movsp
, 0 },
4769 { "pad", s_arm_unwind_pad
, 0 },
4770 { "setfp", s_arm_unwind_setfp
, 0 },
4771 { "unwind_raw", s_arm_unwind_raw
, 0 },
4772 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4773 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4777 /* These are used for dwarf. */
4781 /* These are used for dwarf2. */
4782 { "file", dwarf2_directive_file
, 0 },
4783 { "loc", dwarf2_directive_loc
, 0 },
4784 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4786 { "extend", float_cons
, 'x' },
4787 { "ldouble", float_cons
, 'x' },
4788 { "packed", float_cons
, 'p' },
4790 {"secrel32", pe_directive_secrel
, 0},
4793 /* These are for compatibility with CodeComposer Studio. */
4794 {"ref", s_ccs_ref
, 0},
4795 {"def", s_ccs_def
, 0},
4796 {"asmfunc", s_ccs_asmfunc
, 0},
4797 {"endasmfunc", s_ccs_endasmfunc
, 0},
4802 /* Parser functions used exclusively in instruction operands. */
4804 /* Generic immediate-value read function for use in insn parsing.
4805 STR points to the beginning of the immediate (the leading #);
4806 VAL receives the value; if the value is outside [MIN, MAX]
4807 issue an error. PREFIX_OPT is true if the immediate prefix is
4811 parse_immediate (char **str
, int *val
, int min
, int max
,
4812 bfd_boolean prefix_opt
)
4816 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4817 if (exp
.X_op
!= O_constant
)
4819 inst
.error
= _("constant expression required");
4823 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4825 inst
.error
= _("immediate value out of range");
4829 *val
= exp
.X_add_number
;
4833 /* Less-generic immediate-value read function with the possibility of loading a
4834 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4835 instructions. Puts the result directly in inst.operands[i]. */
4838 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4839 bfd_boolean allow_symbol_p
)
4842 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4845 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4847 if (exp_p
->X_op
== O_constant
)
4849 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4850 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4851 O_constant. We have to be careful not to break compilation for
4852 32-bit X_add_number, though. */
4853 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4855 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4856 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4858 inst
.operands
[i
].regisimm
= 1;
4861 else if (exp_p
->X_op
== O_big
4862 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4864 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4866 /* Bignums have their least significant bits in
4867 generic_bignum[0]. Make sure we put 32 bits in imm and
4868 32 bits in reg, in a (hopefully) portable way. */
4869 gas_assert (parts
!= 0);
4871 /* Make sure that the number is not too big.
4872 PR 11972: Bignums can now be sign-extended to the
4873 size of a .octa so check that the out of range bits
4874 are all zero or all one. */
4875 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4877 LITTLENUM_TYPE m
= -1;
4879 if (generic_bignum
[parts
* 2] != 0
4880 && generic_bignum
[parts
* 2] != m
)
4883 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4884 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4888 inst
.operands
[i
].imm
= 0;
4889 for (j
= 0; j
< parts
; j
++, idx
++)
4890 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4891 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4892 inst
.operands
[i
].reg
= 0;
4893 for (j
= 0; j
< parts
; j
++, idx
++)
4894 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4895 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4896 inst
.operands
[i
].regisimm
= 1;
4898 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4906 /* Returns the pseudo-register number of an FPA immediate constant,
4907 or FAIL if there isn't a valid constant here. */
4910 parse_fpa_immediate (char ** str
)
4912 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4918 /* First try and match exact strings, this is to guarantee
4919 that some formats will work even for cross assembly. */
4921 for (i
= 0; fp_const
[i
]; i
++)
4923 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4927 *str
+= strlen (fp_const
[i
]);
4928 if (is_end_of_line
[(unsigned char) **str
])
4934 /* Just because we didn't get a match doesn't mean that the constant
4935 isn't valid, just that it is in a format that we don't
4936 automatically recognize. Try parsing it with the standard
4937 expression routines. */
4939 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4941 /* Look for a raw floating point number. */
4942 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4943 && is_end_of_line
[(unsigned char) *save_in
])
4945 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4947 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4949 if (words
[j
] != fp_values
[i
][j
])
4953 if (j
== MAX_LITTLENUMS
)
4961 /* Try and parse a more complex expression, this will probably fail
4962 unless the code uses a floating point prefix (eg "0f"). */
4963 save_in
= input_line_pointer
;
4964 input_line_pointer
= *str
;
4965 if (expression (&exp
) == absolute_section
4966 && exp
.X_op
== O_big
4967 && exp
.X_add_number
< 0)
4969 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4971 #define X_PRECISION 5
4972 #define E_PRECISION 15L
4973 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4975 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4977 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4979 if (words
[j
] != fp_values
[i
][j
])
4983 if (j
== MAX_LITTLENUMS
)
4985 *str
= input_line_pointer
;
4986 input_line_pointer
= save_in
;
4993 *str
= input_line_pointer
;
4994 input_line_pointer
= save_in
;
4995 inst
.error
= _("invalid FPA immediate expression");
4999 /* Returns 1 if a number has "quarter-precision" float format
5000 0baBbbbbbc defgh000 00000000 00000000. */
5003 is_quarter_float (unsigned imm
)
5005 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5006 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5010 /* Detect the presence of a floating point or integer zero constant,
5014 parse_ifimm_zero (char **in
)
5018 if (!is_immediate_prefix (**in
))
5020 /* In unified syntax, all prefixes are optional. */
5021 if (!unified_syntax
)
5027 /* Accept #0x0 as a synonym for #0. */
5028 if (strncmp (*in
, "0x", 2) == 0)
5031 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5036 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5037 &generic_floating_point_number
);
5040 && generic_floating_point_number
.sign
== '+'
5041 && (generic_floating_point_number
.low
5042 > generic_floating_point_number
.leader
))
5048 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5049 0baBbbbbbc defgh000 00000000 00000000.
5050 The zero and minus-zero cases need special handling, since they can't be
5051 encoded in the "quarter-precision" float format, but can nonetheless be
5052 loaded as integer constants. */
5055 parse_qfloat_immediate (char **ccp
, int *immed
)
5059 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5060 int found_fpchar
= 0;
5062 skip_past_char (&str
, '#');
5064 /* We must not accidentally parse an integer as a floating-point number. Make
5065 sure that the value we parse is not an integer by checking for special
5066 characters '.' or 'e'.
5067 FIXME: This is a horrible hack, but doing better is tricky because type
5068 information isn't in a very usable state at parse time. */
5070 skip_whitespace (fpnum
);
5072 if (strncmp (fpnum
, "0x", 2) == 0)
5076 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5077 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5087 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5089 unsigned fpword
= 0;
5092 /* Our FP word must be 32 bits (single-precision FP). */
5093 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5095 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5099 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5112 /* Shift operands. */
5115 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5118 struct asm_shift_name
5121 enum shift_kind kind
;
5124 /* Third argument to parse_shift. */
5125 enum parse_shift_mode
5127 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5128 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5129 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5130 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5131 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5134 /* Parse a <shift> specifier on an ARM data processing instruction.
5135 This has three forms:
5137 (LSL|LSR|ASL|ASR|ROR) Rs
5138 (LSL|LSR|ASL|ASR|ROR) #imm
5141 Note that ASL is assimilated to LSL in the instruction encoding, and
5142 RRX to ROR #0 (which cannot be written as such). */
5145 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5147 const struct asm_shift_name
*shift_name
;
5148 enum shift_kind shift
;
5153 for (p
= *str
; ISALPHA (*p
); p
++)
5158 inst
.error
= _("shift expression expected");
5162 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5165 if (shift_name
== NULL
)
5167 inst
.error
= _("shift expression expected");
5171 shift
= shift_name
->kind
;
5175 case NO_SHIFT_RESTRICT
:
5176 case SHIFT_IMMEDIATE
: break;
5178 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5179 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5181 inst
.error
= _("'LSL' or 'ASR' required");
5186 case SHIFT_LSL_IMMEDIATE
:
5187 if (shift
!= SHIFT_LSL
)
5189 inst
.error
= _("'LSL' required");
5194 case SHIFT_ASR_IMMEDIATE
:
5195 if (shift
!= SHIFT_ASR
)
5197 inst
.error
= _("'ASR' required");
5205 if (shift
!= SHIFT_RRX
)
5207 /* Whitespace can appear here if the next thing is a bare digit. */
5208 skip_whitespace (p
);
5210 if (mode
== NO_SHIFT_RESTRICT
5211 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5213 inst
.operands
[i
].imm
= reg
;
5214 inst
.operands
[i
].immisreg
= 1;
5216 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5219 inst
.operands
[i
].shift_kind
= shift
;
5220 inst
.operands
[i
].shifted
= 1;
5225 /* Parse a <shifter_operand> for an ARM data processing instruction:
5228 #<immediate>, <rotate>
5232 where <shift> is defined by parse_shift above, and <rotate> is a
5233 multiple of 2 between 0 and 30. Validation of immediate operands
5234 is deferred to md_apply_fix. */
5237 parse_shifter_operand (char **str
, int i
)
5242 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5244 inst
.operands
[i
].reg
= value
;
5245 inst
.operands
[i
].isreg
= 1;
5247 /* parse_shift will override this if appropriate */
5248 inst
.relocs
[0].exp
.X_op
= O_constant
;
5249 inst
.relocs
[0].exp
.X_add_number
= 0;
5251 if (skip_past_comma (str
) == FAIL
)
5254 /* Shift operation on register. */
5255 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5258 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5261 if (skip_past_comma (str
) == SUCCESS
)
5263 /* #x, y -- ie explicit rotation by Y. */
5264 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5267 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5269 inst
.error
= _("constant expression expected");
5273 value
= exp
.X_add_number
;
5274 if (value
< 0 || value
> 30 || value
% 2 != 0)
5276 inst
.error
= _("invalid rotation");
5279 if (inst
.relocs
[0].exp
.X_add_number
< 0
5280 || inst
.relocs
[0].exp
.X_add_number
> 255)
5282 inst
.error
= _("invalid constant");
5286 /* Encode as specified. */
5287 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5291 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5292 inst
.relocs
[0].pc_rel
= 0;
5296 /* Group relocation information. Each entry in the table contains the
5297 textual name of the relocation as may appear in assembler source
5298 and must end with a colon.
5299 Along with this textual name are the relocation codes to be used if
5300 the corresponding instruction is an ALU instruction (ADD or SUB only),
5301 an LDR, an LDRS, or an LDC. */
5303 struct group_reloc_table_entry
5314 /* Varieties of non-ALU group relocation. */
5321 static struct group_reloc_table_entry group_reloc_table
[] =
5322 { /* Program counter relative: */
5324 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5329 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5330 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5331 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5332 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5334 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5339 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5340 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5341 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5342 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5344 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5345 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5346 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5347 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5348 /* Section base relative */
5350 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5355 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5356 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5357 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5358 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5360 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5365 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5366 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5367 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5368 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5370 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5371 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5372 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5373 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5374 /* Absolute thumb alu relocations. */
5376 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5381 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5386 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5391 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5396 /* Given the address of a pointer pointing to the textual name of a group
5397 relocation as may appear in assembler source, attempt to find its details
5398 in group_reloc_table. The pointer will be updated to the character after
5399 the trailing colon. On failure, FAIL will be returned; SUCCESS
5400 otherwise. On success, *entry will be updated to point at the relevant
5401 group_reloc_table entry. */
5404 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5407 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5409 int length
= strlen (group_reloc_table
[i
].name
);
5411 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5412 && (*str
)[length
] == ':')
5414 *out
= &group_reloc_table
[i
];
5415 *str
+= (length
+ 1);
5423 /* Parse a <shifter_operand> for an ARM data processing instruction
5424 (as for parse_shifter_operand) where group relocations are allowed:
5427 #<immediate>, <rotate>
5428 #:<group_reloc>:<expression>
5432 where <group_reloc> is one of the strings defined in group_reloc_table.
5433 The hashes are optional.
5435 Everything else is as for parse_shifter_operand. */
5437 static parse_operand_result
5438 parse_shifter_operand_group_reloc (char **str
, int i
)
5440 /* Determine if we have the sequence of characters #: or just :
5441 coming next. If we do, then we check for a group relocation.
5442 If we don't, punt the whole lot to parse_shifter_operand. */
5444 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5445 || (*str
)[0] == ':')
5447 struct group_reloc_table_entry
*entry
;
5449 if ((*str
)[0] == '#')
5454 /* Try to parse a group relocation. Anything else is an error. */
5455 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5457 inst
.error
= _("unknown group relocation");
5458 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5461 /* We now have the group relocation table entry corresponding to
5462 the name in the assembler source. Next, we parse the expression. */
5463 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5464 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5466 /* Record the relocation type (always the ALU variant here). */
5467 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5468 gas_assert (inst
.relocs
[0].type
!= 0);
5470 return PARSE_OPERAND_SUCCESS
;
5473 return parse_shifter_operand (str
, i
) == SUCCESS
5474 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5476 /* Never reached. */
5479 /* Parse a Neon alignment expression. Information is written to
5480 inst.operands[i]. We assume the initial ':' has been skipped.
5482 align .imm = align << 8, .immisalign=1, .preind=0 */
5483 static parse_operand_result
5484 parse_neon_alignment (char **str
, int i
)
5489 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5491 if (exp
.X_op
!= O_constant
)
5493 inst
.error
= _("alignment must be constant");
5494 return PARSE_OPERAND_FAIL
;
5497 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5498 inst
.operands
[i
].immisalign
= 1;
5499 /* Alignments are not pre-indexes. */
5500 inst
.operands
[i
].preind
= 0;
5503 return PARSE_OPERAND_SUCCESS
;
5506 /* Parse all forms of an ARM address expression. Information is written
5507 to inst.operands[i] and/or inst.relocs[0].
5509 Preindexed addressing (.preind=1):
5511 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5512 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5513 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5514 .shift_kind=shift .relocs[0].exp=shift_imm
5516 These three may have a trailing ! which causes .writeback to be set also.
5518 Postindexed addressing (.postind=1, .writeback=1):
5520 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5521 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5522 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5523 .shift_kind=shift .relocs[0].exp=shift_imm
5525 Unindexed addressing (.preind=0, .postind=0):
5527 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5531 [Rn]{!} shorthand for [Rn,#0]{!}
5532 =immediate .isreg=0 .relocs[0].exp=immediate
5533 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5535 It is the caller's responsibility to check for addressing modes not
5536 supported by the instruction, and to set inst.relocs[0].type. */
5538 static parse_operand_result
5539 parse_address_main (char **str
, int i
, int group_relocations
,
5540 group_reloc_type group_type
)
5545 if (skip_past_char (&p
, '[') == FAIL
)
5547 if (skip_past_char (&p
, '=') == FAIL
)
5549 /* Bare address - translate to PC-relative offset. */
5550 inst
.relocs
[0].pc_rel
= 1;
5551 inst
.operands
[i
].reg
= REG_PC
;
5552 inst
.operands
[i
].isreg
= 1;
5553 inst
.operands
[i
].preind
= 1;
5555 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5556 return PARSE_OPERAND_FAIL
;
5558 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5559 /*allow_symbol_p=*/TRUE
))
5560 return PARSE_OPERAND_FAIL
;
5563 return PARSE_OPERAND_SUCCESS
;
5566 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5567 skip_whitespace (p
);
5569 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5571 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5572 return PARSE_OPERAND_FAIL
;
5574 inst
.operands
[i
].reg
= reg
;
5575 inst
.operands
[i
].isreg
= 1;
5577 if (skip_past_comma (&p
) == SUCCESS
)
5579 inst
.operands
[i
].preind
= 1;
5582 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5584 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5586 inst
.operands
[i
].imm
= reg
;
5587 inst
.operands
[i
].immisreg
= 1;
5589 if (skip_past_comma (&p
) == SUCCESS
)
5590 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5591 return PARSE_OPERAND_FAIL
;
5593 else if (skip_past_char (&p
, ':') == SUCCESS
)
5595 /* FIXME: '@' should be used here, but it's filtered out by generic
5596 code before we get to see it here. This may be subject to
5598 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5600 if (result
!= PARSE_OPERAND_SUCCESS
)
5605 if (inst
.operands
[i
].negative
)
5607 inst
.operands
[i
].negative
= 0;
5611 if (group_relocations
5612 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5614 struct group_reloc_table_entry
*entry
;
5616 /* Skip over the #: or : sequence. */
5622 /* Try to parse a group relocation. Anything else is an
5624 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5626 inst
.error
= _("unknown group relocation");
5627 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5630 /* We now have the group relocation table entry corresponding to
5631 the name in the assembler source. Next, we parse the
5633 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5634 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5636 /* Record the relocation type. */
5641 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5646 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5651 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5658 if (inst
.relocs
[0].type
== 0)
5660 inst
.error
= _("this group relocation is not allowed on this instruction");
5661 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5668 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5669 return PARSE_OPERAND_FAIL
;
5670 /* If the offset is 0, find out if it's a +0 or -0. */
5671 if (inst
.relocs
[0].exp
.X_op
== O_constant
5672 && inst
.relocs
[0].exp
.X_add_number
== 0)
5674 skip_whitespace (q
);
5678 skip_whitespace (q
);
5681 inst
.operands
[i
].negative
= 1;
5686 else if (skip_past_char (&p
, ':') == SUCCESS
)
5688 /* FIXME: '@' should be used here, but it's filtered out by generic code
5689 before we get to see it here. This may be subject to change. */
5690 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5692 if (result
!= PARSE_OPERAND_SUCCESS
)
5696 if (skip_past_char (&p
, ']') == FAIL
)
5698 inst
.error
= _("']' expected");
5699 return PARSE_OPERAND_FAIL
;
5702 if (skip_past_char (&p
, '!') == SUCCESS
)
5703 inst
.operands
[i
].writeback
= 1;
5705 else if (skip_past_comma (&p
) == SUCCESS
)
5707 if (skip_past_char (&p
, '{') == SUCCESS
)
5709 /* [Rn], {expr} - unindexed, with option */
5710 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5711 0, 255, TRUE
) == FAIL
)
5712 return PARSE_OPERAND_FAIL
;
5714 if (skip_past_char (&p
, '}') == FAIL
)
5716 inst
.error
= _("'}' expected at end of 'option' field");
5717 return PARSE_OPERAND_FAIL
;
5719 if (inst
.operands
[i
].preind
)
5721 inst
.error
= _("cannot combine index with option");
5722 return PARSE_OPERAND_FAIL
;
5725 return PARSE_OPERAND_SUCCESS
;
5729 inst
.operands
[i
].postind
= 1;
5730 inst
.operands
[i
].writeback
= 1;
5732 if (inst
.operands
[i
].preind
)
5734 inst
.error
= _("cannot combine pre- and post-indexing");
5735 return PARSE_OPERAND_FAIL
;
5739 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5741 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5743 /* We might be using the immediate for alignment already. If we
5744 are, OR the register number into the low-order bits. */
5745 if (inst
.operands
[i
].immisalign
)
5746 inst
.operands
[i
].imm
|= reg
;
5748 inst
.operands
[i
].imm
= reg
;
5749 inst
.operands
[i
].immisreg
= 1;
5751 if (skip_past_comma (&p
) == SUCCESS
)
5752 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5753 return PARSE_OPERAND_FAIL
;
5759 if (inst
.operands
[i
].negative
)
5761 inst
.operands
[i
].negative
= 0;
5764 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5765 return PARSE_OPERAND_FAIL
;
5766 /* If the offset is 0, find out if it's a +0 or -0. */
5767 if (inst
.relocs
[0].exp
.X_op
== O_constant
5768 && inst
.relocs
[0].exp
.X_add_number
== 0)
5770 skip_whitespace (q
);
5774 skip_whitespace (q
);
5777 inst
.operands
[i
].negative
= 1;
5783 /* If at this point neither .preind nor .postind is set, we have a
5784 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5785 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5787 inst
.operands
[i
].preind
= 1;
5788 inst
.relocs
[0].exp
.X_op
= O_constant
;
5789 inst
.relocs
[0].exp
.X_add_number
= 0;
5792 return PARSE_OPERAND_SUCCESS
;
5796 parse_address (char **str
, int i
)
5798 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5802 static parse_operand_result
5803 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5805 return parse_address_main (str
, i
, 1, type
);
5808 /* Parse an operand for a MOVW or MOVT instruction. */
5810 parse_half (char **str
)
5815 skip_past_char (&p
, '#');
5816 if (strncasecmp (p
, ":lower16:", 9) == 0)
5817 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
5818 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5819 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
5821 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
5824 skip_whitespace (p
);
5827 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5830 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
5832 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
5834 inst
.error
= _("constant expression expected");
5837 if (inst
.relocs
[0].exp
.X_add_number
< 0
5838 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
5840 inst
.error
= _("immediate value out of range");
5848 /* Miscellaneous. */
5850 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5851 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5853 parse_psr (char **str
, bfd_boolean lhs
)
5856 unsigned long psr_field
;
5857 const struct asm_psr
*psr
;
5859 bfd_boolean is_apsr
= FALSE
;
5860 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5862 /* PR gas/12698: If the user has specified -march=all then m_profile will
5863 be TRUE, but we want to ignore it in this case as we are building for any
5864 CPU type, including non-m variants. */
5865 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5868 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5869 feature for ease of use and backwards compatibility. */
5871 if (strncasecmp (p
, "SPSR", 4) == 0)
5874 goto unsupported_psr
;
5876 psr_field
= SPSR_BIT
;
5878 else if (strncasecmp (p
, "CPSR", 4) == 0)
5881 goto unsupported_psr
;
5885 else if (strncasecmp (p
, "APSR", 4) == 0)
5887 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5888 and ARMv7-R architecture CPUs. */
5897 while (ISALNUM (*p
) || *p
== '_');
5899 if (strncasecmp (start
, "iapsr", 5) == 0
5900 || strncasecmp (start
, "eapsr", 5) == 0
5901 || strncasecmp (start
, "xpsr", 4) == 0
5902 || strncasecmp (start
, "psr", 3) == 0)
5903 p
= start
+ strcspn (start
, "rR") + 1;
5905 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5911 /* If APSR is being written, a bitfield may be specified. Note that
5912 APSR itself is handled above. */
5913 if (psr
->field
<= 3)
5915 psr_field
= psr
->field
;
5921 /* M-profile MSR instructions have the mask field set to "10", except
5922 *PSR variants which modify APSR, which may use a different mask (and
5923 have been handled already). Do that by setting the PSR_f field
5925 return psr
->field
| (lhs
? PSR_f
: 0);
5928 goto unsupported_psr
;
5934 /* A suffix follows. */
5940 while (ISALNUM (*p
) || *p
== '_');
5944 /* APSR uses a notation for bits, rather than fields. */
5945 unsigned int nzcvq_bits
= 0;
5946 unsigned int g_bit
= 0;
5949 for (bit
= start
; bit
!= p
; bit
++)
5951 switch (TOLOWER (*bit
))
5954 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5958 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5962 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5966 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5970 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5974 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5978 inst
.error
= _("unexpected bit specified after APSR");
5983 if (nzcvq_bits
== 0x1f)
5988 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5990 inst
.error
= _("selected processor does not "
5991 "support DSP extension");
5998 if ((nzcvq_bits
& 0x20) != 0
5999 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6000 || (g_bit
& 0x2) != 0)
6002 inst
.error
= _("bad bitmask specified after APSR");
6008 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6013 psr_field
|= psr
->field
;
6019 goto error
; /* Garbage after "[CS]PSR". */
6021 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6022 is deprecated, but allow it anyway. */
6026 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6029 else if (!m_profile
)
6030 /* These bits are never right for M-profile devices: don't set them
6031 (only code paths which read/write APSR reach here). */
6032 psr_field
|= (PSR_c
| PSR_f
);
6038 inst
.error
= _("selected processor does not support requested special "
6039 "purpose register");
6043 inst
.error
= _("flag for {c}psr instruction expected");
6047 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6048 value suitable for splatting into the AIF field of the instruction. */
6051 parse_cps_flags (char **str
)
6060 case '\0': case ',':
6063 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6064 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6065 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6068 inst
.error
= _("unrecognized CPS flag");
6073 if (saw_a_flag
== 0)
6075 inst
.error
= _("missing CPS flags");
6083 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6084 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6087 parse_endian_specifier (char **str
)
6092 if (strncasecmp (s
, "BE", 2))
6094 else if (strncasecmp (s
, "LE", 2))
6098 inst
.error
= _("valid endian specifiers are be or le");
6102 if (ISALNUM (s
[2]) || s
[2] == '_')
6104 inst
.error
= _("valid endian specifiers are be or le");
6109 return little_endian
;
6112 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6113 value suitable for poking into the rotate field of an sxt or sxta
6114 instruction, or FAIL on error. */
6117 parse_ror (char **str
)
6122 if (strncasecmp (s
, "ROR", 3) == 0)
6126 inst
.error
= _("missing rotation field after comma");
6130 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6135 case 0: *str
= s
; return 0x0;
6136 case 8: *str
= s
; return 0x1;
6137 case 16: *str
= s
; return 0x2;
6138 case 24: *str
= s
; return 0x3;
6141 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6146 /* Parse a conditional code (from conds[] below). The value returned is in the
6147 range 0 .. 14, or FAIL. */
6149 parse_cond (char **str
)
6152 const struct asm_cond
*c
;
6154 /* Condition codes are always 2 characters, so matching up to
6155 3 characters is sufficient. */
6160 while (ISALPHA (*q
) && n
< 3)
6162 cond
[n
] = TOLOWER (*q
);
6167 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6170 inst
.error
= _("condition required");
6178 /* Record a use of the given feature. */
6180 record_feature_use (const arm_feature_set
*feature
)
6183 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6185 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6188 /* If the given feature is currently allowed, mark it as used and return TRUE.
6189 Return FALSE otherwise. */
6191 mark_feature_used (const arm_feature_set
*feature
)
6193 /* Ensure the option is currently allowed. */
6194 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6197 /* Add the appropriate architecture feature for the barrier option used. */
6198 record_feature_use (feature
);
6203 /* Parse an option for a barrier instruction. Returns the encoding for the
6206 parse_barrier (char **str
)
6209 const struct asm_barrier_opt
*o
;
6212 while (ISALPHA (*q
))
6215 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6220 if (!mark_feature_used (&o
->arch
))
6227 /* Parse the operands of a table branch instruction. Similar to a memory
6230 parse_tb (char **str
)
6235 if (skip_past_char (&p
, '[') == FAIL
)
6237 inst
.error
= _("'[' expected");
6241 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6243 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6246 inst
.operands
[0].reg
= reg
;
6248 if (skip_past_comma (&p
) == FAIL
)
6250 inst
.error
= _("',' expected");
6254 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6256 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6259 inst
.operands
[0].imm
= reg
;
6261 if (skip_past_comma (&p
) == SUCCESS
)
6263 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6265 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6267 inst
.error
= _("invalid shift");
6270 inst
.operands
[0].shifted
= 1;
6273 if (skip_past_char (&p
, ']') == FAIL
)
6275 inst
.error
= _("']' expected");
6282 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6283 information on the types the operands can take and how they are encoded.
6284 Up to four operands may be read; this function handles setting the
6285 ".present" field for each read operand itself.
6286 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6287 else returns FAIL. */
6290 parse_neon_mov (char **str
, int *which_operand
)
6292 int i
= *which_operand
, val
;
6293 enum arm_reg_type rtype
;
6295 struct neon_type_el optype
;
6297 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6299 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6300 inst
.operands
[i
].reg
= val
;
6301 inst
.operands
[i
].isscalar
= 1;
6302 inst
.operands
[i
].vectype
= optype
;
6303 inst
.operands
[i
++].present
= 1;
6305 if (skip_past_comma (&ptr
) == FAIL
)
6308 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].present
= 1;
6315 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6318 /* Cases 0, 1, 2, 3, 5 (D only). */
6319 if (skip_past_comma (&ptr
) == FAIL
)
6322 inst
.operands
[i
].reg
= val
;
6323 inst
.operands
[i
].isreg
= 1;
6324 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6325 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6326 inst
.operands
[i
].isvec
= 1;
6327 inst
.operands
[i
].vectype
= optype
;
6328 inst
.operands
[i
++].present
= 1;
6330 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6332 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6333 Case 13: VMOV <Sd>, <Rm> */
6334 inst
.operands
[i
].reg
= val
;
6335 inst
.operands
[i
].isreg
= 1;
6336 inst
.operands
[i
].present
= 1;
6338 if (rtype
== REG_TYPE_NQ
)
6340 first_error (_("can't use Neon quad register here"));
6343 else if (rtype
!= REG_TYPE_VFS
)
6346 if (skip_past_comma (&ptr
) == FAIL
)
6348 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6350 inst
.operands
[i
].reg
= val
;
6351 inst
.operands
[i
].isreg
= 1;
6352 inst
.operands
[i
].present
= 1;
6355 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6358 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6359 Case 1: VMOV<c><q> <Dd>, <Dm>
6360 Case 8: VMOV.F32 <Sd>, <Sm>
6361 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6363 inst
.operands
[i
].reg
= val
;
6364 inst
.operands
[i
].isreg
= 1;
6365 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6366 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].vectype
= optype
;
6369 inst
.operands
[i
].present
= 1;
6371 if (skip_past_comma (&ptr
) == SUCCESS
)
6376 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6379 inst
.operands
[i
].reg
= val
;
6380 inst
.operands
[i
].isreg
= 1;
6381 inst
.operands
[i
++].present
= 1;
6383 if (skip_past_comma (&ptr
) == FAIL
)
6386 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6389 inst
.operands
[i
].reg
= val
;
6390 inst
.operands
[i
].isreg
= 1;
6391 inst
.operands
[i
].present
= 1;
6394 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6395 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6396 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6397 Case 10: VMOV.F32 <Sd>, #<imm>
6398 Case 11: VMOV.F64 <Dd>, #<imm> */
6399 inst
.operands
[i
].immisfloat
= 1;
6400 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6402 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6403 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6407 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6411 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6414 inst
.operands
[i
].reg
= val
;
6415 inst
.operands
[i
].isreg
= 1;
6416 inst
.operands
[i
++].present
= 1;
6418 if (skip_past_comma (&ptr
) == FAIL
)
6421 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6423 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6424 inst
.operands
[i
].reg
= val
;
6425 inst
.operands
[i
].isscalar
= 1;
6426 inst
.operands
[i
].present
= 1;
6427 inst
.operands
[i
].vectype
= optype
;
6429 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6431 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6432 inst
.operands
[i
].reg
= val
;
6433 inst
.operands
[i
].isreg
= 1;
6434 inst
.operands
[i
++].present
= 1;
6436 if (skip_past_comma (&ptr
) == FAIL
)
6439 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6442 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6446 inst
.operands
[i
].reg
= val
;
6447 inst
.operands
[i
].isreg
= 1;
6448 inst
.operands
[i
].isvec
= 1;
6449 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6450 inst
.operands
[i
].vectype
= optype
;
6451 inst
.operands
[i
].present
= 1;
6453 if (rtype
== REG_TYPE_VFS
)
6457 if (skip_past_comma (&ptr
) == FAIL
)
6459 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6462 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6465 inst
.operands
[i
].reg
= val
;
6466 inst
.operands
[i
].isreg
= 1;
6467 inst
.operands
[i
].isvec
= 1;
6468 inst
.operands
[i
].issingle
= 1;
6469 inst
.operands
[i
].vectype
= optype
;
6470 inst
.operands
[i
].present
= 1;
6473 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6477 inst
.operands
[i
].reg
= val
;
6478 inst
.operands
[i
].isreg
= 1;
6479 inst
.operands
[i
].isvec
= 1;
6480 inst
.operands
[i
].issingle
= 1;
6481 inst
.operands
[i
].vectype
= optype
;
6482 inst
.operands
[i
].present
= 1;
6487 first_error (_("parse error"));
6491 /* Successfully parsed the operands. Update args. */
6497 first_error (_("expected comma"));
6501 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6505 /* Use this macro when the operand constraints are different
6506 for ARM and THUMB (e.g. ldrd). */
6507 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6508 ((arm_operand) | ((thumb_operand) << 16))
6510 /* Matcher codes for parse_operands. */
6511 enum operand_parse_code
6513 OP_stop
, /* end of line */
6515 OP_RR
, /* ARM register */
6516 OP_RRnpc
, /* ARM register, not r15 */
6517 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6518 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6519 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6520 optional trailing ! */
6521 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6522 OP_RCP
, /* Coprocessor number */
6523 OP_RCN
, /* Coprocessor register */
6524 OP_RF
, /* FPA register */
6525 OP_RVS
, /* VFP single precision register */
6526 OP_RVD
, /* VFP double precision register (0..15) */
6527 OP_RND
, /* Neon double precision register (0..31) */
6528 OP_RNQ
, /* Neon quad precision register */
6529 OP_RVSD
, /* VFP single or double precision register */
6530 OP_RNSD
, /* Neon single or double precision register */
6531 OP_RNDQ
, /* Neon double or quad precision register */
6532 OP_RNSDQ
, /* Neon single, double or quad precision register */
6533 OP_RNSC
, /* Neon scalar D[X] */
6534 OP_RVC
, /* VFP control register */
6535 OP_RMF
, /* Maverick F register */
6536 OP_RMD
, /* Maverick D register */
6537 OP_RMFX
, /* Maverick FX register */
6538 OP_RMDX
, /* Maverick DX register */
6539 OP_RMAX
, /* Maverick AX register */
6540 OP_RMDS
, /* Maverick DSPSC register */
6541 OP_RIWR
, /* iWMMXt wR register */
6542 OP_RIWC
, /* iWMMXt wC register */
6543 OP_RIWG
, /* iWMMXt wCG register */
6544 OP_RXA
, /* XScale accumulator register */
6546 OP_REGLST
, /* ARM register list */
6547 OP_VRSLST
, /* VFP single-precision register list */
6548 OP_VRDLST
, /* VFP double-precision register list */
6549 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6550 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6551 OP_NSTRLST
, /* Neon element/structure list */
6553 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6554 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6555 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6556 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6557 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6558 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6559 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6560 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6561 OP_VMOV
, /* Neon VMOV operands. */
6562 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6563 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6564 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6566 OP_I0
, /* immediate zero */
6567 OP_I7
, /* immediate value 0 .. 7 */
6568 OP_I15
, /* 0 .. 15 */
6569 OP_I16
, /* 1 .. 16 */
6570 OP_I16z
, /* 0 .. 16 */
6571 OP_I31
, /* 0 .. 31 */
6572 OP_I31w
, /* 0 .. 31, optional trailing ! */
6573 OP_I32
, /* 1 .. 32 */
6574 OP_I32z
, /* 0 .. 32 */
6575 OP_I63
, /* 0 .. 63 */
6576 OP_I63s
, /* -64 .. 63 */
6577 OP_I64
, /* 1 .. 64 */
6578 OP_I64z
, /* 0 .. 64 */
6579 OP_I255
, /* 0 .. 255 */
6581 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6582 OP_I7b
, /* 0 .. 7 */
6583 OP_I15b
, /* 0 .. 15 */
6584 OP_I31b
, /* 0 .. 31 */
6586 OP_SH
, /* shifter operand */
6587 OP_SHG
, /* shifter operand with possible group relocation */
6588 OP_ADDR
, /* Memory address expression (any mode) */
6589 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6590 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6591 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6592 OP_EXP
, /* arbitrary expression */
6593 OP_EXPi
, /* same, with optional immediate prefix */
6594 OP_EXPr
, /* same, with optional relocation suffix */
6595 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6596 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6597 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6598 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6600 OP_CPSF
, /* CPS flags */
6601 OP_ENDI
, /* Endianness specifier */
6602 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6603 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6604 OP_COND
, /* conditional code */
6605 OP_TB
, /* Table branch. */
6607 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6609 OP_RRnpc_I0
, /* ARM register or literal 0 */
6610 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6611 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6612 OP_RF_IF
, /* FPA register or immediate */
6613 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6614 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6616 /* Optional operands. */
6617 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6618 OP_oI31b
, /* 0 .. 31 */
6619 OP_oI32b
, /* 1 .. 32 */
6620 OP_oI32z
, /* 0 .. 32 */
6621 OP_oIffffb
, /* 0 .. 65535 */
6622 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6624 OP_oRR
, /* ARM register */
6625 OP_oRRnpc
, /* ARM register, not the PC */
6626 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6627 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6628 OP_oRND
, /* Optional Neon double precision register */
6629 OP_oRNQ
, /* Optional Neon quad precision register */
6630 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6631 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6632 OP_oSHll
, /* LSL immediate */
6633 OP_oSHar
, /* ASR immediate */
6634 OP_oSHllar
, /* LSL or ASR immediate */
6635 OP_oROR
, /* ROR 0/8/16/24 */
6636 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6638 /* Some pre-defined mixed (ARM/THUMB) operands. */
6639 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6640 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6641 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6643 OP_FIRST_OPTIONAL
= OP_oI7b
6646 /* Generic instruction operand parser. This does no encoding and no
6647 semantic validation; it merely squirrels values away in the inst
6648 structure. Returns SUCCESS or FAIL depending on whether the
6649 specified grammar matched. */
6651 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6653 unsigned const int *upat
= pattern
;
6654 char *backtrack_pos
= 0;
6655 const char *backtrack_error
= 0;
6656 int i
, val
= 0, backtrack_index
= 0;
6657 enum arm_reg_type rtype
;
6658 parse_operand_result result
;
6659 unsigned int op_parse_code
;
6661 #define po_char_or_fail(chr) \
6664 if (skip_past_char (&str, chr) == FAIL) \
6669 #define po_reg_or_fail(regtype) \
6672 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6673 & inst.operands[i].vectype); \
6676 first_error (_(reg_expected_msgs[regtype])); \
6679 inst.operands[i].reg = val; \
6680 inst.operands[i].isreg = 1; \
6681 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6682 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6683 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6684 || rtype == REG_TYPE_VFD \
6685 || rtype == REG_TYPE_NQ); \
6689 #define po_reg_or_goto(regtype, label) \
6692 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6693 & inst.operands[i].vectype); \
6697 inst.operands[i].reg = val; \
6698 inst.operands[i].isreg = 1; \
6699 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6700 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6701 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6702 || rtype == REG_TYPE_VFD \
6703 || rtype == REG_TYPE_NQ); \
6707 #define po_imm_or_fail(min, max, popt) \
6710 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6712 inst.operands[i].imm = val; \
6716 #define po_scalar_or_goto(elsz, label) \
6719 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6722 inst.operands[i].reg = val; \
6723 inst.operands[i].isscalar = 1; \
6727 #define po_misc_or_fail(expr) \
6735 #define po_misc_or_fail_no_backtrack(expr) \
6739 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6740 backtrack_pos = 0; \
6741 if (result != PARSE_OPERAND_SUCCESS) \
6746 #define po_barrier_or_imm(str) \
6749 val = parse_barrier (&str); \
6750 if (val == FAIL && ! ISALPHA (*str)) \
6753 /* ISB can only take SY as an option. */ \
6754 || ((inst.instruction & 0xf0) == 0x60 \
6757 inst.error = _("invalid barrier type"); \
6758 backtrack_pos = 0; \
6764 skip_whitespace (str
);
6766 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6768 op_parse_code
= upat
[i
];
6769 if (op_parse_code
>= 1<<16)
6770 op_parse_code
= thumb
? (op_parse_code
>> 16)
6771 : (op_parse_code
& ((1<<16)-1));
6773 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6775 /* Remember where we are in case we need to backtrack. */
6776 gas_assert (!backtrack_pos
);
6777 backtrack_pos
= str
;
6778 backtrack_error
= inst
.error
;
6779 backtrack_index
= i
;
6782 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6783 po_char_or_fail (',');
6785 switch (op_parse_code
)
6793 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6794 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6795 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6796 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6797 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6798 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6800 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6802 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6804 /* Also accept generic coprocessor regs for unknown registers. */
6806 po_reg_or_fail (REG_TYPE_CN
);
6808 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6809 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6810 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6811 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6812 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6813 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6814 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6815 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6816 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6817 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6819 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6820 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6822 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6823 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6825 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6827 /* Neon scalar. Using an element size of 8 means that some invalid
6828 scalars are accepted here, so deal with those in later code. */
6829 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6833 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6836 po_imm_or_fail (0, 0, TRUE
);
6841 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6846 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6849 if (parse_ifimm_zero (&str
))
6850 inst
.operands
[i
].imm
= 0;
6854 = _("only floating point zero is allowed as immediate value");
6862 po_scalar_or_goto (8, try_rr
);
6865 po_reg_or_fail (REG_TYPE_RN
);
6871 po_scalar_or_goto (8, try_nsdq
);
6874 po_reg_or_fail (REG_TYPE_NSDQ
);
6880 po_scalar_or_goto (8, try_s_scalar
);
6883 po_scalar_or_goto (4, try_nsd
);
6886 po_reg_or_fail (REG_TYPE_NSD
);
6892 po_scalar_or_goto (8, try_ndq
);
6895 po_reg_or_fail (REG_TYPE_NDQ
);
6901 po_scalar_or_goto (8, try_vfd
);
6904 po_reg_or_fail (REG_TYPE_VFD
);
6909 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6910 not careful then bad things might happen. */
6911 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6916 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6919 /* There's a possibility of getting a 64-bit immediate here, so
6920 we need special handling. */
6921 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6924 inst
.error
= _("immediate value is out of range");
6932 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6935 po_imm_or_fail (0, 63, TRUE
);
6940 po_char_or_fail ('[');
6941 po_reg_or_fail (REG_TYPE_RN
);
6942 po_char_or_fail (']');
6948 po_reg_or_fail (REG_TYPE_RN
);
6949 if (skip_past_char (&str
, '!') == SUCCESS
)
6950 inst
.operands
[i
].writeback
= 1;
6954 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6955 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6956 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6957 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6958 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6959 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6960 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6961 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6962 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6963 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6964 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6965 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6967 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6969 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6970 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6972 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6973 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6974 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6975 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6977 /* Immediate variants */
6979 po_char_or_fail ('{');
6980 po_imm_or_fail (0, 255, TRUE
);
6981 po_char_or_fail ('}');
6985 /* The expression parser chokes on a trailing !, so we have
6986 to find it first and zap it. */
6989 while (*s
&& *s
!= ',')
6994 inst
.operands
[i
].writeback
= 1;
6996 po_imm_or_fail (0, 31, TRUE
);
7004 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7009 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7014 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7016 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7018 val
= parse_reloc (&str
);
7021 inst
.error
= _("unrecognized relocation suffix");
7024 else if (val
!= BFD_RELOC_UNUSED
)
7026 inst
.operands
[i
].imm
= val
;
7027 inst
.operands
[i
].hasreloc
= 1;
7033 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7035 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7037 inst
.operands
[i
].hasreloc
= 1;
7039 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7041 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7042 inst
.operands
[i
].hasreloc
= 0;
7046 /* Operand for MOVW or MOVT. */
7048 po_misc_or_fail (parse_half (&str
));
7051 /* Register or expression. */
7052 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7053 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7055 /* Register or immediate. */
7056 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7057 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7059 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7061 if (!is_immediate_prefix (*str
))
7064 val
= parse_fpa_immediate (&str
);
7067 /* FPA immediates are encoded as registers 8-15.
7068 parse_fpa_immediate has already applied the offset. */
7069 inst
.operands
[i
].reg
= val
;
7070 inst
.operands
[i
].isreg
= 1;
7073 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7074 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7076 /* Two kinds of register. */
7079 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7081 || (rege
->type
!= REG_TYPE_MMXWR
7082 && rege
->type
!= REG_TYPE_MMXWC
7083 && rege
->type
!= REG_TYPE_MMXWCG
))
7085 inst
.error
= _("iWMMXt data or control register expected");
7088 inst
.operands
[i
].reg
= rege
->number
;
7089 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7095 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7097 || (rege
->type
!= REG_TYPE_MMXWC
7098 && rege
->type
!= REG_TYPE_MMXWCG
))
7100 inst
.error
= _("iWMMXt control register expected");
7103 inst
.operands
[i
].reg
= rege
->number
;
7104 inst
.operands
[i
].isreg
= 1;
7109 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7110 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7111 case OP_oROR
: val
= parse_ror (&str
); break;
7112 case OP_COND
: val
= parse_cond (&str
); break;
7113 case OP_oBARRIER_I15
:
7114 po_barrier_or_imm (str
); break;
7116 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7122 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7123 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7125 inst
.error
= _("Banked registers are not available with this "
7131 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7135 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7138 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7140 if (strncasecmp (str
, "APSR_", 5) == 0)
7147 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7148 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7149 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7150 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7151 default: found
= 16;
7155 inst
.operands
[i
].isvec
= 1;
7156 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7157 inst
.operands
[i
].reg
= REG_PC
;
7164 po_misc_or_fail (parse_tb (&str
));
7167 /* Register lists. */
7169 val
= parse_reg_list (&str
);
7172 inst
.operands
[i
].writeback
= 1;
7178 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7182 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7186 /* Allow Q registers too. */
7187 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7192 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7194 inst
.operands
[i
].issingle
= 1;
7199 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7204 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7205 &inst
.operands
[i
].vectype
);
7208 /* Addressing modes */
7210 po_misc_or_fail (parse_address (&str
, i
));
7214 po_misc_or_fail_no_backtrack (
7215 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7219 po_misc_or_fail_no_backtrack (
7220 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7224 po_misc_or_fail_no_backtrack (
7225 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7229 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7233 po_misc_or_fail_no_backtrack (
7234 parse_shifter_operand_group_reloc (&str
, i
));
7238 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7242 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7246 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7250 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7253 /* Various value-based sanity checks and shared operations. We
7254 do not signal immediate failures for the register constraints;
7255 this allows a syntax error to take precedence. */
7256 switch (op_parse_code
)
7264 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7265 inst
.error
= BAD_PC
;
7270 if (inst
.operands
[i
].isreg
)
7272 if (inst
.operands
[i
].reg
== REG_PC
)
7273 inst
.error
= BAD_PC
;
7274 else if (inst
.operands
[i
].reg
== REG_SP
7275 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7276 relaxed since ARMv8-A. */
7277 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7280 inst
.error
= BAD_SP
;
7286 if (inst
.operands
[i
].isreg
7287 && inst
.operands
[i
].reg
== REG_PC
7288 && (inst
.operands
[i
].writeback
|| thumb
))
7289 inst
.error
= BAD_PC
;
7298 case OP_oBARRIER_I15
:
7307 inst
.operands
[i
].imm
= val
;
7314 /* If we get here, this operand was successfully parsed. */
7315 inst
.operands
[i
].present
= 1;
7319 inst
.error
= BAD_ARGS
;
7324 /* The parse routine should already have set inst.error, but set a
7325 default here just in case. */
7327 inst
.error
= _("syntax error");
7331 /* Do not backtrack over a trailing optional argument that
7332 absorbed some text. We will only fail again, with the
7333 'garbage following instruction' error message, which is
7334 probably less helpful than the current one. */
7335 if (backtrack_index
== i
&& backtrack_pos
!= str
7336 && upat
[i
+1] == OP_stop
)
7339 inst
.error
= _("syntax error");
7343 /* Try again, skipping the optional argument at backtrack_pos. */
7344 str
= backtrack_pos
;
7345 inst
.error
= backtrack_error
;
7346 inst
.operands
[backtrack_index
].present
= 0;
7347 i
= backtrack_index
;
7351 /* Check that we have parsed all the arguments. */
7352 if (*str
!= '\0' && !inst
.error
)
7353 inst
.error
= _("garbage following instruction");
7355 return inst
.error
? FAIL
: SUCCESS
;
7358 #undef po_char_or_fail
7359 #undef po_reg_or_fail
7360 #undef po_reg_or_goto
7361 #undef po_imm_or_fail
7362 #undef po_scalar_or_fail
7363 #undef po_barrier_or_imm
7365 /* Shorthand macro for instruction encoding functions issuing errors. */
7366 #define constraint(expr, err) \
7377 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7378 instructions are unpredictable if these registers are used. This
7379 is the BadReg predicate in ARM's Thumb-2 documentation.
7381 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7382 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7383 #define reject_bad_reg(reg) \
7385 if (reg == REG_PC) \
7387 inst.error = BAD_PC; \
7390 else if (reg == REG_SP \
7391 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7393 inst.error = BAD_SP; \
7398 /* If REG is R13 (the stack pointer), warn that its use is
7400 #define warn_deprecated_sp(reg) \
7402 if (warn_on_deprecated && reg == REG_SP) \
7403 as_tsktsk (_("use of r13 is deprecated")); \
7406 /* Functions for operand encoding. ARM, then Thumb. */
7408 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7410 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7412 The only binary encoding difference is the Coprocessor number. Coprocessor
7413 9 is used for half-precision calculations or conversions. The format of the
7414 instruction is the same as the equivalent Coprocessor 10 instruction that
7415 exists for Single-Precision operation. */
7418 do_scalar_fp16_v82_encode (void)
7420 if (inst
.cond
!= COND_ALWAYS
)
7421 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7422 " the behaviour is UNPREDICTABLE"));
7423 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7426 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7427 mark_feature_used (&arm_ext_fp16
);
7430 /* If VAL can be encoded in the immediate field of an ARM instruction,
7431 return the encoded form. Otherwise, return FAIL. */
7434 encode_arm_immediate (unsigned int val
)
7441 for (i
= 2; i
< 32; i
+= 2)
7442 if ((a
= rotate_left (val
, i
)) <= 0xff)
7443 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7448 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7449 return the encoded form. Otherwise, return FAIL. */
7451 encode_thumb32_immediate (unsigned int val
)
7458 for (i
= 1; i
<= 24; i
++)
7461 if ((val
& ~(0xff << i
)) == 0)
7462 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7466 if (val
== ((a
<< 16) | a
))
7468 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7472 if (val
== ((a
<< 16) | a
))
7473 return 0x200 | (a
>> 8);
7477 /* Encode a VFP SP or DP register number into inst.instruction. */
7480 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7482 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7485 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7488 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7491 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7496 first_error (_("D register out of range for selected VFP version"));
7504 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7508 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7512 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7516 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7520 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7524 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7532 /* Encode a <shift> in an ARM-format instruction. The immediate,
7533 if any, is handled by md_apply_fix. */
7535 encode_arm_shift (int i
)
7537 /* register-shifted register. */
7538 if (inst
.operands
[i
].immisreg
)
7541 for (op_index
= 0; op_index
<= i
; ++op_index
)
7543 /* Check the operand only when it's presented. In pre-UAL syntax,
7544 if the destination register is the same as the first operand, two
7545 register form of the instruction can be used. */
7546 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7547 && inst
.operands
[op_index
].reg
== REG_PC
)
7548 as_warn (UNPRED_REG ("r15"));
7551 if (inst
.operands
[i
].imm
== REG_PC
)
7552 as_warn (UNPRED_REG ("r15"));
7555 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7556 inst
.instruction
|= SHIFT_ROR
<< 5;
7559 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7560 if (inst
.operands
[i
].immisreg
)
7562 inst
.instruction
|= SHIFT_BY_REG
;
7563 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7566 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7571 encode_arm_shifter_operand (int i
)
7573 if (inst
.operands
[i
].isreg
)
7575 inst
.instruction
|= inst
.operands
[i
].reg
;
7576 encode_arm_shift (i
);
7580 inst
.instruction
|= INST_IMMEDIATE
;
7581 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
7582 inst
.instruction
|= inst
.operands
[i
].imm
;
7586 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7588 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7591 Generate an error if the operand is not a register. */
7592 constraint (!inst
.operands
[i
].isreg
,
7593 _("Instruction does not support =N addresses"));
7595 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7597 if (inst
.operands
[i
].preind
)
7601 inst
.error
= _("instruction does not accept preindexed addressing");
7604 inst
.instruction
|= PRE_INDEX
;
7605 if (inst
.operands
[i
].writeback
)
7606 inst
.instruction
|= WRITE_BACK
;
7609 else if (inst
.operands
[i
].postind
)
7611 gas_assert (inst
.operands
[i
].writeback
);
7613 inst
.instruction
|= WRITE_BACK
;
7615 else /* unindexed - only for coprocessor */
7617 inst
.error
= _("instruction does not accept unindexed addressing");
7621 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7622 && (((inst
.instruction
& 0x000f0000) >> 16)
7623 == ((inst
.instruction
& 0x0000f000) >> 12)))
7624 as_warn ((inst
.instruction
& LOAD_BIT
)
7625 ? _("destination register same as write-back base")
7626 : _("source register same as write-back base"));
7629 /* inst.operands[i] was set up by parse_address. Encode it into an
7630 ARM-format mode 2 load or store instruction. If is_t is true,
7631 reject forms that cannot be used with a T instruction (i.e. not
7634 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7636 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7638 encode_arm_addr_mode_common (i
, is_t
);
7640 if (inst
.operands
[i
].immisreg
)
7642 constraint ((inst
.operands
[i
].imm
== REG_PC
7643 || (is_pc
&& inst
.operands
[i
].writeback
)),
7645 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7646 inst
.instruction
|= inst
.operands
[i
].imm
;
7647 if (!inst
.operands
[i
].negative
)
7648 inst
.instruction
|= INDEX_UP
;
7649 if (inst
.operands
[i
].shifted
)
7651 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7652 inst
.instruction
|= SHIFT_ROR
<< 5;
7655 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7656 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7660 else /* immediate offset in inst.relocs[0] */
7662 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
7664 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7666 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7667 cannot use PC in addressing.
7668 PC cannot be used in writeback addressing, either. */
7669 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7672 /* Use of PC in str is deprecated for ARMv7. */
7673 if (warn_on_deprecated
7675 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7676 as_tsktsk (_("use of PC in this instruction is deprecated"));
7679 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7681 /* Prefer + for zero encoded value. */
7682 if (!inst
.operands
[i
].negative
)
7683 inst
.instruction
|= INDEX_UP
;
7684 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
7689 /* inst.operands[i] was set up by parse_address. Encode it into an
7690 ARM-format mode 3 load or store instruction. Reject forms that
7691 cannot be used with such instructions. If is_t is true, reject
7692 forms that cannot be used with a T instruction (i.e. not
7695 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7697 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7699 inst
.error
= _("instruction does not accept scaled register index");
7703 encode_arm_addr_mode_common (i
, is_t
);
7705 if (inst
.operands
[i
].immisreg
)
7707 constraint ((inst
.operands
[i
].imm
== REG_PC
7708 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7710 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7712 inst
.instruction
|= inst
.operands
[i
].imm
;
7713 if (!inst
.operands
[i
].negative
)
7714 inst
.instruction
|= INDEX_UP
;
7716 else /* immediate offset in inst.relocs[0] */
7718 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
7719 && inst
.operands
[i
].writeback
),
7721 inst
.instruction
|= HWOFFSET_IMM
;
7722 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7724 /* Prefer + for zero encoded value. */
7725 if (!inst
.operands
[i
].negative
)
7726 inst
.instruction
|= INDEX_UP
;
7728 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7733 /* Write immediate bits [7:0] to the following locations:
7735 |28/24|23 19|18 16|15 4|3 0|
7736 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7738 This function is used by VMOV/VMVN/VORR/VBIC. */
7741 neon_write_immbits (unsigned immbits
)
7743 inst
.instruction
|= immbits
& 0xf;
7744 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7745 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7748 /* Invert low-order SIZE bits of XHI:XLO. */
7751 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7753 unsigned immlo
= xlo
? *xlo
: 0;
7754 unsigned immhi
= xhi
? *xhi
: 0;
7759 immlo
= (~immlo
) & 0xff;
7763 immlo
= (~immlo
) & 0xffff;
7767 immhi
= (~immhi
) & 0xffffffff;
7771 immlo
= (~immlo
) & 0xffffffff;
7785 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7789 neon_bits_same_in_bytes (unsigned imm
)
7791 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7792 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7793 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7794 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7797 /* For immediate of above form, return 0bABCD. */
7800 neon_squash_bits (unsigned imm
)
7802 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7803 | ((imm
& 0x01000000) >> 21);
7806 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7809 neon_qfloat_bits (unsigned imm
)
7811 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7814 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7815 the instruction. *OP is passed as the initial value of the op field, and
7816 may be set to a different value depending on the constant (i.e.
7817 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7818 MVN). If the immediate looks like a repeated pattern then also
7819 try smaller element sizes. */
7822 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7823 unsigned *immbits
, int *op
, int size
,
7824 enum neon_el_type type
)
7826 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7828 if (type
== NT_float
&& !float_p
)
7831 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7833 if (size
!= 32 || *op
== 1)
7835 *immbits
= neon_qfloat_bits (immlo
);
7841 if (neon_bits_same_in_bytes (immhi
)
7842 && neon_bits_same_in_bytes (immlo
))
7846 *immbits
= (neon_squash_bits (immhi
) << 4)
7847 | neon_squash_bits (immlo
);
7858 if (immlo
== (immlo
& 0x000000ff))
7863 else if (immlo
== (immlo
& 0x0000ff00))
7865 *immbits
= immlo
>> 8;
7868 else if (immlo
== (immlo
& 0x00ff0000))
7870 *immbits
= immlo
>> 16;
7873 else if (immlo
== (immlo
& 0xff000000))
7875 *immbits
= immlo
>> 24;
7878 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7880 *immbits
= (immlo
>> 8) & 0xff;
7883 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7885 *immbits
= (immlo
>> 16) & 0xff;
7889 if ((immlo
& 0xffff) != (immlo
>> 16))
7896 if (immlo
== (immlo
& 0x000000ff))
7901 else if (immlo
== (immlo
& 0x0000ff00))
7903 *immbits
= immlo
>> 8;
7907 if ((immlo
& 0xff) != (immlo
>> 8))
7912 if (immlo
== (immlo
& 0x000000ff))
7914 /* Don't allow MVN with 8-bit immediate. */
7924 #if defined BFD_HOST_64_BIT
7925 /* Returns TRUE if double precision value V may be cast
7926 to single precision without loss of accuracy. */
7929 is_double_a_single (bfd_int64_t v
)
7931 int exp
= (int)((v
>> 52) & 0x7FF);
7932 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7934 return (exp
== 0 || exp
== 0x7FF
7935 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7936 && (mantissa
& 0x1FFFFFFFl
) == 0;
7939 /* Returns a double precision value casted to single precision
7940 (ignoring the least significant bits in exponent and mantissa). */
7943 double_to_single (bfd_int64_t v
)
7945 int sign
= (int) ((v
>> 63) & 1l);
7946 int exp
= (int) ((v
>> 52) & 0x7FF);
7947 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7953 exp
= exp
- 1023 + 127;
7962 /* No denormalized numbers. */
7968 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7970 #endif /* BFD_HOST_64_BIT */
7979 static void do_vfp_nsyn_opcode (const char *);
7981 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
7982 Determine whether it can be performed with a move instruction; if
7983 it can, convert inst.instruction to that move instruction and
7984 return TRUE; if it can't, convert inst.instruction to a literal-pool
7985 load and return FALSE. If this is not a valid thing to do in the
7986 current context, set inst.error and return TRUE.
7988 inst.operands[i] describes the destination register. */
7991 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7994 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7995 bfd_boolean arm_p
= (t
== CONST_ARM
);
7998 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8002 if ((inst
.instruction
& tbit
) == 0)
8004 inst
.error
= _("invalid pseudo operation");
8008 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8009 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8010 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8012 inst
.error
= _("constant expression expected");
8016 if (inst
.relocs
[0].exp
.X_op
== O_constant
8017 || inst
.relocs
[0].exp
.X_op
== O_big
)
8019 #if defined BFD_HOST_64_BIT
8024 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8026 LITTLENUM_TYPE w
[X_PRECISION
];
8029 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8031 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8033 /* FIXME: Should we check words w[2..5] ? */
8038 #if defined BFD_HOST_64_BIT
8040 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8041 << LITTLENUM_NUMBER_OF_BITS
)
8042 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8043 << LITTLENUM_NUMBER_OF_BITS
)
8044 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8045 << LITTLENUM_NUMBER_OF_BITS
)
8046 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8048 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8049 | (l
[0] & LITTLENUM_MASK
);
8053 v
= inst
.relocs
[0].exp
.X_add_number
;
8055 if (!inst
.operands
[i
].issingle
)
8059 /* LDR should not use lead in a flag-setting instruction being
8060 chosen so we do not check whether movs can be used. */
8062 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8063 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8064 && inst
.operands
[i
].reg
!= 13
8065 && inst
.operands
[i
].reg
!= 15)
8067 /* Check if on thumb2 it can be done with a mov.w, mvn or
8068 movw instruction. */
8069 unsigned int newimm
;
8070 bfd_boolean isNegated
;
8072 newimm
= encode_thumb32_immediate (v
);
8073 if (newimm
!= (unsigned int) FAIL
)
8077 newimm
= encode_thumb32_immediate (~v
);
8078 if (newimm
!= (unsigned int) FAIL
)
8082 /* The number can be loaded with a mov.w or mvn
8084 if (newimm
!= (unsigned int) FAIL
8085 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8087 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8088 | (inst
.operands
[i
].reg
<< 8));
8089 /* Change to MOVN. */
8090 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8091 inst
.instruction
|= (newimm
& 0x800) << 15;
8092 inst
.instruction
|= (newimm
& 0x700) << 4;
8093 inst
.instruction
|= (newimm
& 0x0ff);
8096 /* The number can be loaded with a movw instruction. */
8097 else if ((v
& ~0xFFFF) == 0
8098 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8100 int imm
= v
& 0xFFFF;
8102 inst
.instruction
= 0xf2400000; /* MOVW. */
8103 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8104 inst
.instruction
|= (imm
& 0xf000) << 4;
8105 inst
.instruction
|= (imm
& 0x0800) << 15;
8106 inst
.instruction
|= (imm
& 0x0700) << 4;
8107 inst
.instruction
|= (imm
& 0x00ff);
8114 int value
= encode_arm_immediate (v
);
8118 /* This can be done with a mov instruction. */
8119 inst
.instruction
&= LITERAL_MASK
;
8120 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8121 inst
.instruction
|= value
& 0xfff;
8125 value
= encode_arm_immediate (~ v
);
8128 /* This can be done with a mvn instruction. */
8129 inst
.instruction
&= LITERAL_MASK
;
8130 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8131 inst
.instruction
|= value
& 0xfff;
8135 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8138 unsigned immbits
= 0;
8139 unsigned immlo
= inst
.operands
[1].imm
;
8140 unsigned immhi
= inst
.operands
[1].regisimm
8141 ? inst
.operands
[1].reg
8142 : inst
.relocs
[0].exp
.X_unsigned
8144 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8145 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8146 &op
, 64, NT_invtype
);
8150 neon_invert_size (&immlo
, &immhi
, 64);
8152 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8153 &op
, 64, NT_invtype
);
8158 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8164 /* Fill other bits in vmov encoding for both thumb and arm. */
8166 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8168 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8169 neon_write_immbits (immbits
);
8177 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8178 if (inst
.operands
[i
].issingle
8179 && is_quarter_float (inst
.operands
[1].imm
)
8180 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8182 inst
.operands
[1].imm
=
8183 neon_qfloat_bits (v
);
8184 do_vfp_nsyn_opcode ("fconsts");
8188 /* If our host does not support a 64-bit type then we cannot perform
8189 the following optimization. This mean that there will be a
8190 discrepancy between the output produced by an assembler built for
8191 a 32-bit-only host and the output produced from a 64-bit host, but
8192 this cannot be helped. */
8193 #if defined BFD_HOST_64_BIT
8194 else if (!inst
.operands
[1].issingle
8195 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8197 if (is_double_a_single (v
)
8198 && is_quarter_float (double_to_single (v
)))
8200 inst
.operands
[1].imm
=
8201 neon_qfloat_bits (double_to_single (v
));
8202 do_vfp_nsyn_opcode ("fconstd");
8210 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8211 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8214 inst
.operands
[1].reg
= REG_PC
;
8215 inst
.operands
[1].isreg
= 1;
8216 inst
.operands
[1].preind
= 1;
8217 inst
.relocs
[0].pc_rel
= 1;
8218 inst
.relocs
[0].type
= (thumb_p
8219 ? BFD_RELOC_ARM_THUMB_OFFSET
8221 ? BFD_RELOC_ARM_HWLITERAL
8222 : BFD_RELOC_ARM_LITERAL
));
8226 /* inst.operands[i] was set up by parse_address. Encode it into an
8227 ARM-format instruction. Reject all forms which cannot be encoded
8228 into a coprocessor load/store instruction. If wb_ok is false,
8229 reject use of writeback; if unind_ok is false, reject use of
8230 unindexed addressing. If reloc_override is not 0, use it instead
8231 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8232 (in which case it is preserved). */
8235 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8237 if (!inst
.operands
[i
].isreg
)
8240 if (! inst
.operands
[0].isvec
)
8242 inst
.error
= _("invalid co-processor operand");
8245 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8249 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8251 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8253 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8255 gas_assert (!inst
.operands
[i
].writeback
);
8258 inst
.error
= _("instruction does not support unindexed addressing");
8261 inst
.instruction
|= inst
.operands
[i
].imm
;
8262 inst
.instruction
|= INDEX_UP
;
8266 if (inst
.operands
[i
].preind
)
8267 inst
.instruction
|= PRE_INDEX
;
8269 if (inst
.operands
[i
].writeback
)
8271 if (inst
.operands
[i
].reg
== REG_PC
)
8273 inst
.error
= _("pc may not be used with write-back");
8278 inst
.error
= _("instruction does not support writeback");
8281 inst
.instruction
|= WRITE_BACK
;
8285 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8286 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8287 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8288 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8291 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8293 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8296 /* Prefer + for zero encoded value. */
8297 if (!inst
.operands
[i
].negative
)
8298 inst
.instruction
|= INDEX_UP
;
8303 /* Functions for instruction encoding, sorted by sub-architecture.
8304 First some generics; their names are taken from the conventional
8305 bit positions for register arguments in ARM format instructions. */
8315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8328 inst
.instruction
|= inst
.operands
[1].reg
;
8334 inst
.instruction
|= inst
.operands
[0].reg
;
8335 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8342 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8348 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8349 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8355 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8356 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8360 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8362 if (ARM_CPU_IS_ANY (cpu_variant
))
8364 as_tsktsk ("%s", msg
);
8367 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8379 unsigned Rn
= inst
.operands
[2].reg
;
8380 /* Enforce restrictions on SWP instruction. */
8381 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8383 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8384 _("Rn must not overlap other operands"));
8386 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8388 if (!check_obsolete (&arm_ext_v8
,
8389 _("swp{b} use is obsoleted for ARMv8 and later"))
8390 && warn_on_deprecated
8391 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8392 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8396 inst
.instruction
|= inst
.operands
[1].reg
;
8397 inst
.instruction
|= Rn
<< 16;
8403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8404 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8405 inst
.instruction
|= inst
.operands
[2].reg
;
8411 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8412 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8413 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8414 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8416 inst
.instruction
|= inst
.operands
[0].reg
;
8417 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8418 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8424 inst
.instruction
|= inst
.operands
[0].imm
;
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8434 /* ARM instructions, in alphabetical order by function name (except
8435 that wrapper functions appear immediately after the function they
8438 /* This is a pseudo-op of the form "adr rd, label" to be converted
8439 into a relative address of the form "add rd, pc, #label-.-8". */
8444 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8446 /* Frag hacking will turn this into a sub instruction if the offset turns
8447 out to be negative. */
8448 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8449 inst
.relocs
[0].pc_rel
= 1;
8450 inst
.relocs
[0].exp
.X_add_number
-= 8;
8452 if (support_interwork
8453 && inst
.relocs
[0].exp
.X_op
== O_symbol
8454 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8455 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8456 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8457 inst
.relocs
[0].exp
.X_add_number
|= 1;
8460 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8461 into a relative address of the form:
8462 add rd, pc, #low(label-.-8)"
8463 add rd, rd, #high(label-.-8)" */
8468 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8470 /* Frag hacking will turn this into a sub instruction if the offset turns
8471 out to be negative. */
8472 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8473 inst
.relocs
[0].pc_rel
= 1;
8474 inst
.size
= INSN_SIZE
* 2;
8475 inst
.relocs
[0].exp
.X_add_number
-= 8;
8477 if (support_interwork
8478 && inst
.relocs
[0].exp
.X_op
== O_symbol
8479 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8480 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8481 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8482 inst
.relocs
[0].exp
.X_add_number
|= 1;
8488 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8489 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8491 if (!inst
.operands
[1].present
)
8492 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8494 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8495 encode_arm_shifter_operand (2);
8501 if (inst
.operands
[0].present
)
8502 inst
.instruction
|= inst
.operands
[0].imm
;
8504 inst
.instruction
|= 0xf;
8510 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8511 constraint (msb
> 32, _("bit-field extends past end of register"));
8512 /* The instruction encoding stores the LSB and MSB,
8513 not the LSB and width. */
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8516 inst
.instruction
|= (msb
- 1) << 16;
8524 /* #0 in second position is alternative syntax for bfc, which is
8525 the same instruction but with REG_PC in the Rm field. */
8526 if (!inst
.operands
[1].isreg
)
8527 inst
.operands
[1].reg
= REG_PC
;
8529 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8530 constraint (msb
> 32, _("bit-field extends past end of register"));
8531 /* The instruction encoding stores the LSB and MSB,
8532 not the LSB and width. */
8533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8534 inst
.instruction
|= inst
.operands
[1].reg
;
8535 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8536 inst
.instruction
|= (msb
- 1) << 16;
8542 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8543 _("bit-field extends past end of register"));
8544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8545 inst
.instruction
|= inst
.operands
[1].reg
;
8546 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8547 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8550 /* ARM V5 breakpoint instruction (argument parse)
8551 BKPT <16 bit unsigned immediate>
8552 Instruction is not conditional.
8553 The bit pattern given in insns[] has the COND_ALWAYS condition,
8554 and it is an error if the caller tried to override that. */
8559 /* Top 12 of 16 bits to bits 19:8. */
8560 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8562 /* Bottom 4 of 16 bits to bits 3:0. */
8563 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8567 encode_branch (int default_reloc
)
8569 if (inst
.operands
[0].hasreloc
)
8571 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8572 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8573 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8574 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8575 ? BFD_RELOC_ARM_PLT32
8576 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8579 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
8580 inst
.relocs
[0].pc_rel
= 1;
8587 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8588 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8591 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8598 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8600 if (inst
.cond
== COND_ALWAYS
)
8601 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8603 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8607 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8610 /* ARM V5 branch-link-exchange instruction (argument parse)
8611 BLX <target_addr> ie BLX(1)
8612 BLX{<condition>} <Rm> ie BLX(2)
8613 Unfortunately, there are two different opcodes for this mnemonic.
8614 So, the insns[].value is not used, and the code here zaps values
8615 into inst.instruction.
8616 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8621 if (inst
.operands
[0].isreg
)
8623 /* Arg is a register; the opcode provided by insns[] is correct.
8624 It is not illegal to do "blx pc", just useless. */
8625 if (inst
.operands
[0].reg
== REG_PC
)
8626 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8628 inst
.instruction
|= inst
.operands
[0].reg
;
8632 /* Arg is an address; this instruction cannot be executed
8633 conditionally, and the opcode must be adjusted.
8634 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8635 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8636 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8637 inst
.instruction
= 0xfa000000;
8638 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8645 bfd_boolean want_reloc
;
8647 if (inst
.operands
[0].reg
== REG_PC
)
8648 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8650 inst
.instruction
|= inst
.operands
[0].reg
;
8651 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8652 it is for ARMv4t or earlier. */
8653 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8654 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8655 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8659 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8664 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
8668 /* ARM v5TEJ. Jump to Jazelle code. */
8673 if (inst
.operands
[0].reg
== REG_PC
)
8674 as_tsktsk (_("use of r15 in bxj is not really useful"));
8676 inst
.instruction
|= inst
.operands
[0].reg
;
8679 /* Co-processor data operation:
8680 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8681 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8686 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8687 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8688 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8689 inst
.instruction
|= inst
.operands
[4].reg
;
8690 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8696 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8697 encode_arm_shifter_operand (1);
8700 /* Transfer between coprocessor and ARM registers.
8701 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8706 No special properties. */
8708 struct deprecated_coproc_regs_s
8715 arm_feature_set deprecated
;
8716 arm_feature_set obsoleted
;
8717 const char *dep_msg
;
8718 const char *obs_msg
;
8721 #define DEPR_ACCESS_V8 \
8722 N_("This coprocessor register access is deprecated in ARMv8")
8724 /* Table of all deprecated coprocessor registers. */
8725 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8727 {15, 0, 7, 10, 5, /* CP15DMB. */
8728 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8729 DEPR_ACCESS_V8
, NULL
},
8730 {15, 0, 7, 10, 4, /* CP15DSB. */
8731 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8732 DEPR_ACCESS_V8
, NULL
},
8733 {15, 0, 7, 5, 4, /* CP15ISB. */
8734 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8735 DEPR_ACCESS_V8
, NULL
},
8736 {14, 6, 1, 0, 0, /* TEEHBR. */
8737 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8738 DEPR_ACCESS_V8
, NULL
},
8739 {14, 6, 0, 0, 0, /* TEECR. */
8740 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8741 DEPR_ACCESS_V8
, NULL
},
8744 #undef DEPR_ACCESS_V8
8746 static const size_t deprecated_coproc_reg_count
=
8747 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8755 Rd
= inst
.operands
[2].reg
;
8758 if (inst
.instruction
== 0xee000010
8759 || inst
.instruction
== 0xfe000010)
8761 reject_bad_reg (Rd
);
8762 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8764 constraint (Rd
== REG_SP
, BAD_SP
);
8769 if (inst
.instruction
== 0xe000010)
8770 constraint (Rd
== REG_PC
, BAD_PC
);
8773 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8775 const struct deprecated_coproc_regs_s
*r
=
8776 deprecated_coproc_regs
+ i
;
8778 if (inst
.operands
[0].reg
== r
->cp
8779 && inst
.operands
[1].imm
== r
->opc1
8780 && inst
.operands
[3].reg
== r
->crn
8781 && inst
.operands
[4].reg
== r
->crm
8782 && inst
.operands
[5].imm
== r
->opc2
)
8784 if (! ARM_CPU_IS_ANY (cpu_variant
)
8785 && warn_on_deprecated
8786 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8787 as_tsktsk ("%s", r
->dep_msg
);
8791 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8792 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8793 inst
.instruction
|= Rd
<< 12;
8794 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8795 inst
.instruction
|= inst
.operands
[4].reg
;
8796 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8799 /* Transfer between coprocessor register and pair of ARM registers.
8800 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8805 Two XScale instructions are special cases of these:
8807 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8808 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8810 Result unpredictable if Rd or Rn is R15. */
8817 Rd
= inst
.operands
[2].reg
;
8818 Rn
= inst
.operands
[3].reg
;
8822 reject_bad_reg (Rd
);
8823 reject_bad_reg (Rn
);
8827 constraint (Rd
== REG_PC
, BAD_PC
);
8828 constraint (Rn
== REG_PC
, BAD_PC
);
8831 /* Only check the MRRC{2} variants. */
8832 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8834 /* If Rd == Rn, error that the operation is
8835 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8836 constraint (Rd
== Rn
, BAD_OVERLAP
);
8839 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8840 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8841 inst
.instruction
|= Rd
<< 12;
8842 inst
.instruction
|= Rn
<< 16;
8843 inst
.instruction
|= inst
.operands
[4].reg
;
8849 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8850 if (inst
.operands
[1].present
)
8852 inst
.instruction
|= CPSI_MMOD
;
8853 inst
.instruction
|= inst
.operands
[1].imm
;
8860 inst
.instruction
|= inst
.operands
[0].imm
;
8866 unsigned Rd
, Rn
, Rm
;
8868 Rd
= inst
.operands
[0].reg
;
8869 Rn
= (inst
.operands
[1].present
8870 ? inst
.operands
[1].reg
: Rd
);
8871 Rm
= inst
.operands
[2].reg
;
8873 constraint ((Rd
== REG_PC
), BAD_PC
);
8874 constraint ((Rn
== REG_PC
), BAD_PC
);
8875 constraint ((Rm
== REG_PC
), BAD_PC
);
8877 inst
.instruction
|= Rd
<< 16;
8878 inst
.instruction
|= Rn
<< 0;
8879 inst
.instruction
|= Rm
<< 8;
8885 /* There is no IT instruction in ARM mode. We
8886 process it to do the validation as if in
8887 thumb mode, just in case the code gets
8888 assembled for thumb using the unified syntax. */
8893 set_it_insn_type (IT_INSN
);
8894 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8895 now_it
.cc
= inst
.operands
[0].imm
;
8899 /* If there is only one register in the register list,
8900 then return its register number. Otherwise return -1. */
8902 only_one_reg_in_list (int range
)
8904 int i
= ffs (range
) - 1;
8905 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8909 encode_ldmstm(int from_push_pop_mnem
)
8911 int base_reg
= inst
.operands
[0].reg
;
8912 int range
= inst
.operands
[1].imm
;
8915 inst
.instruction
|= base_reg
<< 16;
8916 inst
.instruction
|= range
;
8918 if (inst
.operands
[1].writeback
)
8919 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8921 if (inst
.operands
[0].writeback
)
8923 inst
.instruction
|= WRITE_BACK
;
8924 /* Check for unpredictable uses of writeback. */
8925 if (inst
.instruction
& LOAD_BIT
)
8927 /* Not allowed in LDM type 2. */
8928 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8929 && ((range
& (1 << REG_PC
)) == 0))
8930 as_warn (_("writeback of base register is UNPREDICTABLE"));
8931 /* Only allowed if base reg not in list for other types. */
8932 else if (range
& (1 << base_reg
))
8933 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8937 /* Not allowed for type 2. */
8938 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8939 as_warn (_("writeback of base register is UNPREDICTABLE"));
8940 /* Only allowed if base reg not in list, or first in list. */
8941 else if ((range
& (1 << base_reg
))
8942 && (range
& ((1 << base_reg
) - 1)))
8943 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8947 /* If PUSH/POP has only one register, then use the A2 encoding. */
8948 one_reg
= only_one_reg_in_list (range
);
8949 if (from_push_pop_mnem
&& one_reg
>= 0)
8951 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8953 if (is_push
&& one_reg
== 13 /* SP */)
8954 /* PR 22483: The A2 encoding cannot be used when
8955 pushing the stack pointer as this is UNPREDICTABLE. */
8958 inst
.instruction
&= A_COND_MASK
;
8959 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8960 inst
.instruction
|= one_reg
<< 12;
8967 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8970 /* ARMv5TE load-consecutive (argument parse)
8979 constraint (inst
.operands
[0].reg
% 2 != 0,
8980 _("first transfer register must be even"));
8981 constraint (inst
.operands
[1].present
8982 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8983 _("can only transfer two consecutive registers"));
8984 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8985 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8987 if (!inst
.operands
[1].present
)
8988 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8990 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8991 register and the first register written; we have to diagnose
8992 overlap between the base and the second register written here. */
8994 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8995 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8996 as_warn (_("base register written back, and overlaps "
8997 "second transfer register"));
8999 if (!(inst
.instruction
& V4_STR_BIT
))
9001 /* For an index-register load, the index register must not overlap the
9002 destination (even if not write-back). */
9003 if (inst
.operands
[2].immisreg
9004 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9005 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9006 as_warn (_("index register overlaps transfer register"));
9008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9009 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9015 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9016 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9017 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9018 || inst
.operands
[1].negative
9019 /* This can arise if the programmer has written
9021 or if they have mistakenly used a register name as the last
9024 It is very difficult to distinguish between these two cases
9025 because "rX" might actually be a label. ie the register
9026 name has been occluded by a symbol of the same name. So we
9027 just generate a general 'bad addressing mode' type error
9028 message and leave it up to the programmer to discover the
9029 true cause and fix their mistake. */
9030 || (inst
.operands
[1].reg
== REG_PC
),
9033 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9034 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9035 _("offset must be zero in ARM encoding"));
9037 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9041 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9047 constraint (inst
.operands
[0].reg
% 2 != 0,
9048 _("even register required"));
9049 constraint (inst
.operands
[1].present
9050 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9051 _("can only load two consecutive registers"));
9052 /* If op 1 were present and equal to PC, this function wouldn't
9053 have been called in the first place. */
9054 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9057 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9060 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9061 which is not a multiple of four is UNPREDICTABLE. */
9063 check_ldr_r15_aligned (void)
9065 constraint (!(inst
.operands
[1].immisreg
)
9066 && (inst
.operands
[0].reg
== REG_PC
9067 && inst
.operands
[1].reg
== REG_PC
9068 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9069 _("ldr to register 15 must be 4-byte aligned"));
9075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9076 if (!inst
.operands
[1].isreg
)
9077 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9079 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9080 check_ldr_r15_aligned ();
9086 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9088 if (inst
.operands
[1].preind
)
9090 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9091 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9092 _("this instruction requires a post-indexed address"));
9094 inst
.operands
[1].preind
= 0;
9095 inst
.operands
[1].postind
= 1;
9096 inst
.operands
[1].writeback
= 1;
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9102 /* Halfword and signed-byte load/store operations. */
9107 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9109 if (!inst
.operands
[1].isreg
)
9110 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9112 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9118 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9120 if (inst
.operands
[1].preind
)
9122 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9123 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9124 _("this instruction requires a post-indexed address"));
9126 inst
.operands
[1].preind
= 0;
9127 inst
.operands
[1].postind
= 1;
9128 inst
.operands
[1].writeback
= 1;
9130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9131 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9134 /* Co-processor register load/store.
9135 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9139 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9141 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9147 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9148 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9149 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9150 && !(inst
.instruction
& 0x00400000))
9151 as_tsktsk (_("Rd and Rm should be different in mla"));
9153 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9154 inst
.instruction
|= inst
.operands
[1].reg
;
9155 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9156 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9162 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9163 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9166 encode_arm_shifter_operand (1);
9169 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9176 top
= (inst
.instruction
& 0x00400000) != 0;
9177 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9178 _(":lower16: not allowed in this instruction"));
9179 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9180 _(":upper16: not allowed in this instruction"));
9181 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9182 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9184 imm
= inst
.relocs
[0].exp
.X_add_number
;
9185 /* The value is in two pieces: 0:11, 16:19. */
9186 inst
.instruction
|= (imm
& 0x00000fff);
9187 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9192 do_vfp_nsyn_mrs (void)
9194 if (inst
.operands
[0].isvec
)
9196 if (inst
.operands
[1].reg
!= 1)
9197 first_error (_("operand 1 must be FPSCR"));
9198 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9199 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9200 do_vfp_nsyn_opcode ("fmstat");
9202 else if (inst
.operands
[1].isvec
)
9203 do_vfp_nsyn_opcode ("fmrx");
9211 do_vfp_nsyn_msr (void)
9213 if (inst
.operands
[0].isvec
)
9214 do_vfp_nsyn_opcode ("fmxr");
9224 unsigned Rt
= inst
.operands
[0].reg
;
9226 if (thumb_mode
&& Rt
== REG_SP
)
9228 inst
.error
= BAD_SP
;
9232 /* MVFR2 is only valid at ARMv8-A. */
9233 if (inst
.operands
[1].reg
== 5)
9234 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9237 /* APSR_ sets isvec. All other refs to PC are illegal. */
9238 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9240 inst
.error
= BAD_PC
;
9244 /* If we get through parsing the register name, we just insert the number
9245 generated into the instruction without further validation. */
9246 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9247 inst
.instruction
|= (Rt
<< 12);
9253 unsigned Rt
= inst
.operands
[1].reg
;
9256 reject_bad_reg (Rt
);
9257 else if (Rt
== REG_PC
)
9259 inst
.error
= BAD_PC
;
9263 /* MVFR2 is only valid for ARMv8-A. */
9264 if (inst
.operands
[0].reg
== 5)
9265 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9268 /* If we get through parsing the register name, we just insert the number
9269 generated into the instruction without further validation. */
9270 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9271 inst
.instruction
|= (Rt
<< 12);
9279 if (do_vfp_nsyn_mrs () == SUCCESS
)
9282 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9285 if (inst
.operands
[1].isreg
)
9287 br
= inst
.operands
[1].reg
;
9288 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9289 as_bad (_("bad register for mrs"));
9293 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9294 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9296 _("'APSR', 'CPSR' or 'SPSR' expected"));
9297 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9300 inst
.instruction
|= br
;
9303 /* Two possible forms:
9304 "{C|S}PSR_<field>, Rm",
9305 "{C|S}PSR_f, #expression". */
9310 if (do_vfp_nsyn_msr () == SUCCESS
)
9313 inst
.instruction
|= inst
.operands
[0].imm
;
9314 if (inst
.operands
[1].isreg
)
9315 inst
.instruction
|= inst
.operands
[1].reg
;
9318 inst
.instruction
|= INST_IMMEDIATE
;
9319 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9320 inst
.relocs
[0].pc_rel
= 0;
9327 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9329 if (!inst
.operands
[2].present
)
9330 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9332 inst
.instruction
|= inst
.operands
[1].reg
;
9333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9335 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9336 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9337 as_tsktsk (_("Rd and Rm should be different in mul"));
9340 /* Long Multiply Parser
9341 UMULL RdLo, RdHi, Rm, Rs
9342 SMULL RdLo, RdHi, Rm, Rs
9343 UMLAL RdLo, RdHi, Rm, Rs
9344 SMLAL RdLo, RdHi, Rm, Rs. */
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9351 inst
.instruction
|= inst
.operands
[2].reg
;
9352 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9354 /* rdhi and rdlo must be different. */
9355 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9356 as_tsktsk (_("rdhi and rdlo must be different"));
9358 /* rdhi, rdlo and rm must all be different before armv6. */
9359 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9360 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9361 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9362 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9368 if (inst
.operands
[0].present
9369 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9371 /* Architectural NOP hints are CPSR sets with no bits selected. */
9372 inst
.instruction
&= 0xf0000000;
9373 inst
.instruction
|= 0x0320f000;
9374 if (inst
.operands
[0].present
)
9375 inst
.instruction
|= inst
.operands
[0].imm
;
9379 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9380 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9381 Condition defaults to COND_ALWAYS.
9382 Error if Rd, Rn or Rm are R15. */
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9389 inst
.instruction
|= inst
.operands
[2].reg
;
9390 if (inst
.operands
[3].present
)
9391 encode_arm_shift (3);
9394 /* ARM V6 PKHTB (Argument Parse). */
9399 if (!inst
.operands
[3].present
)
9401 /* If the shift specifier is omitted, turn the instruction
9402 into pkhbt rd, rm, rn. */
9403 inst
.instruction
&= 0xfff00010;
9404 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9405 inst
.instruction
|= inst
.operands
[1].reg
;
9406 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9411 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9412 inst
.instruction
|= inst
.operands
[2].reg
;
9413 encode_arm_shift (3);
9417 /* ARMv5TE: Preload-Cache
9418 MP Extensions: Preload for write
9422 Syntactically, like LDR with B=1, W=0, L=1. */
9427 constraint (!inst
.operands
[0].isreg
,
9428 _("'[' expected after PLD mnemonic"));
9429 constraint (inst
.operands
[0].postind
,
9430 _("post-indexed expression used in preload instruction"));
9431 constraint (inst
.operands
[0].writeback
,
9432 _("writeback used in preload instruction"));
9433 constraint (!inst
.operands
[0].preind
,
9434 _("unindexed addressing used in preload instruction"));
9435 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9438 /* ARMv7: PLI <addr_mode> */
9442 constraint (!inst
.operands
[0].isreg
,
9443 _("'[' expected after PLI mnemonic"));
9444 constraint (inst
.operands
[0].postind
,
9445 _("post-indexed expression used in preload instruction"));
9446 constraint (inst
.operands
[0].writeback
,
9447 _("writeback used in preload instruction"));
9448 constraint (!inst
.operands
[0].preind
,
9449 _("unindexed addressing used in preload instruction"));
9450 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9451 inst
.instruction
&= ~PRE_INDEX
;
9457 constraint (inst
.operands
[0].writeback
,
9458 _("push/pop do not support {reglist}^"));
9459 inst
.operands
[1] = inst
.operands
[0];
9460 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9461 inst
.operands
[0].isreg
= 1;
9462 inst
.operands
[0].writeback
= 1;
9463 inst
.operands
[0].reg
= REG_SP
;
9464 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9467 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9468 word at the specified address and the following word
9470 Unconditionally executed.
9471 Error if Rn is R15. */
9476 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9477 if (inst
.operands
[0].writeback
)
9478 inst
.instruction
|= WRITE_BACK
;
9481 /* ARM V6 ssat (argument parse). */
9486 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9487 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9488 inst
.instruction
|= inst
.operands
[2].reg
;
9490 if (inst
.operands
[3].present
)
9491 encode_arm_shift (3);
9494 /* ARM V6 usat (argument parse). */
9499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9500 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9501 inst
.instruction
|= inst
.operands
[2].reg
;
9503 if (inst
.operands
[3].present
)
9504 encode_arm_shift (3);
9507 /* ARM V6 ssat16 (argument parse). */
9512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9513 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9514 inst
.instruction
|= inst
.operands
[2].reg
;
9520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9521 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9522 inst
.instruction
|= inst
.operands
[2].reg
;
9525 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9526 preserving the other bits.
9528 setend <endian_specifier>, where <endian_specifier> is either
9534 if (warn_on_deprecated
9535 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9536 as_tsktsk (_("setend use is deprecated for ARMv8"));
9538 if (inst
.operands
[0].imm
)
9539 inst
.instruction
|= 0x200;
9545 unsigned int Rm
= (inst
.operands
[1].present
9546 ? inst
.operands
[1].reg
9547 : inst
.operands
[0].reg
);
9549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9550 inst
.instruction
|= Rm
;
9551 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9553 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9554 inst
.instruction
|= SHIFT_BY_REG
;
9555 /* PR 12854: Error on extraneous shifts. */
9556 constraint (inst
.operands
[2].shifted
,
9557 _("extraneous shift as part of operand to shift insn"));
9560 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
9566 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
9567 inst
.relocs
[0].pc_rel
= 0;
9573 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
9574 inst
.relocs
[0].pc_rel
= 0;
9580 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
9581 inst
.relocs
[0].pc_rel
= 0;
9587 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9588 _("selected processor does not support SETPAN instruction"));
9590 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9596 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9597 _("selected processor does not support SETPAN instruction"));
9599 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9602 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9603 SMLAxy{cond} Rd,Rm,Rs,Rn
9604 SMLAWy{cond} Rd,Rm,Rs,Rn
9605 Error if any register is R15. */
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[1].reg
;
9612 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9613 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9616 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9617 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9618 Error if any register is R15.
9619 Warning if Rdlo == Rdhi. */
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9625 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9626 inst
.instruction
|= inst
.operands
[2].reg
;
9627 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9629 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9630 as_tsktsk (_("rdhi and rdlo must be different"));
9633 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9634 SMULxy{cond} Rd,Rm,Rs
9635 Error if any register is R15. */
9640 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9641 inst
.instruction
|= inst
.operands
[1].reg
;
9642 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9645 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9646 the same for both ARM and Thumb-2. */
9653 if (inst
.operands
[0].present
)
9655 reg
= inst
.operands
[0].reg
;
9656 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9661 inst
.instruction
|= reg
<< 16;
9662 inst
.instruction
|= inst
.operands
[1].imm
;
9663 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9664 inst
.instruction
|= WRITE_BACK
;
9667 /* ARM V6 strex (argument parse). */
9672 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9673 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9674 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9675 || inst
.operands
[2].negative
9676 /* See comment in do_ldrex(). */
9677 || (inst
.operands
[2].reg
== REG_PC
),
9680 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9681 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9684 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9685 _("offset must be zero in ARM encoding"));
9687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9688 inst
.instruction
|= inst
.operands
[1].reg
;
9689 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9690 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9696 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9697 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9698 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9699 || inst
.operands
[2].negative
,
9702 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9703 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9711 constraint (inst
.operands
[1].reg
% 2 != 0,
9712 _("even register required"));
9713 constraint (inst
.operands
[2].present
9714 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9715 _("can only store two consecutive registers"));
9716 /* If op 2 were present and equal to PC, this function wouldn't
9717 have been called in the first place. */
9718 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9720 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9721 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9722 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9726 inst
.instruction
|= inst
.operands
[1].reg
;
9727 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9734 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9735 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9743 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9744 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9749 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9750 extends it to 32-bits, and adds the result to a value in another
9751 register. You can specify a rotation by 0, 8, 16, or 24 bits
9752 before extracting the 16-bit value.
9753 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9754 Condition defaults to COND_ALWAYS.
9755 Error if any register uses R15. */
9760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9761 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9762 inst
.instruction
|= inst
.operands
[2].reg
;
9763 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9768 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9769 Condition defaults to COND_ALWAYS.
9770 Error if any register uses R15. */
9775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9776 inst
.instruction
|= inst
.operands
[1].reg
;
9777 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9780 /* VFP instructions. In a logical order: SP variant first, monad
9781 before dyad, arithmetic then move then load/store. */
9784 do_vfp_sp_monadic (void)
9786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9787 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9791 do_vfp_sp_dyadic (void)
9793 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9794 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9795 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9799 do_vfp_sp_compare_z (void)
9801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9805 do_vfp_dp_sp_cvt (void)
9807 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9808 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9812 do_vfp_sp_dp_cvt (void)
9814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9815 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9819 do_vfp_reg_from_sp (void)
9821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9822 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9826 do_vfp_reg2_from_sp2 (void)
9828 constraint (inst
.operands
[2].imm
!= 2,
9829 _("only two consecutive VFP SP registers allowed here"));
9830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9832 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9836 do_vfp_sp_from_reg (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9839 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9843 do_vfp_sp2_from_reg2 (void)
9845 constraint (inst
.operands
[0].imm
!= 2,
9846 _("only two consecutive VFP SP registers allowed here"));
9847 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9848 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9849 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9853 do_vfp_sp_ldst (void)
9855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9856 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9860 do_vfp_dp_ldst (void)
9862 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9863 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9868 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9870 if (inst
.operands
[0].writeback
)
9871 inst
.instruction
|= WRITE_BACK
;
9873 constraint (ldstm_type
!= VFP_LDSTMIA
,
9874 _("this addressing mode requires base-register writeback"));
9875 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9876 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9877 inst
.instruction
|= inst
.operands
[1].imm
;
9881 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9885 if (inst
.operands
[0].writeback
)
9886 inst
.instruction
|= WRITE_BACK
;
9888 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9889 _("this addressing mode requires base-register writeback"));
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9892 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9894 count
= inst
.operands
[1].imm
<< 1;
9895 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9898 inst
.instruction
|= count
;
9902 do_vfp_sp_ldstmia (void)
9904 vfp_sp_ldstm (VFP_LDSTMIA
);
9908 do_vfp_sp_ldstmdb (void)
9910 vfp_sp_ldstm (VFP_LDSTMDB
);
9914 do_vfp_dp_ldstmia (void)
9916 vfp_dp_ldstm (VFP_LDSTMIA
);
9920 do_vfp_dp_ldstmdb (void)
9922 vfp_dp_ldstm (VFP_LDSTMDB
);
9926 do_vfp_xp_ldstmia (void)
9928 vfp_dp_ldstm (VFP_LDSTMIAX
);
9932 do_vfp_xp_ldstmdb (void)
9934 vfp_dp_ldstm (VFP_LDSTMDBX
);
9938 do_vfp_dp_rd_rm (void)
9940 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9941 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9945 do_vfp_dp_rn_rd (void)
9947 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9948 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9952 do_vfp_dp_rd_rn (void)
9954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9955 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9959 do_vfp_dp_rd_rn_rm (void)
9961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9962 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9963 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9969 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9973 do_vfp_dp_rm_rd_rn (void)
9975 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9976 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9977 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9980 /* VFPv3 instructions. */
9982 do_vfp_sp_const (void)
9984 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9985 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9986 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9990 do_vfp_dp_const (void)
9992 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9993 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9994 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9998 vfp_conv (int srcsize
)
10000 int immbits
= srcsize
- inst
.operands
[1].imm
;
10002 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10004 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10005 i.e. immbits must be in range 0 - 16. */
10006 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10009 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10011 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10012 i.e. immbits must be in range 0 - 31. */
10013 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10017 inst
.instruction
|= (immbits
& 1) << 5;
10018 inst
.instruction
|= (immbits
>> 1);
10022 do_vfp_sp_conv_16 (void)
10024 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10029 do_vfp_dp_conv_16 (void)
10031 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10036 do_vfp_sp_conv_32 (void)
10038 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10043 do_vfp_dp_conv_32 (void)
10045 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10049 /* FPA instructions. Also in a logical order. */
10054 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10055 inst
.instruction
|= inst
.operands
[1].reg
;
10059 do_fpa_ldmstm (void)
10061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10062 switch (inst
.operands
[1].imm
)
10064 case 1: inst
.instruction
|= CP_T_X
; break;
10065 case 2: inst
.instruction
|= CP_T_Y
; break;
10066 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10071 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10073 /* The instruction specified "ea" or "fd", so we can only accept
10074 [Rn]{!}. The instruction does not really support stacking or
10075 unstacking, so we have to emulate these by setting appropriate
10076 bits and offsets. */
10077 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10078 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10079 _("this instruction does not support indexing"));
10081 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10082 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10084 if (!(inst
.instruction
& INDEX_UP
))
10085 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10087 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10089 inst
.operands
[2].preind
= 0;
10090 inst
.operands
[2].postind
= 1;
10094 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10097 /* iWMMXt instructions: strictly in alphabetical order. */
10100 do_iwmmxt_tandorc (void)
10102 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10106 do_iwmmxt_textrc (void)
10108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10109 inst
.instruction
|= inst
.operands
[1].imm
;
10113 do_iwmmxt_textrm (void)
10115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10117 inst
.instruction
|= inst
.operands
[2].imm
;
10121 do_iwmmxt_tinsr (void)
10123 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10124 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10125 inst
.instruction
|= inst
.operands
[2].imm
;
10129 do_iwmmxt_tmia (void)
10131 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10132 inst
.instruction
|= inst
.operands
[1].reg
;
10133 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10137 do_iwmmxt_waligni (void)
10139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10140 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10141 inst
.instruction
|= inst
.operands
[2].reg
;
10142 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10146 do_iwmmxt_wmerge (void)
10148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10150 inst
.instruction
|= inst
.operands
[2].reg
;
10151 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10155 do_iwmmxt_wmov (void)
10157 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10159 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10160 inst
.instruction
|= inst
.operands
[1].reg
;
10164 do_iwmmxt_wldstbh (void)
10167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10169 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10171 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10172 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10176 do_iwmmxt_wldstw (void)
10178 /* RIWR_RIWC clears .isreg for a control register. */
10179 if (!inst
.operands
[0].isreg
)
10181 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10182 inst
.instruction
|= 0xf0000000;
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10186 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10190 do_iwmmxt_wldstd (void)
10192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10193 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10194 && inst
.operands
[1].immisreg
)
10196 inst
.instruction
&= ~0x1a000ff;
10197 inst
.instruction
|= (0xfU
<< 28);
10198 if (inst
.operands
[1].preind
)
10199 inst
.instruction
|= PRE_INDEX
;
10200 if (!inst
.operands
[1].negative
)
10201 inst
.instruction
|= INDEX_UP
;
10202 if (inst
.operands
[1].writeback
)
10203 inst
.instruction
|= WRITE_BACK
;
10204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10205 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10206 inst
.instruction
|= inst
.operands
[1].imm
;
10209 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10213 do_iwmmxt_wshufh (void)
10215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10216 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10217 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10218 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10222 do_iwmmxt_wzero (void)
10224 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10225 inst
.instruction
|= inst
.operands
[0].reg
;
10226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10227 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10231 do_iwmmxt_wrwrwr_or_imm5 (void)
10233 if (inst
.operands
[2].isreg
)
10236 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10237 _("immediate operand requires iWMMXt2"));
10239 if (inst
.operands
[2].imm
== 0)
10241 switch ((inst
.instruction
>> 20) & 0xf)
10247 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10248 inst
.operands
[2].imm
= 16;
10249 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10255 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10256 inst
.operands
[2].imm
= 32;
10257 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10264 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10266 wrn
= (inst
.instruction
>> 16) & 0xf;
10267 inst
.instruction
&= 0xff0fff0f;
10268 inst
.instruction
|= wrn
;
10269 /* Bail out here; the instruction is now assembled. */
10274 /* Map 32 -> 0, etc. */
10275 inst
.operands
[2].imm
&= 0x1f;
10276 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10280 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10281 operations first, then control, shift, and load/store. */
10283 /* Insns like "foo X,Y,Z". */
10286 do_mav_triple (void)
10288 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10289 inst
.instruction
|= inst
.operands
[1].reg
;
10290 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10293 /* Insns like "foo W,X,Y,Z".
10294 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10299 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10300 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10301 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10302 inst
.instruction
|= inst
.operands
[3].reg
;
10305 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10307 do_mav_dspsc (void)
10309 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10312 /* Maverick shift immediate instructions.
10313 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10314 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10317 do_mav_shift (void)
10319 int imm
= inst
.operands
[2].imm
;
10321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10322 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10324 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10325 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10326 Bit 4 should be 0. */
10327 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10329 inst
.instruction
|= imm
;
10332 /* XScale instructions. Also sorted arithmetic before move. */
10334 /* Xscale multiply-accumulate (argument parse)
10337 MIAxycc acc0,Rm,Rs. */
10342 inst
.instruction
|= inst
.operands
[1].reg
;
10343 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10346 /* Xscale move-accumulator-register (argument parse)
10348 MARcc acc0,RdLo,RdHi. */
10353 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10354 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10357 /* Xscale move-register-accumulator (argument parse)
10359 MRAcc RdLo,RdHi,acc0. */
10364 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10366 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10369 /* Encoding functions relevant only to Thumb. */
10371 /* inst.operands[i] is a shifted-register operand; encode
10372 it into inst.instruction in the format used by Thumb32. */
10375 encode_thumb32_shifted_operand (int i
)
10377 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10378 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10380 constraint (inst
.operands
[i
].immisreg
,
10381 _("shift by register not allowed in thumb mode"));
10382 inst
.instruction
|= inst
.operands
[i
].reg
;
10383 if (shift
== SHIFT_RRX
)
10384 inst
.instruction
|= SHIFT_ROR
<< 4;
10387 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10388 _("expression too complex"));
10390 constraint (value
> 32
10391 || (value
== 32 && (shift
== SHIFT_LSL
10392 || shift
== SHIFT_ROR
)),
10393 _("shift expression is too large"));
10397 else if (value
== 32)
10400 inst
.instruction
|= shift
<< 4;
10401 inst
.instruction
|= (value
& 0x1c) << 10;
10402 inst
.instruction
|= (value
& 0x03) << 6;
10407 /* inst.operands[i] was set up by parse_address. Encode it into a
10408 Thumb32 format load or store instruction. Reject forms that cannot
10409 be used with such instructions. If is_t is true, reject forms that
10410 cannot be used with a T instruction; if is_d is true, reject forms
10411 that cannot be used with a D instruction. If it is a store insn,
10412 reject PC in Rn. */
10415 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10417 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10419 constraint (!inst
.operands
[i
].isreg
,
10420 _("Instruction does not support =N addresses"));
10422 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10423 if (inst
.operands
[i
].immisreg
)
10425 constraint (is_pc
, BAD_PC_ADDRESSING
);
10426 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10427 constraint (inst
.operands
[i
].negative
,
10428 _("Thumb does not support negative register indexing"));
10429 constraint (inst
.operands
[i
].postind
,
10430 _("Thumb does not support register post-indexing"));
10431 constraint (inst
.operands
[i
].writeback
,
10432 _("Thumb does not support register indexing with writeback"));
10433 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10434 _("Thumb supports only LSL in shifted register indexing"));
10436 inst
.instruction
|= inst
.operands
[i
].imm
;
10437 if (inst
.operands
[i
].shifted
)
10439 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10440 _("expression too complex"));
10441 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10442 || inst
.relocs
[0].exp
.X_add_number
> 3,
10443 _("shift out of range"));
10444 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10446 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10448 else if (inst
.operands
[i
].preind
)
10450 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10451 constraint (is_t
&& inst
.operands
[i
].writeback
,
10452 _("cannot use writeback with this instruction"));
10453 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10454 BAD_PC_ADDRESSING
);
10458 inst
.instruction
|= 0x01000000;
10459 if (inst
.operands
[i
].writeback
)
10460 inst
.instruction
|= 0x00200000;
10464 inst
.instruction
|= 0x00000c00;
10465 if (inst
.operands
[i
].writeback
)
10466 inst
.instruction
|= 0x00000100;
10468 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10470 else if (inst
.operands
[i
].postind
)
10472 gas_assert (inst
.operands
[i
].writeback
);
10473 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10474 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10477 inst
.instruction
|= 0x00200000;
10479 inst
.instruction
|= 0x00000900;
10480 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10482 else /* unindexed - only for coprocessor */
10483 inst
.error
= _("instruction does not accept unindexed addressing");
10486 /* Table of Thumb instructions which exist in both 16- and 32-bit
10487 encodings (the latter only in post-V6T2 cores). The index is the
10488 value used in the insns table below. When there is more than one
10489 possible 16-bit encoding for the instruction, this table always
10491 Also contains several pseudo-instructions used during relaxation. */
10492 #define T16_32_TAB \
10493 X(_adc, 4140, eb400000), \
10494 X(_adcs, 4140, eb500000), \
10495 X(_add, 1c00, eb000000), \
10496 X(_adds, 1c00, eb100000), \
10497 X(_addi, 0000, f1000000), \
10498 X(_addis, 0000, f1100000), \
10499 X(_add_pc,000f, f20f0000), \
10500 X(_add_sp,000d, f10d0000), \
10501 X(_adr, 000f, f20f0000), \
10502 X(_and, 4000, ea000000), \
10503 X(_ands, 4000, ea100000), \
10504 X(_asr, 1000, fa40f000), \
10505 X(_asrs, 1000, fa50f000), \
10506 X(_b, e000, f000b000), \
10507 X(_bcond, d000, f0008000), \
10508 X(_bf, 0000, f040e001), \
10509 X(_bfx, 0000, f060e001), \
10510 X(_bfl, 0000, f000c001), \
10511 X(_bflx, 0000, f070e001), \
10512 X(_bic, 4380, ea200000), \
10513 X(_bics, 4380, ea300000), \
10514 X(_cmn, 42c0, eb100f00), \
10515 X(_cmp, 2800, ebb00f00), \
10516 X(_cpsie, b660, f3af8400), \
10517 X(_cpsid, b670, f3af8600), \
10518 X(_cpy, 4600, ea4f0000), \
10519 X(_dec_sp,80dd, f1ad0d00), \
10520 X(_eor, 4040, ea800000), \
10521 X(_eors, 4040, ea900000), \
10522 X(_inc_sp,00dd, f10d0d00), \
10523 X(_ldmia, c800, e8900000), \
10524 X(_ldr, 6800, f8500000), \
10525 X(_ldrb, 7800, f8100000), \
10526 X(_ldrh, 8800, f8300000), \
10527 X(_ldrsb, 5600, f9100000), \
10528 X(_ldrsh, 5e00, f9300000), \
10529 X(_ldr_pc,4800, f85f0000), \
10530 X(_ldr_pc2,4800, f85f0000), \
10531 X(_ldr_sp,9800, f85d0000), \
10532 X(_lsl, 0000, fa00f000), \
10533 X(_lsls, 0000, fa10f000), \
10534 X(_lsr, 0800, fa20f000), \
10535 X(_lsrs, 0800, fa30f000), \
10536 X(_mov, 2000, ea4f0000), \
10537 X(_movs, 2000, ea5f0000), \
10538 X(_mul, 4340, fb00f000), \
10539 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10540 X(_mvn, 43c0, ea6f0000), \
10541 X(_mvns, 43c0, ea7f0000), \
10542 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10543 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10544 X(_orr, 4300, ea400000), \
10545 X(_orrs, 4300, ea500000), \
10546 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10547 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10548 X(_rev, ba00, fa90f080), \
10549 X(_rev16, ba40, fa90f090), \
10550 X(_revsh, bac0, fa90f0b0), \
10551 X(_ror, 41c0, fa60f000), \
10552 X(_rors, 41c0, fa70f000), \
10553 X(_sbc, 4180, eb600000), \
10554 X(_sbcs, 4180, eb700000), \
10555 X(_stmia, c000, e8800000), \
10556 X(_str, 6000, f8400000), \
10557 X(_strb, 7000, f8000000), \
10558 X(_strh, 8000, f8200000), \
10559 X(_str_sp,9000, f84d0000), \
10560 X(_sub, 1e00, eba00000), \
10561 X(_subs, 1e00, ebb00000), \
10562 X(_subi, 8000, f1a00000), \
10563 X(_subis, 8000, f1b00000), \
10564 X(_sxtb, b240, fa4ff080), \
10565 X(_sxth, b200, fa0ff080), \
10566 X(_tst, 4200, ea100f00), \
10567 X(_uxtb, b2c0, fa5ff080), \
10568 X(_uxth, b280, fa1ff080), \
10569 X(_nop, bf00, f3af8000), \
10570 X(_yield, bf10, f3af8001), \
10571 X(_wfe, bf20, f3af8002), \
10572 X(_wfi, bf30, f3af8003), \
10573 X(_sev, bf40, f3af8004), \
10574 X(_sevl, bf50, f3af8005), \
10575 X(_udf, de00, f7f0a000)
10577 /* To catch errors in encoding functions, the codes are all offset by
10578 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10579 as 16-bit instructions. */
10580 #define X(a,b,c) T_MNEM##a
10581 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10584 #define X(a,b,c) 0x##b
10585 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10586 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10589 #define X(a,b,c) 0x##c
10590 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10591 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10592 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10596 /* Thumb instruction encoders, in alphabetical order. */
10598 /* ADDW or SUBW. */
10601 do_t_add_sub_w (void)
10605 Rd
= inst
.operands
[0].reg
;
10606 Rn
= inst
.operands
[1].reg
;
10608 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10609 is the SP-{plus,minus}-immediate form of the instruction. */
10611 constraint (Rd
== REG_PC
, BAD_PC
);
10613 reject_bad_reg (Rd
);
10615 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10616 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10619 /* Parse an add or subtract instruction. We get here with inst.instruction
10620 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10623 do_t_add_sub (void)
10627 Rd
= inst
.operands
[0].reg
;
10628 Rs
= (inst
.operands
[1].present
10629 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10630 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10633 set_it_insn_type_last ();
10635 if (unified_syntax
)
10638 bfd_boolean narrow
;
10641 flags
= (inst
.instruction
== T_MNEM_adds
10642 || inst
.instruction
== T_MNEM_subs
);
10644 narrow
= !in_it_block ();
10646 narrow
= in_it_block ();
10647 if (!inst
.operands
[2].isreg
)
10651 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10652 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10654 add
= (inst
.instruction
== T_MNEM_add
10655 || inst
.instruction
== T_MNEM_adds
);
10657 if (inst
.size_req
!= 4)
10659 /* Attempt to use a narrow opcode, with relaxation if
10661 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10662 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10663 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10664 opcode
= T_MNEM_add_sp
;
10665 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10666 opcode
= T_MNEM_add_pc
;
10667 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10670 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10672 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10676 inst
.instruction
= THUMB_OP16(opcode
);
10677 inst
.instruction
|= (Rd
<< 4) | Rs
;
10678 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10679 || (inst
.relocs
[0].type
10680 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
10682 if (inst
.size_req
== 2)
10683 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10685 inst
.relax
= opcode
;
10689 constraint (inst
.size_req
== 2, BAD_HIREG
);
10691 if (inst
.size_req
== 4
10692 || (inst
.size_req
!= 2 && !opcode
))
10694 constraint ((inst
.relocs
[0].type
10695 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
10696 && (inst
.relocs
[0].type
10697 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
10698 THUMB1_RELOC_ONLY
);
10701 constraint (add
, BAD_PC
);
10702 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10703 _("only SUBS PC, LR, #const allowed"));
10704 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10705 _("expression too complex"));
10706 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10707 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
10708 _("immediate value out of range"));
10709 inst
.instruction
= T2_SUBS_PC_LR
10710 | inst
.relocs
[0].exp
.X_add_number
;
10711 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10714 else if (Rs
== REG_PC
)
10716 /* Always use addw/subw. */
10717 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10718 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10722 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10723 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10726 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10728 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10730 inst
.instruction
|= Rd
<< 8;
10731 inst
.instruction
|= Rs
<< 16;
10736 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10737 unsigned int shift
= inst
.operands
[2].shift_kind
;
10739 Rn
= inst
.operands
[2].reg
;
10740 /* See if we can do this with a 16-bit instruction. */
10741 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10743 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10748 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10749 || inst
.instruction
== T_MNEM_add
)
10751 : T_OPCODE_SUB_R3
);
10752 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10756 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10758 /* Thumb-1 cores (except v6-M) require at least one high
10759 register in a narrow non flag setting add. */
10760 if (Rd
> 7 || Rn
> 7
10761 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10762 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10769 inst
.instruction
= T_OPCODE_ADD_HI
;
10770 inst
.instruction
|= (Rd
& 8) << 4;
10771 inst
.instruction
|= (Rd
& 7);
10772 inst
.instruction
|= Rn
<< 3;
10778 constraint (Rd
== REG_PC
, BAD_PC
);
10779 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10780 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10781 constraint (Rs
== REG_PC
, BAD_PC
);
10782 reject_bad_reg (Rn
);
10784 /* If we get here, it can't be done in 16 bits. */
10785 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10786 _("shift must be constant"));
10787 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10788 inst
.instruction
|= Rd
<< 8;
10789 inst
.instruction
|= Rs
<< 16;
10790 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10791 _("shift value over 3 not allowed in thumb mode"));
10792 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10793 _("only LSL shift allowed in thumb mode"));
10794 encode_thumb32_shifted_operand (2);
10799 constraint (inst
.instruction
== T_MNEM_adds
10800 || inst
.instruction
== T_MNEM_subs
,
10803 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10805 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10806 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10809 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10810 ? 0x0000 : 0x8000);
10811 inst
.instruction
|= (Rd
<< 4) | Rs
;
10812 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10816 Rn
= inst
.operands
[2].reg
;
10817 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10819 /* We now have Rd, Rs, and Rn set to registers. */
10820 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10822 /* Can't do this for SUB. */
10823 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10824 inst
.instruction
= T_OPCODE_ADD_HI
;
10825 inst
.instruction
|= (Rd
& 8) << 4;
10826 inst
.instruction
|= (Rd
& 7);
10828 inst
.instruction
|= Rn
<< 3;
10830 inst
.instruction
|= Rs
<< 3;
10832 constraint (1, _("dest must overlap one source register"));
10836 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10837 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10838 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10848 Rd
= inst
.operands
[0].reg
;
10849 reject_bad_reg (Rd
);
10851 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10853 /* Defer to section relaxation. */
10854 inst
.relax
= inst
.instruction
;
10855 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10856 inst
.instruction
|= Rd
<< 4;
10858 else if (unified_syntax
&& inst
.size_req
!= 2)
10860 /* Generate a 32-bit opcode. */
10861 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10862 inst
.instruction
|= Rd
<< 8;
10863 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10864 inst
.relocs
[0].pc_rel
= 1;
10868 /* Generate a 16-bit opcode. */
10869 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10870 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10871 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
10872 inst
.relocs
[0].pc_rel
= 1;
10873 inst
.instruction
|= Rd
<< 4;
10876 if (inst
.relocs
[0].exp
.X_op
== O_symbol
10877 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
10878 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
10879 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
10880 inst
.relocs
[0].exp
.X_add_number
+= 1;
10883 /* Arithmetic instructions for which there is just one 16-bit
10884 instruction encoding, and it allows only two low registers.
10885 For maximal compatibility with ARM syntax, we allow three register
10886 operands even when Thumb-32 instructions are not available, as long
10887 as the first two are identical. For instance, both "sbc r0,r1" and
10888 "sbc r0,r0,r1" are allowed. */
10894 Rd
= inst
.operands
[0].reg
;
10895 Rs
= (inst
.operands
[1].present
10896 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10897 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10898 Rn
= inst
.operands
[2].reg
;
10900 reject_bad_reg (Rd
);
10901 reject_bad_reg (Rs
);
10902 if (inst
.operands
[2].isreg
)
10903 reject_bad_reg (Rn
);
10905 if (unified_syntax
)
10907 if (!inst
.operands
[2].isreg
)
10909 /* For an immediate, we always generate a 32-bit opcode;
10910 section relaxation will shrink it later if possible. */
10911 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10912 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10913 inst
.instruction
|= Rd
<< 8;
10914 inst
.instruction
|= Rs
<< 16;
10915 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10919 bfd_boolean narrow
;
10921 /* See if we can do this with a 16-bit instruction. */
10922 if (THUMB_SETS_FLAGS (inst
.instruction
))
10923 narrow
= !in_it_block ();
10925 narrow
= in_it_block ();
10927 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10929 if (inst
.operands
[2].shifted
)
10931 if (inst
.size_req
== 4)
10937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 inst
.instruction
|= Rd
;
10939 inst
.instruction
|= Rn
<< 3;
10943 /* If we get here, it can't be done in 16 bits. */
10944 constraint (inst
.operands
[2].shifted
10945 && inst
.operands
[2].immisreg
,
10946 _("shift must be constant"));
10947 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10948 inst
.instruction
|= Rd
<< 8;
10949 inst
.instruction
|= Rs
<< 16;
10950 encode_thumb32_shifted_operand (2);
10955 /* On its face this is a lie - the instruction does set the
10956 flags. However, the only supported mnemonic in this mode
10957 says it doesn't. */
10958 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10960 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10961 _("unshifted register required"));
10962 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10963 constraint (Rd
!= Rs
,
10964 _("dest and source1 must be the same register"));
10966 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10967 inst
.instruction
|= Rd
;
10968 inst
.instruction
|= Rn
<< 3;
10972 /* Similarly, but for instructions where the arithmetic operation is
10973 commutative, so we can allow either of them to be different from
10974 the destination operand in a 16-bit instruction. For instance, all
10975 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10982 Rd
= inst
.operands
[0].reg
;
10983 Rs
= (inst
.operands
[1].present
10984 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10985 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10986 Rn
= inst
.operands
[2].reg
;
10988 reject_bad_reg (Rd
);
10989 reject_bad_reg (Rs
);
10990 if (inst
.operands
[2].isreg
)
10991 reject_bad_reg (Rn
);
10993 if (unified_syntax
)
10995 if (!inst
.operands
[2].isreg
)
10997 /* For an immediate, we always generate a 32-bit opcode;
10998 section relaxation will shrink it later if possible. */
10999 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11000 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11001 inst
.instruction
|= Rd
<< 8;
11002 inst
.instruction
|= Rs
<< 16;
11003 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11007 bfd_boolean narrow
;
11009 /* See if we can do this with a 16-bit instruction. */
11010 if (THUMB_SETS_FLAGS (inst
.instruction
))
11011 narrow
= !in_it_block ();
11013 narrow
= in_it_block ();
11015 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11017 if (inst
.operands
[2].shifted
)
11019 if (inst
.size_req
== 4)
11026 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11027 inst
.instruction
|= Rd
;
11028 inst
.instruction
|= Rn
<< 3;
11033 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11034 inst
.instruction
|= Rd
;
11035 inst
.instruction
|= Rs
<< 3;
11040 /* If we get here, it can't be done in 16 bits. */
11041 constraint (inst
.operands
[2].shifted
11042 && inst
.operands
[2].immisreg
,
11043 _("shift must be constant"));
11044 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11045 inst
.instruction
|= Rd
<< 8;
11046 inst
.instruction
|= Rs
<< 16;
11047 encode_thumb32_shifted_operand (2);
11052 /* On its face this is a lie - the instruction does set the
11053 flags. However, the only supported mnemonic in this mode
11054 says it doesn't. */
11055 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11057 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11058 _("unshifted register required"));
11059 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11061 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11062 inst
.instruction
|= Rd
;
11065 inst
.instruction
|= Rn
<< 3;
11067 inst
.instruction
|= Rs
<< 3;
11069 constraint (1, _("dest must overlap one source register"));
11077 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11078 constraint (msb
> 32, _("bit-field extends past end of register"));
11079 /* The instruction encoding stores the LSB and MSB,
11080 not the LSB and width. */
11081 Rd
= inst
.operands
[0].reg
;
11082 reject_bad_reg (Rd
);
11083 inst
.instruction
|= Rd
<< 8;
11084 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11085 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11086 inst
.instruction
|= msb
- 1;
11095 Rd
= inst
.operands
[0].reg
;
11096 reject_bad_reg (Rd
);
11098 /* #0 in second position is alternative syntax for bfc, which is
11099 the same instruction but with REG_PC in the Rm field. */
11100 if (!inst
.operands
[1].isreg
)
11104 Rn
= inst
.operands
[1].reg
;
11105 reject_bad_reg (Rn
);
11108 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11109 constraint (msb
> 32, _("bit-field extends past end of register"));
11110 /* The instruction encoding stores the LSB and MSB,
11111 not the LSB and width. */
11112 inst
.instruction
|= Rd
<< 8;
11113 inst
.instruction
|= Rn
<< 16;
11114 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11115 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11116 inst
.instruction
|= msb
- 1;
11124 Rd
= inst
.operands
[0].reg
;
11125 Rn
= inst
.operands
[1].reg
;
11127 reject_bad_reg (Rd
);
11128 reject_bad_reg (Rn
);
11130 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11131 _("bit-field extends past end of register"));
11132 inst
.instruction
|= Rd
<< 8;
11133 inst
.instruction
|= Rn
<< 16;
11134 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11135 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11136 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11139 /* ARM V5 Thumb BLX (argument parse)
11140 BLX <target_addr> which is BLX(1)
11141 BLX <Rm> which is BLX(2)
11142 Unfortunately, there are two different opcodes for this mnemonic.
11143 So, the insns[].value is not used, and the code here zaps values
11144 into inst.instruction.
11146 ??? How to take advantage of the additional two bits of displacement
11147 available in Thumb32 mode? Need new relocation? */
11152 set_it_insn_type_last ();
11154 if (inst
.operands
[0].isreg
)
11156 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11157 /* We have a register, so this is BLX(2). */
11158 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11162 /* No register. This must be BLX(1). */
11163 inst
.instruction
= 0xf000e800;
11164 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11173 bfd_reloc_code_real_type reloc
;
11176 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11178 if (in_it_block ())
11180 /* Conditional branches inside IT blocks are encoded as unconditional
11182 cond
= COND_ALWAYS
;
11187 if (cond
!= COND_ALWAYS
)
11188 opcode
= T_MNEM_bcond
;
11190 opcode
= inst
.instruction
;
11193 && (inst
.size_req
== 4
11194 || (inst
.size_req
!= 2
11195 && (inst
.operands
[0].hasreloc
11196 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11198 inst
.instruction
= THUMB_OP32(opcode
);
11199 if (cond
== COND_ALWAYS
)
11200 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11203 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11204 _("selected architecture does not support "
11205 "wide conditional branch instruction"));
11207 gas_assert (cond
!= 0xF);
11208 inst
.instruction
|= cond
<< 22;
11209 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11214 inst
.instruction
= THUMB_OP16(opcode
);
11215 if (cond
== COND_ALWAYS
)
11216 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11219 inst
.instruction
|= cond
<< 8;
11220 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11222 /* Allow section relaxation. */
11223 if (unified_syntax
&& inst
.size_req
!= 2)
11224 inst
.relax
= opcode
;
11226 inst
.relocs
[0].type
= reloc
;
11227 inst
.relocs
[0].pc_rel
= 1;
11230 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11231 between the two is the maximum immediate allowed - which is passed in
11234 do_t_bkpt_hlt1 (int range
)
11236 constraint (inst
.cond
!= COND_ALWAYS
,
11237 _("instruction is always unconditional"));
11238 if (inst
.operands
[0].present
)
11240 constraint (inst
.operands
[0].imm
> range
,
11241 _("immediate value out of range"));
11242 inst
.instruction
|= inst
.operands
[0].imm
;
11245 set_it_insn_type (NEUTRAL_IT_INSN
);
11251 do_t_bkpt_hlt1 (63);
11257 do_t_bkpt_hlt1 (255);
11261 do_t_branch23 (void)
11263 set_it_insn_type_last ();
11264 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11266 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11267 this file. We used to simply ignore the PLT reloc type here --
11268 the branch encoding is now needed to deal with TLSCALL relocs.
11269 So if we see a PLT reloc now, put it back to how it used to be to
11270 keep the preexisting behaviour. */
11271 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11272 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11274 #if defined(OBJ_COFF)
11275 /* If the destination of the branch is a defined symbol which does not have
11276 the THUMB_FUNC attribute, then we must be calling a function which has
11277 the (interfacearm) attribute. We look for the Thumb entry point to that
11278 function and change the branch to refer to that function instead. */
11279 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11280 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11281 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11282 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11283 inst
.relocs
[0].exp
.X_add_symbol
11284 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11291 set_it_insn_type_last ();
11292 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11293 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11294 should cause the alignment to be checked once it is known. This is
11295 because BX PC only works if the instruction is word aligned. */
11303 set_it_insn_type_last ();
11304 Rm
= inst
.operands
[0].reg
;
11305 reject_bad_reg (Rm
);
11306 inst
.instruction
|= Rm
<< 16;
11315 Rd
= inst
.operands
[0].reg
;
11316 Rm
= inst
.operands
[1].reg
;
11318 reject_bad_reg (Rd
);
11319 reject_bad_reg (Rm
);
11321 inst
.instruction
|= Rd
<< 8;
11322 inst
.instruction
|= Rm
<< 16;
11323 inst
.instruction
|= Rm
;
11329 set_it_insn_type (OUTSIDE_IT_INSN
);
11335 set_it_insn_type (OUTSIDE_IT_INSN
);
11336 inst
.instruction
|= inst
.operands
[0].imm
;
11342 set_it_insn_type (OUTSIDE_IT_INSN
);
11344 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11345 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11347 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11348 inst
.instruction
= 0xf3af8000;
11349 inst
.instruction
|= imod
<< 9;
11350 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11351 if (inst
.operands
[1].present
)
11352 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11356 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11357 && (inst
.operands
[0].imm
& 4),
11358 _("selected processor does not support 'A' form "
11359 "of this instruction"));
11360 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11361 _("Thumb does not support the 2-argument "
11362 "form of this instruction"));
11363 inst
.instruction
|= inst
.operands
[0].imm
;
11367 /* THUMB CPY instruction (argument parse). */
11372 if (inst
.size_req
== 4)
11374 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11375 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11376 inst
.instruction
|= inst
.operands
[1].reg
;
11380 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11381 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11382 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11389 set_it_insn_type (OUTSIDE_IT_INSN
);
11390 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11391 inst
.instruction
|= inst
.operands
[0].reg
;
11392 inst
.relocs
[0].pc_rel
= 1;
11393 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11399 inst
.instruction
|= inst
.operands
[0].imm
;
11405 unsigned Rd
, Rn
, Rm
;
11407 Rd
= inst
.operands
[0].reg
;
11408 Rn
= (inst
.operands
[1].present
11409 ? inst
.operands
[1].reg
: Rd
);
11410 Rm
= inst
.operands
[2].reg
;
11412 reject_bad_reg (Rd
);
11413 reject_bad_reg (Rn
);
11414 reject_bad_reg (Rm
);
11416 inst
.instruction
|= Rd
<< 8;
11417 inst
.instruction
|= Rn
<< 16;
11418 inst
.instruction
|= Rm
;
11424 if (unified_syntax
&& inst
.size_req
== 4)
11425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11427 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11433 unsigned int cond
= inst
.operands
[0].imm
;
11435 set_it_insn_type (IT_INSN
);
11436 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11438 now_it
.warn_deprecated
= FALSE
;
11440 /* If the condition is a negative condition, invert the mask. */
11441 if ((cond
& 0x1) == 0x0)
11443 unsigned int mask
= inst
.instruction
& 0x000f;
11445 if ((mask
& 0x7) == 0)
11447 /* No conversion needed. */
11448 now_it
.block_length
= 1;
11450 else if ((mask
& 0x3) == 0)
11453 now_it
.block_length
= 2;
11455 else if ((mask
& 0x1) == 0)
11458 now_it
.block_length
= 3;
11463 now_it
.block_length
= 4;
11466 inst
.instruction
&= 0xfff0;
11467 inst
.instruction
|= mask
;
11470 inst
.instruction
|= cond
<< 4;
11473 /* Helper function used for both push/pop and ldm/stm. */
11475 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11479 load
= (inst
.instruction
& (1 << 20)) != 0;
11481 if (mask
& (1 << 13))
11482 inst
.error
= _("SP not allowed in register list");
11484 if ((mask
& (1 << base
)) != 0
11486 inst
.error
= _("having the base register in the register list when "
11487 "using write back is UNPREDICTABLE");
11491 if (mask
& (1 << 15))
11493 if (mask
& (1 << 14))
11494 inst
.error
= _("LR and PC should not both be in register list");
11496 set_it_insn_type_last ();
11501 if (mask
& (1 << 15))
11502 inst
.error
= _("PC not allowed in register list");
11505 if ((mask
& (mask
- 1)) == 0)
11507 /* Single register transfers implemented as str/ldr. */
11510 if (inst
.instruction
& (1 << 23))
11511 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11513 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11517 if (inst
.instruction
& (1 << 23))
11518 inst
.instruction
= 0x00800000; /* ia -> [base] */
11520 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11523 inst
.instruction
|= 0xf8400000;
11525 inst
.instruction
|= 0x00100000;
11527 mask
= ffs (mask
) - 1;
11530 else if (writeback
)
11531 inst
.instruction
|= WRITE_BACK
;
11533 inst
.instruction
|= mask
;
11534 inst
.instruction
|= base
<< 16;
11540 /* This really doesn't seem worth it. */
11541 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
11542 _("expression too complex"));
11543 constraint (inst
.operands
[1].writeback
,
11544 _("Thumb load/store multiple does not support {reglist}^"));
11546 if (unified_syntax
)
11548 bfd_boolean narrow
;
11552 /* See if we can use a 16-bit instruction. */
11553 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11554 && inst
.size_req
!= 4
11555 && !(inst
.operands
[1].imm
& ~0xff))
11557 mask
= 1 << inst
.operands
[0].reg
;
11559 if (inst
.operands
[0].reg
<= 7)
11561 if (inst
.instruction
== T_MNEM_stmia
11562 ? inst
.operands
[0].writeback
11563 : (inst
.operands
[0].writeback
11564 == !(inst
.operands
[1].imm
& mask
)))
11566 if (inst
.instruction
== T_MNEM_stmia
11567 && (inst
.operands
[1].imm
& mask
)
11568 && (inst
.operands
[1].imm
& (mask
- 1)))
11569 as_warn (_("value stored for r%d is UNKNOWN"),
11570 inst
.operands
[0].reg
);
11572 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11574 inst
.instruction
|= inst
.operands
[1].imm
;
11577 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11579 /* This means 1 register in reg list one of 3 situations:
11580 1. Instruction is stmia, but without writeback.
11581 2. lmdia without writeback, but with Rn not in
11583 3. ldmia with writeback, but with Rn in reglist.
11584 Case 3 is UNPREDICTABLE behaviour, so we handle
11585 case 1 and 2 which can be converted into a 16-bit
11586 str or ldr. The SP cases are handled below. */
11587 unsigned long opcode
;
11588 /* First, record an error for Case 3. */
11589 if (inst
.operands
[1].imm
& mask
11590 && inst
.operands
[0].writeback
)
11592 _("having the base register in the register list when "
11593 "using write back is UNPREDICTABLE");
11595 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11597 inst
.instruction
= THUMB_OP16 (opcode
);
11598 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11599 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11603 else if (inst
.operands
[0] .reg
== REG_SP
)
11605 if (inst
.operands
[0].writeback
)
11608 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11609 ? T_MNEM_push
: T_MNEM_pop
);
11610 inst
.instruction
|= inst
.operands
[1].imm
;
11613 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11616 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11617 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11618 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11626 if (inst
.instruction
< 0xffff)
11627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11629 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11630 inst
.operands
[0].writeback
);
11635 constraint (inst
.operands
[0].reg
> 7
11636 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11637 constraint (inst
.instruction
!= T_MNEM_ldmia
11638 && inst
.instruction
!= T_MNEM_stmia
,
11639 _("Thumb-2 instruction only valid in unified syntax"));
11640 if (inst
.instruction
== T_MNEM_stmia
)
11642 if (!inst
.operands
[0].writeback
)
11643 as_warn (_("this instruction will write back the base register"));
11644 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11645 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11646 as_warn (_("value stored for r%d is UNKNOWN"),
11647 inst
.operands
[0].reg
);
11651 if (!inst
.operands
[0].writeback
11652 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11653 as_warn (_("this instruction will write back the base register"));
11654 else if (inst
.operands
[0].writeback
11655 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11656 as_warn (_("this instruction will not write back the base register"));
11659 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11660 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11661 inst
.instruction
|= inst
.operands
[1].imm
;
11668 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11669 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11670 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11671 || inst
.operands
[1].negative
,
11674 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11677 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11678 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11684 if (!inst
.operands
[1].present
)
11686 constraint (inst
.operands
[0].reg
== REG_LR
,
11687 _("r14 not allowed as first register "
11688 "when second register is omitted"));
11689 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11691 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11695 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11696 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11702 unsigned long opcode
;
11705 if (inst
.operands
[0].isreg
11706 && !inst
.operands
[0].preind
11707 && inst
.operands
[0].reg
== REG_PC
)
11708 set_it_insn_type_last ();
11710 opcode
= inst
.instruction
;
11711 if (unified_syntax
)
11713 if (!inst
.operands
[1].isreg
)
11715 if (opcode
<= 0xffff)
11716 inst
.instruction
= THUMB_OP32 (opcode
);
11717 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11720 if (inst
.operands
[1].isreg
11721 && !inst
.operands
[1].writeback
11722 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11723 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11724 && opcode
<= 0xffff
11725 && inst
.size_req
!= 4)
11727 /* Insn may have a 16-bit form. */
11728 Rn
= inst
.operands
[1].reg
;
11729 if (inst
.operands
[1].immisreg
)
11731 inst
.instruction
= THUMB_OP16 (opcode
);
11733 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11735 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11736 reject_bad_reg (inst
.operands
[1].imm
);
11738 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11739 && opcode
!= T_MNEM_ldrsb
)
11740 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11741 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11748 if (inst
.relocs
[0].pc_rel
)
11749 opcode
= T_MNEM_ldr_pc2
;
11751 opcode
= T_MNEM_ldr_pc
;
11755 if (opcode
== T_MNEM_ldr
)
11756 opcode
= T_MNEM_ldr_sp
;
11758 opcode
= T_MNEM_str_sp
;
11760 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11764 inst
.instruction
= inst
.operands
[0].reg
;
11765 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11767 inst
.instruction
|= THUMB_OP16 (opcode
);
11768 if (inst
.size_req
== 2)
11769 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11771 inst
.relax
= opcode
;
11775 /* Definitely a 32-bit variant. */
11777 /* Warning for Erratum 752419. */
11778 if (opcode
== T_MNEM_ldr
11779 && inst
.operands
[0].reg
== REG_SP
11780 && inst
.operands
[1].writeback
== 1
11781 && !inst
.operands
[1].immisreg
)
11783 if (no_cpu_selected ()
11784 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11785 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11786 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11787 as_warn (_("This instruction may be unpredictable "
11788 "if executed on M-profile cores "
11789 "with interrupts enabled."));
11792 /* Do some validations regarding addressing modes. */
11793 if (inst
.operands
[1].immisreg
)
11794 reject_bad_reg (inst
.operands
[1].imm
);
11796 constraint (inst
.operands
[1].writeback
== 1
11797 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11800 inst
.instruction
= THUMB_OP32 (opcode
);
11801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11802 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11803 check_ldr_r15_aligned ();
11807 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11809 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11811 /* Only [Rn,Rm] is acceptable. */
11812 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11813 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11814 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11815 || inst
.operands
[1].negative
,
11816 _("Thumb does not support this addressing mode"));
11817 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11822 if (!inst
.operands
[1].isreg
)
11823 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11826 constraint (!inst
.operands
[1].preind
11827 || inst
.operands
[1].shifted
11828 || inst
.operands
[1].writeback
,
11829 _("Thumb does not support this addressing mode"));
11830 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11832 constraint (inst
.instruction
& 0x0600,
11833 _("byte or halfword not valid for base register"));
11834 constraint (inst
.operands
[1].reg
== REG_PC
11835 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11836 _("r15 based store not allowed"));
11837 constraint (inst
.operands
[1].immisreg
,
11838 _("invalid base register for register offset"));
11840 if (inst
.operands
[1].reg
== REG_PC
)
11841 inst
.instruction
= T_OPCODE_LDR_PC
;
11842 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11843 inst
.instruction
= T_OPCODE_LDR_SP
;
11845 inst
.instruction
= T_OPCODE_STR_SP
;
11847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11852 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11853 if (!inst
.operands
[1].immisreg
)
11855 /* Immediate offset. */
11856 inst
.instruction
|= inst
.operands
[0].reg
;
11857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11858 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11862 /* Register offset. */
11863 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11864 constraint (inst
.operands
[1].negative
,
11865 _("Thumb does not support this addressing mode"));
11868 switch (inst
.instruction
)
11870 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11871 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11872 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11873 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11874 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11875 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11876 case 0x5600 /* ldrsb */:
11877 case 0x5e00 /* ldrsh */: break;
11881 inst
.instruction
|= inst
.operands
[0].reg
;
11882 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11883 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11889 if (!inst
.operands
[1].present
)
11891 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11892 constraint (inst
.operands
[0].reg
== REG_LR
,
11893 _("r14 not allowed here"));
11894 constraint (inst
.operands
[0].reg
== REG_R12
,
11895 _("r12 not allowed here"));
11898 if (inst
.operands
[2].writeback
11899 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11900 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11901 as_warn (_("base register written back, and overlaps "
11902 "one of transfer registers"));
11904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11905 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11906 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11913 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11919 unsigned Rd
, Rn
, Rm
, Ra
;
11921 Rd
= inst
.operands
[0].reg
;
11922 Rn
= inst
.operands
[1].reg
;
11923 Rm
= inst
.operands
[2].reg
;
11924 Ra
= inst
.operands
[3].reg
;
11926 reject_bad_reg (Rd
);
11927 reject_bad_reg (Rn
);
11928 reject_bad_reg (Rm
);
11929 reject_bad_reg (Ra
);
11931 inst
.instruction
|= Rd
<< 8;
11932 inst
.instruction
|= Rn
<< 16;
11933 inst
.instruction
|= Rm
;
11934 inst
.instruction
|= Ra
<< 12;
11940 unsigned RdLo
, RdHi
, Rn
, Rm
;
11942 RdLo
= inst
.operands
[0].reg
;
11943 RdHi
= inst
.operands
[1].reg
;
11944 Rn
= inst
.operands
[2].reg
;
11945 Rm
= inst
.operands
[3].reg
;
11947 reject_bad_reg (RdLo
);
11948 reject_bad_reg (RdHi
);
11949 reject_bad_reg (Rn
);
11950 reject_bad_reg (Rm
);
11952 inst
.instruction
|= RdLo
<< 12;
11953 inst
.instruction
|= RdHi
<< 8;
11954 inst
.instruction
|= Rn
<< 16;
11955 inst
.instruction
|= Rm
;
11959 do_t_mov_cmp (void)
11963 Rn
= inst
.operands
[0].reg
;
11964 Rm
= inst
.operands
[1].reg
;
11967 set_it_insn_type_last ();
11969 if (unified_syntax
)
11971 int r0off
= (inst
.instruction
== T_MNEM_mov
11972 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11973 unsigned long opcode
;
11974 bfd_boolean narrow
;
11975 bfd_boolean low_regs
;
11977 low_regs
= (Rn
<= 7 && Rm
<= 7);
11978 opcode
= inst
.instruction
;
11979 if (in_it_block ())
11980 narrow
= opcode
!= T_MNEM_movs
;
11982 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11983 if (inst
.size_req
== 4
11984 || inst
.operands
[1].shifted
)
11987 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11988 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11989 && !inst
.operands
[1].shifted
11993 inst
.instruction
= T2_SUBS_PC_LR
;
11997 if (opcode
== T_MNEM_cmp
)
11999 constraint (Rn
== REG_PC
, BAD_PC
);
12002 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12004 warn_deprecated_sp (Rm
);
12005 /* R15 was documented as a valid choice for Rm in ARMv6,
12006 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12007 tools reject R15, so we do too. */
12008 constraint (Rm
== REG_PC
, BAD_PC
);
12011 reject_bad_reg (Rm
);
12013 else if (opcode
== T_MNEM_mov
12014 || opcode
== T_MNEM_movs
)
12016 if (inst
.operands
[1].isreg
)
12018 if (opcode
== T_MNEM_movs
)
12020 reject_bad_reg (Rn
);
12021 reject_bad_reg (Rm
);
12025 /* This is mov.n. */
12026 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12027 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12029 as_tsktsk (_("Use of r%u as a source register is "
12030 "deprecated when r%u is the destination "
12031 "register."), Rm
, Rn
);
12036 /* This is mov.w. */
12037 constraint (Rn
== REG_PC
, BAD_PC
);
12038 constraint (Rm
== REG_PC
, BAD_PC
);
12039 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12040 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12044 reject_bad_reg (Rn
);
12047 if (!inst
.operands
[1].isreg
)
12049 /* Immediate operand. */
12050 if (!in_it_block () && opcode
== T_MNEM_mov
)
12052 if (low_regs
&& narrow
)
12054 inst
.instruction
= THUMB_OP16 (opcode
);
12055 inst
.instruction
|= Rn
<< 8;
12056 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12057 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12059 if (inst
.size_req
== 2)
12060 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12062 inst
.relax
= opcode
;
12067 constraint ((inst
.relocs
[0].type
12068 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12069 && (inst
.relocs
[0].type
12070 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12071 THUMB1_RELOC_ONLY
);
12073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12074 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12075 inst
.instruction
|= Rn
<< r0off
;
12076 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12079 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12080 && (inst
.instruction
== T_MNEM_mov
12081 || inst
.instruction
== T_MNEM_movs
))
12083 /* Register shifts are encoded as separate shift instructions. */
12084 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12086 if (in_it_block ())
12091 if (inst
.size_req
== 4)
12094 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12100 switch (inst
.operands
[1].shift_kind
)
12103 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12106 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12109 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12112 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12118 inst
.instruction
= opcode
;
12121 inst
.instruction
|= Rn
;
12122 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12127 inst
.instruction
|= CONDS_BIT
;
12129 inst
.instruction
|= Rn
<< 8;
12130 inst
.instruction
|= Rm
<< 16;
12131 inst
.instruction
|= inst
.operands
[1].imm
;
12136 /* Some mov with immediate shift have narrow variants.
12137 Register shifts are handled above. */
12138 if (low_regs
&& inst
.operands
[1].shifted
12139 && (inst
.instruction
== T_MNEM_mov
12140 || inst
.instruction
== T_MNEM_movs
))
12142 if (in_it_block ())
12143 narrow
= (inst
.instruction
== T_MNEM_mov
);
12145 narrow
= (inst
.instruction
== T_MNEM_movs
);
12150 switch (inst
.operands
[1].shift_kind
)
12152 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12153 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12154 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12155 default: narrow
= FALSE
; break;
12161 inst
.instruction
|= Rn
;
12162 inst
.instruction
|= Rm
<< 3;
12163 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12167 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12168 inst
.instruction
|= Rn
<< r0off
;
12169 encode_thumb32_shifted_operand (1);
12173 switch (inst
.instruction
)
12176 /* In v4t or v5t a move of two lowregs produces unpredictable
12177 results. Don't allow this. */
12180 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12181 "MOV Rd, Rs with two low registers is not "
12182 "permitted on this architecture");
12183 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12187 inst
.instruction
= T_OPCODE_MOV_HR
;
12188 inst
.instruction
|= (Rn
& 0x8) << 4;
12189 inst
.instruction
|= (Rn
& 0x7);
12190 inst
.instruction
|= Rm
<< 3;
12194 /* We know we have low registers at this point.
12195 Generate LSLS Rd, Rs, #0. */
12196 inst
.instruction
= T_OPCODE_LSL_I
;
12197 inst
.instruction
|= Rn
;
12198 inst
.instruction
|= Rm
<< 3;
12204 inst
.instruction
= T_OPCODE_CMP_LR
;
12205 inst
.instruction
|= Rn
;
12206 inst
.instruction
|= Rm
<< 3;
12210 inst
.instruction
= T_OPCODE_CMP_HR
;
12211 inst
.instruction
|= (Rn
& 0x8) << 4;
12212 inst
.instruction
|= (Rn
& 0x7);
12213 inst
.instruction
|= Rm
<< 3;
12220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12222 /* PR 10443: Do not silently ignore shifted operands. */
12223 constraint (inst
.operands
[1].shifted
,
12224 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12226 if (inst
.operands
[1].isreg
)
12228 if (Rn
< 8 && Rm
< 8)
12230 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12231 since a MOV instruction produces unpredictable results. */
12232 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12233 inst
.instruction
= T_OPCODE_ADD_I3
;
12235 inst
.instruction
= T_OPCODE_CMP_LR
;
12237 inst
.instruction
|= Rn
;
12238 inst
.instruction
|= Rm
<< 3;
12242 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12243 inst
.instruction
= T_OPCODE_MOV_HR
;
12245 inst
.instruction
= T_OPCODE_CMP_HR
;
12251 constraint (Rn
> 7,
12252 _("only lo regs allowed with immediate"));
12253 inst
.instruction
|= Rn
<< 8;
12254 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12265 top
= (inst
.instruction
& 0x00800000) != 0;
12266 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12268 constraint (top
, _(":lower16: not allowed in this instruction"));
12269 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12271 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12273 constraint (!top
, _(":upper16: not allowed in this instruction"));
12274 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12277 Rd
= inst
.operands
[0].reg
;
12278 reject_bad_reg (Rd
);
12280 inst
.instruction
|= Rd
<< 8;
12281 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12283 imm
= inst
.relocs
[0].exp
.X_add_number
;
12284 inst
.instruction
|= (imm
& 0xf000) << 4;
12285 inst
.instruction
|= (imm
& 0x0800) << 15;
12286 inst
.instruction
|= (imm
& 0x0700) << 4;
12287 inst
.instruction
|= (imm
& 0x00ff);
12292 do_t_mvn_tst (void)
12296 Rn
= inst
.operands
[0].reg
;
12297 Rm
= inst
.operands
[1].reg
;
12299 if (inst
.instruction
== T_MNEM_cmp
12300 || inst
.instruction
== T_MNEM_cmn
)
12301 constraint (Rn
== REG_PC
, BAD_PC
);
12303 reject_bad_reg (Rn
);
12304 reject_bad_reg (Rm
);
12306 if (unified_syntax
)
12308 int r0off
= (inst
.instruction
== T_MNEM_mvn
12309 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12310 bfd_boolean narrow
;
12312 if (inst
.size_req
== 4
12313 || inst
.instruction
> 0xffff
12314 || inst
.operands
[1].shifted
12315 || Rn
> 7 || Rm
> 7)
12317 else if (inst
.instruction
== T_MNEM_cmn
12318 || inst
.instruction
== T_MNEM_tst
)
12320 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12321 narrow
= !in_it_block ();
12323 narrow
= in_it_block ();
12325 if (!inst
.operands
[1].isreg
)
12327 /* For an immediate, we always generate a 32-bit opcode;
12328 section relaxation will shrink it later if possible. */
12329 if (inst
.instruction
< 0xffff)
12330 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12331 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12332 inst
.instruction
|= Rn
<< r0off
;
12333 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12337 /* See if we can do this with a 16-bit instruction. */
12340 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12341 inst
.instruction
|= Rn
;
12342 inst
.instruction
|= Rm
<< 3;
12346 constraint (inst
.operands
[1].shifted
12347 && inst
.operands
[1].immisreg
,
12348 _("shift must be constant"));
12349 if (inst
.instruction
< 0xffff)
12350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12351 inst
.instruction
|= Rn
<< r0off
;
12352 encode_thumb32_shifted_operand (1);
12358 constraint (inst
.instruction
> 0xffff
12359 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12360 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12361 _("unshifted register required"));
12362 constraint (Rn
> 7 || Rm
> 7,
12365 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12366 inst
.instruction
|= Rn
;
12367 inst
.instruction
|= Rm
<< 3;
12376 if (do_vfp_nsyn_mrs () == SUCCESS
)
12379 Rd
= inst
.operands
[0].reg
;
12380 reject_bad_reg (Rd
);
12381 inst
.instruction
|= Rd
<< 8;
12383 if (inst
.operands
[1].isreg
)
12385 unsigned br
= inst
.operands
[1].reg
;
12386 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12387 as_bad (_("bad register for mrs"));
12389 inst
.instruction
|= br
& (0xf << 16);
12390 inst
.instruction
|= (br
& 0x300) >> 4;
12391 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12395 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12397 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12399 /* PR gas/12698: The constraint is only applied for m_profile.
12400 If the user has specified -march=all, we want to ignore it as
12401 we are building for any CPU type, including non-m variants. */
12402 bfd_boolean m_profile
=
12403 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12404 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12405 "not support requested special purpose register"));
12408 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12410 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12411 _("'APSR', 'CPSR' or 'SPSR' expected"));
12413 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12414 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12415 inst
.instruction
|= 0xf0000;
12425 if (do_vfp_nsyn_msr () == SUCCESS
)
12428 constraint (!inst
.operands
[1].isreg
,
12429 _("Thumb encoding does not support an immediate here"));
12431 if (inst
.operands
[0].isreg
)
12432 flags
= (int)(inst
.operands
[0].reg
);
12434 flags
= inst
.operands
[0].imm
;
12436 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12438 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12440 /* PR gas/12698: The constraint is only applied for m_profile.
12441 If the user has specified -march=all, we want to ignore it as
12442 we are building for any CPU type, including non-m variants. */
12443 bfd_boolean m_profile
=
12444 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12445 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12446 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12447 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12448 && bits
!= PSR_f
)) && m_profile
,
12449 _("selected processor does not support requested special "
12450 "purpose register"));
12453 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12454 "requested special purpose register"));
12456 Rn
= inst
.operands
[1].reg
;
12457 reject_bad_reg (Rn
);
12459 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12460 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12461 inst
.instruction
|= (flags
& 0x300) >> 4;
12462 inst
.instruction
|= (flags
& 0xff);
12463 inst
.instruction
|= Rn
<< 16;
12469 bfd_boolean narrow
;
12470 unsigned Rd
, Rn
, Rm
;
12472 if (!inst
.operands
[2].present
)
12473 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12475 Rd
= inst
.operands
[0].reg
;
12476 Rn
= inst
.operands
[1].reg
;
12477 Rm
= inst
.operands
[2].reg
;
12479 if (unified_syntax
)
12481 if (inst
.size_req
== 4
12487 else if (inst
.instruction
== T_MNEM_muls
)
12488 narrow
= !in_it_block ();
12490 narrow
= in_it_block ();
12494 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12495 constraint (Rn
> 7 || Rm
> 7,
12502 /* 16-bit MULS/Conditional MUL. */
12503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12504 inst
.instruction
|= Rd
;
12507 inst
.instruction
|= Rm
<< 3;
12509 inst
.instruction
|= Rn
<< 3;
12511 constraint (1, _("dest must overlap one source register"));
12515 constraint (inst
.instruction
!= T_MNEM_mul
,
12516 _("Thumb-2 MUL must not set flags"));
12518 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12519 inst
.instruction
|= Rd
<< 8;
12520 inst
.instruction
|= Rn
<< 16;
12521 inst
.instruction
|= Rm
<< 0;
12523 reject_bad_reg (Rd
);
12524 reject_bad_reg (Rn
);
12525 reject_bad_reg (Rm
);
12532 unsigned RdLo
, RdHi
, Rn
, Rm
;
12534 RdLo
= inst
.operands
[0].reg
;
12535 RdHi
= inst
.operands
[1].reg
;
12536 Rn
= inst
.operands
[2].reg
;
12537 Rm
= inst
.operands
[3].reg
;
12539 reject_bad_reg (RdLo
);
12540 reject_bad_reg (RdHi
);
12541 reject_bad_reg (Rn
);
12542 reject_bad_reg (Rm
);
12544 inst
.instruction
|= RdLo
<< 12;
12545 inst
.instruction
|= RdHi
<< 8;
12546 inst
.instruction
|= Rn
<< 16;
12547 inst
.instruction
|= Rm
;
12550 as_tsktsk (_("rdhi and rdlo must be different"));
12556 set_it_insn_type (NEUTRAL_IT_INSN
);
12558 if (unified_syntax
)
12560 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12562 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12563 inst
.instruction
|= inst
.operands
[0].imm
;
12567 /* PR9722: Check for Thumb2 availability before
12568 generating a thumb2 nop instruction. */
12569 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12572 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12575 inst
.instruction
= 0x46c0;
12580 constraint (inst
.operands
[0].present
,
12581 _("Thumb does not support NOP with hints"));
12582 inst
.instruction
= 0x46c0;
12589 if (unified_syntax
)
12591 bfd_boolean narrow
;
12593 if (THUMB_SETS_FLAGS (inst
.instruction
))
12594 narrow
= !in_it_block ();
12596 narrow
= in_it_block ();
12597 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12599 if (inst
.size_req
== 4)
12604 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12610 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12611 inst
.instruction
|= inst
.operands
[0].reg
;
12612 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12617 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12619 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12621 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12622 inst
.instruction
|= inst
.operands
[0].reg
;
12623 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12632 Rd
= inst
.operands
[0].reg
;
12633 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12635 reject_bad_reg (Rd
);
12636 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12637 reject_bad_reg (Rn
);
12639 inst
.instruction
|= Rd
<< 8;
12640 inst
.instruction
|= Rn
<< 16;
12642 if (!inst
.operands
[2].isreg
)
12644 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12645 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12651 Rm
= inst
.operands
[2].reg
;
12652 reject_bad_reg (Rm
);
12654 constraint (inst
.operands
[2].shifted
12655 && inst
.operands
[2].immisreg
,
12656 _("shift must be constant"));
12657 encode_thumb32_shifted_operand (2);
12664 unsigned Rd
, Rn
, Rm
;
12666 Rd
= inst
.operands
[0].reg
;
12667 Rn
= inst
.operands
[1].reg
;
12668 Rm
= inst
.operands
[2].reg
;
12670 reject_bad_reg (Rd
);
12671 reject_bad_reg (Rn
);
12672 reject_bad_reg (Rm
);
12674 inst
.instruction
|= Rd
<< 8;
12675 inst
.instruction
|= Rn
<< 16;
12676 inst
.instruction
|= Rm
;
12677 if (inst
.operands
[3].present
)
12679 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
12680 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
12681 _("expression too complex"));
12682 inst
.instruction
|= (val
& 0x1c) << 10;
12683 inst
.instruction
|= (val
& 0x03) << 6;
12690 if (!inst
.operands
[3].present
)
12694 inst
.instruction
&= ~0x00000020;
12696 /* PR 10168. Swap the Rm and Rn registers. */
12697 Rtmp
= inst
.operands
[1].reg
;
12698 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12699 inst
.operands
[2].reg
= Rtmp
;
12707 if (inst
.operands
[0].immisreg
)
12708 reject_bad_reg (inst
.operands
[0].imm
);
12710 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12714 do_t_push_pop (void)
12718 constraint (inst
.operands
[0].writeback
,
12719 _("push/pop do not support {reglist}^"));
12720 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12721 _("expression too complex"));
12723 mask
= inst
.operands
[0].imm
;
12724 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12725 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12726 else if (inst
.size_req
!= 4
12727 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12728 ? REG_LR
: REG_PC
)))
12730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12731 inst
.instruction
|= THUMB_PP_PC_LR
;
12732 inst
.instruction
|= mask
& 0xff;
12734 else if (unified_syntax
)
12736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12737 encode_thumb2_ldmstm (13, mask
, TRUE
);
12741 inst
.error
= _("invalid register list to push/pop instruction");
12751 Rd
= inst
.operands
[0].reg
;
12752 Rm
= inst
.operands
[1].reg
;
12754 reject_bad_reg (Rd
);
12755 reject_bad_reg (Rm
);
12757 inst
.instruction
|= Rd
<< 8;
12758 inst
.instruction
|= Rm
<< 16;
12759 inst
.instruction
|= Rm
;
12767 Rd
= inst
.operands
[0].reg
;
12768 Rm
= inst
.operands
[1].reg
;
12770 reject_bad_reg (Rd
);
12771 reject_bad_reg (Rm
);
12773 if (Rd
<= 7 && Rm
<= 7
12774 && inst
.size_req
!= 4)
12776 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12777 inst
.instruction
|= Rd
;
12778 inst
.instruction
|= Rm
<< 3;
12780 else if (unified_syntax
)
12782 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12783 inst
.instruction
|= Rd
<< 8;
12784 inst
.instruction
|= Rm
<< 16;
12785 inst
.instruction
|= Rm
;
12788 inst
.error
= BAD_HIREG
;
12796 Rd
= inst
.operands
[0].reg
;
12797 Rm
= inst
.operands
[1].reg
;
12799 reject_bad_reg (Rd
);
12800 reject_bad_reg (Rm
);
12802 inst
.instruction
|= Rd
<< 8;
12803 inst
.instruction
|= Rm
;
12811 Rd
= inst
.operands
[0].reg
;
12812 Rs
= (inst
.operands
[1].present
12813 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12814 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12816 reject_bad_reg (Rd
);
12817 reject_bad_reg (Rs
);
12818 if (inst
.operands
[2].isreg
)
12819 reject_bad_reg (inst
.operands
[2].reg
);
12821 inst
.instruction
|= Rd
<< 8;
12822 inst
.instruction
|= Rs
<< 16;
12823 if (!inst
.operands
[2].isreg
)
12825 bfd_boolean narrow
;
12827 if ((inst
.instruction
& 0x00100000) != 0)
12828 narrow
= !in_it_block ();
12830 narrow
= in_it_block ();
12832 if (Rd
> 7 || Rs
> 7)
12835 if (inst
.size_req
== 4 || !unified_syntax
)
12838 if (inst
.relocs
[0].exp
.X_op
!= O_constant
12839 || inst
.relocs
[0].exp
.X_add_number
!= 0)
12842 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12843 relaxation, but it doesn't seem worth the hassle. */
12846 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12847 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12848 inst
.instruction
|= Rs
<< 3;
12849 inst
.instruction
|= Rd
;
12853 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12854 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12858 encode_thumb32_shifted_operand (2);
12864 if (warn_on_deprecated
12865 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12866 as_tsktsk (_("setend use is deprecated for ARMv8"));
12868 set_it_insn_type (OUTSIDE_IT_INSN
);
12869 if (inst
.operands
[0].imm
)
12870 inst
.instruction
|= 0x8;
12876 if (!inst
.operands
[1].present
)
12877 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12879 if (unified_syntax
)
12881 bfd_boolean narrow
;
12884 switch (inst
.instruction
)
12887 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12889 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12891 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12893 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12897 if (THUMB_SETS_FLAGS (inst
.instruction
))
12898 narrow
= !in_it_block ();
12900 narrow
= in_it_block ();
12901 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12903 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12905 if (inst
.operands
[2].isreg
12906 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12907 || inst
.operands
[2].reg
> 7))
12909 if (inst
.size_req
== 4)
12912 reject_bad_reg (inst
.operands
[0].reg
);
12913 reject_bad_reg (inst
.operands
[1].reg
);
12917 if (inst
.operands
[2].isreg
)
12919 reject_bad_reg (inst
.operands
[2].reg
);
12920 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12921 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12922 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12923 inst
.instruction
|= inst
.operands
[2].reg
;
12925 /* PR 12854: Error on extraneous shifts. */
12926 constraint (inst
.operands
[2].shifted
,
12927 _("extraneous shift as part of operand to shift insn"));
12931 inst
.operands
[1].shifted
= 1;
12932 inst
.operands
[1].shift_kind
= shift_kind
;
12933 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12934 ? T_MNEM_movs
: T_MNEM_mov
);
12935 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12936 encode_thumb32_shifted_operand (1);
12937 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12938 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
12943 if (inst
.operands
[2].isreg
)
12945 switch (shift_kind
)
12947 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12948 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12949 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12950 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12954 inst
.instruction
|= inst
.operands
[0].reg
;
12955 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12957 /* PR 12854: Error on extraneous shifts. */
12958 constraint (inst
.operands
[2].shifted
,
12959 _("extraneous shift as part of operand to shift insn"));
12963 switch (shift_kind
)
12965 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12966 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12967 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12970 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12971 inst
.instruction
|= inst
.operands
[0].reg
;
12972 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12978 constraint (inst
.operands
[0].reg
> 7
12979 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12980 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12982 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12984 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12985 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12986 _("source1 and dest must be same register"));
12988 switch (inst
.instruction
)
12990 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12991 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12992 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12993 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12997 inst
.instruction
|= inst
.operands
[0].reg
;
12998 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13000 /* PR 12854: Error on extraneous shifts. */
13001 constraint (inst
.operands
[2].shifted
,
13002 _("extraneous shift as part of operand to shift insn"));
13006 switch (inst
.instruction
)
13008 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13009 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13010 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13011 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13014 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13015 inst
.instruction
|= inst
.operands
[0].reg
;
13016 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13024 unsigned Rd
, Rn
, Rm
;
13026 Rd
= inst
.operands
[0].reg
;
13027 Rn
= inst
.operands
[1].reg
;
13028 Rm
= inst
.operands
[2].reg
;
13030 reject_bad_reg (Rd
);
13031 reject_bad_reg (Rn
);
13032 reject_bad_reg (Rm
);
13034 inst
.instruction
|= Rd
<< 8;
13035 inst
.instruction
|= Rn
<< 16;
13036 inst
.instruction
|= Rm
;
13042 unsigned Rd
, Rn
, Rm
;
13044 Rd
= inst
.operands
[0].reg
;
13045 Rm
= inst
.operands
[1].reg
;
13046 Rn
= inst
.operands
[2].reg
;
13048 reject_bad_reg (Rd
);
13049 reject_bad_reg (Rn
);
13050 reject_bad_reg (Rm
);
13052 inst
.instruction
|= Rd
<< 8;
13053 inst
.instruction
|= Rn
<< 16;
13054 inst
.instruction
|= Rm
;
13060 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13062 _("SMC is not permitted on this architecture"));
13063 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13064 _("expression too complex"));
13065 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13066 inst
.instruction
|= (value
& 0xf000) >> 12;
13067 inst
.instruction
|= (value
& 0x0ff0);
13068 inst
.instruction
|= (value
& 0x000f) << 16;
13069 /* PR gas/15623: SMC instructions must be last in an IT block. */
13070 set_it_insn_type_last ();
13076 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13078 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13079 inst
.instruction
|= (value
& 0x0fff);
13080 inst
.instruction
|= (value
& 0xf000) << 4;
13084 do_t_ssat_usat (int bias
)
13088 Rd
= inst
.operands
[0].reg
;
13089 Rn
= inst
.operands
[2].reg
;
13091 reject_bad_reg (Rd
);
13092 reject_bad_reg (Rn
);
13094 inst
.instruction
|= Rd
<< 8;
13095 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13096 inst
.instruction
|= Rn
<< 16;
13098 if (inst
.operands
[3].present
)
13100 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13102 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13104 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13105 _("expression too complex"));
13107 if (shift_amount
!= 0)
13109 constraint (shift_amount
> 31,
13110 _("shift expression is too large"));
13112 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13113 inst
.instruction
|= 0x00200000; /* sh bit. */
13115 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13116 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13124 do_t_ssat_usat (1);
13132 Rd
= inst
.operands
[0].reg
;
13133 Rn
= inst
.operands
[2].reg
;
13135 reject_bad_reg (Rd
);
13136 reject_bad_reg (Rn
);
13138 inst
.instruction
|= Rd
<< 8;
13139 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13140 inst
.instruction
|= Rn
<< 16;
13146 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13147 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13148 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13149 || inst
.operands
[2].negative
,
13152 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13154 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13155 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13156 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13157 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13163 if (!inst
.operands
[2].present
)
13164 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13166 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13167 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13168 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13171 inst
.instruction
|= inst
.operands
[0].reg
;
13172 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13173 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13174 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13180 unsigned Rd
, Rn
, Rm
;
13182 Rd
= inst
.operands
[0].reg
;
13183 Rn
= inst
.operands
[1].reg
;
13184 Rm
= inst
.operands
[2].reg
;
13186 reject_bad_reg (Rd
);
13187 reject_bad_reg (Rn
);
13188 reject_bad_reg (Rm
);
13190 inst
.instruction
|= Rd
<< 8;
13191 inst
.instruction
|= Rn
<< 16;
13192 inst
.instruction
|= Rm
;
13193 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13201 Rd
= inst
.operands
[0].reg
;
13202 Rm
= inst
.operands
[1].reg
;
13204 reject_bad_reg (Rd
);
13205 reject_bad_reg (Rm
);
13207 if (inst
.instruction
<= 0xffff
13208 && inst
.size_req
!= 4
13209 && Rd
<= 7 && Rm
<= 7
13210 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13212 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13213 inst
.instruction
|= Rd
;
13214 inst
.instruction
|= Rm
<< 3;
13216 else if (unified_syntax
)
13218 if (inst
.instruction
<= 0xffff)
13219 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13220 inst
.instruction
|= Rd
<< 8;
13221 inst
.instruction
|= Rm
;
13222 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13226 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13227 _("Thumb encoding does not support rotation"));
13228 constraint (1, BAD_HIREG
);
13235 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13244 half
= (inst
.instruction
& 0x10) != 0;
13245 set_it_insn_type_last ();
13246 constraint (inst
.operands
[0].immisreg
,
13247 _("instruction requires register index"));
13249 Rn
= inst
.operands
[0].reg
;
13250 Rm
= inst
.operands
[0].imm
;
13252 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13253 constraint (Rn
== REG_SP
, BAD_SP
);
13254 reject_bad_reg (Rm
);
13256 constraint (!half
&& inst
.operands
[0].shifted
,
13257 _("instruction does not allow shifted index"));
13258 inst
.instruction
|= (Rn
<< 16) | Rm
;
13264 if (!inst
.operands
[0].present
)
13265 inst
.operands
[0].imm
= 0;
13267 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13269 constraint (inst
.size_req
== 2,
13270 _("immediate value out of range"));
13271 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13272 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13273 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13277 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13278 inst
.instruction
|= inst
.operands
[0].imm
;
13281 set_it_insn_type (NEUTRAL_IT_INSN
);
13288 do_t_ssat_usat (0);
13296 Rd
= inst
.operands
[0].reg
;
13297 Rn
= inst
.operands
[2].reg
;
13299 reject_bad_reg (Rd
);
13300 reject_bad_reg (Rn
);
13302 inst
.instruction
|= Rd
<< 8;
13303 inst
.instruction
|= inst
.operands
[1].imm
;
13304 inst
.instruction
|= Rn
<< 16;
13307 /* Checking the range of the branch offset (VAL) with NBITS bits
13308 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13310 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13312 gas_assert (nbits
> 0 && nbits
<= 32);
13315 int cmp
= (1 << (nbits
- 1));
13316 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13321 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13327 /* For branches in Armv8.1-M Mainline. */
13329 do_t_branch_future (void)
13331 unsigned long insn
= inst
.instruction
;
13333 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13334 if (inst
.operands
[0].hasreloc
== 0)
13336 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13337 as_bad (BAD_BRANCH_OFF
);
13339 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13343 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13344 inst
.relocs
[0].pc_rel
= 1;
13350 if (inst
.operands
[1].hasreloc
== 0)
13352 int val
= inst
.operands
[1].imm
;
13353 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13354 as_bad (BAD_BRANCH_OFF
);
13356 int immA
= (val
& 0x0001f000) >> 12;
13357 int immB
= (val
& 0x00000ffc) >> 2;
13358 int immC
= (val
& 0x00000002) >> 1;
13359 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13363 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13364 inst
.relocs
[1].pc_rel
= 1;
13369 if (inst
.operands
[1].hasreloc
== 0)
13371 int val
= inst
.operands
[1].imm
;
13372 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13373 as_bad (BAD_BRANCH_OFF
);
13375 int immA
= (val
& 0x0007f000) >> 12;
13376 int immB
= (val
& 0x00000ffc) >> 2;
13377 int immC
= (val
& 0x00000002) >> 1;
13378 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13382 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13383 inst
.relocs
[1].pc_rel
= 1;
13389 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13396 /* Neon instruction encoder helpers. */
13398 /* Encodings for the different types for various Neon opcodes. */
13400 /* An "invalid" code for the following tables. */
13403 struct neon_tab_entry
13406 unsigned float_or_poly
;
13407 unsigned scalar_or_imm
;
13410 /* Map overloaded Neon opcodes to their respective encodings. */
13411 #define NEON_ENC_TAB \
13412 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13413 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13414 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13415 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13416 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13417 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13418 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13419 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13420 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13421 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13422 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13423 /* Register variants of the following two instructions are encoded as
13424 vcge / vcgt with the operands reversed. */ \
13425 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13426 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13427 X(vfma, N_INV, 0x0000c10, N_INV), \
13428 X(vfms, N_INV, 0x0200c10, N_INV), \
13429 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13430 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13431 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13432 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13433 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13434 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13435 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13436 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13437 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13438 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13439 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13440 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13441 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13442 X(vshl, 0x0000400, N_INV, 0x0800510), \
13443 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13444 X(vand, 0x0000110, N_INV, 0x0800030), \
13445 X(vbic, 0x0100110, N_INV, 0x0800030), \
13446 X(veor, 0x1000110, N_INV, N_INV), \
13447 X(vorn, 0x0300110, N_INV, 0x0800010), \
13448 X(vorr, 0x0200110, N_INV, 0x0800010), \
13449 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13450 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13451 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13452 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13453 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13454 X(vst1, 0x0000000, 0x0800000, N_INV), \
13455 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13456 X(vst2, 0x0000100, 0x0800100, N_INV), \
13457 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13458 X(vst3, 0x0000200, 0x0800200, N_INV), \
13459 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13460 X(vst4, 0x0000300, 0x0800300, N_INV), \
13461 X(vmovn, 0x1b20200, N_INV, N_INV), \
13462 X(vtrn, 0x1b20080, N_INV, N_INV), \
13463 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13464 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13465 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13466 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13467 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13468 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13469 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13470 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13471 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13472 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13473 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13474 X(vseleq, 0xe000a00, N_INV, N_INV), \
13475 X(vselvs, 0xe100a00, N_INV, N_INV), \
13476 X(vselge, 0xe200a00, N_INV, N_INV), \
13477 X(vselgt, 0xe300a00, N_INV, N_INV), \
13478 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13479 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13480 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13481 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13482 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13483 X(aes, 0x3b00300, N_INV, N_INV), \
13484 X(sha3op, 0x2000c00, N_INV, N_INV), \
13485 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13486 X(sha2op, 0x3ba0380, N_INV, N_INV)
13490 #define X(OPC,I,F,S) N_MNEM_##OPC
13495 static const struct neon_tab_entry neon_enc_tab
[] =
13497 #define X(OPC,I,F,S) { (I), (F), (S) }
13502 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13503 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13504 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13505 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13506 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13507 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13508 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13509 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13510 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13511 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13512 #define NEON_ENC_SINGLE_(X) \
13513 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13514 #define NEON_ENC_DOUBLE_(X) \
13515 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13516 #define NEON_ENC_FPV8_(X) \
13517 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13519 #define NEON_ENCODE(type, inst) \
13522 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13523 inst.is_neon = 1; \
13527 #define check_neon_suffixes \
13530 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13532 as_bad (_("invalid neon suffix for non neon instruction")); \
13538 /* Define shapes for instruction operands. The following mnemonic characters
13539 are used in this table:
13541 F - VFP S<n> register
13542 D - Neon D<n> register
13543 Q - Neon Q<n> register
13547 L - D<n> register list
13549 This table is used to generate various data:
13550 - enumerations of the form NS_DDR to be used as arguments to
13552 - a table classifying shapes into single, double, quad, mixed.
13553 - a table used to drive neon_select_shape. */
13555 #define NEON_SHAPE_DEF \
13556 X(3, (D, D, D), DOUBLE), \
13557 X(3, (Q, Q, Q), QUAD), \
13558 X(3, (D, D, I), DOUBLE), \
13559 X(3, (Q, Q, I), QUAD), \
13560 X(3, (D, D, S), DOUBLE), \
13561 X(3, (Q, Q, S), QUAD), \
13562 X(2, (D, D), DOUBLE), \
13563 X(2, (Q, Q), QUAD), \
13564 X(2, (D, S), DOUBLE), \
13565 X(2, (Q, S), QUAD), \
13566 X(2, (D, R), DOUBLE), \
13567 X(2, (Q, R), QUAD), \
13568 X(2, (D, I), DOUBLE), \
13569 X(2, (Q, I), QUAD), \
13570 X(3, (D, L, D), DOUBLE), \
13571 X(2, (D, Q), MIXED), \
13572 X(2, (Q, D), MIXED), \
13573 X(3, (D, Q, I), MIXED), \
13574 X(3, (Q, D, I), MIXED), \
13575 X(3, (Q, D, D), MIXED), \
13576 X(3, (D, Q, Q), MIXED), \
13577 X(3, (Q, Q, D), MIXED), \
13578 X(3, (Q, D, S), MIXED), \
13579 X(3, (D, Q, S), MIXED), \
13580 X(4, (D, D, D, I), DOUBLE), \
13581 X(4, (Q, Q, Q, I), QUAD), \
13582 X(4, (D, D, S, I), DOUBLE), \
13583 X(4, (Q, Q, S, I), QUAD), \
13584 X(2, (F, F), SINGLE), \
13585 X(3, (F, F, F), SINGLE), \
13586 X(2, (F, I), SINGLE), \
13587 X(2, (F, D), MIXED), \
13588 X(2, (D, F), MIXED), \
13589 X(3, (F, F, I), MIXED), \
13590 X(4, (R, R, F, F), SINGLE), \
13591 X(4, (F, F, R, R), SINGLE), \
13592 X(3, (D, R, R), DOUBLE), \
13593 X(3, (R, R, D), DOUBLE), \
13594 X(2, (S, R), SINGLE), \
13595 X(2, (R, S), SINGLE), \
13596 X(2, (F, R), SINGLE), \
13597 X(2, (R, F), SINGLE), \
13598 /* Half float shape supported so far. */\
13599 X (2, (H, D), MIXED), \
13600 X (2, (D, H), MIXED), \
13601 X (2, (H, F), MIXED), \
13602 X (2, (F, H), MIXED), \
13603 X (2, (H, H), HALF), \
13604 X (2, (H, R), HALF), \
13605 X (2, (R, H), HALF), \
13606 X (2, (H, I), HALF), \
13607 X (3, (H, H, H), HALF), \
13608 X (3, (H, F, I), MIXED), \
13609 X (3, (F, H, I), MIXED), \
13610 X (3, (D, H, H), MIXED), \
13611 X (3, (D, H, S), MIXED)
13613 #define S2(A,B) NS_##A##B
13614 #define S3(A,B,C) NS_##A##B##C
13615 #define S4(A,B,C,D) NS_##A##B##C##D
13617 #define X(N, L, C) S##N L
13630 enum neon_shape_class
13639 #define X(N, L, C) SC_##C
13641 static enum neon_shape_class neon_shape_class
[] =
13660 /* Register widths of above. */
13661 static unsigned neon_shape_el_size
[] =
13673 struct neon_shape_info
13676 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13679 #define S2(A,B) { SE_##A, SE_##B }
13680 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13681 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13683 #define X(N, L, C) { N, S##N L }
13685 static struct neon_shape_info neon_shape_tab
[] =
13695 /* Bit masks used in type checking given instructions.
13696 'N_EQK' means the type must be the same as (or based on in some way) the key
13697 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13698 set, various other bits can be set as well in order to modify the meaning of
13699 the type constraint. */
13701 enum neon_type_mask
13725 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13726 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13727 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13728 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13729 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13730 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13731 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13732 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13733 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13734 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13735 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13737 N_MAX_NONSPECIAL
= N_P64
13740 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13742 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13743 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13744 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13745 #define N_S_32 (N_S8 | N_S16 | N_S32)
13746 #define N_F_16_32 (N_F16 | N_F32)
13747 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13748 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13749 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13750 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13752 /* Pass this as the first type argument to neon_check_type to ignore types
13754 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13756 /* Select a "shape" for the current instruction (describing register types or
13757 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13758 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13759 function of operand parsing, so this function doesn't need to be called.
13760 Shapes should be listed in order of decreasing length. */
13762 static enum neon_shape
13763 neon_select_shape (enum neon_shape shape
, ...)
13766 enum neon_shape first_shape
= shape
;
13768 /* Fix missing optional operands. FIXME: we don't know at this point how
13769 many arguments we should have, so this makes the assumption that we have
13770 > 1. This is true of all current Neon opcodes, I think, but may not be
13771 true in the future. */
13772 if (!inst
.operands
[1].present
)
13773 inst
.operands
[1] = inst
.operands
[0];
13775 va_start (ap
, shape
);
13777 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13782 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13784 if (!inst
.operands
[j
].present
)
13790 switch (neon_shape_tab
[shape
].el
[j
])
13792 /* If a .f16, .16, .u16, .s16 type specifier is given over
13793 a VFP single precision register operand, it's essentially
13794 means only half of the register is used.
13796 If the type specifier is given after the mnemonics, the
13797 information is stored in inst.vectype. If the type specifier
13798 is given after register operand, the information is stored
13799 in inst.operands[].vectype.
13801 When there is only one type specifier, and all the register
13802 operands are the same type of hardware register, the type
13803 specifier applies to all register operands.
13805 If no type specifier is given, the shape is inferred from
13806 operand information.
13809 vadd.f16 s0, s1, s2: NS_HHH
13810 vabs.f16 s0, s1: NS_HH
13811 vmov.f16 s0, r1: NS_HR
13812 vmov.f16 r0, s1: NS_RH
13813 vcvt.f16 r0, s1: NS_RH
13814 vcvt.f16.s32 s2, s2, #29: NS_HFI
13815 vcvt.f16.s32 s2, s2: NS_HF
13818 if (!(inst
.operands
[j
].isreg
13819 && inst
.operands
[j
].isvec
13820 && inst
.operands
[j
].issingle
13821 && !inst
.operands
[j
].isquad
13822 && ((inst
.vectype
.elems
== 1
13823 && inst
.vectype
.el
[0].size
== 16)
13824 || (inst
.vectype
.elems
> 1
13825 && inst
.vectype
.el
[j
].size
== 16)
13826 || (inst
.vectype
.elems
== 0
13827 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13828 && inst
.operands
[j
].vectype
.size
== 16))))
13833 if (!(inst
.operands
[j
].isreg
13834 && inst
.operands
[j
].isvec
13835 && inst
.operands
[j
].issingle
13836 && !inst
.operands
[j
].isquad
13837 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13838 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13839 || (inst
.vectype
.elems
== 0
13840 && (inst
.operands
[j
].vectype
.size
== 32
13841 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13846 if (!(inst
.operands
[j
].isreg
13847 && inst
.operands
[j
].isvec
13848 && !inst
.operands
[j
].isquad
13849 && !inst
.operands
[j
].issingle
))
13854 if (!(inst
.operands
[j
].isreg
13855 && !inst
.operands
[j
].isvec
))
13860 if (!(inst
.operands
[j
].isreg
13861 && inst
.operands
[j
].isvec
13862 && inst
.operands
[j
].isquad
13863 && !inst
.operands
[j
].issingle
))
13868 if (!(!inst
.operands
[j
].isreg
13869 && !inst
.operands
[j
].isscalar
))
13874 if (!(!inst
.operands
[j
].isreg
13875 && inst
.operands
[j
].isscalar
))
13885 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13886 /* We've matched all the entries in the shape table, and we don't
13887 have any left over operands which have not been matched. */
13893 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13894 first_error (_("invalid instruction shape"));
13899 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13900 means the Q bit should be set). */
13903 neon_quad (enum neon_shape shape
)
13905 return neon_shape_class
[shape
] == SC_QUAD
;
13909 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13912 /* Allow modification to be made to types which are constrained to be
13913 based on the key element, based on bits set alongside N_EQK. */
13914 if ((typebits
& N_EQK
) != 0)
13916 if ((typebits
& N_HLF
) != 0)
13918 else if ((typebits
& N_DBL
) != 0)
13920 if ((typebits
& N_SGN
) != 0)
13921 *g_type
= NT_signed
;
13922 else if ((typebits
& N_UNS
) != 0)
13923 *g_type
= NT_unsigned
;
13924 else if ((typebits
& N_INT
) != 0)
13925 *g_type
= NT_integer
;
13926 else if ((typebits
& N_FLT
) != 0)
13927 *g_type
= NT_float
;
13928 else if ((typebits
& N_SIZ
) != 0)
13929 *g_type
= NT_untyped
;
13933 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13934 operand type, i.e. the single type specified in a Neon instruction when it
13935 is the only one given. */
13937 static struct neon_type_el
13938 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13940 struct neon_type_el dest
= *key
;
13942 gas_assert ((thisarg
& N_EQK
) != 0);
13944 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13949 /* Convert Neon type and size into compact bitmask representation. */
13951 static enum neon_type_mask
13952 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13959 case 8: return N_8
;
13960 case 16: return N_16
;
13961 case 32: return N_32
;
13962 case 64: return N_64
;
13970 case 8: return N_I8
;
13971 case 16: return N_I16
;
13972 case 32: return N_I32
;
13973 case 64: return N_I64
;
13981 case 16: return N_F16
;
13982 case 32: return N_F32
;
13983 case 64: return N_F64
;
13991 case 8: return N_P8
;
13992 case 16: return N_P16
;
13993 case 64: return N_P64
;
14001 case 8: return N_S8
;
14002 case 16: return N_S16
;
14003 case 32: return N_S32
;
14004 case 64: return N_S64
;
14012 case 8: return N_U8
;
14013 case 16: return N_U16
;
14014 case 32: return N_U32
;
14015 case 64: return N_U64
;
14026 /* Convert compact Neon bitmask type representation to a type and size. Only
14027 handles the case where a single bit is set in the mask. */
14030 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14031 enum neon_type_mask mask
)
14033 if ((mask
& N_EQK
) != 0)
14036 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14038 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14040 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14042 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14047 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14049 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14050 *type
= NT_unsigned
;
14051 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14052 *type
= NT_integer
;
14053 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14054 *type
= NT_untyped
;
14055 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14057 else if ((mask
& (N_F_ALL
)) != 0)
14065 /* Modify a bitmask of allowed types. This is only needed for type
14069 modify_types_allowed (unsigned allowed
, unsigned mods
)
14072 enum neon_el_type type
;
14078 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14080 if (el_type_of_type_chk (&type
, &size
,
14081 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14083 neon_modify_type_size (mods
, &type
, &size
);
14084 destmask
|= type_chk_of_el_type (type
, size
);
14091 /* Check type and return type classification.
14092 The manual states (paraphrase): If one datatype is given, it indicates the
14094 - the second operand, if there is one
14095 - the operand, if there is no second operand
14096 - the result, if there are no operands.
14097 This isn't quite good enough though, so we use a concept of a "key" datatype
14098 which is set on a per-instruction basis, which is the one which matters when
14099 only one data type is written.
14100 Note: this function has side-effects (e.g. filling in missing operands). All
14101 Neon instructions should call it before performing bit encoding. */
14103 static struct neon_type_el
14104 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14107 unsigned i
, pass
, key_el
= 0;
14108 unsigned types
[NEON_MAX_TYPE_ELS
];
14109 enum neon_el_type k_type
= NT_invtype
;
14110 unsigned k_size
= -1u;
14111 struct neon_type_el badtype
= {NT_invtype
, -1};
14112 unsigned key_allowed
= 0;
14114 /* Optional registers in Neon instructions are always (not) in operand 1.
14115 Fill in the missing operand here, if it was omitted. */
14116 if (els
> 1 && !inst
.operands
[1].present
)
14117 inst
.operands
[1] = inst
.operands
[0];
14119 /* Suck up all the varargs. */
14121 for (i
= 0; i
< els
; i
++)
14123 unsigned thisarg
= va_arg (ap
, unsigned);
14124 if (thisarg
== N_IGNORE_TYPE
)
14129 types
[i
] = thisarg
;
14130 if ((thisarg
& N_KEY
) != 0)
14135 if (inst
.vectype
.elems
> 0)
14136 for (i
= 0; i
< els
; i
++)
14137 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14139 first_error (_("types specified in both the mnemonic and operands"));
14143 /* Duplicate inst.vectype elements here as necessary.
14144 FIXME: No idea if this is exactly the same as the ARM assembler,
14145 particularly when an insn takes one register and one non-register
14147 if (inst
.vectype
.elems
== 1 && els
> 1)
14150 inst
.vectype
.elems
= els
;
14151 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14152 for (j
= 0; j
< els
; j
++)
14154 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14157 else if (inst
.vectype
.elems
== 0 && els
> 0)
14160 /* No types were given after the mnemonic, so look for types specified
14161 after each operand. We allow some flexibility here; as long as the
14162 "key" operand has a type, we can infer the others. */
14163 for (j
= 0; j
< els
; j
++)
14164 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14165 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14167 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14169 for (j
= 0; j
< els
; j
++)
14170 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14171 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14176 first_error (_("operand types can't be inferred"));
14180 else if (inst
.vectype
.elems
!= els
)
14182 first_error (_("type specifier has the wrong number of parts"));
14186 for (pass
= 0; pass
< 2; pass
++)
14188 for (i
= 0; i
< els
; i
++)
14190 unsigned thisarg
= types
[i
];
14191 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14192 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14193 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14194 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14196 /* Decay more-specific signed & unsigned types to sign-insensitive
14197 integer types if sign-specific variants are unavailable. */
14198 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14199 && (types_allowed
& N_SU_ALL
) == 0)
14200 g_type
= NT_integer
;
14202 /* If only untyped args are allowed, decay any more specific types to
14203 them. Some instructions only care about signs for some element
14204 sizes, so handle that properly. */
14205 if (((types_allowed
& N_UNT
) == 0)
14206 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14207 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14208 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14209 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14210 g_type
= NT_untyped
;
14214 if ((thisarg
& N_KEY
) != 0)
14218 key_allowed
= thisarg
& ~N_KEY
;
14220 /* Check architecture constraint on FP16 extension. */
14222 && k_type
== NT_float
14223 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14225 inst
.error
= _(BAD_FP16
);
14232 if ((thisarg
& N_VFP
) != 0)
14234 enum neon_shape_el regshape
;
14235 unsigned regwidth
, match
;
14237 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14240 first_error (_("invalid instruction shape"));
14243 regshape
= neon_shape_tab
[ns
].el
[i
];
14244 regwidth
= neon_shape_el_size
[regshape
];
14246 /* In VFP mode, operands must match register widths. If we
14247 have a key operand, use its width, else use the width of
14248 the current operand. */
14254 /* FP16 will use a single precision register. */
14255 if (regwidth
== 32 && match
== 16)
14257 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14261 inst
.error
= _(BAD_FP16
);
14266 if (regwidth
!= match
)
14268 first_error (_("operand size must match register width"));
14273 if ((thisarg
& N_EQK
) == 0)
14275 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14277 if ((given_type
& types_allowed
) == 0)
14279 first_error (_("bad type in Neon instruction"));
14285 enum neon_el_type mod_k_type
= k_type
;
14286 unsigned mod_k_size
= k_size
;
14287 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14288 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14290 first_error (_("inconsistent types in Neon instruction"));
14298 return inst
.vectype
.el
[key_el
];
14301 /* Neon-style VFP instruction forwarding. */
14303 /* Thumb VFP instructions have 0xE in the condition field. */
14306 do_vfp_cond_or_thumb (void)
14311 inst
.instruction
|= 0xe0000000;
14313 inst
.instruction
|= inst
.cond
<< 28;
14316 /* Look up and encode a simple mnemonic, for use as a helper function for the
14317 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14318 etc. It is assumed that operand parsing has already been done, and that the
14319 operands are in the form expected by the given opcode (this isn't necessarily
14320 the same as the form in which they were parsed, hence some massaging must
14321 take place before this function is called).
14322 Checks current arch version against that in the looked-up opcode. */
14325 do_vfp_nsyn_opcode (const char *opname
)
14327 const struct asm_opcode
*opcode
;
14329 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14334 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14335 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14342 inst
.instruction
= opcode
->tvalue
;
14343 opcode
->tencode ();
14347 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14348 opcode
->aencode ();
14353 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14355 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14357 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14360 do_vfp_nsyn_opcode ("fadds");
14362 do_vfp_nsyn_opcode ("fsubs");
14364 /* ARMv8.2 fp16 instruction. */
14366 do_scalar_fp16_v82_encode ();
14371 do_vfp_nsyn_opcode ("faddd");
14373 do_vfp_nsyn_opcode ("fsubd");
14377 /* Check operand types to see if this is a VFP instruction, and if so call
14381 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14383 enum neon_shape rs
;
14384 struct neon_type_el et
;
14389 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14390 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14394 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14395 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14396 N_F_ALL
| N_KEY
| N_VFP
);
14403 if (et
.type
!= NT_invtype
)
14414 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14416 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14418 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14421 do_vfp_nsyn_opcode ("fmacs");
14423 do_vfp_nsyn_opcode ("fnmacs");
14425 /* ARMv8.2 fp16 instruction. */
14427 do_scalar_fp16_v82_encode ();
14432 do_vfp_nsyn_opcode ("fmacd");
14434 do_vfp_nsyn_opcode ("fnmacd");
14439 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14441 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14443 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14446 do_vfp_nsyn_opcode ("ffmas");
14448 do_vfp_nsyn_opcode ("ffnmas");
14450 /* ARMv8.2 fp16 instruction. */
14452 do_scalar_fp16_v82_encode ();
14457 do_vfp_nsyn_opcode ("ffmad");
14459 do_vfp_nsyn_opcode ("ffnmad");
14464 do_vfp_nsyn_mul (enum neon_shape rs
)
14466 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14468 do_vfp_nsyn_opcode ("fmuls");
14470 /* ARMv8.2 fp16 instruction. */
14472 do_scalar_fp16_v82_encode ();
14475 do_vfp_nsyn_opcode ("fmuld");
14479 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14481 int is_neg
= (inst
.instruction
& 0x80) != 0;
14482 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14484 if (rs
== NS_FF
|| rs
== NS_HH
)
14487 do_vfp_nsyn_opcode ("fnegs");
14489 do_vfp_nsyn_opcode ("fabss");
14491 /* ARMv8.2 fp16 instruction. */
14493 do_scalar_fp16_v82_encode ();
14498 do_vfp_nsyn_opcode ("fnegd");
14500 do_vfp_nsyn_opcode ("fabsd");
14504 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14505 insns belong to Neon, and are handled elsewhere. */
14508 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14510 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14514 do_vfp_nsyn_opcode ("fldmdbs");
14516 do_vfp_nsyn_opcode ("fldmias");
14521 do_vfp_nsyn_opcode ("fstmdbs");
14523 do_vfp_nsyn_opcode ("fstmias");
14528 do_vfp_nsyn_sqrt (void)
14530 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14531 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14533 if (rs
== NS_FF
|| rs
== NS_HH
)
14535 do_vfp_nsyn_opcode ("fsqrts");
14537 /* ARMv8.2 fp16 instruction. */
14539 do_scalar_fp16_v82_encode ();
14542 do_vfp_nsyn_opcode ("fsqrtd");
14546 do_vfp_nsyn_div (void)
14548 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14549 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14550 N_F_ALL
| N_KEY
| N_VFP
);
14552 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14554 do_vfp_nsyn_opcode ("fdivs");
14556 /* ARMv8.2 fp16 instruction. */
14558 do_scalar_fp16_v82_encode ();
14561 do_vfp_nsyn_opcode ("fdivd");
14565 do_vfp_nsyn_nmul (void)
14567 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14568 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14569 N_F_ALL
| N_KEY
| N_VFP
);
14571 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14573 NEON_ENCODE (SINGLE
, inst
);
14574 do_vfp_sp_dyadic ();
14576 /* ARMv8.2 fp16 instruction. */
14578 do_scalar_fp16_v82_encode ();
14582 NEON_ENCODE (DOUBLE
, inst
);
14583 do_vfp_dp_rd_rn_rm ();
14585 do_vfp_cond_or_thumb ();
14590 do_vfp_nsyn_cmp (void)
14592 enum neon_shape rs
;
14593 if (inst
.operands
[1].isreg
)
14595 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14596 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14598 if (rs
== NS_FF
|| rs
== NS_HH
)
14600 NEON_ENCODE (SINGLE
, inst
);
14601 do_vfp_sp_monadic ();
14605 NEON_ENCODE (DOUBLE
, inst
);
14606 do_vfp_dp_rd_rm ();
14611 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14612 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14614 switch (inst
.instruction
& 0x0fffffff)
14617 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14620 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14626 if (rs
== NS_FI
|| rs
== NS_HI
)
14628 NEON_ENCODE (SINGLE
, inst
);
14629 do_vfp_sp_compare_z ();
14633 NEON_ENCODE (DOUBLE
, inst
);
14637 do_vfp_cond_or_thumb ();
14639 /* ARMv8.2 fp16 instruction. */
14640 if (rs
== NS_HI
|| rs
== NS_HH
)
14641 do_scalar_fp16_v82_encode ();
14645 nsyn_insert_sp (void)
14647 inst
.operands
[1] = inst
.operands
[0];
14648 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14649 inst
.operands
[0].reg
= REG_SP
;
14650 inst
.operands
[0].isreg
= 1;
14651 inst
.operands
[0].writeback
= 1;
14652 inst
.operands
[0].present
= 1;
14656 do_vfp_nsyn_push (void)
14660 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14661 _("register list must contain at least 1 and at most 16 "
14664 if (inst
.operands
[1].issingle
)
14665 do_vfp_nsyn_opcode ("fstmdbs");
14667 do_vfp_nsyn_opcode ("fstmdbd");
14671 do_vfp_nsyn_pop (void)
14675 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14676 _("register list must contain at least 1 and at most 16 "
14679 if (inst
.operands
[1].issingle
)
14680 do_vfp_nsyn_opcode ("fldmias");
14682 do_vfp_nsyn_opcode ("fldmiad");
14685 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14686 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14689 neon_dp_fixup (struct arm_it
* insn
)
14691 unsigned int i
= insn
->instruction
;
14696 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14707 insn
->instruction
= i
;
14710 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14714 neon_logbits (unsigned x
)
14716 return ffs (x
) - 4;
14719 #define LOW4(R) ((R) & 0xf)
14720 #define HI1(R) (((R) >> 4) & 1)
14722 /* Encode insns with bit pattern:
14724 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14725 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14727 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14728 different meaning for some instruction. */
14731 neon_three_same (int isquad
, int ubit
, int size
)
14733 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14734 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14735 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14736 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14737 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14738 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14739 inst
.instruction
|= (isquad
!= 0) << 6;
14740 inst
.instruction
|= (ubit
!= 0) << 24;
14742 inst
.instruction
|= neon_logbits (size
) << 20;
14744 neon_dp_fixup (&inst
);
14747 /* Encode instructions of the form:
14749 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14750 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14752 Don't write size if SIZE == -1. */
14755 neon_two_same (int qbit
, int ubit
, int size
)
14757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14761 inst
.instruction
|= (qbit
!= 0) << 6;
14762 inst
.instruction
|= (ubit
!= 0) << 24;
14765 inst
.instruction
|= neon_logbits (size
) << 18;
14767 neon_dp_fixup (&inst
);
14770 /* Neon instruction encoders, in approximate order of appearance. */
14773 do_neon_dyadic_i_su (void)
14775 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14776 struct neon_type_el et
= neon_check_type (3, rs
,
14777 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14778 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14782 do_neon_dyadic_i64_su (void)
14784 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14785 struct neon_type_el et
= neon_check_type (3, rs
,
14786 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14787 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14791 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14794 unsigned size
= et
.size
>> 3;
14795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14799 inst
.instruction
|= (isquad
!= 0) << 6;
14800 inst
.instruction
|= immbits
<< 16;
14801 inst
.instruction
|= (size
>> 3) << 7;
14802 inst
.instruction
|= (size
& 0x7) << 19;
14804 inst
.instruction
|= (uval
!= 0) << 24;
14806 neon_dp_fixup (&inst
);
14810 do_neon_shl_imm (void)
14812 if (!inst
.operands
[2].isreg
)
14814 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14815 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14816 int imm
= inst
.operands
[2].imm
;
14818 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14819 _("immediate out of range for shift"));
14820 NEON_ENCODE (IMMED
, inst
);
14821 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14825 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14826 struct neon_type_el et
= neon_check_type (3, rs
,
14827 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14830 /* VSHL/VQSHL 3-register variants have syntax such as:
14832 whereas other 3-register operations encoded by neon_three_same have
14835 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14837 tmp
= inst
.operands
[2].reg
;
14838 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14839 inst
.operands
[1].reg
= tmp
;
14840 NEON_ENCODE (INTEGER
, inst
);
14841 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14846 do_neon_qshl_imm (void)
14848 if (!inst
.operands
[2].isreg
)
14850 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14851 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14852 int imm
= inst
.operands
[2].imm
;
14854 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14855 _("immediate out of range for shift"));
14856 NEON_ENCODE (IMMED
, inst
);
14857 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14861 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14862 struct neon_type_el et
= neon_check_type (3, rs
,
14863 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14866 /* See note in do_neon_shl_imm. */
14867 tmp
= inst
.operands
[2].reg
;
14868 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14869 inst
.operands
[1].reg
= tmp
;
14870 NEON_ENCODE (INTEGER
, inst
);
14871 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14876 do_neon_rshl (void)
14878 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14879 struct neon_type_el et
= neon_check_type (3, rs
,
14880 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14883 tmp
= inst
.operands
[2].reg
;
14884 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14885 inst
.operands
[1].reg
= tmp
;
14886 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14890 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14892 /* Handle .I8 pseudo-instructions. */
14895 /* Unfortunately, this will make everything apart from zero out-of-range.
14896 FIXME is this the intended semantics? There doesn't seem much point in
14897 accepting .I8 if so. */
14898 immediate
|= immediate
<< 8;
14904 if (immediate
== (immediate
& 0x000000ff))
14906 *immbits
= immediate
;
14909 else if (immediate
== (immediate
& 0x0000ff00))
14911 *immbits
= immediate
>> 8;
14914 else if (immediate
== (immediate
& 0x00ff0000))
14916 *immbits
= immediate
>> 16;
14919 else if (immediate
== (immediate
& 0xff000000))
14921 *immbits
= immediate
>> 24;
14924 if ((immediate
& 0xffff) != (immediate
>> 16))
14925 goto bad_immediate
;
14926 immediate
&= 0xffff;
14929 if (immediate
== (immediate
& 0x000000ff))
14931 *immbits
= immediate
;
14934 else if (immediate
== (immediate
& 0x0000ff00))
14936 *immbits
= immediate
>> 8;
14941 first_error (_("immediate value out of range"));
14946 do_neon_logic (void)
14948 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14950 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14951 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14952 /* U bit and size field were set as part of the bitmask. */
14953 NEON_ENCODE (INTEGER
, inst
);
14954 neon_three_same (neon_quad (rs
), 0, -1);
14958 const int three_ops_form
= (inst
.operands
[2].present
14959 && !inst
.operands
[2].isreg
);
14960 const int immoperand
= (three_ops_form
? 2 : 1);
14961 enum neon_shape rs
= (three_ops_form
14962 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14963 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14964 struct neon_type_el et
= neon_check_type (2, rs
,
14965 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14966 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14970 if (et
.type
== NT_invtype
)
14973 if (three_ops_form
)
14974 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14975 _("first and second operands shall be the same register"));
14977 NEON_ENCODE (IMMED
, inst
);
14979 immbits
= inst
.operands
[immoperand
].imm
;
14982 /* .i64 is a pseudo-op, so the immediate must be a repeating
14984 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14985 inst
.operands
[immoperand
].reg
: 0))
14987 /* Set immbits to an invalid constant. */
14988 immbits
= 0xdeadbeef;
14995 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14999 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15003 /* Pseudo-instruction for VBIC. */
15004 neon_invert_size (&immbits
, 0, et
.size
);
15005 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15009 /* Pseudo-instruction for VORR. */
15010 neon_invert_size (&immbits
, 0, et
.size
);
15011 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15021 inst
.instruction
|= neon_quad (rs
) << 6;
15022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15024 inst
.instruction
|= cmode
<< 8;
15025 neon_write_immbits (immbits
);
15027 neon_dp_fixup (&inst
);
15032 do_neon_bitfield (void)
15034 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15035 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15036 neon_three_same (neon_quad (rs
), 0, -1);
15040 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15043 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15044 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15046 if (et
.type
== NT_float
)
15048 NEON_ENCODE (FLOAT
, inst
);
15049 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15053 NEON_ENCODE (INTEGER
, inst
);
15054 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15059 do_neon_dyadic_if_su (void)
15061 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15065 do_neon_dyadic_if_su_d (void)
15067 /* This version only allow D registers, but that constraint is enforced during
15068 operand parsing so we don't need to do anything extra here. */
15069 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15073 do_neon_dyadic_if_i_d (void)
15075 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15076 affected if we specify unsigned args. */
15077 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15080 enum vfp_or_neon_is_neon_bits
15083 NEON_CHECK_ARCH
= 2,
15084 NEON_CHECK_ARCH8
= 4
15087 /* Call this function if an instruction which may have belonged to the VFP or
15088 Neon instruction sets, but turned out to be a Neon instruction (due to the
15089 operand types involved, etc.). We have to check and/or fix-up a couple of
15092 - Make sure the user hasn't attempted to make a Neon instruction
15094 - Alter the value in the condition code field if necessary.
15095 - Make sure that the arch supports Neon instructions.
15097 Which of these operations take place depends on bits from enum
15098 vfp_or_neon_is_neon_bits.
15100 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15101 current instruction's condition is COND_ALWAYS, the condition field is
15102 changed to inst.uncond_value. This is necessary because instructions shared
15103 between VFP and Neon may be conditional for the VFP variants only, and the
15104 unconditional Neon version must have, e.g., 0xF in the condition field. */
15107 vfp_or_neon_is_neon (unsigned check
)
15109 /* Conditions are always legal in Thumb mode (IT blocks). */
15110 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15112 if (inst
.cond
!= COND_ALWAYS
)
15114 first_error (_(BAD_COND
));
15117 if (inst
.uncond_value
!= -1)
15118 inst
.instruction
|= inst
.uncond_value
<< 28;
15121 if ((check
& NEON_CHECK_ARCH
)
15122 && !mark_feature_used (&fpu_neon_ext_v1
))
15124 first_error (_(BAD_FPU
));
15128 if ((check
& NEON_CHECK_ARCH8
)
15129 && !mark_feature_used (&fpu_neon_ext_armv8
))
15131 first_error (_(BAD_FPU
));
15139 do_neon_addsub_if_i (void)
15141 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15144 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15147 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15148 affected if we specify unsigned args. */
15149 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15152 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15154 V<op> A,B (A is operand 0, B is operand 2)
15159 so handle that case specially. */
15162 neon_exchange_operands (void)
15164 if (inst
.operands
[1].present
)
15166 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15168 /* Swap operands[1] and operands[2]. */
15169 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15170 inst
.operands
[1] = inst
.operands
[2];
15171 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15176 inst
.operands
[1] = inst
.operands
[2];
15177 inst
.operands
[2] = inst
.operands
[0];
15182 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15184 if (inst
.operands
[2].isreg
)
15187 neon_exchange_operands ();
15188 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15192 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15193 struct neon_type_el et
= neon_check_type (2, rs
,
15194 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15196 NEON_ENCODE (IMMED
, inst
);
15197 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15198 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15199 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15200 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15201 inst
.instruction
|= neon_quad (rs
) << 6;
15202 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15203 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15205 neon_dp_fixup (&inst
);
15212 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15216 do_neon_cmp_inv (void)
15218 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15224 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15227 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15228 scalars, which are encoded in 5 bits, M : Rm.
15229 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15230 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15233 Dot Product instructions are similar to multiply instructions except elsize
15234 should always be 32.
15236 This function translates SCALAR, which is GAS's internal encoding of indexed
15237 scalar register, to raw encoding. There is also register and index range
15238 check based on ELSIZE. */
15241 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15243 unsigned regno
= NEON_SCALAR_REG (scalar
);
15244 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15249 if (regno
> 7 || elno
> 3)
15251 return regno
| (elno
<< 3);
15254 if (regno
> 15 || elno
> 1)
15256 return regno
| (elno
<< 4);
15260 first_error (_("scalar out of range for multiply instruction"));
15266 /* Encode multiply / multiply-accumulate scalar instructions. */
15269 neon_mul_mac (struct neon_type_el et
, int ubit
)
15273 /* Give a more helpful error message if we have an invalid type. */
15274 if (et
.type
== NT_invtype
)
15277 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15278 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15279 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15280 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15281 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15282 inst
.instruction
|= LOW4 (scalar
);
15283 inst
.instruction
|= HI1 (scalar
) << 5;
15284 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15285 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15286 inst
.instruction
|= (ubit
!= 0) << 24;
15288 neon_dp_fixup (&inst
);
15292 do_neon_mac_maybe_scalar (void)
15294 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15297 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15300 if (inst
.operands
[2].isscalar
)
15302 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15303 struct neon_type_el et
= neon_check_type (3, rs
,
15304 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15305 NEON_ENCODE (SCALAR
, inst
);
15306 neon_mul_mac (et
, neon_quad (rs
));
15310 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15311 affected if we specify unsigned args. */
15312 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15317 do_neon_fmac (void)
15319 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15322 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15325 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15331 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15332 struct neon_type_el et
= neon_check_type (3, rs
,
15333 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15334 neon_three_same (neon_quad (rs
), 0, et
.size
);
15337 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15338 same types as the MAC equivalents. The polynomial type for this instruction
15339 is encoded the same as the integer type. */
15344 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15347 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15350 if (inst
.operands
[2].isscalar
)
15351 do_neon_mac_maybe_scalar ();
15353 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15357 do_neon_qdmulh (void)
15359 if (inst
.operands
[2].isscalar
)
15361 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15362 struct neon_type_el et
= neon_check_type (3, rs
,
15363 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15364 NEON_ENCODE (SCALAR
, inst
);
15365 neon_mul_mac (et
, neon_quad (rs
));
15369 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15370 struct neon_type_el et
= neon_check_type (3, rs
,
15371 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15372 NEON_ENCODE (INTEGER
, inst
);
15373 /* The U bit (rounding) comes from bit mask. */
15374 neon_three_same (neon_quad (rs
), 0, et
.size
);
15379 do_neon_qrdmlah (void)
15381 /* Check we're on the correct architecture. */
15382 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15384 _("instruction form not available on this architecture.");
15385 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15387 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15388 record_feature_use (&fpu_neon_ext_v8_1
);
15391 if (inst
.operands
[2].isscalar
)
15393 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15394 struct neon_type_el et
= neon_check_type (3, rs
,
15395 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15396 NEON_ENCODE (SCALAR
, inst
);
15397 neon_mul_mac (et
, neon_quad (rs
));
15401 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15402 struct neon_type_el et
= neon_check_type (3, rs
,
15403 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15404 NEON_ENCODE (INTEGER
, inst
);
15405 /* The U bit (rounding) comes from bit mask. */
15406 neon_three_same (neon_quad (rs
), 0, et
.size
);
15411 do_neon_fcmp_absolute (void)
15413 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15414 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15415 N_F_16_32
| N_KEY
);
15416 /* Size field comes from bit mask. */
15417 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15421 do_neon_fcmp_absolute_inv (void)
15423 neon_exchange_operands ();
15424 do_neon_fcmp_absolute ();
15428 do_neon_step (void)
15430 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15431 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15432 N_F_16_32
| N_KEY
);
15433 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15437 do_neon_abs_neg (void)
15439 enum neon_shape rs
;
15440 struct neon_type_el et
;
15442 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15445 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15448 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15449 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15451 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15453 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15455 inst
.instruction
|= neon_quad (rs
) << 6;
15456 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15457 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15459 neon_dp_fixup (&inst
);
15465 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15466 struct neon_type_el et
= neon_check_type (2, rs
,
15467 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15468 int imm
= inst
.operands
[2].imm
;
15469 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15470 _("immediate out of range for insert"));
15471 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15477 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15478 struct neon_type_el et
= neon_check_type (2, rs
,
15479 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15480 int imm
= inst
.operands
[2].imm
;
15481 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15482 _("immediate out of range for insert"));
15483 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15487 do_neon_qshlu_imm (void)
15489 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15490 struct neon_type_el et
= neon_check_type (2, rs
,
15491 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15492 int imm
= inst
.operands
[2].imm
;
15493 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15494 _("immediate out of range for shift"));
15495 /* Only encodes the 'U present' variant of the instruction.
15496 In this case, signed types have OP (bit 8) set to 0.
15497 Unsigned types have OP set to 1. */
15498 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15499 /* The rest of the bits are the same as other immediate shifts. */
15500 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15504 do_neon_qmovn (void)
15506 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15507 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15508 /* Saturating move where operands can be signed or unsigned, and the
15509 destination has the same signedness. */
15510 NEON_ENCODE (INTEGER
, inst
);
15511 if (et
.type
== NT_unsigned
)
15512 inst
.instruction
|= 0xc0;
15514 inst
.instruction
|= 0x80;
15515 neon_two_same (0, 1, et
.size
/ 2);
15519 do_neon_qmovun (void)
15521 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15522 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15523 /* Saturating move with unsigned results. Operands must be signed. */
15524 NEON_ENCODE (INTEGER
, inst
);
15525 neon_two_same (0, 1, et
.size
/ 2);
15529 do_neon_rshift_sat_narrow (void)
15531 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15532 or unsigned. If operands are unsigned, results must also be unsigned. */
15533 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15534 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15535 int imm
= inst
.operands
[2].imm
;
15536 /* This gets the bounds check, size encoding and immediate bits calculation
15540 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15541 VQMOVN.I<size> <Dd>, <Qm>. */
15544 inst
.operands
[2].present
= 0;
15545 inst
.instruction
= N_MNEM_vqmovn
;
15550 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15551 _("immediate out of range"));
15552 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15556 do_neon_rshift_sat_narrow_u (void)
15558 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15559 or unsigned. If operands are unsigned, results must also be unsigned. */
15560 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15561 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15562 int imm
= inst
.operands
[2].imm
;
15563 /* This gets the bounds check, size encoding and immediate bits calculation
15567 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15568 VQMOVUN.I<size> <Dd>, <Qm>. */
15571 inst
.operands
[2].present
= 0;
15572 inst
.instruction
= N_MNEM_vqmovun
;
15577 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15578 _("immediate out of range"));
15579 /* FIXME: The manual is kind of unclear about what value U should have in
15580 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15582 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15586 do_neon_movn (void)
15588 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15589 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15590 NEON_ENCODE (INTEGER
, inst
);
15591 neon_two_same (0, 1, et
.size
/ 2);
15595 do_neon_rshift_narrow (void)
15597 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15598 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15599 int imm
= inst
.operands
[2].imm
;
15600 /* This gets the bounds check, size encoding and immediate bits calculation
15604 /* If immediate is zero then we are a pseudo-instruction for
15605 VMOVN.I<size> <Dd>, <Qm> */
15608 inst
.operands
[2].present
= 0;
15609 inst
.instruction
= N_MNEM_vmovn
;
15614 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15615 _("immediate out of range for narrowing operation"));
15616 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15620 do_neon_shll (void)
15622 /* FIXME: Type checking when lengthening. */
15623 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15624 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15625 unsigned imm
= inst
.operands
[2].imm
;
15627 if (imm
== et
.size
)
15629 /* Maximum shift variant. */
15630 NEON_ENCODE (INTEGER
, inst
);
15631 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15632 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15635 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15637 neon_dp_fixup (&inst
);
15641 /* A more-specific type check for non-max versions. */
15642 et
= neon_check_type (2, NS_QDI
,
15643 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15644 NEON_ENCODE (IMMED
, inst
);
15645 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15649 /* Check the various types for the VCVT instruction, and return which version
15650 the current instruction is. */
15652 #define CVT_FLAVOUR_VAR \
15653 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15654 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15655 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15656 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15657 /* Half-precision conversions. */ \
15658 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15659 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15660 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15661 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15662 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15663 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15664 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15665 Compared with single/double precision variants, only the co-processor \
15666 field is different, so the encoding flow is reused here. */ \
15667 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15668 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15669 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15670 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15671 /* VFP instructions. */ \
15672 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15673 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15674 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15675 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15676 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15677 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15678 /* VFP instructions with bitshift. */ \
15679 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15680 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15681 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15682 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15683 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15684 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15685 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15686 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15688 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15689 neon_cvt_flavour_##C,
15691 /* The different types of conversions we can do. */
15692 enum neon_cvt_flavour
15695 neon_cvt_flavour_invalid
,
15696 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15701 static enum neon_cvt_flavour
15702 get_neon_cvt_flavour (enum neon_shape rs
)
15704 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15705 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15706 if (et.type != NT_invtype) \
15708 inst.error = NULL; \
15709 return (neon_cvt_flavour_##C); \
15712 struct neon_type_el et
;
15713 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15714 || rs
== NS_FF
) ? N_VFP
: 0;
15715 /* The instruction versions which take an immediate take one register
15716 argument, which is extended to the width of the full register. Thus the
15717 "source" and "destination" registers must have the same width. Hack that
15718 here by making the size equal to the key (wider, in this case) operand. */
15719 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15723 return neon_cvt_flavour_invalid
;
15738 /* Neon-syntax VFP conversions. */
15741 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15743 const char *opname
= 0;
15745 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15746 || rs
== NS_FHI
|| rs
== NS_HFI
)
15748 /* Conversions with immediate bitshift. */
15749 const char *enc
[] =
15751 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15757 if (flavour
< (int) ARRAY_SIZE (enc
))
15759 opname
= enc
[flavour
];
15760 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15761 _("operands 0 and 1 must be the same register"));
15762 inst
.operands
[1] = inst
.operands
[2];
15763 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15768 /* Conversions without bitshift. */
15769 const char *enc
[] =
15771 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15777 if (flavour
< (int) ARRAY_SIZE (enc
))
15778 opname
= enc
[flavour
];
15782 do_vfp_nsyn_opcode (opname
);
15784 /* ARMv8.2 fp16 VCVT instruction. */
15785 if (flavour
== neon_cvt_flavour_s32_f16
15786 || flavour
== neon_cvt_flavour_u32_f16
15787 || flavour
== neon_cvt_flavour_f16_u32
15788 || flavour
== neon_cvt_flavour_f16_s32
)
15789 do_scalar_fp16_v82_encode ();
15793 do_vfp_nsyn_cvtz (void)
15795 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15796 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15797 const char *enc
[] =
15799 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15805 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15806 do_vfp_nsyn_opcode (enc
[flavour
]);
15810 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15811 enum neon_cvt_mode mode
)
15816 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15817 D register operands. */
15818 if (flavour
== neon_cvt_flavour_s32_f64
15819 || flavour
== neon_cvt_flavour_u32_f64
)
15820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15823 if (flavour
== neon_cvt_flavour_s32_f16
15824 || flavour
== neon_cvt_flavour_u32_f16
)
15825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15828 set_it_insn_type (OUTSIDE_IT_INSN
);
15832 case neon_cvt_flavour_s32_f64
:
15836 case neon_cvt_flavour_s32_f32
:
15840 case neon_cvt_flavour_s32_f16
:
15844 case neon_cvt_flavour_u32_f64
:
15848 case neon_cvt_flavour_u32_f32
:
15852 case neon_cvt_flavour_u32_f16
:
15857 first_error (_("invalid instruction shape"));
15863 case neon_cvt_mode_a
: rm
= 0; break;
15864 case neon_cvt_mode_n
: rm
= 1; break;
15865 case neon_cvt_mode_p
: rm
= 2; break;
15866 case neon_cvt_mode_m
: rm
= 3; break;
15867 default: first_error (_("invalid rounding mode")); return;
15870 NEON_ENCODE (FPV8
, inst
);
15871 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15872 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15873 inst
.instruction
|= sz
<< 8;
15875 /* ARMv8.2 fp16 VCVT instruction. */
15876 if (flavour
== neon_cvt_flavour_s32_f16
15877 ||flavour
== neon_cvt_flavour_u32_f16
)
15878 do_scalar_fp16_v82_encode ();
15879 inst
.instruction
|= op
<< 7;
15880 inst
.instruction
|= rm
<< 16;
15881 inst
.instruction
|= 0xf0000000;
15882 inst
.is_neon
= TRUE
;
15886 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15888 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15889 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15890 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15892 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15894 if (flavour
== neon_cvt_flavour_invalid
)
15897 /* PR11109: Handle round-to-zero for VCVT conversions. */
15898 if (mode
== neon_cvt_mode_z
15899 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15900 && (flavour
== neon_cvt_flavour_s16_f16
15901 || flavour
== neon_cvt_flavour_u16_f16
15902 || flavour
== neon_cvt_flavour_s32_f32
15903 || flavour
== neon_cvt_flavour_u32_f32
15904 || flavour
== neon_cvt_flavour_s32_f64
15905 || flavour
== neon_cvt_flavour_u32_f64
)
15906 && (rs
== NS_FD
|| rs
== NS_FF
))
15908 do_vfp_nsyn_cvtz ();
15912 /* ARMv8.2 fp16 VCVT conversions. */
15913 if (mode
== neon_cvt_mode_z
15914 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15915 && (flavour
== neon_cvt_flavour_s32_f16
15916 || flavour
== neon_cvt_flavour_u32_f16
)
15919 do_vfp_nsyn_cvtz ();
15920 do_scalar_fp16_v82_encode ();
15924 /* VFP rather than Neon conversions. */
15925 if (flavour
>= neon_cvt_flavour_first_fp
)
15927 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15928 do_vfp_nsyn_cvt (rs
, flavour
);
15930 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15941 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15942 0x0000100, 0x1000100, 0x0, 0x1000000};
15944 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15947 /* Fixed-point conversion with #0 immediate is encoded as an
15948 integer conversion. */
15949 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15951 NEON_ENCODE (IMMED
, inst
);
15952 if (flavour
!= neon_cvt_flavour_invalid
)
15953 inst
.instruction
|= enctab
[flavour
];
15954 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15955 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15956 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15957 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15958 inst
.instruction
|= neon_quad (rs
) << 6;
15959 inst
.instruction
|= 1 << 21;
15960 if (flavour
< neon_cvt_flavour_s16_f16
)
15962 inst
.instruction
|= 1 << 21;
15963 immbits
= 32 - inst
.operands
[2].imm
;
15964 inst
.instruction
|= immbits
<< 16;
15968 inst
.instruction
|= 3 << 20;
15969 immbits
= 16 - inst
.operands
[2].imm
;
15970 inst
.instruction
|= immbits
<< 16;
15971 inst
.instruction
&= ~(1 << 9);
15974 neon_dp_fixup (&inst
);
15980 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15982 NEON_ENCODE (FLOAT
, inst
);
15983 set_it_insn_type (OUTSIDE_IT_INSN
);
15985 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15988 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15989 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15990 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15991 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15992 inst
.instruction
|= neon_quad (rs
) << 6;
15993 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15994 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15995 inst
.instruction
|= mode
<< 8;
15996 if (flavour
== neon_cvt_flavour_u16_f16
15997 || flavour
== neon_cvt_flavour_s16_f16
)
15998 /* Mask off the original size bits and reencode them. */
15999 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
16002 inst
.instruction
|= 0xfc000000;
16004 inst
.instruction
|= 0xf0000000;
16010 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
16011 0x100, 0x180, 0x0, 0x080};
16013 NEON_ENCODE (INTEGER
, inst
);
16015 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16018 if (flavour
!= neon_cvt_flavour_invalid
)
16019 inst
.instruction
|= enctab
[flavour
];
16021 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16022 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16023 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16024 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16025 inst
.instruction
|= neon_quad (rs
) << 6;
16026 if (flavour
>= neon_cvt_flavour_s16_f16
16027 && flavour
<= neon_cvt_flavour_f16_u16
)
16028 /* Half precision. */
16029 inst
.instruction
|= 1 << 18;
16031 inst
.instruction
|= 2 << 18;
16033 neon_dp_fixup (&inst
);
16038 /* Half-precision conversions for Advanced SIMD -- neon. */
16041 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16045 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
16047 as_bad (_("operand size must match register width"));
16052 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
16054 as_bad (_("operand size must match register width"));
16059 inst
.instruction
= 0x3b60600;
16061 inst
.instruction
= 0x3b60700;
16063 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16064 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16065 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16066 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16067 neon_dp_fixup (&inst
);
16071 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
16072 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16073 do_vfp_nsyn_cvt (rs
, flavour
);
16075 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16080 do_neon_cvtr (void)
16082 do_neon_cvt_1 (neon_cvt_mode_x
);
16088 do_neon_cvt_1 (neon_cvt_mode_z
);
16092 do_neon_cvta (void)
16094 do_neon_cvt_1 (neon_cvt_mode_a
);
16098 do_neon_cvtn (void)
16100 do_neon_cvt_1 (neon_cvt_mode_n
);
16104 do_neon_cvtp (void)
16106 do_neon_cvt_1 (neon_cvt_mode_p
);
16110 do_neon_cvtm (void)
16112 do_neon_cvt_1 (neon_cvt_mode_m
);
16116 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16119 mark_feature_used (&fpu_vfp_ext_armv8
);
16121 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16122 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16123 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16124 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16125 inst
.instruction
|= to
? 0x10000 : 0;
16126 inst
.instruction
|= t
? 0x80 : 0;
16127 inst
.instruction
|= is_double
? 0x100 : 0;
16128 do_vfp_cond_or_thumb ();
16132 do_neon_cvttb_1 (bfd_boolean t
)
16134 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16135 NS_DF
, NS_DH
, NS_NULL
);
16139 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16142 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16144 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16147 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16149 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16151 /* The VCVTB and VCVTT instructions with D-register operands
16152 don't work for SP only targets. */
16153 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16157 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16159 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16161 /* The VCVTB and VCVTT instructions with D-register operands
16162 don't work for SP only targets. */
16163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16167 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16174 do_neon_cvtb (void)
16176 do_neon_cvttb_1 (FALSE
);
16181 do_neon_cvtt (void)
16183 do_neon_cvttb_1 (TRUE
);
16187 neon_move_immediate (void)
16189 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16190 struct neon_type_el et
= neon_check_type (2, rs
,
16191 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16192 unsigned immlo
, immhi
= 0, immbits
;
16193 int op
, cmode
, float_p
;
16195 constraint (et
.type
== NT_invtype
,
16196 _("operand size must be specified for immediate VMOV"));
16198 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16199 op
= (inst
.instruction
& (1 << 5)) != 0;
16201 immlo
= inst
.operands
[1].imm
;
16202 if (inst
.operands
[1].regisimm
)
16203 immhi
= inst
.operands
[1].reg
;
16205 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16206 _("immediate has bits set outside the operand size"));
16208 float_p
= inst
.operands
[1].immisfloat
;
16210 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16211 et
.size
, et
.type
)) == FAIL
)
16213 /* Invert relevant bits only. */
16214 neon_invert_size (&immlo
, &immhi
, et
.size
);
16215 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16216 with one or the other; those cases are caught by
16217 neon_cmode_for_move_imm. */
16219 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16220 &op
, et
.size
, et
.type
)) == FAIL
)
16222 first_error (_("immediate out of range"));
16227 inst
.instruction
&= ~(1 << 5);
16228 inst
.instruction
|= op
<< 5;
16230 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16231 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16232 inst
.instruction
|= neon_quad (rs
) << 6;
16233 inst
.instruction
|= cmode
<< 8;
16235 neon_write_immbits (immbits
);
16241 if (inst
.operands
[1].isreg
)
16243 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16245 NEON_ENCODE (INTEGER
, inst
);
16246 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16247 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16248 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16249 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16250 inst
.instruction
|= neon_quad (rs
) << 6;
16254 NEON_ENCODE (IMMED
, inst
);
16255 neon_move_immediate ();
16258 neon_dp_fixup (&inst
);
16261 /* Encode instructions of form:
16263 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16264 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16267 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16269 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16270 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16271 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16272 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16273 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16274 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16275 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16276 inst
.instruction
|= neon_logbits (size
) << 20;
16278 neon_dp_fixup (&inst
);
16282 do_neon_dyadic_long (void)
16284 /* FIXME: Type checking for lengthening op. */
16285 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16286 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16287 neon_mixed_length (et
, et
.size
);
16291 do_neon_abal (void)
16293 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16294 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16295 neon_mixed_length (et
, et
.size
);
16299 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16301 if (inst
.operands
[2].isscalar
)
16303 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16304 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16305 NEON_ENCODE (SCALAR
, inst
);
16306 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16310 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16311 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16312 NEON_ENCODE (INTEGER
, inst
);
16313 neon_mixed_length (et
, et
.size
);
16318 do_neon_mac_maybe_scalar_long (void)
16320 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16323 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16324 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16327 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16329 unsigned regno
= NEON_SCALAR_REG (scalar
);
16330 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16334 if (regno
> 7 || elno
> 3)
16337 return ((regno
& 0x7)
16338 | ((elno
& 0x1) << 3)
16339 | (((elno
>> 1) & 0x1) << 5));
16343 if (regno
> 15 || elno
> 1)
16346 return (((regno
& 0x1) << 5)
16347 | ((regno
>> 1) & 0x7)
16348 | ((elno
& 0x1) << 3));
16352 first_error (_("scalar out of range for multiply instruction"));
16357 do_neon_fmac_maybe_scalar_long (int subtype
)
16359 enum neon_shape rs
;
16361 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16362 field (bits[21:20]) has different meaning. For scalar index variant, it's
16363 used to differentiate add and subtract, otherwise it's with fixed value
16367 if (inst
.cond
!= COND_ALWAYS
)
16368 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16369 "behaviour is UNPREDICTABLE"));
16371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16377 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16378 be a scalar index register. */
16379 if (inst
.operands
[2].isscalar
)
16381 high8
= 0xfe000000;
16384 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16388 high8
= 0xfc000000;
16391 inst
.instruction
|= (0x1 << 23);
16392 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16395 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16397 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16398 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16399 so we simply pass -1 as size. */
16400 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16401 neon_three_same (quad_p
, 0, size
);
16403 /* Undo neon_dp_fixup. Redo the high eight bits. */
16404 inst
.instruction
&= 0x00ffffff;
16405 inst
.instruction
|= high8
;
16407 #define LOW1(R) ((R) & 0x1)
16408 #define HI4(R) (((R) >> 1) & 0xf)
16409 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16410 whether the instruction is in Q form and whether Vm is a scalar indexed
16412 if (inst
.operands
[2].isscalar
)
16415 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16416 inst
.instruction
&= 0xffffffd0;
16417 inst
.instruction
|= rm
;
16421 /* Redo Rn as well. */
16422 inst
.instruction
&= 0xfff0ff7f;
16423 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16424 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16429 /* Redo Rn and Rm. */
16430 inst
.instruction
&= 0xfff0ff50;
16431 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16432 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16433 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16434 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16439 do_neon_vfmal (void)
16441 return do_neon_fmac_maybe_scalar_long (0);
16445 do_neon_vfmsl (void)
16447 return do_neon_fmac_maybe_scalar_long (1);
16451 do_neon_dyadic_wide (void)
16453 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16454 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16455 neon_mixed_length (et
, et
.size
);
16459 do_neon_dyadic_narrow (void)
16461 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16462 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16463 /* Operand sign is unimportant, and the U bit is part of the opcode,
16464 so force the operand type to integer. */
16465 et
.type
= NT_integer
;
16466 neon_mixed_length (et
, et
.size
/ 2);
16470 do_neon_mul_sat_scalar_long (void)
16472 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16476 do_neon_vmull (void)
16478 if (inst
.operands
[2].isscalar
)
16479 do_neon_mac_maybe_scalar_long ();
16482 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16483 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16485 if (et
.type
== NT_poly
)
16486 NEON_ENCODE (POLY
, inst
);
16488 NEON_ENCODE (INTEGER
, inst
);
16490 /* For polynomial encoding the U bit must be zero, and the size must
16491 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16492 obviously, as 0b10). */
16495 /* Check we're on the correct architecture. */
16496 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16498 _("Instruction form not available on this architecture.");
16503 neon_mixed_length (et
, et
.size
);
16510 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16511 struct neon_type_el et
= neon_check_type (3, rs
,
16512 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16513 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16515 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16516 _("shift out of range"));
16517 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16518 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16519 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16520 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16521 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16522 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16523 inst
.instruction
|= neon_quad (rs
) << 6;
16524 inst
.instruction
|= imm
<< 8;
16526 neon_dp_fixup (&inst
);
16532 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16533 struct neon_type_el et
= neon_check_type (2, rs
,
16534 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16535 unsigned op
= (inst
.instruction
>> 7) & 3;
16536 /* N (width of reversed regions) is encoded as part of the bitmask. We
16537 extract it here to check the elements to be reversed are smaller.
16538 Otherwise we'd get a reserved instruction. */
16539 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16540 gas_assert (elsize
!= 0);
16541 constraint (et
.size
>= elsize
,
16542 _("elements must be smaller than reversal region"));
16543 neon_two_same (neon_quad (rs
), 1, et
.size
);
16549 if (inst
.operands
[1].isscalar
)
16551 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16552 struct neon_type_el et
= neon_check_type (2, rs
,
16553 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16554 unsigned sizebits
= et
.size
>> 3;
16555 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16556 int logsize
= neon_logbits (et
.size
);
16557 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16559 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16562 NEON_ENCODE (SCALAR
, inst
);
16563 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16564 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16565 inst
.instruction
|= LOW4 (dm
);
16566 inst
.instruction
|= HI1 (dm
) << 5;
16567 inst
.instruction
|= neon_quad (rs
) << 6;
16568 inst
.instruction
|= x
<< 17;
16569 inst
.instruction
|= sizebits
<< 16;
16571 neon_dp_fixup (&inst
);
16575 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16576 struct neon_type_el et
= neon_check_type (2, rs
,
16577 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16578 /* Duplicate ARM register to lanes of vector. */
16579 NEON_ENCODE (ARMREG
, inst
);
16582 case 8: inst
.instruction
|= 0x400000; break;
16583 case 16: inst
.instruction
|= 0x000020; break;
16584 case 32: inst
.instruction
|= 0x000000; break;
16587 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16590 inst
.instruction
|= neon_quad (rs
) << 21;
16591 /* The encoding for this instruction is identical for the ARM and Thumb
16592 variants, except for the condition field. */
16593 do_vfp_cond_or_thumb ();
16597 /* VMOV has particularly many variations. It can be one of:
16598 0. VMOV<c><q> <Qd>, <Qm>
16599 1. VMOV<c><q> <Dd>, <Dm>
16600 (Register operations, which are VORR with Rm = Rn.)
16601 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16602 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16604 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16605 (ARM register to scalar.)
16606 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16607 (Two ARM registers to vector.)
16608 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16609 (Scalar to ARM register.)
16610 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16611 (Vector to two ARM registers.)
16612 8. VMOV.F32 <Sd>, <Sm>
16613 9. VMOV.F64 <Dd>, <Dm>
16614 (VFP register moves.)
16615 10. VMOV.F32 <Sd>, #imm
16616 11. VMOV.F64 <Dd>, #imm
16617 (VFP float immediate load.)
16618 12. VMOV <Rd>, <Sm>
16619 (VFP single to ARM reg.)
16620 13. VMOV <Sd>, <Rm>
16621 (ARM reg to VFP single.)
16622 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16623 (Two ARM regs to two VFP singles.)
16624 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16625 (Two VFP singles to two ARM regs.)
16627 These cases can be disambiguated using neon_select_shape, except cases 1/9
16628 and 3/11 which depend on the operand type too.
16630 All the encoded bits are hardcoded by this function.
16632 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16633 Cases 5, 7 may be used with VFPv2 and above.
16635 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16636 can specify a type where it doesn't make sense to, and is ignored). */
16641 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16642 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16643 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16644 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16645 struct neon_type_el et
;
16646 const char *ldconst
= 0;
16650 case NS_DD
: /* case 1/9. */
16651 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16652 /* It is not an error here if no type is given. */
16654 if (et
.type
== NT_float
&& et
.size
== 64)
16656 do_vfp_nsyn_opcode ("fcpyd");
16659 /* fall through. */
16661 case NS_QQ
: /* case 0/1. */
16663 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16665 /* The architecture manual I have doesn't explicitly state which
16666 value the U bit should have for register->register moves, but
16667 the equivalent VORR instruction has U = 0, so do that. */
16668 inst
.instruction
= 0x0200110;
16669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16673 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16674 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16675 inst
.instruction
|= neon_quad (rs
) << 6;
16677 neon_dp_fixup (&inst
);
16681 case NS_DI
: /* case 3/11. */
16682 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16684 if (et
.type
== NT_float
&& et
.size
== 64)
16686 /* case 11 (fconstd). */
16687 ldconst
= "fconstd";
16688 goto encode_fconstd
;
16690 /* fall through. */
16692 case NS_QI
: /* case 2/3. */
16693 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16695 inst
.instruction
= 0x0800010;
16696 neon_move_immediate ();
16697 neon_dp_fixup (&inst
);
16700 case NS_SR
: /* case 4. */
16702 unsigned bcdebits
= 0;
16704 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16705 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16707 /* .<size> is optional here, defaulting to .32. */
16708 if (inst
.vectype
.elems
== 0
16709 && inst
.operands
[0].vectype
.type
== NT_invtype
16710 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16712 inst
.vectype
.el
[0].type
= NT_untyped
;
16713 inst
.vectype
.el
[0].size
= 32;
16714 inst
.vectype
.elems
= 1;
16717 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16718 logsize
= neon_logbits (et
.size
);
16720 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16723 && et
.size
!= 32, _(BAD_FPU
));
16724 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16725 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16729 case 8: bcdebits
= 0x8; break;
16730 case 16: bcdebits
= 0x1; break;
16731 case 32: bcdebits
= 0x0; break;
16735 bcdebits
|= x
<< logsize
;
16737 inst
.instruction
= 0xe000b10;
16738 do_vfp_cond_or_thumb ();
16739 inst
.instruction
|= LOW4 (dn
) << 16;
16740 inst
.instruction
|= HI1 (dn
) << 7;
16741 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16742 inst
.instruction
|= (bcdebits
& 3) << 5;
16743 inst
.instruction
|= (bcdebits
>> 2) << 21;
16747 case NS_DRR
: /* case 5 (fmdrr). */
16748 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16751 inst
.instruction
= 0xc400b10;
16752 do_vfp_cond_or_thumb ();
16753 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16754 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16755 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16756 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16759 case NS_RS
: /* case 6. */
16762 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16763 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16764 unsigned abcdebits
= 0;
16766 /* .<dt> is optional here, defaulting to .32. */
16767 if (inst
.vectype
.elems
== 0
16768 && inst
.operands
[0].vectype
.type
== NT_invtype
16769 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16771 inst
.vectype
.el
[0].type
= NT_untyped
;
16772 inst
.vectype
.el
[0].size
= 32;
16773 inst
.vectype
.elems
= 1;
16776 et
= neon_check_type (2, NS_NULL
,
16777 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16778 logsize
= neon_logbits (et
.size
);
16780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16782 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16783 && et
.size
!= 32, _(BAD_FPU
));
16784 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16785 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16789 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16790 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16791 case 32: abcdebits
= 0x00; break;
16795 abcdebits
|= x
<< logsize
;
16796 inst
.instruction
= 0xe100b10;
16797 do_vfp_cond_or_thumb ();
16798 inst
.instruction
|= LOW4 (dn
) << 16;
16799 inst
.instruction
|= HI1 (dn
) << 7;
16800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16801 inst
.instruction
|= (abcdebits
& 3) << 5;
16802 inst
.instruction
|= (abcdebits
>> 2) << 21;
16806 case NS_RRD
: /* case 7 (fmrrd). */
16807 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16810 inst
.instruction
= 0xc500b10;
16811 do_vfp_cond_or_thumb ();
16812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16813 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16814 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16815 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16818 case NS_FF
: /* case 8 (fcpys). */
16819 do_vfp_nsyn_opcode ("fcpys");
16823 case NS_FI
: /* case 10 (fconsts). */
16824 ldconst
= "fconsts";
16826 if (!inst
.operands
[1].immisfloat
)
16829 /* Immediate has to fit in 8 bits so float is enough. */
16830 float imm
= (float) inst
.operands
[1].imm
;
16831 memcpy (&new_imm
, &imm
, sizeof (float));
16832 /* But the assembly may have been written to provide an integer
16833 bit pattern that equates to a float, so check that the
16834 conversion has worked. */
16835 if (is_quarter_float (new_imm
))
16837 if (is_quarter_float (inst
.operands
[1].imm
))
16838 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16840 inst
.operands
[1].imm
= new_imm
;
16841 inst
.operands
[1].immisfloat
= 1;
16845 if (is_quarter_float (inst
.operands
[1].imm
))
16847 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16848 do_vfp_nsyn_opcode (ldconst
);
16850 /* ARMv8.2 fp16 vmov.f16 instruction. */
16852 do_scalar_fp16_v82_encode ();
16855 first_error (_("immediate out of range"));
16859 case NS_RF
: /* case 12 (fmrs). */
16860 do_vfp_nsyn_opcode ("fmrs");
16861 /* ARMv8.2 fp16 vmov.f16 instruction. */
16863 do_scalar_fp16_v82_encode ();
16867 case NS_FR
: /* case 13 (fmsr). */
16868 do_vfp_nsyn_opcode ("fmsr");
16869 /* ARMv8.2 fp16 vmov.f16 instruction. */
16871 do_scalar_fp16_v82_encode ();
16874 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16875 (one of which is a list), but we have parsed four. Do some fiddling to
16876 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16878 case NS_RRFF
: /* case 14 (fmrrs). */
16879 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16880 _("VFP registers must be adjacent"));
16881 inst
.operands
[2].imm
= 2;
16882 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16883 do_vfp_nsyn_opcode ("fmrrs");
16886 case NS_FFRR
: /* case 15 (fmsrr). */
16887 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16888 _("VFP registers must be adjacent"));
16889 inst
.operands
[1] = inst
.operands
[2];
16890 inst
.operands
[2] = inst
.operands
[3];
16891 inst
.operands
[0].imm
= 2;
16892 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16893 do_vfp_nsyn_opcode ("fmsrr");
16897 /* neon_select_shape has determined that the instruction
16898 shape is wrong and has already set the error message. */
16907 do_neon_rshift_round_imm (void)
16909 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16910 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16911 int imm
= inst
.operands
[2].imm
;
16913 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16916 inst
.operands
[2].present
= 0;
16921 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16922 _("immediate out of range for shift"));
16923 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16928 do_neon_movhf (void)
16930 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16931 constraint (rs
!= NS_HH
, _("invalid suffix"));
16933 if (inst
.cond
!= COND_ALWAYS
)
16937 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16938 " the behaviour is UNPREDICTABLE"));
16942 inst
.error
= BAD_COND
;
16947 do_vfp_sp_monadic ();
16950 inst
.instruction
|= 0xf0000000;
16954 do_neon_movl (void)
16956 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16957 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16958 unsigned sizebits
= et
.size
>> 3;
16959 inst
.instruction
|= sizebits
<< 19;
16960 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16966 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16967 struct neon_type_el et
= neon_check_type (2, rs
,
16968 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16969 NEON_ENCODE (INTEGER
, inst
);
16970 neon_two_same (neon_quad (rs
), 1, et
.size
);
16974 do_neon_zip_uzp (void)
16976 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16977 struct neon_type_el et
= neon_check_type (2, rs
,
16978 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16979 if (rs
== NS_DD
&& et
.size
== 32)
16981 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16982 inst
.instruction
= N_MNEM_vtrn
;
16986 neon_two_same (neon_quad (rs
), 1, et
.size
);
16990 do_neon_sat_abs_neg (void)
16992 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16993 struct neon_type_el et
= neon_check_type (2, rs
,
16994 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16995 neon_two_same (neon_quad (rs
), 1, et
.size
);
16999 do_neon_pair_long (void)
17001 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17002 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17003 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
17004 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
17005 neon_two_same (neon_quad (rs
), 1, et
.size
);
17009 do_neon_recip_est (void)
17011 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17012 struct neon_type_el et
= neon_check_type (2, rs
,
17013 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
17014 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17015 neon_two_same (neon_quad (rs
), 1, et
.size
);
17021 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17022 struct neon_type_el et
= neon_check_type (2, rs
,
17023 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17024 neon_two_same (neon_quad (rs
), 1, et
.size
);
17030 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17031 struct neon_type_el et
= neon_check_type (2, rs
,
17032 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
17033 neon_two_same (neon_quad (rs
), 1, et
.size
);
17039 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17040 struct neon_type_el et
= neon_check_type (2, rs
,
17041 N_EQK
| N_INT
, N_8
| N_KEY
);
17042 neon_two_same (neon_quad (rs
), 1, et
.size
);
17048 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17049 neon_two_same (neon_quad (rs
), 1, -1);
17053 do_neon_tbl_tbx (void)
17055 unsigned listlenbits
;
17056 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
17058 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
17060 first_error (_("bad list length for table lookup"));
17064 listlenbits
= inst
.operands
[1].imm
- 1;
17065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17067 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17069 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17070 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17071 inst
.instruction
|= listlenbits
<< 8;
17073 neon_dp_fixup (&inst
);
17077 do_neon_ldm_stm (void)
17079 /* P, U and L bits are part of bitmask. */
17080 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
17081 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
17083 if (inst
.operands
[1].issingle
)
17085 do_vfp_nsyn_ldm_stm (is_dbmode
);
17089 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
17090 _("writeback (!) must be used for VLDMDB and VSTMDB"));
17092 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
17093 _("register list must contain at least 1 and at most 16 "
17096 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
17097 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17098 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17099 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17101 inst
.instruction
|= offsetbits
;
17103 do_vfp_cond_or_thumb ();
17107 do_neon_ldr_str (void)
17109 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17111 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17112 And is UNPREDICTABLE in thumb mode. */
17114 && inst
.operands
[1].reg
== REG_PC
17115 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17118 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17119 else if (warn_on_deprecated
)
17120 as_tsktsk (_("Use of PC here is deprecated"));
17123 if (inst
.operands
[0].issingle
)
17126 do_vfp_nsyn_opcode ("flds");
17128 do_vfp_nsyn_opcode ("fsts");
17130 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17131 if (inst
.vectype
.el
[0].size
== 16)
17132 do_scalar_fp16_v82_encode ();
17137 do_vfp_nsyn_opcode ("fldd");
17139 do_vfp_nsyn_opcode ("fstd");
17143 /* "interleave" version also handles non-interleaving register VLD1/VST1
17147 do_neon_ld_st_interleave (void)
17149 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17150 N_8
| N_16
| N_32
| N_64
);
17151 unsigned alignbits
= 0;
17153 /* The bits in this table go:
17154 0: register stride of one (0) or two (1)
17155 1,2: register list length, minus one (1, 2, 3, 4).
17156 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17157 We use -1 for invalid entries. */
17158 const int typetable
[] =
17160 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17161 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17162 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17163 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17167 if (et
.type
== NT_invtype
)
17170 if (inst
.operands
[1].immisalign
)
17171 switch (inst
.operands
[1].imm
>> 8)
17173 case 64: alignbits
= 1; break;
17175 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17176 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17177 goto bad_alignment
;
17181 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17182 goto bad_alignment
;
17187 first_error (_("bad alignment"));
17191 inst
.instruction
|= alignbits
<< 4;
17192 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17194 /* Bits [4:6] of the immediate in a list specifier encode register stride
17195 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17196 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17197 up the right value for "type" in a table based on this value and the given
17198 list style, then stick it back. */
17199 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17200 | (((inst
.instruction
>> 8) & 3) << 3);
17202 typebits
= typetable
[idx
];
17204 constraint (typebits
== -1, _("bad list type for instruction"));
17205 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17206 _("bad element type for instruction"));
17208 inst
.instruction
&= ~0xf00;
17209 inst
.instruction
|= typebits
<< 8;
17212 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17213 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17214 otherwise. The variable arguments are a list of pairs of legal (size, align)
17215 values, terminated with -1. */
17218 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17221 int result
= FAIL
, thissize
, thisalign
;
17223 if (!inst
.operands
[1].immisalign
)
17229 va_start (ap
, do_alignment
);
17233 thissize
= va_arg (ap
, int);
17234 if (thissize
== -1)
17236 thisalign
= va_arg (ap
, int);
17238 if (size
== thissize
&& align
== thisalign
)
17241 while (result
!= SUCCESS
);
17245 if (result
== SUCCESS
)
17248 first_error (_("unsupported alignment for instruction"));
17254 do_neon_ld_st_lane (void)
17256 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17257 int align_good
, do_alignment
= 0;
17258 int logsize
= neon_logbits (et
.size
);
17259 int align
= inst
.operands
[1].imm
>> 8;
17260 int n
= (inst
.instruction
>> 8) & 3;
17261 int max_el
= 64 / et
.size
;
17263 if (et
.type
== NT_invtype
)
17266 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17267 _("bad list length"));
17268 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17269 _("scalar index out of range"));
17270 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17272 _("stride of 2 unavailable when element size is 8"));
17276 case 0: /* VLD1 / VST1. */
17277 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17279 if (align_good
== FAIL
)
17283 unsigned alignbits
= 0;
17286 case 16: alignbits
= 0x1; break;
17287 case 32: alignbits
= 0x3; break;
17290 inst
.instruction
|= alignbits
<< 4;
17294 case 1: /* VLD2 / VST2. */
17295 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17296 16, 32, 32, 64, -1);
17297 if (align_good
== FAIL
)
17300 inst
.instruction
|= 1 << 4;
17303 case 2: /* VLD3 / VST3. */
17304 constraint (inst
.operands
[1].immisalign
,
17305 _("can't use alignment with this instruction"));
17308 case 3: /* VLD4 / VST4. */
17309 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17310 16, 64, 32, 64, 32, 128, -1);
17311 if (align_good
== FAIL
)
17315 unsigned alignbits
= 0;
17318 case 8: alignbits
= 0x1; break;
17319 case 16: alignbits
= 0x1; break;
17320 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17323 inst
.instruction
|= alignbits
<< 4;
17330 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17331 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17332 inst
.instruction
|= 1 << (4 + logsize
);
17334 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17335 inst
.instruction
|= logsize
<< 10;
17338 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17341 do_neon_ld_dup (void)
17343 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17344 int align_good
, do_alignment
= 0;
17346 if (et
.type
== NT_invtype
)
17349 switch ((inst
.instruction
>> 8) & 3)
17351 case 0: /* VLD1. */
17352 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17353 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17354 &do_alignment
, 16, 16, 32, 32, -1);
17355 if (align_good
== FAIL
)
17357 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17360 case 2: inst
.instruction
|= 1 << 5; break;
17361 default: first_error (_("bad list length")); return;
17363 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17366 case 1: /* VLD2. */
17367 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17368 &do_alignment
, 8, 16, 16, 32, 32, 64,
17370 if (align_good
== FAIL
)
17372 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17373 _("bad list length"));
17374 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17375 inst
.instruction
|= 1 << 5;
17376 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17379 case 2: /* VLD3. */
17380 constraint (inst
.operands
[1].immisalign
,
17381 _("can't use alignment with this instruction"));
17382 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17383 _("bad list length"));
17384 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17385 inst
.instruction
|= 1 << 5;
17386 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17389 case 3: /* VLD4. */
17391 int align
= inst
.operands
[1].imm
>> 8;
17392 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17393 16, 64, 32, 64, 32, 128, -1);
17394 if (align_good
== FAIL
)
17396 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17397 _("bad list length"));
17398 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17399 inst
.instruction
|= 1 << 5;
17400 if (et
.size
== 32 && align
== 128)
17401 inst
.instruction
|= 0x3 << 6;
17403 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17410 inst
.instruction
|= do_alignment
<< 4;
17413 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17414 apart from bits [11:4]. */
17417 do_neon_ldx_stx (void)
17419 if (inst
.operands
[1].isreg
)
17420 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17422 switch (NEON_LANE (inst
.operands
[0].imm
))
17424 case NEON_INTERLEAVE_LANES
:
17425 NEON_ENCODE (INTERLV
, inst
);
17426 do_neon_ld_st_interleave ();
17429 case NEON_ALL_LANES
:
17430 NEON_ENCODE (DUP
, inst
);
17431 if (inst
.instruction
== N_INV
)
17433 first_error ("only loads support such operands");
17440 NEON_ENCODE (LANE
, inst
);
17441 do_neon_ld_st_lane ();
17444 /* L bit comes from bit mask. */
17445 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17446 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17447 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17449 if (inst
.operands
[1].postind
)
17451 int postreg
= inst
.operands
[1].imm
& 0xf;
17452 constraint (!inst
.operands
[1].immisreg
,
17453 _("post-index must be a register"));
17454 constraint (postreg
== 0xd || postreg
== 0xf,
17455 _("bad register for post-index"));
17456 inst
.instruction
|= postreg
;
17460 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17461 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
17462 || inst
.relocs
[0].exp
.X_add_number
!= 0,
17465 if (inst
.operands
[1].writeback
)
17467 inst
.instruction
|= 0xd;
17470 inst
.instruction
|= 0xf;
17474 inst
.instruction
|= 0xf9000000;
17476 inst
.instruction
|= 0xf4000000;
17481 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17483 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17484 D register operands. */
17485 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17489 NEON_ENCODE (FPV8
, inst
);
17491 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17493 do_vfp_sp_dyadic ();
17495 /* ARMv8.2 fp16 instruction. */
17497 do_scalar_fp16_v82_encode ();
17500 do_vfp_dp_rd_rn_rm ();
17503 inst
.instruction
|= 0x100;
17505 inst
.instruction
|= 0xf0000000;
17511 set_it_insn_type (OUTSIDE_IT_INSN
);
17513 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17514 first_error (_("invalid instruction shape"));
17520 set_it_insn_type (OUTSIDE_IT_INSN
);
17522 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17525 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17528 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17532 do_vrint_1 (enum neon_cvt_mode mode
)
17534 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17535 struct neon_type_el et
;
17540 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17541 D register operands. */
17542 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17546 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17548 if (et
.type
!= NT_invtype
)
17550 /* VFP encodings. */
17551 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17552 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17553 set_it_insn_type (OUTSIDE_IT_INSN
);
17555 NEON_ENCODE (FPV8
, inst
);
17556 if (rs
== NS_FF
|| rs
== NS_HH
)
17557 do_vfp_sp_monadic ();
17559 do_vfp_dp_rd_rm ();
17563 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17564 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17565 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17566 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17567 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17568 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17569 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17573 inst
.instruction
|= (rs
== NS_DD
) << 8;
17574 do_vfp_cond_or_thumb ();
17576 /* ARMv8.2 fp16 vrint instruction. */
17578 do_scalar_fp16_v82_encode ();
17582 /* Neon encodings (or something broken...). */
17584 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17586 if (et
.type
== NT_invtype
)
17589 set_it_insn_type (OUTSIDE_IT_INSN
);
17590 NEON_ENCODE (FLOAT
, inst
);
17592 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17595 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17596 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17597 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17598 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17599 inst
.instruction
|= neon_quad (rs
) << 6;
17600 /* Mask off the original size bits and reencode them. */
17601 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17602 | neon_logbits (et
.size
) << 18);
17606 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17607 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17608 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17609 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17610 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17611 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17612 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17617 inst
.instruction
|= 0xfc000000;
17619 inst
.instruction
|= 0xf0000000;
17626 do_vrint_1 (neon_cvt_mode_x
);
17632 do_vrint_1 (neon_cvt_mode_z
);
17638 do_vrint_1 (neon_cvt_mode_r
);
17644 do_vrint_1 (neon_cvt_mode_a
);
17650 do_vrint_1 (neon_cvt_mode_n
);
17656 do_vrint_1 (neon_cvt_mode_p
);
17662 do_vrint_1 (neon_cvt_mode_m
);
17666 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17668 unsigned regno
= NEON_SCALAR_REG (opnd
);
17669 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17671 if (elsize
== 16 && elno
< 2 && regno
< 16)
17672 return regno
| (elno
<< 4);
17673 else if (elsize
== 32 && elno
== 0)
17676 first_error (_("scalar out of range"));
17683 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17685 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17686 _("expression too complex"));
17687 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17688 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17689 _("immediate out of range"));
17691 if (inst
.operands
[2].isscalar
)
17693 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17694 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17695 N_KEY
| N_F16
| N_F32
).size
;
17696 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17698 inst
.instruction
= 0xfe000800;
17699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17700 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17701 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17702 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17703 inst
.instruction
|= LOW4 (m
);
17704 inst
.instruction
|= HI1 (m
) << 5;
17705 inst
.instruction
|= neon_quad (rs
) << 6;
17706 inst
.instruction
|= rot
<< 20;
17707 inst
.instruction
|= (size
== 32) << 23;
17711 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17712 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17713 N_KEY
| N_F16
| N_F32
).size
;
17714 neon_three_same (neon_quad (rs
), 0, -1);
17715 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17716 inst
.instruction
|= 0xfc200800;
17717 inst
.instruction
|= rot
<< 23;
17718 inst
.instruction
|= (size
== 32) << 20;
17725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17727 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
17728 _("expression too complex"));
17729 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17730 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17731 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17732 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17733 N_KEY
| N_F16
| N_F32
).size
;
17734 neon_three_same (neon_quad (rs
), 0, -1);
17735 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17736 inst
.instruction
|= 0xfc800800;
17737 inst
.instruction
|= (rot
== 270) << 24;
17738 inst
.instruction
|= (size
== 32) << 20;
17741 /* Dot Product instructions encoding support. */
17744 do_neon_dotproduct (int unsigned_p
)
17746 enum neon_shape rs
;
17747 unsigned scalar_oprd2
= 0;
17750 if (inst
.cond
!= COND_ALWAYS
)
17751 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17752 "is UNPREDICTABLE"));
17754 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17757 /* Dot Product instructions are in three-same D/Q register format or the third
17758 operand can be a scalar index register. */
17759 if (inst
.operands
[2].isscalar
)
17761 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17762 high8
= 0xfe000000;
17763 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17767 high8
= 0xfc000000;
17768 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17772 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17774 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17776 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17777 Product instruction, so we pass 0 as the "ubit" parameter. And the
17778 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17779 neon_three_same (neon_quad (rs
), 0, 32);
17781 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17782 different NEON three-same encoding. */
17783 inst
.instruction
&= 0x00ffffff;
17784 inst
.instruction
|= high8
;
17785 /* Encode 'U' bit which indicates signedness. */
17786 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17787 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17788 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17789 the instruction encoding. */
17790 if (inst
.operands
[2].isscalar
)
17792 inst
.instruction
&= 0xffffffd0;
17793 inst
.instruction
|= LOW4 (scalar_oprd2
);
17794 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17798 /* Dot Product instructions for signed integer. */
17801 do_neon_dotproduct_s (void)
17803 return do_neon_dotproduct (0);
17806 /* Dot Product instructions for unsigned integer. */
17809 do_neon_dotproduct_u (void)
17811 return do_neon_dotproduct (1);
17814 /* Crypto v1 instructions. */
17816 do_crypto_2op_1 (unsigned elttype
, int op
)
17818 set_it_insn_type (OUTSIDE_IT_INSN
);
17820 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17826 NEON_ENCODE (INTEGER
, inst
);
17827 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17828 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17829 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17830 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17832 inst
.instruction
|= op
<< 6;
17835 inst
.instruction
|= 0xfc000000;
17837 inst
.instruction
|= 0xf0000000;
17841 do_crypto_3op_1 (int u
, int op
)
17843 set_it_insn_type (OUTSIDE_IT_INSN
);
17845 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17846 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17851 NEON_ENCODE (INTEGER
, inst
);
17852 neon_three_same (1, u
, 8 << op
);
17858 do_crypto_2op_1 (N_8
, 0);
17864 do_crypto_2op_1 (N_8
, 1);
17870 do_crypto_2op_1 (N_8
, 2);
17876 do_crypto_2op_1 (N_8
, 3);
17882 do_crypto_3op_1 (0, 0);
17888 do_crypto_3op_1 (0, 1);
17894 do_crypto_3op_1 (0, 2);
17900 do_crypto_3op_1 (0, 3);
17906 do_crypto_3op_1 (1, 0);
17912 do_crypto_3op_1 (1, 1);
17916 do_sha256su1 (void)
17918 do_crypto_3op_1 (1, 2);
17924 do_crypto_2op_1 (N_32
, -1);
17930 do_crypto_2op_1 (N_32
, 0);
17934 do_sha256su0 (void)
17936 do_crypto_2op_1 (N_32
, 1);
17940 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17942 unsigned int Rd
= inst
.operands
[0].reg
;
17943 unsigned int Rn
= inst
.operands
[1].reg
;
17944 unsigned int Rm
= inst
.operands
[2].reg
;
17946 set_it_insn_type (OUTSIDE_IT_INSN
);
17947 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17948 inst
.instruction
|= LOW4 (Rn
) << 16;
17949 inst
.instruction
|= LOW4 (Rm
);
17950 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17951 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17953 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17954 as_warn (UNPRED_REG ("r15"));
17996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17998 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17999 do_vfp_sp_dp_cvt ();
18000 do_vfp_cond_or_thumb ();
18004 /* Overall per-instruction processing. */
18006 /* We need to be able to fix up arbitrary expressions in some statements.
18007 This is so that we can handle symbols that are an arbitrary distance from
18008 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
18009 which returns part of an address in a form which will be valid for
18010 a data instruction. We do this by pushing the expression into a symbol
18011 in the expr_section, and creating a fix for that. */
18014 fix_new_arm (fragS
* frag
,
18028 /* Create an absolute valued symbol, so we have something to
18029 refer to in the object file. Unfortunately for us, gas's
18030 generic expression parsing will already have folded out
18031 any use of .set foo/.type foo %function that may have
18032 been used to set type information of the target location,
18033 that's being specified symbolically. We have to presume
18034 the user knows what they are doing. */
18038 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
18040 symbol
= symbol_find_or_make (name
);
18041 S_SET_SEGMENT (symbol
, absolute_section
);
18042 symbol_set_frag (symbol
, &zero_address_frag
);
18043 S_SET_VALUE (symbol
, exp
->X_add_number
);
18044 exp
->X_op
= O_symbol
;
18045 exp
->X_add_symbol
= symbol
;
18046 exp
->X_add_number
= 0;
18052 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
18053 (enum bfd_reloc_code_real
) reloc
);
18057 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
18058 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
18062 /* Mark whether the fix is to a THUMB instruction, or an ARM
18064 new_fix
->tc_fix_data
= thumb_mode
;
18067 /* Create a frg for an instruction requiring relaxation. */
18069 output_relax_insn (void)
18075 /* The size of the instruction is unknown, so tie the debug info to the
18076 start of the instruction. */
18077 dwarf2_emit_insn (0);
18079 switch (inst
.relocs
[0].exp
.X_op
)
18082 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
18083 offset
= inst
.relocs
[0].exp
.X_add_number
;
18087 offset
= inst
.relocs
[0].exp
.X_add_number
;
18090 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
18094 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
18095 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
18096 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
18099 /* Write a 32-bit thumb instruction to buf. */
18101 put_thumb32_insn (char * buf
, unsigned long insn
)
18103 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18104 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18108 output_inst (const char * str
)
18114 as_bad ("%s -- `%s'", inst
.error
, str
);
18119 output_relax_insn ();
18122 if (inst
.size
== 0)
18125 to
= frag_more (inst
.size
);
18126 /* PR 9814: Record the thumb mode into the current frag so that we know
18127 what type of NOP padding to use, if necessary. We override any previous
18128 setting so that if the mode has changed then the NOPS that we use will
18129 match the encoding of the last instruction in the frag. */
18130 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18132 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18134 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18135 put_thumb32_insn (to
, inst
.instruction
);
18137 else if (inst
.size
> INSN_SIZE
)
18139 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18140 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18141 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18144 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18147 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18149 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
18150 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18151 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
18152 inst
.relocs
[r
].type
);
18155 dwarf2_emit_insn (inst
.size
);
18159 output_it_inst (int cond
, int mask
, char * to
)
18161 unsigned long instruction
= 0xbf00;
18164 instruction
|= mask
;
18165 instruction
|= cond
<< 4;
18169 to
= frag_more (2);
18171 dwarf2_emit_insn (2);
18175 md_number_to_chars (to
, instruction
, 2);
18180 /* Tag values used in struct asm_opcode's tag field. */
18183 OT_unconditional
, /* Instruction cannot be conditionalized.
18184 The ARM condition field is still 0xE. */
18185 OT_unconditionalF
, /* Instruction cannot be conditionalized
18186 and carries 0xF in its ARM condition field. */
18187 OT_csuffix
, /* Instruction takes a conditional suffix. */
18188 OT_csuffixF
, /* Some forms of the instruction take a conditional
18189 suffix, others place 0xF where the condition field
18191 OT_cinfix3
, /* Instruction takes a conditional infix,
18192 beginning at character index 3. (In
18193 unified mode, it becomes a suffix.) */
18194 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18195 tsts, cmps, cmns, and teqs. */
18196 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18197 character index 3, even in unified mode. Used for
18198 legacy instructions where suffix and infix forms
18199 may be ambiguous. */
18200 OT_csuf_or_in3
, /* Instruction takes either a conditional
18201 suffix or an infix at character index 3. */
18202 OT_odd_infix_unc
, /* This is the unconditional variant of an
18203 instruction that takes a conditional infix
18204 at an unusual position. In unified mode,
18205 this variant will accept a suffix. */
18206 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18207 are the conditional variants of instructions that
18208 take conditional infixes in unusual positions.
18209 The infix appears at character index
18210 (tag - OT_odd_infix_0). These are not accepted
18211 in unified mode. */
18214 /* Subroutine of md_assemble, responsible for looking up the primary
18215 opcode from the mnemonic the user wrote. STR points to the
18216 beginning of the mnemonic.
18218 This is not simply a hash table lookup, because of conditional
18219 variants. Most instructions have conditional variants, which are
18220 expressed with a _conditional affix_ to the mnemonic. If we were
18221 to encode each conditional variant as a literal string in the opcode
18222 table, it would have approximately 20,000 entries.
18224 Most mnemonics take this affix as a suffix, and in unified syntax,
18225 'most' is upgraded to 'all'. However, in the divided syntax, some
18226 instructions take the affix as an infix, notably the s-variants of
18227 the arithmetic instructions. Of those instructions, all but six
18228 have the infix appear after the third character of the mnemonic.
18230 Accordingly, the algorithm for looking up primary opcodes given
18233 1. Look up the identifier in the opcode table.
18234 If we find a match, go to step U.
18236 2. Look up the last two characters of the identifier in the
18237 conditions table. If we find a match, look up the first N-2
18238 characters of the identifier in the opcode table. If we
18239 find a match, go to step CE.
18241 3. Look up the fourth and fifth characters of the identifier in
18242 the conditions table. If we find a match, extract those
18243 characters from the identifier, and look up the remaining
18244 characters in the opcode table. If we find a match, go
18249 U. Examine the tag field of the opcode structure, in case this is
18250 one of the six instructions with its conditional infix in an
18251 unusual place. If it is, the tag tells us where to find the
18252 infix; look it up in the conditions table and set inst.cond
18253 accordingly. Otherwise, this is an unconditional instruction.
18254 Again set inst.cond accordingly. Return the opcode structure.
18256 CE. Examine the tag field to make sure this is an instruction that
18257 should receive a conditional suffix. If it is not, fail.
18258 Otherwise, set inst.cond from the suffix we already looked up,
18259 and return the opcode structure.
18261 CM. Examine the tag field to make sure this is an instruction that
18262 should receive a conditional infix after the third character.
18263 If it is not, fail. Otherwise, undo the edits to the current
18264 line of input and proceed as for case CE. */
18266 static const struct asm_opcode
*
18267 opcode_lookup (char **str
)
18271 const struct asm_opcode
*opcode
;
18272 const struct asm_cond
*cond
;
18275 /* Scan up to the end of the mnemonic, which must end in white space,
18276 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18277 for (base
= end
= *str
; *end
!= '\0'; end
++)
18278 if (*end
== ' ' || *end
== '.')
18284 /* Handle a possible width suffix and/or Neon type suffix. */
18289 /* The .w and .n suffixes are only valid if the unified syntax is in
18291 if (unified_syntax
&& end
[1] == 'w')
18293 else if (unified_syntax
&& end
[1] == 'n')
18298 inst
.vectype
.elems
= 0;
18300 *str
= end
+ offset
;
18302 if (end
[offset
] == '.')
18304 /* See if we have a Neon type suffix (possible in either unified or
18305 non-unified ARM syntax mode). */
18306 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18309 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18315 /* Look for unaffixed or special-case affixed mnemonic. */
18316 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18321 if (opcode
->tag
< OT_odd_infix_0
)
18323 inst
.cond
= COND_ALWAYS
;
18327 if (warn_on_deprecated
&& unified_syntax
)
18328 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18329 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18330 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18333 inst
.cond
= cond
->value
;
18337 /* Cannot have a conditional suffix on a mnemonic of less than two
18339 if (end
- base
< 3)
18342 /* Look for suffixed mnemonic. */
18344 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18345 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18347 if (opcode
&& cond
)
18350 switch (opcode
->tag
)
18352 case OT_cinfix3_legacy
:
18353 /* Ignore conditional suffixes matched on infix only mnemonics. */
18357 case OT_cinfix3_deprecated
:
18358 case OT_odd_infix_unc
:
18359 if (!unified_syntax
)
18361 /* Fall through. */
18365 case OT_csuf_or_in3
:
18366 inst
.cond
= cond
->value
;
18369 case OT_unconditional
:
18370 case OT_unconditionalF
:
18372 inst
.cond
= cond
->value
;
18375 /* Delayed diagnostic. */
18376 inst
.error
= BAD_COND
;
18377 inst
.cond
= COND_ALWAYS
;
18386 /* Cannot have a usual-position infix on a mnemonic of less than
18387 six characters (five would be a suffix). */
18388 if (end
- base
< 6)
18391 /* Look for infixed mnemonic in the usual position. */
18393 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18397 memcpy (save
, affix
, 2);
18398 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18399 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18401 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18402 memcpy (affix
, save
, 2);
18405 && (opcode
->tag
== OT_cinfix3
18406 || opcode
->tag
== OT_cinfix3_deprecated
18407 || opcode
->tag
== OT_csuf_or_in3
18408 || opcode
->tag
== OT_cinfix3_legacy
))
18411 if (warn_on_deprecated
&& unified_syntax
18412 && (opcode
->tag
== OT_cinfix3
18413 || opcode
->tag
== OT_cinfix3_deprecated
))
18414 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18416 inst
.cond
= cond
->value
;
18423 /* This function generates an initial IT instruction, leaving its block
18424 virtually open for the new instructions. Eventually,
18425 the mask will be updated by now_it_add_mask () each time
18426 a new instruction needs to be included in the IT block.
18427 Finally, the block is closed with close_automatic_it_block ().
18428 The block closure can be requested either from md_assemble (),
18429 a tencode (), or due to a label hook. */
18432 new_automatic_it_block (int cond
)
18434 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18435 now_it
.mask
= 0x18;
18437 now_it
.block_length
= 1;
18438 mapping_state (MAP_THUMB
);
18439 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18440 now_it
.warn_deprecated
= FALSE
;
18441 now_it
.insn_cond
= TRUE
;
18444 /* Close an automatic IT block.
18445 See comments in new_automatic_it_block (). */
18448 close_automatic_it_block (void)
18450 now_it
.mask
= 0x10;
18451 now_it
.block_length
= 0;
18454 /* Update the mask of the current automatically-generated IT
18455 instruction. See comments in new_automatic_it_block (). */
18458 now_it_add_mask (int cond
)
18460 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18461 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18462 | ((bitvalue) << (nbit)))
18463 const int resulting_bit
= (cond
& 1);
18465 now_it
.mask
&= 0xf;
18466 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18468 (5 - now_it
.block_length
));
18469 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18471 ((5 - now_it
.block_length
) - 1) );
18472 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18475 #undef SET_BIT_VALUE
18478 /* The IT blocks handling machinery is accessed through the these functions:
18479 it_fsm_pre_encode () from md_assemble ()
18480 set_it_insn_type () optional, from the tencode functions
18481 set_it_insn_type_last () ditto
18482 in_it_block () ditto
18483 it_fsm_post_encode () from md_assemble ()
18484 force_automatic_it_block_close () from label handling functions
18487 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18488 initializing the IT insn type with a generic initial value depending
18489 on the inst.condition.
18490 2) During the tencode function, two things may happen:
18491 a) The tencode function overrides the IT insn type by
18492 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18493 b) The tencode function queries the IT block state by
18494 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18496 Both set_it_insn_type and in_it_block run the internal FSM state
18497 handling function (handle_it_state), because: a) setting the IT insn
18498 type may incur in an invalid state (exiting the function),
18499 and b) querying the state requires the FSM to be updated.
18500 Specifically we want to avoid creating an IT block for conditional
18501 branches, so it_fsm_pre_encode is actually a guess and we can't
18502 determine whether an IT block is required until the tencode () routine
18503 has decided what type of instruction this actually it.
18504 Because of this, if set_it_insn_type and in_it_block have to be used,
18505 set_it_insn_type has to be called first.
18507 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18508 determines the insn IT type depending on the inst.cond code.
18509 When a tencode () routine encodes an instruction that can be
18510 either outside an IT block, or, in the case of being inside, has to be
18511 the last one, set_it_insn_type_last () will determine the proper
18512 IT instruction type based on the inst.cond code. Otherwise,
18513 set_it_insn_type can be called for overriding that logic or
18514 for covering other cases.
18516 Calling handle_it_state () may not transition the IT block state to
18517 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18518 still queried. Instead, if the FSM determines that the state should
18519 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18520 after the tencode () function: that's what it_fsm_post_encode () does.
18522 Since in_it_block () calls the state handling function to get an
18523 updated state, an error may occur (due to invalid insns combination).
18524 In that case, inst.error is set.
18525 Therefore, inst.error has to be checked after the execution of
18526 the tencode () routine.
18528 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18529 any pending state change (if any) that didn't take place in
18530 handle_it_state () as explained above. */
18533 it_fsm_pre_encode (void)
18535 if (inst
.cond
!= COND_ALWAYS
)
18536 inst
.it_insn_type
= INSIDE_IT_INSN
;
18538 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18540 now_it
.state_handled
= 0;
18543 /* IT state FSM handling function. */
18546 handle_it_state (void)
18548 now_it
.state_handled
= 1;
18549 now_it
.insn_cond
= FALSE
;
18551 switch (now_it
.state
)
18553 case OUTSIDE_IT_BLOCK
:
18554 switch (inst
.it_insn_type
)
18556 case OUTSIDE_IT_INSN
:
18559 case INSIDE_IT_INSN
:
18560 case INSIDE_IT_LAST_INSN
:
18561 if (thumb_mode
== 0)
18564 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18565 as_tsktsk (_("Warning: conditional outside an IT block"\
18570 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18571 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18573 /* Automatically generate the IT instruction. */
18574 new_automatic_it_block (inst
.cond
);
18575 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18576 close_automatic_it_block ();
18580 inst
.error
= BAD_OUT_IT
;
18586 case IF_INSIDE_IT_LAST_INSN
:
18587 case NEUTRAL_IT_INSN
:
18591 now_it
.state
= MANUAL_IT_BLOCK
;
18592 now_it
.block_length
= 0;
18597 case AUTOMATIC_IT_BLOCK
:
18598 /* Three things may happen now:
18599 a) We should increment current it block size;
18600 b) We should close current it block (closing insn or 4 insns);
18601 c) We should close current it block and start a new one (due
18602 to incompatible conditions or
18603 4 insns-length block reached). */
18605 switch (inst
.it_insn_type
)
18607 case OUTSIDE_IT_INSN
:
18608 /* The closure of the block shall happen immediately,
18609 so any in_it_block () call reports the block as closed. */
18610 force_automatic_it_block_close ();
18613 case INSIDE_IT_INSN
:
18614 case INSIDE_IT_LAST_INSN
:
18615 case IF_INSIDE_IT_LAST_INSN
:
18616 now_it
.block_length
++;
18618 if (now_it
.block_length
> 4
18619 || !now_it_compatible (inst
.cond
))
18621 force_automatic_it_block_close ();
18622 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18623 new_automatic_it_block (inst
.cond
);
18627 now_it
.insn_cond
= TRUE
;
18628 now_it_add_mask (inst
.cond
);
18631 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18632 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18633 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18634 close_automatic_it_block ();
18637 case NEUTRAL_IT_INSN
:
18638 now_it
.block_length
++;
18639 now_it
.insn_cond
= TRUE
;
18641 if (now_it
.block_length
> 4)
18642 force_automatic_it_block_close ();
18644 now_it_add_mask (now_it
.cc
& 1);
18648 close_automatic_it_block ();
18649 now_it
.state
= MANUAL_IT_BLOCK
;
18654 case MANUAL_IT_BLOCK
:
18656 /* Check conditional suffixes. */
18657 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18660 now_it
.mask
&= 0x1f;
18661 is_last
= (now_it
.mask
== 0x10);
18662 now_it
.insn_cond
= TRUE
;
18664 switch (inst
.it_insn_type
)
18666 case OUTSIDE_IT_INSN
:
18667 inst
.error
= BAD_NOT_IT
;
18670 case INSIDE_IT_INSN
:
18671 if (cond
!= inst
.cond
)
18673 inst
.error
= BAD_IT_COND
;
18678 case INSIDE_IT_LAST_INSN
:
18679 case IF_INSIDE_IT_LAST_INSN
:
18680 if (cond
!= inst
.cond
)
18682 inst
.error
= BAD_IT_COND
;
18687 inst
.error
= BAD_BRANCH
;
18692 case NEUTRAL_IT_INSN
:
18693 /* The BKPT instruction is unconditional even in an IT block. */
18697 inst
.error
= BAD_IT_IT
;
18707 struct depr_insn_mask
18709 unsigned long pattern
;
18710 unsigned long mask
;
18711 const char* description
;
18714 /* List of 16-bit instruction patterns deprecated in an IT block in
18716 static const struct depr_insn_mask depr_it_insns
[] = {
18717 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18718 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18719 { 0xa000, 0xb800, N_("ADR") },
18720 { 0x4800, 0xf800, N_("Literal loads") },
18721 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18722 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18723 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18724 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18725 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18730 it_fsm_post_encode (void)
18734 if (!now_it
.state_handled
)
18735 handle_it_state ();
18737 if (now_it
.insn_cond
18738 && !now_it
.warn_deprecated
18739 && warn_on_deprecated
18740 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18741 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18743 if (inst
.instruction
>= 0x10000)
18745 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18746 "performance deprecated in ARMv8-A and ARMv8-R"));
18747 now_it
.warn_deprecated
= TRUE
;
18751 const struct depr_insn_mask
*p
= depr_it_insns
;
18753 while (p
->mask
!= 0)
18755 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18757 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18758 "instructions of the following class are "
18759 "performance deprecated in ARMv8-A and "
18760 "ARMv8-R: %s"), p
->description
);
18761 now_it
.warn_deprecated
= TRUE
;
18769 if (now_it
.block_length
> 1)
18771 as_tsktsk (_("IT blocks containing more than one conditional "
18772 "instruction are performance deprecated in ARMv8-A and "
18774 now_it
.warn_deprecated
= TRUE
;
18778 is_last
= (now_it
.mask
== 0x10);
18781 now_it
.state
= OUTSIDE_IT_BLOCK
;
18787 force_automatic_it_block_close (void)
18789 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18791 close_automatic_it_block ();
18792 now_it
.state
= OUTSIDE_IT_BLOCK
;
18800 if (!now_it
.state_handled
)
18801 handle_it_state ();
18803 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18806 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18807 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18808 here, hence the "known" in the function name. */
18811 known_t32_only_insn (const struct asm_opcode
*opcode
)
18813 /* Original Thumb-1 wide instruction. */
18814 if (opcode
->tencode
== do_t_blx
18815 || opcode
->tencode
== do_t_branch23
18816 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18817 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18820 /* Wide-only instruction added to ARMv8-M Baseline. */
18821 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18822 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18823 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18824 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18830 /* Whether wide instruction variant can be used if available for a valid OPCODE
18834 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18836 if (known_t32_only_insn (opcode
))
18839 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18840 of variant T3 of B.W is checked in do_t_branch. */
18841 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18842 && opcode
->tencode
== do_t_branch
)
18845 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18846 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18847 && opcode
->tencode
== do_t_mov_cmp
18848 /* Make sure CMP instruction is not affected. */
18849 && opcode
->aencode
== do_mov
)
18852 /* Wide instruction variants of all instructions with narrow *and* wide
18853 variants become available with ARMv6t2. Other opcodes are either
18854 narrow-only or wide-only and are thus available if OPCODE is valid. */
18855 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18858 /* OPCODE with narrow only instruction variant or wide variant not
18864 md_assemble (char *str
)
18867 const struct asm_opcode
* opcode
;
18869 /* Align the previous label if needed. */
18870 if (last_label_seen
!= NULL
)
18872 symbol_set_frag (last_label_seen
, frag_now
);
18873 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18874 S_SET_SEGMENT (last_label_seen
, now_seg
);
18877 memset (&inst
, '\0', sizeof (inst
));
18879 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18880 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
18882 opcode
= opcode_lookup (&p
);
18885 /* It wasn't an instruction, but it might be a register alias of
18886 the form alias .req reg, or a Neon .dn/.qn directive. */
18887 if (! create_register_alias (str
, p
)
18888 && ! create_neon_reg_alias (str
, p
))
18889 as_bad (_("bad instruction `%s'"), str
);
18894 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18895 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18897 /* The value which unconditional instructions should have in place of the
18898 condition field. */
18899 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18903 arm_feature_set variant
;
18905 variant
= cpu_variant
;
18906 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18907 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18908 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18909 /* Check that this instruction is supported for this CPU. */
18910 if (!opcode
->tvariant
18911 || (thumb_mode
== 1
18912 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18914 if (opcode
->tencode
== do_t_swi
)
18915 as_bad (_("SVC is not permitted on this architecture"));
18917 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18920 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18921 && opcode
->tencode
!= do_t_branch
)
18923 as_bad (_("Thumb does not support conditional execution"));
18927 /* Two things are addressed here:
18928 1) Implicit require narrow instructions on Thumb-1.
18929 This avoids relaxation accidentally introducing Thumb-2
18931 2) Reject wide instructions in non Thumb-2 cores.
18933 Only instructions with narrow and wide variants need to be handled
18934 but selecting all non wide-only instructions is easier. */
18935 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18936 && !t32_insn_ok (variant
, opcode
))
18938 if (inst
.size_req
== 0)
18940 else if (inst
.size_req
== 4)
18942 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18943 as_bad (_("selected processor does not support 32bit wide "
18944 "variant of instruction `%s'"), str
);
18946 as_bad (_("selected processor does not support `%s' in "
18947 "Thumb-2 mode"), str
);
18952 inst
.instruction
= opcode
->tvalue
;
18954 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18956 /* Prepare the it_insn_type for those encodings that don't set
18958 it_fsm_pre_encode ();
18960 opcode
->tencode ();
18962 it_fsm_post_encode ();
18965 if (!(inst
.error
|| inst
.relax
))
18967 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18968 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18969 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18971 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18976 /* Something has gone badly wrong if we try to relax a fixed size
18978 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18980 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18981 *opcode
->tvariant
);
18982 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18983 set those bits when Thumb-2 32-bit instructions are seen. The impact
18984 of relaxable instructions will be considered later after we finish all
18986 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18987 variant
= arm_arch_none
;
18989 variant
= cpu_variant
;
18990 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18991 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18994 check_neon_suffixes
;
18998 mapping_state (MAP_THUMB
);
19001 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19005 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
19006 is_bx
= (opcode
->aencode
== do_bx
);
19008 /* Check that this instruction is supported for this CPU. */
19009 if (!(is_bx
&& fix_v4bx
)
19010 && !(opcode
->avariant
&&
19011 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
19013 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
19018 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
19022 inst
.instruction
= opcode
->avalue
;
19023 if (opcode
->tag
== OT_unconditionalF
)
19024 inst
.instruction
|= 0xFU
<< 28;
19026 inst
.instruction
|= inst
.cond
<< 28;
19027 inst
.size
= INSN_SIZE
;
19028 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
19030 it_fsm_pre_encode ();
19031 opcode
->aencode ();
19032 it_fsm_post_encode ();
19034 /* Arm mode bx is marked as both v4T and v5 because it's still required
19035 on a hypothetical non-thumb v5 core. */
19037 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
19039 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
19040 *opcode
->avariant
);
19042 check_neon_suffixes
;
19046 mapping_state (MAP_ARM
);
19051 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
19059 check_it_blocks_finished (void)
19064 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
19065 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
19066 == MANUAL_IT_BLOCK
)
19068 as_warn (_("section '%s' finished with an open IT block."),
19072 if (now_it
.state
== MANUAL_IT_BLOCK
)
19073 as_warn (_("file finished with an open IT block."));
19077 /* Various frobbings of labels and their addresses. */
19080 arm_start_line_hook (void)
19082 last_label_seen
= NULL
;
19086 arm_frob_label (symbolS
* sym
)
19088 last_label_seen
= sym
;
19090 ARM_SET_THUMB (sym
, thumb_mode
);
19092 #if defined OBJ_COFF || defined OBJ_ELF
19093 ARM_SET_INTERWORK (sym
, support_interwork
);
19096 force_automatic_it_block_close ();
19098 /* Note - do not allow local symbols (.Lxxx) to be labelled
19099 as Thumb functions. This is because these labels, whilst
19100 they exist inside Thumb code, are not the entry points for
19101 possible ARM->Thumb calls. Also, these labels can be used
19102 as part of a computed goto or switch statement. eg gcc
19103 can generate code that looks like this:
19105 ldr r2, [pc, .Laaa]
19115 The first instruction loads the address of the jump table.
19116 The second instruction converts a table index into a byte offset.
19117 The third instruction gets the jump address out of the table.
19118 The fourth instruction performs the jump.
19120 If the address stored at .Laaa is that of a symbol which has the
19121 Thumb_Func bit set, then the linker will arrange for this address
19122 to have the bottom bit set, which in turn would mean that the
19123 address computation performed by the third instruction would end
19124 up with the bottom bit set. Since the ARM is capable of unaligned
19125 word loads, the instruction would then load the incorrect address
19126 out of the jump table, and chaos would ensue. */
19127 if (label_is_thumb_function_name
19128 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19129 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19131 /* When the address of a Thumb function is taken the bottom
19132 bit of that address should be set. This will allow
19133 interworking between Arm and Thumb functions to work
19136 THUMB_SET_FUNC (sym
, 1);
19138 label_is_thumb_function_name
= FALSE
;
19141 dwarf2_emit_label (sym
);
19145 arm_data_in_code (void)
19147 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19149 *input_line_pointer
= '/';
19150 input_line_pointer
+= 5;
19151 *input_line_pointer
= 0;
19159 arm_canonicalize_symbol_name (char * name
)
19163 if (thumb_mode
&& (len
= strlen (name
)) > 5
19164 && streq (name
+ len
- 5, "/data"))
19165 *(name
+ len
- 5) = 0;
19170 /* Table of all register names defined by default. The user can
19171 define additional names with .req. Note that all register names
19172 should appear in both upper and lowercase variants. Some registers
19173 also have mixed-case names. */
19175 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19176 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19177 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19178 #define REGSET(p,t) \
19179 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19180 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19181 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19182 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19183 #define REGSETH(p,t) \
19184 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19185 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19186 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19187 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19188 #define REGSET2(p,t) \
19189 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19190 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19191 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19192 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19193 #define SPLRBANK(base,bank,t) \
19194 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19195 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19196 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19197 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19198 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19199 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19201 static const struct reg_entry reg_names
[] =
19203 /* ARM integer registers. */
19204 REGSET(r
, RN
), REGSET(R
, RN
),
19206 /* ATPCS synonyms. */
19207 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19208 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19209 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19211 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19212 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19213 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19215 /* Well-known aliases. */
19216 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19217 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19219 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19220 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19222 /* Coprocessor numbers. */
19223 REGSET(p
, CP
), REGSET(P
, CP
),
19225 /* Coprocessor register numbers. The "cr" variants are for backward
19227 REGSET(c
, CN
), REGSET(C
, CN
),
19228 REGSET(cr
, CN
), REGSET(CR
, CN
),
19230 /* ARM banked registers. */
19231 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19232 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19233 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19234 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19235 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19236 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19237 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19239 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19240 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19241 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19242 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19243 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19244 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19245 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19246 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19248 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19249 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19250 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19251 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19252 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19253 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19254 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19255 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19256 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19258 /* FPA registers. */
19259 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19260 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19262 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19263 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19265 /* VFP SP registers. */
19266 REGSET(s
,VFS
), REGSET(S
,VFS
),
19267 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19269 /* VFP DP Registers. */
19270 REGSET(d
,VFD
), REGSET(D
,VFD
),
19271 /* Extra Neon DP registers. */
19272 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19274 /* Neon QP registers. */
19275 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19277 /* VFP control registers. */
19278 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19279 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19280 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19281 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19282 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19283 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19284 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19286 /* Maverick DSP coprocessor registers. */
19287 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19288 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19290 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19291 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19292 REGDEF(dspsc
,0,DSPSC
),
19294 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19295 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19296 REGDEF(DSPSC
,0,DSPSC
),
19298 /* iWMMXt data registers - p0, c0-15. */
19299 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19301 /* iWMMXt control registers - p1, c0-3. */
19302 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19303 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19304 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19305 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19307 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19308 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19309 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19310 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19311 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19313 /* XScale accumulator registers. */
19314 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19320 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19321 within psr_required_here. */
19322 static const struct asm_psr psrs
[] =
19324 /* Backward compatibility notation. Note that "all" is no longer
19325 truly all possible PSR bits. */
19326 {"all", PSR_c
| PSR_f
},
19330 /* Individual flags. */
19336 /* Combinations of flags. */
19337 {"fs", PSR_f
| PSR_s
},
19338 {"fx", PSR_f
| PSR_x
},
19339 {"fc", PSR_f
| PSR_c
},
19340 {"sf", PSR_s
| PSR_f
},
19341 {"sx", PSR_s
| PSR_x
},
19342 {"sc", PSR_s
| PSR_c
},
19343 {"xf", PSR_x
| PSR_f
},
19344 {"xs", PSR_x
| PSR_s
},
19345 {"xc", PSR_x
| PSR_c
},
19346 {"cf", PSR_c
| PSR_f
},
19347 {"cs", PSR_c
| PSR_s
},
19348 {"cx", PSR_c
| PSR_x
},
19349 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19350 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19351 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19352 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19353 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19354 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19355 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19356 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19357 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19358 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19359 {"scf", PSR_s
| PSR_c
| PSR_f
},
19360 {"scx", PSR_s
| PSR_c
| PSR_x
},
19361 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19362 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19363 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19364 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19365 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19366 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19367 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19368 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19369 {"csf", PSR_c
| PSR_s
| PSR_f
},
19370 {"csx", PSR_c
| PSR_s
| PSR_x
},
19371 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19372 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19373 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19374 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19375 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19376 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19377 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19378 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19379 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19380 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19381 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19382 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19383 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19384 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19385 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19386 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19387 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19388 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19389 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19390 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19391 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19392 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19393 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19394 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19395 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19396 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19399 /* Table of V7M psr names. */
19400 static const struct asm_psr v7m_psrs
[] =
19402 {"apsr", 0x0 }, {"APSR", 0x0 },
19403 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19404 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19405 {"psr", 0x3 }, {"PSR", 0x3 },
19406 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19407 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19408 {"epsr", 0x6 }, {"EPSR", 0x6 },
19409 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19410 {"msp", 0x8 }, {"MSP", 0x8 },
19411 {"psp", 0x9 }, {"PSP", 0x9 },
19412 {"msplim", 0xa }, {"MSPLIM", 0xa },
19413 {"psplim", 0xb }, {"PSPLIM", 0xb },
19414 {"primask", 0x10}, {"PRIMASK", 0x10},
19415 {"basepri", 0x11}, {"BASEPRI", 0x11},
19416 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19417 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19418 {"control", 0x14}, {"CONTROL", 0x14},
19419 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19420 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19421 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19422 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19423 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19424 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19425 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19426 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19427 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19430 /* Table of all shift-in-operand names. */
19431 static const struct asm_shift_name shift_names
[] =
19433 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19434 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19435 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19436 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19437 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19438 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19441 /* Table of all explicit relocation names. */
19443 static struct reloc_entry reloc_names
[] =
19445 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19446 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19447 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19448 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19449 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19450 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19451 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19452 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19453 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19454 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19455 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19456 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19457 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19458 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19459 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19460 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19461 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19462 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19463 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19464 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19465 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19466 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19467 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19468 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19469 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19470 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19471 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19475 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19476 static const struct asm_cond conds
[] =
19480 {"cs", 0x2}, {"hs", 0x2},
19481 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19495 #define UL_BARRIER(L,U,CODE,FEAT) \
19496 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19497 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19499 static struct asm_barrier_opt barrier_opt_names
[] =
19501 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19502 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19503 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19504 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19505 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19506 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19507 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19508 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19509 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19510 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19511 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19512 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19513 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19514 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19515 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19516 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19521 /* Table of ARM-format instructions. */
19523 /* Macros for gluing together operand strings. N.B. In all cases
19524 other than OPS0, the trailing OP_stop comes from default
19525 zero-initialization of the unspecified elements of the array. */
19526 #define OPS0() { OP_stop, }
19527 #define OPS1(a) { OP_##a, }
19528 #define OPS2(a,b) { OP_##a,OP_##b, }
19529 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19530 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19531 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19532 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19534 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19535 This is useful when mixing operands for ARM and THUMB, i.e. using the
19536 MIX_ARM_THUMB_OPERANDS macro.
19537 In order to use these macros, prefix the number of operands with _
19539 #define OPS_1(a) { a, }
19540 #define OPS_2(a,b) { a,b, }
19541 #define OPS_3(a,b,c) { a,b,c, }
19542 #define OPS_4(a,b,c,d) { a,b,c,d, }
19543 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19544 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19546 /* These macros abstract out the exact format of the mnemonic table and
19547 save some repeated characters. */
19549 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19550 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19551 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19552 THUMB_VARIANT, do_##ae, do_##te }
19554 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19555 a T_MNEM_xyz enumerator. */
19556 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19557 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19558 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19559 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19561 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19562 infix after the third character. */
19563 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19564 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19565 THUMB_VARIANT, do_##ae, do_##te }
19566 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19567 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19568 THUMB_VARIANT, do_##ae, do_##te }
19569 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19570 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19571 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19572 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19573 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19574 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19575 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19576 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19578 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19579 field is still 0xE. Many of the Thumb variants can be executed
19580 conditionally, so this is checked separately. */
19581 #define TUE(mnem, op, top, nops, ops, ae, te) \
19582 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19583 THUMB_VARIANT, do_##ae, do_##te }
19585 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19586 Used by mnemonics that have very minimal differences in the encoding for
19587 ARM and Thumb variants and can be handled in a common function. */
19588 #define TUEc(mnem, op, top, nops, ops, en) \
19589 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19590 THUMB_VARIANT, do_##en, do_##en }
19592 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19593 condition code field. */
19594 #define TUF(mnem, op, top, nops, ops, ae, te) \
19595 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19596 THUMB_VARIANT, do_##ae, do_##te }
19598 /* ARM-only variants of all the above. */
19599 #define CE(mnem, op, nops, ops, ae) \
19600 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19602 #define C3(mnem, op, nops, ops, ae) \
19603 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19605 /* Thumb-only variants of TCE and TUE. */
19606 #define ToC(mnem, top, nops, ops, te) \
19607 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19610 #define ToU(mnem, top, nops, ops, te) \
19611 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19614 /* T_MNEM_xyz enumerator variants of ToC. */
19615 #define toC(mnem, top, nops, ops, te) \
19616 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
19619 /* Legacy mnemonics that always have conditional infix after the third
19621 #define CL(mnem, op, nops, ops, ae) \
19622 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19623 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19625 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19626 #define cCE(mnem, op, nops, ops, ae) \
19627 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19629 /* Legacy coprocessor instructions where conditional infix and conditional
19630 suffix are ambiguous. For consistency this includes all FPA instructions,
19631 not just the potentially ambiguous ones. */
19632 #define cCL(mnem, op, nops, ops, ae) \
19633 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19634 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19636 /* Coprocessor, takes either a suffix or a position-3 infix
19637 (for an FPA corner case). */
19638 #define C3E(mnem, op, nops, ops, ae) \
19639 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19640 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19642 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19643 { m1 #m2 m3, OPS##nops ops, \
19644 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19645 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19647 #define CM(m1, m2, op, nops, ops, ae) \
19648 xCM_ (m1, , m2, op, nops, ops, ae), \
19649 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19650 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19651 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19652 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19653 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19654 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19655 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19656 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19657 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19658 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19659 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19660 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19661 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19662 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19663 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19664 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19665 xCM_ (m1, le, m2, op, nops, ops, ae), \
19666 xCM_ (m1, al, m2, op, nops, ops, ae)
19668 #define UE(mnem, op, nops, ops, ae) \
19669 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19671 #define UF(mnem, op, nops, ops, ae) \
19672 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19674 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19675 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19676 use the same encoding function for each. */
19677 #define NUF(mnem, op, nops, ops, enc) \
19678 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19679 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19681 /* Neon data processing, version which indirects through neon_enc_tab for
19682 the various overloaded versions of opcodes. */
19683 #define nUF(mnem, op, nops, ops, enc) \
19684 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19685 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19687 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19689 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19690 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19691 THUMB_VARIANT, do_##enc, do_##enc }
19693 #define NCE(mnem, op, nops, ops, enc) \
19694 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19696 #define NCEF(mnem, op, nops, ops, enc) \
19697 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19699 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19700 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19701 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19702 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19704 #define nCE(mnem, op, nops, ops, enc) \
19705 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19707 #define nCEF(mnem, op, nops, ops, enc) \
19708 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19712 static const struct asm_opcode insns
[] =
19714 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19715 #define THUMB_VARIANT & arm_ext_v4t
19716 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19717 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19718 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19719 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19720 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19721 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19722 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19723 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19724 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19725 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19726 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19727 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19728 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19729 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19730 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19731 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19733 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19734 for setting PSR flag bits. They are obsolete in V6 and do not
19735 have Thumb equivalents. */
19736 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19737 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19738 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19739 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19740 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19741 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19742 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19743 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19744 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19746 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19747 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19748 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19749 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19751 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19752 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19753 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19755 OP_ADDRGLDR
),ldst
, t_ldst
),
19756 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19758 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19759 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19760 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19761 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19762 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19763 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19765 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19766 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19769 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19770 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19771 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19772 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19774 /* Thumb-compatibility pseudo ops. */
19775 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19776 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19777 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19778 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19779 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19780 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19781 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19782 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19783 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19784 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19785 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19786 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19788 /* These may simplify to neg. */
19789 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19790 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19792 #undef THUMB_VARIANT
19793 #define THUMB_VARIANT & arm_ext_os
19795 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19796 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19798 #undef THUMB_VARIANT
19799 #define THUMB_VARIANT & arm_ext_v6
19801 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19803 /* V1 instructions with no Thumb analogue prior to V6T2. */
19804 #undef THUMB_VARIANT
19805 #define THUMB_VARIANT & arm_ext_v6t2
19807 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19808 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19809 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19811 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19812 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19813 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19814 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19816 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19817 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19819 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19820 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19822 /* V1 instructions with no Thumb analogue at all. */
19823 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19824 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19826 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19827 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19828 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19829 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19830 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19831 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19832 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19833 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19836 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19837 #undef THUMB_VARIANT
19838 #define THUMB_VARIANT & arm_ext_v4t
19840 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19841 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19843 #undef THUMB_VARIANT
19844 #define THUMB_VARIANT & arm_ext_v6t2
19846 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19847 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19849 /* Generic coprocessor instructions. */
19850 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19851 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19852 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19853 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19854 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19855 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19856 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19859 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19861 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19862 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19865 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19866 #undef THUMB_VARIANT
19867 #define THUMB_VARIANT & arm_ext_msr
19869 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19870 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19873 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19874 #undef THUMB_VARIANT
19875 #define THUMB_VARIANT & arm_ext_v6t2
19877 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19878 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19879 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19880 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19881 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19882 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19883 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19884 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19887 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19888 #undef THUMB_VARIANT
19889 #define THUMB_VARIANT & arm_ext_v4t
19891 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19892 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19893 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19894 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19895 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19896 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19899 #define ARM_VARIANT & arm_ext_v4t_5
19901 /* ARM Architecture 4T. */
19902 /* Note: bx (and blx) are required on V5, even if the processor does
19903 not support Thumb. */
19904 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19907 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19908 #undef THUMB_VARIANT
19909 #define THUMB_VARIANT & arm_ext_v5t
19911 /* Note: blx has 2 variants; the .value coded here is for
19912 BLX(2). Only this variant has conditional execution. */
19913 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19914 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19916 #undef THUMB_VARIANT
19917 #define THUMB_VARIANT & arm_ext_v6t2
19919 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19920 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19921 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19922 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19923 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19924 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19925 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19926 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19929 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19930 #undef THUMB_VARIANT
19931 #define THUMB_VARIANT & arm_ext_v5exp
19933 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19934 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19935 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19936 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19938 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19939 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19941 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19942 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19943 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19944 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19946 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19947 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19948 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19949 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19951 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19952 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19954 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19955 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19956 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19957 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19960 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19961 #undef THUMB_VARIANT
19962 #define THUMB_VARIANT & arm_ext_v6t2
19964 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19965 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19967 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19968 ADDRGLDRS
), ldrd
, t_ldstd
),
19970 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19971 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19974 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19976 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19979 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19980 #undef THUMB_VARIANT
19981 #define THUMB_VARIANT & arm_ext_v6
19983 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19984 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19985 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19986 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19987 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19988 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19989 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19990 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19991 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19992 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19994 #undef THUMB_VARIANT
19995 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19997 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19998 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20000 #undef THUMB_VARIANT
20001 #define THUMB_VARIANT & arm_ext_v6t2
20003 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20004 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20006 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
20007 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
20009 /* ARM V6 not included in V7M. */
20010 #undef THUMB_VARIANT
20011 #define THUMB_VARIANT & arm_ext_v6_notm
20012 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20013 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20014 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
20015 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
20016 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20017 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20018 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
20019 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20020 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
20021 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20022 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20023 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20024 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20025 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20026 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
20027 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
20028 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20029 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20030 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
20032 /* ARM V6 not included in V7M (eg. integer SIMD). */
20033 #undef THUMB_VARIANT
20034 #define THUMB_VARIANT & arm_ext_v6_dsp
20035 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
20036 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
20037 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20038 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20039 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20040 /* Old name for QASX. */
20041 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20042 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20043 /* Old name for QSAX. */
20044 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20045 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20046 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20047 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20048 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20049 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20050 /* Old name for SASX. */
20051 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20052 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20053 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20054 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20055 /* Old name for SHASX. */
20056 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20057 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20058 /* Old name for SHSAX. */
20059 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20060 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20061 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20062 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20063 /* Old name for SSAX. */
20064 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20065 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20066 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20067 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20068 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20069 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20070 /* Old name for UASX. */
20071 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20072 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20073 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20074 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20075 /* Old name for UHASX. */
20076 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20077 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20078 /* Old name for UHSAX. */
20079 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20080 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20081 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20082 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20083 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20084 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20085 /* Old name for UQASX. */
20086 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20087 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20088 /* Old name for UQSAX. */
20089 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20090 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20091 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20092 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20093 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20094 /* Old name for USAX. */
20095 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20096 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20097 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20098 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20099 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20100 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20101 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20102 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20103 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20104 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20105 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20106 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20107 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20108 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20109 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20110 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20111 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20112 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20113 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
20114 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20115 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20116 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20117 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20118 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20119 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20120 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20121 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20122 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20123 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20124 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
20125 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
20126 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20127 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
20128 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
20131 #define ARM_VARIANT & arm_ext_v6k_v6t2
20132 #undef THUMB_VARIANT
20133 #define THUMB_VARIANT & arm_ext_v6k_v6t2
20135 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
20136 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
20137 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
20138 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20140 #undef THUMB_VARIANT
20141 #define THUMB_VARIANT & arm_ext_v6_notm
20142 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20144 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20145 RRnpcb
), strexd
, t_strexd
),
20147 #undef THUMB_VARIANT
20148 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20149 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20151 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20153 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20155 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20157 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20160 #define ARM_VARIANT & arm_ext_sec
20161 #undef THUMB_VARIANT
20162 #define THUMB_VARIANT & arm_ext_sec
20164 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20167 #define ARM_VARIANT & arm_ext_virt
20168 #undef THUMB_VARIANT
20169 #define THUMB_VARIANT & arm_ext_virt
20171 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20172 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20175 #define ARM_VARIANT & arm_ext_pan
20176 #undef THUMB_VARIANT
20177 #define THUMB_VARIANT & arm_ext_pan
20179 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20182 #define ARM_VARIANT & arm_ext_v6t2
20183 #undef THUMB_VARIANT
20184 #define THUMB_VARIANT & arm_ext_v6t2
20186 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20187 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20188 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20189 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20191 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20192 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20194 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20195 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20196 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20197 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20200 #define ARM_VARIANT & arm_ext_v3
20201 #undef THUMB_VARIANT
20202 #define THUMB_VARIANT & arm_ext_v6t2
20204 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20205 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20206 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20209 #define ARM_VARIANT & arm_ext_v6t2
20210 #undef THUMB_VARIANT
20211 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20212 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20213 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20215 /* Thumb-only instructions. */
20217 #define ARM_VARIANT NULL
20218 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20219 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20221 /* ARM does not really have an IT instruction, so always allow it.
20222 The opcode is copied from Thumb in order to allow warnings in
20223 -mimplicit-it=[never | arm] modes. */
20225 #define ARM_VARIANT & arm_ext_v1
20226 #undef THUMB_VARIANT
20227 #define THUMB_VARIANT & arm_ext_v6t2
20229 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20230 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20231 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20232 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20233 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20234 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20235 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20236 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20237 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20238 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20239 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20240 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20241 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20242 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20243 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20244 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20245 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20246 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20248 /* Thumb2 only instructions. */
20250 #define ARM_VARIANT NULL
20252 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20253 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20254 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20255 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20256 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20257 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20259 /* Hardware division instructions. */
20261 #define ARM_VARIANT & arm_ext_adiv
20262 #undef THUMB_VARIANT
20263 #define THUMB_VARIANT & arm_ext_div
20265 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20266 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20268 /* ARM V6M/V7 instructions. */
20270 #define ARM_VARIANT & arm_ext_barrier
20271 #undef THUMB_VARIANT
20272 #define THUMB_VARIANT & arm_ext_barrier
20274 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20275 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20276 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20278 /* ARM V7 instructions. */
20280 #define ARM_VARIANT & arm_ext_v7
20281 #undef THUMB_VARIANT
20282 #define THUMB_VARIANT & arm_ext_v7
20284 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20285 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20288 #define ARM_VARIANT & arm_ext_mp
20289 #undef THUMB_VARIANT
20290 #define THUMB_VARIANT & arm_ext_mp
20292 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20294 /* AArchv8 instructions. */
20296 #define ARM_VARIANT & arm_ext_v8
20298 /* Instructions shared between armv8-a and armv8-m. */
20299 #undef THUMB_VARIANT
20300 #define THUMB_VARIANT & arm_ext_atomics
20302 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20303 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20304 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20305 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20306 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20307 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20308 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20309 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20310 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20311 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20313 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20315 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20317 #undef THUMB_VARIANT
20318 #define THUMB_VARIANT & arm_ext_v8
20320 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20321 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20323 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20326 /* Defined in V8 but is in undefined encoding space for earlier
20327 architectures. However earlier architectures are required to treat
20328 this instuction as a semihosting trap as well. Hence while not explicitly
20329 defined as such, it is in fact correct to define the instruction for all
20331 #undef THUMB_VARIANT
20332 #define THUMB_VARIANT & arm_ext_v1
20334 #define ARM_VARIANT & arm_ext_v1
20335 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20337 /* ARMv8 T32 only. */
20339 #define ARM_VARIANT NULL
20340 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20341 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20342 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20344 /* FP for ARMv8. */
20346 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20347 #undef THUMB_VARIANT
20348 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20350 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20351 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20352 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20353 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20354 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20355 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20356 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20357 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20358 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20359 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20360 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20361 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20362 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20363 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20364 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20365 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20366 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20368 /* Crypto v1 extensions. */
20370 #define ARM_VARIANT & fpu_crypto_ext_armv8
20371 #undef THUMB_VARIANT
20372 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20374 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20375 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20376 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20377 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20378 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20379 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20380 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20381 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20382 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20383 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20384 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20385 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20386 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20387 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20390 #define ARM_VARIANT & crc_ext_armv8
20391 #undef THUMB_VARIANT
20392 #define THUMB_VARIANT & crc_ext_armv8
20393 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20394 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20395 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20396 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20397 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20398 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20400 /* ARMv8.2 RAS extension. */
20402 #define ARM_VARIANT & arm_ext_ras
20403 #undef THUMB_VARIANT
20404 #define THUMB_VARIANT & arm_ext_ras
20405 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20408 #define ARM_VARIANT & arm_ext_v8_3
20409 #undef THUMB_VARIANT
20410 #define THUMB_VARIANT & arm_ext_v8_3
20411 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20412 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20413 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20416 #define ARM_VARIANT & fpu_neon_ext_dotprod
20417 #undef THUMB_VARIANT
20418 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20419 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20420 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20423 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20424 #undef THUMB_VARIANT
20425 #define THUMB_VARIANT NULL
20427 cCE("wfs", e200110
, 1, (RR
), rd
),
20428 cCE("rfs", e300110
, 1, (RR
), rd
),
20429 cCE("wfc", e400110
, 1, (RR
), rd
),
20430 cCE("rfc", e500110
, 1, (RR
), rd
),
20432 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20433 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20434 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20435 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20437 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20438 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20439 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20440 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20442 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20444 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20446 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20447 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20453 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20457 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20459 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20460 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20466 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20470 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20472 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20473 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20479 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20482 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20483 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20484 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20485 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20486 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20487 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20488 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20489 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20490 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20491 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20492 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20494 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20495 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20496 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20497 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20498 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20499 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20500 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20501 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20502 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20503 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20504 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20505 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20507 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20508 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20509 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20510 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20511 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20512 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20513 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20514 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20515 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20516 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20517 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20518 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20520 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20521 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20522 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20523 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20524 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20525 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20526 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20527 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20528 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20529 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20530 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20531 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20533 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20534 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20535 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20536 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20537 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20538 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20539 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20540 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20541 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20542 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20543 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20544 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20546 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20547 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20548 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20549 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20550 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20551 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20552 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20553 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20554 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20555 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20556 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20557 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20559 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20560 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20561 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20562 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20563 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20564 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20565 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20566 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20567 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20568 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20569 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20570 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20572 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20573 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20574 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20575 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20576 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20577 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20578 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20579 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20580 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20581 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20582 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20583 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20585 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20586 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20587 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20588 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20589 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20590 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20591 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20592 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20593 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20594 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20595 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20596 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20598 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20599 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20600 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20601 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20602 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20603 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20604 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20605 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20606 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20607 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20608 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20609 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20611 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20612 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20613 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20614 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20615 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20616 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20617 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20618 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20619 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20620 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20621 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20622 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20624 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20625 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20626 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20627 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20628 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20629 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20630 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20631 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20632 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20633 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20634 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20635 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20637 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20638 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20639 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20640 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20641 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20642 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20643 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20644 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20645 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20646 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20647 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20648 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20650 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20651 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20652 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20653 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20654 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20655 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20656 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20657 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20658 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20659 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20660 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20661 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20663 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20664 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20665 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20666 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20667 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20668 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20669 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20670 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20671 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20672 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20673 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20674 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20676 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20677 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20678 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20679 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20680 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20681 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20682 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20683 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20684 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20685 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20686 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20687 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20689 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20690 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20691 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20692 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20693 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20694 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20695 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20696 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20697 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20698 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20699 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20700 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20702 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20703 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20704 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20705 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20706 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20707 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20708 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20709 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20710 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20711 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20712 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20713 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20715 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20716 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20717 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20718 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20719 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20720 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20721 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20722 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20723 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20724 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20725 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20726 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20728 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20729 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20730 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20731 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20732 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20733 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20734 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20735 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20736 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20737 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20738 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20739 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20741 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20742 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20743 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20744 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20745 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20746 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20747 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20748 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20749 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20750 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20751 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20752 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20754 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20755 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20756 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20757 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20758 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20759 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20760 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20761 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20762 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20763 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20764 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20765 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20767 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20768 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20769 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20770 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20771 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20772 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20773 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20774 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20775 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20776 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20777 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20778 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20780 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20781 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20782 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20783 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20784 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20785 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20786 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20787 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20788 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20789 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20790 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20791 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20793 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20794 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20795 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20796 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20797 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20798 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20799 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20800 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20801 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20802 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20803 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20804 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20806 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20807 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20808 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20809 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20810 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20811 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20812 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20813 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20814 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20815 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20816 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20817 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20819 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20820 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20821 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20822 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20824 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20825 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20826 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20827 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20828 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20829 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20830 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20831 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20832 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20833 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20834 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20835 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20837 /* The implementation of the FIX instruction is broken on some
20838 assemblers, in that it accepts a precision specifier as well as a
20839 rounding specifier, despite the fact that this is meaningless.
20840 To be more compatible, we accept it as well, though of course it
20841 does not set any bits. */
20842 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20843 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20844 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20845 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20846 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20847 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20848 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20849 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20850 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20851 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20852 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20853 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20854 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20856 /* Instructions that were new with the real FPA, call them V2. */
20858 #define ARM_VARIANT & fpu_fpa_ext_v2
20860 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20861 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20862 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20863 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20864 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20865 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20868 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20870 /* Moves and type conversions. */
20871 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20872 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20873 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20874 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20875 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20876 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20877 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20878 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20879 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20880 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20881 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20882 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20883 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20884 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20886 /* Memory operations. */
20887 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20888 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20889 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20890 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20891 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20892 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20893 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20894 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20895 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20896 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20897 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20898 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20899 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20900 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20901 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20902 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20903 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20904 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20906 /* Monadic operations. */
20907 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20908 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20909 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20911 /* Dyadic operations. */
20912 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20913 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20914 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20915 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20916 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20917 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20918 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20919 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20920 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20923 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20924 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20925 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20926 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20928 /* Double precision load/store are still present on single precision
20929 implementations. */
20930 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20931 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20932 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20933 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20934 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20935 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20936 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20937 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20938 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20939 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20942 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20944 /* Moves and type conversions. */
20945 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20946 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20947 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20948 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20949 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20950 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20951 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20952 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20953 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20954 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20955 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20956 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20957 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20959 /* Monadic operations. */
20960 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20961 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20962 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20964 /* Dyadic operations. */
20965 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20966 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20967 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20968 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20969 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20970 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20971 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20972 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20973 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20976 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20977 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20978 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20979 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20982 #define ARM_VARIANT & fpu_vfp_ext_v2
20984 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20985 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20986 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20987 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20989 /* Instructions which may belong to either the Neon or VFP instruction sets.
20990 Individual encoder functions perform additional architecture checks. */
20992 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20993 #undef THUMB_VARIANT
20994 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20996 /* These mnemonics are unique to VFP. */
20997 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20998 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20999 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21000 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21001 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21002 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21003 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21004 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
21005 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
21006 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
21008 /* Mnemonics shared by Neon and VFP. */
21009 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
21010 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21011 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21013 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21014 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
21016 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21017 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
21019 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21020 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21021 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21022 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21023 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21024 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21025 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21026 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
21028 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
21029 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
21030 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
21031 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
21034 /* NOTE: All VMOV encoding is special-cased! */
21035 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
21036 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
21039 #define ARM_VARIANT & arm_ext_fp16
21040 #undef THUMB_VARIANT
21041 #define THUMB_VARIANT & arm_ext_fp16
21042 /* New instructions added from v8.2, allowing the extraction and insertion of
21043 the upper 16 bits of a 32-bit vector register. */
21044 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
21045 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
21047 /* New backported fma/fms instructions optional in v8.2. */
21048 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
21049 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
21051 #undef THUMB_VARIANT
21052 #define THUMB_VARIANT & fpu_neon_ext_v1
21054 #define ARM_VARIANT & fpu_neon_ext_v1
21056 /* Data processing with three registers of the same length. */
21057 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
21058 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
21059 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
21060 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21061 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21062 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21063 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21064 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21065 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21066 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
21067 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21068 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21069 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21070 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21071 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21072 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21073 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21074 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21075 /* If not immediate, fall back to neon_dyadic_i64_su.
21076 shl_imm should accept I8 I16 I32 I64,
21077 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21078 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
21079 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
21080 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
21081 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
21082 /* Logic ops, types optional & ignored. */
21083 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21084 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21085 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21086 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21087 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21088 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21089 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21090 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21091 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
21092 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
21093 /* Bitfield ops, untyped. */
21094 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21095 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21096 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21097 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21098 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21099 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21100 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21101 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21102 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21103 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21104 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21105 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
21106 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
21107 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
21108 back to neon_dyadic_if_su. */
21109 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21110 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21111 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
21112 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
21113 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21114 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21115 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
21116 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
21117 /* Comparison. Type I8 I16 I32 F32. */
21118 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
21119 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
21120 /* As above, D registers only. */
21121 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21122 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
21123 /* Int and float variants, signedness unimportant. */
21124 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21125 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
21126 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
21127 /* Add/sub take types I8 I16 I32 I64 F32. */
21128 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21129 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
21130 /* vtst takes sizes 8, 16, 32. */
21131 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
21132 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
21133 /* VMUL takes I8 I16 I32 F32 P8. */
21134 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
21135 /* VQD{R}MULH takes S16 S32. */
21136 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21137 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21138 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
21139 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
21140 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21141 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21142 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
21143 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
21144 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21145 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21146 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
21147 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
21148 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21149 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21150 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21151 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21152 /* ARM v8.1 extension. */
21153 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21154 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21155 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21156 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21158 /* Two address, int/float. Types S8 S16 S32 F32. */
21159 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21160 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21162 /* Data processing with two registers and a shift amount. */
21163 /* Right shifts, and variants with rounding.
21164 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21165 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21166 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21167 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21168 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21169 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21170 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21171 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21172 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21173 /* Shift and insert. Sizes accepted 8 16 32 64. */
21174 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21175 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21176 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21177 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21178 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21179 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21180 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21181 /* Right shift immediate, saturating & narrowing, with rounding variants.
21182 Types accepted S16 S32 S64 U16 U32 U64. */
21183 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21184 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21185 /* As above, unsigned. Types accepted S16 S32 S64. */
21186 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21187 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21188 /* Right shift narrowing. Types accepted I16 I32 I64. */
21189 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21190 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21191 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21192 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21193 /* CVT with optional immediate for fixed-point variant. */
21194 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21196 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21197 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21199 /* Data processing, three registers of different lengths. */
21200 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21201 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21202 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21203 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21204 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21205 /* If not scalar, fall back to neon_dyadic_long.
21206 Vector types as above, scalar types S16 S32 U16 U32. */
21207 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21208 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21209 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21210 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21211 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21212 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21213 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21214 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21215 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21216 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21217 /* Saturating doubling multiplies. Types S16 S32. */
21218 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21219 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21220 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21221 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21222 S16 S32 U16 U32. */
21223 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21225 /* Extract. Size 8. */
21226 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21227 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21229 /* Two registers, miscellaneous. */
21230 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21231 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21232 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21233 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21234 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21235 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21236 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21237 /* Vector replicate. Sizes 8 16 32. */
21238 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21239 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21240 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21241 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21242 /* VMOVN. Types I16 I32 I64. */
21243 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21244 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21245 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21246 /* VQMOVUN. Types S16 S32 S64. */
21247 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21248 /* VZIP / VUZP. Sizes 8 16 32. */
21249 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21250 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21251 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21252 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21253 /* VQABS / VQNEG. Types S8 S16 S32. */
21254 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21255 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21256 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21257 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21258 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21259 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21260 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21261 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21262 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21263 /* Reciprocal estimates. Types U32 F16 F32. */
21264 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21265 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21266 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21267 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21268 /* VCLS. Types S8 S16 S32. */
21269 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21270 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21271 /* VCLZ. Types I8 I16 I32. */
21272 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21273 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21274 /* VCNT. Size 8. */
21275 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21276 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21277 /* Two address, untyped. */
21278 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21279 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21280 /* VTRN. Sizes 8 16 32. */
21281 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21282 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21284 /* Table lookup. Size 8. */
21285 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21286 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21288 #undef THUMB_VARIANT
21289 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21291 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21293 /* Neon element/structure load/store. */
21294 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21295 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21296 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21297 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21298 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21299 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21300 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21301 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21303 #undef THUMB_VARIANT
21304 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21306 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21307 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21308 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21309 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21310 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21311 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21312 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21313 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21314 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21315 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21317 #undef THUMB_VARIANT
21318 #define THUMB_VARIANT & fpu_vfp_ext_v3
21320 #define ARM_VARIANT & fpu_vfp_ext_v3
21322 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21323 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21324 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21325 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21326 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21327 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21328 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21329 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21330 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21333 #define ARM_VARIANT & fpu_vfp_ext_fma
21334 #undef THUMB_VARIANT
21335 #define THUMB_VARIANT & fpu_vfp_ext_fma
21336 /* Mnemonics shared by Neon and VFP. These are included in the
21337 VFP FMA variant; NEON and VFP FMA always includes the NEON
21338 FMA instructions. */
21339 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21340 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21341 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21342 the v form should always be used. */
21343 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21344 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21345 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21346 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21347 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21348 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21350 #undef THUMB_VARIANT
21352 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21354 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21355 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21356 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21357 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21358 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21359 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21360 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21361 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21364 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21366 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21367 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21368 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21369 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21370 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21371 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21372 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21373 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21374 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21375 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21376 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21377 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21378 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21379 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21380 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21381 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21382 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21383 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21384 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21385 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21386 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21387 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21388 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21389 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21390 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21391 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21392 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21393 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21394 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21395 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21396 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21397 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21398 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21399 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21400 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21401 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21402 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21403 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21404 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21405 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21406 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21407 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21408 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21409 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21410 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21411 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21412 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21413 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21417 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21418 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21419 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21420 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21421 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21422 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21423 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21424 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21425 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21426 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21427 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21428 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21429 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21430 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21431 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21432 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21433 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21434 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21435 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21436 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21437 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21438 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21439 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21440 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21441 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21442 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21443 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21444 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21445 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21446 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21447 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21448 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21449 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21450 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21451 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21452 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21453 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21454 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21455 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21456 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21457 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21458 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21459 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21460 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21461 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21462 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21463 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21464 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21465 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21466 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21467 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21468 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21469 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21470 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21471 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21472 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21473 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21474 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21475 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21476 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21477 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21478 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21479 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21480 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21481 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21482 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21483 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21484 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21485 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21486 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21487 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21488 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21489 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21490 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21491 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21492 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21493 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21494 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21495 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21496 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21497 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21498 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21499 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21500 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21501 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21502 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21503 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21504 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21505 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21506 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21507 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21508 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21509 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21510 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21511 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21512 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21513 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21514 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21515 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21516 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21517 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21518 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21519 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21520 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21521 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21522 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21523 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21524 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21525 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21526 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21527 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21530 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21532 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21533 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21534 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21535 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21536 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21537 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21538 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21539 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21540 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21541 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21542 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21543 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21544 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21545 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21546 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21547 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21548 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21549 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21550 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21551 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21552 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21553 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21554 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21555 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21556 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21557 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21558 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21559 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21560 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21561 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21562 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21563 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21564 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21565 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21566 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21567 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21568 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21569 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21570 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21571 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21572 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21573 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21574 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21575 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21576 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21577 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21578 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21579 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21580 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21581 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21582 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21583 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21584 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21585 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21586 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21587 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21588 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21591 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21593 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21594 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21595 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21596 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21597 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21598 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21599 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21600 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21601 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21602 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21603 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21604 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21605 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21606 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21607 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21608 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21609 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21610 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21611 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21612 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21613 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21614 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21615 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21616 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21617 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21618 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21619 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21620 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21621 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21622 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21623 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21624 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21625 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21626 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21627 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21628 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21629 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21630 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21631 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21632 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21633 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21634 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21635 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21636 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21637 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21638 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21639 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21640 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21641 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21642 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21643 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21644 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21645 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21646 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21647 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21648 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21649 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21650 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21651 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21652 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21653 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21654 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21655 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21656 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21657 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21658 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21659 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21660 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21661 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21662 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21663 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21664 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21665 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21666 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21667 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21668 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21670 /* ARMv8.5-A instructions. */
21672 #define ARM_VARIANT & arm_ext_sb
21673 #undef THUMB_VARIANT
21674 #define THUMB_VARIANT & arm_ext_sb
21675 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
21678 #define ARM_VARIANT & arm_ext_predres
21679 #undef THUMB_VARIANT
21680 #define THUMB_VARIANT & arm_ext_predres
21681 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
21682 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
21683 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
21685 /* ARMv8-M instructions. */
21687 #define ARM_VARIANT NULL
21688 #undef THUMB_VARIANT
21689 #define THUMB_VARIANT & arm_ext_v8m
21690 ToU("sg", e97fe97f
, 0, (), noargs
),
21691 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21692 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21693 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21694 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21695 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21696 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21698 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21699 instructions behave as nop if no VFP is present. */
21700 #undef THUMB_VARIANT
21701 #define THUMB_VARIANT & arm_ext_v8m_main
21702 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21703 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21705 /* Armv8.1-M Mainline instructions. */
21706 #undef THUMB_VARIANT
21707 #define THUMB_VARIANT & arm_ext_v8_1m_main
21708 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
21709 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21710 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
21711 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
21714 #undef THUMB_VARIANT
21745 /* MD interface: bits in the object file. */
21747 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21748 for use in the a.out file, and stores them in the array pointed to by buf.
21749 This knows about the endian-ness of the target machine and does
21750 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21751 2 (short) and 4 (long) Floating numbers are put out as a series of
21752 LITTLENUMS (shorts, here at least). */
21755 md_number_to_chars (char * buf
, valueT val
, int n
)
21757 if (target_big_endian
)
21758 number_to_chars_bigendian (buf
, val
, n
);
21760 number_to_chars_littleendian (buf
, val
, n
);
21764 md_chars_to_number (char * buf
, int n
)
21767 unsigned char * where
= (unsigned char *) buf
;
21769 if (target_big_endian
)
21774 result
|= (*where
++ & 255);
21782 result
|= (where
[n
] & 255);
21789 /* MD interface: Sections. */
21791 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21792 that an rs_machine_dependent frag may reach. */
21795 arm_frag_max_var (fragS
*fragp
)
21797 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21798 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21800 Note that we generate relaxable instructions even for cases that don't
21801 really need it, like an immediate that's a trivial constant. So we're
21802 overestimating the instruction size for some of those cases. Rather
21803 than putting more intelligence here, it would probably be better to
21804 avoid generating a relaxation frag in the first place when it can be
21805 determined up front that a short instruction will suffice. */
21807 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21811 /* Estimate the size of a frag before relaxing. Assume everything fits in
21815 md_estimate_size_before_relax (fragS
* fragp
,
21816 segT segtype ATTRIBUTE_UNUSED
)
21822 /* Convert a machine dependent frag. */
21825 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21827 unsigned long insn
;
21828 unsigned long old_op
;
21836 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21838 old_op
= bfd_get_16(abfd
, buf
);
21839 if (fragp
->fr_symbol
)
21841 exp
.X_op
= O_symbol
;
21842 exp
.X_add_symbol
= fragp
->fr_symbol
;
21846 exp
.X_op
= O_constant
;
21848 exp
.X_add_number
= fragp
->fr_offset
;
21849 opcode
= fragp
->fr_subtype
;
21852 case T_MNEM_ldr_pc
:
21853 case T_MNEM_ldr_pc2
:
21854 case T_MNEM_ldr_sp
:
21855 case T_MNEM_str_sp
:
21862 if (fragp
->fr_var
== 4)
21864 insn
= THUMB_OP32 (opcode
);
21865 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21867 insn
|= (old_op
& 0x700) << 4;
21871 insn
|= (old_op
& 7) << 12;
21872 insn
|= (old_op
& 0x38) << 13;
21874 insn
|= 0x00000c00;
21875 put_thumb32_insn (buf
, insn
);
21876 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21880 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21882 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21885 if (fragp
->fr_var
== 4)
21887 insn
= THUMB_OP32 (opcode
);
21888 insn
|= (old_op
& 0xf0) << 4;
21889 put_thumb32_insn (buf
, insn
);
21890 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21894 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21895 exp
.X_add_number
-= 4;
21903 if (fragp
->fr_var
== 4)
21905 int r0off
= (opcode
== T_MNEM_mov
21906 || opcode
== T_MNEM_movs
) ? 0 : 8;
21907 insn
= THUMB_OP32 (opcode
);
21908 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21909 insn
|= (old_op
& 0x700) << r0off
;
21910 put_thumb32_insn (buf
, insn
);
21911 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21915 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21920 if (fragp
->fr_var
== 4)
21922 insn
= THUMB_OP32(opcode
);
21923 put_thumb32_insn (buf
, insn
);
21924 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21927 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21931 if (fragp
->fr_var
== 4)
21933 insn
= THUMB_OP32(opcode
);
21934 insn
|= (old_op
& 0xf00) << 14;
21935 put_thumb32_insn (buf
, insn
);
21936 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21939 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21942 case T_MNEM_add_sp
:
21943 case T_MNEM_add_pc
:
21944 case T_MNEM_inc_sp
:
21945 case T_MNEM_dec_sp
:
21946 if (fragp
->fr_var
== 4)
21948 /* ??? Choose between add and addw. */
21949 insn
= THUMB_OP32 (opcode
);
21950 insn
|= (old_op
& 0xf0) << 4;
21951 put_thumb32_insn (buf
, insn
);
21952 if (opcode
== T_MNEM_add_pc
)
21953 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21955 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21958 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21966 if (fragp
->fr_var
== 4)
21968 insn
= THUMB_OP32 (opcode
);
21969 insn
|= (old_op
& 0xf0) << 4;
21970 insn
|= (old_op
& 0xf) << 16;
21971 put_thumb32_insn (buf
, insn
);
21972 if (insn
& (1 << 20))
21973 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21975 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21978 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21984 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21985 (enum bfd_reloc_code_real
) reloc_type
);
21986 fixp
->fx_file
= fragp
->fr_file
;
21987 fixp
->fx_line
= fragp
->fr_line
;
21988 fragp
->fr_fix
+= fragp
->fr_var
;
21990 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21991 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21992 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21993 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21996 /* Return the size of a relaxable immediate operand instruction.
21997 SHIFT and SIZE specify the form of the allowable immediate. */
21999 relax_immediate (fragS
*fragp
, int size
, int shift
)
22005 /* ??? Should be able to do better than this. */
22006 if (fragp
->fr_symbol
)
22009 low
= (1 << shift
) - 1;
22010 mask
= (1 << (shift
+ size
)) - (1 << shift
);
22011 offset
= fragp
->fr_offset
;
22012 /* Force misaligned offsets to 32-bit variant. */
22015 if (offset
& ~mask
)
22020 /* Get the address of a symbol during relaxation. */
22022 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
22028 sym
= fragp
->fr_symbol
;
22029 sym_frag
= symbol_get_frag (sym
);
22030 know (S_GET_SEGMENT (sym
) != absolute_section
22031 || sym_frag
== &zero_address_frag
);
22032 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
22034 /* If frag has yet to be reached on this pass, assume it will
22035 move by STRETCH just as we did. If this is not so, it will
22036 be because some frag between grows, and that will force
22040 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
22044 /* Adjust stretch for any alignment frag. Note that if have
22045 been expanding the earlier code, the symbol may be
22046 defined in what appears to be an earlier frag. FIXME:
22047 This doesn't handle the fr_subtype field, which specifies
22048 a maximum number of bytes to skip when doing an
22050 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
22052 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
22055 stretch
= - ((- stretch
)
22056 & ~ ((1 << (int) f
->fr_offset
) - 1));
22058 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
22070 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
22073 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
22078 /* Assume worst case for symbols not known to be in the same section. */
22079 if (fragp
->fr_symbol
== NULL
22080 || !S_IS_DEFINED (fragp
->fr_symbol
)
22081 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22082 || S_IS_WEAK (fragp
->fr_symbol
))
22085 val
= relaxed_symbol_addr (fragp
, stretch
);
22086 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
22087 addr
= (addr
+ 4) & ~3;
22088 /* Force misaligned targets to 32-bit variant. */
22092 if (val
< 0 || val
> 1020)
22097 /* Return the size of a relaxable add/sub immediate instruction. */
22099 relax_addsub (fragS
*fragp
, asection
*sec
)
22104 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22105 op
= bfd_get_16(sec
->owner
, buf
);
22106 if ((op
& 0xf) == ((op
>> 4) & 0xf))
22107 return relax_immediate (fragp
, 8, 0);
22109 return relax_immediate (fragp
, 3, 0);
22112 /* Return TRUE iff the definition of symbol S could be pre-empted
22113 (overridden) at link or load time. */
22115 symbol_preemptible (symbolS
*s
)
22117 /* Weak symbols can always be pre-empted. */
22121 /* Non-global symbols cannot be pre-empted. */
22122 if (! S_IS_EXTERNAL (s
))
22126 /* In ELF, a global symbol can be marked protected, or private. In that
22127 case it can't be pre-empted (other definitions in the same link unit
22128 would violate the ODR). */
22129 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
22133 /* Other global symbols might be pre-empted. */
22137 /* Return the size of a relaxable branch instruction. BITS is the
22138 size of the offset field in the narrow instruction. */
22141 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
22147 /* Assume worst case for symbols not known to be in the same section. */
22148 if (!S_IS_DEFINED (fragp
->fr_symbol
)
22149 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
22150 || S_IS_WEAK (fragp
->fr_symbol
))
22154 /* A branch to a function in ARM state will require interworking. */
22155 if (S_IS_DEFINED (fragp
->fr_symbol
)
22156 && ARM_IS_FUNC (fragp
->fr_symbol
))
22160 if (symbol_preemptible (fragp
->fr_symbol
))
22163 val
= relaxed_symbol_addr (fragp
, stretch
);
22164 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
22167 /* Offset is a signed value *2 */
22169 if (val
>= limit
|| val
< -limit
)
22175 /* Relax a machine dependent frag. This returns the amount by which
22176 the current size of the frag should change. */
22179 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22184 oldsize
= fragp
->fr_var
;
22185 switch (fragp
->fr_subtype
)
22187 case T_MNEM_ldr_pc2
:
22188 newsize
= relax_adr (fragp
, sec
, stretch
);
22190 case T_MNEM_ldr_pc
:
22191 case T_MNEM_ldr_sp
:
22192 case T_MNEM_str_sp
:
22193 newsize
= relax_immediate (fragp
, 8, 2);
22197 newsize
= relax_immediate (fragp
, 5, 2);
22201 newsize
= relax_immediate (fragp
, 5, 1);
22205 newsize
= relax_immediate (fragp
, 5, 0);
22208 newsize
= relax_adr (fragp
, sec
, stretch
);
22214 newsize
= relax_immediate (fragp
, 8, 0);
22217 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22220 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22222 case T_MNEM_add_sp
:
22223 case T_MNEM_add_pc
:
22224 newsize
= relax_immediate (fragp
, 8, 2);
22226 case T_MNEM_inc_sp
:
22227 case T_MNEM_dec_sp
:
22228 newsize
= relax_immediate (fragp
, 7, 2);
22234 newsize
= relax_addsub (fragp
, sec
);
22240 fragp
->fr_var
= newsize
;
22241 /* Freeze wide instructions that are at or before the same location as
22242 in the previous pass. This avoids infinite loops.
22243 Don't freeze them unconditionally because targets may be artificially
22244 misaligned by the expansion of preceding frags. */
22245 if (stretch
<= 0 && newsize
> 2)
22247 md_convert_frag (sec
->owner
, sec
, fragp
);
22251 return newsize
- oldsize
;
22254 /* Round up a section size to the appropriate boundary. */
22257 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22263 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22264 of an rs_align_code fragment. */
22267 arm_handle_align (fragS
* fragP
)
22269 static unsigned char const arm_noop
[2][2][4] =
22272 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22273 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22276 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22277 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22280 static unsigned char const thumb_noop
[2][2][2] =
22283 {0xc0, 0x46}, /* LE */
22284 {0x46, 0xc0}, /* BE */
22287 {0x00, 0xbf}, /* LE */
22288 {0xbf, 0x00} /* BE */
22291 static unsigned char const wide_thumb_noop
[2][4] =
22292 { /* Wide Thumb-2 */
22293 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22294 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22297 unsigned bytes
, fix
, noop_size
;
22299 const unsigned char * noop
;
22300 const unsigned char *narrow_noop
= NULL
;
22305 if (fragP
->fr_type
!= rs_align_code
)
22308 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22309 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22312 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22313 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22315 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22317 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22319 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22320 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22322 narrow_noop
= thumb_noop
[1][target_big_endian
];
22323 noop
= wide_thumb_noop
[target_big_endian
];
22326 noop
= thumb_noop
[0][target_big_endian
];
22334 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22335 ? selected_cpu
: arm_arch_none
,
22337 [target_big_endian
];
22344 fragP
->fr_var
= noop_size
;
22346 if (bytes
& (noop_size
- 1))
22348 fix
= bytes
& (noop_size
- 1);
22350 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22352 memset (p
, 0, fix
);
22359 if (bytes
& noop_size
)
22361 /* Insert a narrow noop. */
22362 memcpy (p
, narrow_noop
, noop_size
);
22364 bytes
-= noop_size
;
22368 /* Use wide noops for the remainder */
22372 while (bytes
>= noop_size
)
22374 memcpy (p
, noop
, noop_size
);
22376 bytes
-= noop_size
;
22380 fragP
->fr_fix
+= fix
;
22383 /* Called from md_do_align. Used to create an alignment
22384 frag in a code section. */
22387 arm_frag_align_code (int n
, int max
)
22391 /* We assume that there will never be a requirement
22392 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22393 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22398 _("alignments greater than %d bytes not supported in .text sections."),
22399 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22400 as_fatal ("%s", err_msg
);
22403 p
= frag_var (rs_align_code
,
22404 MAX_MEM_FOR_RS_ALIGN_CODE
,
22406 (relax_substateT
) max
,
22413 /* Perform target specific initialisation of a frag.
22414 Note - despite the name this initialisation is not done when the frag
22415 is created, but only when its type is assigned. A frag can be created
22416 and used a long time before its type is set, so beware of assuming that
22417 this initialisation is performed first. */
22421 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22423 /* Record whether this frag is in an ARM or a THUMB area. */
22424 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22427 #else /* OBJ_ELF is defined. */
22429 arm_init_frag (fragS
* fragP
, int max_chars
)
22431 bfd_boolean frag_thumb_mode
;
22433 /* If the current ARM vs THUMB mode has not already
22434 been recorded into this frag then do so now. */
22435 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22436 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22438 /* PR 21809: Do not set a mapping state for debug sections
22439 - it just confuses other tools. */
22440 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22443 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22445 /* Record a mapping symbol for alignment frags. We will delete this
22446 later if the alignment ends up empty. */
22447 switch (fragP
->fr_type
)
22450 case rs_align_test
:
22452 mapping_state_2 (MAP_DATA
, max_chars
);
22454 case rs_align_code
:
22455 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22462 /* When we change sections we need to issue a new mapping symbol. */
22465 arm_elf_change_section (void)
22467 /* Link an unlinked unwind index table section to the .text section. */
22468 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22469 && elf_linked_to_section (now_seg
) == NULL
)
22470 elf_linked_to_section (now_seg
) = text_section
;
22474 arm_elf_section_type (const char * str
, size_t len
)
22476 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22477 return SHT_ARM_EXIDX
;
22482 /* Code to deal with unwinding tables. */
22484 static void add_unwind_adjustsp (offsetT
);
22486 /* Generate any deferred unwind frame offset. */
22489 flush_pending_unwind (void)
22493 offset
= unwind
.pending_offset
;
22494 unwind
.pending_offset
= 0;
22496 add_unwind_adjustsp (offset
);
22499 /* Add an opcode to this list for this function. Two-byte opcodes should
22500 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22504 add_unwind_opcode (valueT op
, int length
)
22506 /* Add any deferred stack adjustment. */
22507 if (unwind
.pending_offset
)
22508 flush_pending_unwind ();
22510 unwind
.sp_restored
= 0;
22512 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22514 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22515 if (unwind
.opcodes
)
22516 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22517 unwind
.opcode_alloc
);
22519 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22524 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22526 unwind
.opcode_count
++;
22530 /* Add unwind opcodes to adjust the stack pointer. */
22533 add_unwind_adjustsp (offsetT offset
)
22537 if (offset
> 0x200)
22539 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22544 /* Long form: 0xb2, uleb128. */
22545 /* This might not fit in a word so add the individual bytes,
22546 remembering the list is built in reverse order. */
22547 o
= (valueT
) ((offset
- 0x204) >> 2);
22549 add_unwind_opcode (0, 1);
22551 /* Calculate the uleb128 encoding of the offset. */
22555 bytes
[n
] = o
& 0x7f;
22561 /* Add the insn. */
22563 add_unwind_opcode (bytes
[n
- 1], 1);
22564 add_unwind_opcode (0xb2, 1);
22566 else if (offset
> 0x100)
22568 /* Two short opcodes. */
22569 add_unwind_opcode (0x3f, 1);
22570 op
= (offset
- 0x104) >> 2;
22571 add_unwind_opcode (op
, 1);
22573 else if (offset
> 0)
22575 /* Short opcode. */
22576 op
= (offset
- 4) >> 2;
22577 add_unwind_opcode (op
, 1);
22579 else if (offset
< 0)
22582 while (offset
> 0x100)
22584 add_unwind_opcode (0x7f, 1);
22587 op
= ((offset
- 4) >> 2) | 0x40;
22588 add_unwind_opcode (op
, 1);
22592 /* Finish the list of unwind opcodes for this function. */
22595 finish_unwind_opcodes (void)
22599 if (unwind
.fp_used
)
22601 /* Adjust sp as necessary. */
22602 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22603 flush_pending_unwind ();
22605 /* After restoring sp from the frame pointer. */
22606 op
= 0x90 | unwind
.fp_reg
;
22607 add_unwind_opcode (op
, 1);
22610 flush_pending_unwind ();
22614 /* Start an exception table entry. If idx is nonzero this is an index table
22618 start_unwind_section (const segT text_seg
, int idx
)
22620 const char * text_name
;
22621 const char * prefix
;
22622 const char * prefix_once
;
22623 const char * group_name
;
22631 prefix
= ELF_STRING_ARM_unwind
;
22632 prefix_once
= ELF_STRING_ARM_unwind_once
;
22633 type
= SHT_ARM_EXIDX
;
22637 prefix
= ELF_STRING_ARM_unwind_info
;
22638 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22639 type
= SHT_PROGBITS
;
22642 text_name
= segment_name (text_seg
);
22643 if (streq (text_name
, ".text"))
22646 if (strncmp (text_name
, ".gnu.linkonce.t.",
22647 strlen (".gnu.linkonce.t.")) == 0)
22649 prefix
= prefix_once
;
22650 text_name
+= strlen (".gnu.linkonce.t.");
22653 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22659 /* Handle COMDAT group. */
22660 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22662 group_name
= elf_group_name (text_seg
);
22663 if (group_name
== NULL
)
22665 as_bad (_("Group section `%s' has no group signature"),
22666 segment_name (text_seg
));
22667 ignore_rest_of_line ();
22670 flags
|= SHF_GROUP
;
22674 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22677 /* Set the section link for index tables. */
22679 elf_linked_to_section (now_seg
) = text_seg
;
22683 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22684 personality routine data. Returns zero, or the index table value for
22685 an inline entry. */
22688 create_unwind_entry (int have_data
)
22693 /* The current word of data. */
22695 /* The number of bytes left in this word. */
22698 finish_unwind_opcodes ();
22700 /* Remember the current text section. */
22701 unwind
.saved_seg
= now_seg
;
22702 unwind
.saved_subseg
= now_subseg
;
22704 start_unwind_section (now_seg
, 0);
22706 if (unwind
.personality_routine
== NULL
)
22708 if (unwind
.personality_index
== -2)
22711 as_bad (_("handlerdata in cantunwind frame"));
22712 return 1; /* EXIDX_CANTUNWIND. */
22715 /* Use a default personality routine if none is specified. */
22716 if (unwind
.personality_index
== -1)
22718 if (unwind
.opcode_count
> 3)
22719 unwind
.personality_index
= 1;
22721 unwind
.personality_index
= 0;
22724 /* Space for the personality routine entry. */
22725 if (unwind
.personality_index
== 0)
22727 if (unwind
.opcode_count
> 3)
22728 as_bad (_("too many unwind opcodes for personality routine 0"));
22732 /* All the data is inline in the index table. */
22735 while (unwind
.opcode_count
> 0)
22737 unwind
.opcode_count
--;
22738 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22742 /* Pad with "finish" opcodes. */
22744 data
= (data
<< 8) | 0xb0;
22751 /* We get two opcodes "free" in the first word. */
22752 size
= unwind
.opcode_count
- 2;
22756 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22757 if (unwind
.personality_index
!= -1)
22759 as_bad (_("attempt to recreate an unwind entry"));
22763 /* An extra byte is required for the opcode count. */
22764 size
= unwind
.opcode_count
+ 1;
22767 size
= (size
+ 3) >> 2;
22769 as_bad (_("too many unwind opcodes"));
22771 frag_align (2, 0, 0);
22772 record_alignment (now_seg
, 2);
22773 unwind
.table_entry
= expr_build_dot ();
22775 /* Allocate the table entry. */
22776 ptr
= frag_more ((size
<< 2) + 4);
22777 /* PR 13449: Zero the table entries in case some of them are not used. */
22778 memset (ptr
, 0, (size
<< 2) + 4);
22779 where
= frag_now_fix () - ((size
<< 2) + 4);
22781 switch (unwind
.personality_index
)
22784 /* ??? Should this be a PLT generating relocation? */
22785 /* Custom personality routine. */
22786 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22787 BFD_RELOC_ARM_PREL31
);
22792 /* Set the first byte to the number of additional words. */
22793 data
= size
> 0 ? size
- 1 : 0;
22797 /* ABI defined personality routines. */
22799 /* Three opcodes bytes are packed into the first word. */
22806 /* The size and first two opcode bytes go in the first word. */
22807 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22812 /* Should never happen. */
22816 /* Pack the opcodes into words (MSB first), reversing the list at the same
22818 while (unwind
.opcode_count
> 0)
22822 md_number_to_chars (ptr
, data
, 4);
22827 unwind
.opcode_count
--;
22829 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22832 /* Finish off the last word. */
22835 /* Pad with "finish" opcodes. */
22837 data
= (data
<< 8) | 0xb0;
22839 md_number_to_chars (ptr
, data
, 4);
22844 /* Add an empty descriptor if there is no user-specified data. */
22845 ptr
= frag_more (4);
22846 md_number_to_chars (ptr
, 0, 4);
22853 /* Initialize the DWARF-2 unwind information for this procedure. */
22856 tc_arm_frame_initial_instructions (void)
22858 cfi_add_CFA_def_cfa (REG_SP
, 0);
22860 #endif /* OBJ_ELF */
22862 /* Convert REGNAME to a DWARF-2 register number. */
22865 tc_arm_regname_to_dw2regnum (char *regname
)
22867 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22871 /* PR 16694: Allow VFP registers as well. */
22872 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22876 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22885 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22889 exp
.X_op
= O_secrel
;
22890 exp
.X_add_symbol
= symbol
;
22891 exp
.X_add_number
= 0;
22892 emit_expr (&exp
, size
);
22896 /* MD interface: Symbol and relocation handling. */
22898 /* Return the address within the segment that a PC-relative fixup is
22899 relative to. For ARM, PC-relative fixups applied to instructions
22900 are generally relative to the location of the fixup plus 8 bytes.
22901 Thumb branches are offset by 4, and Thumb loads relative to PC
22902 require special handling. */
22905 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22907 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22909 /* If this is pc-relative and we are going to emit a relocation
22910 then we just want to put out any pipeline compensation that the linker
22911 will need. Otherwise we want to use the calculated base.
22912 For WinCE we skip the bias for externals as well, since this
22913 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22915 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22916 || (arm_force_relocation (fixP
)
22918 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22924 switch (fixP
->fx_r_type
)
22926 /* PC relative addressing on the Thumb is slightly odd as the
22927 bottom two bits of the PC are forced to zero for the
22928 calculation. This happens *after* application of the
22929 pipeline offset. However, Thumb adrl already adjusts for
22930 this, so we need not do it again. */
22931 case BFD_RELOC_ARM_THUMB_ADD
:
22934 case BFD_RELOC_ARM_THUMB_OFFSET
:
22935 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22936 case BFD_RELOC_ARM_T32_ADD_PC12
:
22937 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22938 return (base
+ 4) & ~3;
22940 /* Thumb branches are simply offset by +4. */
22941 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
22942 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22943 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22944 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22945 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22946 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22947 case BFD_RELOC_ARM_THUMB_BF17
:
22948 case BFD_RELOC_ARM_THUMB_BF19
:
22949 case BFD_RELOC_ARM_THUMB_BF13
:
22952 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22954 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22955 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22956 && ARM_IS_FUNC (fixP
->fx_addsy
)
22957 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22958 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22961 /* BLX is like branches above, but forces the low two bits of PC to
22963 case BFD_RELOC_THUMB_PCREL_BLX
:
22965 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22966 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22967 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22968 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22969 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22970 return (base
+ 4) & ~3;
22972 /* ARM mode branches are offset by +8. However, the Windows CE
22973 loader expects the relocation not to take this into account. */
22974 case BFD_RELOC_ARM_PCREL_BLX
:
22976 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22977 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22978 && ARM_IS_FUNC (fixP
->fx_addsy
)
22979 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22980 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22983 case BFD_RELOC_ARM_PCREL_CALL
:
22985 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22986 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22987 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22988 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22989 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22992 case BFD_RELOC_ARM_PCREL_BRANCH
:
22993 case BFD_RELOC_ARM_PCREL_JUMP
:
22994 case BFD_RELOC_ARM_PLT32
:
22996 /* When handling fixups immediately, because we have already
22997 discovered the value of a symbol, or the address of the frag involved
22998 we must account for the offset by +8, as the OS loader will never see the reloc.
22999 see fixup_segment() in write.c
23000 The S_IS_EXTERNAL test handles the case of global symbols.
23001 Those need the calculated base, not just the pipe compensation the linker will need. */
23003 && fixP
->fx_addsy
!= NULL
23004 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23005 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
23013 /* ARM mode loads relative to PC are also offset by +8. Unlike
23014 branches, the Windows CE loader *does* expect the relocation
23015 to take this into account. */
23016 case BFD_RELOC_ARM_OFFSET_IMM
:
23017 case BFD_RELOC_ARM_OFFSET_IMM8
:
23018 case BFD_RELOC_ARM_HWLITERAL
:
23019 case BFD_RELOC_ARM_LITERAL
:
23020 case BFD_RELOC_ARM_CP_OFF_IMM
:
23024 /* Other PC-relative relocations are un-offset. */
23030 static bfd_boolean flag_warn_syms
= TRUE
;
23033 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
23035 /* PR 18347 - Warn if the user attempts to create a symbol with the same
23036 name as an ARM instruction. Whilst strictly speaking it is allowed, it
23037 does mean that the resulting code might be very confusing to the reader.
23038 Also this warning can be triggered if the user omits an operand before
23039 an immediate address, eg:
23043 GAS treats this as an assignment of the value of the symbol foo to a
23044 symbol LDR, and so (without this code) it will not issue any kind of
23045 warning or error message.
23047 Note - ARM instructions are case-insensitive but the strings in the hash
23048 table are all stored in lower case, so we must first ensure that name is
23050 if (flag_warn_syms
&& arm_ops_hsh
)
23052 char * nbuf
= strdup (name
);
23055 for (p
= nbuf
; *p
; p
++)
23057 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
23059 static struct hash_control
* already_warned
= NULL
;
23061 if (already_warned
== NULL
)
23062 already_warned
= hash_new ();
23063 /* Only warn about the symbol once. To keep the code
23064 simple we let hash_insert do the lookup for us. */
23065 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
23066 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
23075 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
23076 Otherwise we have no need to default values of symbols. */
23079 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
23082 if (name
[0] == '_' && name
[1] == 'G'
23083 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
23087 if (symbol_find (name
))
23088 as_bad (_("GOT already in the symbol table"));
23090 GOT_symbol
= symbol_new (name
, undefined_section
,
23091 (valueT
) 0, & zero_address_frag
);
23101 /* Subroutine of md_apply_fix. Check to see if an immediate can be
23102 computed as two separate immediate values, added together. We
23103 already know that this value cannot be computed by just one ARM
23106 static unsigned int
23107 validate_immediate_twopart (unsigned int val
,
23108 unsigned int * highpart
)
23113 for (i
= 0; i
< 32; i
+= 2)
23114 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
23120 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
23122 else if (a
& 0xff0000)
23124 if (a
& 0xff000000)
23126 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
23130 gas_assert (a
& 0xff000000);
23131 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
23134 return (a
& 0xff) | (i
<< 7);
23141 validate_offset_imm (unsigned int val
, int hwse
)
23143 if ((hwse
&& val
> 255) || val
> 4095)
23148 /* Subroutine of md_apply_fix. Do those data_ops which can take a
23149 negative immediate constant by altering the instruction. A bit of
23154 by inverting the second operand, and
23157 by negating the second operand. */
23160 negate_data_op (unsigned long * instruction
,
23161 unsigned long value
)
23164 unsigned long negated
, inverted
;
23166 negated
= encode_arm_immediate (-value
);
23167 inverted
= encode_arm_immediate (~value
);
23169 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
23172 /* First negates. */
23173 case OPCODE_SUB
: /* ADD <-> SUB */
23174 new_inst
= OPCODE_ADD
;
23179 new_inst
= OPCODE_SUB
;
23183 case OPCODE_CMP
: /* CMP <-> CMN */
23184 new_inst
= OPCODE_CMN
;
23189 new_inst
= OPCODE_CMP
;
23193 /* Now Inverted ops. */
23194 case OPCODE_MOV
: /* MOV <-> MVN */
23195 new_inst
= OPCODE_MVN
;
23200 new_inst
= OPCODE_MOV
;
23204 case OPCODE_AND
: /* AND <-> BIC */
23205 new_inst
= OPCODE_BIC
;
23210 new_inst
= OPCODE_AND
;
23214 case OPCODE_ADC
: /* ADC <-> SBC */
23215 new_inst
= OPCODE_SBC
;
23220 new_inst
= OPCODE_ADC
;
23224 /* We cannot do anything. */
23229 if (value
== (unsigned) FAIL
)
23232 *instruction
&= OPCODE_MASK
;
23233 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23237 /* Like negate_data_op, but for Thumb-2. */
23239 static unsigned int
23240 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23244 unsigned int negated
, inverted
;
23246 negated
= encode_thumb32_immediate (-value
);
23247 inverted
= encode_thumb32_immediate (~value
);
23249 rd
= (*instruction
>> 8) & 0xf;
23250 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23253 /* ADD <-> SUB. Includes CMP <-> CMN. */
23254 case T2_OPCODE_SUB
:
23255 new_inst
= T2_OPCODE_ADD
;
23259 case T2_OPCODE_ADD
:
23260 new_inst
= T2_OPCODE_SUB
;
23264 /* ORR <-> ORN. Includes MOV <-> MVN. */
23265 case T2_OPCODE_ORR
:
23266 new_inst
= T2_OPCODE_ORN
;
23270 case T2_OPCODE_ORN
:
23271 new_inst
= T2_OPCODE_ORR
;
23275 /* AND <-> BIC. TST has no inverted equivalent. */
23276 case T2_OPCODE_AND
:
23277 new_inst
= T2_OPCODE_BIC
;
23284 case T2_OPCODE_BIC
:
23285 new_inst
= T2_OPCODE_AND
;
23290 case T2_OPCODE_ADC
:
23291 new_inst
= T2_OPCODE_SBC
;
23295 case T2_OPCODE_SBC
:
23296 new_inst
= T2_OPCODE_ADC
;
23300 /* We cannot do anything. */
23305 if (value
== (unsigned int)FAIL
)
23308 *instruction
&= T2_OPCODE_MASK
;
23309 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23313 /* Read a 32-bit thumb instruction from buf. */
23315 static unsigned long
23316 get_thumb32_insn (char * buf
)
23318 unsigned long insn
;
23319 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23320 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23325 /* We usually want to set the low bit on the address of thumb function
23326 symbols. In particular .word foo - . should have the low bit set.
23327 Generic code tries to fold the difference of two symbols to
23328 a constant. Prevent this and force a relocation when the first symbols
23329 is a thumb function. */
23332 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23334 if (op
== O_subtract
23335 && l
->X_op
== O_symbol
23336 && r
->X_op
== O_symbol
23337 && THUMB_IS_FUNC (l
->X_add_symbol
))
23339 l
->X_op
= O_subtract
;
23340 l
->X_op_symbol
= r
->X_add_symbol
;
23341 l
->X_add_number
-= r
->X_add_number
;
23345 /* Process as normal. */
23349 /* Encode Thumb2 unconditional branches and calls. The encoding
23350 for the 2 are identical for the immediate values. */
23353 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23355 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23358 addressT S
, I1
, I2
, lo
, hi
;
23360 S
= (value
>> 24) & 0x01;
23361 I1
= (value
>> 23) & 0x01;
23362 I2
= (value
>> 22) & 0x01;
23363 hi
= (value
>> 12) & 0x3ff;
23364 lo
= (value
>> 1) & 0x7ff;
23365 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23366 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23367 newval
|= (S
<< 10) | hi
;
23368 newval2
&= ~T2I1I2MASK
;
23369 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23370 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23371 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23375 md_apply_fix (fixS
* fixP
,
23379 offsetT value
= * valP
;
23381 unsigned int newimm
;
23382 unsigned long temp
;
23384 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23386 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23388 /* Note whether this will delete the relocation. */
23390 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23393 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23394 consistency with the behaviour on 32-bit hosts. Remember value
23396 value
&= 0xffffffff;
23397 value
^= 0x80000000;
23398 value
-= 0x80000000;
23401 fixP
->fx_addnumber
= value
;
23403 /* Same treatment for fixP->fx_offset. */
23404 fixP
->fx_offset
&= 0xffffffff;
23405 fixP
->fx_offset
^= 0x80000000;
23406 fixP
->fx_offset
-= 0x80000000;
23408 switch (fixP
->fx_r_type
)
23410 case BFD_RELOC_NONE
:
23411 /* This will need to go in the object file. */
23415 case BFD_RELOC_ARM_IMMEDIATE
:
23416 /* We claim that this fixup has been processed here,
23417 even if in fact we generate an error because we do
23418 not have a reloc for it, so tc_gen_reloc will reject it. */
23421 if (fixP
->fx_addsy
)
23423 const char *msg
= 0;
23425 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23426 msg
= _("undefined symbol %s used as an immediate value");
23427 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23428 msg
= _("symbol %s is in a different section");
23429 else if (S_IS_WEAK (fixP
->fx_addsy
))
23430 msg
= _("symbol %s is weak and may be overridden later");
23434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23435 msg
, S_GET_NAME (fixP
->fx_addsy
));
23440 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23442 /* If the offset is negative, we should use encoding A2 for ADR. */
23443 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23444 newimm
= negate_data_op (&temp
, value
);
23447 newimm
= encode_arm_immediate (value
);
23449 /* If the instruction will fail, see if we can fix things up by
23450 changing the opcode. */
23451 if (newimm
== (unsigned int) FAIL
)
23452 newimm
= negate_data_op (&temp
, value
);
23453 /* MOV accepts both ARM modified immediate (A1 encoding) and
23454 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23455 When disassembling, MOV is preferred when there is no encoding
23457 if (newimm
== (unsigned int) FAIL
23458 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23459 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23460 && !((temp
>> SBIT_SHIFT
) & 0x1)
23461 && value
>= 0 && value
<= 0xffff)
23463 /* Clear bits[23:20] to change encoding from A1 to A2. */
23464 temp
&= 0xff0fffff;
23465 /* Encoding high 4bits imm. Code below will encode the remaining
23467 temp
|= (value
& 0x0000f000) << 4;
23468 newimm
= value
& 0x00000fff;
23472 if (newimm
== (unsigned int) FAIL
)
23474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23475 _("invalid constant (%lx) after fixup"),
23476 (unsigned long) value
);
23480 newimm
|= (temp
& 0xfffff000);
23481 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23484 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23486 unsigned int highpart
= 0;
23487 unsigned int newinsn
= 0xe1a00000; /* nop. */
23489 if (fixP
->fx_addsy
)
23491 const char *msg
= 0;
23493 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23494 msg
= _("undefined symbol %s used as an immediate value");
23495 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23496 msg
= _("symbol %s is in a different section");
23497 else if (S_IS_WEAK (fixP
->fx_addsy
))
23498 msg
= _("symbol %s is weak and may be overridden later");
23502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23503 msg
, S_GET_NAME (fixP
->fx_addsy
));
23508 newimm
= encode_arm_immediate (value
);
23509 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23511 /* If the instruction will fail, see if we can fix things up by
23512 changing the opcode. */
23513 if (newimm
== (unsigned int) FAIL
23514 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23516 /* No ? OK - try using two ADD instructions to generate
23518 newimm
= validate_immediate_twopart (value
, & highpart
);
23520 /* Yes - then make sure that the second instruction is
23522 if (newimm
!= (unsigned int) FAIL
)
23524 /* Still No ? Try using a negated value. */
23525 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23526 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23527 /* Otherwise - give up. */
23530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23531 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23536 /* Replace the first operand in the 2nd instruction (which
23537 is the PC) with the destination register. We have
23538 already added in the PC in the first instruction and we
23539 do not want to do it again. */
23540 newinsn
&= ~ 0xf0000;
23541 newinsn
|= ((newinsn
& 0x0f000) << 4);
23544 newimm
|= (temp
& 0xfffff000);
23545 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23547 highpart
|= (newinsn
& 0xfffff000);
23548 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23552 case BFD_RELOC_ARM_OFFSET_IMM
:
23553 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23555 /* Fall through. */
23557 case BFD_RELOC_ARM_LITERAL
:
23563 if (validate_offset_imm (value
, 0) == FAIL
)
23565 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23567 _("invalid literal constant: pool needs to be closer"));
23569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23570 _("bad immediate value for offset (%ld)"),
23575 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23577 newval
&= 0xfffff000;
23580 newval
&= 0xff7ff000;
23581 newval
|= value
| (sign
? INDEX_UP
: 0);
23583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23586 case BFD_RELOC_ARM_OFFSET_IMM8
:
23587 case BFD_RELOC_ARM_HWLITERAL
:
23593 if (validate_offset_imm (value
, 1) == FAIL
)
23595 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23597 _("invalid literal constant: pool needs to be closer"));
23599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23600 _("bad immediate value for 8-bit offset (%ld)"),
23605 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23607 newval
&= 0xfffff0f0;
23610 newval
&= 0xff7ff0f0;
23611 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23613 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23616 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23617 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23619 _("bad immediate value for offset (%ld)"), (long) value
);
23622 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23624 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23627 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23628 /* This is a complicated relocation used for all varieties of Thumb32
23629 load/store instruction with immediate offset:
23631 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23632 *4, optional writeback(W)
23633 (doubleword load/store)
23635 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23636 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23637 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23638 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23639 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23641 Uppercase letters indicate bits that are already encoded at
23642 this point. Lowercase letters are our problem. For the
23643 second block of instructions, the secondary opcode nybble
23644 (bits 8..11) is present, and bit 23 is zero, even if this is
23645 a PC-relative operation. */
23646 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23648 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23650 if ((newval
& 0xf0000000) == 0xe0000000)
23652 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23654 newval
|= (1 << 23);
23657 if (value
% 4 != 0)
23659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23660 _("offset not a multiple of 4"));
23666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23667 _("offset out of range"));
23672 else if ((newval
& 0x000f0000) == 0x000f0000)
23674 /* PC-relative, 12-bit offset. */
23676 newval
|= (1 << 23);
23681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23682 _("offset out of range"));
23687 else if ((newval
& 0x00000100) == 0x00000100)
23689 /* Writeback: 8-bit, +/- offset. */
23691 newval
|= (1 << 9);
23696 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23697 _("offset out of range"));
23702 else if ((newval
& 0x00000f00) == 0x00000e00)
23704 /* T-instruction: positive 8-bit offset. */
23705 if (value
< 0 || value
> 0xff)
23707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23708 _("offset out of range"));
23716 /* Positive 12-bit or negative 8-bit offset. */
23720 newval
|= (1 << 23);
23730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23731 _("offset out of range"));
23738 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23739 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23742 case BFD_RELOC_ARM_SHIFT_IMM
:
23743 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23744 if (((unsigned long) value
) > 32
23746 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23749 _("shift expression is too large"));
23754 /* Shifts of zero must be done as lsl. */
23756 else if (value
== 32)
23758 newval
&= 0xfffff07f;
23759 newval
|= (value
& 0x1f) << 7;
23760 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23763 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23764 case BFD_RELOC_ARM_T32_ADD_IMM
:
23765 case BFD_RELOC_ARM_T32_IMM12
:
23766 case BFD_RELOC_ARM_T32_ADD_PC12
:
23767 /* We claim that this fixup has been processed here,
23768 even if in fact we generate an error because we do
23769 not have a reloc for it, so tc_gen_reloc will reject it. */
23773 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23776 _("undefined symbol %s used as an immediate value"),
23777 S_GET_NAME (fixP
->fx_addsy
));
23781 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23783 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23786 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23787 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23788 Thumb2 modified immediate encoding (T2). */
23789 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23790 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23792 newimm
= encode_thumb32_immediate (value
);
23793 if (newimm
== (unsigned int) FAIL
)
23794 newimm
= thumb32_negate_data_op (&newval
, value
);
23796 if (newimm
== (unsigned int) FAIL
)
23798 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23800 /* Turn add/sum into addw/subw. */
23801 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23802 newval
= (newval
& 0xfeffffff) | 0x02000000;
23803 /* No flat 12-bit imm encoding for addsw/subsw. */
23804 if ((newval
& 0x00100000) == 0)
23806 /* 12 bit immediate for addw/subw. */
23810 newval
^= 0x00a00000;
23813 newimm
= (unsigned int) FAIL
;
23820 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23821 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23822 disassembling, MOV is preferred when there is no encoding
23824 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23825 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23826 but with the Rn field [19:16] set to 1111. */
23827 && (((newval
>> 16) & 0xf) == 0xf)
23828 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23829 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23830 && value
>= 0 && value
<= 0xffff)
23832 /* Toggle bit[25] to change encoding from T2 to T3. */
23834 /* Clear bits[19:16]. */
23835 newval
&= 0xfff0ffff;
23836 /* Encoding high 4bits imm. Code below will encode the
23837 remaining low 12bits. */
23838 newval
|= (value
& 0x0000f000) << 4;
23839 newimm
= value
& 0x00000fff;
23844 if (newimm
== (unsigned int)FAIL
)
23846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23847 _("invalid constant (%lx) after fixup"),
23848 (unsigned long) value
);
23852 newval
|= (newimm
& 0x800) << 15;
23853 newval
|= (newimm
& 0x700) << 4;
23854 newval
|= (newimm
& 0x0ff);
23856 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23857 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23860 case BFD_RELOC_ARM_SMC
:
23861 if (((unsigned long) value
) > 0xffff)
23862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23863 _("invalid smc expression"));
23864 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23865 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23866 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23869 case BFD_RELOC_ARM_HVC
:
23870 if (((unsigned long) value
) > 0xffff)
23871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23872 _("invalid hvc expression"));
23873 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23874 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23875 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23878 case BFD_RELOC_ARM_SWI
:
23879 if (fixP
->tc_fix_data
!= 0)
23881 if (((unsigned long) value
) > 0xff)
23882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23883 _("invalid swi expression"));
23884 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23886 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23890 if (((unsigned long) value
) > 0x00ffffff)
23891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23892 _("invalid swi expression"));
23893 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23895 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23899 case BFD_RELOC_ARM_MULTI
:
23900 if (((unsigned long) value
) > 0xffff)
23901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23902 _("invalid expression in load/store multiple"));
23903 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23904 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23908 case BFD_RELOC_ARM_PCREL_CALL
:
23910 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23912 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23913 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23914 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23915 /* Flip the bl to blx. This is a simple flip
23916 bit here because we generate PCREL_CALL for
23917 unconditional bls. */
23919 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23920 newval
= newval
| 0x10000000;
23921 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23927 goto arm_branch_common
;
23929 case BFD_RELOC_ARM_PCREL_JUMP
:
23930 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23932 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23933 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23934 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23936 /* This would map to a bl<cond>, b<cond>,
23937 b<always> to a Thumb function. We
23938 need to force a relocation for this particular
23940 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23943 /* Fall through. */
23945 case BFD_RELOC_ARM_PLT32
:
23947 case BFD_RELOC_ARM_PCREL_BRANCH
:
23949 goto arm_branch_common
;
23951 case BFD_RELOC_ARM_PCREL_BLX
:
23954 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23956 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23957 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23958 && ARM_IS_FUNC (fixP
->fx_addsy
))
23960 /* Flip the blx to a bl and warn. */
23961 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23962 newval
= 0xeb000000;
23963 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23964 _("blx to '%s' an ARM ISA state function changed to bl"),
23966 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23972 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23973 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23977 /* We are going to store value (shifted right by two) in the
23978 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23979 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23983 _("misaligned branch destination"));
23984 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23985 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23990 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23991 newval
|= (value
>> 2) & 0x00ffffff;
23992 /* Set the H bit on BLX instructions. */
23996 newval
|= 0x01000000;
23998 newval
&= ~0x01000000;
24000 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24004 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
24005 /* CBZ can only branch forward. */
24007 /* Attempts to use CBZ to branch to the next instruction
24008 (which, strictly speaking, are prohibited) will be turned into
24011 FIXME: It may be better to remove the instruction completely and
24012 perform relaxation. */
24015 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24016 newval
= 0xbf00; /* NOP encoding T1 */
24017 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24024 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24027 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
24028 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24033 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
24034 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
24035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24037 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24039 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24040 newval
|= (value
& 0x1ff) >> 1;
24041 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24045 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
24046 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
24047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24049 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24051 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24052 newval
|= (value
& 0xfff) >> 1;
24053 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24057 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24059 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24060 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24061 && ARM_IS_FUNC (fixP
->fx_addsy
)
24062 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24064 /* Force a relocation for a branch 20 bits wide. */
24067 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
24068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24069 _("conditional branch out of range"));
24071 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24074 addressT S
, J1
, J2
, lo
, hi
;
24076 S
= (value
& 0x00100000) >> 20;
24077 J2
= (value
& 0x00080000) >> 19;
24078 J1
= (value
& 0x00040000) >> 18;
24079 hi
= (value
& 0x0003f000) >> 12;
24080 lo
= (value
& 0x00000ffe) >> 1;
24082 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24083 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24084 newval
|= (S
<< 10) | hi
;
24085 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
24086 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24087 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24091 case BFD_RELOC_THUMB_PCREL_BLX
:
24092 /* If there is a blx from a thumb state function to
24093 another thumb function flip this to a bl and warn
24097 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24098 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24099 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24101 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24102 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24103 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
24105 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24106 newval
= newval
| 0x1000;
24107 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24108 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24113 goto thumb_bl_common
;
24115 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24116 /* A bl from Thumb state ISA to an internal ARM state function
24117 is converted to a blx. */
24119 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24120 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24121 && ARM_IS_FUNC (fixP
->fx_addsy
)
24122 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24124 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24125 newval
= newval
& ~0x1000;
24126 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
24127 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
24133 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24134 /* For a BLX instruction, make sure that the relocation is rounded up
24135 to a word boundary. This follows the semantics of the instruction
24136 which specifies that bit 1 of the target address will come from bit
24137 1 of the base address. */
24138 value
= (value
+ 3) & ~ 3;
24141 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
24142 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
24143 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24146 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
24148 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
24149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24150 else if ((value
& ~0x1ffffff)
24151 && ((value
& ~0x1ffffff) != ~0x1ffffff))
24152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24153 _("Thumb2 branch out of range"));
24156 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24157 encode_thumb2_b_bl_offset (buf
, value
);
24161 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24162 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
24163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24166 encode_thumb2_b_bl_offset (buf
, value
);
24171 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24176 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24177 md_number_to_chars (buf
, value
, 2);
24181 case BFD_RELOC_ARM_TLS_CALL
:
24182 case BFD_RELOC_ARM_THM_TLS_CALL
:
24183 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24184 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24185 case BFD_RELOC_ARM_TLS_GOTDESC
:
24186 case BFD_RELOC_ARM_TLS_GD32
:
24187 case BFD_RELOC_ARM_TLS_LE32
:
24188 case BFD_RELOC_ARM_TLS_IE32
:
24189 case BFD_RELOC_ARM_TLS_LDM32
:
24190 case BFD_RELOC_ARM_TLS_LDO32
:
24191 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24194 /* Same handling as above, but with the arm_fdpic guard. */
24195 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24196 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24197 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24200 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24205 _("Relocation supported only in FDPIC mode"));
24209 case BFD_RELOC_ARM_GOT32
:
24210 case BFD_RELOC_ARM_GOTOFF
:
24213 case BFD_RELOC_ARM_GOT_PREL
:
24214 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24215 md_number_to_chars (buf
, value
, 4);
24218 case BFD_RELOC_ARM_TARGET2
:
24219 /* TARGET2 is not partial-inplace, so we need to write the
24220 addend here for REL targets, because it won't be written out
24221 during reloc processing later. */
24222 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24223 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24226 /* Relocations for FDPIC. */
24227 case BFD_RELOC_ARM_GOTFUNCDESC
:
24228 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24229 case BFD_RELOC_ARM_FUNCDESC
:
24232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24233 md_number_to_chars (buf
, 0, 4);
24237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24238 _("Relocation supported only in FDPIC mode"));
24243 case BFD_RELOC_RVA
:
24245 case BFD_RELOC_ARM_TARGET1
:
24246 case BFD_RELOC_ARM_ROSEGREL32
:
24247 case BFD_RELOC_ARM_SBREL32
:
24248 case BFD_RELOC_32_PCREL
:
24250 case BFD_RELOC_32_SECREL
:
24252 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24254 /* For WinCE we only do this for pcrel fixups. */
24255 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24257 md_number_to_chars (buf
, value
, 4);
24261 case BFD_RELOC_ARM_PREL31
:
24262 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24264 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24265 if ((value
^ (value
>> 1)) & 0x40000000)
24267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24268 _("rel31 relocation overflow"));
24270 newval
|= value
& 0x7fffffff;
24271 md_number_to_chars (buf
, newval
, 4);
24276 case BFD_RELOC_ARM_CP_OFF_IMM
:
24277 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24278 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24279 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24281 newval
= get_thumb32_insn (buf
);
24282 if ((newval
& 0x0f200f00) == 0x0d000900)
24284 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24285 has permitted values that are multiples of 2, in the range 0
24287 if (value
< -510 || value
> 510 || (value
& 1))
24288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24289 _("co-processor offset out of range"));
24291 else if (value
< -1023 || value
> 1023 || (value
& 3))
24292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24293 _("co-processor offset out of range"));
24298 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24299 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24300 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24302 newval
= get_thumb32_insn (buf
);
24304 newval
&= 0xffffff00;
24307 newval
&= 0xff7fff00;
24308 if ((newval
& 0x0f200f00) == 0x0d000900)
24310 /* This is a fp16 vstr/vldr.
24312 It requires the immediate offset in the instruction is shifted
24313 left by 1 to be a half-word offset.
24315 Here, left shift by 1 first, and later right shift by 2
24316 should get the right offset. */
24319 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24321 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24322 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24323 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24325 put_thumb32_insn (buf
, newval
);
24328 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24329 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24330 if (value
< -255 || value
> 255)
24331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24332 _("co-processor offset out of range"));
24334 goto cp_off_common
;
24336 case BFD_RELOC_ARM_THUMB_OFFSET
:
24337 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24338 /* Exactly what ranges, and where the offset is inserted depends
24339 on the type of instruction, we can establish this from the
24341 switch (newval
>> 12)
24343 case 4: /* PC load. */
24344 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24345 forced to zero for these loads; md_pcrel_from has already
24346 compensated for this. */
24348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24349 _("invalid offset, target not word aligned (0x%08lX)"),
24350 (((unsigned long) fixP
->fx_frag
->fr_address
24351 + (unsigned long) fixP
->fx_where
) & ~3)
24352 + (unsigned long) value
);
24354 if (value
& ~0x3fc)
24355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24356 _("invalid offset, value too big (0x%08lX)"),
24359 newval
|= value
>> 2;
24362 case 9: /* SP load/store. */
24363 if (value
& ~0x3fc)
24364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24365 _("invalid offset, value too big (0x%08lX)"),
24367 newval
|= value
>> 2;
24370 case 6: /* Word load/store. */
24372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24373 _("invalid offset, value too big (0x%08lX)"),
24375 newval
|= value
<< 4; /* 6 - 2. */
24378 case 7: /* Byte load/store. */
24380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24381 _("invalid offset, value too big (0x%08lX)"),
24383 newval
|= value
<< 6;
24386 case 8: /* Halfword load/store. */
24388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24389 _("invalid offset, value too big (0x%08lX)"),
24391 newval
|= value
<< 5; /* 6 - 1. */
24395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24396 "Unable to process relocation for thumb opcode: %lx",
24397 (unsigned long) newval
);
24400 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24403 case BFD_RELOC_ARM_THUMB_ADD
:
24404 /* This is a complicated relocation, since we use it for all of
24405 the following immediate relocations:
24409 9bit ADD/SUB SP word-aligned
24410 10bit ADD PC/SP word-aligned
24412 The type of instruction being processed is encoded in the
24419 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24421 int rd
= (newval
>> 4) & 0xf;
24422 int rs
= newval
& 0xf;
24423 int subtract
= !!(newval
& 0x8000);
24425 /* Check for HI regs, only very restricted cases allowed:
24426 Adjusting SP, and using PC or SP to get an address. */
24427 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24428 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24430 _("invalid Hi register with immediate"));
24432 /* If value is negative, choose the opposite instruction. */
24436 subtract
= !subtract
;
24438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24439 _("immediate value out of range"));
24444 if (value
& ~0x1fc)
24445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24446 _("invalid immediate for stack address calculation"));
24447 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24448 newval
|= value
>> 2;
24450 else if (rs
== REG_PC
|| rs
== REG_SP
)
24452 /* PR gas/18541. If the addition is for a defined symbol
24453 within range of an ADR instruction then accept it. */
24456 && fixP
->fx_addsy
!= NULL
)
24460 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24461 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24462 || S_IS_WEAK (fixP
->fx_addsy
))
24464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24465 _("address calculation needs a strongly defined nearby symbol"));
24469 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24471 /* Round up to the next 4-byte boundary. */
24476 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24481 _("symbol too far away"));
24491 if (subtract
|| value
& ~0x3fc)
24492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24493 _("invalid immediate for address calculation (value = 0x%08lX)"),
24494 (unsigned long) (subtract
? - value
: value
));
24495 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24497 newval
|= value
>> 2;
24502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24503 _("immediate value out of range"));
24504 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24505 newval
|= (rd
<< 8) | value
;
24510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24511 _("immediate value out of range"));
24512 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24513 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24516 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24519 case BFD_RELOC_ARM_THUMB_IMM
:
24520 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24521 if (value
< 0 || value
> 255)
24522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24523 _("invalid immediate: %ld is out of range"),
24526 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24529 case BFD_RELOC_ARM_THUMB_SHIFT
:
24530 /* 5bit shift value (0..32). LSL cannot take 32. */
24531 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24532 temp
= newval
& 0xf800;
24533 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24535 _("invalid shift value: %ld"), (long) value
);
24536 /* Shifts of zero must be encoded as LSL. */
24538 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24539 /* Shifts of 32 are encoded as zero. */
24540 else if (value
== 32)
24542 newval
|= value
<< 6;
24543 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24546 case BFD_RELOC_VTABLE_INHERIT
:
24547 case BFD_RELOC_VTABLE_ENTRY
:
24551 case BFD_RELOC_ARM_MOVW
:
24552 case BFD_RELOC_ARM_MOVT
:
24553 case BFD_RELOC_ARM_THUMB_MOVW
:
24554 case BFD_RELOC_ARM_THUMB_MOVT
:
24555 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24557 /* REL format relocations are limited to a 16-bit addend. */
24558 if (!fixP
->fx_done
)
24560 if (value
< -0x8000 || value
> 0x7fff)
24561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24562 _("offset out of range"));
24564 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24565 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24570 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24571 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24573 newval
= get_thumb32_insn (buf
);
24574 newval
&= 0xfbf08f00;
24575 newval
|= (value
& 0xf000) << 4;
24576 newval
|= (value
& 0x0800) << 15;
24577 newval
|= (value
& 0x0700) << 4;
24578 newval
|= (value
& 0x00ff);
24579 put_thumb32_insn (buf
, newval
);
24583 newval
= md_chars_to_number (buf
, 4);
24584 newval
&= 0xfff0f000;
24585 newval
|= value
& 0x0fff;
24586 newval
|= (value
& 0xf000) << 4;
24587 md_number_to_chars (buf
, newval
, 4);
24592 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24593 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24594 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24595 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24596 gas_assert (!fixP
->fx_done
);
24599 bfd_boolean is_mov
;
24600 bfd_vma encoded_addend
= value
;
24602 /* Check that addend can be encoded in instruction. */
24603 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24605 _("the offset 0x%08lX is not representable"),
24606 (unsigned long) encoded_addend
);
24608 /* Extract the instruction. */
24609 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24610 is_mov
= (insn
& 0xf800) == 0x2000;
24615 if (!seg
->use_rela_p
)
24616 insn
|= encoded_addend
;
24622 /* Extract the instruction. */
24623 /* Encoding is the following
24628 /* The following conditions must be true :
24633 rd
= (insn
>> 4) & 0xf;
24635 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24637 _("Unable to process relocation for thumb opcode: %lx"),
24638 (unsigned long) insn
);
24640 /* Encode as ADD immediate8 thumb 1 code. */
24641 insn
= 0x3000 | (rd
<< 8);
24643 /* Place the encoded addend into the first 8 bits of the
24645 if (!seg
->use_rela_p
)
24646 insn
|= encoded_addend
;
24649 /* Update the instruction. */
24650 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24654 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24655 case BFD_RELOC_ARM_ALU_PC_G0
:
24656 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24657 case BFD_RELOC_ARM_ALU_PC_G1
:
24658 case BFD_RELOC_ARM_ALU_PC_G2
:
24659 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24660 case BFD_RELOC_ARM_ALU_SB_G0
:
24661 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24662 case BFD_RELOC_ARM_ALU_SB_G1
:
24663 case BFD_RELOC_ARM_ALU_SB_G2
:
24664 gas_assert (!fixP
->fx_done
);
24665 if (!seg
->use_rela_p
)
24668 bfd_vma encoded_addend
;
24669 bfd_vma addend_abs
= llabs (value
);
24671 /* Check that the absolute value of the addend can be
24672 expressed as an 8-bit constant plus a rotation. */
24673 encoded_addend
= encode_arm_immediate (addend_abs
);
24674 if (encoded_addend
== (unsigned int) FAIL
)
24675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24676 _("the offset 0x%08lX is not representable"),
24677 (unsigned long) addend_abs
);
24679 /* Extract the instruction. */
24680 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24682 /* If the addend is positive, use an ADD instruction.
24683 Otherwise use a SUB. Take care not to destroy the S bit. */
24684 insn
&= 0xff1fffff;
24690 /* Place the encoded addend into the first 12 bits of the
24692 insn
&= 0xfffff000;
24693 insn
|= encoded_addend
;
24695 /* Update the instruction. */
24696 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24700 case BFD_RELOC_ARM_LDR_PC_G0
:
24701 case BFD_RELOC_ARM_LDR_PC_G1
:
24702 case BFD_RELOC_ARM_LDR_PC_G2
:
24703 case BFD_RELOC_ARM_LDR_SB_G0
:
24704 case BFD_RELOC_ARM_LDR_SB_G1
:
24705 case BFD_RELOC_ARM_LDR_SB_G2
:
24706 gas_assert (!fixP
->fx_done
);
24707 if (!seg
->use_rela_p
)
24710 bfd_vma addend_abs
= llabs (value
);
24712 /* Check that the absolute value of the addend can be
24713 encoded in 12 bits. */
24714 if (addend_abs
>= 0x1000)
24715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24716 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24717 (unsigned long) addend_abs
);
24719 /* Extract the instruction. */
24720 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24722 /* If the addend is negative, clear bit 23 of the instruction.
24723 Otherwise set it. */
24725 insn
&= ~(1 << 23);
24729 /* Place the absolute value of the addend into the first 12 bits
24730 of the instruction. */
24731 insn
&= 0xfffff000;
24732 insn
|= addend_abs
;
24734 /* Update the instruction. */
24735 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24739 case BFD_RELOC_ARM_LDRS_PC_G0
:
24740 case BFD_RELOC_ARM_LDRS_PC_G1
:
24741 case BFD_RELOC_ARM_LDRS_PC_G2
:
24742 case BFD_RELOC_ARM_LDRS_SB_G0
:
24743 case BFD_RELOC_ARM_LDRS_SB_G1
:
24744 case BFD_RELOC_ARM_LDRS_SB_G2
:
24745 gas_assert (!fixP
->fx_done
);
24746 if (!seg
->use_rela_p
)
24749 bfd_vma addend_abs
= llabs (value
);
24751 /* Check that the absolute value of the addend can be
24752 encoded in 8 bits. */
24753 if (addend_abs
>= 0x100)
24754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24755 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24756 (unsigned long) addend_abs
);
24758 /* Extract the instruction. */
24759 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24761 /* If the addend is negative, clear bit 23 of the instruction.
24762 Otherwise set it. */
24764 insn
&= ~(1 << 23);
24768 /* Place the first four bits of the absolute value of the addend
24769 into the first 4 bits of the instruction, and the remaining
24770 four into bits 8 .. 11. */
24771 insn
&= 0xfffff0f0;
24772 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24774 /* Update the instruction. */
24775 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24779 case BFD_RELOC_ARM_LDC_PC_G0
:
24780 case BFD_RELOC_ARM_LDC_PC_G1
:
24781 case BFD_RELOC_ARM_LDC_PC_G2
:
24782 case BFD_RELOC_ARM_LDC_SB_G0
:
24783 case BFD_RELOC_ARM_LDC_SB_G1
:
24784 case BFD_RELOC_ARM_LDC_SB_G2
:
24785 gas_assert (!fixP
->fx_done
);
24786 if (!seg
->use_rela_p
)
24789 bfd_vma addend_abs
= llabs (value
);
24791 /* Check that the absolute value of the addend is a multiple of
24792 four and, when divided by four, fits in 8 bits. */
24793 if (addend_abs
& 0x3)
24794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24795 _("bad offset 0x%08lX (must be word-aligned)"),
24796 (unsigned long) addend_abs
);
24798 if ((addend_abs
>> 2) > 0xff)
24799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24800 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24801 (unsigned long) addend_abs
);
24803 /* Extract the instruction. */
24804 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24806 /* If the addend is negative, clear bit 23 of the instruction.
24807 Otherwise set it. */
24809 insn
&= ~(1 << 23);
24813 /* Place the addend (divided by four) into the first eight
24814 bits of the instruction. */
24815 insn
&= 0xfffffff0;
24816 insn
|= addend_abs
>> 2;
24818 /* Update the instruction. */
24819 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24823 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24825 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24826 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24827 && ARM_IS_FUNC (fixP
->fx_addsy
)
24828 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24830 /* Force a relocation for a branch 5 bits wide. */
24833 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
24834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24837 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24839 addressT boff
= value
>> 1;
24841 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24842 newval
|= (boff
<< 7);
24843 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24847 case BFD_RELOC_ARM_THUMB_BF17
:
24849 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24850 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24851 && ARM_IS_FUNC (fixP
->fx_addsy
)
24852 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24854 /* Force a relocation for a branch 17 bits wide. */
24858 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
24859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24862 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24865 addressT immA
, immB
, immC
;
24867 immA
= (value
& 0x0001f000) >> 12;
24868 immB
= (value
& 0x00000ffc) >> 2;
24869 immC
= (value
& 0x00000002) >> 1;
24871 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24872 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24874 newval2
|= (immC
<< 11) | (immB
<< 1);
24875 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24876 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24880 case BFD_RELOC_ARM_THUMB_BF19
:
24882 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24883 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24884 && ARM_IS_FUNC (fixP
->fx_addsy
)
24885 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24887 /* Force a relocation for a branch 19 bits wide. */
24891 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
24892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24895 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24898 addressT immA
, immB
, immC
;
24900 immA
= (value
& 0x0007f000) >> 12;
24901 immB
= (value
& 0x00000ffc) >> 2;
24902 immC
= (value
& 0x00000002) >> 1;
24904 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24905 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24907 newval2
|= (immC
<< 11) | (immB
<< 1);
24908 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24909 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24913 case BFD_RELOC_ARM_THUMB_BF13
:
24915 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24916 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24917 && ARM_IS_FUNC (fixP
->fx_addsy
)
24918 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
24920 /* Force a relocation for a branch 13 bits wide. */
24924 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
24925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24928 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24931 addressT immA
, immB
, immC
;
24933 immA
= (value
& 0x00001000) >> 12;
24934 immB
= (value
& 0x00000ffc) >> 2;
24935 immC
= (value
& 0x00000002) >> 1;
24937 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24938 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24940 newval2
|= (immC
<< 11) | (immB
<< 1);
24941 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24942 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24946 case BFD_RELOC_ARM_V4BX
:
24947 /* This will need to go in the object file. */
24951 case BFD_RELOC_UNUSED
:
24953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24954 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24958 /* Translate internal representation of relocation info to BFD target
24962 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24965 bfd_reloc_code_real_type code
;
24967 reloc
= XNEW (arelent
);
24969 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24970 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24971 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24973 if (fixp
->fx_pcrel
)
24975 if (section
->use_rela_p
)
24976 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24978 fixp
->fx_offset
= reloc
->address
;
24980 reloc
->addend
= fixp
->fx_offset
;
24982 switch (fixp
->fx_r_type
)
24985 if (fixp
->fx_pcrel
)
24987 code
= BFD_RELOC_8_PCREL
;
24990 /* Fall through. */
24993 if (fixp
->fx_pcrel
)
24995 code
= BFD_RELOC_16_PCREL
;
24998 /* Fall through. */
25001 if (fixp
->fx_pcrel
)
25003 code
= BFD_RELOC_32_PCREL
;
25006 /* Fall through. */
25008 case BFD_RELOC_ARM_MOVW
:
25009 if (fixp
->fx_pcrel
)
25011 code
= BFD_RELOC_ARM_MOVW_PCREL
;
25014 /* Fall through. */
25016 case BFD_RELOC_ARM_MOVT
:
25017 if (fixp
->fx_pcrel
)
25019 code
= BFD_RELOC_ARM_MOVT_PCREL
;
25022 /* Fall through. */
25024 case BFD_RELOC_ARM_THUMB_MOVW
:
25025 if (fixp
->fx_pcrel
)
25027 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
25030 /* Fall through. */
25032 case BFD_RELOC_ARM_THUMB_MOVT
:
25033 if (fixp
->fx_pcrel
)
25035 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
25038 /* Fall through. */
25040 case BFD_RELOC_NONE
:
25041 case BFD_RELOC_ARM_PCREL_BRANCH
:
25042 case BFD_RELOC_ARM_PCREL_BLX
:
25043 case BFD_RELOC_RVA
:
25044 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25045 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25046 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25047 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25048 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25049 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25050 case BFD_RELOC_VTABLE_ENTRY
:
25051 case BFD_RELOC_VTABLE_INHERIT
:
25053 case BFD_RELOC_32_SECREL
:
25055 code
= fixp
->fx_r_type
;
25058 case BFD_RELOC_THUMB_PCREL_BLX
:
25060 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
25061 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25064 code
= BFD_RELOC_THUMB_PCREL_BLX
;
25067 case BFD_RELOC_ARM_LITERAL
:
25068 case BFD_RELOC_ARM_HWLITERAL
:
25069 /* If this is called then the a literal has
25070 been referenced across a section boundary. */
25071 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25072 _("literal referenced across section boundary"));
25076 case BFD_RELOC_ARM_TLS_CALL
:
25077 case BFD_RELOC_ARM_THM_TLS_CALL
:
25078 case BFD_RELOC_ARM_TLS_DESCSEQ
:
25079 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
25080 case BFD_RELOC_ARM_GOT32
:
25081 case BFD_RELOC_ARM_GOTOFF
:
25082 case BFD_RELOC_ARM_GOT_PREL
:
25083 case BFD_RELOC_ARM_PLT32
:
25084 case BFD_RELOC_ARM_TARGET1
:
25085 case BFD_RELOC_ARM_ROSEGREL32
:
25086 case BFD_RELOC_ARM_SBREL32
:
25087 case BFD_RELOC_ARM_PREL31
:
25088 case BFD_RELOC_ARM_TARGET2
:
25089 case BFD_RELOC_ARM_TLS_LDO32
:
25090 case BFD_RELOC_ARM_PCREL_CALL
:
25091 case BFD_RELOC_ARM_PCREL_JUMP
:
25092 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
25093 case BFD_RELOC_ARM_ALU_PC_G0
:
25094 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
25095 case BFD_RELOC_ARM_ALU_PC_G1
:
25096 case BFD_RELOC_ARM_ALU_PC_G2
:
25097 case BFD_RELOC_ARM_LDR_PC_G0
:
25098 case BFD_RELOC_ARM_LDR_PC_G1
:
25099 case BFD_RELOC_ARM_LDR_PC_G2
:
25100 case BFD_RELOC_ARM_LDRS_PC_G0
:
25101 case BFD_RELOC_ARM_LDRS_PC_G1
:
25102 case BFD_RELOC_ARM_LDRS_PC_G2
:
25103 case BFD_RELOC_ARM_LDC_PC_G0
:
25104 case BFD_RELOC_ARM_LDC_PC_G1
:
25105 case BFD_RELOC_ARM_LDC_PC_G2
:
25106 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
25107 case BFD_RELOC_ARM_ALU_SB_G0
:
25108 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
25109 case BFD_RELOC_ARM_ALU_SB_G1
:
25110 case BFD_RELOC_ARM_ALU_SB_G2
:
25111 case BFD_RELOC_ARM_LDR_SB_G0
:
25112 case BFD_RELOC_ARM_LDR_SB_G1
:
25113 case BFD_RELOC_ARM_LDR_SB_G2
:
25114 case BFD_RELOC_ARM_LDRS_SB_G0
:
25115 case BFD_RELOC_ARM_LDRS_SB_G1
:
25116 case BFD_RELOC_ARM_LDRS_SB_G2
:
25117 case BFD_RELOC_ARM_LDC_SB_G0
:
25118 case BFD_RELOC_ARM_LDC_SB_G1
:
25119 case BFD_RELOC_ARM_LDC_SB_G2
:
25120 case BFD_RELOC_ARM_V4BX
:
25121 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
25122 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
25123 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
25124 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
25125 case BFD_RELOC_ARM_GOTFUNCDESC
:
25126 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
25127 case BFD_RELOC_ARM_FUNCDESC
:
25128 case BFD_RELOC_ARM_THUMB_BF17
:
25129 case BFD_RELOC_ARM_THUMB_BF19
:
25130 case BFD_RELOC_ARM_THUMB_BF13
:
25131 code
= fixp
->fx_r_type
;
25134 case BFD_RELOC_ARM_TLS_GOTDESC
:
25135 case BFD_RELOC_ARM_TLS_GD32
:
25136 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
25137 case BFD_RELOC_ARM_TLS_LE32
:
25138 case BFD_RELOC_ARM_TLS_IE32
:
25139 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
25140 case BFD_RELOC_ARM_TLS_LDM32
:
25141 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
25142 /* BFD will include the symbol's address in the addend.
25143 But we don't want that, so subtract it out again here. */
25144 if (!S_IS_COMMON (fixp
->fx_addsy
))
25145 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
25146 code
= fixp
->fx_r_type
;
25150 case BFD_RELOC_ARM_IMMEDIATE
:
25151 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25152 _("internal relocation (type: IMMEDIATE) not fixed up"));
25155 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25157 _("ADRL used for a symbol not defined in the same file"));
25160 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25161 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25162 _("%s used for a symbol not defined in the same file"),
25163 bfd_get_reloc_code_name (fixp
->fx_r_type
));
25166 case BFD_RELOC_ARM_OFFSET_IMM
:
25167 if (section
->use_rela_p
)
25169 code
= fixp
->fx_r_type
;
25173 if (fixp
->fx_addsy
!= NULL
25174 && !S_IS_DEFINED (fixp
->fx_addsy
)
25175 && S_IS_LOCAL (fixp
->fx_addsy
))
25177 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25178 _("undefined local label `%s'"),
25179 S_GET_NAME (fixp
->fx_addsy
));
25183 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25184 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
25191 switch (fixp
->fx_r_type
)
25193 case BFD_RELOC_NONE
: type
= "NONE"; break;
25194 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
25195 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
25196 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
25197 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
25198 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
25199 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
25200 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
25201 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
25202 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
25203 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
25204 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
25205 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
25206 default: type
= _("<unknown>"); break;
25208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25209 _("cannot represent %s relocation in this object file format"),
25216 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
25218 && fixp
->fx_addsy
== GOT_symbol
)
25220 code
= BFD_RELOC_ARM_GOTPC
;
25221 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
25225 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
25227 if (reloc
->howto
== NULL
)
25229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
25230 _("cannot represent %s relocation in this object file format"),
25231 bfd_get_reloc_code_name (code
));
25235 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
25236 vtable entry to be used in the relocation's section offset. */
25237 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25238 reloc
->address
= fixp
->fx_offset
;
25243 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
25246 cons_fix_new_arm (fragS
* frag
,
25250 bfd_reloc_code_real_type reloc
)
25255 FIXME: @@ Should look at CPU word size. */
25259 reloc
= BFD_RELOC_8
;
25262 reloc
= BFD_RELOC_16
;
25266 reloc
= BFD_RELOC_32
;
25269 reloc
= BFD_RELOC_64
;
25274 if (exp
->X_op
== O_secrel
)
25276 exp
->X_op
= O_symbol
;
25277 reloc
= BFD_RELOC_32_SECREL
;
25281 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
25284 #if defined (OBJ_COFF)
25286 arm_validate_fix (fixS
* fixP
)
25288 /* If the destination of the branch is a defined symbol which does not have
25289 the THUMB_FUNC attribute, then we must be calling a function which has
25290 the (interfacearm) attribute. We look for the Thumb entry point to that
25291 function and change the branch to refer to that function instead. */
25292 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
25293 && fixP
->fx_addsy
!= NULL
25294 && S_IS_DEFINED (fixP
->fx_addsy
)
25295 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
25297 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
25304 arm_force_relocation (struct fix
* fixp
)
25306 #if defined (OBJ_COFF) && defined (TE_PE)
25307 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
25311 /* In case we have a call or a branch to a function in ARM ISA mode from
25312 a thumb function or vice-versa force the relocation. These relocations
25313 are cleared off for some cores that might have blx and simple transformations
25317 switch (fixp
->fx_r_type
)
25319 case BFD_RELOC_ARM_PCREL_JUMP
:
25320 case BFD_RELOC_ARM_PCREL_CALL
:
25321 case BFD_RELOC_THUMB_PCREL_BLX
:
25322 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25326 case BFD_RELOC_ARM_PCREL_BLX
:
25327 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25328 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25329 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25330 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25339 /* Resolve these relocations even if the symbol is extern or weak.
25340 Technically this is probably wrong due to symbol preemption.
25341 In practice these relocations do not have enough range to be useful
25342 at dynamic link time, and some code (e.g. in the Linux kernel)
25343 expects these references to be resolved. */
25344 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25345 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25346 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25347 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25348 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25349 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25350 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25351 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25352 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25353 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25354 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25355 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25356 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25357 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25360 /* Always leave these relocations for the linker. */
25361 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25362 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25363 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25366 /* Always generate relocations against function symbols. */
25367 if (fixp
->fx_r_type
== BFD_RELOC_32
25369 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25372 return generic_force_reloc (fixp
);
25375 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25376 /* Relocations against function names must be left unadjusted,
25377 so that the linker can use this information to generate interworking
25378 stubs. The MIPS version of this function
25379 also prevents relocations that are mips-16 specific, but I do not
25380 know why it does this.
25383 There is one other problem that ought to be addressed here, but
25384 which currently is not: Taking the address of a label (rather
25385 than a function) and then later jumping to that address. Such
25386 addresses also ought to have their bottom bit set (assuming that
25387 they reside in Thumb code), but at the moment they will not. */
25390 arm_fix_adjustable (fixS
* fixP
)
25392 if (fixP
->fx_addsy
== NULL
)
25395 /* Preserve relocations against symbols with function type. */
25396 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25399 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25400 && fixP
->fx_subsy
== NULL
)
25403 /* We need the symbol name for the VTABLE entries. */
25404 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25405 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25408 /* Don't allow symbols to be discarded on GOT related relocs. */
25409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25410 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25411 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25412 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25413 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25414 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25415 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25416 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25417 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25418 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25419 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25420 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25421 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25422 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25423 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25424 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25425 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25428 /* Similarly for group relocations. */
25429 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25430 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25431 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25434 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25435 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25436 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25437 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25438 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25439 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25440 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25441 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25442 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25445 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25446 offsets, so keep these symbols. */
25447 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25448 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25453 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25457 elf32_arm_target_format (void)
25460 return (target_big_endian
25461 ? "elf32-bigarm-symbian"
25462 : "elf32-littlearm-symbian");
25463 #elif defined (TE_VXWORKS)
25464 return (target_big_endian
25465 ? "elf32-bigarm-vxworks"
25466 : "elf32-littlearm-vxworks");
25467 #elif defined (TE_NACL)
25468 return (target_big_endian
25469 ? "elf32-bigarm-nacl"
25470 : "elf32-littlearm-nacl");
25474 if (target_big_endian
)
25475 return "elf32-bigarm-fdpic";
25477 return "elf32-littlearm-fdpic";
25481 if (target_big_endian
)
25482 return "elf32-bigarm";
25484 return "elf32-littlearm";
25490 armelf_frob_symbol (symbolS
* symp
,
25493 elf_frob_symbol (symp
, puntp
);
25497 /* MD interface: Finalization. */
25502 literal_pool
* pool
;
25504 /* Ensure that all the IT blocks are properly closed. */
25505 check_it_blocks_finished ();
25507 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25509 /* Put it at the end of the relevant section. */
25510 subseg_set (pool
->section
, pool
->sub_section
);
25512 arm_elf_change_section ();
25519 /* Remove any excess mapping symbols generated for alignment frags in
25520 SEC. We may have created a mapping symbol before a zero byte
25521 alignment; remove it if there's a mapping symbol after the
25524 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25525 void *dummy ATTRIBUTE_UNUSED
)
25527 segment_info_type
*seginfo
= seg_info (sec
);
25530 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25533 for (fragp
= seginfo
->frchainP
->frch_root
;
25535 fragp
= fragp
->fr_next
)
25537 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25538 fragS
*next
= fragp
->fr_next
;
25540 /* Variable-sized frags have been converted to fixed size by
25541 this point. But if this was variable-sized to start with,
25542 there will be a fixed-size frag after it. So don't handle
25544 if (sym
== NULL
|| next
== NULL
)
25547 if (S_GET_VALUE (sym
) < next
->fr_address
)
25548 /* Not at the end of this frag. */
25550 know (S_GET_VALUE (sym
) == next
->fr_address
);
25554 if (next
->tc_frag_data
.first_map
!= NULL
)
25556 /* Next frag starts with a mapping symbol. Discard this
25558 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25562 if (next
->fr_next
== NULL
)
25564 /* This mapping symbol is at the end of the section. Discard
25566 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25567 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25571 /* As long as we have empty frags without any mapping symbols,
25573 /* If the next frag is non-empty and does not start with a
25574 mapping symbol, then this mapping symbol is required. */
25575 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25578 next
= next
->fr_next
;
25580 while (next
!= NULL
);
25585 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25589 arm_adjust_symtab (void)
25594 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25596 if (ARM_IS_THUMB (sym
))
25598 if (THUMB_IS_FUNC (sym
))
25600 /* Mark the symbol as a Thumb function. */
25601 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25602 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25603 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25605 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25606 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25608 as_bad (_("%s: unexpected function type: %d"),
25609 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25611 else switch (S_GET_STORAGE_CLASS (sym
))
25614 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25617 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25620 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25628 if (ARM_IS_INTERWORK (sym
))
25629 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25636 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25638 if (ARM_IS_THUMB (sym
))
25640 elf_symbol_type
* elf_sym
;
25642 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25643 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25645 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25646 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25648 /* If it's a .thumb_func, declare it as so,
25649 otherwise tag label as .code 16. */
25650 if (THUMB_IS_FUNC (sym
))
25651 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25652 ST_BRANCH_TO_THUMB
);
25653 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25654 elf_sym
->internal_elf_sym
.st_info
=
25655 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25660 /* Remove any overlapping mapping symbols generated by alignment frags. */
25661 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25662 /* Now do generic ELF adjustments. */
25663 elf_adjust_symtab ();
25667 /* MD interface: Initialization. */
25670 set_constant_flonums (void)
25674 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25675 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25679 /* Auto-select Thumb mode if it's the only available instruction set for the
25680 given architecture. */
25683 autoselect_thumb_from_cpu_variant (void)
25685 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25686 opcode_select (16);
25695 if ( (arm_ops_hsh
= hash_new ()) == NULL
25696 || (arm_cond_hsh
= hash_new ()) == NULL
25697 || (arm_shift_hsh
= hash_new ()) == NULL
25698 || (arm_psr_hsh
= hash_new ()) == NULL
25699 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25700 || (arm_reg_hsh
= hash_new ()) == NULL
25701 || (arm_reloc_hsh
= hash_new ()) == NULL
25702 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25703 as_fatal (_("virtual memory exhausted"));
25705 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25706 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25707 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25708 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25709 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25710 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25711 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25712 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25713 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25714 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25715 (void *) (v7m_psrs
+ i
));
25716 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25717 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25719 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25721 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25722 (void *) (barrier_opt_names
+ i
));
25724 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25726 struct reloc_entry
* entry
= reloc_names
+ i
;
25728 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25729 /* This makes encode_branch() use the EABI versions of this relocation. */
25730 entry
->reloc
= BFD_RELOC_UNUSED
;
25732 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25736 set_constant_flonums ();
25738 /* Set the cpu variant based on the command-line options. We prefer
25739 -mcpu= over -march= if both are set (as for GCC); and we prefer
25740 -mfpu= over any other way of setting the floating point unit.
25741 Use of legacy options with new options are faulted. */
25744 if (mcpu_cpu_opt
|| march_cpu_opt
)
25745 as_bad (_("use of old and new-style options to set CPU type"));
25747 selected_arch
= *legacy_cpu
;
25749 else if (mcpu_cpu_opt
)
25751 selected_arch
= *mcpu_cpu_opt
;
25752 selected_ext
= *mcpu_ext_opt
;
25754 else if (march_cpu_opt
)
25756 selected_arch
= *march_cpu_opt
;
25757 selected_ext
= *march_ext_opt
;
25759 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25764 as_bad (_("use of old and new-style options to set FPU type"));
25766 selected_fpu
= *legacy_fpu
;
25769 selected_fpu
= *mfpu_opt
;
25772 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25773 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25774 /* Some environments specify a default FPU. If they don't, infer it
25775 from the processor. */
25777 selected_fpu
= *mcpu_fpu_opt
;
25778 else if (march_fpu_opt
)
25779 selected_fpu
= *march_fpu_opt
;
25781 selected_fpu
= fpu_default
;
25785 if (ARM_FEATURE_ZERO (selected_fpu
))
25787 if (!no_cpu_selected ())
25788 selected_fpu
= fpu_default
;
25790 selected_fpu
= fpu_arch_fpa
;
25794 if (ARM_FEATURE_ZERO (selected_arch
))
25796 selected_arch
= cpu_default
;
25797 selected_cpu
= selected_arch
;
25799 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25801 /* Autodection of feature mode: allow all features in cpu_variant but leave
25802 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25803 after all instruction have been processed and we can decide what CPU
25804 should be selected. */
25805 if (ARM_FEATURE_ZERO (selected_arch
))
25806 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25808 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25811 autoselect_thumb_from_cpu_variant ();
25813 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25815 #if defined OBJ_COFF || defined OBJ_ELF
25817 unsigned int flags
= 0;
25819 #if defined OBJ_ELF
25820 flags
= meabi_flags
;
25822 switch (meabi_flags
)
25824 case EF_ARM_EABI_UNKNOWN
:
25826 /* Set the flags in the private structure. */
25827 if (uses_apcs_26
) flags
|= F_APCS26
;
25828 if (support_interwork
) flags
|= F_INTERWORK
;
25829 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25830 if (pic_code
) flags
|= F_PIC
;
25831 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25832 flags
|= F_SOFT_FLOAT
;
25834 switch (mfloat_abi_opt
)
25836 case ARM_FLOAT_ABI_SOFT
:
25837 case ARM_FLOAT_ABI_SOFTFP
:
25838 flags
|= F_SOFT_FLOAT
;
25841 case ARM_FLOAT_ABI_HARD
:
25842 if (flags
& F_SOFT_FLOAT
)
25843 as_bad (_("hard-float conflicts with specified fpu"));
25847 /* Using pure-endian doubles (even if soft-float). */
25848 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25849 flags
|= F_VFP_FLOAT
;
25851 #if defined OBJ_ELF
25852 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25853 flags
|= EF_ARM_MAVERICK_FLOAT
;
25856 case EF_ARM_EABI_VER4
:
25857 case EF_ARM_EABI_VER5
:
25858 /* No additional flags to set. */
25865 bfd_set_private_flags (stdoutput
, flags
);
25867 /* We have run out flags in the COFF header to encode the
25868 status of ATPCS support, so instead we create a dummy,
25869 empty, debug section called .arm.atpcs. */
25874 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25878 bfd_set_section_flags
25879 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25880 bfd_set_section_size (stdoutput
, sec
, 0);
25881 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25887 /* Record the CPU type as well. */
25888 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25889 mach
= bfd_mach_arm_iWMMXt2
;
25890 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25891 mach
= bfd_mach_arm_iWMMXt
;
25892 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25893 mach
= bfd_mach_arm_XScale
;
25894 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25895 mach
= bfd_mach_arm_ep9312
;
25896 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25897 mach
= bfd_mach_arm_5TE
;
25898 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25900 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25901 mach
= bfd_mach_arm_5T
;
25903 mach
= bfd_mach_arm_5
;
25905 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25908 mach
= bfd_mach_arm_4T
;
25910 mach
= bfd_mach_arm_4
;
25912 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25913 mach
= bfd_mach_arm_3M
;
25914 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25915 mach
= bfd_mach_arm_3
;
25916 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25917 mach
= bfd_mach_arm_2a
;
25918 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25919 mach
= bfd_mach_arm_2
;
25921 mach
= bfd_mach_arm_unknown
;
25923 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25926 /* Command line processing. */
25929 Invocation line includes a switch not recognized by the base assembler.
25930 See if it's a processor-specific option.
25932 This routine is somewhat complicated by the need for backwards
25933 compatibility (since older releases of gcc can't be changed).
25934 The new options try to make the interface as compatible as
25937 New options (supported) are:
25939 -mcpu=<cpu name> Assemble for selected processor
25940 -march=<architecture name> Assemble for selected architecture
25941 -mfpu=<fpu architecture> Assemble for selected FPU.
25942 -EB/-mbig-endian Big-endian
25943 -EL/-mlittle-endian Little-endian
25944 -k Generate PIC code
25945 -mthumb Start in Thumb mode
25946 -mthumb-interwork Code supports ARM/Thumb interworking
25948 -m[no-]warn-deprecated Warn about deprecated features
25949 -m[no-]warn-syms Warn when symbols match instructions
25951 For now we will also provide support for:
25953 -mapcs-32 32-bit Program counter
25954 -mapcs-26 26-bit Program counter
25955 -macps-float Floats passed in FP registers
25956 -mapcs-reentrant Reentrant code
25958 (sometime these will probably be replaced with -mapcs=<list of options>
25959 and -matpcs=<list of options>)
25961 The remaining options are only supported for back-wards compatibility.
25962 Cpu variants, the arm part is optional:
25963 -m[arm]1 Currently not supported.
25964 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25965 -m[arm]3 Arm 3 processor
25966 -m[arm]6[xx], Arm 6 processors
25967 -m[arm]7[xx][t][[d]m] Arm 7 processors
25968 -m[arm]8[10] Arm 8 processors
25969 -m[arm]9[20][tdmi] Arm 9 processors
25970 -mstrongarm[110[0]] StrongARM processors
25971 -mxscale XScale processors
25972 -m[arm]v[2345[t[e]]] Arm architectures
25973 -mall All (except the ARM1)
25975 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25976 -mfpe-old (No float load/store multiples)
25977 -mvfpxd VFP Single precision
25979 -mno-fpu Disable all floating point instructions
25981 The following CPU names are recognized:
25982 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25983 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25984 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25985 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25986 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25987 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25988 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25992 const char * md_shortopts
= "m:k";
25994 #ifdef ARM_BI_ENDIAN
25995 #define OPTION_EB (OPTION_MD_BASE + 0)
25996 #define OPTION_EL (OPTION_MD_BASE + 1)
25998 #if TARGET_BYTES_BIG_ENDIAN
25999 #define OPTION_EB (OPTION_MD_BASE + 0)
26001 #define OPTION_EL (OPTION_MD_BASE + 1)
26004 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
26005 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
26007 struct option md_longopts
[] =
26010 {"EB", no_argument
, NULL
, OPTION_EB
},
26013 {"EL", no_argument
, NULL
, OPTION_EL
},
26015 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
26017 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
26019 {NULL
, no_argument
, NULL
, 0}
26022 size_t md_longopts_size
= sizeof (md_longopts
);
26024 struct arm_option_table
26026 const char * option
; /* Option name to match. */
26027 const char * help
; /* Help information. */
26028 int * var
; /* Variable to change. */
26029 int value
; /* What to change it to. */
26030 const char * deprecated
; /* If non-null, print this message. */
26033 struct arm_option_table arm_opts
[] =
26035 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
26036 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
26037 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
26038 &support_interwork
, 1, NULL
},
26039 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
26040 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
26041 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
26043 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
26044 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
26045 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
26046 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
26049 /* These are recognized by the assembler, but have no affect on code. */
26050 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
26051 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
26053 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
26054 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
26055 &warn_on_deprecated
, 0, NULL
},
26056 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
26057 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
26058 {NULL
, NULL
, NULL
, 0, NULL
}
26061 struct arm_legacy_option_table
26063 const char * option
; /* Option name to match. */
26064 const arm_feature_set
** var
; /* Variable to change. */
26065 const arm_feature_set value
; /* What to change it to. */
26066 const char * deprecated
; /* If non-null, print this message. */
26069 const struct arm_legacy_option_table arm_legacy_opts
[] =
26071 /* DON'T add any new processors to this list -- we want the whole list
26072 to go away... Add them to the processors table instead. */
26073 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26074 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
26075 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26076 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
26077 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26078 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
26079 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26080 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
26081 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26082 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
26083 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26084 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
26085 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26086 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
26087 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26088 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
26089 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26090 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
26091 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26092 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
26093 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26094 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
26095 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26096 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
26097 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26098 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
26099 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26100 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
26101 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26102 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
26103 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26104 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
26105 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26106 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
26107 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26108 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
26109 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26110 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
26111 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26112 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
26113 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26114 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
26115 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26116 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
26117 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26118 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
26119 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26120 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26121 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26122 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
26123 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26124 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
26125 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26126 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
26127 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26128 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
26129 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26130 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
26131 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26132 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
26133 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26134 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
26135 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26136 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
26137 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26138 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
26139 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26140 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
26141 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
26142 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
26143 N_("use -mcpu=strongarm110")},
26144 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
26145 N_("use -mcpu=strongarm1100")},
26146 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
26147 N_("use -mcpu=strongarm1110")},
26148 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
26149 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
26150 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
26152 /* Architecture variants -- don't add any more to this list either. */
26153 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26154 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
26155 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26156 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
26157 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26158 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
26159 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26160 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
26161 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26162 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
26163 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26164 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
26165 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26166 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
26167 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26168 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
26169 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26170 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
26172 /* Floating point variants -- don't add any more to this list either. */
26173 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
26174 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
26175 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
26176 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
26177 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
26179 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
26182 struct arm_cpu_option_table
26186 const arm_feature_set value
;
26187 const arm_feature_set ext
;
26188 /* For some CPUs we assume an FPU unless the user explicitly sets
26190 const arm_feature_set default_fpu
;
26191 /* The canonical name of the CPU, or NULL to use NAME converted to upper
26193 const char * canonical_name
;
26196 /* This list should, at a minimum, contain all the cpu names
26197 recognized by GCC. */
26198 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
26200 static const struct arm_cpu_option_table arm_cpus
[] =
26202 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
26205 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
26208 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
26211 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
26214 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
26217 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
26220 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
26223 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
26226 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
26229 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
26232 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
26235 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
26238 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
26241 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
26244 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
26247 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
26250 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
26253 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
26256 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
26259 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
26262 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
26265 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
26268 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
26271 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
26274 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
26277 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
26280 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
26283 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
26286 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
26289 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
26292 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
26295 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
26298 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
26301 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
26304 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
26307 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
26310 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
26313 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26316 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26319 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26322 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26325 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26328 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26331 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26334 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26337 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26341 /* For V5 or later processors we default to using VFP; but the user
26342 should really set the FPU type explicitly. */
26343 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26346 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26349 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26352 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26355 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26358 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26361 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26364 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26367 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26370 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26373 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26376 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26379 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26382 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26385 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26388 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26391 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26394 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26397 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26400 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26403 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26406 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26409 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26412 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26415 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26418 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26421 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26424 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26427 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26430 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26433 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26436 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26439 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26442 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26445 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26448 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26451 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26452 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26454 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26456 FPU_ARCH_NEON_VFP_V4
),
26457 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26458 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26459 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26460 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26461 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26462 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26463 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26465 FPU_ARCH_NEON_VFP_V4
),
26466 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26468 FPU_ARCH_NEON_VFP_V4
),
26469 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26471 FPU_ARCH_NEON_VFP_V4
),
26472 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26473 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26474 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26475 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26476 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26477 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26478 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26479 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26480 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26481 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26482 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26483 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26484 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26485 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26486 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26487 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26488 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26489 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26490 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26491 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26492 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26493 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26494 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26495 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26496 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26497 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26498 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26499 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
26500 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26501 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26502 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26505 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26507 FPU_ARCH_VFP_V3D16
),
26508 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26509 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26511 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26512 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26513 FPU_ARCH_VFP_V3D16
),
26514 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26515 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26516 FPU_ARCH_VFP_V3D16
),
26517 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26518 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26519 FPU_ARCH_NEON_VFP_ARMV8
),
26520 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26521 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26523 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26526 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26529 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26532 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26535 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26538 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26541 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26544 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26545 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26546 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26547 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
26548 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26549 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26550 /* ??? XSCALE is really an architecture. */
26551 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26555 /* ??? iwmmxt is not a processor. */
26556 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26559 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26562 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26567 ARM_CPU_OPT ("ep9312", "ARM920T",
26568 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26569 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26571 /* Marvell processors. */
26572 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26573 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26574 FPU_ARCH_VFP_V3D16
),
26575 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26576 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26577 FPU_ARCH_NEON_VFP_V4
),
26579 /* APM X-Gene family. */
26580 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26582 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26583 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26584 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26585 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26587 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26591 struct arm_ext_table
26595 const arm_feature_set merge
;
26596 const arm_feature_set clear
;
26599 struct arm_arch_option_table
26603 const arm_feature_set value
;
26604 const arm_feature_set default_fpu
;
26605 const struct arm_ext_table
* ext_table
;
26608 /* Used to add support for +E and +noE extension. */
26609 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
26610 /* Used to add support for a +E extension. */
26611 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
26612 /* Used to add support for a +noE extension. */
26613 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
26615 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
26616 ~0 & ~FPU_ENDIAN_PURE)
26618 static const struct arm_ext_table armv5te_ext_table
[] =
26620 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
26621 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26624 static const struct arm_ext_table armv7_ext_table
[] =
26626 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26627 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26630 static const struct arm_ext_table armv7ve_ext_table
[] =
26632 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
26633 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
26634 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26635 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26636 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26637 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
26638 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26640 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
26641 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26643 /* Aliases for +simd. */
26644 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26646 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26647 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26648 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26650 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26653 static const struct arm_ext_table armv7a_ext_table
[] =
26655 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26656 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26657 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
26658 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26659 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
26660 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
26661 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
26663 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
26664 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
26666 /* Aliases for +simd. */
26667 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26668 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
26670 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
26671 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
26673 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
26674 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
26675 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26678 static const struct arm_ext_table armv7r_ext_table
[] =
26680 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
26681 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
26682 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
26683 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
26684 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
26685 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
26686 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26687 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
26688 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26691 static const struct arm_ext_table armv7em_ext_table
[] =
26693 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
26694 /* Alias for +fp, used to be known as fpv4-sp-d16. */
26695 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
26696 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
26697 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26698 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
26699 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26702 static const struct arm_ext_table armv8a_ext_table
[] =
26704 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26705 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26706 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26707 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26709 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26710 should use the +simd option to turn on FP. */
26711 ARM_REMOVE ("fp", ALL_FP
),
26712 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26713 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26714 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26718 static const struct arm_ext_table armv81a_ext_table
[] =
26720 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26721 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26722 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26724 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26725 should use the +simd option to turn on FP. */
26726 ARM_REMOVE ("fp", ALL_FP
),
26727 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26728 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26729 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26732 static const struct arm_ext_table armv82a_ext_table
[] =
26734 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
26735 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
26736 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
26737 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
26738 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26739 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26741 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26742 should use the +simd option to turn on FP. */
26743 ARM_REMOVE ("fp", ALL_FP
),
26744 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26745 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26746 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26749 static const struct arm_ext_table armv84a_ext_table
[] =
26751 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26752 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26753 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26754 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26756 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26757 should use the +simd option to turn on FP. */
26758 ARM_REMOVE ("fp", ALL_FP
),
26759 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
26760 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
26761 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26764 static const struct arm_ext_table armv85a_ext_table
[] =
26766 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
26767 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
26768 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
26769 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26771 /* Armv8-a does not allow an FP implementation without SIMD, so the user
26772 should use the +simd option to turn on FP. */
26773 ARM_REMOVE ("fp", ALL_FP
),
26774 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26777 static const struct arm_ext_table armv8m_main_ext_table
[] =
26779 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26780 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26781 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
26782 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
26783 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26786 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
26788 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26789 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
26791 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26792 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
26795 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
26796 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
26797 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26800 static const struct arm_ext_table armv8r_ext_table
[] =
26802 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
26803 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
26804 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26805 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
26806 ARM_REMOVE ("fp", ALL_FP
),
26807 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
26808 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26811 /* This list should, at a minimum, contain all the architecture names
26812 recognized by GCC. */
26813 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
26814 #define ARM_ARCH_OPT2(N, V, DF, ext) \
26815 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
26817 static const struct arm_arch_option_table arm_archs
[] =
26819 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26820 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26821 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26822 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26823 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26824 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26825 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26826 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26827 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26828 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26829 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26830 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26831 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26832 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26833 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
26834 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
26835 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
26836 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26837 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
26838 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
26839 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
26840 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26841 kept to preserve existing behaviour. */
26842 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26843 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
26844 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
26845 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
26846 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
26847 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26848 kept to preserve existing behaviour. */
26849 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26850 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
26851 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26852 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26853 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
26854 /* The official spelling of the ARMv7 profile variants is the dashed form.
26855 Accept the non-dashed form for compatibility with old toolchains. */
26856 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26857 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
26858 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26859 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26860 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
26861 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
26862 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26863 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
26864 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26865 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
26867 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
26869 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
26870 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
26871 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
26872 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
26873 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
26874 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
26875 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
26876 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26877 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26878 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
26879 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26881 #undef ARM_ARCH_OPT
26883 /* ISA extensions in the co-processor and main instruction set space. */
26885 struct arm_option_extension_value_table
26889 const arm_feature_set merge_value
;
26890 const arm_feature_set clear_value
;
26891 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26892 indicates that an extension is available for all architectures while
26893 ARM_ANY marks an empty entry. */
26894 const arm_feature_set allowed_archs
[2];
26897 /* The following table must be in alphabetical order with a NULL last entry. */
26899 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26900 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26902 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
26903 use the context sensitive approach using arm_ext_table's. */
26904 static const struct arm_option_extension_value_table arm_extensions
[] =
26906 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26907 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26908 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26909 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26910 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26911 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26912 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26914 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26915 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26916 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26917 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26918 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26919 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26920 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26922 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26923 | ARM_EXT2_FP16_FML
),
26924 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26925 | ARM_EXT2_FP16_FML
),
26927 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26928 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26929 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26930 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26931 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26932 Thumb divide instruction. Due to this having the same name as the
26933 previous entry, this will be ignored when doing command-line parsing and
26934 only considered by build attribute selection code. */
26935 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26936 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26937 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26938 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26939 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26940 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26941 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26942 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26943 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26944 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26945 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26946 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26947 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26948 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26949 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26950 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26951 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26952 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26953 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26954 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26955 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
26957 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26958 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26959 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26960 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26961 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26962 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26963 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26964 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
26966 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26967 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26968 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26969 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26970 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26971 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26972 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26973 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26975 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26976 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26977 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26978 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26979 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26983 /* ISA floating-point and Advanced SIMD extensions. */
26984 struct arm_option_fpu_value_table
26987 const arm_feature_set value
;
26990 /* This list should, at a minimum, contain all the fpu names
26991 recognized by GCC. */
26992 static const struct arm_option_fpu_value_table arm_fpus
[] =
26994 {"softfpa", FPU_NONE
},
26995 {"fpe", FPU_ARCH_FPE
},
26996 {"fpe2", FPU_ARCH_FPE
},
26997 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26998 {"fpa", FPU_ARCH_FPA
},
26999 {"fpa10", FPU_ARCH_FPA
},
27000 {"fpa11", FPU_ARCH_FPA
},
27001 {"arm7500fe", FPU_ARCH_FPA
},
27002 {"softvfp", FPU_ARCH_VFP
},
27003 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
27004 {"vfp", FPU_ARCH_VFP_V2
},
27005 {"vfp9", FPU_ARCH_VFP_V2
},
27006 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
27007 {"vfp10", FPU_ARCH_VFP_V2
},
27008 {"vfp10-r0", FPU_ARCH_VFP_V1
},
27009 {"vfpxd", FPU_ARCH_VFP_V1xD
},
27010 {"vfpv2", FPU_ARCH_VFP_V2
},
27011 {"vfpv3", FPU_ARCH_VFP_V3
},
27012 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
27013 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
27014 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
27015 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
27016 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
27017 {"arm1020t", FPU_ARCH_VFP_V1
},
27018 {"arm1020e", FPU_ARCH_VFP_V2
},
27019 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
27020 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
27021 {"maverick", FPU_ARCH_MAVERICK
},
27022 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27023 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
27024 {"neon-fp16", FPU_ARCH_NEON_FP16
},
27025 {"vfpv4", FPU_ARCH_VFP_V4
},
27026 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
27027 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
27028 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
27029 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
27030 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
27031 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
27032 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
27033 {"crypto-neon-fp-armv8",
27034 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
27035 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
27036 {"crypto-neon-fp-armv8.1",
27037 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
27038 {NULL
, ARM_ARCH_NONE
}
27041 struct arm_option_value_table
27047 static const struct arm_option_value_table arm_float_abis
[] =
27049 {"hard", ARM_FLOAT_ABI_HARD
},
27050 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
27051 {"soft", ARM_FLOAT_ABI_SOFT
},
27056 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
27057 static const struct arm_option_value_table arm_eabis
[] =
27059 {"gnu", EF_ARM_EABI_UNKNOWN
},
27060 {"4", EF_ARM_EABI_VER4
},
27061 {"5", EF_ARM_EABI_VER5
},
27066 struct arm_long_option_table
27068 const char * option
; /* Substring to match. */
27069 const char * help
; /* Help information. */
27070 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
27071 const char * deprecated
; /* If non-null, print this message. */
27075 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
27076 arm_feature_set
*ext_set
,
27077 const struct arm_ext_table
*ext_table
)
27079 /* We insist on extensions being specified in alphabetical order, and with
27080 extensions being added before being removed. We achieve this by having
27081 the global ARM_EXTENSIONS table in alphabetical order, and using the
27082 ADDING_VALUE variable to indicate whether we are adding an extension (1)
27083 or removing it (0) and only allowing it to change in the order
27085 const struct arm_option_extension_value_table
* opt
= NULL
;
27086 const arm_feature_set arm_any
= ARM_ANY
;
27087 int adding_value
= -1;
27089 while (str
!= NULL
&& *str
!= 0)
27096 as_bad (_("invalid architectural extension"));
27101 ext
= strchr (str
, '+');
27106 len
= strlen (str
);
27108 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
27110 if (adding_value
!= 0)
27113 opt
= arm_extensions
;
27121 if (adding_value
== -1)
27124 opt
= arm_extensions
;
27126 else if (adding_value
!= 1)
27128 as_bad (_("must specify extensions to add before specifying "
27129 "those to remove"));
27136 as_bad (_("missing architectural extension"));
27140 gas_assert (adding_value
!= -1);
27141 gas_assert (opt
!= NULL
);
27143 if (ext_table
!= NULL
)
27145 const struct arm_ext_table
* ext_opt
= ext_table
;
27146 bfd_boolean found
= FALSE
;
27147 for (; ext_opt
->name
!= NULL
; ext_opt
++)
27148 if (ext_opt
->name_len
== len
27149 && strncmp (ext_opt
->name
, str
, len
) == 0)
27153 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
27154 /* TODO: Option not supported. When we remove the
27155 legacy table this case should error out. */
27158 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
27162 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
27163 /* TODO: Option not supported. When we remove the
27164 legacy table this case should error out. */
27166 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
27178 /* Scan over the options table trying to find an exact match. */
27179 for (; opt
->name
!= NULL
; opt
++)
27180 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27182 int i
, nb_allowed_archs
=
27183 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27184 /* Check we can apply the extension to this architecture. */
27185 for (i
= 0; i
< nb_allowed_archs
; i
++)
27188 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27190 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
27193 if (i
== nb_allowed_archs
)
27195 as_bad (_("extension does not apply to the base architecture"));
27199 /* Add or remove the extension. */
27201 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
27203 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
27205 /* Allowing Thumb division instructions for ARMv7 in autodetection
27206 rely on this break so that duplicate extensions (extensions
27207 with the same name as a previous extension in the list) are not
27208 considered for command-line parsing. */
27212 if (opt
->name
== NULL
)
27214 /* Did we fail to find an extension because it wasn't specified in
27215 alphabetical order, or because it does not exist? */
27217 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27218 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27221 if (opt
->name
== NULL
)
27222 as_bad (_("unknown architectural extension `%s'"), str
);
27224 as_bad (_("architectural extensions must be specified in "
27225 "alphabetical order"));
27231 /* We should skip the extension we've just matched the next time
27243 arm_parse_cpu (const char *str
)
27245 const struct arm_cpu_option_table
*opt
;
27246 const char *ext
= strchr (str
, '+');
27252 len
= strlen (str
);
27256 as_bad (_("missing cpu name `%s'"), str
);
27260 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
27261 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27263 mcpu_cpu_opt
= &opt
->value
;
27264 if (mcpu_ext_opt
== NULL
)
27265 mcpu_ext_opt
= XNEW (arm_feature_set
);
27266 *mcpu_ext_opt
= opt
->ext
;
27267 mcpu_fpu_opt
= &opt
->default_fpu
;
27268 if (opt
->canonical_name
)
27270 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
27271 strcpy (selected_cpu_name
, opt
->canonical_name
);
27277 if (len
>= sizeof selected_cpu_name
)
27278 len
= (sizeof selected_cpu_name
) - 1;
27280 for (i
= 0; i
< len
; i
++)
27281 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27282 selected_cpu_name
[i
] = 0;
27286 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
27291 as_bad (_("unknown cpu `%s'"), str
);
27296 arm_parse_arch (const char *str
)
27298 const struct arm_arch_option_table
*opt
;
27299 const char *ext
= strchr (str
, '+');
27305 len
= strlen (str
);
27309 as_bad (_("missing architecture name `%s'"), str
);
27313 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
27314 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
27316 march_cpu_opt
= &opt
->value
;
27317 if (march_ext_opt
== NULL
)
27318 march_ext_opt
= XNEW (arm_feature_set
);
27319 *march_ext_opt
= arm_arch_none
;
27320 march_fpu_opt
= &opt
->default_fpu
;
27321 strcpy (selected_cpu_name
, opt
->name
);
27324 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
27330 as_bad (_("unknown architecture `%s'\n"), str
);
27335 arm_parse_fpu (const char * str
)
27337 const struct arm_option_fpu_value_table
* opt
;
27339 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27340 if (streq (opt
->name
, str
))
27342 mfpu_opt
= &opt
->value
;
27346 as_bad (_("unknown floating point format `%s'\n"), str
);
27351 arm_parse_float_abi (const char * str
)
27353 const struct arm_option_value_table
* opt
;
27355 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
27356 if (streq (opt
->name
, str
))
27358 mfloat_abi_opt
= opt
->value
;
27362 as_bad (_("unknown floating point abi `%s'\n"), str
);
27368 arm_parse_eabi (const char * str
)
27370 const struct arm_option_value_table
*opt
;
27372 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
27373 if (streq (opt
->name
, str
))
27375 meabi_flags
= opt
->value
;
27378 as_bad (_("unknown EABI `%s'\n"), str
);
27384 arm_parse_it_mode (const char * str
)
27386 bfd_boolean ret
= TRUE
;
27388 if (streq ("arm", str
))
27389 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
27390 else if (streq ("thumb", str
))
27391 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
27392 else if (streq ("always", str
))
27393 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
27394 else if (streq ("never", str
))
27395 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
27398 as_bad (_("unknown implicit IT mode `%s', should be "\
27399 "arm, thumb, always, or never."), str
);
27407 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
27409 codecomposer_syntax
= TRUE
;
27410 arm_comment_chars
[0] = ';';
27411 arm_line_separator_chars
[0] = 0;
27415 struct arm_long_option_table arm_long_opts
[] =
27417 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
27418 arm_parse_cpu
, NULL
},
27419 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
27420 arm_parse_arch
, NULL
},
27421 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
27422 arm_parse_fpu
, NULL
},
27423 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
27424 arm_parse_float_abi
, NULL
},
27426 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
27427 arm_parse_eabi
, NULL
},
27429 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
27430 arm_parse_it_mode
, NULL
},
27431 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
27432 arm_ccs_mode
, NULL
},
27433 {NULL
, NULL
, 0, NULL
}
27437 md_parse_option (int c
, const char * arg
)
27439 struct arm_option_table
*opt
;
27440 const struct arm_legacy_option_table
*fopt
;
27441 struct arm_long_option_table
*lopt
;
27447 target_big_endian
= 1;
27453 target_big_endian
= 0;
27457 case OPTION_FIX_V4BX
:
27465 #endif /* OBJ_ELF */
27468 /* Listing option. Just ignore these, we don't support additional
27473 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27475 if (c
== opt
->option
[0]
27476 && ((arg
== NULL
&& opt
->option
[1] == 0)
27477 || streq (arg
, opt
->option
+ 1)))
27479 /* If the option is deprecated, tell the user. */
27480 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
27481 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27482 arg
? arg
: "", _(opt
->deprecated
));
27484 if (opt
->var
!= NULL
)
27485 *opt
->var
= opt
->value
;
27491 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
27493 if (c
== fopt
->option
[0]
27494 && ((arg
== NULL
&& fopt
->option
[1] == 0)
27495 || streq (arg
, fopt
->option
+ 1)))
27497 /* If the option is deprecated, tell the user. */
27498 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
27499 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
27500 arg
? arg
: "", _(fopt
->deprecated
));
27502 if (fopt
->var
!= NULL
)
27503 *fopt
->var
= &fopt
->value
;
27509 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27511 /* These options are expected to have an argument. */
27512 if (c
== lopt
->option
[0]
27514 && strncmp (arg
, lopt
->option
+ 1,
27515 strlen (lopt
->option
+ 1)) == 0)
27517 /* If the option is deprecated, tell the user. */
27518 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
27519 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
27520 _(lopt
->deprecated
));
27522 /* Call the sup-option parser. */
27523 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
27534 md_show_usage (FILE * fp
)
27536 struct arm_option_table
*opt
;
27537 struct arm_long_option_table
*lopt
;
27539 fprintf (fp
, _(" ARM-specific assembler options:\n"));
27541 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
27542 if (opt
->help
!= NULL
)
27543 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
27545 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
27546 if (lopt
->help
!= NULL
)
27547 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
27551 -EB assemble code for a big-endian cpu\n"));
27556 -EL assemble code for a little-endian cpu\n"));
27560 --fix-v4bx Allow BX in ARMv4 code\n"));
27564 --fdpic generate an FDPIC object file\n"));
27565 #endif /* OBJ_ELF */
27573 arm_feature_set flags
;
27574 } cpu_arch_ver_table
;
27576 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27577 chronologically for architectures, with an exception for ARMv6-M and
27578 ARMv6S-M due to legacy reasons. No new architecture should have a
27579 special case. This allows for build attribute selection results to be
27580 stable when new architectures are added. */
27581 static const cpu_arch_ver_table cpu_arch_ver
[] =
27583 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27584 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27585 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27586 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27587 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27588 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27589 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27590 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27591 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27592 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27593 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27594 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27595 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27596 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27597 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27598 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27599 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27600 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27601 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27602 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27603 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27604 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27605 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27606 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27608 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27609 always selected build attributes to match those of ARMv6-M
27610 (resp. ARMv6S-M). However, due to these architectures being a strict
27611 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27612 would be selected when fully respecting chronology of architectures.
27613 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27614 move them before ARMv7 architectures. */
27615 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27616 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27618 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27619 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27620 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27621 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27622 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27623 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27624 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27625 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27626 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27627 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27628 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27629 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27630 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27631 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27632 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
27633 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
27634 {-1, ARM_ARCH_NONE
}
27637 /* Set an attribute if it has not already been set by the user. */
27640 aeabi_set_attribute_int (int tag
, int value
)
27643 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27644 || !attributes_set_explicitly
[tag
])
27645 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27649 aeabi_set_attribute_string (int tag
, const char *value
)
27652 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27653 || !attributes_set_explicitly
[tag
])
27654 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27657 /* Return whether features in the *NEEDED feature set are available via
27658 extensions for the architecture whose feature set is *ARCH_FSET. */
27661 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27662 const arm_feature_set
*needed
)
27664 int i
, nb_allowed_archs
;
27665 arm_feature_set ext_fset
;
27666 const struct arm_option_extension_value_table
*opt
;
27668 ext_fset
= arm_arch_none
;
27669 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27671 /* Extension does not provide any feature we need. */
27672 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27676 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27677 for (i
= 0; i
< nb_allowed_archs
; i
++)
27680 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27683 /* Extension is available, add it. */
27684 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27685 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27689 /* Can we enable all features in *needed? */
27690 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27693 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27694 a given architecture feature set *ARCH_EXT_FSET including extension feature
27695 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27696 - if true, check for an exact match of the architecture modulo extensions;
27697 - otherwise, select build attribute value of the first superset
27698 architecture released so that results remains stable when new architectures
27700 For -march/-mcpu=all the build attribute value of the most featureful
27701 architecture is returned. Tag_CPU_arch_profile result is returned in
27705 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27706 const arm_feature_set
*ext_fset
,
27707 char *profile
, int exact_match
)
27709 arm_feature_set arch_fset
;
27710 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27712 /* Select most featureful architecture with all its extensions if building
27713 for -march=all as the feature sets used to set build attributes. */
27714 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27716 /* Force revisiting of decision for each new architecture. */
27717 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27719 return TAG_CPU_ARCH_V8
;
27722 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27724 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27726 arm_feature_set known_arch_fset
;
27728 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27731 /* Base architecture match user-specified architecture and
27732 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27733 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27738 /* Base architecture match user-specified architecture only
27739 (eg. ARMv6-M in the same case as above). Record it in case we
27740 find a match with above condition. */
27741 else if (p_ver_ret
== NULL
27742 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27748 /* Architecture has all features wanted. */
27749 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27751 arm_feature_set added_fset
;
27753 /* Compute features added by this architecture over the one
27754 recorded in p_ver_ret. */
27755 if (p_ver_ret
!= NULL
)
27756 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27758 /* First architecture that match incl. with extensions, or the
27759 only difference in features over the recorded match is
27760 features that were optional and are now mandatory. */
27761 if (p_ver_ret
== NULL
27762 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27768 else if (p_ver_ret
== NULL
)
27770 arm_feature_set needed_ext_fset
;
27772 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27774 /* Architecture has all features needed when using some
27775 extensions. Record it and continue searching in case there
27776 exist an architecture providing all needed features without
27777 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27779 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27786 if (p_ver_ret
== NULL
)
27790 /* Tag_CPU_arch_profile. */
27791 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27792 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27793 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27794 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27796 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27798 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27802 return p_ver_ret
->val
;
27805 /* Set the public EABI object attributes. */
27808 aeabi_set_public_attributes (void)
27810 char profile
= '\0';
27813 int fp16_optional
= 0;
27814 int skip_exact_match
= 0;
27815 arm_feature_set flags
, flags_arch
, flags_ext
;
27817 /* Autodetection mode, choose the architecture based the instructions
27819 if (no_cpu_selected ())
27821 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27823 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27824 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27826 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27827 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27829 /* Code run during relaxation relies on selected_cpu being set. */
27830 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27831 flags_ext
= arm_arch_none
;
27832 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27833 selected_ext
= flags_ext
;
27834 selected_cpu
= flags
;
27836 /* Otherwise, choose the architecture based on the capabilities of the
27840 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27841 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27842 flags_ext
= selected_ext
;
27843 flags
= selected_cpu
;
27845 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27847 /* Allow the user to override the reported architecture. */
27848 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27850 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27851 flags_ext
= arm_arch_none
;
27854 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27856 /* When this function is run again after relaxation has happened there is no
27857 way to determine whether an architecture or CPU was specified by the user:
27858 - selected_cpu is set above for relaxation to work;
27859 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27860 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27861 Therefore, if not in -march=all case we first try an exact match and fall
27862 back to autodetection. */
27863 if (!skip_exact_match
)
27864 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27866 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27868 as_bad (_("no architecture contains all the instructions used\n"));
27870 /* Tag_CPU_name. */
27871 if (selected_cpu_name
[0])
27875 q
= selected_cpu_name
;
27876 if (strncmp (q
, "armv", 4) == 0)
27881 for (i
= 0; q
[i
]; i
++)
27882 q
[i
] = TOUPPER (q
[i
]);
27884 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27887 /* Tag_CPU_arch. */
27888 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27890 /* Tag_CPU_arch_profile. */
27891 if (profile
!= '\0')
27892 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27894 /* Tag_DSP_extension. */
27895 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27896 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27898 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27899 /* Tag_ARM_ISA_use. */
27900 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27901 || ARM_FEATURE_ZERO (flags_arch
))
27902 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27904 /* Tag_THUMB_ISA_use. */
27905 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27906 || ARM_FEATURE_ZERO (flags_arch
))
27910 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27911 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27913 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27917 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27920 /* Tag_VFP_arch. */
27921 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27922 aeabi_set_attribute_int (Tag_VFP_arch
,
27923 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27925 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27926 aeabi_set_attribute_int (Tag_VFP_arch
,
27927 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27929 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27932 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27934 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27936 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27939 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27940 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27941 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27942 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27943 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27945 /* Tag_ABI_HardFP_use. */
27946 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27947 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27948 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27950 /* Tag_WMMX_arch. */
27951 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27952 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27953 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27954 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27956 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27957 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27958 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27959 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27960 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27961 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27963 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27965 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27969 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27974 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27975 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27976 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27980 We set Tag_DIV_use to two when integer divide instructions have been used
27981 in ARM state, or when Thumb integer divide instructions have been used,
27982 but we have no architecture profile set, nor have we any ARM instructions.
27984 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27985 by the base architecture.
27987 For new architectures we will have to check these tests. */
27988 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
27989 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27990 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27991 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27992 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27993 || (profile
== '\0'
27994 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27995 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27996 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27998 /* Tag_MP_extension_use. */
27999 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
28000 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
28002 /* Tag Virtualization_use. */
28003 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
28005 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
28008 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
28011 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
28012 finished and free extension feature bits which will not be used anymore. */
28015 arm_md_post_relax (void)
28017 aeabi_set_public_attributes ();
28018 XDELETE (mcpu_ext_opt
);
28019 mcpu_ext_opt
= NULL
;
28020 XDELETE (march_ext_opt
);
28021 march_ext_opt
= NULL
;
28024 /* Add the default contents for the .ARM.attributes section. */
28029 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28032 aeabi_set_public_attributes ();
28034 #endif /* OBJ_ELF */
28036 /* Parse a .cpu directive. */
28039 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
28041 const struct arm_cpu_option_table
*opt
;
28045 name
= input_line_pointer
;
28046 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28047 input_line_pointer
++;
28048 saved_char
= *input_line_pointer
;
28049 *input_line_pointer
= 0;
28051 /* Skip the first "all" entry. */
28052 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
28053 if (streq (opt
->name
, name
))
28055 selected_arch
= opt
->value
;
28056 selected_ext
= opt
->ext
;
28057 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28058 if (opt
->canonical_name
)
28059 strcpy (selected_cpu_name
, opt
->canonical_name
);
28063 for (i
= 0; opt
->name
[i
]; i
++)
28064 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
28066 selected_cpu_name
[i
] = 0;
28068 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28070 *input_line_pointer
= saved_char
;
28071 demand_empty_rest_of_line ();
28074 as_bad (_("unknown cpu `%s'"), name
);
28075 *input_line_pointer
= saved_char
;
28076 ignore_rest_of_line ();
28079 /* Parse a .arch directive. */
28082 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
28084 const struct arm_arch_option_table
*opt
;
28088 name
= input_line_pointer
;
28089 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28090 input_line_pointer
++;
28091 saved_char
= *input_line_pointer
;
28092 *input_line_pointer
= 0;
28094 /* Skip the first "all" entry. */
28095 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28096 if (streq (opt
->name
, name
))
28098 selected_arch
= opt
->value
;
28099 selected_ext
= arm_arch_none
;
28100 selected_cpu
= selected_arch
;
28101 strcpy (selected_cpu_name
, opt
->name
);
28102 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28103 *input_line_pointer
= saved_char
;
28104 demand_empty_rest_of_line ();
28108 as_bad (_("unknown architecture `%s'\n"), name
);
28109 *input_line_pointer
= saved_char
;
28110 ignore_rest_of_line ();
28113 /* Parse a .object_arch directive. */
28116 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
28118 const struct arm_arch_option_table
*opt
;
28122 name
= input_line_pointer
;
28123 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28124 input_line_pointer
++;
28125 saved_char
= *input_line_pointer
;
28126 *input_line_pointer
= 0;
28128 /* Skip the first "all" entry. */
28129 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
28130 if (streq (opt
->name
, name
))
28132 selected_object_arch
= opt
->value
;
28133 *input_line_pointer
= saved_char
;
28134 demand_empty_rest_of_line ();
28138 as_bad (_("unknown architecture `%s'\n"), name
);
28139 *input_line_pointer
= saved_char
;
28140 ignore_rest_of_line ();
28143 /* Parse a .arch_extension directive. */
28146 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
28148 const struct arm_option_extension_value_table
*opt
;
28151 int adding_value
= 1;
28153 name
= input_line_pointer
;
28154 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28155 input_line_pointer
++;
28156 saved_char
= *input_line_pointer
;
28157 *input_line_pointer
= 0;
28159 if (strlen (name
) >= 2
28160 && strncmp (name
, "no", 2) == 0)
28166 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28167 if (streq (opt
->name
, name
))
28169 int i
, nb_allowed_archs
=
28170 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
28171 for (i
= 0; i
< nb_allowed_archs
; i
++)
28174 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
28176 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
28180 if (i
== nb_allowed_archs
)
28182 as_bad (_("architectural extension `%s' is not allowed for the "
28183 "current base architecture"), name
);
28188 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
28191 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
28193 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28194 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28195 *input_line_pointer
= saved_char
;
28196 demand_empty_rest_of_line ();
28197 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
28198 on this return so that duplicate extensions (extensions with the
28199 same name as a previous extension in the list) are not considered
28200 for command-line parsing. */
28204 if (opt
->name
== NULL
)
28205 as_bad (_("unknown architecture extension `%s'\n"), name
);
28207 *input_line_pointer
= saved_char
;
28208 ignore_rest_of_line ();
28211 /* Parse a .fpu directive. */
28214 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
28216 const struct arm_option_fpu_value_table
*opt
;
28220 name
= input_line_pointer
;
28221 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
28222 input_line_pointer
++;
28223 saved_char
= *input_line_pointer
;
28224 *input_line_pointer
= 0;
28226 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
28227 if (streq (opt
->name
, name
))
28229 selected_fpu
= opt
->value
;
28230 #ifndef CPU_DEFAULT
28231 if (no_cpu_selected ())
28232 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28235 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28236 *input_line_pointer
= saved_char
;
28237 demand_empty_rest_of_line ();
28241 as_bad (_("unknown floating point format `%s'\n"), name
);
28242 *input_line_pointer
= saved_char
;
28243 ignore_rest_of_line ();
28246 /* Copy symbol information. */
28249 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
28251 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
28255 /* Given a symbolic attribute NAME, return the proper integer value.
28256 Returns -1 if the attribute is not known. */
28259 arm_convert_symbolic_attribute (const char *name
)
28261 static const struct
28266 attribute_table
[] =
28268 /* When you modify this table you should
28269 also modify the list in doc/c-arm.texi. */
28270 #define T(tag) {#tag, tag}
28271 T (Tag_CPU_raw_name
),
28274 T (Tag_CPU_arch_profile
),
28275 T (Tag_ARM_ISA_use
),
28276 T (Tag_THUMB_ISA_use
),
28280 T (Tag_Advanced_SIMD_arch
),
28281 T (Tag_PCS_config
),
28282 T (Tag_ABI_PCS_R9_use
),
28283 T (Tag_ABI_PCS_RW_data
),
28284 T (Tag_ABI_PCS_RO_data
),
28285 T (Tag_ABI_PCS_GOT_use
),
28286 T (Tag_ABI_PCS_wchar_t
),
28287 T (Tag_ABI_FP_rounding
),
28288 T (Tag_ABI_FP_denormal
),
28289 T (Tag_ABI_FP_exceptions
),
28290 T (Tag_ABI_FP_user_exceptions
),
28291 T (Tag_ABI_FP_number_model
),
28292 T (Tag_ABI_align_needed
),
28293 T (Tag_ABI_align8_needed
),
28294 T (Tag_ABI_align_preserved
),
28295 T (Tag_ABI_align8_preserved
),
28296 T (Tag_ABI_enum_size
),
28297 T (Tag_ABI_HardFP_use
),
28298 T (Tag_ABI_VFP_args
),
28299 T (Tag_ABI_WMMX_args
),
28300 T (Tag_ABI_optimization_goals
),
28301 T (Tag_ABI_FP_optimization_goals
),
28302 T (Tag_compatibility
),
28303 T (Tag_CPU_unaligned_access
),
28304 T (Tag_FP_HP_extension
),
28305 T (Tag_VFP_HP_extension
),
28306 T (Tag_ABI_FP_16bit_format
),
28307 T (Tag_MPextension_use
),
28309 T (Tag_nodefaults
),
28310 T (Tag_also_compatible_with
),
28311 T (Tag_conformance
),
28313 T (Tag_Virtualization_use
),
28314 T (Tag_DSP_extension
),
28315 /* We deliberately do not include Tag_MPextension_use_legacy. */
28323 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
28324 if (streq (name
, attribute_table
[i
].name
))
28325 return attribute_table
[i
].tag
;
28330 /* Apply sym value for relocations only in the case that they are for
28331 local symbols in the same segment as the fixup and you have the
28332 respective architectural feature for blx and simple switches. */
28335 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
28338 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28339 /* PR 17444: If the local symbol is in a different section then a reloc
28340 will always be generated for it, so applying the symbol value now
28341 will result in a double offset being stored in the relocation. */
28342 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
28343 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
28345 switch (fixP
->fx_r_type
)
28347 case BFD_RELOC_ARM_PCREL_BLX
:
28348 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28349 if (ARM_IS_FUNC (fixP
->fx_addsy
))
28353 case BFD_RELOC_ARM_PCREL_CALL
:
28354 case BFD_RELOC_THUMB_PCREL_BLX
:
28355 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
28366 #endif /* OBJ_ELF */