1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, ARM_EXT2_V8M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
211 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
212 static const arm_feature_set arm_ext_v6t2_v8m
=
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics
=
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
217 static const arm_feature_set arm_ext_v8_2
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
223 static const arm_feature_set arm_arch_any
= ARM_ANY
;
224 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
226 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
227 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
229 static const arm_feature_set arm_cext_iwmmxt2
=
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
231 static const arm_feature_set arm_cext_iwmmxt
=
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
233 static const arm_feature_set arm_cext_xscale
=
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
235 static const arm_feature_set arm_cext_maverick
=
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
237 static const arm_feature_set fpu_fpa_ext_v1
=
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
239 static const arm_feature_set fpu_fpa_ext_v2
=
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
241 static const arm_feature_set fpu_vfp_ext_v1xd
=
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
243 static const arm_feature_set fpu_vfp_ext_v1
=
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
245 static const arm_feature_set fpu_vfp_ext_v2
=
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
247 static const arm_feature_set fpu_vfp_ext_v3xd
=
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
249 static const arm_feature_set fpu_vfp_ext_v3
=
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
251 static const arm_feature_set fpu_vfp_ext_d32
=
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
253 static const arm_feature_set fpu_neon_ext_v1
=
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
257 static const arm_feature_set fpu_vfp_fp16
=
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
259 static const arm_feature_set fpu_neon_ext_fma
=
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
261 static const arm_feature_set fpu_vfp_ext_fma
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
263 static const arm_feature_set fpu_vfp_ext_armv8
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
265 static const arm_feature_set fpu_vfp_ext_armv8xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
267 static const arm_feature_set fpu_neon_ext_armv8
=
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
269 static const arm_feature_set fpu_crypto_ext_armv8
=
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
271 static const arm_feature_set crc_ext_armv8
=
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
273 static const arm_feature_set fpu_neon_ext_v8_1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
276 static int mfloat_abi_opt
= -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name
[20];
282 extern FLONUM_TYPE generic_floating_point_number
;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
293 static int meabi_flags
= EABI_DEFAULT
;
295 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
298 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
303 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS
* GOT_symbol
;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode
= 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER
= 0x00,
326 IMPLICIT_IT_MODE_ARM
= 0x01,
327 IMPLICIT_IT_MODE_THUMB
= 0x02,
328 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
330 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax
= FALSE
;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars
[] = "#[]{}";
376 enum neon_el_type type
;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN
/* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction
;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype
;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type
;
428 enum it_instruction_type it_insn_type
;
434 struct neon_type_el vectype
;
435 unsigned present
: 1; /* Operand present. */
436 unsigned isreg
: 1; /* Operand was a register. */
437 unsigned immisreg
: 1; /* .imm field is a second register. */
438 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
448 unsigned writeback
: 1; /* Operand has trailing ! */
449 unsigned preind
: 1; /* Preindexed address. */
450 unsigned postind
: 1; /* Postindexed address. */
451 unsigned negative
: 1; /* Index register was negated. */
452 unsigned shifted
: 1; /* Shift applied to operation. */
453 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
454 } operands
[ARM_IT_MAX_OPERANDS
];
457 static struct arm_it inst
;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const
[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name
;
493 #define COND_ALWAYS 0xE
497 const char * template_name
;
501 struct asm_barrier_opt
503 const char * template_name
;
505 const arm_feature_set arch
;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc
;
525 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
526 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
531 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined
;
542 struct neon_type_el eltype
;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin
;
583 struct neon_typed_alias
* neon
;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs
[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name
;
627 /* Parameters to instruction. */
628 unsigned int operands
[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag
: 4;
633 /* Basic instruction code. */
634 unsigned int avalue
: 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set
* avariant
;
641 const arm_feature_set
* tvariant
;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode
) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode
) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
790 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
792 static struct hash_control
* arm_ops_hsh
;
793 static struct hash_control
* arm_cond_hsh
;
794 static struct hash_control
* arm_shift_hsh
;
795 static struct hash_control
* arm_psr_hsh
;
796 static struct hash_control
* arm_v7m_psr_hsh
;
797 static struct hash_control
* arm_reg_hsh
;
798 static struct hash_control
* arm_reloc_hsh
;
799 static struct hash_control
* arm_barrier_opt_hsh
;
801 /* Stuff needed to resolve the label ambiguity
810 symbolS
* last_label_seen
;
811 static int label_is_thumb_function_name
= FALSE
;
813 /* Literal pool structure. Held on a per-section
814 and per-sub-section basis. */
816 #define MAX_LITERAL_POOL_SIZE 1024
817 typedef struct literal_pool
819 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
820 unsigned int next_free_entry
;
826 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
828 struct literal_pool
* next
;
829 unsigned int alignment
;
832 /* Pointer to a linked list of literal pools. */
833 literal_pool
* list_of_pools
= NULL
;
835 typedef enum asmfunc_states
838 WAITING_ASMFUNC_NAME
,
842 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
845 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
847 static struct current_it now_it
;
851 now_it_compatible (int cond
)
853 return (cond
& ~1) == (now_it
.cc
& ~1);
857 conditional_insn (void)
859 return inst
.cond
!= COND_ALWAYS
;
862 static int in_it_block (void);
864 static int handle_it_state (void);
866 static void force_automatic_it_block_close (void);
868 static void it_fsm_post_encode (void);
870 #define set_it_insn_type(type) \
873 inst.it_insn_type = type; \
874 if (handle_it_state () == FAIL) \
879 #define set_it_insn_type_nonvoid(type, failret) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_last() \
891 if (inst.cond == COND_ALWAYS) \
892 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
894 set_it_insn_type (INSIDE_IT_LAST_INSN); \
900 /* This array holds the chars that always start a comment. If the
901 pre-processor is disabled, these aren't very useful. */
902 char arm_comment_chars
[] = "@";
904 /* This array holds the chars that only start a comment at the beginning of
905 a line. If the line seems to have the form '# 123 filename'
906 .line and .file directives will appear in the pre-processed output. */
907 /* Note that input_file.c hand checks for '#' at the beginning of the
908 first line of the input file. This is because the compiler outputs
909 #NO_APP at the beginning of its output. */
910 /* Also note that comments like this one will always work. */
911 const char line_comment_chars
[] = "#";
913 char arm_line_separator_chars
[] = ";";
915 /* Chars that can be used to separate mant
916 from exp in floating point numbers. */
917 const char EXP_CHARS
[] = "eE";
919 /* Chars that mean this number is a floating point constant. */
923 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
925 /* Prefix characters that indicate the start of an immediate
927 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
929 /* Separator character handling. */
931 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
934 skip_past_char (char ** str
, char c
)
936 /* PR gas/14987: Allow for whitespace before the expected character. */
937 skip_whitespace (*str
);
948 #define skip_past_comma(str) skip_past_char (str, ',')
950 /* Arithmetic expressions (possibly involving symbols). */
952 /* Return TRUE if anything in the expression is a bignum. */
955 walk_no_bignums (symbolS
* sp
)
957 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
960 if (symbol_get_value_expression (sp
)->X_add_symbol
)
962 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
963 || (symbol_get_value_expression (sp
)->X_op_symbol
964 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
970 static int in_my_get_expression
= 0;
972 /* Third argument to my_get_expression. */
973 #define GE_NO_PREFIX 0
974 #define GE_IMM_PREFIX 1
975 #define GE_OPT_PREFIX 2
976 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
977 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
978 #define GE_OPT_PREFIX_BIG 3
981 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
986 /* In unified syntax, all prefixes are optional. */
988 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
993 case GE_NO_PREFIX
: break;
995 if (!is_immediate_prefix (**str
))
997 inst
.error
= _("immediate expression requires a # prefix");
1003 case GE_OPT_PREFIX_BIG
:
1004 if (is_immediate_prefix (**str
))
1010 memset (ep
, 0, sizeof (expressionS
));
1012 save_in
= input_line_pointer
;
1013 input_line_pointer
= *str
;
1014 in_my_get_expression
= 1;
1015 seg
= expression (ep
);
1016 in_my_get_expression
= 0;
1018 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1020 /* We found a bad or missing expression in md_operand(). */
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1023 if (inst
.error
== NULL
)
1024 inst
.error
= (ep
->X_op
== O_absent
1025 ? _("missing expression") :_("bad expression"));
1030 if (seg
!= absolute_section
1031 && seg
!= text_section
1032 && seg
!= data_section
1033 && seg
!= bss_section
1034 && seg
!= undefined_section
)
1036 inst
.error
= _("bad segment");
1037 *str
= input_line_pointer
;
1038 input_line_pointer
= save_in
;
1045 /* Get rid of any bignums now, so that we don't generate an error for which
1046 we can't establish a line number later on. Big numbers are never valid
1047 in instructions, which is where this routine is always called. */
1048 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1049 && (ep
->X_op
== O_big
1050 || (ep
->X_add_symbol
1051 && (walk_no_bignums (ep
->X_add_symbol
)
1053 && walk_no_bignums (ep
->X_op_symbol
))))))
1055 inst
.error
= _("invalid constant");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1061 *str
= input_line_pointer
;
1062 input_line_pointer
= save_in
;
1066 /* Turn a string in input_line_pointer into a floating point constant
1067 of type TYPE, and store the appropriate bytes in *LITP. The number
1068 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1069 returned, or NULL on OK.
1071 Note that fp constants aren't represent in the normal way on the ARM.
1072 In big endian mode, things are as expected. However, in little endian
1073 mode fp constants are big-endian word-wise, and little-endian byte-wise
1074 within the words. For example, (double) 1.1 in big endian mode is
1075 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1076 the byte sequence 99 99 f1 3f 9a 99 99 99.
1078 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1081 md_atof (int type
, char * litP
, int * sizeP
)
1084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1116 return _("Unrecognized or unsupported floating point constant");
1119 t
= atof_ieee (input_line_pointer
, type
, words
);
1121 input_line_pointer
= t
;
1122 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1124 if (target_big_endian
)
1126 for (i
= 0; i
< prec
; i
++)
1128 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1129 litP
+= sizeof (LITTLENUM_TYPE
);
1134 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1135 for (i
= prec
- 1; i
>= 0; i
--)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1141 /* For a 4 byte float the order of elements in `words' is 1 0.
1142 For an 8 byte float the order is 1 0 3 2. */
1143 for (i
= 0; i
< prec
; i
+= 2)
1145 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1146 sizeof (LITTLENUM_TYPE
));
1147 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1148 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1149 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1156 /* We handle all bad expressions here, so that we can report the faulty
1157 instruction in the error message. */
1159 md_operand (expressionS
* exp
)
1161 if (in_my_get_expression
)
1162 exp
->X_op
= O_illegal
;
1165 /* Immediate values. */
1167 /* Generic immediate-value read function for use in directives.
1168 Accepts anything that 'expression' can fold to a constant.
1169 *val receives the number. */
1172 immediate_for_directive (int *val
)
1175 exp
.X_op
= O_illegal
;
1177 if (is_immediate_prefix (*input_line_pointer
))
1179 input_line_pointer
++;
1183 if (exp
.X_op
!= O_constant
)
1185 as_bad (_("expected #constant"));
1186 ignore_rest_of_line ();
1189 *val
= exp
.X_add_number
;
1194 /* Register parsing. */
1196 /* Generic register parser. CCP points to what should be the
1197 beginning of a register name. If it is indeed a valid register
1198 name, advance CCP over it and return the reg_entry structure;
1199 otherwise return NULL. Does not issue diagnostics. */
1201 static struct reg_entry
*
1202 arm_reg_parse_multi (char **ccp
)
1206 struct reg_entry
*reg
;
1208 skip_whitespace (start
);
1210 #ifdef REGISTER_PREFIX
1211 if (*start
!= REGISTER_PREFIX
)
1215 #ifdef OPTIONAL_REGISTER_PREFIX
1216 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1221 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1226 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1228 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1238 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1239 enum arm_reg_type type
)
1241 /* Alternative syntaxes are accepted for a few register classes. */
1248 /* Generic coprocessor register names are allowed for these. */
1249 if (reg
&& reg
->type
== REG_TYPE_CN
)
1254 /* For backward compatibility, a bare number is valid here. */
1256 unsigned long processor
= strtoul (start
, ccp
, 10);
1257 if (*ccp
!= start
&& processor
<= 15)
1261 case REG_TYPE_MMXWC
:
1262 /* WC includes WCG. ??? I'm not sure this is true for all
1263 instructions that take WC registers. */
1264 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1275 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1276 return value is the register number or FAIL. */
1279 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1282 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1285 /* Do not allow a scalar (reg+index) to parse as a register. */
1286 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1289 if (reg
&& reg
->type
== type
)
1292 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1299 /* Parse a Neon type specifier. *STR should point at the leading '.'
1300 character. Does no verification at this stage that the type fits the opcode
1307 Can all be legally parsed by this function.
1309 Fills in neon_type struct pointer with parsed information, and updates STR
1310 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1311 type, FAIL if not. */
1314 parse_neon_type (struct neon_type
*type
, char **str
)
1321 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1323 enum neon_el_type thistype
= NT_untyped
;
1324 unsigned thissize
= -1u;
1331 /* Just a size without an explicit type. */
1335 switch (TOLOWER (*ptr
))
1337 case 'i': thistype
= NT_integer
; break;
1338 case 'f': thistype
= NT_float
; break;
1339 case 'p': thistype
= NT_poly
; break;
1340 case 's': thistype
= NT_signed
; break;
1341 case 'u': thistype
= NT_unsigned
; break;
1343 thistype
= NT_float
;
1348 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1354 /* .f is an abbreviation for .f32. */
1355 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1360 thissize
= strtoul (ptr
, &ptr
, 10);
1362 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1365 as_bad (_("bad size %d in type specifier"), thissize
);
1373 type
->el
[type
->elems
].type
= thistype
;
1374 type
->el
[type
->elems
].size
= thissize
;
1379 /* Empty/missing type is not a successful parse. */
1380 if (type
->elems
== 0)
1388 /* Errors may be set multiple times during parsing or bit encoding
1389 (particularly in the Neon bits), but usually the earliest error which is set
1390 will be the most meaningful. Avoid overwriting it with later (cascading)
1391 errors by calling this function. */
1394 first_error (const char *err
)
1400 /* Parse a single type, e.g. ".s32", leading period included. */
1402 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1405 struct neon_type optype
;
1409 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1411 if (optype
.elems
== 1)
1412 *vectype
= optype
.el
[0];
1415 first_error (_("only one type should be specified for operand"));
1421 first_error (_("vector type expected"));
1433 /* Special meanings for indices (which have a range of 0-7), which will fit into
1436 #define NEON_ALL_LANES 15
1437 #define NEON_INTERLEAVE_LANES 14
1439 /* Parse either a register or a scalar, with an optional type. Return the
1440 register number, and optionally fill in the actual type of the register
1441 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1442 type/index information in *TYPEINFO. */
1445 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1446 enum arm_reg_type
*rtype
,
1447 struct neon_typed_alias
*typeinfo
)
1450 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1451 struct neon_typed_alias atype
;
1452 struct neon_type_el parsetype
;
1456 atype
.eltype
.type
= NT_invtype
;
1457 atype
.eltype
.size
= -1;
1459 /* Try alternate syntax for some types of register. Note these are mutually
1460 exclusive with the Neon syntax extensions. */
1463 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1471 /* Undo polymorphism when a set of register types may be accepted. */
1472 if ((type
== REG_TYPE_NDQ
1473 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1474 || (type
== REG_TYPE_VFSD
1475 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1476 || (type
== REG_TYPE_NSDQ
1477 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1478 || reg
->type
== REG_TYPE_NQ
))
1479 || (type
== REG_TYPE_MMXWC
1480 && (reg
->type
== REG_TYPE_MMXWCG
)))
1481 type
= (enum arm_reg_type
) reg
->type
;
1483 if (type
!= reg
->type
)
1489 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1491 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1493 first_error (_("can't redefine type for operand"));
1496 atype
.defined
|= NTA_HASTYPE
;
1497 atype
.eltype
= parsetype
;
1500 if (skip_past_char (&str
, '[') == SUCCESS
)
1502 if (type
!= REG_TYPE_VFD
)
1504 first_error (_("only D registers may be indexed"));
1508 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1510 first_error (_("can't change index for operand"));
1514 atype
.defined
|= NTA_HASINDEX
;
1516 if (skip_past_char (&str
, ']') == SUCCESS
)
1517 atype
.index
= NEON_ALL_LANES
;
1522 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1524 if (exp
.X_op
!= O_constant
)
1526 first_error (_("constant expression required"));
1530 if (skip_past_char (&str
, ']') == FAIL
)
1533 atype
.index
= exp
.X_add_number
;
1548 /* Like arm_reg_parse, but allow allow the following extra features:
1549 - If RTYPE is non-zero, return the (possibly restricted) type of the
1550 register (e.g. Neon double or quad reg when either has been requested).
1551 - If this is a Neon vector type with additional type information, fill
1552 in the struct pointed to by VECTYPE (if non-NULL).
1553 This function will fault on encountering a scalar. */
1556 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1557 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1559 struct neon_typed_alias atype
;
1561 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1566 /* Do not allow regname(... to parse as a register. */
1570 /* Do not allow a scalar (reg+index) to parse as a register. */
1571 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1573 first_error (_("register operand expected, but got scalar"));
1578 *vectype
= atype
.eltype
;
1585 #define NEON_SCALAR_REG(X) ((X) >> 4)
1586 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1588 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1589 have enough information to be able to do a good job bounds-checking. So, we
1590 just do easy checks here, and do further checks later. */
1593 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1597 struct neon_typed_alias atype
;
1599 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1601 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1604 if (atype
.index
== NEON_ALL_LANES
)
1606 first_error (_("scalar must have an index"));
1609 else if (atype
.index
>= 64 / elsize
)
1611 first_error (_("scalar index out of range"));
1616 *type
= atype
.eltype
;
1620 return reg
* 16 + atype
.index
;
1623 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1626 parse_reg_list (char ** strp
)
1628 char * str
= * strp
;
1632 /* We come back here if we get ranges concatenated by '+' or '|'. */
1635 skip_whitespace (str
);
1649 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1651 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1661 first_error (_("bad range in register list"));
1665 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1667 if (range
& (1 << i
))
1669 (_("Warning: duplicated register (r%d) in register list"),
1677 if (range
& (1 << reg
))
1678 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1680 else if (reg
<= cur_reg
)
1681 as_tsktsk (_("Warning: register range not in ascending order"));
1686 while (skip_past_comma (&str
) != FAIL
1687 || (in_range
= 1, *str
++ == '-'));
1690 if (skip_past_char (&str
, '}') == FAIL
)
1692 first_error (_("missing `}'"));
1700 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1703 if (exp
.X_op
== O_constant
)
1705 if (exp
.X_add_number
1706 != (exp
.X_add_number
& 0x0000ffff))
1708 inst
.error
= _("invalid register mask");
1712 if ((range
& exp
.X_add_number
) != 0)
1714 int regno
= range
& exp
.X_add_number
;
1717 regno
= (1 << regno
) - 1;
1719 (_("Warning: duplicated register (r%d) in register list"),
1723 range
|= exp
.X_add_number
;
1727 if (inst
.reloc
.type
!= 0)
1729 inst
.error
= _("expression too complex");
1733 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1734 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1735 inst
.reloc
.pc_rel
= 0;
1739 if (*str
== '|' || *str
== '+')
1745 while (another_range
);
1751 /* Types of registers in a list. */
1760 /* Parse a VFP register list. If the string is invalid return FAIL.
1761 Otherwise return the number of registers, and set PBASE to the first
1762 register. Parses registers of type ETYPE.
1763 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1764 - Q registers can be used to specify pairs of D registers
1765 - { } can be omitted from around a singleton register list
1766 FIXME: This is not implemented, as it would require backtracking in
1769 This could be done (the meaning isn't really ambiguous), but doesn't
1770 fit in well with the current parsing framework.
1771 - 32 D registers may be used (also true for VFPv3).
1772 FIXME: Types are ignored in these register lists, which is probably a
1776 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1781 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1785 unsigned long mask
= 0;
1788 if (skip_past_char (&str
, '{') == FAIL
)
1790 inst
.error
= _("expecting {");
1797 regtype
= REG_TYPE_VFS
;
1802 regtype
= REG_TYPE_VFD
;
1805 case REGLIST_NEON_D
:
1806 regtype
= REG_TYPE_NDQ
;
1810 if (etype
!= REGLIST_VFP_S
)
1812 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1817 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1820 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1827 base_reg
= max_regs
;
1831 int setmask
= 1, addregs
= 1;
1833 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1835 if (new_base
== FAIL
)
1837 first_error (_(reg_expected_msgs
[regtype
]));
1841 if (new_base
>= max_regs
)
1843 first_error (_("register out of range in list"));
1847 /* Note: a value of 2 * n is returned for the register Q<n>. */
1848 if (regtype
== REG_TYPE_NQ
)
1854 if (new_base
< base_reg
)
1855 base_reg
= new_base
;
1857 if (mask
& (setmask
<< new_base
))
1859 first_error (_("invalid register list"));
1863 if ((mask
>> new_base
) != 0 && ! warned
)
1865 as_tsktsk (_("register list not in ascending order"));
1869 mask
|= setmask
<< new_base
;
1872 if (*str
== '-') /* We have the start of a range expression */
1878 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1881 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1885 if (high_range
>= max_regs
)
1887 first_error (_("register out of range in list"));
1891 if (regtype
== REG_TYPE_NQ
)
1892 high_range
= high_range
+ 1;
1894 if (high_range
<= new_base
)
1896 inst
.error
= _("register range not in ascending order");
1900 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1902 if (mask
& (setmask
<< new_base
))
1904 inst
.error
= _("invalid register list");
1908 mask
|= setmask
<< new_base
;
1913 while (skip_past_comma (&str
) != FAIL
);
1917 /* Sanity check -- should have raised a parse error above. */
1918 if (count
== 0 || count
> max_regs
)
1923 /* Final test -- the registers must be consecutive. */
1925 for (i
= 0; i
< count
; i
++)
1927 if ((mask
& (1u << i
)) == 0)
1929 inst
.error
= _("non-contiguous register range");
1939 /* True if two alias types are the same. */
1942 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1950 if (a
->defined
!= b
->defined
)
1953 if ((a
->defined
& NTA_HASTYPE
) != 0
1954 && (a
->eltype
.type
!= b
->eltype
.type
1955 || a
->eltype
.size
!= b
->eltype
.size
))
1958 if ((a
->defined
& NTA_HASINDEX
) != 0
1959 && (a
->index
!= b
->index
))
1965 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1966 The base register is put in *PBASE.
1967 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1969 The register stride (minus one) is put in bit 4 of the return value.
1970 Bits [6:5] encode the list length (minus one).
1971 The type of the list elements is put in *ELTYPE, if non-NULL. */
1973 #define NEON_LANE(X) ((X) & 0xf)
1974 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1975 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1978 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1979 struct neon_type_el
*eltype
)
1986 int leading_brace
= 0;
1987 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1988 const char *const incr_error
= _("register stride must be 1 or 2");
1989 const char *const type_error
= _("mismatched element/structure types in list");
1990 struct neon_typed_alias firsttype
;
1991 firsttype
.defined
= 0;
1992 firsttype
.eltype
.type
= NT_invtype
;
1993 firsttype
.eltype
.size
= -1;
1994 firsttype
.index
= -1;
1996 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2001 struct neon_typed_alias atype
;
2002 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2006 first_error (_(reg_expected_msgs
[rtype
]));
2013 if (rtype
== REG_TYPE_NQ
)
2019 else if (reg_incr
== -1)
2021 reg_incr
= getreg
- base_reg
;
2022 if (reg_incr
< 1 || reg_incr
> 2)
2024 first_error (_(incr_error
));
2028 else if (getreg
!= base_reg
+ reg_incr
* count
)
2030 first_error (_(incr_error
));
2034 if (! neon_alias_types_same (&atype
, &firsttype
))
2036 first_error (_(type_error
));
2040 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2044 struct neon_typed_alias htype
;
2045 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2047 lane
= NEON_INTERLEAVE_LANES
;
2048 else if (lane
!= NEON_INTERLEAVE_LANES
)
2050 first_error (_(type_error
));
2055 else if (reg_incr
!= 1)
2057 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2061 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2064 first_error (_(reg_expected_msgs
[rtype
]));
2067 if (! neon_alias_types_same (&htype
, &firsttype
))
2069 first_error (_(type_error
));
2072 count
+= hireg
+ dregs
- getreg
;
2076 /* If we're using Q registers, we can't use [] or [n] syntax. */
2077 if (rtype
== REG_TYPE_NQ
)
2083 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2087 else if (lane
!= atype
.index
)
2089 first_error (_(type_error
));
2093 else if (lane
== -1)
2094 lane
= NEON_INTERLEAVE_LANES
;
2095 else if (lane
!= NEON_INTERLEAVE_LANES
)
2097 first_error (_(type_error
));
2102 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2104 /* No lane set by [x]. We must be interleaving structures. */
2106 lane
= NEON_INTERLEAVE_LANES
;
2109 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2110 || (count
> 1 && reg_incr
== -1))
2112 first_error (_("error parsing element/structure list"));
2116 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2118 first_error (_("expected }"));
2126 *eltype
= firsttype
.eltype
;
2131 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2134 /* Parse an explicit relocation suffix on an expression. This is
2135 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2136 arm_reloc_hsh contains no entries, so this function can only
2137 succeed if there is no () after the word. Returns -1 on error,
2138 BFD_RELOC_UNUSED if there wasn't any suffix. */
2141 parse_reloc (char **str
)
2143 struct reloc_entry
*r
;
2147 return BFD_RELOC_UNUSED
;
2152 while (*q
&& *q
!= ')' && *q
!= ',')
2157 if ((r
= (struct reloc_entry
*)
2158 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2165 /* Directives: register aliases. */
2167 static struct reg_entry
*
2168 insert_reg_alias (char *str
, unsigned number
, int type
)
2170 struct reg_entry
*new_reg
;
2173 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2175 if (new_reg
->builtin
)
2176 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2178 /* Only warn about a redefinition if it's not defined as the
2180 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2181 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2186 name
= xstrdup (str
);
2187 new_reg
= XNEW (struct reg_entry
);
2189 new_reg
->name
= name
;
2190 new_reg
->number
= number
;
2191 new_reg
->type
= type
;
2192 new_reg
->builtin
= FALSE
;
2193 new_reg
->neon
= NULL
;
2195 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2202 insert_neon_reg_alias (char *str
, int number
, int type
,
2203 struct neon_typed_alias
*atype
)
2205 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2209 first_error (_("attempt to redefine typed alias"));
2215 reg
->neon
= XNEW (struct neon_typed_alias
);
2216 *reg
->neon
= *atype
;
2220 /* Look for the .req directive. This is of the form:
2222 new_register_name .req existing_register_name
2224 If we find one, or if it looks sufficiently like one that we want to
2225 handle any error here, return TRUE. Otherwise return FALSE. */
2228 create_register_alias (char * newname
, char *p
)
2230 struct reg_entry
*old
;
2231 char *oldname
, *nbuf
;
2234 /* The input scrubber ensures that whitespace after the mnemonic is
2235 collapsed to single spaces. */
2237 if (strncmp (oldname
, " .req ", 6) != 0)
2241 if (*oldname
== '\0')
2244 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2247 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2251 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2252 the desired alias name, and p points to its end. If not, then
2253 the desired alias name is in the global original_case_string. */
2254 #ifdef TC_CASE_SENSITIVE
2257 newname
= original_case_string
;
2258 nlen
= strlen (newname
);
2261 nbuf
= xmalloc (nlen
+ 1);
2262 memcpy (nbuf
, newname
, nlen
);
2265 /* Create aliases under the new name as stated; an all-lowercase
2266 version of the new name; and an all-uppercase version of the new
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2270 for (p
= nbuf
; *p
; p
++)
2273 if (strncmp (nbuf
, newname
, nlen
))
2275 /* If this attempt to create an additional alias fails, do not bother
2276 trying to create the all-lower case alias. We will fail and issue
2277 a second, duplicate error message. This situation arises when the
2278 programmer does something like:
2281 The second .req creates the "Foo" alias but then fails to create
2282 the artificial FOO alias because it has already been created by the
2284 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2291 for (p
= nbuf
; *p
; p
++)
2294 if (strncmp (nbuf
, newname
, nlen
))
2295 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2302 /* Create a Neon typed/indexed register alias using directives, e.g.:
2307 These typed registers can be used instead of the types specified after the
2308 Neon mnemonic, so long as all operands given have types. Types can also be
2309 specified directly, e.g.:
2310 vadd d0.s32, d1.s32, d2.s32 */
2313 create_neon_reg_alias (char *newname
, char *p
)
2315 enum arm_reg_type basetype
;
2316 struct reg_entry
*basereg
;
2317 struct reg_entry mybasereg
;
2318 struct neon_type ntype
;
2319 struct neon_typed_alias typeinfo
;
2320 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2323 typeinfo
.defined
= 0;
2324 typeinfo
.eltype
.type
= NT_invtype
;
2325 typeinfo
.eltype
.size
= -1;
2326 typeinfo
.index
= -1;
2330 if (strncmp (p
, " .dn ", 5) == 0)
2331 basetype
= REG_TYPE_VFD
;
2332 else if (strncmp (p
, " .qn ", 5) == 0)
2333 basetype
= REG_TYPE_NQ
;
2342 basereg
= arm_reg_parse_multi (&p
);
2344 if (basereg
&& basereg
->type
!= basetype
)
2346 as_bad (_("bad type for register"));
2350 if (basereg
== NULL
)
2353 /* Try parsing as an integer. */
2354 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2355 if (exp
.X_op
!= O_constant
)
2357 as_bad (_("expression must be constant"));
2360 basereg
= &mybasereg
;
2361 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2367 typeinfo
= *basereg
->neon
;
2369 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2371 /* We got a type. */
2372 if (typeinfo
.defined
& NTA_HASTYPE
)
2374 as_bad (_("can't redefine the type of a register alias"));
2378 typeinfo
.defined
|= NTA_HASTYPE
;
2379 if (ntype
.elems
!= 1)
2381 as_bad (_("you must specify a single type only"));
2384 typeinfo
.eltype
= ntype
.el
[0];
2387 if (skip_past_char (&p
, '[') == SUCCESS
)
2390 /* We got a scalar index. */
2392 if (typeinfo
.defined
& NTA_HASINDEX
)
2394 as_bad (_("can't redefine the index of a scalar alias"));
2398 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2400 if (exp
.X_op
!= O_constant
)
2402 as_bad (_("scalar index must be constant"));
2406 typeinfo
.defined
|= NTA_HASINDEX
;
2407 typeinfo
.index
= exp
.X_add_number
;
2409 if (skip_past_char (&p
, ']') == FAIL
)
2411 as_bad (_("expecting ]"));
2416 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2417 the desired alias name, and p points to its end. If not, then
2418 the desired alias name is in the global original_case_string. */
2419 #ifdef TC_CASE_SENSITIVE
2420 namelen
= nameend
- newname
;
2422 newname
= original_case_string
;
2423 namelen
= strlen (newname
);
2426 namebuf
= xmalloc (namelen
+ 1);
2427 strncpy (namebuf
, newname
, namelen
);
2428 namebuf
[namelen
] = '\0';
2430 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2431 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2433 /* Insert name in all uppercase. */
2434 for (p
= namebuf
; *p
; p
++)
2437 if (strncmp (namebuf
, newname
, namelen
))
2438 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2439 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2441 /* Insert name in all lowercase. */
2442 for (p
= namebuf
; *p
; p
++)
2445 if (strncmp (namebuf
, newname
, namelen
))
2446 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2447 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Should never be called, as .req goes between the alias and the
2454 register name, not at the beginning of the line. */
2457 s_req (int a ATTRIBUTE_UNUSED
)
2459 as_bad (_("invalid syntax for .req directive"));
2463 s_dn (int a ATTRIBUTE_UNUSED
)
2465 as_bad (_("invalid syntax for .dn directive"));
2469 s_qn (int a ATTRIBUTE_UNUSED
)
2471 as_bad (_("invalid syntax for .qn directive"));
2474 /* The .unreq directive deletes an alias which was previously defined
2475 by .req. For example:
2481 s_unreq (int a ATTRIBUTE_UNUSED
)
2486 name
= input_line_pointer
;
2488 while (*input_line_pointer
!= 0
2489 && *input_line_pointer
!= ' '
2490 && *input_line_pointer
!= '\n')
2491 ++input_line_pointer
;
2493 saved_char
= *input_line_pointer
;
2494 *input_line_pointer
= 0;
2497 as_bad (_("invalid syntax for .unreq directive"));
2500 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2504 as_bad (_("unknown register alias '%s'"), name
);
2505 else if (reg
->builtin
)
2506 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2513 hash_delete (arm_reg_hsh
, name
, FALSE
);
2514 free ((char *) reg
->name
);
2519 /* Also locate the all upper case and all lower case versions.
2520 Do not complain if we cannot find one or the other as it
2521 was probably deleted above. */
2523 nbuf
= strdup (name
);
2524 for (p
= nbuf
; *p
; p
++)
2526 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2529 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2530 free ((char *) reg
->name
);
2536 for (p
= nbuf
; *p
; p
++)
2538 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2541 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2542 free ((char *) reg
->name
);
2552 *input_line_pointer
= saved_char
;
2553 demand_empty_rest_of_line ();
2556 /* Directives: Instruction set selection. */
2559 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2560 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2561 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2562 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2564 /* Create a new mapping symbol for the transition to STATE. */
2567 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2570 const char * symname
;
2577 type
= BSF_NO_FLAGS
;
2581 type
= BSF_NO_FLAGS
;
2585 type
= BSF_NO_FLAGS
;
2591 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2592 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2597 THUMB_SET_FUNC (symbolP
, 0);
2598 ARM_SET_THUMB (symbolP
, 0);
2599 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2603 THUMB_SET_FUNC (symbolP
, 1);
2604 ARM_SET_THUMB (symbolP
, 1);
2605 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2613 /* Save the mapping symbols for future reference. Also check that
2614 we do not place two mapping symbols at the same offset within a
2615 frag. We'll handle overlap between frags in
2616 check_mapping_symbols.
2618 If .fill or other data filling directive generates zero sized data,
2619 the mapping symbol for the following code will have the same value
2620 as the one generated for the data filling directive. In this case,
2621 we replace the old symbol with the new one at the same address. */
2624 if (frag
->tc_frag_data
.first_map
!= NULL
)
2626 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2627 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2629 frag
->tc_frag_data
.first_map
= symbolP
;
2631 if (frag
->tc_frag_data
.last_map
!= NULL
)
2633 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2634 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2635 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2637 frag
->tc_frag_data
.last_map
= symbolP
;
2640 /* We must sometimes convert a region marked as code to data during
2641 code alignment, if an odd number of bytes have to be padded. The
2642 code mapping symbol is pushed to an aligned address. */
2645 insert_data_mapping_symbol (enum mstate state
,
2646 valueT value
, fragS
*frag
, offsetT bytes
)
2648 /* If there was already a mapping symbol, remove it. */
2649 if (frag
->tc_frag_data
.last_map
!= NULL
2650 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2652 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2656 know (frag
->tc_frag_data
.first_map
== symp
);
2657 frag
->tc_frag_data
.first_map
= NULL
;
2659 frag
->tc_frag_data
.last_map
= NULL
;
2660 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2663 make_mapping_symbol (MAP_DATA
, value
, frag
);
2664 make_mapping_symbol (state
, value
+ bytes
, frag
);
2667 static void mapping_state_2 (enum mstate state
, int max_chars
);
2669 /* Set the mapping state to STATE. Only call this when about to
2670 emit some STATE bytes to the file. */
2672 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2674 mapping_state (enum mstate state
)
2676 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2678 if (mapstate
== state
)
2679 /* The mapping symbol has already been emitted.
2680 There is nothing else to do. */
2683 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2685 All ARM instructions require 4-byte alignment.
2686 (Almost) all Thumb instructions require 2-byte alignment.
2688 When emitting instructions into any section, mark the section
2691 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2692 but themselves require 2-byte alignment; this applies to some
2693 PC- relative forms. However, these cases will invovle implicit
2694 literal pool generation or an explicit .align >=2, both of
2695 which will cause the section to me marked with sufficient
2696 alignment. Thus, we don't handle those cases here. */
2697 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2699 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2700 /* This case will be evaluated later. */
2703 mapping_state_2 (state
, 0);
2706 /* Same as mapping_state, but MAX_CHARS bytes have already been
2707 allocated. Put the mapping symbol that far back. */
2710 mapping_state_2 (enum mstate state
, int max_chars
)
2712 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2714 if (!SEG_NORMAL (now_seg
))
2717 if (mapstate
== state
)
2718 /* The mapping symbol has already been emitted.
2719 There is nothing else to do. */
2722 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2723 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2725 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2726 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2729 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2732 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2733 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2737 #define mapping_state(x) ((void)0)
2738 #define mapping_state_2(x, y) ((void)0)
2741 /* Find the real, Thumb encoded start of a Thumb function. */
2745 find_real_start (symbolS
* symbolP
)
2748 const char * name
= S_GET_NAME (symbolP
);
2749 symbolS
* new_target
;
2751 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2752 #define STUB_NAME ".real_start_of"
2757 /* The compiler may generate BL instructions to local labels because
2758 it needs to perform a branch to a far away location. These labels
2759 do not have a corresponding ".real_start_of" label. We check
2760 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2761 the ".real_start_of" convention for nonlocal branches. */
2762 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2765 real_start
= concat (STUB_NAME
, name
, NULL
);
2766 new_target
= symbol_find (real_start
);
2769 if (new_target
== NULL
)
2771 as_warn (_("Failed to find real start of function: %s\n"), name
);
2772 new_target
= symbolP
;
2780 opcode_select (int width
)
2787 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2788 as_bad (_("selected processor does not support THUMB opcodes"));
2791 /* No need to force the alignment, since we will have been
2792 coming from ARM mode, which is word-aligned. */
2793 record_alignment (now_seg
, 1);
2800 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2801 as_bad (_("selected processor does not support ARM opcodes"));
2806 frag_align (2, 0, 0);
2808 record_alignment (now_seg
, 1);
2813 as_bad (_("invalid instruction size selected (%d)"), width
);
2818 s_arm (int ignore ATTRIBUTE_UNUSED
)
2821 demand_empty_rest_of_line ();
2825 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2828 demand_empty_rest_of_line ();
2832 s_code (int unused ATTRIBUTE_UNUSED
)
2836 temp
= get_absolute_expression ();
2841 opcode_select (temp
);
2845 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2850 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2852 /* If we are not already in thumb mode go into it, EVEN if
2853 the target processor does not support thumb instructions.
2854 This is used by gcc/config/arm/lib1funcs.asm for example
2855 to compile interworking support functions even if the
2856 target processor should not support interworking. */
2860 record_alignment (now_seg
, 1);
2863 demand_empty_rest_of_line ();
2867 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2871 /* The following label is the name/address of the start of a Thumb function.
2872 We need to know this for the interworking support. */
2873 label_is_thumb_function_name
= TRUE
;
2876 /* Perform a .set directive, but also mark the alias as
2877 being a thumb function. */
2880 s_thumb_set (int equiv
)
2882 /* XXX the following is a duplicate of the code for s_set() in read.c
2883 We cannot just call that code as we need to get at the symbol that
2890 /* Especial apologies for the random logic:
2891 This just grew, and could be parsed much more simply!
2893 delim
= get_symbol_name (& name
);
2894 end_name
= input_line_pointer
;
2895 (void) restore_line_pointer (delim
);
2897 if (*input_line_pointer
!= ',')
2900 as_bad (_("expected comma after name \"%s\""), name
);
2902 ignore_rest_of_line ();
2906 input_line_pointer
++;
2909 if (name
[0] == '.' && name
[1] == '\0')
2911 /* XXX - this should not happen to .thumb_set. */
2915 if ((symbolP
= symbol_find (name
)) == NULL
2916 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2919 /* When doing symbol listings, play games with dummy fragments living
2920 outside the normal fragment chain to record the file and line info
2922 if (listing
& LISTING_SYMBOLS
)
2924 extern struct list_info_struct
* listing_tail
;
2925 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2927 memset (dummy_frag
, 0, sizeof (fragS
));
2928 dummy_frag
->fr_type
= rs_fill
;
2929 dummy_frag
->line
= listing_tail
;
2930 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2931 dummy_frag
->fr_symbol
= symbolP
;
2935 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2938 /* "set" symbols are local unless otherwise specified. */
2939 SF_SET_LOCAL (symbolP
);
2940 #endif /* OBJ_COFF */
2941 } /* Make a new symbol. */
2943 symbol_table_insert (symbolP
);
2948 && S_IS_DEFINED (symbolP
)
2949 && S_GET_SEGMENT (symbolP
) != reg_section
)
2950 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2952 pseudo_set (symbolP
);
2954 demand_empty_rest_of_line ();
2956 /* XXX Now we come to the Thumb specific bit of code. */
2958 THUMB_SET_FUNC (symbolP
, 1);
2959 ARM_SET_THUMB (symbolP
, 1);
2960 #if defined OBJ_ELF || defined OBJ_COFF
2961 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2965 /* Directives: Mode selection. */
2967 /* .syntax [unified|divided] - choose the new unified syntax
2968 (same for Arm and Thumb encoding, modulo slight differences in what
2969 can be represented) or the old divergent syntax for each mode. */
2971 s_syntax (int unused ATTRIBUTE_UNUSED
)
2975 delim
= get_symbol_name (& name
);
2977 if (!strcasecmp (name
, "unified"))
2978 unified_syntax
= TRUE
;
2979 else if (!strcasecmp (name
, "divided"))
2980 unified_syntax
= FALSE
;
2983 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2986 (void) restore_line_pointer (delim
);
2987 demand_empty_rest_of_line ();
2990 /* Directives: sectioning and alignment. */
2993 s_bss (int ignore ATTRIBUTE_UNUSED
)
2995 /* We don't support putting frags in the BSS segment, we fake it by
2996 marking in_bss, then looking at s_skip for clues. */
2997 subseg_set (bss_section
, 0);
2998 demand_empty_rest_of_line ();
3000 #ifdef md_elf_section_change_hook
3001 md_elf_section_change_hook ();
3006 s_even (int ignore ATTRIBUTE_UNUSED
)
3008 /* Never make frag if expect extra pass. */
3010 frag_align (1, 0, 0);
3012 record_alignment (now_seg
, 1);
3014 demand_empty_rest_of_line ();
3017 /* Directives: CodeComposer Studio. */
3019 /* .ref (for CodeComposer Studio syntax only). */
3021 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3023 if (codecomposer_syntax
)
3024 ignore_rest_of_line ();
3026 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3029 /* If name is not NULL, then it is used for marking the beginning of a
3030 function, wherease if it is NULL then it means the function end. */
3032 asmfunc_debug (const char * name
)
3034 static const char * last_name
= NULL
;
3038 gas_assert (last_name
== NULL
);
3041 if (debug_type
== DEBUG_STABS
)
3042 stabs_generate_asm_func (name
, name
);
3046 gas_assert (last_name
!= NULL
);
3048 if (debug_type
== DEBUG_STABS
)
3049 stabs_generate_asm_endfunc (last_name
, last_name
);
3056 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3058 if (codecomposer_syntax
)
3060 switch (asmfunc_state
)
3062 case OUTSIDE_ASMFUNC
:
3063 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3066 case WAITING_ASMFUNC_NAME
:
3067 as_bad (_(".asmfunc repeated."));
3070 case WAITING_ENDASMFUNC
:
3071 as_bad (_(".asmfunc without function."));
3074 demand_empty_rest_of_line ();
3077 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3081 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3083 if (codecomposer_syntax
)
3085 switch (asmfunc_state
)
3087 case OUTSIDE_ASMFUNC
:
3088 as_bad (_(".endasmfunc without a .asmfunc."));
3091 case WAITING_ASMFUNC_NAME
:
3092 as_bad (_(".endasmfunc without function."));
3095 case WAITING_ENDASMFUNC
:
3096 asmfunc_state
= OUTSIDE_ASMFUNC
;
3097 asmfunc_debug (NULL
);
3100 demand_empty_rest_of_line ();
3103 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3107 s_ccs_def (int name
)
3109 if (codecomposer_syntax
)
3112 as_bad (_(".def pseudo-op only available with -mccs flag."));
3115 /* Directives: Literal pools. */
3117 static literal_pool
*
3118 find_literal_pool (void)
3120 literal_pool
* pool
;
3122 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3124 if (pool
->section
== now_seg
3125 && pool
->sub_section
== now_subseg
)
3132 static literal_pool
*
3133 find_or_make_literal_pool (void)
3135 /* Next literal pool ID number. */
3136 static unsigned int latest_pool_num
= 1;
3137 literal_pool
* pool
;
3139 pool
= find_literal_pool ();
3143 /* Create a new pool. */
3144 pool
= XNEW (literal_pool
);
3148 pool
->next_free_entry
= 0;
3149 pool
->section
= now_seg
;
3150 pool
->sub_section
= now_subseg
;
3151 pool
->next
= list_of_pools
;
3152 pool
->symbol
= NULL
;
3153 pool
->alignment
= 2;
3155 /* Add it to the list. */
3156 list_of_pools
= pool
;
3159 /* New pools, and emptied pools, will have a NULL symbol. */
3160 if (pool
->symbol
== NULL
)
3162 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3163 (valueT
) 0, &zero_address_frag
);
3164 pool
->id
= latest_pool_num
++;
3171 /* Add the literal in the global 'inst'
3172 structure to the relevant literal pool. */
3175 add_to_lit_pool (unsigned int nbytes
)
3177 #define PADDING_SLOT 0x1
3178 #define LIT_ENTRY_SIZE_MASK 0xFF
3179 literal_pool
* pool
;
3180 unsigned int entry
, pool_size
= 0;
3181 bfd_boolean padding_slot_p
= FALSE
;
3187 imm1
= inst
.operands
[1].imm
;
3188 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3189 : inst
.reloc
.exp
.X_unsigned
? 0
3190 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3191 if (target_big_endian
)
3194 imm2
= inst
.operands
[1].imm
;
3198 pool
= find_or_make_literal_pool ();
3200 /* Check if this literal value is already in the pool. */
3201 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3205 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3206 && (inst
.reloc
.exp
.X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
3208 == inst
.reloc
.exp
.X_add_number
)
3209 && (pool
->literals
[entry
].X_md
== nbytes
)
3210 && (pool
->literals
[entry
].X_unsigned
3211 == inst
.reloc
.exp
.X_unsigned
))
3214 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3215 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3216 && (pool
->literals
[entry
].X_add_number
3217 == inst
.reloc
.exp
.X_add_number
)
3218 && (pool
->literals
[entry
].X_add_symbol
3219 == inst
.reloc
.exp
.X_add_symbol
)
3220 && (pool
->literals
[entry
].X_op_symbol
3221 == inst
.reloc
.exp
.X_op_symbol
)
3222 && (pool
->literals
[entry
].X_md
== nbytes
))
3225 else if ((nbytes
== 8)
3226 && !(pool_size
& 0x7)
3227 && ((entry
+ 1) != pool
->next_free_entry
)
3228 && (pool
->literals
[entry
].X_op
== O_constant
)
3229 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
)
3232 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3233 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3234 && (pool
->literals
[entry
+ 1].X_unsigned
3235 == inst
.reloc
.exp
.X_unsigned
))
3238 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3239 if (padding_slot_p
&& (nbytes
== 4))
3245 /* Do we need to create a new entry? */
3246 if (entry
== pool
->next_free_entry
)
3248 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3250 inst
.error
= _("literal pool overflow");
3256 /* For 8-byte entries, we align to an 8-byte boundary,
3257 and split it into two 4-byte entries, because on 32-bit
3258 host, 8-byte constants are treated as big num, thus
3259 saved in "generic_bignum" which will be overwritten
3260 by later assignments.
3262 We also need to make sure there is enough space for
3265 We also check to make sure the literal operand is a
3267 if (!(inst
.reloc
.exp
.X_op
== O_constant
3268 || inst
.reloc
.exp
.X_op
== O_big
))
3270 inst
.error
= _("invalid type for literal pool");
3273 else if (pool_size
& 0x7)
3275 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3277 inst
.error
= _("literal pool overflow");
3281 pool
->literals
[entry
] = inst
.reloc
.exp
;
3282 pool
->literals
[entry
].X_add_number
= 0;
3283 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3284 pool
->next_free_entry
+= 1;
3287 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3289 inst
.error
= _("literal pool overflow");
3293 pool
->literals
[entry
] = inst
.reloc
.exp
;
3294 pool
->literals
[entry
].X_op
= O_constant
;
3295 pool
->literals
[entry
].X_add_number
= imm1
;
3296 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3297 pool
->literals
[entry
++].X_md
= 4;
3298 pool
->literals
[entry
] = inst
.reloc
.exp
;
3299 pool
->literals
[entry
].X_op
= O_constant
;
3300 pool
->literals
[entry
].X_add_number
= imm2
;
3301 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3302 pool
->literals
[entry
].X_md
= 4;
3303 pool
->alignment
= 3;
3304 pool
->next_free_entry
+= 1;
3308 pool
->literals
[entry
] = inst
.reloc
.exp
;
3309 pool
->literals
[entry
].X_md
= 4;
3313 /* PR ld/12974: Record the location of the first source line to reference
3314 this entry in the literal pool. If it turns out during linking that the
3315 symbol does not exist we will be able to give an accurate line number for
3316 the (first use of the) missing reference. */
3317 if (debug_type
== DEBUG_DWARF2
)
3318 dwarf2_where (pool
->locs
+ entry
);
3320 pool
->next_free_entry
+= 1;
3322 else if (padding_slot_p
)
3324 pool
->literals
[entry
] = inst
.reloc
.exp
;
3325 pool
->literals
[entry
].X_md
= nbytes
;
3328 inst
.reloc
.exp
.X_op
= O_symbol
;
3329 inst
.reloc
.exp
.X_add_number
= pool_size
;
3330 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3336 tc_start_label_without_colon (void)
3338 bfd_boolean ret
= TRUE
;
3340 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3342 const char *label
= input_line_pointer
;
3344 while (!is_end_of_line
[(int) label
[-1]])
3349 as_bad (_("Invalid label '%s'"), label
);
3353 asmfunc_debug (label
);
3355 asmfunc_state
= WAITING_ENDASMFUNC
;
3361 /* Can't use symbol_new here, so have to create a symbol and then at
3362 a later date assign it a value. Thats what these functions do. */
3365 symbol_locate (symbolS
* symbolP
,
3366 const char * name
, /* It is copied, the caller can modify. */
3367 segT segment
, /* Segment identifier (SEG_<something>). */
3368 valueT valu
, /* Symbol value. */
3369 fragS
* frag
) /* Associated fragment. */
3372 char * preserved_copy_of_name
;
3374 name_length
= strlen (name
) + 1; /* +1 for \0. */
3375 obstack_grow (¬es
, name
, name_length
);
3376 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3378 #ifdef tc_canonicalize_symbol_name
3379 preserved_copy_of_name
=
3380 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3383 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3385 S_SET_SEGMENT (symbolP
, segment
);
3386 S_SET_VALUE (symbolP
, valu
);
3387 symbol_clear_list_pointers (symbolP
);
3389 symbol_set_frag (symbolP
, frag
);
3391 /* Link to end of symbol chain. */
3393 extern int symbol_table_frozen
;
3395 if (symbol_table_frozen
)
3399 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3401 obj_symbol_new_hook (symbolP
);
3403 #ifdef tc_symbol_new_hook
3404 tc_symbol_new_hook (symbolP
);
3408 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3409 #endif /* DEBUG_SYMS */
3413 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3416 literal_pool
* pool
;
3419 pool
= find_literal_pool ();
3421 || pool
->symbol
== NULL
3422 || pool
->next_free_entry
== 0)
3425 /* Align pool as you have word accesses.
3426 Only make a frag if we have to. */
3428 frag_align (pool
->alignment
, 0, 0);
3430 record_alignment (now_seg
, 2);
3433 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3434 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3436 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3438 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3439 (valueT
) frag_now_fix (), frag_now
);
3440 symbol_table_insert (pool
->symbol
);
3442 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3444 #if defined OBJ_COFF || defined OBJ_ELF
3445 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3448 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3451 if (debug_type
== DEBUG_DWARF2
)
3452 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3454 /* First output the expression in the instruction to the pool. */
3455 emit_expr (&(pool
->literals
[entry
]),
3456 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3459 /* Mark the pool as empty. */
3460 pool
->next_free_entry
= 0;
3461 pool
->symbol
= NULL
;
3465 /* Forward declarations for functions below, in the MD interface
3467 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3468 static valueT
create_unwind_entry (int);
3469 static void start_unwind_section (const segT
, int);
3470 static void add_unwind_opcode (valueT
, int);
3471 static void flush_pending_unwind (void);
3473 /* Directives: Data. */
3476 s_arm_elf_cons (int nbytes
)
3480 #ifdef md_flush_pending_output
3481 md_flush_pending_output ();
3484 if (is_it_end_of_statement ())
3486 demand_empty_rest_of_line ();
3490 #ifdef md_cons_align
3491 md_cons_align (nbytes
);
3494 mapping_state (MAP_DATA
);
3498 char *base
= input_line_pointer
;
3502 if (exp
.X_op
!= O_symbol
)
3503 emit_expr (&exp
, (unsigned int) nbytes
);
3506 char *before_reloc
= input_line_pointer
;
3507 reloc
= parse_reloc (&input_line_pointer
);
3510 as_bad (_("unrecognized relocation suffix"));
3511 ignore_rest_of_line ();
3514 else if (reloc
== BFD_RELOC_UNUSED
)
3515 emit_expr (&exp
, (unsigned int) nbytes
);
3518 reloc_howto_type
*howto
= (reloc_howto_type
*)
3519 bfd_reloc_type_lookup (stdoutput
,
3520 (bfd_reloc_code_real_type
) reloc
);
3521 int size
= bfd_get_reloc_size (howto
);
3523 if (reloc
== BFD_RELOC_ARM_PLT32
)
3525 as_bad (_("(plt) is only valid on branch targets"));
3526 reloc
= BFD_RELOC_UNUSED
;
3531 as_bad (_("%s relocations do not fit in %d bytes"),
3532 howto
->name
, nbytes
);
3535 /* We've parsed an expression stopping at O_symbol.
3536 But there may be more expression left now that we
3537 have parsed the relocation marker. Parse it again.
3538 XXX Surely there is a cleaner way to do this. */
3539 char *p
= input_line_pointer
;
3541 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3543 memcpy (save_buf
, base
, input_line_pointer
- base
);
3544 memmove (base
+ (input_line_pointer
- before_reloc
),
3545 base
, before_reloc
- base
);
3547 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3549 memcpy (base
, save_buf
, p
- base
);
3551 offset
= nbytes
- size
;
3552 p
= frag_more (nbytes
);
3553 memset (p
, 0, nbytes
);
3554 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3555 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3561 while (*input_line_pointer
++ == ',');
3563 /* Put terminator back into stream. */
3564 input_line_pointer
--;
3565 demand_empty_rest_of_line ();
3568 /* Emit an expression containing a 32-bit thumb instruction.
3569 Implementation based on put_thumb32_insn. */
3572 emit_thumb32_expr (expressionS
* exp
)
3574 expressionS exp_high
= *exp
;
3576 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3577 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3578 exp
->X_add_number
&= 0xffff;
3579 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3582 /* Guess the instruction size based on the opcode. */
3585 thumb_insn_size (int opcode
)
3587 if ((unsigned int) opcode
< 0xe800u
)
3589 else if ((unsigned int) opcode
>= 0xe8000000u
)
3596 emit_insn (expressionS
*exp
, int nbytes
)
3600 if (exp
->X_op
== O_constant
)
3605 size
= thumb_insn_size (exp
->X_add_number
);
3609 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3611 as_bad (_(".inst.n operand too big. "\
3612 "Use .inst.w instead"));
3617 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3618 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3620 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3622 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3623 emit_thumb32_expr (exp
);
3625 emit_expr (exp
, (unsigned int) size
);
3627 it_fsm_post_encode ();
3631 as_bad (_("cannot determine Thumb instruction size. " \
3632 "Use .inst.n/.inst.w instead"));
3635 as_bad (_("constant expression required"));
3640 /* Like s_arm_elf_cons but do not use md_cons_align and
3641 set the mapping state to MAP_ARM/MAP_THUMB. */
3644 s_arm_elf_inst (int nbytes
)
3646 if (is_it_end_of_statement ())
3648 demand_empty_rest_of_line ();
3652 /* Calling mapping_state () here will not change ARM/THUMB,
3653 but will ensure not to be in DATA state. */
3656 mapping_state (MAP_THUMB
);
3661 as_bad (_("width suffixes are invalid in ARM mode"));
3662 ignore_rest_of_line ();
3668 mapping_state (MAP_ARM
);
3677 if (! emit_insn (& exp
, nbytes
))
3679 ignore_rest_of_line ();
3683 while (*input_line_pointer
++ == ',');
3685 /* Put terminator back into stream. */
3686 input_line_pointer
--;
3687 demand_empty_rest_of_line ();
3690 /* Parse a .rel31 directive. */
3693 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3700 if (*input_line_pointer
== '1')
3701 highbit
= 0x80000000;
3702 else if (*input_line_pointer
!= '0')
3703 as_bad (_("expected 0 or 1"));
3705 input_line_pointer
++;
3706 if (*input_line_pointer
!= ',')
3707 as_bad (_("missing comma"));
3708 input_line_pointer
++;
3710 #ifdef md_flush_pending_output
3711 md_flush_pending_output ();
3714 #ifdef md_cons_align
3718 mapping_state (MAP_DATA
);
3723 md_number_to_chars (p
, highbit
, 4);
3724 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3725 BFD_RELOC_ARM_PREL31
);
3727 demand_empty_rest_of_line ();
3730 /* Directives: AEABI stack-unwind tables. */
3732 /* Parse an unwind_fnstart directive. Simply records the current location. */
3735 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3737 demand_empty_rest_of_line ();
3738 if (unwind
.proc_start
)
3740 as_bad (_("duplicate .fnstart directive"));
3744 /* Mark the start of the function. */
3745 unwind
.proc_start
= expr_build_dot ();
3747 /* Reset the rest of the unwind info. */
3748 unwind
.opcode_count
= 0;
3749 unwind
.table_entry
= NULL
;
3750 unwind
.personality_routine
= NULL
;
3751 unwind
.personality_index
= -1;
3752 unwind
.frame_size
= 0;
3753 unwind
.fp_offset
= 0;
3754 unwind
.fp_reg
= REG_SP
;
3756 unwind
.sp_restored
= 0;
3760 /* Parse a handlerdata directive. Creates the exception handling table entry
3761 for the function. */
3764 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3766 demand_empty_rest_of_line ();
3767 if (!unwind
.proc_start
)
3768 as_bad (MISSING_FNSTART
);
3770 if (unwind
.table_entry
)
3771 as_bad (_("duplicate .handlerdata directive"));
3773 create_unwind_entry (1);
3776 /* Parse an unwind_fnend directive. Generates the index table entry. */
3779 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3784 unsigned int marked_pr_dependency
;
3786 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3790 as_bad (_(".fnend directive without .fnstart"));
3794 /* Add eh table entry. */
3795 if (unwind
.table_entry
== NULL
)
3796 val
= create_unwind_entry (0);
3800 /* Add index table entry. This is two words. */
3801 start_unwind_section (unwind
.saved_seg
, 1);
3802 frag_align (2, 0, 0);
3803 record_alignment (now_seg
, 2);
3805 ptr
= frag_more (8);
3807 where
= frag_now_fix () - 8;
3809 /* Self relative offset of the function start. */
3810 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3811 BFD_RELOC_ARM_PREL31
);
3813 /* Indicate dependency on EHABI-defined personality routines to the
3814 linker, if it hasn't been done already. */
3815 marked_pr_dependency
3816 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3817 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3818 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3820 static const char *const name
[] =
3822 "__aeabi_unwind_cpp_pr0",
3823 "__aeabi_unwind_cpp_pr1",
3824 "__aeabi_unwind_cpp_pr2"
3826 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3827 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3828 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3829 |= 1 << unwind
.personality_index
;
3833 /* Inline exception table entry. */
3834 md_number_to_chars (ptr
+ 4, val
, 4);
3836 /* Self relative offset of the table entry. */
3837 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3838 BFD_RELOC_ARM_PREL31
);
3840 /* Restore the original section. */
3841 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3843 unwind
.proc_start
= NULL
;
3847 /* Parse an unwind_cantunwind directive. */
3850 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3852 demand_empty_rest_of_line ();
3853 if (!unwind
.proc_start
)
3854 as_bad (MISSING_FNSTART
);
3856 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3857 as_bad (_("personality routine specified for cantunwind frame"));
3859 unwind
.personality_index
= -2;
3863 /* Parse a personalityindex directive. */
3866 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3870 if (!unwind
.proc_start
)
3871 as_bad (MISSING_FNSTART
);
3873 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3874 as_bad (_("duplicate .personalityindex directive"));
3878 if (exp
.X_op
!= O_constant
3879 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3881 as_bad (_("bad personality routine number"));
3882 ignore_rest_of_line ();
3886 unwind
.personality_index
= exp
.X_add_number
;
3888 demand_empty_rest_of_line ();
3892 /* Parse a personality directive. */
3895 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3899 if (!unwind
.proc_start
)
3900 as_bad (MISSING_FNSTART
);
3902 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3903 as_bad (_("duplicate .personality directive"));
3905 c
= get_symbol_name (& name
);
3906 p
= input_line_pointer
;
3908 ++ input_line_pointer
;
3909 unwind
.personality_routine
= symbol_find_or_make (name
);
3911 demand_empty_rest_of_line ();
3915 /* Parse a directive saving core registers. */
3918 s_arm_unwind_save_core (void)
3924 range
= parse_reg_list (&input_line_pointer
);
3927 as_bad (_("expected register list"));
3928 ignore_rest_of_line ();
3932 demand_empty_rest_of_line ();
3934 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3935 into .unwind_save {..., sp...}. We aren't bothered about the value of
3936 ip because it is clobbered by calls. */
3937 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3938 && (range
& 0x3000) == 0x1000)
3940 unwind
.opcode_count
--;
3941 unwind
.sp_restored
= 0;
3942 range
= (range
| 0x2000) & ~0x1000;
3943 unwind
.pending_offset
= 0;
3949 /* See if we can use the short opcodes. These pop a block of up to 8
3950 registers starting with r4, plus maybe r14. */
3951 for (n
= 0; n
< 8; n
++)
3953 /* Break at the first non-saved register. */
3954 if ((range
& (1 << (n
+ 4))) == 0)
3957 /* See if there are any other bits set. */
3958 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3960 /* Use the long form. */
3961 op
= 0x8000 | ((range
>> 4) & 0xfff);
3962 add_unwind_opcode (op
, 2);
3966 /* Use the short form. */
3968 op
= 0xa8; /* Pop r14. */
3970 op
= 0xa0; /* Do not pop r14. */
3972 add_unwind_opcode (op
, 1);
3979 op
= 0xb100 | (range
& 0xf);
3980 add_unwind_opcode (op
, 2);
3983 /* Record the number of bytes pushed. */
3984 for (n
= 0; n
< 16; n
++)
3986 if (range
& (1 << n
))
3987 unwind
.frame_size
+= 4;
3992 /* Parse a directive saving FPA registers. */
3995 s_arm_unwind_save_fpa (int reg
)
4001 /* Get Number of registers to transfer. */
4002 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4005 exp
.X_op
= O_illegal
;
4007 if (exp
.X_op
!= O_constant
)
4009 as_bad (_("expected , <constant>"));
4010 ignore_rest_of_line ();
4014 num_regs
= exp
.X_add_number
;
4016 if (num_regs
< 1 || num_regs
> 4)
4018 as_bad (_("number of registers must be in the range [1:4]"));
4019 ignore_rest_of_line ();
4023 demand_empty_rest_of_line ();
4028 op
= 0xb4 | (num_regs
- 1);
4029 add_unwind_opcode (op
, 1);
4034 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4035 add_unwind_opcode (op
, 2);
4037 unwind
.frame_size
+= num_regs
* 12;
4041 /* Parse a directive saving VFP registers for ARMv6 and above. */
4044 s_arm_unwind_save_vfp_armv6 (void)
4049 int num_vfpv3_regs
= 0;
4050 int num_regs_below_16
;
4052 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4055 as_bad (_("expected register list"));
4056 ignore_rest_of_line ();
4060 demand_empty_rest_of_line ();
4062 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4063 than FSTMX/FLDMX-style ones). */
4065 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4067 num_vfpv3_regs
= count
;
4068 else if (start
+ count
> 16)
4069 num_vfpv3_regs
= start
+ count
- 16;
4071 if (num_vfpv3_regs
> 0)
4073 int start_offset
= start
> 16 ? start
- 16 : 0;
4074 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4075 add_unwind_opcode (op
, 2);
4078 /* Generate opcode for registers numbered in the range 0 .. 15. */
4079 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4080 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4081 if (num_regs_below_16
> 0)
4083 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4084 add_unwind_opcode (op
, 2);
4087 unwind
.frame_size
+= count
* 8;
4091 /* Parse a directive saving VFP registers for pre-ARMv6. */
4094 s_arm_unwind_save_vfp (void)
4100 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4103 as_bad (_("expected register list"));
4104 ignore_rest_of_line ();
4108 demand_empty_rest_of_line ();
4113 op
= 0xb8 | (count
- 1);
4114 add_unwind_opcode (op
, 1);
4119 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4120 add_unwind_opcode (op
, 2);
4122 unwind
.frame_size
+= count
* 8 + 4;
4126 /* Parse a directive saving iWMMXt data registers. */
4129 s_arm_unwind_save_mmxwr (void)
4137 if (*input_line_pointer
== '{')
4138 input_line_pointer
++;
4142 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4146 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4151 as_tsktsk (_("register list not in ascending order"));
4154 if (*input_line_pointer
== '-')
4156 input_line_pointer
++;
4157 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4160 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4163 else if (reg
>= hi_reg
)
4165 as_bad (_("bad register range"));
4168 for (; reg
< hi_reg
; reg
++)
4172 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4174 skip_past_char (&input_line_pointer
, '}');
4176 demand_empty_rest_of_line ();
4178 /* Generate any deferred opcodes because we're going to be looking at
4180 flush_pending_unwind ();
4182 for (i
= 0; i
< 16; i
++)
4184 if (mask
& (1 << i
))
4185 unwind
.frame_size
+= 8;
4188 /* Attempt to combine with a previous opcode. We do this because gcc
4189 likes to output separate unwind directives for a single block of
4191 if (unwind
.opcode_count
> 0)
4193 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4194 if ((i
& 0xf8) == 0xc0)
4197 /* Only merge if the blocks are contiguous. */
4200 if ((mask
& 0xfe00) == (1 << 9))
4202 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4203 unwind
.opcode_count
--;
4206 else if (i
== 6 && unwind
.opcode_count
>= 2)
4208 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4212 op
= 0xffff << (reg
- 1);
4214 && ((mask
& op
) == (1u << (reg
- 1))))
4216 op
= (1 << (reg
+ i
+ 1)) - 1;
4217 op
&= ~((1 << reg
) - 1);
4219 unwind
.opcode_count
-= 2;
4226 /* We want to generate opcodes in the order the registers have been
4227 saved, ie. descending order. */
4228 for (reg
= 15; reg
>= -1; reg
--)
4230 /* Save registers in blocks. */
4232 || !(mask
& (1 << reg
)))
4234 /* We found an unsaved reg. Generate opcodes to save the
4241 op
= 0xc0 | (hi_reg
- 10);
4242 add_unwind_opcode (op
, 1);
4247 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4248 add_unwind_opcode (op
, 2);
4257 ignore_rest_of_line ();
4261 s_arm_unwind_save_mmxwcg (void)
4268 if (*input_line_pointer
== '{')
4269 input_line_pointer
++;
4271 skip_whitespace (input_line_pointer
);
4275 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4279 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4285 as_tsktsk (_("register list not in ascending order"));
4288 if (*input_line_pointer
== '-')
4290 input_line_pointer
++;
4291 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4294 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4297 else if (reg
>= hi_reg
)
4299 as_bad (_("bad register range"));
4302 for (; reg
< hi_reg
; reg
++)
4306 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4308 skip_past_char (&input_line_pointer
, '}');
4310 demand_empty_rest_of_line ();
4312 /* Generate any deferred opcodes because we're going to be looking at
4314 flush_pending_unwind ();
4316 for (reg
= 0; reg
< 16; reg
++)
4318 if (mask
& (1 << reg
))
4319 unwind
.frame_size
+= 4;
4322 add_unwind_opcode (op
, 2);
4325 ignore_rest_of_line ();
4329 /* Parse an unwind_save directive.
4330 If the argument is non-zero, this is a .vsave directive. */
4333 s_arm_unwind_save (int arch_v6
)
4336 struct reg_entry
*reg
;
4337 bfd_boolean had_brace
= FALSE
;
4339 if (!unwind
.proc_start
)
4340 as_bad (MISSING_FNSTART
);
4342 /* Figure out what sort of save we have. */
4343 peek
= input_line_pointer
;
4351 reg
= arm_reg_parse_multi (&peek
);
4355 as_bad (_("register expected"));
4356 ignore_rest_of_line ();
4365 as_bad (_("FPA .unwind_save does not take a register list"));
4366 ignore_rest_of_line ();
4369 input_line_pointer
= peek
;
4370 s_arm_unwind_save_fpa (reg
->number
);
4374 s_arm_unwind_save_core ();
4379 s_arm_unwind_save_vfp_armv6 ();
4381 s_arm_unwind_save_vfp ();
4384 case REG_TYPE_MMXWR
:
4385 s_arm_unwind_save_mmxwr ();
4388 case REG_TYPE_MMXWCG
:
4389 s_arm_unwind_save_mmxwcg ();
4393 as_bad (_(".unwind_save does not support this kind of register"));
4394 ignore_rest_of_line ();
4399 /* Parse an unwind_movsp directive. */
4402 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4408 if (!unwind
.proc_start
)
4409 as_bad (MISSING_FNSTART
);
4411 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4414 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4415 ignore_rest_of_line ();
4419 /* Optional constant. */
4420 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4422 if (immediate_for_directive (&offset
) == FAIL
)
4428 demand_empty_rest_of_line ();
4430 if (reg
== REG_SP
|| reg
== REG_PC
)
4432 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4436 if (unwind
.fp_reg
!= REG_SP
)
4437 as_bad (_("unexpected .unwind_movsp directive"));
4439 /* Generate opcode to restore the value. */
4441 add_unwind_opcode (op
, 1);
4443 /* Record the information for later. */
4444 unwind
.fp_reg
= reg
;
4445 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4446 unwind
.sp_restored
= 1;
4449 /* Parse an unwind_pad directive. */
4452 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4456 if (!unwind
.proc_start
)
4457 as_bad (MISSING_FNSTART
);
4459 if (immediate_for_directive (&offset
) == FAIL
)
4464 as_bad (_("stack increment must be multiple of 4"));
4465 ignore_rest_of_line ();
4469 /* Don't generate any opcodes, just record the details for later. */
4470 unwind
.frame_size
+= offset
;
4471 unwind
.pending_offset
+= offset
;
4473 demand_empty_rest_of_line ();
4476 /* Parse an unwind_setfp directive. */
4479 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4485 if (!unwind
.proc_start
)
4486 as_bad (MISSING_FNSTART
);
4488 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4489 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4492 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4494 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4496 as_bad (_("expected <reg>, <reg>"));
4497 ignore_rest_of_line ();
4501 /* Optional constant. */
4502 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4504 if (immediate_for_directive (&offset
) == FAIL
)
4510 demand_empty_rest_of_line ();
4512 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4514 as_bad (_("register must be either sp or set by a previous"
4515 "unwind_movsp directive"));
4519 /* Don't generate any opcodes, just record the information for later. */
4520 unwind
.fp_reg
= fp_reg
;
4522 if (sp_reg
== REG_SP
)
4523 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4525 unwind
.fp_offset
-= offset
;
4528 /* Parse an unwind_raw directive. */
4531 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4534 /* This is an arbitrary limit. */
4535 unsigned char op
[16];
4538 if (!unwind
.proc_start
)
4539 as_bad (MISSING_FNSTART
);
4542 if (exp
.X_op
== O_constant
4543 && skip_past_comma (&input_line_pointer
) != FAIL
)
4545 unwind
.frame_size
+= exp
.X_add_number
;
4549 exp
.X_op
= O_illegal
;
4551 if (exp
.X_op
!= O_constant
)
4553 as_bad (_("expected <offset>, <opcode>"));
4554 ignore_rest_of_line ();
4560 /* Parse the opcode. */
4565 as_bad (_("unwind opcode too long"));
4566 ignore_rest_of_line ();
4568 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4570 as_bad (_("invalid unwind opcode"));
4571 ignore_rest_of_line ();
4574 op
[count
++] = exp
.X_add_number
;
4576 /* Parse the next byte. */
4577 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4583 /* Add the opcode bytes in reverse order. */
4585 add_unwind_opcode (op
[count
], 1);
4587 demand_empty_rest_of_line ();
4591 /* Parse a .eabi_attribute directive. */
4594 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4596 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4598 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4599 attributes_set_explicitly
[tag
] = 1;
4602 /* Emit a tls fix for the symbol. */
4605 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4609 #ifdef md_flush_pending_output
4610 md_flush_pending_output ();
4613 #ifdef md_cons_align
4617 /* Since we're just labelling the code, there's no need to define a
4620 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4621 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4622 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4623 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4625 #endif /* OBJ_ELF */
4627 static void s_arm_arch (int);
4628 static void s_arm_object_arch (int);
4629 static void s_arm_cpu (int);
4630 static void s_arm_fpu (int);
4631 static void s_arm_arch_extension (int);
4636 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4643 if (exp
.X_op
== O_symbol
)
4644 exp
.X_op
= O_secrel
;
4646 emit_expr (&exp
, 4);
4648 while (*input_line_pointer
++ == ',');
4650 input_line_pointer
--;
4651 demand_empty_rest_of_line ();
4655 /* This table describes all the machine specific pseudo-ops the assembler
4656 has to support. The fields are:
4657 pseudo-op name without dot
4658 function to call to execute this pseudo-op
4659 Integer arg to pass to the function. */
4661 const pseudo_typeS md_pseudo_table
[] =
4663 /* Never called because '.req' does not start a line. */
4664 { "req", s_req
, 0 },
4665 /* Following two are likewise never called. */
4668 { "unreq", s_unreq
, 0 },
4669 { "bss", s_bss
, 0 },
4670 { "align", s_align_ptwo
, 2 },
4671 { "arm", s_arm
, 0 },
4672 { "thumb", s_thumb
, 0 },
4673 { "code", s_code
, 0 },
4674 { "force_thumb", s_force_thumb
, 0 },
4675 { "thumb_func", s_thumb_func
, 0 },
4676 { "thumb_set", s_thumb_set
, 0 },
4677 { "even", s_even
, 0 },
4678 { "ltorg", s_ltorg
, 0 },
4679 { "pool", s_ltorg
, 0 },
4680 { "syntax", s_syntax
, 0 },
4681 { "cpu", s_arm_cpu
, 0 },
4682 { "arch", s_arm_arch
, 0 },
4683 { "object_arch", s_arm_object_arch
, 0 },
4684 { "fpu", s_arm_fpu
, 0 },
4685 { "arch_extension", s_arm_arch_extension
, 0 },
4687 { "word", s_arm_elf_cons
, 4 },
4688 { "long", s_arm_elf_cons
, 4 },
4689 { "inst.n", s_arm_elf_inst
, 2 },
4690 { "inst.w", s_arm_elf_inst
, 4 },
4691 { "inst", s_arm_elf_inst
, 0 },
4692 { "rel31", s_arm_rel31
, 0 },
4693 { "fnstart", s_arm_unwind_fnstart
, 0 },
4694 { "fnend", s_arm_unwind_fnend
, 0 },
4695 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4696 { "personality", s_arm_unwind_personality
, 0 },
4697 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4698 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4699 { "save", s_arm_unwind_save
, 0 },
4700 { "vsave", s_arm_unwind_save
, 1 },
4701 { "movsp", s_arm_unwind_movsp
, 0 },
4702 { "pad", s_arm_unwind_pad
, 0 },
4703 { "setfp", s_arm_unwind_setfp
, 0 },
4704 { "unwind_raw", s_arm_unwind_raw
, 0 },
4705 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4706 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4710 /* These are used for dwarf. */
4714 /* These are used for dwarf2. */
4715 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4716 { "loc", dwarf2_directive_loc
, 0 },
4717 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4719 { "extend", float_cons
, 'x' },
4720 { "ldouble", float_cons
, 'x' },
4721 { "packed", float_cons
, 'p' },
4723 {"secrel32", pe_directive_secrel
, 0},
4726 /* These are for compatibility with CodeComposer Studio. */
4727 {"ref", s_ccs_ref
, 0},
4728 {"def", s_ccs_def
, 0},
4729 {"asmfunc", s_ccs_asmfunc
, 0},
4730 {"endasmfunc", s_ccs_endasmfunc
, 0},
4735 /* Parser functions used exclusively in instruction operands. */
4737 /* Generic immediate-value read function for use in insn parsing.
4738 STR points to the beginning of the immediate (the leading #);
4739 VAL receives the value; if the value is outside [MIN, MAX]
4740 issue an error. PREFIX_OPT is true if the immediate prefix is
4744 parse_immediate (char **str
, int *val
, int min
, int max
,
4745 bfd_boolean prefix_opt
)
4748 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4749 if (exp
.X_op
!= O_constant
)
4751 inst
.error
= _("constant expression required");
4755 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4757 inst
.error
= _("immediate value out of range");
4761 *val
= exp
.X_add_number
;
4765 /* Less-generic immediate-value read function with the possibility of loading a
4766 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4767 instructions. Puts the result directly in inst.operands[i]. */
4770 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4771 bfd_boolean allow_symbol_p
)
4774 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4777 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4779 if (exp_p
->X_op
== O_constant
)
4781 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4782 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4783 O_constant. We have to be careful not to break compilation for
4784 32-bit X_add_number, though. */
4785 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4787 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4788 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4790 inst
.operands
[i
].regisimm
= 1;
4793 else if (exp_p
->X_op
== O_big
4794 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4796 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4798 /* Bignums have their least significant bits in
4799 generic_bignum[0]. Make sure we put 32 bits in imm and
4800 32 bits in reg, in a (hopefully) portable way. */
4801 gas_assert (parts
!= 0);
4803 /* Make sure that the number is not too big.
4804 PR 11972: Bignums can now be sign-extended to the
4805 size of a .octa so check that the out of range bits
4806 are all zero or all one. */
4807 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4809 LITTLENUM_TYPE m
= -1;
4811 if (generic_bignum
[parts
* 2] != 0
4812 && generic_bignum
[parts
* 2] != m
)
4815 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4816 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4820 inst
.operands
[i
].imm
= 0;
4821 for (j
= 0; j
< parts
; j
++, idx
++)
4822 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4823 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4824 inst
.operands
[i
].reg
= 0;
4825 for (j
= 0; j
< parts
; j
++, idx
++)
4826 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4827 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4828 inst
.operands
[i
].regisimm
= 1;
4830 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4838 /* Returns the pseudo-register number of an FPA immediate constant,
4839 or FAIL if there isn't a valid constant here. */
4842 parse_fpa_immediate (char ** str
)
4844 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4850 /* First try and match exact strings, this is to guarantee
4851 that some formats will work even for cross assembly. */
4853 for (i
= 0; fp_const
[i
]; i
++)
4855 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4859 *str
+= strlen (fp_const
[i
]);
4860 if (is_end_of_line
[(unsigned char) **str
])
4866 /* Just because we didn't get a match doesn't mean that the constant
4867 isn't valid, just that it is in a format that we don't
4868 automatically recognize. Try parsing it with the standard
4869 expression routines. */
4871 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4873 /* Look for a raw floating point number. */
4874 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4875 && is_end_of_line
[(unsigned char) *save_in
])
4877 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4879 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4881 if (words
[j
] != fp_values
[i
][j
])
4885 if (j
== MAX_LITTLENUMS
)
4893 /* Try and parse a more complex expression, this will probably fail
4894 unless the code uses a floating point prefix (eg "0f"). */
4895 save_in
= input_line_pointer
;
4896 input_line_pointer
= *str
;
4897 if (expression (&exp
) == absolute_section
4898 && exp
.X_op
== O_big
4899 && exp
.X_add_number
< 0)
4901 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4903 #define X_PRECISION 5
4904 #define E_PRECISION 15L
4905 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4907 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4909 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4911 if (words
[j
] != fp_values
[i
][j
])
4915 if (j
== MAX_LITTLENUMS
)
4917 *str
= input_line_pointer
;
4918 input_line_pointer
= save_in
;
4925 *str
= input_line_pointer
;
4926 input_line_pointer
= save_in
;
4927 inst
.error
= _("invalid FPA immediate expression");
4931 /* Returns 1 if a number has "quarter-precision" float format
4932 0baBbbbbbc defgh000 00000000 00000000. */
4935 is_quarter_float (unsigned imm
)
4937 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4938 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4942 /* Detect the presence of a floating point or integer zero constant,
4946 parse_ifimm_zero (char **in
)
4950 if (!is_immediate_prefix (**in
))
4955 /* Accept #0x0 as a synonym for #0. */
4956 if (strncmp (*in
, "0x", 2) == 0)
4959 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4964 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4965 &generic_floating_point_number
);
4968 && generic_floating_point_number
.sign
== '+'
4969 && (generic_floating_point_number
.low
4970 > generic_floating_point_number
.leader
))
4976 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4977 0baBbbbbbc defgh000 00000000 00000000.
4978 The zero and minus-zero cases need special handling, since they can't be
4979 encoded in the "quarter-precision" float format, but can nonetheless be
4980 loaded as integer constants. */
4983 parse_qfloat_immediate (char **ccp
, int *immed
)
4987 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4988 int found_fpchar
= 0;
4990 skip_past_char (&str
, '#');
4992 /* We must not accidentally parse an integer as a floating-point number. Make
4993 sure that the value we parse is not an integer by checking for special
4994 characters '.' or 'e'.
4995 FIXME: This is a horrible hack, but doing better is tricky because type
4996 information isn't in a very usable state at parse time. */
4998 skip_whitespace (fpnum
);
5000 if (strncmp (fpnum
, "0x", 2) == 0)
5004 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5005 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5015 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5017 unsigned fpword
= 0;
5020 /* Our FP word must be 32 bits (single-precision FP). */
5021 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5023 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5027 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5040 /* Shift operands. */
5043 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5046 struct asm_shift_name
5049 enum shift_kind kind
;
5052 /* Third argument to parse_shift. */
5053 enum parse_shift_mode
5055 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5056 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5057 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5058 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5059 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5062 /* Parse a <shift> specifier on an ARM data processing instruction.
5063 This has three forms:
5065 (LSL|LSR|ASL|ASR|ROR) Rs
5066 (LSL|LSR|ASL|ASR|ROR) #imm
5069 Note that ASL is assimilated to LSL in the instruction encoding, and
5070 RRX to ROR #0 (which cannot be written as such). */
5073 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5075 const struct asm_shift_name
*shift_name
;
5076 enum shift_kind shift
;
5081 for (p
= *str
; ISALPHA (*p
); p
++)
5086 inst
.error
= _("shift expression expected");
5090 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5093 if (shift_name
== NULL
)
5095 inst
.error
= _("shift expression expected");
5099 shift
= shift_name
->kind
;
5103 case NO_SHIFT_RESTRICT
:
5104 case SHIFT_IMMEDIATE
: break;
5106 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5107 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5109 inst
.error
= _("'LSL' or 'ASR' required");
5114 case SHIFT_LSL_IMMEDIATE
:
5115 if (shift
!= SHIFT_LSL
)
5117 inst
.error
= _("'LSL' required");
5122 case SHIFT_ASR_IMMEDIATE
:
5123 if (shift
!= SHIFT_ASR
)
5125 inst
.error
= _("'ASR' required");
5133 if (shift
!= SHIFT_RRX
)
5135 /* Whitespace can appear here if the next thing is a bare digit. */
5136 skip_whitespace (p
);
5138 if (mode
== NO_SHIFT_RESTRICT
5139 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5141 inst
.operands
[i
].imm
= reg
;
5142 inst
.operands
[i
].immisreg
= 1;
5144 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5147 inst
.operands
[i
].shift_kind
= shift
;
5148 inst
.operands
[i
].shifted
= 1;
5153 /* Parse a <shifter_operand> for an ARM data processing instruction:
5156 #<immediate>, <rotate>
5160 where <shift> is defined by parse_shift above, and <rotate> is a
5161 multiple of 2 between 0 and 30. Validation of immediate operands
5162 is deferred to md_apply_fix. */
5165 parse_shifter_operand (char **str
, int i
)
5170 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5172 inst
.operands
[i
].reg
= value
;
5173 inst
.operands
[i
].isreg
= 1;
5175 /* parse_shift will override this if appropriate */
5176 inst
.reloc
.exp
.X_op
= O_constant
;
5177 inst
.reloc
.exp
.X_add_number
= 0;
5179 if (skip_past_comma (str
) == FAIL
)
5182 /* Shift operation on register. */
5183 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5186 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5189 if (skip_past_comma (str
) == SUCCESS
)
5191 /* #x, y -- ie explicit rotation by Y. */
5192 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5195 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5197 inst
.error
= _("constant expression expected");
5201 value
= exp
.X_add_number
;
5202 if (value
< 0 || value
> 30 || value
% 2 != 0)
5204 inst
.error
= _("invalid rotation");
5207 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5209 inst
.error
= _("invalid constant");
5213 /* Encode as specified. */
5214 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5218 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5219 inst
.reloc
.pc_rel
= 0;
5223 /* Group relocation information. Each entry in the table contains the
5224 textual name of the relocation as may appear in assembler source
5225 and must end with a colon.
5226 Along with this textual name are the relocation codes to be used if
5227 the corresponding instruction is an ALU instruction (ADD or SUB only),
5228 an LDR, an LDRS, or an LDC. */
5230 struct group_reloc_table_entry
5241 /* Varieties of non-ALU group relocation. */
5248 static struct group_reloc_table_entry group_reloc_table
[] =
5249 { /* Program counter relative: */
5251 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5256 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5257 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5258 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5259 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5261 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5266 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5267 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5268 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5269 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5271 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5272 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5273 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5274 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5275 /* Section base relative */
5277 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5282 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5283 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5284 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5285 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5287 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5292 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5293 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5297 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5298 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5299 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5300 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5301 /* Absolute thumb alu relocations. */
5303 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5308 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5313 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5318 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5323 /* Given the address of a pointer pointing to the textual name of a group
5324 relocation as may appear in assembler source, attempt to find its details
5325 in group_reloc_table. The pointer will be updated to the character after
5326 the trailing colon. On failure, FAIL will be returned; SUCCESS
5327 otherwise. On success, *entry will be updated to point at the relevant
5328 group_reloc_table entry. */
5331 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5334 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5336 int length
= strlen (group_reloc_table
[i
].name
);
5338 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5339 && (*str
)[length
] == ':')
5341 *out
= &group_reloc_table
[i
];
5342 *str
+= (length
+ 1);
5350 /* Parse a <shifter_operand> for an ARM data processing instruction
5351 (as for parse_shifter_operand) where group relocations are allowed:
5354 #<immediate>, <rotate>
5355 #:<group_reloc>:<expression>
5359 where <group_reloc> is one of the strings defined in group_reloc_table.
5360 The hashes are optional.
5362 Everything else is as for parse_shifter_operand. */
5364 static parse_operand_result
5365 parse_shifter_operand_group_reloc (char **str
, int i
)
5367 /* Determine if we have the sequence of characters #: or just :
5368 coming next. If we do, then we check for a group relocation.
5369 If we don't, punt the whole lot to parse_shifter_operand. */
5371 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5372 || (*str
)[0] == ':')
5374 struct group_reloc_table_entry
*entry
;
5376 if ((*str
)[0] == '#')
5381 /* Try to parse a group relocation. Anything else is an error. */
5382 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5384 inst
.error
= _("unknown group relocation");
5385 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5388 /* We now have the group relocation table entry corresponding to
5389 the name in the assembler source. Next, we parse the expression. */
5390 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5391 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5393 /* Record the relocation type (always the ALU variant here). */
5394 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5395 gas_assert (inst
.reloc
.type
!= 0);
5397 return PARSE_OPERAND_SUCCESS
;
5400 return parse_shifter_operand (str
, i
) == SUCCESS
5401 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5403 /* Never reached. */
5406 /* Parse a Neon alignment expression. Information is written to
5407 inst.operands[i]. We assume the initial ':' has been skipped.
5409 align .imm = align << 8, .immisalign=1, .preind=0 */
5410 static parse_operand_result
5411 parse_neon_alignment (char **str
, int i
)
5416 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5418 if (exp
.X_op
!= O_constant
)
5420 inst
.error
= _("alignment must be constant");
5421 return PARSE_OPERAND_FAIL
;
5424 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5425 inst
.operands
[i
].immisalign
= 1;
5426 /* Alignments are not pre-indexes. */
5427 inst
.operands
[i
].preind
= 0;
5430 return PARSE_OPERAND_SUCCESS
;
5433 /* Parse all forms of an ARM address expression. Information is written
5434 to inst.operands[i] and/or inst.reloc.
5436 Preindexed addressing (.preind=1):
5438 [Rn, #offset] .reg=Rn .reloc.exp=offset
5439 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5440 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5441 .shift_kind=shift .reloc.exp=shift_imm
5443 These three may have a trailing ! which causes .writeback to be set also.
5445 Postindexed addressing (.postind=1, .writeback=1):
5447 [Rn], #offset .reg=Rn .reloc.exp=offset
5448 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5449 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5450 .shift_kind=shift .reloc.exp=shift_imm
5452 Unindexed addressing (.preind=0, .postind=0):
5454 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5458 [Rn]{!} shorthand for [Rn,#0]{!}
5459 =immediate .isreg=0 .reloc.exp=immediate
5460 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5462 It is the caller's responsibility to check for addressing modes not
5463 supported by the instruction, and to set inst.reloc.type. */
5465 static parse_operand_result
5466 parse_address_main (char **str
, int i
, int group_relocations
,
5467 group_reloc_type group_type
)
5472 if (skip_past_char (&p
, '[') == FAIL
)
5474 if (skip_past_char (&p
, '=') == FAIL
)
5476 /* Bare address - translate to PC-relative offset. */
5477 inst
.reloc
.pc_rel
= 1;
5478 inst
.operands
[i
].reg
= REG_PC
;
5479 inst
.operands
[i
].isreg
= 1;
5480 inst
.operands
[i
].preind
= 1;
5482 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5483 return PARSE_OPERAND_FAIL
;
5485 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5486 /*allow_symbol_p=*/TRUE
))
5487 return PARSE_OPERAND_FAIL
;
5490 return PARSE_OPERAND_SUCCESS
;
5493 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5494 skip_whitespace (p
);
5496 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5498 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5499 return PARSE_OPERAND_FAIL
;
5501 inst
.operands
[i
].reg
= reg
;
5502 inst
.operands
[i
].isreg
= 1;
5504 if (skip_past_comma (&p
) == SUCCESS
)
5506 inst
.operands
[i
].preind
= 1;
5509 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5513 inst
.operands
[i
].imm
= reg
;
5514 inst
.operands
[i
].immisreg
= 1;
5516 if (skip_past_comma (&p
) == SUCCESS
)
5517 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5518 return PARSE_OPERAND_FAIL
;
5520 else if (skip_past_char (&p
, ':') == SUCCESS
)
5522 /* FIXME: '@' should be used here, but it's filtered out by generic
5523 code before we get to see it here. This may be subject to
5525 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5527 if (result
!= PARSE_OPERAND_SUCCESS
)
5532 if (inst
.operands
[i
].negative
)
5534 inst
.operands
[i
].negative
= 0;
5538 if (group_relocations
5539 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5541 struct group_reloc_table_entry
*entry
;
5543 /* Skip over the #: or : sequence. */
5549 /* Try to parse a group relocation. Anything else is an
5551 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5553 inst
.error
= _("unknown group relocation");
5554 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5557 /* We now have the group relocation table entry corresponding to
5558 the name in the assembler source. Next, we parse the
5560 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5561 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5563 /* Record the relocation type. */
5567 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5571 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5575 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5582 if (inst
.reloc
.type
== 0)
5584 inst
.error
= _("this group relocation is not allowed on this instruction");
5585 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5591 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5592 return PARSE_OPERAND_FAIL
;
5593 /* If the offset is 0, find out if it's a +0 or -0. */
5594 if (inst
.reloc
.exp
.X_op
== O_constant
5595 && inst
.reloc
.exp
.X_add_number
== 0)
5597 skip_whitespace (q
);
5601 skip_whitespace (q
);
5604 inst
.operands
[i
].negative
= 1;
5609 else if (skip_past_char (&p
, ':') == SUCCESS
)
5611 /* FIXME: '@' should be used here, but it's filtered out by generic code
5612 before we get to see it here. This may be subject to change. */
5613 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5615 if (result
!= PARSE_OPERAND_SUCCESS
)
5619 if (skip_past_char (&p
, ']') == FAIL
)
5621 inst
.error
= _("']' expected");
5622 return PARSE_OPERAND_FAIL
;
5625 if (skip_past_char (&p
, '!') == SUCCESS
)
5626 inst
.operands
[i
].writeback
= 1;
5628 else if (skip_past_comma (&p
) == SUCCESS
)
5630 if (skip_past_char (&p
, '{') == SUCCESS
)
5632 /* [Rn], {expr} - unindexed, with option */
5633 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5634 0, 255, TRUE
) == FAIL
)
5635 return PARSE_OPERAND_FAIL
;
5637 if (skip_past_char (&p
, '}') == FAIL
)
5639 inst
.error
= _("'}' expected at end of 'option' field");
5640 return PARSE_OPERAND_FAIL
;
5642 if (inst
.operands
[i
].preind
)
5644 inst
.error
= _("cannot combine index with option");
5645 return PARSE_OPERAND_FAIL
;
5648 return PARSE_OPERAND_SUCCESS
;
5652 inst
.operands
[i
].postind
= 1;
5653 inst
.operands
[i
].writeback
= 1;
5655 if (inst
.operands
[i
].preind
)
5657 inst
.error
= _("cannot combine pre- and post-indexing");
5658 return PARSE_OPERAND_FAIL
;
5662 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5664 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5666 /* We might be using the immediate for alignment already. If we
5667 are, OR the register number into the low-order bits. */
5668 if (inst
.operands
[i
].immisalign
)
5669 inst
.operands
[i
].imm
|= reg
;
5671 inst
.operands
[i
].imm
= reg
;
5672 inst
.operands
[i
].immisreg
= 1;
5674 if (skip_past_comma (&p
) == SUCCESS
)
5675 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5676 return PARSE_OPERAND_FAIL
;
5681 if (inst
.operands
[i
].negative
)
5683 inst
.operands
[i
].negative
= 0;
5686 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5687 return PARSE_OPERAND_FAIL
;
5688 /* If the offset is 0, find out if it's a +0 or -0. */
5689 if (inst
.reloc
.exp
.X_op
== O_constant
5690 && inst
.reloc
.exp
.X_add_number
== 0)
5692 skip_whitespace (q
);
5696 skip_whitespace (q
);
5699 inst
.operands
[i
].negative
= 1;
5705 /* If at this point neither .preind nor .postind is set, we have a
5706 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5707 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5709 inst
.operands
[i
].preind
= 1;
5710 inst
.reloc
.exp
.X_op
= O_constant
;
5711 inst
.reloc
.exp
.X_add_number
= 0;
5714 return PARSE_OPERAND_SUCCESS
;
5718 parse_address (char **str
, int i
)
5720 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5724 static parse_operand_result
5725 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5727 return parse_address_main (str
, i
, 1, type
);
5730 /* Parse an operand for a MOVW or MOVT instruction. */
5732 parse_half (char **str
)
5737 skip_past_char (&p
, '#');
5738 if (strncasecmp (p
, ":lower16:", 9) == 0)
5739 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5740 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5741 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5743 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5746 skip_whitespace (p
);
5749 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5752 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5754 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5756 inst
.error
= _("constant expression expected");
5759 if (inst
.reloc
.exp
.X_add_number
< 0
5760 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5762 inst
.error
= _("immediate value out of range");
5770 /* Miscellaneous. */
5772 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5773 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5775 parse_psr (char **str
, bfd_boolean lhs
)
5778 unsigned long psr_field
;
5779 const struct asm_psr
*psr
;
5781 bfd_boolean is_apsr
= FALSE
;
5782 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5784 /* PR gas/12698: If the user has specified -march=all then m_profile will
5785 be TRUE, but we want to ignore it in this case as we are building for any
5786 CPU type, including non-m variants. */
5787 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5790 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5791 feature for ease of use and backwards compatibility. */
5793 if (strncasecmp (p
, "SPSR", 4) == 0)
5796 goto unsupported_psr
;
5798 psr_field
= SPSR_BIT
;
5800 else if (strncasecmp (p
, "CPSR", 4) == 0)
5803 goto unsupported_psr
;
5807 else if (strncasecmp (p
, "APSR", 4) == 0)
5809 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5810 and ARMv7-R architecture CPUs. */
5819 while (ISALNUM (*p
) || *p
== '_');
5821 if (strncasecmp (start
, "iapsr", 5) == 0
5822 || strncasecmp (start
, "eapsr", 5) == 0
5823 || strncasecmp (start
, "xpsr", 4) == 0
5824 || strncasecmp (start
, "psr", 3) == 0)
5825 p
= start
+ strcspn (start
, "rR") + 1;
5827 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5833 /* If APSR is being written, a bitfield may be specified. Note that
5834 APSR itself is handled above. */
5835 if (psr
->field
<= 3)
5837 psr_field
= psr
->field
;
5843 /* M-profile MSR instructions have the mask field set to "10", except
5844 *PSR variants which modify APSR, which may use a different mask (and
5845 have been handled already). Do that by setting the PSR_f field
5847 return psr
->field
| (lhs
? PSR_f
: 0);
5850 goto unsupported_psr
;
5856 /* A suffix follows. */
5862 while (ISALNUM (*p
) || *p
== '_');
5866 /* APSR uses a notation for bits, rather than fields. */
5867 unsigned int nzcvq_bits
= 0;
5868 unsigned int g_bit
= 0;
5871 for (bit
= start
; bit
!= p
; bit
++)
5873 switch (TOLOWER (*bit
))
5876 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5880 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5884 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5888 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5892 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5896 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5900 inst
.error
= _("unexpected bit specified after APSR");
5905 if (nzcvq_bits
== 0x1f)
5910 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5912 inst
.error
= _("selected processor does not "
5913 "support DSP extension");
5920 if ((nzcvq_bits
& 0x20) != 0
5921 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5922 || (g_bit
& 0x2) != 0)
5924 inst
.error
= _("bad bitmask specified after APSR");
5930 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5935 psr_field
|= psr
->field
;
5941 goto error
; /* Garbage after "[CS]PSR". */
5943 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5944 is deprecated, but allow it anyway. */
5948 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5951 else if (!m_profile
)
5952 /* These bits are never right for M-profile devices: don't set them
5953 (only code paths which read/write APSR reach here). */
5954 psr_field
|= (PSR_c
| PSR_f
);
5960 inst
.error
= _("selected processor does not support requested special "
5961 "purpose register");
5965 inst
.error
= _("flag for {c}psr instruction expected");
5969 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5970 value suitable for splatting into the AIF field of the instruction. */
5973 parse_cps_flags (char **str
)
5982 case '\0': case ',':
5985 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5986 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5987 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5990 inst
.error
= _("unrecognized CPS flag");
5995 if (saw_a_flag
== 0)
5997 inst
.error
= _("missing CPS flags");
6005 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6006 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6009 parse_endian_specifier (char **str
)
6014 if (strncasecmp (s
, "BE", 2))
6016 else if (strncasecmp (s
, "LE", 2))
6020 inst
.error
= _("valid endian specifiers are be or le");
6024 if (ISALNUM (s
[2]) || s
[2] == '_')
6026 inst
.error
= _("valid endian specifiers are be or le");
6031 return little_endian
;
6034 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6035 value suitable for poking into the rotate field of an sxt or sxta
6036 instruction, or FAIL on error. */
6039 parse_ror (char **str
)
6044 if (strncasecmp (s
, "ROR", 3) == 0)
6048 inst
.error
= _("missing rotation field after comma");
6052 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6057 case 0: *str
= s
; return 0x0;
6058 case 8: *str
= s
; return 0x1;
6059 case 16: *str
= s
; return 0x2;
6060 case 24: *str
= s
; return 0x3;
6063 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6068 /* Parse a conditional code (from conds[] below). The value returned is in the
6069 range 0 .. 14, or FAIL. */
6071 parse_cond (char **str
)
6074 const struct asm_cond
*c
;
6076 /* Condition codes are always 2 characters, so matching up to
6077 3 characters is sufficient. */
6082 while (ISALPHA (*q
) && n
< 3)
6084 cond
[n
] = TOLOWER (*q
);
6089 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6092 inst
.error
= _("condition required");
6100 /* Record a use of the given feature. */
6102 record_feature_use (const arm_feature_set
*feature
)
6105 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6107 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6110 /* If the given feature available in the selected CPU, mark it as used.
6111 Returns TRUE iff feature is available. */
6113 mark_feature_used (const arm_feature_set
*feature
)
6115 /* Ensure the option is valid on the current architecture. */
6116 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6119 /* Add the appropriate architecture feature for the barrier option used.
6121 record_feature_use (feature
);
6126 /* Parse an option for a barrier instruction. Returns the encoding for the
6129 parse_barrier (char **str
)
6132 const struct asm_barrier_opt
*o
;
6135 while (ISALPHA (*q
))
6138 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6143 if (!mark_feature_used (&o
->arch
))
6150 /* Parse the operands of a table branch instruction. Similar to a memory
6153 parse_tb (char **str
)
6158 if (skip_past_char (&p
, '[') == FAIL
)
6160 inst
.error
= _("'[' expected");
6164 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6166 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6169 inst
.operands
[0].reg
= reg
;
6171 if (skip_past_comma (&p
) == FAIL
)
6173 inst
.error
= _("',' expected");
6177 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6179 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6182 inst
.operands
[0].imm
= reg
;
6184 if (skip_past_comma (&p
) == SUCCESS
)
6186 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6188 if (inst
.reloc
.exp
.X_add_number
!= 1)
6190 inst
.error
= _("invalid shift");
6193 inst
.operands
[0].shifted
= 1;
6196 if (skip_past_char (&p
, ']') == FAIL
)
6198 inst
.error
= _("']' expected");
6205 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6206 information on the types the operands can take and how they are encoded.
6207 Up to four operands may be read; this function handles setting the
6208 ".present" field for each read operand itself.
6209 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6210 else returns FAIL. */
6213 parse_neon_mov (char **str
, int *which_operand
)
6215 int i
= *which_operand
, val
;
6216 enum arm_reg_type rtype
;
6218 struct neon_type_el optype
;
6220 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6222 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6223 inst
.operands
[i
].reg
= val
;
6224 inst
.operands
[i
].isscalar
= 1;
6225 inst
.operands
[i
].vectype
= optype
;
6226 inst
.operands
[i
++].present
= 1;
6228 if (skip_past_comma (&ptr
) == FAIL
)
6231 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].present
= 1;
6238 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6241 /* Cases 0, 1, 2, 3, 5 (D only). */
6242 if (skip_past_comma (&ptr
) == FAIL
)
6245 inst
.operands
[i
].reg
= val
;
6246 inst
.operands
[i
].isreg
= 1;
6247 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6248 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6249 inst
.operands
[i
].isvec
= 1;
6250 inst
.operands
[i
].vectype
= optype
;
6251 inst
.operands
[i
++].present
= 1;
6253 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6255 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6256 Case 13: VMOV <Sd>, <Rm> */
6257 inst
.operands
[i
].reg
= val
;
6258 inst
.operands
[i
].isreg
= 1;
6259 inst
.operands
[i
].present
= 1;
6261 if (rtype
== REG_TYPE_NQ
)
6263 first_error (_("can't use Neon quad register here"));
6266 else if (rtype
!= REG_TYPE_VFS
)
6269 if (skip_past_comma (&ptr
) == FAIL
)
6271 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6273 inst
.operands
[i
].reg
= val
;
6274 inst
.operands
[i
].isreg
= 1;
6275 inst
.operands
[i
].present
= 1;
6278 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6281 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6282 Case 1: VMOV<c><q> <Dd>, <Dm>
6283 Case 8: VMOV.F32 <Sd>, <Sm>
6284 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6286 inst
.operands
[i
].reg
= val
;
6287 inst
.operands
[i
].isreg
= 1;
6288 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6289 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6290 inst
.operands
[i
].isvec
= 1;
6291 inst
.operands
[i
].vectype
= optype
;
6292 inst
.operands
[i
].present
= 1;
6294 if (skip_past_comma (&ptr
) == SUCCESS
)
6299 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6302 inst
.operands
[i
].reg
= val
;
6303 inst
.operands
[i
].isreg
= 1;
6304 inst
.operands
[i
++].present
= 1;
6306 if (skip_past_comma (&ptr
) == FAIL
)
6309 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6312 inst
.operands
[i
].reg
= val
;
6313 inst
.operands
[i
].isreg
= 1;
6314 inst
.operands
[i
].present
= 1;
6317 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6318 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6319 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6320 Case 10: VMOV.F32 <Sd>, #<imm>
6321 Case 11: VMOV.F64 <Dd>, #<imm> */
6322 inst
.operands
[i
].immisfloat
= 1;
6323 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6325 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6326 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6330 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6334 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6337 inst
.operands
[i
].reg
= val
;
6338 inst
.operands
[i
].isreg
= 1;
6339 inst
.operands
[i
++].present
= 1;
6341 if (skip_past_comma (&ptr
) == FAIL
)
6344 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6346 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6347 inst
.operands
[i
].reg
= val
;
6348 inst
.operands
[i
].isscalar
= 1;
6349 inst
.operands
[i
].present
= 1;
6350 inst
.operands
[i
].vectype
= optype
;
6352 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6354 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6355 inst
.operands
[i
].reg
= val
;
6356 inst
.operands
[i
].isreg
= 1;
6357 inst
.operands
[i
++].present
= 1;
6359 if (skip_past_comma (&ptr
) == FAIL
)
6362 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6365 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6369 inst
.operands
[i
].reg
= val
;
6370 inst
.operands
[i
].isreg
= 1;
6371 inst
.operands
[i
].isvec
= 1;
6372 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6373 inst
.operands
[i
].vectype
= optype
;
6374 inst
.operands
[i
].present
= 1;
6376 if (rtype
== REG_TYPE_VFS
)
6380 if (skip_past_comma (&ptr
) == FAIL
)
6382 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6385 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6388 inst
.operands
[i
].reg
= val
;
6389 inst
.operands
[i
].isreg
= 1;
6390 inst
.operands
[i
].isvec
= 1;
6391 inst
.operands
[i
].issingle
= 1;
6392 inst
.operands
[i
].vectype
= optype
;
6393 inst
.operands
[i
].present
= 1;
6396 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6400 inst
.operands
[i
].reg
= val
;
6401 inst
.operands
[i
].isreg
= 1;
6402 inst
.operands
[i
].isvec
= 1;
6403 inst
.operands
[i
].issingle
= 1;
6404 inst
.operands
[i
].vectype
= optype
;
6405 inst
.operands
[i
].present
= 1;
6410 first_error (_("parse error"));
6414 /* Successfully parsed the operands. Update args. */
6420 first_error (_("expected comma"));
6424 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6428 /* Use this macro when the operand constraints are different
6429 for ARM and THUMB (e.g. ldrd). */
6430 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6431 ((arm_operand) | ((thumb_operand) << 16))
6433 /* Matcher codes for parse_operands. */
6434 enum operand_parse_code
6436 OP_stop
, /* end of line */
6438 OP_RR
, /* ARM register */
6439 OP_RRnpc
, /* ARM register, not r15 */
6440 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6441 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6442 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6443 optional trailing ! */
6444 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6445 OP_RCP
, /* Coprocessor number */
6446 OP_RCN
, /* Coprocessor register */
6447 OP_RF
, /* FPA register */
6448 OP_RVS
, /* VFP single precision register */
6449 OP_RVD
, /* VFP double precision register (0..15) */
6450 OP_RND
, /* Neon double precision register (0..31) */
6451 OP_RNQ
, /* Neon quad precision register */
6452 OP_RVSD
, /* VFP single or double precision register */
6453 OP_RNDQ
, /* Neon double or quad precision register */
6454 OP_RNSDQ
, /* Neon single, double or quad precision register */
6455 OP_RNSC
, /* Neon scalar D[X] */
6456 OP_RVC
, /* VFP control register */
6457 OP_RMF
, /* Maverick F register */
6458 OP_RMD
, /* Maverick D register */
6459 OP_RMFX
, /* Maverick FX register */
6460 OP_RMDX
, /* Maverick DX register */
6461 OP_RMAX
, /* Maverick AX register */
6462 OP_RMDS
, /* Maverick DSPSC register */
6463 OP_RIWR
, /* iWMMXt wR register */
6464 OP_RIWC
, /* iWMMXt wC register */
6465 OP_RIWG
, /* iWMMXt wCG register */
6466 OP_RXA
, /* XScale accumulator register */
6468 OP_REGLST
, /* ARM register list */
6469 OP_VRSLST
, /* VFP single-precision register list */
6470 OP_VRDLST
, /* VFP double-precision register list */
6471 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6472 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6473 OP_NSTRLST
, /* Neon element/structure list */
6475 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6476 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6477 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6478 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6479 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6480 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6481 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6482 OP_VMOV
, /* Neon VMOV operands. */
6483 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6484 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6485 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6487 OP_I0
, /* immediate zero */
6488 OP_I7
, /* immediate value 0 .. 7 */
6489 OP_I15
, /* 0 .. 15 */
6490 OP_I16
, /* 1 .. 16 */
6491 OP_I16z
, /* 0 .. 16 */
6492 OP_I31
, /* 0 .. 31 */
6493 OP_I31w
, /* 0 .. 31, optional trailing ! */
6494 OP_I32
, /* 1 .. 32 */
6495 OP_I32z
, /* 0 .. 32 */
6496 OP_I63
, /* 0 .. 63 */
6497 OP_I63s
, /* -64 .. 63 */
6498 OP_I64
, /* 1 .. 64 */
6499 OP_I64z
, /* 0 .. 64 */
6500 OP_I255
, /* 0 .. 255 */
6502 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6503 OP_I7b
, /* 0 .. 7 */
6504 OP_I15b
, /* 0 .. 15 */
6505 OP_I31b
, /* 0 .. 31 */
6507 OP_SH
, /* shifter operand */
6508 OP_SHG
, /* shifter operand with possible group relocation */
6509 OP_ADDR
, /* Memory address expression (any mode) */
6510 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6511 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6512 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6513 OP_EXP
, /* arbitrary expression */
6514 OP_EXPi
, /* same, with optional immediate prefix */
6515 OP_EXPr
, /* same, with optional relocation suffix */
6516 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6518 OP_CPSF
, /* CPS flags */
6519 OP_ENDI
, /* Endianness specifier */
6520 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6521 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6522 OP_COND
, /* conditional code */
6523 OP_TB
, /* Table branch. */
6525 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6527 OP_RRnpc_I0
, /* ARM register or literal 0 */
6528 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6529 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6530 OP_RF_IF
, /* FPA register or immediate */
6531 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6532 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6534 /* Optional operands. */
6535 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6536 OP_oI31b
, /* 0 .. 31 */
6537 OP_oI32b
, /* 1 .. 32 */
6538 OP_oI32z
, /* 0 .. 32 */
6539 OP_oIffffb
, /* 0 .. 65535 */
6540 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6542 OP_oRR
, /* ARM register */
6543 OP_oRRnpc
, /* ARM register, not the PC */
6544 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6545 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6546 OP_oRND
, /* Optional Neon double precision register */
6547 OP_oRNQ
, /* Optional Neon quad precision register */
6548 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6549 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6550 OP_oSHll
, /* LSL immediate */
6551 OP_oSHar
, /* ASR immediate */
6552 OP_oSHllar
, /* LSL or ASR immediate */
6553 OP_oROR
, /* ROR 0/8/16/24 */
6554 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6556 /* Some pre-defined mixed (ARM/THUMB) operands. */
6557 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6558 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6559 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6561 OP_FIRST_OPTIONAL
= OP_oI7b
6564 /* Generic instruction operand parser. This does no encoding and no
6565 semantic validation; it merely squirrels values away in the inst
6566 structure. Returns SUCCESS or FAIL depending on whether the
6567 specified grammar matched. */
6569 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6571 unsigned const int *upat
= pattern
;
6572 char *backtrack_pos
= 0;
6573 const char *backtrack_error
= 0;
6574 int i
, val
= 0, backtrack_index
= 0;
6575 enum arm_reg_type rtype
;
6576 parse_operand_result result
;
6577 unsigned int op_parse_code
;
6579 #define po_char_or_fail(chr) \
6582 if (skip_past_char (&str, chr) == FAIL) \
6587 #define po_reg_or_fail(regtype) \
6590 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6591 & inst.operands[i].vectype); \
6594 first_error (_(reg_expected_msgs[regtype])); \
6597 inst.operands[i].reg = val; \
6598 inst.operands[i].isreg = 1; \
6599 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6600 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6601 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6602 || rtype == REG_TYPE_VFD \
6603 || rtype == REG_TYPE_NQ); \
6607 #define po_reg_or_goto(regtype, label) \
6610 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6611 & inst.operands[i].vectype); \
6615 inst.operands[i].reg = val; \
6616 inst.operands[i].isreg = 1; \
6617 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6618 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6619 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6620 || rtype == REG_TYPE_VFD \
6621 || rtype == REG_TYPE_NQ); \
6625 #define po_imm_or_fail(min, max, popt) \
6628 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6630 inst.operands[i].imm = val; \
6634 #define po_scalar_or_goto(elsz, label) \
6637 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6640 inst.operands[i].reg = val; \
6641 inst.operands[i].isscalar = 1; \
6645 #define po_misc_or_fail(expr) \
6653 #define po_misc_or_fail_no_backtrack(expr) \
6657 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6658 backtrack_pos = 0; \
6659 if (result != PARSE_OPERAND_SUCCESS) \
6664 #define po_barrier_or_imm(str) \
6667 val = parse_barrier (&str); \
6668 if (val == FAIL && ! ISALPHA (*str)) \
6671 /* ISB can only take SY as an option. */ \
6672 || ((inst.instruction & 0xf0) == 0x60 \
6675 inst.error = _("invalid barrier type"); \
6676 backtrack_pos = 0; \
6682 skip_whitespace (str
);
6684 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6686 op_parse_code
= upat
[i
];
6687 if (op_parse_code
>= 1<<16)
6688 op_parse_code
= thumb
? (op_parse_code
>> 16)
6689 : (op_parse_code
& ((1<<16)-1));
6691 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6693 /* Remember where we are in case we need to backtrack. */
6694 gas_assert (!backtrack_pos
);
6695 backtrack_pos
= str
;
6696 backtrack_error
= inst
.error
;
6697 backtrack_index
= i
;
6700 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6701 po_char_or_fail (',');
6703 switch (op_parse_code
)
6711 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6712 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6713 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6714 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6715 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6716 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6718 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6720 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6722 /* Also accept generic coprocessor regs for unknown registers. */
6724 po_reg_or_fail (REG_TYPE_CN
);
6726 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6727 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6728 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6729 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6730 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6731 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6732 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6733 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6734 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6735 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6737 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6739 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6740 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6742 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6744 /* Neon scalar. Using an element size of 8 means that some invalid
6745 scalars are accepted here, so deal with those in later code. */
6746 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6750 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6753 po_imm_or_fail (0, 0, TRUE
);
6758 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6763 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6766 if (parse_ifimm_zero (&str
))
6767 inst
.operands
[i
].imm
= 0;
6771 = _("only floating point zero is allowed as immediate value");
6779 po_scalar_or_goto (8, try_rr
);
6782 po_reg_or_fail (REG_TYPE_RN
);
6788 po_scalar_or_goto (8, try_nsdq
);
6791 po_reg_or_fail (REG_TYPE_NSDQ
);
6797 po_scalar_or_goto (8, try_ndq
);
6800 po_reg_or_fail (REG_TYPE_NDQ
);
6806 po_scalar_or_goto (8, try_vfd
);
6809 po_reg_or_fail (REG_TYPE_VFD
);
6814 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6815 not careful then bad things might happen. */
6816 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6821 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6824 /* There's a possibility of getting a 64-bit immediate here, so
6825 we need special handling. */
6826 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6829 inst
.error
= _("immediate value is out of range");
6837 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6840 po_imm_or_fail (0, 63, TRUE
);
6845 po_char_or_fail ('[');
6846 po_reg_or_fail (REG_TYPE_RN
);
6847 po_char_or_fail (']');
6853 po_reg_or_fail (REG_TYPE_RN
);
6854 if (skip_past_char (&str
, '!') == SUCCESS
)
6855 inst
.operands
[i
].writeback
= 1;
6859 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6860 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6861 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6862 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6863 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6864 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6865 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6866 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6867 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6868 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6869 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6870 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6872 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6874 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6875 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6877 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6878 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6879 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6880 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6882 /* Immediate variants */
6884 po_char_or_fail ('{');
6885 po_imm_or_fail (0, 255, TRUE
);
6886 po_char_or_fail ('}');
6890 /* The expression parser chokes on a trailing !, so we have
6891 to find it first and zap it. */
6894 while (*s
&& *s
!= ',')
6899 inst
.operands
[i
].writeback
= 1;
6901 po_imm_or_fail (0, 31, TRUE
);
6909 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6914 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6919 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6921 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6923 val
= parse_reloc (&str
);
6926 inst
.error
= _("unrecognized relocation suffix");
6929 else if (val
!= BFD_RELOC_UNUSED
)
6931 inst
.operands
[i
].imm
= val
;
6932 inst
.operands
[i
].hasreloc
= 1;
6937 /* Operand for MOVW or MOVT. */
6939 po_misc_or_fail (parse_half (&str
));
6942 /* Register or expression. */
6943 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6944 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6946 /* Register or immediate. */
6947 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6948 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6950 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6952 if (!is_immediate_prefix (*str
))
6955 val
= parse_fpa_immediate (&str
);
6958 /* FPA immediates are encoded as registers 8-15.
6959 parse_fpa_immediate has already applied the offset. */
6960 inst
.operands
[i
].reg
= val
;
6961 inst
.operands
[i
].isreg
= 1;
6964 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6965 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6967 /* Two kinds of register. */
6970 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6972 || (rege
->type
!= REG_TYPE_MMXWR
6973 && rege
->type
!= REG_TYPE_MMXWC
6974 && rege
->type
!= REG_TYPE_MMXWCG
))
6976 inst
.error
= _("iWMMXt data or control register expected");
6979 inst
.operands
[i
].reg
= rege
->number
;
6980 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6986 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6988 || (rege
->type
!= REG_TYPE_MMXWC
6989 && rege
->type
!= REG_TYPE_MMXWCG
))
6991 inst
.error
= _("iWMMXt control register expected");
6994 inst
.operands
[i
].reg
= rege
->number
;
6995 inst
.operands
[i
].isreg
= 1;
7000 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7001 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7002 case OP_oROR
: val
= parse_ror (&str
); break;
7003 case OP_COND
: val
= parse_cond (&str
); break;
7004 case OP_oBARRIER_I15
:
7005 po_barrier_or_imm (str
); break;
7007 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7013 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7014 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7016 inst
.error
= _("Banked registers are not available with this "
7022 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7026 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7029 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7031 if (strncasecmp (str
, "APSR_", 5) == 0)
7038 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7039 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7040 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7041 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7042 default: found
= 16;
7046 inst
.operands
[i
].isvec
= 1;
7047 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7048 inst
.operands
[i
].reg
= REG_PC
;
7055 po_misc_or_fail (parse_tb (&str
));
7058 /* Register lists. */
7060 val
= parse_reg_list (&str
);
7063 inst
.operands
[i
].writeback
= 1;
7069 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7073 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7077 /* Allow Q registers too. */
7078 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7083 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7085 inst
.operands
[i
].issingle
= 1;
7090 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7095 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7096 &inst
.operands
[i
].vectype
);
7099 /* Addressing modes */
7101 po_misc_or_fail (parse_address (&str
, i
));
7105 po_misc_or_fail_no_backtrack (
7106 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7110 po_misc_or_fail_no_backtrack (
7111 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7115 po_misc_or_fail_no_backtrack (
7116 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7120 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7124 po_misc_or_fail_no_backtrack (
7125 parse_shifter_operand_group_reloc (&str
, i
));
7129 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7133 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7137 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7141 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7144 /* Various value-based sanity checks and shared operations. We
7145 do not signal immediate failures for the register constraints;
7146 this allows a syntax error to take precedence. */
7147 switch (op_parse_code
)
7155 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7156 inst
.error
= BAD_PC
;
7161 if (inst
.operands
[i
].isreg
)
7163 if (inst
.operands
[i
].reg
== REG_PC
)
7164 inst
.error
= BAD_PC
;
7165 else if (inst
.operands
[i
].reg
== REG_SP
)
7166 inst
.error
= BAD_SP
;
7171 if (inst
.operands
[i
].isreg
7172 && inst
.operands
[i
].reg
== REG_PC
7173 && (inst
.operands
[i
].writeback
|| thumb
))
7174 inst
.error
= BAD_PC
;
7183 case OP_oBARRIER_I15
:
7192 inst
.operands
[i
].imm
= val
;
7199 /* If we get here, this operand was successfully parsed. */
7200 inst
.operands
[i
].present
= 1;
7204 inst
.error
= BAD_ARGS
;
7209 /* The parse routine should already have set inst.error, but set a
7210 default here just in case. */
7212 inst
.error
= _("syntax error");
7216 /* Do not backtrack over a trailing optional argument that
7217 absorbed some text. We will only fail again, with the
7218 'garbage following instruction' error message, which is
7219 probably less helpful than the current one. */
7220 if (backtrack_index
== i
&& backtrack_pos
!= str
7221 && upat
[i
+1] == OP_stop
)
7224 inst
.error
= _("syntax error");
7228 /* Try again, skipping the optional argument at backtrack_pos. */
7229 str
= backtrack_pos
;
7230 inst
.error
= backtrack_error
;
7231 inst
.operands
[backtrack_index
].present
= 0;
7232 i
= backtrack_index
;
7236 /* Check that we have parsed all the arguments. */
7237 if (*str
!= '\0' && !inst
.error
)
7238 inst
.error
= _("garbage following instruction");
7240 return inst
.error
? FAIL
: SUCCESS
;
7243 #undef po_char_or_fail
7244 #undef po_reg_or_fail
7245 #undef po_reg_or_goto
7246 #undef po_imm_or_fail
7247 #undef po_scalar_or_fail
7248 #undef po_barrier_or_imm
7250 /* Shorthand macro for instruction encoding functions issuing errors. */
7251 #define constraint(expr, err) \
7262 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7263 instructions are unpredictable if these registers are used. This
7264 is the BadReg predicate in ARM's Thumb-2 documentation. */
7265 #define reject_bad_reg(reg) \
7267 if (reg == REG_SP || reg == REG_PC) \
7269 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7274 /* If REG is R13 (the stack pointer), warn that its use is
7276 #define warn_deprecated_sp(reg) \
7278 if (warn_on_deprecated && reg == REG_SP) \
7279 as_tsktsk (_("use of r13 is deprecated")); \
7282 /* Functions for operand encoding. ARM, then Thumb. */
7284 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7286 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7288 The only binary encoding difference is the Coprocessor number. Coprocessor
7289 9 is used for half-precision calculations or conversions. The format of the
7290 instruction is the same as the equivalent Coprocessor 10 instuction that
7291 exists for Single-Precision operation. */
7294 do_scalar_fp16_v82_encode (void)
7296 if (inst
.cond
!= COND_ALWAYS
)
7297 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7298 " the behaviour is UNPREDICTABLE"));
7299 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7302 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7303 mark_feature_used (&arm_ext_fp16
);
7306 /* If VAL can be encoded in the immediate field of an ARM instruction,
7307 return the encoded form. Otherwise, return FAIL. */
7310 encode_arm_immediate (unsigned int val
)
7317 for (i
= 2; i
< 32; i
+= 2)
7318 if ((a
= rotate_left (val
, i
)) <= 0xff)
7319 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7324 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7325 return the encoded form. Otherwise, return FAIL. */
7327 encode_thumb32_immediate (unsigned int val
)
7334 for (i
= 1; i
<= 24; i
++)
7337 if ((val
& ~(0xff << i
)) == 0)
7338 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7342 if (val
== ((a
<< 16) | a
))
7344 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7348 if (val
== ((a
<< 16) | a
))
7349 return 0x200 | (a
>> 8);
7353 /* Encode a VFP SP or DP register number into inst.instruction. */
7356 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7358 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7361 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7364 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7367 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7372 first_error (_("D register out of range for selected VFP version"));
7380 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7384 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7388 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7392 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7396 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7400 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7408 /* Encode a <shift> in an ARM-format instruction. The immediate,
7409 if any, is handled by md_apply_fix. */
7411 encode_arm_shift (int i
)
7413 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7414 inst
.instruction
|= SHIFT_ROR
<< 5;
7417 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7418 if (inst
.operands
[i
].immisreg
)
7420 inst
.instruction
|= SHIFT_BY_REG
;
7421 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7424 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7429 encode_arm_shifter_operand (int i
)
7431 if (inst
.operands
[i
].isreg
)
7433 inst
.instruction
|= inst
.operands
[i
].reg
;
7434 encode_arm_shift (i
);
7438 inst
.instruction
|= INST_IMMEDIATE
;
7439 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7440 inst
.instruction
|= inst
.operands
[i
].imm
;
7444 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7446 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7449 Generate an error if the operand is not a register. */
7450 constraint (!inst
.operands
[i
].isreg
,
7451 _("Instruction does not support =N addresses"));
7453 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7455 if (inst
.operands
[i
].preind
)
7459 inst
.error
= _("instruction does not accept preindexed addressing");
7462 inst
.instruction
|= PRE_INDEX
;
7463 if (inst
.operands
[i
].writeback
)
7464 inst
.instruction
|= WRITE_BACK
;
7467 else if (inst
.operands
[i
].postind
)
7469 gas_assert (inst
.operands
[i
].writeback
);
7471 inst
.instruction
|= WRITE_BACK
;
7473 else /* unindexed - only for coprocessor */
7475 inst
.error
= _("instruction does not accept unindexed addressing");
7479 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7480 && (((inst
.instruction
& 0x000f0000) >> 16)
7481 == ((inst
.instruction
& 0x0000f000) >> 12)))
7482 as_warn ((inst
.instruction
& LOAD_BIT
)
7483 ? _("destination register same as write-back base")
7484 : _("source register same as write-back base"));
7487 /* inst.operands[i] was set up by parse_address. Encode it into an
7488 ARM-format mode 2 load or store instruction. If is_t is true,
7489 reject forms that cannot be used with a T instruction (i.e. not
7492 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7494 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7496 encode_arm_addr_mode_common (i
, is_t
);
7498 if (inst
.operands
[i
].immisreg
)
7500 constraint ((inst
.operands
[i
].imm
== REG_PC
7501 || (is_pc
&& inst
.operands
[i
].writeback
)),
7503 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7504 inst
.instruction
|= inst
.operands
[i
].imm
;
7505 if (!inst
.operands
[i
].negative
)
7506 inst
.instruction
|= INDEX_UP
;
7507 if (inst
.operands
[i
].shifted
)
7509 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7510 inst
.instruction
|= SHIFT_ROR
<< 5;
7513 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7514 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7518 else /* immediate offset in inst.reloc */
7520 if (is_pc
&& !inst
.reloc
.pc_rel
)
7522 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7524 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7525 cannot use PC in addressing.
7526 PC cannot be used in writeback addressing, either. */
7527 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7530 /* Use of PC in str is deprecated for ARMv7. */
7531 if (warn_on_deprecated
7533 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7534 as_tsktsk (_("use of PC in this instruction is deprecated"));
7537 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7539 /* Prefer + for zero encoded value. */
7540 if (!inst
.operands
[i
].negative
)
7541 inst
.instruction
|= INDEX_UP
;
7542 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7547 /* inst.operands[i] was set up by parse_address. Encode it into an
7548 ARM-format mode 3 load or store instruction. Reject forms that
7549 cannot be used with such instructions. If is_t is true, reject
7550 forms that cannot be used with a T instruction (i.e. not
7553 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7555 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7557 inst
.error
= _("instruction does not accept scaled register index");
7561 encode_arm_addr_mode_common (i
, is_t
);
7563 if (inst
.operands
[i
].immisreg
)
7565 constraint ((inst
.operands
[i
].imm
== REG_PC
7566 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7568 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7570 inst
.instruction
|= inst
.operands
[i
].imm
;
7571 if (!inst
.operands
[i
].negative
)
7572 inst
.instruction
|= INDEX_UP
;
7574 else /* immediate offset in inst.reloc */
7576 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7577 && inst
.operands
[i
].writeback
),
7579 inst
.instruction
|= HWOFFSET_IMM
;
7580 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7582 /* Prefer + for zero encoded value. */
7583 if (!inst
.operands
[i
].negative
)
7584 inst
.instruction
|= INDEX_UP
;
7586 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7591 /* Write immediate bits [7:0] to the following locations:
7593 |28/24|23 19|18 16|15 4|3 0|
7594 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7596 This function is used by VMOV/VMVN/VORR/VBIC. */
7599 neon_write_immbits (unsigned immbits
)
7601 inst
.instruction
|= immbits
& 0xf;
7602 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7603 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7606 /* Invert low-order SIZE bits of XHI:XLO. */
7609 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7611 unsigned immlo
= xlo
? *xlo
: 0;
7612 unsigned immhi
= xhi
? *xhi
: 0;
7617 immlo
= (~immlo
) & 0xff;
7621 immlo
= (~immlo
) & 0xffff;
7625 immhi
= (~immhi
) & 0xffffffff;
7629 immlo
= (~immlo
) & 0xffffffff;
7643 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7647 neon_bits_same_in_bytes (unsigned imm
)
7649 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7650 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7651 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7652 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7655 /* For immediate of above form, return 0bABCD. */
7658 neon_squash_bits (unsigned imm
)
7660 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7661 | ((imm
& 0x01000000) >> 21);
7664 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7667 neon_qfloat_bits (unsigned imm
)
7669 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7672 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7673 the instruction. *OP is passed as the initial value of the op field, and
7674 may be set to a different value depending on the constant (i.e.
7675 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7676 MVN). If the immediate looks like a repeated pattern then also
7677 try smaller element sizes. */
7680 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7681 unsigned *immbits
, int *op
, int size
,
7682 enum neon_el_type type
)
7684 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7686 if (type
== NT_float
&& !float_p
)
7689 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7691 if (size
!= 32 || *op
== 1)
7693 *immbits
= neon_qfloat_bits (immlo
);
7699 if (neon_bits_same_in_bytes (immhi
)
7700 && neon_bits_same_in_bytes (immlo
))
7704 *immbits
= (neon_squash_bits (immhi
) << 4)
7705 | neon_squash_bits (immlo
);
7716 if (immlo
== (immlo
& 0x000000ff))
7721 else if (immlo
== (immlo
& 0x0000ff00))
7723 *immbits
= immlo
>> 8;
7726 else if (immlo
== (immlo
& 0x00ff0000))
7728 *immbits
= immlo
>> 16;
7731 else if (immlo
== (immlo
& 0xff000000))
7733 *immbits
= immlo
>> 24;
7736 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7738 *immbits
= (immlo
>> 8) & 0xff;
7741 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7743 *immbits
= (immlo
>> 16) & 0xff;
7747 if ((immlo
& 0xffff) != (immlo
>> 16))
7754 if (immlo
== (immlo
& 0x000000ff))
7759 else if (immlo
== (immlo
& 0x0000ff00))
7761 *immbits
= immlo
>> 8;
7765 if ((immlo
& 0xff) != (immlo
>> 8))
7770 if (immlo
== (immlo
& 0x000000ff))
7772 /* Don't allow MVN with 8-bit immediate. */
7782 #if defined BFD_HOST_64_BIT
7783 /* Returns TRUE if double precision value V may be cast
7784 to single precision without loss of accuracy. */
7787 is_double_a_single (bfd_int64_t v
)
7789 int exp
= (int)((v
>> 52) & 0x7FF);
7790 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7792 return (exp
== 0 || exp
== 0x7FF
7793 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7794 && (mantissa
& 0x1FFFFFFFl
) == 0;
7797 /* Returns a double precision value casted to single precision
7798 (ignoring the least significant bits in exponent and mantissa). */
7801 double_to_single (bfd_int64_t v
)
7803 int sign
= (int) ((v
>> 63) & 1l);
7804 int exp
= (int) ((v
>> 52) & 0x7FF);
7805 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7811 exp
= exp
- 1023 + 127;
7820 /* No denormalized numbers. */
7826 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7828 #endif /* BFD_HOST_64_BIT */
7837 static void do_vfp_nsyn_opcode (const char *);
7839 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7840 Determine whether it can be performed with a move instruction; if
7841 it can, convert inst.instruction to that move instruction and
7842 return TRUE; if it can't, convert inst.instruction to a literal-pool
7843 load and return FALSE. If this is not a valid thing to do in the
7844 current context, set inst.error and return TRUE.
7846 inst.operands[i] describes the destination register. */
7849 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7852 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7853 bfd_boolean arm_p
= (t
== CONST_ARM
);
7856 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7860 if ((inst
.instruction
& tbit
) == 0)
7862 inst
.error
= _("invalid pseudo operation");
7866 if (inst
.reloc
.exp
.X_op
!= O_constant
7867 && inst
.reloc
.exp
.X_op
!= O_symbol
7868 && inst
.reloc
.exp
.X_op
!= O_big
)
7870 inst
.error
= _("constant expression expected");
7874 if (inst
.reloc
.exp
.X_op
== O_constant
7875 || inst
.reloc
.exp
.X_op
== O_big
)
7877 #if defined BFD_HOST_64_BIT
7882 if (inst
.reloc
.exp
.X_op
== O_big
)
7884 LITTLENUM_TYPE w
[X_PRECISION
];
7887 if (inst
.reloc
.exp
.X_add_number
== -1)
7889 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7891 /* FIXME: Should we check words w[2..5] ? */
7896 #if defined BFD_HOST_64_BIT
7898 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7899 << LITTLENUM_NUMBER_OF_BITS
)
7900 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7901 << LITTLENUM_NUMBER_OF_BITS
)
7902 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7903 << LITTLENUM_NUMBER_OF_BITS
)
7904 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7906 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7907 | (l
[0] & LITTLENUM_MASK
);
7911 v
= inst
.reloc
.exp
.X_add_number
;
7913 if (!inst
.operands
[i
].issingle
)
7917 /* This can be encoded only for a low register. */
7918 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7920 /* This can be done with a mov(1) instruction. */
7921 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7922 inst
.instruction
|= v
;
7926 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7927 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7929 /* Check if on thumb2 it can be done with a mov.w, mvn or
7930 movw instruction. */
7931 unsigned int newimm
;
7932 bfd_boolean isNegated
;
7934 newimm
= encode_thumb32_immediate (v
);
7935 if (newimm
!= (unsigned int) FAIL
)
7939 newimm
= encode_thumb32_immediate (~v
);
7940 if (newimm
!= (unsigned int) FAIL
)
7944 /* The number can be loaded with a mov.w or mvn
7946 if (newimm
!= (unsigned int) FAIL
7947 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7949 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7950 | (inst
.operands
[i
].reg
<< 8));
7951 /* Change to MOVN. */
7952 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7953 inst
.instruction
|= (newimm
& 0x800) << 15;
7954 inst
.instruction
|= (newimm
& 0x700) << 4;
7955 inst
.instruction
|= (newimm
& 0x0ff);
7958 /* The number can be loaded with a movw instruction. */
7959 else if ((v
& ~0xFFFF) == 0
7960 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7962 int imm
= v
& 0xFFFF;
7964 inst
.instruction
= 0xf2400000; /* MOVW. */
7965 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7966 inst
.instruction
|= (imm
& 0xf000) << 4;
7967 inst
.instruction
|= (imm
& 0x0800) << 15;
7968 inst
.instruction
|= (imm
& 0x0700) << 4;
7969 inst
.instruction
|= (imm
& 0x00ff);
7976 int value
= encode_arm_immediate (v
);
7980 /* This can be done with a mov instruction. */
7981 inst
.instruction
&= LITERAL_MASK
;
7982 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7983 inst
.instruction
|= value
& 0xfff;
7987 value
= encode_arm_immediate (~ v
);
7990 /* This can be done with a mvn instruction. */
7991 inst
.instruction
&= LITERAL_MASK
;
7992 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7993 inst
.instruction
|= value
& 0xfff;
7997 else if (t
== CONST_VEC
)
8000 unsigned immbits
= 0;
8001 unsigned immlo
= inst
.operands
[1].imm
;
8002 unsigned immhi
= inst
.operands
[1].regisimm
8003 ? inst
.operands
[1].reg
8004 : inst
.reloc
.exp
.X_unsigned
8006 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8007 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8008 &op
, 64, NT_invtype
);
8012 neon_invert_size (&immlo
, &immhi
, 64);
8014 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8015 &op
, 64, NT_invtype
);
8020 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8026 /* Fill other bits in vmov encoding for both thumb and arm. */
8028 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8030 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8031 neon_write_immbits (immbits
);
8039 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8040 if (inst
.operands
[i
].issingle
8041 && is_quarter_float (inst
.operands
[1].imm
)
8042 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8044 inst
.operands
[1].imm
=
8045 neon_qfloat_bits (v
);
8046 do_vfp_nsyn_opcode ("fconsts");
8050 /* If our host does not support a 64-bit type then we cannot perform
8051 the following optimization. This mean that there will be a
8052 discrepancy between the output produced by an assembler built for
8053 a 32-bit-only host and the output produced from a 64-bit host, but
8054 this cannot be helped. */
8055 #if defined BFD_HOST_64_BIT
8056 else if (!inst
.operands
[1].issingle
8057 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8059 if (is_double_a_single (v
)
8060 && is_quarter_float (double_to_single (v
)))
8062 inst
.operands
[1].imm
=
8063 neon_qfloat_bits (double_to_single (v
));
8064 do_vfp_nsyn_opcode ("fconstd");
8072 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8073 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8076 inst
.operands
[1].reg
= REG_PC
;
8077 inst
.operands
[1].isreg
= 1;
8078 inst
.operands
[1].preind
= 1;
8079 inst
.reloc
.pc_rel
= 1;
8080 inst
.reloc
.type
= (thumb_p
8081 ? BFD_RELOC_ARM_THUMB_OFFSET
8083 ? BFD_RELOC_ARM_HWLITERAL
8084 : BFD_RELOC_ARM_LITERAL
));
8088 /* inst.operands[i] was set up by parse_address. Encode it into an
8089 ARM-format instruction. Reject all forms which cannot be encoded
8090 into a coprocessor load/store instruction. If wb_ok is false,
8091 reject use of writeback; if unind_ok is false, reject use of
8092 unindexed addressing. If reloc_override is not 0, use it instead
8093 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8094 (in which case it is preserved). */
8097 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8099 if (!inst
.operands
[i
].isreg
)
8102 if (! inst
.operands
[0].isvec
)
8104 inst
.error
= _("invalid co-processor operand");
8107 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8111 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8113 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8115 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8117 gas_assert (!inst
.operands
[i
].writeback
);
8120 inst
.error
= _("instruction does not support unindexed addressing");
8123 inst
.instruction
|= inst
.operands
[i
].imm
;
8124 inst
.instruction
|= INDEX_UP
;
8128 if (inst
.operands
[i
].preind
)
8129 inst
.instruction
|= PRE_INDEX
;
8131 if (inst
.operands
[i
].writeback
)
8133 if (inst
.operands
[i
].reg
== REG_PC
)
8135 inst
.error
= _("pc may not be used with write-back");
8140 inst
.error
= _("instruction does not support writeback");
8143 inst
.instruction
|= WRITE_BACK
;
8147 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8148 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8149 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8150 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8153 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8155 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8158 /* Prefer + for zero encoded value. */
8159 if (!inst
.operands
[i
].negative
)
8160 inst
.instruction
|= INDEX_UP
;
8165 /* Functions for instruction encoding, sorted by sub-architecture.
8166 First some generics; their names are taken from the conventional
8167 bit positions for register arguments in ARM format instructions. */
8177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8184 inst
.instruction
|= inst
.operands
[1].reg
;
8190 inst
.instruction
|= inst
.operands
[0].reg
;
8191 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8197 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8198 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8204 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8205 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8211 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8212 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8216 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8218 if (ARM_CPU_IS_ANY (cpu_variant
))
8220 as_tsktsk ("%s", msg
);
8223 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8235 unsigned Rn
= inst
.operands
[2].reg
;
8236 /* Enforce restrictions on SWP instruction. */
8237 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8239 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8240 _("Rn must not overlap other operands"));
8242 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8244 if (!check_obsolete (&arm_ext_v8
,
8245 _("swp{b} use is obsoleted for ARMv8 and later"))
8246 && warn_on_deprecated
8247 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8248 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8251 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8252 inst
.instruction
|= inst
.operands
[1].reg
;
8253 inst
.instruction
|= Rn
<< 16;
8259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8261 inst
.instruction
|= inst
.operands
[2].reg
;
8267 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8268 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8269 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8270 || inst
.reloc
.exp
.X_add_number
!= 0),
8272 inst
.instruction
|= inst
.operands
[0].reg
;
8273 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8274 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8280 inst
.instruction
|= inst
.operands
[0].imm
;
8286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8287 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8290 /* ARM instructions, in alphabetical order by function name (except
8291 that wrapper functions appear immediately after the function they
8294 /* This is a pseudo-op of the form "adr rd, label" to be converted
8295 into a relative address of the form "add rd, pc, #label-.-8". */
8300 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8302 /* Frag hacking will turn this into a sub instruction if the offset turns
8303 out to be negative. */
8304 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8305 inst
.reloc
.pc_rel
= 1;
8306 inst
.reloc
.exp
.X_add_number
-= 8;
8309 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8310 into a relative address of the form:
8311 add rd, pc, #low(label-.-8)"
8312 add rd, rd, #high(label-.-8)" */
8317 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8319 /* Frag hacking will turn this into a sub instruction if the offset turns
8320 out to be negative. */
8321 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8322 inst
.reloc
.pc_rel
= 1;
8323 inst
.size
= INSN_SIZE
* 2;
8324 inst
.reloc
.exp
.X_add_number
-= 8;
8330 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8331 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8333 if (!inst
.operands
[1].present
)
8334 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8337 encode_arm_shifter_operand (2);
8343 if (inst
.operands
[0].present
)
8344 inst
.instruction
|= inst
.operands
[0].imm
;
8346 inst
.instruction
|= 0xf;
8352 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8353 constraint (msb
> 32, _("bit-field extends past end of register"));
8354 /* The instruction encoding stores the LSB and MSB,
8355 not the LSB and width. */
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8358 inst
.instruction
|= (msb
- 1) << 16;
8366 /* #0 in second position is alternative syntax for bfc, which is
8367 the same instruction but with REG_PC in the Rm field. */
8368 if (!inst
.operands
[1].isreg
)
8369 inst
.operands
[1].reg
= REG_PC
;
8371 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8372 constraint (msb
> 32, _("bit-field extends past end of register"));
8373 /* The instruction encoding stores the LSB and MSB,
8374 not the LSB and width. */
8375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8376 inst
.instruction
|= inst
.operands
[1].reg
;
8377 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8378 inst
.instruction
|= (msb
- 1) << 16;
8384 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8385 _("bit-field extends past end of register"));
8386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8387 inst
.instruction
|= inst
.operands
[1].reg
;
8388 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8389 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8392 /* ARM V5 breakpoint instruction (argument parse)
8393 BKPT <16 bit unsigned immediate>
8394 Instruction is not conditional.
8395 The bit pattern given in insns[] has the COND_ALWAYS condition,
8396 and it is an error if the caller tried to override that. */
8401 /* Top 12 of 16 bits to bits 19:8. */
8402 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8404 /* Bottom 4 of 16 bits to bits 3:0. */
8405 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8409 encode_branch (int default_reloc
)
8411 if (inst
.operands
[0].hasreloc
)
8413 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8414 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8415 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8416 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8417 ? BFD_RELOC_ARM_PLT32
8418 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8421 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8422 inst
.reloc
.pc_rel
= 1;
8429 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8430 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8433 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8440 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8442 if (inst
.cond
== COND_ALWAYS
)
8443 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8445 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8449 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8452 /* ARM V5 branch-link-exchange instruction (argument parse)
8453 BLX <target_addr> ie BLX(1)
8454 BLX{<condition>} <Rm> ie BLX(2)
8455 Unfortunately, there are two different opcodes for this mnemonic.
8456 So, the insns[].value is not used, and the code here zaps values
8457 into inst.instruction.
8458 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8463 if (inst
.operands
[0].isreg
)
8465 /* Arg is a register; the opcode provided by insns[] is correct.
8466 It is not illegal to do "blx pc", just useless. */
8467 if (inst
.operands
[0].reg
== REG_PC
)
8468 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8470 inst
.instruction
|= inst
.operands
[0].reg
;
8474 /* Arg is an address; this instruction cannot be executed
8475 conditionally, and the opcode must be adjusted.
8476 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8477 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8478 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8479 inst
.instruction
= 0xfa000000;
8480 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8487 bfd_boolean want_reloc
;
8489 if (inst
.operands
[0].reg
== REG_PC
)
8490 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8492 inst
.instruction
|= inst
.operands
[0].reg
;
8493 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8494 it is for ARMv4t or earlier. */
8495 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8496 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8500 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8505 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8509 /* ARM v5TEJ. Jump to Jazelle code. */
8514 if (inst
.operands
[0].reg
== REG_PC
)
8515 as_tsktsk (_("use of r15 in bxj is not really useful"));
8517 inst
.instruction
|= inst
.operands
[0].reg
;
8520 /* Co-processor data operation:
8521 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8522 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8526 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8527 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8528 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8529 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8530 inst
.instruction
|= inst
.operands
[4].reg
;
8531 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8537 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8538 encode_arm_shifter_operand (1);
8541 /* Transfer between coprocessor and ARM registers.
8542 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8547 No special properties. */
8549 struct deprecated_coproc_regs_s
8556 arm_feature_set deprecated
;
8557 arm_feature_set obsoleted
;
8558 const char *dep_msg
;
8559 const char *obs_msg
;
8562 #define DEPR_ACCESS_V8 \
8563 N_("This coprocessor register access is deprecated in ARMv8")
8565 /* Table of all deprecated coprocessor registers. */
8566 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8568 {15, 0, 7, 10, 5, /* CP15DMB. */
8569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8570 DEPR_ACCESS_V8
, NULL
},
8571 {15, 0, 7, 10, 4, /* CP15DSB. */
8572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8573 DEPR_ACCESS_V8
, NULL
},
8574 {15, 0, 7, 5, 4, /* CP15ISB. */
8575 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8576 DEPR_ACCESS_V8
, NULL
},
8577 {14, 6, 1, 0, 0, /* TEEHBR. */
8578 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8579 DEPR_ACCESS_V8
, NULL
},
8580 {14, 6, 0, 0, 0, /* TEECR. */
8581 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8582 DEPR_ACCESS_V8
, NULL
},
8585 #undef DEPR_ACCESS_V8
8587 static const size_t deprecated_coproc_reg_count
=
8588 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8596 Rd
= inst
.operands
[2].reg
;
8599 if (inst
.instruction
== 0xee000010
8600 || inst
.instruction
== 0xfe000010)
8602 reject_bad_reg (Rd
);
8605 constraint (Rd
== REG_SP
, BAD_SP
);
8610 if (inst
.instruction
== 0xe000010)
8611 constraint (Rd
== REG_PC
, BAD_PC
);
8614 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8616 const struct deprecated_coproc_regs_s
*r
=
8617 deprecated_coproc_regs
+ i
;
8619 if (inst
.operands
[0].reg
== r
->cp
8620 && inst
.operands
[1].imm
== r
->opc1
8621 && inst
.operands
[3].reg
== r
->crn
8622 && inst
.operands
[4].reg
== r
->crm
8623 && inst
.operands
[5].imm
== r
->opc2
)
8625 if (! ARM_CPU_IS_ANY (cpu_variant
)
8626 && warn_on_deprecated
8627 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8628 as_tsktsk ("%s", r
->dep_msg
);
8632 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8633 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8634 inst
.instruction
|= Rd
<< 12;
8635 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8636 inst
.instruction
|= inst
.operands
[4].reg
;
8637 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8640 /* Transfer between coprocessor register and pair of ARM registers.
8641 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8646 Two XScale instructions are special cases of these:
8648 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8649 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8651 Result unpredictable if Rd or Rn is R15. */
8658 Rd
= inst
.operands
[2].reg
;
8659 Rn
= inst
.operands
[3].reg
;
8663 reject_bad_reg (Rd
);
8664 reject_bad_reg (Rn
);
8668 constraint (Rd
== REG_PC
, BAD_PC
);
8669 constraint (Rn
== REG_PC
, BAD_PC
);
8672 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8673 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8674 inst
.instruction
|= Rd
<< 12;
8675 inst
.instruction
|= Rn
<< 16;
8676 inst
.instruction
|= inst
.operands
[4].reg
;
8682 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8683 if (inst
.operands
[1].present
)
8685 inst
.instruction
|= CPSI_MMOD
;
8686 inst
.instruction
|= inst
.operands
[1].imm
;
8693 inst
.instruction
|= inst
.operands
[0].imm
;
8699 unsigned Rd
, Rn
, Rm
;
8701 Rd
= inst
.operands
[0].reg
;
8702 Rn
= (inst
.operands
[1].present
8703 ? inst
.operands
[1].reg
: Rd
);
8704 Rm
= inst
.operands
[2].reg
;
8706 constraint ((Rd
== REG_PC
), BAD_PC
);
8707 constraint ((Rn
== REG_PC
), BAD_PC
);
8708 constraint ((Rm
== REG_PC
), BAD_PC
);
8710 inst
.instruction
|= Rd
<< 16;
8711 inst
.instruction
|= Rn
<< 0;
8712 inst
.instruction
|= Rm
<< 8;
8718 /* There is no IT instruction in ARM mode. We
8719 process it to do the validation as if in
8720 thumb mode, just in case the code gets
8721 assembled for thumb using the unified syntax. */
8726 set_it_insn_type (IT_INSN
);
8727 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8728 now_it
.cc
= inst
.operands
[0].imm
;
8732 /* If there is only one register in the register list,
8733 then return its register number. Otherwise return -1. */
8735 only_one_reg_in_list (int range
)
8737 int i
= ffs (range
) - 1;
8738 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8742 encode_ldmstm(int from_push_pop_mnem
)
8744 int base_reg
= inst
.operands
[0].reg
;
8745 int range
= inst
.operands
[1].imm
;
8748 inst
.instruction
|= base_reg
<< 16;
8749 inst
.instruction
|= range
;
8751 if (inst
.operands
[1].writeback
)
8752 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8754 if (inst
.operands
[0].writeback
)
8756 inst
.instruction
|= WRITE_BACK
;
8757 /* Check for unpredictable uses of writeback. */
8758 if (inst
.instruction
& LOAD_BIT
)
8760 /* Not allowed in LDM type 2. */
8761 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8762 && ((range
& (1 << REG_PC
)) == 0))
8763 as_warn (_("writeback of base register is UNPREDICTABLE"));
8764 /* Only allowed if base reg not in list for other types. */
8765 else if (range
& (1 << base_reg
))
8766 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8770 /* Not allowed for type 2. */
8771 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8772 as_warn (_("writeback of base register is UNPREDICTABLE"));
8773 /* Only allowed if base reg not in list, or first in list. */
8774 else if ((range
& (1 << base_reg
))
8775 && (range
& ((1 << base_reg
) - 1)))
8776 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8780 /* If PUSH/POP has only one register, then use the A2 encoding. */
8781 one_reg
= only_one_reg_in_list (range
);
8782 if (from_push_pop_mnem
&& one_reg
>= 0)
8784 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8786 inst
.instruction
&= A_COND_MASK
;
8787 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8788 inst
.instruction
|= one_reg
<< 12;
8795 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8798 /* ARMv5TE load-consecutive (argument parse)
8807 constraint (inst
.operands
[0].reg
% 2 != 0,
8808 _("first transfer register must be even"));
8809 constraint (inst
.operands
[1].present
8810 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8811 _("can only transfer two consecutive registers"));
8812 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8813 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8815 if (!inst
.operands
[1].present
)
8816 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8818 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8819 register and the first register written; we have to diagnose
8820 overlap between the base and the second register written here. */
8822 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8823 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8824 as_warn (_("base register written back, and overlaps "
8825 "second transfer register"));
8827 if (!(inst
.instruction
& V4_STR_BIT
))
8829 /* For an index-register load, the index register must not overlap the
8830 destination (even if not write-back). */
8831 if (inst
.operands
[2].immisreg
8832 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8833 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8834 as_warn (_("index register overlaps transfer register"));
8836 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8837 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8843 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8844 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8845 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8846 || inst
.operands
[1].negative
8847 /* This can arise if the programmer has written
8849 or if they have mistakenly used a register name as the last
8852 It is very difficult to distinguish between these two cases
8853 because "rX" might actually be a label. ie the register
8854 name has been occluded by a symbol of the same name. So we
8855 just generate a general 'bad addressing mode' type error
8856 message and leave it up to the programmer to discover the
8857 true cause and fix their mistake. */
8858 || (inst
.operands
[1].reg
== REG_PC
),
8861 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8862 || inst
.reloc
.exp
.X_add_number
!= 0,
8863 _("offset must be zero in ARM encoding"));
8865 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8868 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8869 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8875 constraint (inst
.operands
[0].reg
% 2 != 0,
8876 _("even register required"));
8877 constraint (inst
.operands
[1].present
8878 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8879 _("can only load two consecutive registers"));
8880 /* If op 1 were present and equal to PC, this function wouldn't
8881 have been called in the first place. */
8882 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8885 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8888 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8889 which is not a multiple of four is UNPREDICTABLE. */
8891 check_ldr_r15_aligned (void)
8893 constraint (!(inst
.operands
[1].immisreg
)
8894 && (inst
.operands
[0].reg
== REG_PC
8895 && inst
.operands
[1].reg
== REG_PC
8896 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8897 _("ldr to register 15 must be 4-byte alligned"));
8903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8904 if (!inst
.operands
[1].isreg
)
8905 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8907 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8908 check_ldr_r15_aligned ();
8914 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8916 if (inst
.operands
[1].preind
)
8918 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8919 || inst
.reloc
.exp
.X_add_number
!= 0,
8920 _("this instruction requires a post-indexed address"));
8922 inst
.operands
[1].preind
= 0;
8923 inst
.operands
[1].postind
= 1;
8924 inst
.operands
[1].writeback
= 1;
8926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8927 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8930 /* Halfword and signed-byte load/store operations. */
8935 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8937 if (!inst
.operands
[1].isreg
)
8938 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8940 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8946 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8948 if (inst
.operands
[1].preind
)
8950 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8951 || inst
.reloc
.exp
.X_add_number
!= 0,
8952 _("this instruction requires a post-indexed address"));
8954 inst
.operands
[1].preind
= 0;
8955 inst
.operands
[1].postind
= 1;
8956 inst
.operands
[1].writeback
= 1;
8958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8959 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8962 /* Co-processor register load/store.
8963 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8967 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8969 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8975 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8976 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8977 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8978 && !(inst
.instruction
& 0x00400000))
8979 as_tsktsk (_("Rd and Rm should be different in mla"));
8981 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8982 inst
.instruction
|= inst
.operands
[1].reg
;
8983 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8984 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8990 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8991 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8994 encode_arm_shifter_operand (1);
8997 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9004 top
= (inst
.instruction
& 0x00400000) != 0;
9005 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9006 _(":lower16: not allowed this instruction"));
9007 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9008 _(":upper16: not allowed instruction"));
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9010 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9012 imm
= inst
.reloc
.exp
.X_add_number
;
9013 /* The value is in two pieces: 0:11, 16:19. */
9014 inst
.instruction
|= (imm
& 0x00000fff);
9015 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9020 do_vfp_nsyn_mrs (void)
9022 if (inst
.operands
[0].isvec
)
9024 if (inst
.operands
[1].reg
!= 1)
9025 first_error (_("operand 1 must be FPSCR"));
9026 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9027 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9028 do_vfp_nsyn_opcode ("fmstat");
9030 else if (inst
.operands
[1].isvec
)
9031 do_vfp_nsyn_opcode ("fmrx");
9039 do_vfp_nsyn_msr (void)
9041 if (inst
.operands
[0].isvec
)
9042 do_vfp_nsyn_opcode ("fmxr");
9052 unsigned Rt
= inst
.operands
[0].reg
;
9054 if (thumb_mode
&& Rt
== REG_SP
)
9056 inst
.error
= BAD_SP
;
9060 /* APSR_ sets isvec. All other refs to PC are illegal. */
9061 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9063 inst
.error
= BAD_PC
;
9067 /* If we get through parsing the register name, we just insert the number
9068 generated into the instruction without further validation. */
9069 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9070 inst
.instruction
|= (Rt
<< 12);
9076 unsigned Rt
= inst
.operands
[1].reg
;
9079 reject_bad_reg (Rt
);
9080 else if (Rt
== REG_PC
)
9082 inst
.error
= BAD_PC
;
9086 /* If we get through parsing the register name, we just insert the number
9087 generated into the instruction without further validation. */
9088 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9089 inst
.instruction
|= (Rt
<< 12);
9097 if (do_vfp_nsyn_mrs () == SUCCESS
)
9100 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9103 if (inst
.operands
[1].isreg
)
9105 br
= inst
.operands
[1].reg
;
9106 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9107 as_bad (_("bad register for mrs"));
9111 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9112 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9114 _("'APSR', 'CPSR' or 'SPSR' expected"));
9115 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9118 inst
.instruction
|= br
;
9121 /* Two possible forms:
9122 "{C|S}PSR_<field>, Rm",
9123 "{C|S}PSR_f, #expression". */
9128 if (do_vfp_nsyn_msr () == SUCCESS
)
9131 inst
.instruction
|= inst
.operands
[0].imm
;
9132 if (inst
.operands
[1].isreg
)
9133 inst
.instruction
|= inst
.operands
[1].reg
;
9136 inst
.instruction
|= INST_IMMEDIATE
;
9137 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9138 inst
.reloc
.pc_rel
= 0;
9145 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9147 if (!inst
.operands
[2].present
)
9148 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9149 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9150 inst
.instruction
|= inst
.operands
[1].reg
;
9151 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9153 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9154 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9155 as_tsktsk (_("Rd and Rm should be different in mul"));
9158 /* Long Multiply Parser
9159 UMULL RdLo, RdHi, Rm, Rs
9160 SMULL RdLo, RdHi, Rm, Rs
9161 UMLAL RdLo, RdHi, Rm, Rs
9162 SMLAL RdLo, RdHi, Rm, Rs. */
9167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9168 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9169 inst
.instruction
|= inst
.operands
[2].reg
;
9170 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9172 /* rdhi and rdlo must be different. */
9173 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9174 as_tsktsk (_("rdhi and rdlo must be different"));
9176 /* rdhi, rdlo and rm must all be different before armv6. */
9177 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9178 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9179 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9180 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9186 if (inst
.operands
[0].present
9187 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9189 /* Architectural NOP hints are CPSR sets with no bits selected. */
9190 inst
.instruction
&= 0xf0000000;
9191 inst
.instruction
|= 0x0320f000;
9192 if (inst
.operands
[0].present
)
9193 inst
.instruction
|= inst
.operands
[0].imm
;
9197 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9198 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9199 Condition defaults to COND_ALWAYS.
9200 Error if Rd, Rn or Rm are R15. */
9205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9206 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9207 inst
.instruction
|= inst
.operands
[2].reg
;
9208 if (inst
.operands
[3].present
)
9209 encode_arm_shift (3);
9212 /* ARM V6 PKHTB (Argument Parse). */
9217 if (!inst
.operands
[3].present
)
9219 /* If the shift specifier is omitted, turn the instruction
9220 into pkhbt rd, rm, rn. */
9221 inst
.instruction
&= 0xfff00010;
9222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9223 inst
.instruction
|= inst
.operands
[1].reg
;
9224 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9230 inst
.instruction
|= inst
.operands
[2].reg
;
9231 encode_arm_shift (3);
9235 /* ARMv5TE: Preload-Cache
9236 MP Extensions: Preload for write
9240 Syntactically, like LDR with B=1, W=0, L=1. */
9245 constraint (!inst
.operands
[0].isreg
,
9246 _("'[' expected after PLD mnemonic"));
9247 constraint (inst
.operands
[0].postind
,
9248 _("post-indexed expression used in preload instruction"));
9249 constraint (inst
.operands
[0].writeback
,
9250 _("writeback used in preload instruction"));
9251 constraint (!inst
.operands
[0].preind
,
9252 _("unindexed addressing used in preload instruction"));
9253 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9256 /* ARMv7: PLI <addr_mode> */
9260 constraint (!inst
.operands
[0].isreg
,
9261 _("'[' expected after PLI mnemonic"));
9262 constraint (inst
.operands
[0].postind
,
9263 _("post-indexed expression used in preload instruction"));
9264 constraint (inst
.operands
[0].writeback
,
9265 _("writeback used in preload instruction"));
9266 constraint (!inst
.operands
[0].preind
,
9267 _("unindexed addressing used in preload instruction"));
9268 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9269 inst
.instruction
&= ~PRE_INDEX
;
9275 constraint (inst
.operands
[0].writeback
,
9276 _("push/pop do not support {reglist}^"));
9277 inst
.operands
[1] = inst
.operands
[0];
9278 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9279 inst
.operands
[0].isreg
= 1;
9280 inst
.operands
[0].writeback
= 1;
9281 inst
.operands
[0].reg
= REG_SP
;
9282 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9285 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9286 word at the specified address and the following word
9288 Unconditionally executed.
9289 Error if Rn is R15. */
9294 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9295 if (inst
.operands
[0].writeback
)
9296 inst
.instruction
|= WRITE_BACK
;
9299 /* ARM V6 ssat (argument parse). */
9304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9305 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9306 inst
.instruction
|= inst
.operands
[2].reg
;
9308 if (inst
.operands
[3].present
)
9309 encode_arm_shift (3);
9312 /* ARM V6 usat (argument parse). */
9317 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9318 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9319 inst
.instruction
|= inst
.operands
[2].reg
;
9321 if (inst
.operands
[3].present
)
9322 encode_arm_shift (3);
9325 /* ARM V6 ssat16 (argument parse). */
9330 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9331 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9332 inst
.instruction
|= inst
.operands
[2].reg
;
9338 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9339 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9340 inst
.instruction
|= inst
.operands
[2].reg
;
9343 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9344 preserving the other bits.
9346 setend <endian_specifier>, where <endian_specifier> is either
9352 if (warn_on_deprecated
9353 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9354 as_tsktsk (_("setend use is deprecated for ARMv8"));
9356 if (inst
.operands
[0].imm
)
9357 inst
.instruction
|= 0x200;
9363 unsigned int Rm
= (inst
.operands
[1].present
9364 ? inst
.operands
[1].reg
9365 : inst
.operands
[0].reg
);
9367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9368 inst
.instruction
|= Rm
;
9369 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9371 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9372 inst
.instruction
|= SHIFT_BY_REG
;
9373 /* PR 12854: Error on extraneous shifts. */
9374 constraint (inst
.operands
[2].shifted
,
9375 _("extraneous shift as part of operand to shift insn"));
9378 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9384 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9385 inst
.reloc
.pc_rel
= 0;
9391 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9392 inst
.reloc
.pc_rel
= 0;
9398 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9399 inst
.reloc
.pc_rel
= 0;
9405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9406 _("selected processor does not support SETPAN instruction"));
9408 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9414 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9415 _("selected processor does not support SETPAN instruction"));
9417 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9420 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9421 SMLAxy{cond} Rd,Rm,Rs,Rn
9422 SMLAWy{cond} Rd,Rm,Rs,Rn
9423 Error if any register is R15. */
9428 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9429 inst
.instruction
|= inst
.operands
[1].reg
;
9430 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9431 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9434 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9435 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9436 Error if any register is R15.
9437 Warning if Rdlo == Rdhi. */
9442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9443 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9444 inst
.instruction
|= inst
.operands
[2].reg
;
9445 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9447 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9448 as_tsktsk (_("rdhi and rdlo must be different"));
9451 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9452 SMULxy{cond} Rd,Rm,Rs
9453 Error if any register is R15. */
9458 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9459 inst
.instruction
|= inst
.operands
[1].reg
;
9460 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9463 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9464 the same for both ARM and Thumb-2. */
9471 if (inst
.operands
[0].present
)
9473 reg
= inst
.operands
[0].reg
;
9474 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9479 inst
.instruction
|= reg
<< 16;
9480 inst
.instruction
|= inst
.operands
[1].imm
;
9481 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9482 inst
.instruction
|= WRITE_BACK
;
9485 /* ARM V6 strex (argument parse). */
9490 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9491 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9492 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9493 || inst
.operands
[2].negative
9494 /* See comment in do_ldrex(). */
9495 || (inst
.operands
[2].reg
== REG_PC
),
9498 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9499 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9501 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9502 || inst
.reloc
.exp
.X_add_number
!= 0,
9503 _("offset must be zero in ARM encoding"));
9505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9506 inst
.instruction
|= inst
.operands
[1].reg
;
9507 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9508 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9514 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9515 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9516 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9517 || inst
.operands
[2].negative
,
9520 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9521 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9529 constraint (inst
.operands
[1].reg
% 2 != 0,
9530 _("even register required"));
9531 constraint (inst
.operands
[2].present
9532 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9533 _("can only store two consecutive registers"));
9534 /* If op 2 were present and equal to PC, this function wouldn't
9535 have been called in the first place. */
9536 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9538 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9539 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9540 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9544 inst
.instruction
|= inst
.operands
[1].reg
;
9545 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9552 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9553 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9561 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9562 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9567 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9568 extends it to 32-bits, and adds the result to a value in another
9569 register. You can specify a rotation by 0, 8, 16, or 24 bits
9570 before extracting the 16-bit value.
9571 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9572 Condition defaults to COND_ALWAYS.
9573 Error if any register uses R15. */
9578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9580 inst
.instruction
|= inst
.operands
[2].reg
;
9581 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9586 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9587 Condition defaults to COND_ALWAYS.
9588 Error if any register uses R15. */
9593 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9594 inst
.instruction
|= inst
.operands
[1].reg
;
9595 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9598 /* VFP instructions. In a logical order: SP variant first, monad
9599 before dyad, arithmetic then move then load/store. */
9602 do_vfp_sp_monadic (void)
9604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9605 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9609 do_vfp_sp_dyadic (void)
9611 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9612 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9613 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9617 do_vfp_sp_compare_z (void)
9619 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9623 do_vfp_dp_sp_cvt (void)
9625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9626 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9630 do_vfp_sp_dp_cvt (void)
9632 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9633 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9637 do_vfp_reg_from_sp (void)
9639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9640 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9644 do_vfp_reg2_from_sp2 (void)
9646 constraint (inst
.operands
[2].imm
!= 2,
9647 _("only two consecutive VFP SP registers allowed here"));
9648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9649 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9650 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9654 do_vfp_sp_from_reg (void)
9656 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9657 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9661 do_vfp_sp2_from_reg2 (void)
9663 constraint (inst
.operands
[0].imm
!= 2,
9664 _("only two consecutive VFP SP registers allowed here"));
9665 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9666 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9667 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9671 do_vfp_sp_ldst (void)
9673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9674 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9678 do_vfp_dp_ldst (void)
9680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9681 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9686 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9688 if (inst
.operands
[0].writeback
)
9689 inst
.instruction
|= WRITE_BACK
;
9691 constraint (ldstm_type
!= VFP_LDSTMIA
,
9692 _("this addressing mode requires base-register writeback"));
9693 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9695 inst
.instruction
|= inst
.operands
[1].imm
;
9699 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9703 if (inst
.operands
[0].writeback
)
9704 inst
.instruction
|= WRITE_BACK
;
9706 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9707 _("this addressing mode requires base-register writeback"));
9709 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9710 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9712 count
= inst
.operands
[1].imm
<< 1;
9713 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9716 inst
.instruction
|= count
;
9720 do_vfp_sp_ldstmia (void)
9722 vfp_sp_ldstm (VFP_LDSTMIA
);
9726 do_vfp_sp_ldstmdb (void)
9728 vfp_sp_ldstm (VFP_LDSTMDB
);
9732 do_vfp_dp_ldstmia (void)
9734 vfp_dp_ldstm (VFP_LDSTMIA
);
9738 do_vfp_dp_ldstmdb (void)
9740 vfp_dp_ldstm (VFP_LDSTMDB
);
9744 do_vfp_xp_ldstmia (void)
9746 vfp_dp_ldstm (VFP_LDSTMIAX
);
9750 do_vfp_xp_ldstmdb (void)
9752 vfp_dp_ldstm (VFP_LDSTMDBX
);
9756 do_vfp_dp_rd_rm (void)
9758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9759 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9763 do_vfp_dp_rn_rd (void)
9765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9766 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9770 do_vfp_dp_rd_rn (void)
9772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9777 do_vfp_dp_rd_rn_rm (void)
9779 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9780 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9781 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9791 do_vfp_dp_rm_rd_rn (void)
9793 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9794 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9795 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9798 /* VFPv3 instructions. */
9800 do_vfp_sp_const (void)
9802 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9803 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9804 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9808 do_vfp_dp_const (void)
9810 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9811 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9812 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9816 vfp_conv (int srcsize
)
9818 int immbits
= srcsize
- inst
.operands
[1].imm
;
9820 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9822 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9823 i.e. immbits must be in range 0 - 16. */
9824 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9827 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9829 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9830 i.e. immbits must be in range 0 - 31. */
9831 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9835 inst
.instruction
|= (immbits
& 1) << 5;
9836 inst
.instruction
|= (immbits
>> 1);
9840 do_vfp_sp_conv_16 (void)
9842 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9847 do_vfp_dp_conv_16 (void)
9849 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9854 do_vfp_sp_conv_32 (void)
9856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9861 do_vfp_dp_conv_32 (void)
9863 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9867 /* FPA instructions. Also in a logical order. */
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[1].reg
;
9877 do_fpa_ldmstm (void)
9879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9880 switch (inst
.operands
[1].imm
)
9882 case 1: inst
.instruction
|= CP_T_X
; break;
9883 case 2: inst
.instruction
|= CP_T_Y
; break;
9884 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9889 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9891 /* The instruction specified "ea" or "fd", so we can only accept
9892 [Rn]{!}. The instruction does not really support stacking or
9893 unstacking, so we have to emulate these by setting appropriate
9894 bits and offsets. */
9895 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9896 || inst
.reloc
.exp
.X_add_number
!= 0,
9897 _("this instruction does not support indexing"));
9899 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9900 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9902 if (!(inst
.instruction
& INDEX_UP
))
9903 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9905 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9907 inst
.operands
[2].preind
= 0;
9908 inst
.operands
[2].postind
= 1;
9912 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9915 /* iWMMXt instructions: strictly in alphabetical order. */
9918 do_iwmmxt_tandorc (void)
9920 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9924 do_iwmmxt_textrc (void)
9926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9927 inst
.instruction
|= inst
.operands
[1].imm
;
9931 do_iwmmxt_textrm (void)
9933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9934 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9935 inst
.instruction
|= inst
.operands
[2].imm
;
9939 do_iwmmxt_tinsr (void)
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9942 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9943 inst
.instruction
|= inst
.operands
[2].imm
;
9947 do_iwmmxt_tmia (void)
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9950 inst
.instruction
|= inst
.operands
[1].reg
;
9951 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9955 do_iwmmxt_waligni (void)
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9958 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9959 inst
.instruction
|= inst
.operands
[2].reg
;
9960 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9964 do_iwmmxt_wmerge (void)
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9968 inst
.instruction
|= inst
.operands
[2].reg
;
9969 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9973 do_iwmmxt_wmov (void)
9975 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9977 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9978 inst
.instruction
|= inst
.operands
[1].reg
;
9982 do_iwmmxt_wldstbh (void)
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9987 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9989 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9990 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9994 do_iwmmxt_wldstw (void)
9996 /* RIWR_RIWC clears .isreg for a control register. */
9997 if (!inst
.operands
[0].isreg
)
9999 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10000 inst
.instruction
|= 0xf0000000;
10003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10004 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10008 do_iwmmxt_wldstd (void)
10010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10011 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10012 && inst
.operands
[1].immisreg
)
10014 inst
.instruction
&= ~0x1a000ff;
10015 inst
.instruction
|= (0xfU
<< 28);
10016 if (inst
.operands
[1].preind
)
10017 inst
.instruction
|= PRE_INDEX
;
10018 if (!inst
.operands
[1].negative
)
10019 inst
.instruction
|= INDEX_UP
;
10020 if (inst
.operands
[1].writeback
)
10021 inst
.instruction
|= WRITE_BACK
;
10022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10023 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10024 inst
.instruction
|= inst
.operands
[1].imm
;
10027 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10031 do_iwmmxt_wshufh (void)
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10035 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10036 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10040 do_iwmmxt_wzero (void)
10042 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10043 inst
.instruction
|= inst
.operands
[0].reg
;
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10045 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10049 do_iwmmxt_wrwrwr_or_imm5 (void)
10051 if (inst
.operands
[2].isreg
)
10054 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10055 _("immediate operand requires iWMMXt2"));
10057 if (inst
.operands
[2].imm
== 0)
10059 switch ((inst
.instruction
>> 20) & 0xf)
10065 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10066 inst
.operands
[2].imm
= 16;
10067 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10073 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10074 inst
.operands
[2].imm
= 32;
10075 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10082 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10084 wrn
= (inst
.instruction
>> 16) & 0xf;
10085 inst
.instruction
&= 0xff0fff0f;
10086 inst
.instruction
|= wrn
;
10087 /* Bail out here; the instruction is now assembled. */
10092 /* Map 32 -> 0, etc. */
10093 inst
.operands
[2].imm
&= 0x1f;
10094 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10098 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10099 operations first, then control, shift, and load/store. */
10101 /* Insns like "foo X,Y,Z". */
10104 do_mav_triple (void)
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10107 inst
.instruction
|= inst
.operands
[1].reg
;
10108 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10111 /* Insns like "foo W,X,Y,Z".
10112 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10117 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10118 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10119 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10120 inst
.instruction
|= inst
.operands
[3].reg
;
10123 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10125 do_mav_dspsc (void)
10127 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10130 /* Maverick shift immediate instructions.
10131 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10132 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10135 do_mav_shift (void)
10137 int imm
= inst
.operands
[2].imm
;
10139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10140 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10142 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10143 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10144 Bit 4 should be 0. */
10145 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10147 inst
.instruction
|= imm
;
10150 /* XScale instructions. Also sorted arithmetic before move. */
10152 /* Xscale multiply-accumulate (argument parse)
10155 MIAxycc acc0,Rm,Rs. */
10160 inst
.instruction
|= inst
.operands
[1].reg
;
10161 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10164 /* Xscale move-accumulator-register (argument parse)
10166 MARcc acc0,RdLo,RdHi. */
10171 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10172 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10175 /* Xscale move-register-accumulator (argument parse)
10177 MRAcc RdLo,RdHi,acc0. */
10182 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10187 /* Encoding functions relevant only to Thumb. */
10189 /* inst.operands[i] is a shifted-register operand; encode
10190 it into inst.instruction in the format used by Thumb32. */
10193 encode_thumb32_shifted_operand (int i
)
10195 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10196 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10198 constraint (inst
.operands
[i
].immisreg
,
10199 _("shift by register not allowed in thumb mode"));
10200 inst
.instruction
|= inst
.operands
[i
].reg
;
10201 if (shift
== SHIFT_RRX
)
10202 inst
.instruction
|= SHIFT_ROR
<< 4;
10205 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10206 _("expression too complex"));
10208 constraint (value
> 32
10209 || (value
== 32 && (shift
== SHIFT_LSL
10210 || shift
== SHIFT_ROR
)),
10211 _("shift expression is too large"));
10215 else if (value
== 32)
10218 inst
.instruction
|= shift
<< 4;
10219 inst
.instruction
|= (value
& 0x1c) << 10;
10220 inst
.instruction
|= (value
& 0x03) << 6;
10225 /* inst.operands[i] was set up by parse_address. Encode it into a
10226 Thumb32 format load or store instruction. Reject forms that cannot
10227 be used with such instructions. If is_t is true, reject forms that
10228 cannot be used with a T instruction; if is_d is true, reject forms
10229 that cannot be used with a D instruction. If it is a store insn,
10230 reject PC in Rn. */
10233 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10235 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10237 constraint (!inst
.operands
[i
].isreg
,
10238 _("Instruction does not support =N addresses"));
10240 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10241 if (inst
.operands
[i
].immisreg
)
10243 constraint (is_pc
, BAD_PC_ADDRESSING
);
10244 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10245 constraint (inst
.operands
[i
].negative
,
10246 _("Thumb does not support negative register indexing"));
10247 constraint (inst
.operands
[i
].postind
,
10248 _("Thumb does not support register post-indexing"));
10249 constraint (inst
.operands
[i
].writeback
,
10250 _("Thumb does not support register indexing with writeback"));
10251 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10252 _("Thumb supports only LSL in shifted register indexing"));
10254 inst
.instruction
|= inst
.operands
[i
].imm
;
10255 if (inst
.operands
[i
].shifted
)
10257 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10258 _("expression too complex"));
10259 constraint (inst
.reloc
.exp
.X_add_number
< 0
10260 || inst
.reloc
.exp
.X_add_number
> 3,
10261 _("shift out of range"));
10262 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10264 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10266 else if (inst
.operands
[i
].preind
)
10268 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10269 constraint (is_t
&& inst
.operands
[i
].writeback
,
10270 _("cannot use writeback with this instruction"));
10271 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10272 BAD_PC_ADDRESSING
);
10276 inst
.instruction
|= 0x01000000;
10277 if (inst
.operands
[i
].writeback
)
10278 inst
.instruction
|= 0x00200000;
10282 inst
.instruction
|= 0x00000c00;
10283 if (inst
.operands
[i
].writeback
)
10284 inst
.instruction
|= 0x00000100;
10286 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10288 else if (inst
.operands
[i
].postind
)
10290 gas_assert (inst
.operands
[i
].writeback
);
10291 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10292 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10295 inst
.instruction
|= 0x00200000;
10297 inst
.instruction
|= 0x00000900;
10298 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10300 else /* unindexed - only for coprocessor */
10301 inst
.error
= _("instruction does not accept unindexed addressing");
10304 /* Table of Thumb instructions which exist in both 16- and 32-bit
10305 encodings (the latter only in post-V6T2 cores). The index is the
10306 value used in the insns table below. When there is more than one
10307 possible 16-bit encoding for the instruction, this table always
10309 Also contains several pseudo-instructions used during relaxation. */
10310 #define T16_32_TAB \
10311 X(_adc, 4140, eb400000), \
10312 X(_adcs, 4140, eb500000), \
10313 X(_add, 1c00, eb000000), \
10314 X(_adds, 1c00, eb100000), \
10315 X(_addi, 0000, f1000000), \
10316 X(_addis, 0000, f1100000), \
10317 X(_add_pc,000f, f20f0000), \
10318 X(_add_sp,000d, f10d0000), \
10319 X(_adr, 000f, f20f0000), \
10320 X(_and, 4000, ea000000), \
10321 X(_ands, 4000, ea100000), \
10322 X(_asr, 1000, fa40f000), \
10323 X(_asrs, 1000, fa50f000), \
10324 X(_b, e000, f000b000), \
10325 X(_bcond, d000, f0008000), \
10326 X(_bic, 4380, ea200000), \
10327 X(_bics, 4380, ea300000), \
10328 X(_cmn, 42c0, eb100f00), \
10329 X(_cmp, 2800, ebb00f00), \
10330 X(_cpsie, b660, f3af8400), \
10331 X(_cpsid, b670, f3af8600), \
10332 X(_cpy, 4600, ea4f0000), \
10333 X(_dec_sp,80dd, f1ad0d00), \
10334 X(_eor, 4040, ea800000), \
10335 X(_eors, 4040, ea900000), \
10336 X(_inc_sp,00dd, f10d0d00), \
10337 X(_ldmia, c800, e8900000), \
10338 X(_ldr, 6800, f8500000), \
10339 X(_ldrb, 7800, f8100000), \
10340 X(_ldrh, 8800, f8300000), \
10341 X(_ldrsb, 5600, f9100000), \
10342 X(_ldrsh, 5e00, f9300000), \
10343 X(_ldr_pc,4800, f85f0000), \
10344 X(_ldr_pc2,4800, f85f0000), \
10345 X(_ldr_sp,9800, f85d0000), \
10346 X(_lsl, 0000, fa00f000), \
10347 X(_lsls, 0000, fa10f000), \
10348 X(_lsr, 0800, fa20f000), \
10349 X(_lsrs, 0800, fa30f000), \
10350 X(_mov, 2000, ea4f0000), \
10351 X(_movs, 2000, ea5f0000), \
10352 X(_mul, 4340, fb00f000), \
10353 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10354 X(_mvn, 43c0, ea6f0000), \
10355 X(_mvns, 43c0, ea7f0000), \
10356 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10357 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10358 X(_orr, 4300, ea400000), \
10359 X(_orrs, 4300, ea500000), \
10360 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10361 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10362 X(_rev, ba00, fa90f080), \
10363 X(_rev16, ba40, fa90f090), \
10364 X(_revsh, bac0, fa90f0b0), \
10365 X(_ror, 41c0, fa60f000), \
10366 X(_rors, 41c0, fa70f000), \
10367 X(_sbc, 4180, eb600000), \
10368 X(_sbcs, 4180, eb700000), \
10369 X(_stmia, c000, e8800000), \
10370 X(_str, 6000, f8400000), \
10371 X(_strb, 7000, f8000000), \
10372 X(_strh, 8000, f8200000), \
10373 X(_str_sp,9000, f84d0000), \
10374 X(_sub, 1e00, eba00000), \
10375 X(_subs, 1e00, ebb00000), \
10376 X(_subi, 8000, f1a00000), \
10377 X(_subis, 8000, f1b00000), \
10378 X(_sxtb, b240, fa4ff080), \
10379 X(_sxth, b200, fa0ff080), \
10380 X(_tst, 4200, ea100f00), \
10381 X(_uxtb, b2c0, fa5ff080), \
10382 X(_uxth, b280, fa1ff080), \
10383 X(_nop, bf00, f3af8000), \
10384 X(_yield, bf10, f3af8001), \
10385 X(_wfe, bf20, f3af8002), \
10386 X(_wfi, bf30, f3af8003), \
10387 X(_sev, bf40, f3af8004), \
10388 X(_sevl, bf50, f3af8005), \
10389 X(_udf, de00, f7f0a000)
10391 /* To catch errors in encoding functions, the codes are all offset by
10392 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10393 as 16-bit instructions. */
10394 #define X(a,b,c) T_MNEM##a
10395 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10398 #define X(a,b,c) 0x##b
10399 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10400 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10403 #define X(a,b,c) 0x##c
10404 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10405 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10406 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10410 /* Thumb instruction encoders, in alphabetical order. */
10412 /* ADDW or SUBW. */
10415 do_t_add_sub_w (void)
10419 Rd
= inst
.operands
[0].reg
;
10420 Rn
= inst
.operands
[1].reg
;
10422 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10423 is the SP-{plus,minus}-immediate form of the instruction. */
10425 constraint (Rd
== REG_PC
, BAD_PC
);
10427 reject_bad_reg (Rd
);
10429 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10430 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10433 /* Parse an add or subtract instruction. We get here with inst.instruction
10434 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10437 do_t_add_sub (void)
10441 Rd
= inst
.operands
[0].reg
;
10442 Rs
= (inst
.operands
[1].present
10443 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10444 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10447 set_it_insn_type_last ();
10449 if (unified_syntax
)
10452 bfd_boolean narrow
;
10455 flags
= (inst
.instruction
== T_MNEM_adds
10456 || inst
.instruction
== T_MNEM_subs
);
10458 narrow
= !in_it_block ();
10460 narrow
= in_it_block ();
10461 if (!inst
.operands
[2].isreg
)
10465 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10467 add
= (inst
.instruction
== T_MNEM_add
10468 || inst
.instruction
== T_MNEM_adds
);
10470 if (inst
.size_req
!= 4)
10472 /* Attempt to use a narrow opcode, with relaxation if
10474 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10475 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10476 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10477 opcode
= T_MNEM_add_sp
;
10478 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10479 opcode
= T_MNEM_add_pc
;
10480 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10483 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10485 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10489 inst
.instruction
= THUMB_OP16(opcode
);
10490 inst
.instruction
|= (Rd
<< 4) | Rs
;
10491 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10492 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10494 if (inst
.size_req
== 2)
10495 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10497 inst
.relax
= opcode
;
10501 constraint (inst
.size_req
== 2, BAD_HIREG
);
10503 if (inst
.size_req
== 4
10504 || (inst
.size_req
!= 2 && !opcode
))
10506 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10507 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10508 THUMB1_RELOC_ONLY
);
10511 constraint (add
, BAD_PC
);
10512 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10513 _("only SUBS PC, LR, #const allowed"));
10514 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10515 _("expression too complex"));
10516 constraint (inst
.reloc
.exp
.X_add_number
< 0
10517 || inst
.reloc
.exp
.X_add_number
> 0xff,
10518 _("immediate value out of range"));
10519 inst
.instruction
= T2_SUBS_PC_LR
10520 | inst
.reloc
.exp
.X_add_number
;
10521 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10524 else if (Rs
== REG_PC
)
10526 /* Always use addw/subw. */
10527 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10528 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10532 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10533 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10536 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10538 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10540 inst
.instruction
|= Rd
<< 8;
10541 inst
.instruction
|= Rs
<< 16;
10546 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10547 unsigned int shift
= inst
.operands
[2].shift_kind
;
10549 Rn
= inst
.operands
[2].reg
;
10550 /* See if we can do this with a 16-bit instruction. */
10551 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10553 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10558 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10559 || inst
.instruction
== T_MNEM_add
)
10561 : T_OPCODE_SUB_R3
);
10562 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10566 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10568 /* Thumb-1 cores (except v6-M) require at least one high
10569 register in a narrow non flag setting add. */
10570 if (Rd
> 7 || Rn
> 7
10571 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10572 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10579 inst
.instruction
= T_OPCODE_ADD_HI
;
10580 inst
.instruction
|= (Rd
& 8) << 4;
10581 inst
.instruction
|= (Rd
& 7);
10582 inst
.instruction
|= Rn
<< 3;
10588 constraint (Rd
== REG_PC
, BAD_PC
);
10589 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10590 constraint (Rs
== REG_PC
, BAD_PC
);
10591 reject_bad_reg (Rn
);
10593 /* If we get here, it can't be done in 16 bits. */
10594 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10595 _("shift must be constant"));
10596 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10597 inst
.instruction
|= Rd
<< 8;
10598 inst
.instruction
|= Rs
<< 16;
10599 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10600 _("shift value over 3 not allowed in thumb mode"));
10601 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10602 _("only LSL shift allowed in thumb mode"));
10603 encode_thumb32_shifted_operand (2);
10608 constraint (inst
.instruction
== T_MNEM_adds
10609 || inst
.instruction
== T_MNEM_subs
,
10612 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10614 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10615 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10618 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10619 ? 0x0000 : 0x8000);
10620 inst
.instruction
|= (Rd
<< 4) | Rs
;
10621 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10625 Rn
= inst
.operands
[2].reg
;
10626 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10628 /* We now have Rd, Rs, and Rn set to registers. */
10629 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10631 /* Can't do this for SUB. */
10632 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10633 inst
.instruction
= T_OPCODE_ADD_HI
;
10634 inst
.instruction
|= (Rd
& 8) << 4;
10635 inst
.instruction
|= (Rd
& 7);
10637 inst
.instruction
|= Rn
<< 3;
10639 inst
.instruction
|= Rs
<< 3;
10641 constraint (1, _("dest must overlap one source register"));
10645 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10646 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10647 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10657 Rd
= inst
.operands
[0].reg
;
10658 reject_bad_reg (Rd
);
10660 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10662 /* Defer to section relaxation. */
10663 inst
.relax
= inst
.instruction
;
10664 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10665 inst
.instruction
|= Rd
<< 4;
10667 else if (unified_syntax
&& inst
.size_req
!= 2)
10669 /* Generate a 32-bit opcode. */
10670 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10671 inst
.instruction
|= Rd
<< 8;
10672 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10673 inst
.reloc
.pc_rel
= 1;
10677 /* Generate a 16-bit opcode. */
10678 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10679 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10680 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10681 inst
.reloc
.pc_rel
= 1;
10683 inst
.instruction
|= Rd
<< 4;
10687 /* Arithmetic instructions for which there is just one 16-bit
10688 instruction encoding, and it allows only two low registers.
10689 For maximal compatibility with ARM syntax, we allow three register
10690 operands even when Thumb-32 instructions are not available, as long
10691 as the first two are identical. For instance, both "sbc r0,r1" and
10692 "sbc r0,r0,r1" are allowed. */
10698 Rd
= inst
.operands
[0].reg
;
10699 Rs
= (inst
.operands
[1].present
10700 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10701 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10702 Rn
= inst
.operands
[2].reg
;
10704 reject_bad_reg (Rd
);
10705 reject_bad_reg (Rs
);
10706 if (inst
.operands
[2].isreg
)
10707 reject_bad_reg (Rn
);
10709 if (unified_syntax
)
10711 if (!inst
.operands
[2].isreg
)
10713 /* For an immediate, we always generate a 32-bit opcode;
10714 section relaxation will shrink it later if possible. */
10715 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10716 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10717 inst
.instruction
|= Rd
<< 8;
10718 inst
.instruction
|= Rs
<< 16;
10719 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10723 bfd_boolean narrow
;
10725 /* See if we can do this with a 16-bit instruction. */
10726 if (THUMB_SETS_FLAGS (inst
.instruction
))
10727 narrow
= !in_it_block ();
10729 narrow
= in_it_block ();
10731 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10733 if (inst
.operands
[2].shifted
)
10735 if (inst
.size_req
== 4)
10741 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10742 inst
.instruction
|= Rd
;
10743 inst
.instruction
|= Rn
<< 3;
10747 /* If we get here, it can't be done in 16 bits. */
10748 constraint (inst
.operands
[2].shifted
10749 && inst
.operands
[2].immisreg
,
10750 _("shift must be constant"));
10751 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10752 inst
.instruction
|= Rd
<< 8;
10753 inst
.instruction
|= Rs
<< 16;
10754 encode_thumb32_shifted_operand (2);
10759 /* On its face this is a lie - the instruction does set the
10760 flags. However, the only supported mnemonic in this mode
10761 says it doesn't. */
10762 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10764 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10765 _("unshifted register required"));
10766 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10767 constraint (Rd
!= Rs
,
10768 _("dest and source1 must be the same register"));
10770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10771 inst
.instruction
|= Rd
;
10772 inst
.instruction
|= Rn
<< 3;
10776 /* Similarly, but for instructions where the arithmetic operation is
10777 commutative, so we can allow either of them to be different from
10778 the destination operand in a 16-bit instruction. For instance, all
10779 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10786 Rd
= inst
.operands
[0].reg
;
10787 Rs
= (inst
.operands
[1].present
10788 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10789 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10790 Rn
= inst
.operands
[2].reg
;
10792 reject_bad_reg (Rd
);
10793 reject_bad_reg (Rs
);
10794 if (inst
.operands
[2].isreg
)
10795 reject_bad_reg (Rn
);
10797 if (unified_syntax
)
10799 if (!inst
.operands
[2].isreg
)
10801 /* For an immediate, we always generate a 32-bit opcode;
10802 section relaxation will shrink it later if possible. */
10803 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10804 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10805 inst
.instruction
|= Rd
<< 8;
10806 inst
.instruction
|= Rs
<< 16;
10807 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10811 bfd_boolean narrow
;
10813 /* See if we can do this with a 16-bit instruction. */
10814 if (THUMB_SETS_FLAGS (inst
.instruction
))
10815 narrow
= !in_it_block ();
10817 narrow
= in_it_block ();
10819 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10821 if (inst
.operands
[2].shifted
)
10823 if (inst
.size_req
== 4)
10830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10831 inst
.instruction
|= Rd
;
10832 inst
.instruction
|= Rn
<< 3;
10837 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10838 inst
.instruction
|= Rd
;
10839 inst
.instruction
|= Rs
<< 3;
10844 /* If we get here, it can't be done in 16 bits. */
10845 constraint (inst
.operands
[2].shifted
10846 && inst
.operands
[2].immisreg
,
10847 _("shift must be constant"));
10848 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10849 inst
.instruction
|= Rd
<< 8;
10850 inst
.instruction
|= Rs
<< 16;
10851 encode_thumb32_shifted_operand (2);
10856 /* On its face this is a lie - the instruction does set the
10857 flags. However, the only supported mnemonic in this mode
10858 says it doesn't. */
10859 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10861 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10862 _("unshifted register required"));
10863 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10865 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10866 inst
.instruction
|= Rd
;
10869 inst
.instruction
|= Rn
<< 3;
10871 inst
.instruction
|= Rs
<< 3;
10873 constraint (1, _("dest must overlap one source register"));
10881 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10882 constraint (msb
> 32, _("bit-field extends past end of register"));
10883 /* The instruction encoding stores the LSB and MSB,
10884 not the LSB and width. */
10885 Rd
= inst
.operands
[0].reg
;
10886 reject_bad_reg (Rd
);
10887 inst
.instruction
|= Rd
<< 8;
10888 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10889 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10890 inst
.instruction
|= msb
- 1;
10899 Rd
= inst
.operands
[0].reg
;
10900 reject_bad_reg (Rd
);
10902 /* #0 in second position is alternative syntax for bfc, which is
10903 the same instruction but with REG_PC in the Rm field. */
10904 if (!inst
.operands
[1].isreg
)
10908 Rn
= inst
.operands
[1].reg
;
10909 reject_bad_reg (Rn
);
10912 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10913 constraint (msb
> 32, _("bit-field extends past end of register"));
10914 /* The instruction encoding stores the LSB and MSB,
10915 not the LSB and width. */
10916 inst
.instruction
|= Rd
<< 8;
10917 inst
.instruction
|= Rn
<< 16;
10918 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10919 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10920 inst
.instruction
|= msb
- 1;
10928 Rd
= inst
.operands
[0].reg
;
10929 Rn
= inst
.operands
[1].reg
;
10931 reject_bad_reg (Rd
);
10932 reject_bad_reg (Rn
);
10934 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10935 _("bit-field extends past end of register"));
10936 inst
.instruction
|= Rd
<< 8;
10937 inst
.instruction
|= Rn
<< 16;
10938 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10939 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10940 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10943 /* ARM V5 Thumb BLX (argument parse)
10944 BLX <target_addr> which is BLX(1)
10945 BLX <Rm> which is BLX(2)
10946 Unfortunately, there are two different opcodes for this mnemonic.
10947 So, the insns[].value is not used, and the code here zaps values
10948 into inst.instruction.
10950 ??? How to take advantage of the additional two bits of displacement
10951 available in Thumb32 mode? Need new relocation? */
10956 set_it_insn_type_last ();
10958 if (inst
.operands
[0].isreg
)
10960 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10961 /* We have a register, so this is BLX(2). */
10962 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10966 /* No register. This must be BLX(1). */
10967 inst
.instruction
= 0xf000e800;
10968 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10977 bfd_reloc_code_real_type reloc
;
10980 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10982 if (in_it_block ())
10984 /* Conditional branches inside IT blocks are encoded as unconditional
10986 cond
= COND_ALWAYS
;
10991 if (cond
!= COND_ALWAYS
)
10992 opcode
= T_MNEM_bcond
;
10994 opcode
= inst
.instruction
;
10997 && (inst
.size_req
== 4
10998 || (inst
.size_req
!= 2
10999 && (inst
.operands
[0].hasreloc
11000 || inst
.reloc
.exp
.X_op
== O_constant
))))
11002 inst
.instruction
= THUMB_OP32(opcode
);
11003 if (cond
== COND_ALWAYS
)
11004 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11007 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11008 _("selected architecture does not support "
11009 "wide conditional branch instruction"));
11011 gas_assert (cond
!= 0xF);
11012 inst
.instruction
|= cond
<< 22;
11013 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11018 inst
.instruction
= THUMB_OP16(opcode
);
11019 if (cond
== COND_ALWAYS
)
11020 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11023 inst
.instruction
|= cond
<< 8;
11024 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11026 /* Allow section relaxation. */
11027 if (unified_syntax
&& inst
.size_req
!= 2)
11028 inst
.relax
= opcode
;
11030 inst
.reloc
.type
= reloc
;
11031 inst
.reloc
.pc_rel
= 1;
11034 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11035 between the two is the maximum immediate allowed - which is passed in
11038 do_t_bkpt_hlt1 (int range
)
11040 constraint (inst
.cond
!= COND_ALWAYS
,
11041 _("instruction is always unconditional"));
11042 if (inst
.operands
[0].present
)
11044 constraint (inst
.operands
[0].imm
> range
,
11045 _("immediate value out of range"));
11046 inst
.instruction
|= inst
.operands
[0].imm
;
11049 set_it_insn_type (NEUTRAL_IT_INSN
);
11055 do_t_bkpt_hlt1 (63);
11061 do_t_bkpt_hlt1 (255);
11065 do_t_branch23 (void)
11067 set_it_insn_type_last ();
11068 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11070 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11071 this file. We used to simply ignore the PLT reloc type here --
11072 the branch encoding is now needed to deal with TLSCALL relocs.
11073 So if we see a PLT reloc now, put it back to how it used to be to
11074 keep the preexisting behaviour. */
11075 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11076 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11078 #if defined(OBJ_COFF)
11079 /* If the destination of the branch is a defined symbol which does not have
11080 the THUMB_FUNC attribute, then we must be calling a function which has
11081 the (interfacearm) attribute. We look for the Thumb entry point to that
11082 function and change the branch to refer to that function instead. */
11083 if ( inst
.reloc
.exp
.X_op
== O_symbol
11084 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11085 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11086 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11087 inst
.reloc
.exp
.X_add_symbol
=
11088 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11095 set_it_insn_type_last ();
11096 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11097 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11098 should cause the alignment to be checked once it is known. This is
11099 because BX PC only works if the instruction is word aligned. */
11107 set_it_insn_type_last ();
11108 Rm
= inst
.operands
[0].reg
;
11109 reject_bad_reg (Rm
);
11110 inst
.instruction
|= Rm
<< 16;
11119 Rd
= inst
.operands
[0].reg
;
11120 Rm
= inst
.operands
[1].reg
;
11122 reject_bad_reg (Rd
);
11123 reject_bad_reg (Rm
);
11125 inst
.instruction
|= Rd
<< 8;
11126 inst
.instruction
|= Rm
<< 16;
11127 inst
.instruction
|= Rm
;
11133 set_it_insn_type (OUTSIDE_IT_INSN
);
11134 inst
.instruction
|= inst
.operands
[0].imm
;
11140 set_it_insn_type (OUTSIDE_IT_INSN
);
11142 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11143 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11145 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11146 inst
.instruction
= 0xf3af8000;
11147 inst
.instruction
|= imod
<< 9;
11148 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11149 if (inst
.operands
[1].present
)
11150 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11155 && (inst
.operands
[0].imm
& 4),
11156 _("selected processor does not support 'A' form "
11157 "of this instruction"));
11158 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11159 _("Thumb does not support the 2-argument "
11160 "form of this instruction"));
11161 inst
.instruction
|= inst
.operands
[0].imm
;
11165 /* THUMB CPY instruction (argument parse). */
11170 if (inst
.size_req
== 4)
11172 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11173 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11174 inst
.instruction
|= inst
.operands
[1].reg
;
11178 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11179 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11180 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11187 set_it_insn_type (OUTSIDE_IT_INSN
);
11188 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11189 inst
.instruction
|= inst
.operands
[0].reg
;
11190 inst
.reloc
.pc_rel
= 1;
11191 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11197 inst
.instruction
|= inst
.operands
[0].imm
;
11203 unsigned Rd
, Rn
, Rm
;
11205 Rd
= inst
.operands
[0].reg
;
11206 Rn
= (inst
.operands
[1].present
11207 ? inst
.operands
[1].reg
: Rd
);
11208 Rm
= inst
.operands
[2].reg
;
11210 reject_bad_reg (Rd
);
11211 reject_bad_reg (Rn
);
11212 reject_bad_reg (Rm
);
11214 inst
.instruction
|= Rd
<< 8;
11215 inst
.instruction
|= Rn
<< 16;
11216 inst
.instruction
|= Rm
;
11222 if (unified_syntax
&& inst
.size_req
== 4)
11223 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11225 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11231 unsigned int cond
= inst
.operands
[0].imm
;
11233 set_it_insn_type (IT_INSN
);
11234 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11236 now_it
.warn_deprecated
= FALSE
;
11238 /* If the condition is a negative condition, invert the mask. */
11239 if ((cond
& 0x1) == 0x0)
11241 unsigned int mask
= inst
.instruction
& 0x000f;
11243 if ((mask
& 0x7) == 0)
11245 /* No conversion needed. */
11246 now_it
.block_length
= 1;
11248 else if ((mask
& 0x3) == 0)
11251 now_it
.block_length
= 2;
11253 else if ((mask
& 0x1) == 0)
11256 now_it
.block_length
= 3;
11261 now_it
.block_length
= 4;
11264 inst
.instruction
&= 0xfff0;
11265 inst
.instruction
|= mask
;
11268 inst
.instruction
|= cond
<< 4;
11271 /* Helper function used for both push/pop and ldm/stm. */
11273 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11277 load
= (inst
.instruction
& (1 << 20)) != 0;
11279 if (mask
& (1 << 13))
11280 inst
.error
= _("SP not allowed in register list");
11282 if ((mask
& (1 << base
)) != 0
11284 inst
.error
= _("having the base register in the register list when "
11285 "using write back is UNPREDICTABLE");
11289 if (mask
& (1 << 15))
11291 if (mask
& (1 << 14))
11292 inst
.error
= _("LR and PC should not both be in register list");
11294 set_it_insn_type_last ();
11299 if (mask
& (1 << 15))
11300 inst
.error
= _("PC not allowed in register list");
11303 if ((mask
& (mask
- 1)) == 0)
11305 /* Single register transfers implemented as str/ldr. */
11308 if (inst
.instruction
& (1 << 23))
11309 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11311 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11315 if (inst
.instruction
& (1 << 23))
11316 inst
.instruction
= 0x00800000; /* ia -> [base] */
11318 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11321 inst
.instruction
|= 0xf8400000;
11323 inst
.instruction
|= 0x00100000;
11325 mask
= ffs (mask
) - 1;
11328 else if (writeback
)
11329 inst
.instruction
|= WRITE_BACK
;
11331 inst
.instruction
|= mask
;
11332 inst
.instruction
|= base
<< 16;
11338 /* This really doesn't seem worth it. */
11339 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11340 _("expression too complex"));
11341 constraint (inst
.operands
[1].writeback
,
11342 _("Thumb load/store multiple does not support {reglist}^"));
11344 if (unified_syntax
)
11346 bfd_boolean narrow
;
11350 /* See if we can use a 16-bit instruction. */
11351 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11352 && inst
.size_req
!= 4
11353 && !(inst
.operands
[1].imm
& ~0xff))
11355 mask
= 1 << inst
.operands
[0].reg
;
11357 if (inst
.operands
[0].reg
<= 7)
11359 if (inst
.instruction
== T_MNEM_stmia
11360 ? inst
.operands
[0].writeback
11361 : (inst
.operands
[0].writeback
11362 == !(inst
.operands
[1].imm
& mask
)))
11364 if (inst
.instruction
== T_MNEM_stmia
11365 && (inst
.operands
[1].imm
& mask
)
11366 && (inst
.operands
[1].imm
& (mask
- 1)))
11367 as_warn (_("value stored for r%d is UNKNOWN"),
11368 inst
.operands
[0].reg
);
11370 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11371 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11372 inst
.instruction
|= inst
.operands
[1].imm
;
11375 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11377 /* This means 1 register in reg list one of 3 situations:
11378 1. Instruction is stmia, but without writeback.
11379 2. lmdia without writeback, but with Rn not in
11381 3. ldmia with writeback, but with Rn in reglist.
11382 Case 3 is UNPREDICTABLE behaviour, so we handle
11383 case 1 and 2 which can be converted into a 16-bit
11384 str or ldr. The SP cases are handled below. */
11385 unsigned long opcode
;
11386 /* First, record an error for Case 3. */
11387 if (inst
.operands
[1].imm
& mask
11388 && inst
.operands
[0].writeback
)
11390 _("having the base register in the register list when "
11391 "using write back is UNPREDICTABLE");
11393 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11395 inst
.instruction
= THUMB_OP16 (opcode
);
11396 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11397 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11401 else if (inst
.operands
[0] .reg
== REG_SP
)
11403 if (inst
.operands
[0].writeback
)
11406 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11407 ? T_MNEM_push
: T_MNEM_pop
);
11408 inst
.instruction
|= inst
.operands
[1].imm
;
11411 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11414 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11415 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11416 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11424 if (inst
.instruction
< 0xffff)
11425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11427 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11428 inst
.operands
[0].writeback
);
11433 constraint (inst
.operands
[0].reg
> 7
11434 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11435 constraint (inst
.instruction
!= T_MNEM_ldmia
11436 && inst
.instruction
!= T_MNEM_stmia
,
11437 _("Thumb-2 instruction only valid in unified syntax"));
11438 if (inst
.instruction
== T_MNEM_stmia
)
11440 if (!inst
.operands
[0].writeback
)
11441 as_warn (_("this instruction will write back the base register"));
11442 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11443 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11444 as_warn (_("value stored for r%d is UNKNOWN"),
11445 inst
.operands
[0].reg
);
11449 if (!inst
.operands
[0].writeback
11450 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11451 as_warn (_("this instruction will write back the base register"));
11452 else if (inst
.operands
[0].writeback
11453 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11454 as_warn (_("this instruction will not write back the base register"));
11457 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11458 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11459 inst
.instruction
|= inst
.operands
[1].imm
;
11466 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11467 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11468 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11469 || inst
.operands
[1].negative
,
11472 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11475 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11476 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11482 if (!inst
.operands
[1].present
)
11484 constraint (inst
.operands
[0].reg
== REG_LR
,
11485 _("r14 not allowed as first register "
11486 "when second register is omitted"));
11487 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11489 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11493 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11494 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11500 unsigned long opcode
;
11503 if (inst
.operands
[0].isreg
11504 && !inst
.operands
[0].preind
11505 && inst
.operands
[0].reg
== REG_PC
)
11506 set_it_insn_type_last ();
11508 opcode
= inst
.instruction
;
11509 if (unified_syntax
)
11511 if (!inst
.operands
[1].isreg
)
11513 if (opcode
<= 0xffff)
11514 inst
.instruction
= THUMB_OP32 (opcode
);
11515 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11518 if (inst
.operands
[1].isreg
11519 && !inst
.operands
[1].writeback
11520 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11521 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11522 && opcode
<= 0xffff
11523 && inst
.size_req
!= 4)
11525 /* Insn may have a 16-bit form. */
11526 Rn
= inst
.operands
[1].reg
;
11527 if (inst
.operands
[1].immisreg
)
11529 inst
.instruction
= THUMB_OP16 (opcode
);
11531 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11533 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11534 reject_bad_reg (inst
.operands
[1].imm
);
11536 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11537 && opcode
!= T_MNEM_ldrsb
)
11538 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11539 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11546 if (inst
.reloc
.pc_rel
)
11547 opcode
= T_MNEM_ldr_pc2
;
11549 opcode
= T_MNEM_ldr_pc
;
11553 if (opcode
== T_MNEM_ldr
)
11554 opcode
= T_MNEM_ldr_sp
;
11556 opcode
= T_MNEM_str_sp
;
11558 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11562 inst
.instruction
= inst
.operands
[0].reg
;
11563 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11565 inst
.instruction
|= THUMB_OP16 (opcode
);
11566 if (inst
.size_req
== 2)
11567 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11569 inst
.relax
= opcode
;
11573 /* Definitely a 32-bit variant. */
11575 /* Warning for Erratum 752419. */
11576 if (opcode
== T_MNEM_ldr
11577 && inst
.operands
[0].reg
== REG_SP
11578 && inst
.operands
[1].writeback
== 1
11579 && !inst
.operands
[1].immisreg
)
11581 if (no_cpu_selected ()
11582 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11583 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11584 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11585 as_warn (_("This instruction may be unpredictable "
11586 "if executed on M-profile cores "
11587 "with interrupts enabled."));
11590 /* Do some validations regarding addressing modes. */
11591 if (inst
.operands
[1].immisreg
)
11592 reject_bad_reg (inst
.operands
[1].imm
);
11594 constraint (inst
.operands
[1].writeback
== 1
11595 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11598 inst
.instruction
= THUMB_OP32 (opcode
);
11599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11600 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11601 check_ldr_r15_aligned ();
11605 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11607 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11609 /* Only [Rn,Rm] is acceptable. */
11610 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11611 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11612 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11613 || inst
.operands
[1].negative
,
11614 _("Thumb does not support this addressing mode"));
11615 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11619 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11620 if (!inst
.operands
[1].isreg
)
11621 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11624 constraint (!inst
.operands
[1].preind
11625 || inst
.operands
[1].shifted
11626 || inst
.operands
[1].writeback
,
11627 _("Thumb does not support this addressing mode"));
11628 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11630 constraint (inst
.instruction
& 0x0600,
11631 _("byte or halfword not valid for base register"));
11632 constraint (inst
.operands
[1].reg
== REG_PC
11633 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11634 _("r15 based store not allowed"));
11635 constraint (inst
.operands
[1].immisreg
,
11636 _("invalid base register for register offset"));
11638 if (inst
.operands
[1].reg
== REG_PC
)
11639 inst
.instruction
= T_OPCODE_LDR_PC
;
11640 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11641 inst
.instruction
= T_OPCODE_LDR_SP
;
11643 inst
.instruction
= T_OPCODE_STR_SP
;
11645 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11646 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11650 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11651 if (!inst
.operands
[1].immisreg
)
11653 /* Immediate offset. */
11654 inst
.instruction
|= inst
.operands
[0].reg
;
11655 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11656 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11660 /* Register offset. */
11661 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11662 constraint (inst
.operands
[1].negative
,
11663 _("Thumb does not support this addressing mode"));
11666 switch (inst
.instruction
)
11668 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11669 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11670 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11671 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11672 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11673 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11674 case 0x5600 /* ldrsb */:
11675 case 0x5e00 /* ldrsh */: break;
11679 inst
.instruction
|= inst
.operands
[0].reg
;
11680 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11681 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11687 if (!inst
.operands
[1].present
)
11689 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11690 constraint (inst
.operands
[0].reg
== REG_LR
,
11691 _("r14 not allowed here"));
11692 constraint (inst
.operands
[0].reg
== REG_R12
,
11693 _("r12 not allowed here"));
11696 if (inst
.operands
[2].writeback
11697 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11698 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11699 as_warn (_("base register written back, and overlaps "
11700 "one of transfer registers"));
11702 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11703 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11704 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11711 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11717 unsigned Rd
, Rn
, Rm
, Ra
;
11719 Rd
= inst
.operands
[0].reg
;
11720 Rn
= inst
.operands
[1].reg
;
11721 Rm
= inst
.operands
[2].reg
;
11722 Ra
= inst
.operands
[3].reg
;
11724 reject_bad_reg (Rd
);
11725 reject_bad_reg (Rn
);
11726 reject_bad_reg (Rm
);
11727 reject_bad_reg (Ra
);
11729 inst
.instruction
|= Rd
<< 8;
11730 inst
.instruction
|= Rn
<< 16;
11731 inst
.instruction
|= Rm
;
11732 inst
.instruction
|= Ra
<< 12;
11738 unsigned RdLo
, RdHi
, Rn
, Rm
;
11740 RdLo
= inst
.operands
[0].reg
;
11741 RdHi
= inst
.operands
[1].reg
;
11742 Rn
= inst
.operands
[2].reg
;
11743 Rm
= inst
.operands
[3].reg
;
11745 reject_bad_reg (RdLo
);
11746 reject_bad_reg (RdHi
);
11747 reject_bad_reg (Rn
);
11748 reject_bad_reg (Rm
);
11750 inst
.instruction
|= RdLo
<< 12;
11751 inst
.instruction
|= RdHi
<< 8;
11752 inst
.instruction
|= Rn
<< 16;
11753 inst
.instruction
|= Rm
;
11757 do_t_mov_cmp (void)
11761 Rn
= inst
.operands
[0].reg
;
11762 Rm
= inst
.operands
[1].reg
;
11765 set_it_insn_type_last ();
11767 if (unified_syntax
)
11769 int r0off
= (inst
.instruction
== T_MNEM_mov
11770 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11771 unsigned long opcode
;
11772 bfd_boolean narrow
;
11773 bfd_boolean low_regs
;
11775 low_regs
= (Rn
<= 7 && Rm
<= 7);
11776 opcode
= inst
.instruction
;
11777 if (in_it_block ())
11778 narrow
= opcode
!= T_MNEM_movs
;
11780 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11781 if (inst
.size_req
== 4
11782 || inst
.operands
[1].shifted
)
11785 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11786 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11787 && !inst
.operands
[1].shifted
11791 inst
.instruction
= T2_SUBS_PC_LR
;
11795 if (opcode
== T_MNEM_cmp
)
11797 constraint (Rn
== REG_PC
, BAD_PC
);
11800 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11802 warn_deprecated_sp (Rm
);
11803 /* R15 was documented as a valid choice for Rm in ARMv6,
11804 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11805 tools reject R15, so we do too. */
11806 constraint (Rm
== REG_PC
, BAD_PC
);
11809 reject_bad_reg (Rm
);
11811 else if (opcode
== T_MNEM_mov
11812 || opcode
== T_MNEM_movs
)
11814 if (inst
.operands
[1].isreg
)
11816 if (opcode
== T_MNEM_movs
)
11818 reject_bad_reg (Rn
);
11819 reject_bad_reg (Rm
);
11823 /* This is mov.n. */
11824 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11825 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11827 as_tsktsk (_("Use of r%u as a source register is "
11828 "deprecated when r%u is the destination "
11829 "register."), Rm
, Rn
);
11834 /* This is mov.w. */
11835 constraint (Rn
== REG_PC
, BAD_PC
);
11836 constraint (Rm
== REG_PC
, BAD_PC
);
11837 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11841 reject_bad_reg (Rn
);
11844 if (!inst
.operands
[1].isreg
)
11846 /* Immediate operand. */
11847 if (!in_it_block () && opcode
== T_MNEM_mov
)
11849 if (low_regs
&& narrow
)
11851 inst
.instruction
= THUMB_OP16 (opcode
);
11852 inst
.instruction
|= Rn
<< 8;
11853 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11854 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11856 if (inst
.size_req
== 2)
11857 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11859 inst
.relax
= opcode
;
11864 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11865 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11866 THUMB1_RELOC_ONLY
);
11868 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11869 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11870 inst
.instruction
|= Rn
<< r0off
;
11871 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11874 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11875 && (inst
.instruction
== T_MNEM_mov
11876 || inst
.instruction
== T_MNEM_movs
))
11878 /* Register shifts are encoded as separate shift instructions. */
11879 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11881 if (in_it_block ())
11886 if (inst
.size_req
== 4)
11889 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11895 switch (inst
.operands
[1].shift_kind
)
11898 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11901 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11904 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11907 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11913 inst
.instruction
= opcode
;
11916 inst
.instruction
|= Rn
;
11917 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11922 inst
.instruction
|= CONDS_BIT
;
11924 inst
.instruction
|= Rn
<< 8;
11925 inst
.instruction
|= Rm
<< 16;
11926 inst
.instruction
|= inst
.operands
[1].imm
;
11931 /* Some mov with immediate shift have narrow variants.
11932 Register shifts are handled above. */
11933 if (low_regs
&& inst
.operands
[1].shifted
11934 && (inst
.instruction
== T_MNEM_mov
11935 || inst
.instruction
== T_MNEM_movs
))
11937 if (in_it_block ())
11938 narrow
= (inst
.instruction
== T_MNEM_mov
);
11940 narrow
= (inst
.instruction
== T_MNEM_movs
);
11945 switch (inst
.operands
[1].shift_kind
)
11947 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11948 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11949 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11950 default: narrow
= FALSE
; break;
11956 inst
.instruction
|= Rn
;
11957 inst
.instruction
|= Rm
<< 3;
11958 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11962 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11963 inst
.instruction
|= Rn
<< r0off
;
11964 encode_thumb32_shifted_operand (1);
11968 switch (inst
.instruction
)
11971 /* In v4t or v5t a move of two lowregs produces unpredictable
11972 results. Don't allow this. */
11975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11976 "MOV Rd, Rs with two low registers is not "
11977 "permitted on this architecture");
11978 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11982 inst
.instruction
= T_OPCODE_MOV_HR
;
11983 inst
.instruction
|= (Rn
& 0x8) << 4;
11984 inst
.instruction
|= (Rn
& 0x7);
11985 inst
.instruction
|= Rm
<< 3;
11989 /* We know we have low registers at this point.
11990 Generate LSLS Rd, Rs, #0. */
11991 inst
.instruction
= T_OPCODE_LSL_I
;
11992 inst
.instruction
|= Rn
;
11993 inst
.instruction
|= Rm
<< 3;
11999 inst
.instruction
= T_OPCODE_CMP_LR
;
12000 inst
.instruction
|= Rn
;
12001 inst
.instruction
|= Rm
<< 3;
12005 inst
.instruction
= T_OPCODE_CMP_HR
;
12006 inst
.instruction
|= (Rn
& 0x8) << 4;
12007 inst
.instruction
|= (Rn
& 0x7);
12008 inst
.instruction
|= Rm
<< 3;
12015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12017 /* PR 10443: Do not silently ignore shifted operands. */
12018 constraint (inst
.operands
[1].shifted
,
12019 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12021 if (inst
.operands
[1].isreg
)
12023 if (Rn
< 8 && Rm
< 8)
12025 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12026 since a MOV instruction produces unpredictable results. */
12027 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12028 inst
.instruction
= T_OPCODE_ADD_I3
;
12030 inst
.instruction
= T_OPCODE_CMP_LR
;
12032 inst
.instruction
|= Rn
;
12033 inst
.instruction
|= Rm
<< 3;
12037 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12038 inst
.instruction
= T_OPCODE_MOV_HR
;
12040 inst
.instruction
= T_OPCODE_CMP_HR
;
12046 constraint (Rn
> 7,
12047 _("only lo regs allowed with immediate"));
12048 inst
.instruction
|= Rn
<< 8;
12049 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12060 top
= (inst
.instruction
& 0x00800000) != 0;
12061 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12063 constraint (top
, _(":lower16: not allowed this instruction"));
12064 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12066 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12068 constraint (!top
, _(":upper16: not allowed this instruction"));
12069 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12072 Rd
= inst
.operands
[0].reg
;
12073 reject_bad_reg (Rd
);
12075 inst
.instruction
|= Rd
<< 8;
12076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12078 imm
= inst
.reloc
.exp
.X_add_number
;
12079 inst
.instruction
|= (imm
& 0xf000) << 4;
12080 inst
.instruction
|= (imm
& 0x0800) << 15;
12081 inst
.instruction
|= (imm
& 0x0700) << 4;
12082 inst
.instruction
|= (imm
& 0x00ff);
12087 do_t_mvn_tst (void)
12091 Rn
= inst
.operands
[0].reg
;
12092 Rm
= inst
.operands
[1].reg
;
12094 if (inst
.instruction
== T_MNEM_cmp
12095 || inst
.instruction
== T_MNEM_cmn
)
12096 constraint (Rn
== REG_PC
, BAD_PC
);
12098 reject_bad_reg (Rn
);
12099 reject_bad_reg (Rm
);
12101 if (unified_syntax
)
12103 int r0off
= (inst
.instruction
== T_MNEM_mvn
12104 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12105 bfd_boolean narrow
;
12107 if (inst
.size_req
== 4
12108 || inst
.instruction
> 0xffff
12109 || inst
.operands
[1].shifted
12110 || Rn
> 7 || Rm
> 7)
12112 else if (inst
.instruction
== T_MNEM_cmn
12113 || inst
.instruction
== T_MNEM_tst
)
12115 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12116 narrow
= !in_it_block ();
12118 narrow
= in_it_block ();
12120 if (!inst
.operands
[1].isreg
)
12122 /* For an immediate, we always generate a 32-bit opcode;
12123 section relaxation will shrink it later if possible. */
12124 if (inst
.instruction
< 0xffff)
12125 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12126 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12127 inst
.instruction
|= Rn
<< r0off
;
12128 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12132 /* See if we can do this with a 16-bit instruction. */
12135 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12136 inst
.instruction
|= Rn
;
12137 inst
.instruction
|= Rm
<< 3;
12141 constraint (inst
.operands
[1].shifted
12142 && inst
.operands
[1].immisreg
,
12143 _("shift must be constant"));
12144 if (inst
.instruction
< 0xffff)
12145 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12146 inst
.instruction
|= Rn
<< r0off
;
12147 encode_thumb32_shifted_operand (1);
12153 constraint (inst
.instruction
> 0xffff
12154 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12155 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12156 _("unshifted register required"));
12157 constraint (Rn
> 7 || Rm
> 7,
12160 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12161 inst
.instruction
|= Rn
;
12162 inst
.instruction
|= Rm
<< 3;
12171 if (do_vfp_nsyn_mrs () == SUCCESS
)
12174 Rd
= inst
.operands
[0].reg
;
12175 reject_bad_reg (Rd
);
12176 inst
.instruction
|= Rd
<< 8;
12178 if (inst
.operands
[1].isreg
)
12180 unsigned br
= inst
.operands
[1].reg
;
12181 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12182 as_bad (_("bad register for mrs"));
12184 inst
.instruction
|= br
& (0xf << 16);
12185 inst
.instruction
|= (br
& 0x300) >> 4;
12186 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12190 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12192 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12194 /* PR gas/12698: The constraint is only applied for m_profile.
12195 If the user has specified -march=all, we want to ignore it as
12196 we are building for any CPU type, including non-m variants. */
12197 bfd_boolean m_profile
=
12198 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12199 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12200 "not support requested special purpose register"));
12203 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12205 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12206 _("'APSR', 'CPSR' or 'SPSR' expected"));
12208 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12209 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12210 inst
.instruction
|= 0xf0000;
12220 if (do_vfp_nsyn_msr () == SUCCESS
)
12223 constraint (!inst
.operands
[1].isreg
,
12224 _("Thumb encoding does not support an immediate here"));
12226 if (inst
.operands
[0].isreg
)
12227 flags
= (int)(inst
.operands
[0].reg
);
12229 flags
= inst
.operands
[0].imm
;
12231 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12233 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12235 /* PR gas/12698: The constraint is only applied for m_profile.
12236 If the user has specified -march=all, we want to ignore it as
12237 we are building for any CPU type, including non-m variants. */
12238 bfd_boolean m_profile
=
12239 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12240 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12241 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12242 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12243 && bits
!= PSR_f
)) && m_profile
,
12244 _("selected processor does not support requested special "
12245 "purpose register"));
12248 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12249 "requested special purpose register"));
12251 Rn
= inst
.operands
[1].reg
;
12252 reject_bad_reg (Rn
);
12254 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12255 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12256 inst
.instruction
|= (flags
& 0x300) >> 4;
12257 inst
.instruction
|= (flags
& 0xff);
12258 inst
.instruction
|= Rn
<< 16;
12264 bfd_boolean narrow
;
12265 unsigned Rd
, Rn
, Rm
;
12267 if (!inst
.operands
[2].present
)
12268 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12270 Rd
= inst
.operands
[0].reg
;
12271 Rn
= inst
.operands
[1].reg
;
12272 Rm
= inst
.operands
[2].reg
;
12274 if (unified_syntax
)
12276 if (inst
.size_req
== 4
12282 else if (inst
.instruction
== T_MNEM_muls
)
12283 narrow
= !in_it_block ();
12285 narrow
= in_it_block ();
12289 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12290 constraint (Rn
> 7 || Rm
> 7,
12297 /* 16-bit MULS/Conditional MUL. */
12298 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12299 inst
.instruction
|= Rd
;
12302 inst
.instruction
|= Rm
<< 3;
12304 inst
.instruction
|= Rn
<< 3;
12306 constraint (1, _("dest must overlap one source register"));
12310 constraint (inst
.instruction
!= T_MNEM_mul
,
12311 _("Thumb-2 MUL must not set flags"));
12313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12314 inst
.instruction
|= Rd
<< 8;
12315 inst
.instruction
|= Rn
<< 16;
12316 inst
.instruction
|= Rm
<< 0;
12318 reject_bad_reg (Rd
);
12319 reject_bad_reg (Rn
);
12320 reject_bad_reg (Rm
);
12327 unsigned RdLo
, RdHi
, Rn
, Rm
;
12329 RdLo
= inst
.operands
[0].reg
;
12330 RdHi
= inst
.operands
[1].reg
;
12331 Rn
= inst
.operands
[2].reg
;
12332 Rm
= inst
.operands
[3].reg
;
12334 reject_bad_reg (RdLo
);
12335 reject_bad_reg (RdHi
);
12336 reject_bad_reg (Rn
);
12337 reject_bad_reg (Rm
);
12339 inst
.instruction
|= RdLo
<< 12;
12340 inst
.instruction
|= RdHi
<< 8;
12341 inst
.instruction
|= Rn
<< 16;
12342 inst
.instruction
|= Rm
;
12345 as_tsktsk (_("rdhi and rdlo must be different"));
12351 set_it_insn_type (NEUTRAL_IT_INSN
);
12353 if (unified_syntax
)
12355 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12357 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12358 inst
.instruction
|= inst
.operands
[0].imm
;
12362 /* PR9722: Check for Thumb2 availability before
12363 generating a thumb2 nop instruction. */
12364 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12366 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12367 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12370 inst
.instruction
= 0x46c0;
12375 constraint (inst
.operands
[0].present
,
12376 _("Thumb does not support NOP with hints"));
12377 inst
.instruction
= 0x46c0;
12384 if (unified_syntax
)
12386 bfd_boolean narrow
;
12388 if (THUMB_SETS_FLAGS (inst
.instruction
))
12389 narrow
= !in_it_block ();
12391 narrow
= in_it_block ();
12392 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12394 if (inst
.size_req
== 4)
12399 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12400 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12401 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12405 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12406 inst
.instruction
|= inst
.operands
[0].reg
;
12407 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12412 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12414 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12417 inst
.instruction
|= inst
.operands
[0].reg
;
12418 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12427 Rd
= inst
.operands
[0].reg
;
12428 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12430 reject_bad_reg (Rd
);
12431 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12432 reject_bad_reg (Rn
);
12434 inst
.instruction
|= Rd
<< 8;
12435 inst
.instruction
|= Rn
<< 16;
12437 if (!inst
.operands
[2].isreg
)
12439 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12440 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12446 Rm
= inst
.operands
[2].reg
;
12447 reject_bad_reg (Rm
);
12449 constraint (inst
.operands
[2].shifted
12450 && inst
.operands
[2].immisreg
,
12451 _("shift must be constant"));
12452 encode_thumb32_shifted_operand (2);
12459 unsigned Rd
, Rn
, Rm
;
12461 Rd
= inst
.operands
[0].reg
;
12462 Rn
= inst
.operands
[1].reg
;
12463 Rm
= inst
.operands
[2].reg
;
12465 reject_bad_reg (Rd
);
12466 reject_bad_reg (Rn
);
12467 reject_bad_reg (Rm
);
12469 inst
.instruction
|= Rd
<< 8;
12470 inst
.instruction
|= Rn
<< 16;
12471 inst
.instruction
|= Rm
;
12472 if (inst
.operands
[3].present
)
12474 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12475 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12476 _("expression too complex"));
12477 inst
.instruction
|= (val
& 0x1c) << 10;
12478 inst
.instruction
|= (val
& 0x03) << 6;
12485 if (!inst
.operands
[3].present
)
12489 inst
.instruction
&= ~0x00000020;
12491 /* PR 10168. Swap the Rm and Rn registers. */
12492 Rtmp
= inst
.operands
[1].reg
;
12493 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12494 inst
.operands
[2].reg
= Rtmp
;
12502 if (inst
.operands
[0].immisreg
)
12503 reject_bad_reg (inst
.operands
[0].imm
);
12505 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12509 do_t_push_pop (void)
12513 constraint (inst
.operands
[0].writeback
,
12514 _("push/pop do not support {reglist}^"));
12515 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12516 _("expression too complex"));
12518 mask
= inst
.operands
[0].imm
;
12519 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12520 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12521 else if (inst
.size_req
!= 4
12522 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12523 ? REG_LR
: REG_PC
)))
12525 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12526 inst
.instruction
|= THUMB_PP_PC_LR
;
12527 inst
.instruction
|= mask
& 0xff;
12529 else if (unified_syntax
)
12531 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12532 encode_thumb2_ldmstm (13, mask
, TRUE
);
12536 inst
.error
= _("invalid register list to push/pop instruction");
12546 Rd
= inst
.operands
[0].reg
;
12547 Rm
= inst
.operands
[1].reg
;
12549 reject_bad_reg (Rd
);
12550 reject_bad_reg (Rm
);
12552 inst
.instruction
|= Rd
<< 8;
12553 inst
.instruction
|= Rm
<< 16;
12554 inst
.instruction
|= Rm
;
12562 Rd
= inst
.operands
[0].reg
;
12563 Rm
= inst
.operands
[1].reg
;
12565 reject_bad_reg (Rd
);
12566 reject_bad_reg (Rm
);
12568 if (Rd
<= 7 && Rm
<= 7
12569 && inst
.size_req
!= 4)
12571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12572 inst
.instruction
|= Rd
;
12573 inst
.instruction
|= Rm
<< 3;
12575 else if (unified_syntax
)
12577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12578 inst
.instruction
|= Rd
<< 8;
12579 inst
.instruction
|= Rm
<< 16;
12580 inst
.instruction
|= Rm
;
12583 inst
.error
= BAD_HIREG
;
12591 Rd
= inst
.operands
[0].reg
;
12592 Rm
= inst
.operands
[1].reg
;
12594 reject_bad_reg (Rd
);
12595 reject_bad_reg (Rm
);
12597 inst
.instruction
|= Rd
<< 8;
12598 inst
.instruction
|= Rm
;
12606 Rd
= inst
.operands
[0].reg
;
12607 Rs
= (inst
.operands
[1].present
12608 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12609 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12611 reject_bad_reg (Rd
);
12612 reject_bad_reg (Rs
);
12613 if (inst
.operands
[2].isreg
)
12614 reject_bad_reg (inst
.operands
[2].reg
);
12616 inst
.instruction
|= Rd
<< 8;
12617 inst
.instruction
|= Rs
<< 16;
12618 if (!inst
.operands
[2].isreg
)
12620 bfd_boolean narrow
;
12622 if ((inst
.instruction
& 0x00100000) != 0)
12623 narrow
= !in_it_block ();
12625 narrow
= in_it_block ();
12627 if (Rd
> 7 || Rs
> 7)
12630 if (inst
.size_req
== 4 || !unified_syntax
)
12633 if (inst
.reloc
.exp
.X_op
!= O_constant
12634 || inst
.reloc
.exp
.X_add_number
!= 0)
12637 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12638 relaxation, but it doesn't seem worth the hassle. */
12641 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12642 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12643 inst
.instruction
|= Rs
<< 3;
12644 inst
.instruction
|= Rd
;
12648 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12649 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12653 encode_thumb32_shifted_operand (2);
12659 if (warn_on_deprecated
12660 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12661 as_tsktsk (_("setend use is deprecated for ARMv8"));
12663 set_it_insn_type (OUTSIDE_IT_INSN
);
12664 if (inst
.operands
[0].imm
)
12665 inst
.instruction
|= 0x8;
12671 if (!inst
.operands
[1].present
)
12672 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12674 if (unified_syntax
)
12676 bfd_boolean narrow
;
12679 switch (inst
.instruction
)
12682 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12684 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12686 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12688 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12692 if (THUMB_SETS_FLAGS (inst
.instruction
))
12693 narrow
= !in_it_block ();
12695 narrow
= in_it_block ();
12696 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12698 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12700 if (inst
.operands
[2].isreg
12701 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12702 || inst
.operands
[2].reg
> 7))
12704 if (inst
.size_req
== 4)
12707 reject_bad_reg (inst
.operands
[0].reg
);
12708 reject_bad_reg (inst
.operands
[1].reg
);
12712 if (inst
.operands
[2].isreg
)
12714 reject_bad_reg (inst
.operands
[2].reg
);
12715 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12716 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12717 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12718 inst
.instruction
|= inst
.operands
[2].reg
;
12720 /* PR 12854: Error on extraneous shifts. */
12721 constraint (inst
.operands
[2].shifted
,
12722 _("extraneous shift as part of operand to shift insn"));
12726 inst
.operands
[1].shifted
= 1;
12727 inst
.operands
[1].shift_kind
= shift_kind
;
12728 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12729 ? T_MNEM_movs
: T_MNEM_mov
);
12730 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12731 encode_thumb32_shifted_operand (1);
12732 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12733 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12738 if (inst
.operands
[2].isreg
)
12740 switch (shift_kind
)
12742 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12743 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12744 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12745 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12749 inst
.instruction
|= inst
.operands
[0].reg
;
12750 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12752 /* PR 12854: Error on extraneous shifts. */
12753 constraint (inst
.operands
[2].shifted
,
12754 _("extraneous shift as part of operand to shift insn"));
12758 switch (shift_kind
)
12760 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12761 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12762 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12765 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12766 inst
.instruction
|= inst
.operands
[0].reg
;
12767 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12773 constraint (inst
.operands
[0].reg
> 7
12774 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12775 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12777 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12779 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12780 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12781 _("source1 and dest must be same register"));
12783 switch (inst
.instruction
)
12785 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12786 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12787 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12788 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12792 inst
.instruction
|= inst
.operands
[0].reg
;
12793 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12795 /* PR 12854: Error on extraneous shifts. */
12796 constraint (inst
.operands
[2].shifted
,
12797 _("extraneous shift as part of operand to shift insn"));
12801 switch (inst
.instruction
)
12803 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12804 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12805 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12806 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12809 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12810 inst
.instruction
|= inst
.operands
[0].reg
;
12811 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12819 unsigned Rd
, Rn
, Rm
;
12821 Rd
= inst
.operands
[0].reg
;
12822 Rn
= inst
.operands
[1].reg
;
12823 Rm
= inst
.operands
[2].reg
;
12825 reject_bad_reg (Rd
);
12826 reject_bad_reg (Rn
);
12827 reject_bad_reg (Rm
);
12829 inst
.instruction
|= Rd
<< 8;
12830 inst
.instruction
|= Rn
<< 16;
12831 inst
.instruction
|= Rm
;
12837 unsigned Rd
, Rn
, Rm
;
12839 Rd
= inst
.operands
[0].reg
;
12840 Rm
= inst
.operands
[1].reg
;
12841 Rn
= inst
.operands
[2].reg
;
12843 reject_bad_reg (Rd
);
12844 reject_bad_reg (Rn
);
12845 reject_bad_reg (Rm
);
12847 inst
.instruction
|= Rd
<< 8;
12848 inst
.instruction
|= Rn
<< 16;
12849 inst
.instruction
|= Rm
;
12855 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12857 _("SMC is not permitted on this architecture"));
12858 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12859 _("expression too complex"));
12860 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12861 inst
.instruction
|= (value
& 0xf000) >> 12;
12862 inst
.instruction
|= (value
& 0x0ff0);
12863 inst
.instruction
|= (value
& 0x000f) << 16;
12864 /* PR gas/15623: SMC instructions must be last in an IT block. */
12865 set_it_insn_type_last ();
12871 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12873 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12874 inst
.instruction
|= (value
& 0x0fff);
12875 inst
.instruction
|= (value
& 0xf000) << 4;
12879 do_t_ssat_usat (int bias
)
12883 Rd
= inst
.operands
[0].reg
;
12884 Rn
= inst
.operands
[2].reg
;
12886 reject_bad_reg (Rd
);
12887 reject_bad_reg (Rn
);
12889 inst
.instruction
|= Rd
<< 8;
12890 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12891 inst
.instruction
|= Rn
<< 16;
12893 if (inst
.operands
[3].present
)
12895 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12897 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12899 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12900 _("expression too complex"));
12902 if (shift_amount
!= 0)
12904 constraint (shift_amount
> 31,
12905 _("shift expression is too large"));
12907 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12908 inst
.instruction
|= 0x00200000; /* sh bit. */
12910 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12911 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12919 do_t_ssat_usat (1);
12927 Rd
= inst
.operands
[0].reg
;
12928 Rn
= inst
.operands
[2].reg
;
12930 reject_bad_reg (Rd
);
12931 reject_bad_reg (Rn
);
12933 inst
.instruction
|= Rd
<< 8;
12934 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12935 inst
.instruction
|= Rn
<< 16;
12941 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12942 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12943 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12944 || inst
.operands
[2].negative
,
12947 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12949 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12950 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12951 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12952 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12958 if (!inst
.operands
[2].present
)
12959 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12961 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12962 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12963 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12966 inst
.instruction
|= inst
.operands
[0].reg
;
12967 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12968 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12969 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12975 unsigned Rd
, Rn
, Rm
;
12977 Rd
= inst
.operands
[0].reg
;
12978 Rn
= inst
.operands
[1].reg
;
12979 Rm
= inst
.operands
[2].reg
;
12981 reject_bad_reg (Rd
);
12982 reject_bad_reg (Rn
);
12983 reject_bad_reg (Rm
);
12985 inst
.instruction
|= Rd
<< 8;
12986 inst
.instruction
|= Rn
<< 16;
12987 inst
.instruction
|= Rm
;
12988 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12996 Rd
= inst
.operands
[0].reg
;
12997 Rm
= inst
.operands
[1].reg
;
12999 reject_bad_reg (Rd
);
13000 reject_bad_reg (Rm
);
13002 if (inst
.instruction
<= 0xffff
13003 && inst
.size_req
!= 4
13004 && Rd
<= 7 && Rm
<= 7
13005 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13007 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13008 inst
.instruction
|= Rd
;
13009 inst
.instruction
|= Rm
<< 3;
13011 else if (unified_syntax
)
13013 if (inst
.instruction
<= 0xffff)
13014 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13015 inst
.instruction
|= Rd
<< 8;
13016 inst
.instruction
|= Rm
;
13017 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13021 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13022 _("Thumb encoding does not support rotation"));
13023 constraint (1, BAD_HIREG
);
13030 /* We have to do the following check manually as ARM_EXT_OS only applies
13032 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13034 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13035 /* This only applies to the v6m howver, not later architectures. */
13036 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13037 as_bad (_("SVC is not permitted on this architecture"));
13038 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13041 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13050 half
= (inst
.instruction
& 0x10) != 0;
13051 set_it_insn_type_last ();
13052 constraint (inst
.operands
[0].immisreg
,
13053 _("instruction requires register index"));
13055 Rn
= inst
.operands
[0].reg
;
13056 Rm
= inst
.operands
[0].imm
;
13058 constraint (Rn
== REG_SP
, BAD_SP
);
13059 reject_bad_reg (Rm
);
13061 constraint (!half
&& inst
.operands
[0].shifted
,
13062 _("instruction does not allow shifted index"));
13063 inst
.instruction
|= (Rn
<< 16) | Rm
;
13069 if (!inst
.operands
[0].present
)
13070 inst
.operands
[0].imm
= 0;
13072 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13074 constraint (inst
.size_req
== 2,
13075 _("immediate value out of range"));
13076 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13077 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13078 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13083 inst
.instruction
|= inst
.operands
[0].imm
;
13086 set_it_insn_type (NEUTRAL_IT_INSN
);
13093 do_t_ssat_usat (0);
13101 Rd
= inst
.operands
[0].reg
;
13102 Rn
= inst
.operands
[2].reg
;
13104 reject_bad_reg (Rd
);
13105 reject_bad_reg (Rn
);
13107 inst
.instruction
|= Rd
<< 8;
13108 inst
.instruction
|= inst
.operands
[1].imm
;
13109 inst
.instruction
|= Rn
<< 16;
13112 /* Neon instruction encoder helpers. */
13114 /* Encodings for the different types for various Neon opcodes. */
13116 /* An "invalid" code for the following tables. */
13119 struct neon_tab_entry
13122 unsigned float_or_poly
;
13123 unsigned scalar_or_imm
;
13126 /* Map overloaded Neon opcodes to their respective encodings. */
13127 #define NEON_ENC_TAB \
13128 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13129 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13130 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13131 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13132 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13133 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13134 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13135 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13136 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13137 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13138 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13139 /* Register variants of the following two instructions are encoded as
13140 vcge / vcgt with the operands reversed. */ \
13141 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13142 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13143 X(vfma, N_INV, 0x0000c10, N_INV), \
13144 X(vfms, N_INV, 0x0200c10, N_INV), \
13145 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13146 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13147 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13148 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13149 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13150 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13151 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13152 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13153 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13154 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13155 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13156 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13157 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13158 X(vshl, 0x0000400, N_INV, 0x0800510), \
13159 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13160 X(vand, 0x0000110, N_INV, 0x0800030), \
13161 X(vbic, 0x0100110, N_INV, 0x0800030), \
13162 X(veor, 0x1000110, N_INV, N_INV), \
13163 X(vorn, 0x0300110, N_INV, 0x0800010), \
13164 X(vorr, 0x0200110, N_INV, 0x0800010), \
13165 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13166 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13167 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13168 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13169 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13170 X(vst1, 0x0000000, 0x0800000, N_INV), \
13171 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13172 X(vst2, 0x0000100, 0x0800100, N_INV), \
13173 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13174 X(vst3, 0x0000200, 0x0800200, N_INV), \
13175 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13176 X(vst4, 0x0000300, 0x0800300, N_INV), \
13177 X(vmovn, 0x1b20200, N_INV, N_INV), \
13178 X(vtrn, 0x1b20080, N_INV, N_INV), \
13179 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13180 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13181 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13182 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13183 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13184 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13185 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13186 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13187 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13188 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13189 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13190 X(vseleq, 0xe000a00, N_INV, N_INV), \
13191 X(vselvs, 0xe100a00, N_INV, N_INV), \
13192 X(vselge, 0xe200a00, N_INV, N_INV), \
13193 X(vselgt, 0xe300a00, N_INV, N_INV), \
13194 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13195 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13196 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13197 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13198 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13199 X(aes, 0x3b00300, N_INV, N_INV), \
13200 X(sha3op, 0x2000c00, N_INV, N_INV), \
13201 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13202 X(sha2op, 0x3ba0380, N_INV, N_INV)
13206 #define X(OPC,I,F,S) N_MNEM_##OPC
13211 static const struct neon_tab_entry neon_enc_tab
[] =
13213 #define X(OPC,I,F,S) { (I), (F), (S) }
13218 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13219 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13220 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13221 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13222 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13223 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13224 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13225 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13226 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13227 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13228 #define NEON_ENC_SINGLE_(X) \
13229 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13230 #define NEON_ENC_DOUBLE_(X) \
13231 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13232 #define NEON_ENC_FPV8_(X) \
13233 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13235 #define NEON_ENCODE(type, inst) \
13238 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13239 inst.is_neon = 1; \
13243 #define check_neon_suffixes \
13246 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13248 as_bad (_("invalid neon suffix for non neon instruction")); \
13254 /* Define shapes for instruction operands. The following mnemonic characters
13255 are used in this table:
13257 F - VFP S<n> register
13258 D - Neon D<n> register
13259 Q - Neon Q<n> register
13263 L - D<n> register list
13265 This table is used to generate various data:
13266 - enumerations of the form NS_DDR to be used as arguments to
13268 - a table classifying shapes into single, double, quad, mixed.
13269 - a table used to drive neon_select_shape. */
13271 #define NEON_SHAPE_DEF \
13272 X(3, (D, D, D), DOUBLE), \
13273 X(3, (Q, Q, Q), QUAD), \
13274 X(3, (D, D, I), DOUBLE), \
13275 X(3, (Q, Q, I), QUAD), \
13276 X(3, (D, D, S), DOUBLE), \
13277 X(3, (Q, Q, S), QUAD), \
13278 X(2, (D, D), DOUBLE), \
13279 X(2, (Q, Q), QUAD), \
13280 X(2, (D, S), DOUBLE), \
13281 X(2, (Q, S), QUAD), \
13282 X(2, (D, R), DOUBLE), \
13283 X(2, (Q, R), QUAD), \
13284 X(2, (D, I), DOUBLE), \
13285 X(2, (Q, I), QUAD), \
13286 X(3, (D, L, D), DOUBLE), \
13287 X(2, (D, Q), MIXED), \
13288 X(2, (Q, D), MIXED), \
13289 X(3, (D, Q, I), MIXED), \
13290 X(3, (Q, D, I), MIXED), \
13291 X(3, (Q, D, D), MIXED), \
13292 X(3, (D, Q, Q), MIXED), \
13293 X(3, (Q, Q, D), MIXED), \
13294 X(3, (Q, D, S), MIXED), \
13295 X(3, (D, Q, S), MIXED), \
13296 X(4, (D, D, D, I), DOUBLE), \
13297 X(4, (Q, Q, Q, I), QUAD), \
13298 X(2, (F, F), SINGLE), \
13299 X(3, (F, F, F), SINGLE), \
13300 X(2, (F, I), SINGLE), \
13301 X(2, (F, D), MIXED), \
13302 X(2, (D, F), MIXED), \
13303 X(3, (F, F, I), MIXED), \
13304 X(4, (R, R, F, F), SINGLE), \
13305 X(4, (F, F, R, R), SINGLE), \
13306 X(3, (D, R, R), DOUBLE), \
13307 X(3, (R, R, D), DOUBLE), \
13308 X(2, (S, R), SINGLE), \
13309 X(2, (R, S), SINGLE), \
13310 X(2, (F, R), SINGLE), \
13311 X(2, (R, F), SINGLE), \
13312 /* Half float shape supported so far. */\
13313 X (2, (H, D), MIXED), \
13314 X (2, (D, H), MIXED), \
13315 X (2, (H, F), MIXED), \
13316 X (2, (F, H), MIXED), \
13317 X (2, (H, H), HALF), \
13318 X (2, (H, R), HALF), \
13319 X (2, (R, H), HALF), \
13320 X (2, (H, I), HALF), \
13321 X (3, (H, H, H), HALF), \
13322 X (3, (H, F, I), MIXED), \
13323 X (3, (F, H, I), MIXED)
13325 #define S2(A,B) NS_##A##B
13326 #define S3(A,B,C) NS_##A##B##C
13327 #define S4(A,B,C,D) NS_##A##B##C##D
13329 #define X(N, L, C) S##N L
13342 enum neon_shape_class
13351 #define X(N, L, C) SC_##C
13353 static enum neon_shape_class neon_shape_class
[] =
13372 /* Register widths of above. */
13373 static unsigned neon_shape_el_size
[] =
13385 struct neon_shape_info
13388 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13391 #define S2(A,B) { SE_##A, SE_##B }
13392 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13393 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13395 #define X(N, L, C) { N, S##N L }
13397 static struct neon_shape_info neon_shape_tab
[] =
13407 /* Bit masks used in type checking given instructions.
13408 'N_EQK' means the type must be the same as (or based on in some way) the key
13409 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13410 set, various other bits can be set as well in order to modify the meaning of
13411 the type constraint. */
13413 enum neon_type_mask
13437 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13438 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13439 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13440 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13441 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13442 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13443 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13444 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13445 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13446 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13447 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13449 N_MAX_NONSPECIAL
= N_P64
13452 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13454 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13455 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13456 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13457 #define N_S_32 (N_S8 | N_S16 | N_S32)
13458 #define N_F_16_32 (N_F16 | N_F32)
13459 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13460 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13461 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13462 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13464 /* Pass this as the first type argument to neon_check_type to ignore types
13466 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13468 /* Select a "shape" for the current instruction (describing register types or
13469 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13470 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13471 function of operand parsing, so this function doesn't need to be called.
13472 Shapes should be listed in order of decreasing length. */
13474 static enum neon_shape
13475 neon_select_shape (enum neon_shape shape
, ...)
13478 enum neon_shape first_shape
= shape
;
13480 /* Fix missing optional operands. FIXME: we don't know at this point how
13481 many arguments we should have, so this makes the assumption that we have
13482 > 1. This is true of all current Neon opcodes, I think, but may not be
13483 true in the future. */
13484 if (!inst
.operands
[1].present
)
13485 inst
.operands
[1] = inst
.operands
[0];
13487 va_start (ap
, shape
);
13489 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13494 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13496 if (!inst
.operands
[j
].present
)
13502 switch (neon_shape_tab
[shape
].el
[j
])
13504 /* If a .f16, .16, .u16, .s16 type specifier is given over
13505 a VFP single precision register operand, it's essentially
13506 means only half of the register is used.
13508 If the type specifier is given after the mnemonics, the
13509 information is stored in inst.vectype. If the type specifier
13510 is given after register operand, the information is stored
13511 in inst.operands[].vectype.
13513 When there is only one type specifier, and all the register
13514 operands are the same type of hardware register, the type
13515 specifier applies to all register operands.
13517 If no type specifier is given, the shape is inferred from
13518 operand information.
13521 vadd.f16 s0, s1, s2: NS_HHH
13522 vabs.f16 s0, s1: NS_HH
13523 vmov.f16 s0, r1: NS_HR
13524 vmov.f16 r0, s1: NS_RH
13525 vcvt.f16 r0, s1: NS_RH
13526 vcvt.f16.s32 s2, s2, #29: NS_HFI
13527 vcvt.f16.s32 s2, s2: NS_HF
13530 if (!(inst
.operands
[j
].isreg
13531 && inst
.operands
[j
].isvec
13532 && inst
.operands
[j
].issingle
13533 && !inst
.operands
[j
].isquad
13534 && ((inst
.vectype
.elems
== 1
13535 && inst
.vectype
.el
[0].size
== 16)
13536 || (inst
.vectype
.elems
> 1
13537 && inst
.vectype
.el
[j
].size
== 16)
13538 || (inst
.vectype
.elems
== 0
13539 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13540 && inst
.operands
[j
].vectype
.size
== 16))))
13545 if (!(inst
.operands
[j
].isreg
13546 && inst
.operands
[j
].isvec
13547 && inst
.operands
[j
].issingle
13548 && !inst
.operands
[j
].isquad
13549 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13550 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13551 || (inst
.vectype
.elems
== 0
13552 && (inst
.operands
[j
].vectype
.size
== 32
13553 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13558 if (!(inst
.operands
[j
].isreg
13559 && inst
.operands
[j
].isvec
13560 && !inst
.operands
[j
].isquad
13561 && !inst
.operands
[j
].issingle
))
13566 if (!(inst
.operands
[j
].isreg
13567 && !inst
.operands
[j
].isvec
))
13572 if (!(inst
.operands
[j
].isreg
13573 && inst
.operands
[j
].isvec
13574 && inst
.operands
[j
].isquad
13575 && !inst
.operands
[j
].issingle
))
13580 if (!(!inst
.operands
[j
].isreg
13581 && !inst
.operands
[j
].isscalar
))
13586 if (!(!inst
.operands
[j
].isreg
13587 && inst
.operands
[j
].isscalar
))
13597 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13598 /* We've matched all the entries in the shape table, and we don't
13599 have any left over operands which have not been matched. */
13605 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13606 first_error (_("invalid instruction shape"));
13611 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13612 means the Q bit should be set). */
13615 neon_quad (enum neon_shape shape
)
13617 return neon_shape_class
[shape
] == SC_QUAD
;
13621 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13624 /* Allow modification to be made to types which are constrained to be
13625 based on the key element, based on bits set alongside N_EQK. */
13626 if ((typebits
& N_EQK
) != 0)
13628 if ((typebits
& N_HLF
) != 0)
13630 else if ((typebits
& N_DBL
) != 0)
13632 if ((typebits
& N_SGN
) != 0)
13633 *g_type
= NT_signed
;
13634 else if ((typebits
& N_UNS
) != 0)
13635 *g_type
= NT_unsigned
;
13636 else if ((typebits
& N_INT
) != 0)
13637 *g_type
= NT_integer
;
13638 else if ((typebits
& N_FLT
) != 0)
13639 *g_type
= NT_float
;
13640 else if ((typebits
& N_SIZ
) != 0)
13641 *g_type
= NT_untyped
;
13645 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13646 operand type, i.e. the single type specified in a Neon instruction when it
13647 is the only one given. */
13649 static struct neon_type_el
13650 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13652 struct neon_type_el dest
= *key
;
13654 gas_assert ((thisarg
& N_EQK
) != 0);
13656 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13661 /* Convert Neon type and size into compact bitmask representation. */
13663 static enum neon_type_mask
13664 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13671 case 8: return N_8
;
13672 case 16: return N_16
;
13673 case 32: return N_32
;
13674 case 64: return N_64
;
13682 case 8: return N_I8
;
13683 case 16: return N_I16
;
13684 case 32: return N_I32
;
13685 case 64: return N_I64
;
13693 case 16: return N_F16
;
13694 case 32: return N_F32
;
13695 case 64: return N_F64
;
13703 case 8: return N_P8
;
13704 case 16: return N_P16
;
13705 case 64: return N_P64
;
13713 case 8: return N_S8
;
13714 case 16: return N_S16
;
13715 case 32: return N_S32
;
13716 case 64: return N_S64
;
13724 case 8: return N_U8
;
13725 case 16: return N_U16
;
13726 case 32: return N_U32
;
13727 case 64: return N_U64
;
13738 /* Convert compact Neon bitmask type representation to a type and size. Only
13739 handles the case where a single bit is set in the mask. */
13742 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13743 enum neon_type_mask mask
)
13745 if ((mask
& N_EQK
) != 0)
13748 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13750 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13752 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13754 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13759 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13761 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13762 *type
= NT_unsigned
;
13763 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13764 *type
= NT_integer
;
13765 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13766 *type
= NT_untyped
;
13767 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13769 else if ((mask
& (N_F_ALL
)) != 0)
13777 /* Modify a bitmask of allowed types. This is only needed for type
13781 modify_types_allowed (unsigned allowed
, unsigned mods
)
13784 enum neon_el_type type
;
13790 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13792 if (el_type_of_type_chk (&type
, &size
,
13793 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13795 neon_modify_type_size (mods
, &type
, &size
);
13796 destmask
|= type_chk_of_el_type (type
, size
);
13803 /* Check type and return type classification.
13804 The manual states (paraphrase): If one datatype is given, it indicates the
13806 - the second operand, if there is one
13807 - the operand, if there is no second operand
13808 - the result, if there are no operands.
13809 This isn't quite good enough though, so we use a concept of a "key" datatype
13810 which is set on a per-instruction basis, which is the one which matters when
13811 only one data type is written.
13812 Note: this function has side-effects (e.g. filling in missing operands). All
13813 Neon instructions should call it before performing bit encoding. */
13815 static struct neon_type_el
13816 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13819 unsigned i
, pass
, key_el
= 0;
13820 unsigned types
[NEON_MAX_TYPE_ELS
];
13821 enum neon_el_type k_type
= NT_invtype
;
13822 unsigned k_size
= -1u;
13823 struct neon_type_el badtype
= {NT_invtype
, -1};
13824 unsigned key_allowed
= 0;
13826 /* Optional registers in Neon instructions are always (not) in operand 1.
13827 Fill in the missing operand here, if it was omitted. */
13828 if (els
> 1 && !inst
.operands
[1].present
)
13829 inst
.operands
[1] = inst
.operands
[0];
13831 /* Suck up all the varargs. */
13833 for (i
= 0; i
< els
; i
++)
13835 unsigned thisarg
= va_arg (ap
, unsigned);
13836 if (thisarg
== N_IGNORE_TYPE
)
13841 types
[i
] = thisarg
;
13842 if ((thisarg
& N_KEY
) != 0)
13847 if (inst
.vectype
.elems
> 0)
13848 for (i
= 0; i
< els
; i
++)
13849 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13851 first_error (_("types specified in both the mnemonic and operands"));
13855 /* Duplicate inst.vectype elements here as necessary.
13856 FIXME: No idea if this is exactly the same as the ARM assembler,
13857 particularly when an insn takes one register and one non-register
13859 if (inst
.vectype
.elems
== 1 && els
> 1)
13862 inst
.vectype
.elems
= els
;
13863 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13864 for (j
= 0; j
< els
; j
++)
13866 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13869 else if (inst
.vectype
.elems
== 0 && els
> 0)
13872 /* No types were given after the mnemonic, so look for types specified
13873 after each operand. We allow some flexibility here; as long as the
13874 "key" operand has a type, we can infer the others. */
13875 for (j
= 0; j
< els
; j
++)
13876 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13877 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13879 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13881 for (j
= 0; j
< els
; j
++)
13882 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13883 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13888 first_error (_("operand types can't be inferred"));
13892 else if (inst
.vectype
.elems
!= els
)
13894 first_error (_("type specifier has the wrong number of parts"));
13898 for (pass
= 0; pass
< 2; pass
++)
13900 for (i
= 0; i
< els
; i
++)
13902 unsigned thisarg
= types
[i
];
13903 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13904 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13905 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13906 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13908 /* Decay more-specific signed & unsigned types to sign-insensitive
13909 integer types if sign-specific variants are unavailable. */
13910 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13911 && (types_allowed
& N_SU_ALL
) == 0)
13912 g_type
= NT_integer
;
13914 /* If only untyped args are allowed, decay any more specific types to
13915 them. Some instructions only care about signs for some element
13916 sizes, so handle that properly. */
13917 if (((types_allowed
& N_UNT
) == 0)
13918 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13919 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13920 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13921 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13922 g_type
= NT_untyped
;
13926 if ((thisarg
& N_KEY
) != 0)
13930 key_allowed
= thisarg
& ~N_KEY
;
13932 /* Check architecture constraint on FP16 extension. */
13934 && k_type
== NT_float
13935 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13937 inst
.error
= _(BAD_FP16
);
13944 if ((thisarg
& N_VFP
) != 0)
13946 enum neon_shape_el regshape
;
13947 unsigned regwidth
, match
;
13949 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13952 first_error (_("invalid instruction shape"));
13955 regshape
= neon_shape_tab
[ns
].el
[i
];
13956 regwidth
= neon_shape_el_size
[regshape
];
13958 /* In VFP mode, operands must match register widths. If we
13959 have a key operand, use its width, else use the width of
13960 the current operand. */
13966 /* FP16 will use a single precision register. */
13967 if (regwidth
== 32 && match
== 16)
13969 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13973 inst
.error
= _(BAD_FP16
);
13978 if (regwidth
!= match
)
13980 first_error (_("operand size must match register width"));
13985 if ((thisarg
& N_EQK
) == 0)
13987 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13989 if ((given_type
& types_allowed
) == 0)
13991 first_error (_("bad type in Neon instruction"));
13997 enum neon_el_type mod_k_type
= k_type
;
13998 unsigned mod_k_size
= k_size
;
13999 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14000 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14002 first_error (_("inconsistent types in Neon instruction"));
14010 return inst
.vectype
.el
[key_el
];
14013 /* Neon-style VFP instruction forwarding. */
14015 /* Thumb VFP instructions have 0xE in the condition field. */
14018 do_vfp_cond_or_thumb (void)
14023 inst
.instruction
|= 0xe0000000;
14025 inst
.instruction
|= inst
.cond
<< 28;
14028 /* Look up and encode a simple mnemonic, for use as a helper function for the
14029 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14030 etc. It is assumed that operand parsing has already been done, and that the
14031 operands are in the form expected by the given opcode (this isn't necessarily
14032 the same as the form in which they were parsed, hence some massaging must
14033 take place before this function is called).
14034 Checks current arch version against that in the looked-up opcode. */
14037 do_vfp_nsyn_opcode (const char *opname
)
14039 const struct asm_opcode
*opcode
;
14041 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14046 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14047 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14054 inst
.instruction
= opcode
->tvalue
;
14055 opcode
->tencode ();
14059 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14060 opcode
->aencode ();
14065 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14067 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14069 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14072 do_vfp_nsyn_opcode ("fadds");
14074 do_vfp_nsyn_opcode ("fsubs");
14076 /* ARMv8.2 fp16 instruction. */
14078 do_scalar_fp16_v82_encode ();
14083 do_vfp_nsyn_opcode ("faddd");
14085 do_vfp_nsyn_opcode ("fsubd");
14089 /* Check operand types to see if this is a VFP instruction, and if so call
14093 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14095 enum neon_shape rs
;
14096 struct neon_type_el et
;
14101 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14102 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14106 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14107 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14108 N_F_ALL
| N_KEY
| N_VFP
);
14115 if (et
.type
!= NT_invtype
)
14126 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14128 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14130 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14133 do_vfp_nsyn_opcode ("fmacs");
14135 do_vfp_nsyn_opcode ("fnmacs");
14137 /* ARMv8.2 fp16 instruction. */
14139 do_scalar_fp16_v82_encode ();
14144 do_vfp_nsyn_opcode ("fmacd");
14146 do_vfp_nsyn_opcode ("fnmacd");
14151 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14153 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14155 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14158 do_vfp_nsyn_opcode ("ffmas");
14160 do_vfp_nsyn_opcode ("ffnmas");
14162 /* ARMv8.2 fp16 instruction. */
14164 do_scalar_fp16_v82_encode ();
14169 do_vfp_nsyn_opcode ("ffmad");
14171 do_vfp_nsyn_opcode ("ffnmad");
14176 do_vfp_nsyn_mul (enum neon_shape rs
)
14178 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14180 do_vfp_nsyn_opcode ("fmuls");
14182 /* ARMv8.2 fp16 instruction. */
14184 do_scalar_fp16_v82_encode ();
14187 do_vfp_nsyn_opcode ("fmuld");
14191 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14193 int is_neg
= (inst
.instruction
& 0x80) != 0;
14194 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14196 if (rs
== NS_FF
|| rs
== NS_HH
)
14199 do_vfp_nsyn_opcode ("fnegs");
14201 do_vfp_nsyn_opcode ("fabss");
14203 /* ARMv8.2 fp16 instruction. */
14205 do_scalar_fp16_v82_encode ();
14210 do_vfp_nsyn_opcode ("fnegd");
14212 do_vfp_nsyn_opcode ("fabsd");
14216 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14217 insns belong to Neon, and are handled elsewhere. */
14220 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14222 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14226 do_vfp_nsyn_opcode ("fldmdbs");
14228 do_vfp_nsyn_opcode ("fldmias");
14233 do_vfp_nsyn_opcode ("fstmdbs");
14235 do_vfp_nsyn_opcode ("fstmias");
14240 do_vfp_nsyn_sqrt (void)
14242 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14243 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14245 if (rs
== NS_FF
|| rs
== NS_HH
)
14247 do_vfp_nsyn_opcode ("fsqrts");
14249 /* ARMv8.2 fp16 instruction. */
14251 do_scalar_fp16_v82_encode ();
14254 do_vfp_nsyn_opcode ("fsqrtd");
14258 do_vfp_nsyn_div (void)
14260 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14261 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14262 N_F_ALL
| N_KEY
| N_VFP
);
14264 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14266 do_vfp_nsyn_opcode ("fdivs");
14268 /* ARMv8.2 fp16 instruction. */
14270 do_scalar_fp16_v82_encode ();
14273 do_vfp_nsyn_opcode ("fdivd");
14277 do_vfp_nsyn_nmul (void)
14279 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14280 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14281 N_F_ALL
| N_KEY
| N_VFP
);
14283 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14285 NEON_ENCODE (SINGLE
, inst
);
14286 do_vfp_sp_dyadic ();
14288 /* ARMv8.2 fp16 instruction. */
14290 do_scalar_fp16_v82_encode ();
14294 NEON_ENCODE (DOUBLE
, inst
);
14295 do_vfp_dp_rd_rn_rm ();
14297 do_vfp_cond_or_thumb ();
14302 do_vfp_nsyn_cmp (void)
14304 enum neon_shape rs
;
14305 if (inst
.operands
[1].isreg
)
14307 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14308 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14310 if (rs
== NS_FF
|| rs
== NS_HH
)
14312 NEON_ENCODE (SINGLE
, inst
);
14313 do_vfp_sp_monadic ();
14317 NEON_ENCODE (DOUBLE
, inst
);
14318 do_vfp_dp_rd_rm ();
14323 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14324 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14326 switch (inst
.instruction
& 0x0fffffff)
14329 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14332 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14338 if (rs
== NS_FI
|| rs
== NS_HI
)
14340 NEON_ENCODE (SINGLE
, inst
);
14341 do_vfp_sp_compare_z ();
14345 NEON_ENCODE (DOUBLE
, inst
);
14349 do_vfp_cond_or_thumb ();
14351 /* ARMv8.2 fp16 instruction. */
14352 if (rs
== NS_HI
|| rs
== NS_HH
)
14353 do_scalar_fp16_v82_encode ();
14357 nsyn_insert_sp (void)
14359 inst
.operands
[1] = inst
.operands
[0];
14360 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14361 inst
.operands
[0].reg
= REG_SP
;
14362 inst
.operands
[0].isreg
= 1;
14363 inst
.operands
[0].writeback
= 1;
14364 inst
.operands
[0].present
= 1;
14368 do_vfp_nsyn_push (void)
14371 if (inst
.operands
[1].issingle
)
14372 do_vfp_nsyn_opcode ("fstmdbs");
14374 do_vfp_nsyn_opcode ("fstmdbd");
14378 do_vfp_nsyn_pop (void)
14381 if (inst
.operands
[1].issingle
)
14382 do_vfp_nsyn_opcode ("fldmias");
14384 do_vfp_nsyn_opcode ("fldmiad");
14387 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14388 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14391 neon_dp_fixup (struct arm_it
* insn
)
14393 unsigned int i
= insn
->instruction
;
14398 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14409 insn
->instruction
= i
;
14412 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14416 neon_logbits (unsigned x
)
14418 return ffs (x
) - 4;
14421 #define LOW4(R) ((R) & 0xf)
14422 #define HI1(R) (((R) >> 4) & 1)
14424 /* Encode insns with bit pattern:
14426 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14427 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14429 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14430 different meaning for some instruction. */
14433 neon_three_same (int isquad
, int ubit
, int size
)
14435 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14436 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14437 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14438 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14439 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14440 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14441 inst
.instruction
|= (isquad
!= 0) << 6;
14442 inst
.instruction
|= (ubit
!= 0) << 24;
14444 inst
.instruction
|= neon_logbits (size
) << 20;
14446 neon_dp_fixup (&inst
);
14449 /* Encode instructions of the form:
14451 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14452 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14454 Don't write size if SIZE == -1. */
14457 neon_two_same (int qbit
, int ubit
, int size
)
14459 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14460 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14461 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14462 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14463 inst
.instruction
|= (qbit
!= 0) << 6;
14464 inst
.instruction
|= (ubit
!= 0) << 24;
14467 inst
.instruction
|= neon_logbits (size
) << 18;
14469 neon_dp_fixup (&inst
);
14472 /* Neon instruction encoders, in approximate order of appearance. */
14475 do_neon_dyadic_i_su (void)
14477 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14478 struct neon_type_el et
= neon_check_type (3, rs
,
14479 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14480 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14484 do_neon_dyadic_i64_su (void)
14486 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14487 struct neon_type_el et
= neon_check_type (3, rs
,
14488 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14489 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14493 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14496 unsigned size
= et
.size
>> 3;
14497 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14498 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14499 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14500 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14501 inst
.instruction
|= (isquad
!= 0) << 6;
14502 inst
.instruction
|= immbits
<< 16;
14503 inst
.instruction
|= (size
>> 3) << 7;
14504 inst
.instruction
|= (size
& 0x7) << 19;
14506 inst
.instruction
|= (uval
!= 0) << 24;
14508 neon_dp_fixup (&inst
);
14512 do_neon_shl_imm (void)
14514 if (!inst
.operands
[2].isreg
)
14516 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14517 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14518 int imm
= inst
.operands
[2].imm
;
14520 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14521 _("immediate out of range for shift"));
14522 NEON_ENCODE (IMMED
, inst
);
14523 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14527 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14528 struct neon_type_el et
= neon_check_type (3, rs
,
14529 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14532 /* VSHL/VQSHL 3-register variants have syntax such as:
14534 whereas other 3-register operations encoded by neon_three_same have
14537 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14539 tmp
= inst
.operands
[2].reg
;
14540 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14541 inst
.operands
[1].reg
= tmp
;
14542 NEON_ENCODE (INTEGER
, inst
);
14543 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14548 do_neon_qshl_imm (void)
14550 if (!inst
.operands
[2].isreg
)
14552 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14553 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14554 int imm
= inst
.operands
[2].imm
;
14556 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14557 _("immediate out of range for shift"));
14558 NEON_ENCODE (IMMED
, inst
);
14559 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14563 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14564 struct neon_type_el et
= neon_check_type (3, rs
,
14565 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14568 /* See note in do_neon_shl_imm. */
14569 tmp
= inst
.operands
[2].reg
;
14570 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14571 inst
.operands
[1].reg
= tmp
;
14572 NEON_ENCODE (INTEGER
, inst
);
14573 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14578 do_neon_rshl (void)
14580 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14581 struct neon_type_el et
= neon_check_type (3, rs
,
14582 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14585 tmp
= inst
.operands
[2].reg
;
14586 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14587 inst
.operands
[1].reg
= tmp
;
14588 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14592 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14594 /* Handle .I8 pseudo-instructions. */
14597 /* Unfortunately, this will make everything apart from zero out-of-range.
14598 FIXME is this the intended semantics? There doesn't seem much point in
14599 accepting .I8 if so. */
14600 immediate
|= immediate
<< 8;
14606 if (immediate
== (immediate
& 0x000000ff))
14608 *immbits
= immediate
;
14611 else if (immediate
== (immediate
& 0x0000ff00))
14613 *immbits
= immediate
>> 8;
14616 else if (immediate
== (immediate
& 0x00ff0000))
14618 *immbits
= immediate
>> 16;
14621 else if (immediate
== (immediate
& 0xff000000))
14623 *immbits
= immediate
>> 24;
14626 if ((immediate
& 0xffff) != (immediate
>> 16))
14627 goto bad_immediate
;
14628 immediate
&= 0xffff;
14631 if (immediate
== (immediate
& 0x000000ff))
14633 *immbits
= immediate
;
14636 else if (immediate
== (immediate
& 0x0000ff00))
14638 *immbits
= immediate
>> 8;
14643 first_error (_("immediate value out of range"));
14648 do_neon_logic (void)
14650 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14652 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14653 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14654 /* U bit and size field were set as part of the bitmask. */
14655 NEON_ENCODE (INTEGER
, inst
);
14656 neon_three_same (neon_quad (rs
), 0, -1);
14660 const int three_ops_form
= (inst
.operands
[2].present
14661 && !inst
.operands
[2].isreg
);
14662 const int immoperand
= (three_ops_form
? 2 : 1);
14663 enum neon_shape rs
= (three_ops_form
14664 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14665 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14666 struct neon_type_el et
= neon_check_type (2, rs
,
14667 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14668 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14672 if (et
.type
== NT_invtype
)
14675 if (three_ops_form
)
14676 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14677 _("first and second operands shall be the same register"));
14679 NEON_ENCODE (IMMED
, inst
);
14681 immbits
= inst
.operands
[immoperand
].imm
;
14684 /* .i64 is a pseudo-op, so the immediate must be a repeating
14686 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14687 inst
.operands
[immoperand
].reg
: 0))
14689 /* Set immbits to an invalid constant. */
14690 immbits
= 0xdeadbeef;
14697 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14701 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14705 /* Pseudo-instruction for VBIC. */
14706 neon_invert_size (&immbits
, 0, et
.size
);
14707 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14711 /* Pseudo-instruction for VORR. */
14712 neon_invert_size (&immbits
, 0, et
.size
);
14713 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14723 inst
.instruction
|= neon_quad (rs
) << 6;
14724 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14725 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14726 inst
.instruction
|= cmode
<< 8;
14727 neon_write_immbits (immbits
);
14729 neon_dp_fixup (&inst
);
14734 do_neon_bitfield (void)
14736 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14737 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14738 neon_three_same (neon_quad (rs
), 0, -1);
14742 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14745 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14746 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14748 if (et
.type
== NT_float
)
14750 NEON_ENCODE (FLOAT
, inst
);
14751 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14755 NEON_ENCODE (INTEGER
, inst
);
14756 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14761 do_neon_dyadic_if_su (void)
14763 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14767 do_neon_dyadic_if_su_d (void)
14769 /* This version only allow D registers, but that constraint is enforced during
14770 operand parsing so we don't need to do anything extra here. */
14771 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14775 do_neon_dyadic_if_i_d (void)
14777 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14778 affected if we specify unsigned args. */
14779 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14782 enum vfp_or_neon_is_neon_bits
14785 NEON_CHECK_ARCH
= 2,
14786 NEON_CHECK_ARCH8
= 4
14789 /* Call this function if an instruction which may have belonged to the VFP or
14790 Neon instruction sets, but turned out to be a Neon instruction (due to the
14791 operand types involved, etc.). We have to check and/or fix-up a couple of
14794 - Make sure the user hasn't attempted to make a Neon instruction
14796 - Alter the value in the condition code field if necessary.
14797 - Make sure that the arch supports Neon instructions.
14799 Which of these operations take place depends on bits from enum
14800 vfp_or_neon_is_neon_bits.
14802 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14803 current instruction's condition is COND_ALWAYS, the condition field is
14804 changed to inst.uncond_value. This is necessary because instructions shared
14805 between VFP and Neon may be conditional for the VFP variants only, and the
14806 unconditional Neon version must have, e.g., 0xF in the condition field. */
14809 vfp_or_neon_is_neon (unsigned check
)
14811 /* Conditions are always legal in Thumb mode (IT blocks). */
14812 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14814 if (inst
.cond
!= COND_ALWAYS
)
14816 first_error (_(BAD_COND
));
14819 if (inst
.uncond_value
!= -1)
14820 inst
.instruction
|= inst
.uncond_value
<< 28;
14823 if ((check
& NEON_CHECK_ARCH
)
14824 && !mark_feature_used (&fpu_neon_ext_v1
))
14826 first_error (_(BAD_FPU
));
14830 if ((check
& NEON_CHECK_ARCH8
)
14831 && !mark_feature_used (&fpu_neon_ext_armv8
))
14833 first_error (_(BAD_FPU
));
14841 do_neon_addsub_if_i (void)
14843 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14846 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14849 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14850 affected if we specify unsigned args. */
14851 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14854 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14856 V<op> A,B (A is operand 0, B is operand 2)
14861 so handle that case specially. */
14864 neon_exchange_operands (void)
14866 if (inst
.operands
[1].present
)
14868 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14870 /* Swap operands[1] and operands[2]. */
14871 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14872 inst
.operands
[1] = inst
.operands
[2];
14873 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14878 inst
.operands
[1] = inst
.operands
[2];
14879 inst
.operands
[2] = inst
.operands
[0];
14884 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14886 if (inst
.operands
[2].isreg
)
14889 neon_exchange_operands ();
14890 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14894 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14895 struct neon_type_el et
= neon_check_type (2, rs
,
14896 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14898 NEON_ENCODE (IMMED
, inst
);
14899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14900 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14901 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14902 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14903 inst
.instruction
|= neon_quad (rs
) << 6;
14904 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14905 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14907 neon_dp_fixup (&inst
);
14914 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14918 do_neon_cmp_inv (void)
14920 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14926 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14929 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14930 scalars, which are encoded in 5 bits, M : Rm.
14931 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14932 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14936 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14938 unsigned regno
= NEON_SCALAR_REG (scalar
);
14939 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14944 if (regno
> 7 || elno
> 3)
14946 return regno
| (elno
<< 3);
14949 if (regno
> 15 || elno
> 1)
14951 return regno
| (elno
<< 4);
14955 first_error (_("scalar out of range for multiply instruction"));
14961 /* Encode multiply / multiply-accumulate scalar instructions. */
14964 neon_mul_mac (struct neon_type_el et
, int ubit
)
14968 /* Give a more helpful error message if we have an invalid type. */
14969 if (et
.type
== NT_invtype
)
14972 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14973 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14974 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14975 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14976 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14977 inst
.instruction
|= LOW4 (scalar
);
14978 inst
.instruction
|= HI1 (scalar
) << 5;
14979 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14980 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14981 inst
.instruction
|= (ubit
!= 0) << 24;
14983 neon_dp_fixup (&inst
);
14987 do_neon_mac_maybe_scalar (void)
14989 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14992 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14995 if (inst
.operands
[2].isscalar
)
14997 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14998 struct neon_type_el et
= neon_check_type (3, rs
,
14999 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15000 NEON_ENCODE (SCALAR
, inst
);
15001 neon_mul_mac (et
, neon_quad (rs
));
15005 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15006 affected if we specify unsigned args. */
15007 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15012 do_neon_fmac (void)
15014 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15017 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15020 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15026 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15027 struct neon_type_el et
= neon_check_type (3, rs
,
15028 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15029 neon_three_same (neon_quad (rs
), 0, et
.size
);
15032 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15033 same types as the MAC equivalents. The polynomial type for this instruction
15034 is encoded the same as the integer type. */
15039 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15042 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15045 if (inst
.operands
[2].isscalar
)
15046 do_neon_mac_maybe_scalar ();
15048 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15052 do_neon_qdmulh (void)
15054 if (inst
.operands
[2].isscalar
)
15056 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15057 struct neon_type_el et
= neon_check_type (3, rs
,
15058 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15059 NEON_ENCODE (SCALAR
, inst
);
15060 neon_mul_mac (et
, neon_quad (rs
));
15064 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15065 struct neon_type_el et
= neon_check_type (3, rs
,
15066 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15067 NEON_ENCODE (INTEGER
, inst
);
15068 /* The U bit (rounding) comes from bit mask. */
15069 neon_three_same (neon_quad (rs
), 0, et
.size
);
15074 do_neon_qrdmlah (void)
15076 /* Check we're on the correct architecture. */
15077 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15079 _("instruction form not available on this architecture.");
15080 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15082 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15083 record_feature_use (&fpu_neon_ext_v8_1
);
15086 if (inst
.operands
[2].isscalar
)
15088 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15089 struct neon_type_el et
= neon_check_type (3, rs
,
15090 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15091 NEON_ENCODE (SCALAR
, inst
);
15092 neon_mul_mac (et
, neon_quad (rs
));
15096 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15097 struct neon_type_el et
= neon_check_type (3, rs
,
15098 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15099 NEON_ENCODE (INTEGER
, inst
);
15100 /* The U bit (rounding) comes from bit mask. */
15101 neon_three_same (neon_quad (rs
), 0, et
.size
);
15106 do_neon_fcmp_absolute (void)
15108 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15109 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15110 N_F_16_32
| N_KEY
);
15111 /* Size field comes from bit mask. */
15112 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15116 do_neon_fcmp_absolute_inv (void)
15118 neon_exchange_operands ();
15119 do_neon_fcmp_absolute ();
15123 do_neon_step (void)
15125 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15126 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15127 N_F_16_32
| N_KEY
);
15128 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15132 do_neon_abs_neg (void)
15134 enum neon_shape rs
;
15135 struct neon_type_el et
;
15137 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15140 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15143 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15144 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15147 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15149 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15150 inst
.instruction
|= neon_quad (rs
) << 6;
15151 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15152 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15154 neon_dp_fixup (&inst
);
15160 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15161 struct neon_type_el et
= neon_check_type (2, rs
,
15162 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15163 int imm
= inst
.operands
[2].imm
;
15164 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15165 _("immediate out of range for insert"));
15166 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15172 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15173 struct neon_type_el et
= neon_check_type (2, rs
,
15174 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15175 int imm
= inst
.operands
[2].imm
;
15176 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15177 _("immediate out of range for insert"));
15178 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15182 do_neon_qshlu_imm (void)
15184 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15185 struct neon_type_el et
= neon_check_type (2, rs
,
15186 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15187 int imm
= inst
.operands
[2].imm
;
15188 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15189 _("immediate out of range for shift"));
15190 /* Only encodes the 'U present' variant of the instruction.
15191 In this case, signed types have OP (bit 8) set to 0.
15192 Unsigned types have OP set to 1. */
15193 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15194 /* The rest of the bits are the same as other immediate shifts. */
15195 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15199 do_neon_qmovn (void)
15201 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15202 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15203 /* Saturating move where operands can be signed or unsigned, and the
15204 destination has the same signedness. */
15205 NEON_ENCODE (INTEGER
, inst
);
15206 if (et
.type
== NT_unsigned
)
15207 inst
.instruction
|= 0xc0;
15209 inst
.instruction
|= 0x80;
15210 neon_two_same (0, 1, et
.size
/ 2);
15214 do_neon_qmovun (void)
15216 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15217 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15218 /* Saturating move with unsigned results. Operands must be signed. */
15219 NEON_ENCODE (INTEGER
, inst
);
15220 neon_two_same (0, 1, et
.size
/ 2);
15224 do_neon_rshift_sat_narrow (void)
15226 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15227 or unsigned. If operands are unsigned, results must also be unsigned. */
15228 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15229 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15230 int imm
= inst
.operands
[2].imm
;
15231 /* This gets the bounds check, size encoding and immediate bits calculation
15235 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15236 VQMOVN.I<size> <Dd>, <Qm>. */
15239 inst
.operands
[2].present
= 0;
15240 inst
.instruction
= N_MNEM_vqmovn
;
15245 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15246 _("immediate out of range"));
15247 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15251 do_neon_rshift_sat_narrow_u (void)
15253 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15254 or unsigned. If operands are unsigned, results must also be unsigned. */
15255 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15256 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15257 int imm
= inst
.operands
[2].imm
;
15258 /* This gets the bounds check, size encoding and immediate bits calculation
15262 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15263 VQMOVUN.I<size> <Dd>, <Qm>. */
15266 inst
.operands
[2].present
= 0;
15267 inst
.instruction
= N_MNEM_vqmovun
;
15272 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15273 _("immediate out of range"));
15274 /* FIXME: The manual is kind of unclear about what value U should have in
15275 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15277 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15281 do_neon_movn (void)
15283 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15284 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15285 NEON_ENCODE (INTEGER
, inst
);
15286 neon_two_same (0, 1, et
.size
/ 2);
15290 do_neon_rshift_narrow (void)
15292 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15293 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15294 int imm
= inst
.operands
[2].imm
;
15295 /* This gets the bounds check, size encoding and immediate bits calculation
15299 /* If immediate is zero then we are a pseudo-instruction for
15300 VMOVN.I<size> <Dd>, <Qm> */
15303 inst
.operands
[2].present
= 0;
15304 inst
.instruction
= N_MNEM_vmovn
;
15309 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15310 _("immediate out of range for narrowing operation"));
15311 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15315 do_neon_shll (void)
15317 /* FIXME: Type checking when lengthening. */
15318 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15319 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15320 unsigned imm
= inst
.operands
[2].imm
;
15322 if (imm
== et
.size
)
15324 /* Maximum shift variant. */
15325 NEON_ENCODE (INTEGER
, inst
);
15326 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15327 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15328 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15329 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15330 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15332 neon_dp_fixup (&inst
);
15336 /* A more-specific type check for non-max versions. */
15337 et
= neon_check_type (2, NS_QDI
,
15338 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15339 NEON_ENCODE (IMMED
, inst
);
15340 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15344 /* Check the various types for the VCVT instruction, and return which version
15345 the current instruction is. */
15347 #define CVT_FLAVOUR_VAR \
15348 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15349 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15350 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15351 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15352 /* Half-precision conversions. */ \
15353 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15354 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15355 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15356 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15357 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15358 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15359 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15360 Compared with single/double precision variants, only the co-processor \
15361 field is different, so the encoding flow is reused here. */ \
15362 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15363 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15364 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15365 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15366 /* VFP instructions. */ \
15367 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15368 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15369 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15370 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15371 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15372 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15373 /* VFP instructions with bitshift. */ \
15374 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15375 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15376 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15377 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15378 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15379 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15380 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15381 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15383 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15384 neon_cvt_flavour_##C,
15386 /* The different types of conversions we can do. */
15387 enum neon_cvt_flavour
15390 neon_cvt_flavour_invalid
,
15391 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15396 static enum neon_cvt_flavour
15397 get_neon_cvt_flavour (enum neon_shape rs
)
15399 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15400 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15401 if (et.type != NT_invtype) \
15403 inst.error = NULL; \
15404 return (neon_cvt_flavour_##C); \
15407 struct neon_type_el et
;
15408 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15409 || rs
== NS_FF
) ? N_VFP
: 0;
15410 /* The instruction versions which take an immediate take one register
15411 argument, which is extended to the width of the full register. Thus the
15412 "source" and "destination" registers must have the same width. Hack that
15413 here by making the size equal to the key (wider, in this case) operand. */
15414 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15418 return neon_cvt_flavour_invalid
;
15433 /* Neon-syntax VFP conversions. */
15436 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15438 const char *opname
= 0;
15440 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15441 || rs
== NS_FHI
|| rs
== NS_HFI
)
15443 /* Conversions with immediate bitshift. */
15444 const char *enc
[] =
15446 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15452 if (flavour
< (int) ARRAY_SIZE (enc
))
15454 opname
= enc
[flavour
];
15455 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15456 _("operands 0 and 1 must be the same register"));
15457 inst
.operands
[1] = inst
.operands
[2];
15458 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15463 /* Conversions without bitshift. */
15464 const char *enc
[] =
15466 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15472 if (flavour
< (int) ARRAY_SIZE (enc
))
15473 opname
= enc
[flavour
];
15477 do_vfp_nsyn_opcode (opname
);
15479 /* ARMv8.2 fp16 VCVT instruction. */
15480 if (flavour
== neon_cvt_flavour_s32_f16
15481 || flavour
== neon_cvt_flavour_u32_f16
15482 || flavour
== neon_cvt_flavour_f16_u32
15483 || flavour
== neon_cvt_flavour_f16_s32
)
15484 do_scalar_fp16_v82_encode ();
15488 do_vfp_nsyn_cvtz (void)
15490 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15491 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15492 const char *enc
[] =
15494 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15500 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15501 do_vfp_nsyn_opcode (enc
[flavour
]);
15505 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15506 enum neon_cvt_mode mode
)
15511 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15512 D register operands. */
15513 if (flavour
== neon_cvt_flavour_s32_f64
15514 || flavour
== neon_cvt_flavour_u32_f64
)
15515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15518 if (flavour
== neon_cvt_flavour_s32_f16
15519 || flavour
== neon_cvt_flavour_u32_f16
)
15520 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15523 set_it_insn_type (OUTSIDE_IT_INSN
);
15527 case neon_cvt_flavour_s32_f64
:
15531 case neon_cvt_flavour_s32_f32
:
15535 case neon_cvt_flavour_s32_f16
:
15539 case neon_cvt_flavour_u32_f64
:
15543 case neon_cvt_flavour_u32_f32
:
15547 case neon_cvt_flavour_u32_f16
:
15552 first_error (_("invalid instruction shape"));
15558 case neon_cvt_mode_a
: rm
= 0; break;
15559 case neon_cvt_mode_n
: rm
= 1; break;
15560 case neon_cvt_mode_p
: rm
= 2; break;
15561 case neon_cvt_mode_m
: rm
= 3; break;
15562 default: first_error (_("invalid rounding mode")); return;
15565 NEON_ENCODE (FPV8
, inst
);
15566 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15567 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15568 inst
.instruction
|= sz
<< 8;
15570 /* ARMv8.2 fp16 VCVT instruction. */
15571 if (flavour
== neon_cvt_flavour_s32_f16
15572 ||flavour
== neon_cvt_flavour_u32_f16
)
15573 do_scalar_fp16_v82_encode ();
15574 inst
.instruction
|= op
<< 7;
15575 inst
.instruction
|= rm
<< 16;
15576 inst
.instruction
|= 0xf0000000;
15577 inst
.is_neon
= TRUE
;
15581 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15583 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15584 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15585 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15587 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15589 if (flavour
== neon_cvt_flavour_invalid
)
15592 /* PR11109: Handle round-to-zero for VCVT conversions. */
15593 if (mode
== neon_cvt_mode_z
15594 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15595 && (flavour
== neon_cvt_flavour_s16_f16
15596 || flavour
== neon_cvt_flavour_u16_f16
15597 || flavour
== neon_cvt_flavour_s32_f32
15598 || flavour
== neon_cvt_flavour_u32_f32
15599 || flavour
== neon_cvt_flavour_s32_f64
15600 || flavour
== neon_cvt_flavour_u32_f64
)
15601 && (rs
== NS_FD
|| rs
== NS_FF
))
15603 do_vfp_nsyn_cvtz ();
15607 /* ARMv8.2 fp16 VCVT conversions. */
15608 if (mode
== neon_cvt_mode_z
15609 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15610 && (flavour
== neon_cvt_flavour_s32_f16
15611 || flavour
== neon_cvt_flavour_u32_f16
)
15614 do_vfp_nsyn_cvtz ();
15615 do_scalar_fp16_v82_encode ();
15619 /* VFP rather than Neon conversions. */
15620 if (flavour
>= neon_cvt_flavour_first_fp
)
15622 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15623 do_vfp_nsyn_cvt (rs
, flavour
);
15625 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15636 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15637 0x0000100, 0x1000100, 0x0, 0x1000000};
15639 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15642 /* Fixed-point conversion with #0 immediate is encoded as an
15643 integer conversion. */
15644 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15646 NEON_ENCODE (IMMED
, inst
);
15647 if (flavour
!= neon_cvt_flavour_invalid
)
15648 inst
.instruction
|= enctab
[flavour
];
15649 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15650 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15651 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15652 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15653 inst
.instruction
|= neon_quad (rs
) << 6;
15654 inst
.instruction
|= 1 << 21;
15655 if (flavour
< neon_cvt_flavour_s16_f16
)
15657 inst
.instruction
|= 1 << 21;
15658 immbits
= 32 - inst
.operands
[2].imm
;
15659 inst
.instruction
|= immbits
<< 16;
15663 inst
.instruction
|= 3 << 20;
15664 immbits
= 16 - inst
.operands
[2].imm
;
15665 inst
.instruction
|= immbits
<< 16;
15666 inst
.instruction
&= ~(1 << 9);
15669 neon_dp_fixup (&inst
);
15675 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15677 NEON_ENCODE (FLOAT
, inst
);
15678 set_it_insn_type (OUTSIDE_IT_INSN
);
15680 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15683 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15684 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15685 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15686 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15687 inst
.instruction
|= neon_quad (rs
) << 6;
15688 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15689 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15690 inst
.instruction
|= mode
<< 8;
15691 if (flavour
== neon_cvt_flavour_u16_f16
15692 || flavour
== neon_cvt_flavour_s16_f16
)
15693 /* Mask off the original size bits and reencode them. */
15694 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15697 inst
.instruction
|= 0xfc000000;
15699 inst
.instruction
|= 0xf0000000;
15705 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15706 0x100, 0x180, 0x0, 0x080};
15708 NEON_ENCODE (INTEGER
, inst
);
15710 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15713 if (flavour
!= neon_cvt_flavour_invalid
)
15714 inst
.instruction
|= enctab
[flavour
];
15716 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15717 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15719 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15720 inst
.instruction
|= neon_quad (rs
) << 6;
15721 if (flavour
>= neon_cvt_flavour_s16_f16
15722 && flavour
<= neon_cvt_flavour_f16_u16
)
15723 /* Half precision. */
15724 inst
.instruction
|= 1 << 18;
15726 inst
.instruction
|= 2 << 18;
15728 neon_dp_fixup (&inst
);
15733 /* Half-precision conversions for Advanced SIMD -- neon. */
15738 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15740 as_bad (_("operand size must match register width"));
15745 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15747 as_bad (_("operand size must match register width"));
15752 inst
.instruction
= 0x3b60600;
15754 inst
.instruction
= 0x3b60700;
15756 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15757 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15758 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15759 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15760 neon_dp_fixup (&inst
);
15764 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15765 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15766 do_vfp_nsyn_cvt (rs
, flavour
);
15768 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15773 do_neon_cvtr (void)
15775 do_neon_cvt_1 (neon_cvt_mode_x
);
15781 do_neon_cvt_1 (neon_cvt_mode_z
);
15785 do_neon_cvta (void)
15787 do_neon_cvt_1 (neon_cvt_mode_a
);
15791 do_neon_cvtn (void)
15793 do_neon_cvt_1 (neon_cvt_mode_n
);
15797 do_neon_cvtp (void)
15799 do_neon_cvt_1 (neon_cvt_mode_p
);
15803 do_neon_cvtm (void)
15805 do_neon_cvt_1 (neon_cvt_mode_m
);
15809 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15812 mark_feature_used (&fpu_vfp_ext_armv8
);
15814 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15815 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15816 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15817 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15818 inst
.instruction
|= to
? 0x10000 : 0;
15819 inst
.instruction
|= t
? 0x80 : 0;
15820 inst
.instruction
|= is_double
? 0x100 : 0;
15821 do_vfp_cond_or_thumb ();
15825 do_neon_cvttb_1 (bfd_boolean t
)
15827 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15828 NS_DF
, NS_DH
, NS_NULL
);
15832 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15835 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15837 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15840 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15842 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15844 /* The VCVTB and VCVTT instructions with D-register operands
15845 don't work for SP only targets. */
15846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15850 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15852 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15854 /* The VCVTB and VCVTT instructions with D-register operands
15855 don't work for SP only targets. */
15856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15860 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15867 do_neon_cvtb (void)
15869 do_neon_cvttb_1 (FALSE
);
15874 do_neon_cvtt (void)
15876 do_neon_cvttb_1 (TRUE
);
15880 neon_move_immediate (void)
15882 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15883 struct neon_type_el et
= neon_check_type (2, rs
,
15884 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15885 unsigned immlo
, immhi
= 0, immbits
;
15886 int op
, cmode
, float_p
;
15888 constraint (et
.type
== NT_invtype
,
15889 _("operand size must be specified for immediate VMOV"));
15891 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15892 op
= (inst
.instruction
& (1 << 5)) != 0;
15894 immlo
= inst
.operands
[1].imm
;
15895 if (inst
.operands
[1].regisimm
)
15896 immhi
= inst
.operands
[1].reg
;
15898 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15899 _("immediate has bits set outside the operand size"));
15901 float_p
= inst
.operands
[1].immisfloat
;
15903 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15904 et
.size
, et
.type
)) == FAIL
)
15906 /* Invert relevant bits only. */
15907 neon_invert_size (&immlo
, &immhi
, et
.size
);
15908 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15909 with one or the other; those cases are caught by
15910 neon_cmode_for_move_imm. */
15912 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15913 &op
, et
.size
, et
.type
)) == FAIL
)
15915 first_error (_("immediate out of range"));
15920 inst
.instruction
&= ~(1 << 5);
15921 inst
.instruction
|= op
<< 5;
15923 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15924 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15925 inst
.instruction
|= neon_quad (rs
) << 6;
15926 inst
.instruction
|= cmode
<< 8;
15928 neon_write_immbits (immbits
);
15934 if (inst
.operands
[1].isreg
)
15936 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15938 NEON_ENCODE (INTEGER
, inst
);
15939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15941 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15943 inst
.instruction
|= neon_quad (rs
) << 6;
15947 NEON_ENCODE (IMMED
, inst
);
15948 neon_move_immediate ();
15951 neon_dp_fixup (&inst
);
15954 /* Encode instructions of form:
15956 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15957 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15960 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15962 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15963 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15964 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15966 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15967 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15968 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15969 inst
.instruction
|= neon_logbits (size
) << 20;
15971 neon_dp_fixup (&inst
);
15975 do_neon_dyadic_long (void)
15977 /* FIXME: Type checking for lengthening op. */
15978 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15979 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15980 neon_mixed_length (et
, et
.size
);
15984 do_neon_abal (void)
15986 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15987 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15988 neon_mixed_length (et
, et
.size
);
15992 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15994 if (inst
.operands
[2].isscalar
)
15996 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15997 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15998 NEON_ENCODE (SCALAR
, inst
);
15999 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16003 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16004 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16005 NEON_ENCODE (INTEGER
, inst
);
16006 neon_mixed_length (et
, et
.size
);
16011 do_neon_mac_maybe_scalar_long (void)
16013 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16017 do_neon_dyadic_wide (void)
16019 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16020 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16021 neon_mixed_length (et
, et
.size
);
16025 do_neon_dyadic_narrow (void)
16027 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16028 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16029 /* Operand sign is unimportant, and the U bit is part of the opcode,
16030 so force the operand type to integer. */
16031 et
.type
= NT_integer
;
16032 neon_mixed_length (et
, et
.size
/ 2);
16036 do_neon_mul_sat_scalar_long (void)
16038 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16042 do_neon_vmull (void)
16044 if (inst
.operands
[2].isscalar
)
16045 do_neon_mac_maybe_scalar_long ();
16048 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16049 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16051 if (et
.type
== NT_poly
)
16052 NEON_ENCODE (POLY
, inst
);
16054 NEON_ENCODE (INTEGER
, inst
);
16056 /* For polynomial encoding the U bit must be zero, and the size must
16057 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16058 obviously, as 0b10). */
16061 /* Check we're on the correct architecture. */
16062 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16064 _("Instruction form not available on this architecture.");
16069 neon_mixed_length (et
, et
.size
);
16076 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16077 struct neon_type_el et
= neon_check_type (3, rs
,
16078 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16079 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16081 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16082 _("shift out of range"));
16083 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16084 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16085 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16086 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16087 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16088 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16089 inst
.instruction
|= neon_quad (rs
) << 6;
16090 inst
.instruction
|= imm
<< 8;
16092 neon_dp_fixup (&inst
);
16098 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16099 struct neon_type_el et
= neon_check_type (2, rs
,
16100 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16101 unsigned op
= (inst
.instruction
>> 7) & 3;
16102 /* N (width of reversed regions) is encoded as part of the bitmask. We
16103 extract it here to check the elements to be reversed are smaller.
16104 Otherwise we'd get a reserved instruction. */
16105 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16106 gas_assert (elsize
!= 0);
16107 constraint (et
.size
>= elsize
,
16108 _("elements must be smaller than reversal region"));
16109 neon_two_same (neon_quad (rs
), 1, et
.size
);
16115 if (inst
.operands
[1].isscalar
)
16117 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16118 struct neon_type_el et
= neon_check_type (2, rs
,
16119 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16120 unsigned sizebits
= et
.size
>> 3;
16121 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16122 int logsize
= neon_logbits (et
.size
);
16123 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16125 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16128 NEON_ENCODE (SCALAR
, inst
);
16129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16130 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16131 inst
.instruction
|= LOW4 (dm
);
16132 inst
.instruction
|= HI1 (dm
) << 5;
16133 inst
.instruction
|= neon_quad (rs
) << 6;
16134 inst
.instruction
|= x
<< 17;
16135 inst
.instruction
|= sizebits
<< 16;
16137 neon_dp_fixup (&inst
);
16141 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16142 struct neon_type_el et
= neon_check_type (2, rs
,
16143 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16144 /* Duplicate ARM register to lanes of vector. */
16145 NEON_ENCODE (ARMREG
, inst
);
16148 case 8: inst
.instruction
|= 0x400000; break;
16149 case 16: inst
.instruction
|= 0x000020; break;
16150 case 32: inst
.instruction
|= 0x000000; break;
16153 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16155 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16156 inst
.instruction
|= neon_quad (rs
) << 21;
16157 /* The encoding for this instruction is identical for the ARM and Thumb
16158 variants, except for the condition field. */
16159 do_vfp_cond_or_thumb ();
16163 /* VMOV has particularly many variations. It can be one of:
16164 0. VMOV<c><q> <Qd>, <Qm>
16165 1. VMOV<c><q> <Dd>, <Dm>
16166 (Register operations, which are VORR with Rm = Rn.)
16167 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16168 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16170 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16171 (ARM register to scalar.)
16172 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16173 (Two ARM registers to vector.)
16174 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16175 (Scalar to ARM register.)
16176 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16177 (Vector to two ARM registers.)
16178 8. VMOV.F32 <Sd>, <Sm>
16179 9. VMOV.F64 <Dd>, <Dm>
16180 (VFP register moves.)
16181 10. VMOV.F32 <Sd>, #imm
16182 11. VMOV.F64 <Dd>, #imm
16183 (VFP float immediate load.)
16184 12. VMOV <Rd>, <Sm>
16185 (VFP single to ARM reg.)
16186 13. VMOV <Sd>, <Rm>
16187 (ARM reg to VFP single.)
16188 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16189 (Two ARM regs to two VFP singles.)
16190 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16191 (Two VFP singles to two ARM regs.)
16193 These cases can be disambiguated using neon_select_shape, except cases 1/9
16194 and 3/11 which depend on the operand type too.
16196 All the encoded bits are hardcoded by this function.
16198 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16199 Cases 5, 7 may be used with VFPv2 and above.
16201 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16202 can specify a type where it doesn't make sense to, and is ignored). */
16207 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16208 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16209 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16210 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16211 struct neon_type_el et
;
16212 const char *ldconst
= 0;
16216 case NS_DD
: /* case 1/9. */
16217 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16218 /* It is not an error here if no type is given. */
16220 if (et
.type
== NT_float
&& et
.size
== 64)
16222 do_vfp_nsyn_opcode ("fcpyd");
16225 /* fall through. */
16227 case NS_QQ
: /* case 0/1. */
16229 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16231 /* The architecture manual I have doesn't explicitly state which
16232 value the U bit should have for register->register moves, but
16233 the equivalent VORR instruction has U = 0, so do that. */
16234 inst
.instruction
= 0x0200110;
16235 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16236 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16237 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16238 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16241 inst
.instruction
|= neon_quad (rs
) << 6;
16243 neon_dp_fixup (&inst
);
16247 case NS_DI
: /* case 3/11. */
16248 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16250 if (et
.type
== NT_float
&& et
.size
== 64)
16252 /* case 11 (fconstd). */
16253 ldconst
= "fconstd";
16254 goto encode_fconstd
;
16256 /* fall through. */
16258 case NS_QI
: /* case 2/3. */
16259 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16261 inst
.instruction
= 0x0800010;
16262 neon_move_immediate ();
16263 neon_dp_fixup (&inst
);
16266 case NS_SR
: /* case 4. */
16268 unsigned bcdebits
= 0;
16270 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16271 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16273 /* .<size> is optional here, defaulting to .32. */
16274 if (inst
.vectype
.elems
== 0
16275 && inst
.operands
[0].vectype
.type
== NT_invtype
16276 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16278 inst
.vectype
.el
[0].type
= NT_untyped
;
16279 inst
.vectype
.el
[0].size
= 32;
16280 inst
.vectype
.elems
= 1;
16283 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16284 logsize
= neon_logbits (et
.size
);
16286 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16288 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16289 && et
.size
!= 32, _(BAD_FPU
));
16290 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16291 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16295 case 8: bcdebits
= 0x8; break;
16296 case 16: bcdebits
= 0x1; break;
16297 case 32: bcdebits
= 0x0; break;
16301 bcdebits
|= x
<< logsize
;
16303 inst
.instruction
= 0xe000b10;
16304 do_vfp_cond_or_thumb ();
16305 inst
.instruction
|= LOW4 (dn
) << 16;
16306 inst
.instruction
|= HI1 (dn
) << 7;
16307 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16308 inst
.instruction
|= (bcdebits
& 3) << 5;
16309 inst
.instruction
|= (bcdebits
>> 2) << 21;
16313 case NS_DRR
: /* case 5 (fmdrr). */
16314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16317 inst
.instruction
= 0xc400b10;
16318 do_vfp_cond_or_thumb ();
16319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16321 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16322 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16325 case NS_RS
: /* case 6. */
16328 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16329 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16330 unsigned abcdebits
= 0;
16332 /* .<dt> is optional here, defaulting to .32. */
16333 if (inst
.vectype
.elems
== 0
16334 && inst
.operands
[0].vectype
.type
== NT_invtype
16335 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16337 inst
.vectype
.el
[0].type
= NT_untyped
;
16338 inst
.vectype
.el
[0].size
= 32;
16339 inst
.vectype
.elems
= 1;
16342 et
= neon_check_type (2, NS_NULL
,
16343 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16344 logsize
= neon_logbits (et
.size
);
16346 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16348 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16349 && et
.size
!= 32, _(BAD_FPU
));
16350 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16351 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16355 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16356 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16357 case 32: abcdebits
= 0x00; break;
16361 abcdebits
|= x
<< logsize
;
16362 inst
.instruction
= 0xe100b10;
16363 do_vfp_cond_or_thumb ();
16364 inst
.instruction
|= LOW4 (dn
) << 16;
16365 inst
.instruction
|= HI1 (dn
) << 7;
16366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16367 inst
.instruction
|= (abcdebits
& 3) << 5;
16368 inst
.instruction
|= (abcdebits
>> 2) << 21;
16372 case NS_RRD
: /* case 7 (fmrrd). */
16373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16376 inst
.instruction
= 0xc500b10;
16377 do_vfp_cond_or_thumb ();
16378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16379 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16380 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16381 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16384 case NS_FF
: /* case 8 (fcpys). */
16385 do_vfp_nsyn_opcode ("fcpys");
16389 case NS_FI
: /* case 10 (fconsts). */
16390 ldconst
= "fconsts";
16392 if (is_quarter_float (inst
.operands
[1].imm
))
16394 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16395 do_vfp_nsyn_opcode (ldconst
);
16397 /* ARMv8.2 fp16 vmov.f16 instruction. */
16399 do_scalar_fp16_v82_encode ();
16402 first_error (_("immediate out of range"));
16406 case NS_RF
: /* case 12 (fmrs). */
16407 do_vfp_nsyn_opcode ("fmrs");
16408 /* ARMv8.2 fp16 vmov.f16 instruction. */
16410 do_scalar_fp16_v82_encode ();
16414 case NS_FR
: /* case 13 (fmsr). */
16415 do_vfp_nsyn_opcode ("fmsr");
16416 /* ARMv8.2 fp16 vmov.f16 instruction. */
16418 do_scalar_fp16_v82_encode ();
16421 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16422 (one of which is a list), but we have parsed four. Do some fiddling to
16423 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16425 case NS_RRFF
: /* case 14 (fmrrs). */
16426 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16427 _("VFP registers must be adjacent"));
16428 inst
.operands
[2].imm
= 2;
16429 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16430 do_vfp_nsyn_opcode ("fmrrs");
16433 case NS_FFRR
: /* case 15 (fmsrr). */
16434 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16435 _("VFP registers must be adjacent"));
16436 inst
.operands
[1] = inst
.operands
[2];
16437 inst
.operands
[2] = inst
.operands
[3];
16438 inst
.operands
[0].imm
= 2;
16439 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16440 do_vfp_nsyn_opcode ("fmsrr");
16444 /* neon_select_shape has determined that the instruction
16445 shape is wrong and has already set the error message. */
16454 do_neon_rshift_round_imm (void)
16456 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16457 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16458 int imm
= inst
.operands
[2].imm
;
16460 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16463 inst
.operands
[2].present
= 0;
16468 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16469 _("immediate out of range for shift"));
16470 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16475 do_neon_movhf (void)
16477 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16478 constraint (rs
!= NS_HH
, _("invalid suffix"));
16480 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16483 do_vfp_sp_monadic ();
16486 inst
.instruction
|= 0xf0000000;
16490 do_neon_movl (void)
16492 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16493 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16494 unsigned sizebits
= et
.size
>> 3;
16495 inst
.instruction
|= sizebits
<< 19;
16496 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16502 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16503 struct neon_type_el et
= neon_check_type (2, rs
,
16504 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16505 NEON_ENCODE (INTEGER
, inst
);
16506 neon_two_same (neon_quad (rs
), 1, et
.size
);
16510 do_neon_zip_uzp (void)
16512 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16513 struct neon_type_el et
= neon_check_type (2, rs
,
16514 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16515 if (rs
== NS_DD
&& et
.size
== 32)
16517 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16518 inst
.instruction
= N_MNEM_vtrn
;
16522 neon_two_same (neon_quad (rs
), 1, et
.size
);
16526 do_neon_sat_abs_neg (void)
16528 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16529 struct neon_type_el et
= neon_check_type (2, rs
,
16530 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16531 neon_two_same (neon_quad (rs
), 1, et
.size
);
16535 do_neon_pair_long (void)
16537 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16538 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16539 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16540 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16541 neon_two_same (neon_quad (rs
), 1, et
.size
);
16545 do_neon_recip_est (void)
16547 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16548 struct neon_type_el et
= neon_check_type (2, rs
,
16549 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16550 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16551 neon_two_same (neon_quad (rs
), 1, et
.size
);
16557 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16558 struct neon_type_el et
= neon_check_type (2, rs
,
16559 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16560 neon_two_same (neon_quad (rs
), 1, et
.size
);
16566 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16567 struct neon_type_el et
= neon_check_type (2, rs
,
16568 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16569 neon_two_same (neon_quad (rs
), 1, et
.size
);
16575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16576 struct neon_type_el et
= neon_check_type (2, rs
,
16577 N_EQK
| N_INT
, N_8
| N_KEY
);
16578 neon_two_same (neon_quad (rs
), 1, et
.size
);
16584 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16585 neon_two_same (neon_quad (rs
), 1, -1);
16589 do_neon_tbl_tbx (void)
16591 unsigned listlenbits
;
16592 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16594 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16596 first_error (_("bad list length for table lookup"));
16600 listlenbits
= inst
.operands
[1].imm
- 1;
16601 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16602 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16603 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16604 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16605 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16606 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16607 inst
.instruction
|= listlenbits
<< 8;
16609 neon_dp_fixup (&inst
);
16613 do_neon_ldm_stm (void)
16615 /* P, U and L bits are part of bitmask. */
16616 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16617 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16619 if (inst
.operands
[1].issingle
)
16621 do_vfp_nsyn_ldm_stm (is_dbmode
);
16625 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16626 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16628 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16629 _("register list must contain at least 1 and at most 16 "
16632 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16633 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16634 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16635 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16637 inst
.instruction
|= offsetbits
;
16639 do_vfp_cond_or_thumb ();
16643 do_neon_ldr_str (void)
16645 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16647 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16648 And is UNPREDICTABLE in thumb mode. */
16650 && inst
.operands
[1].reg
== REG_PC
16651 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16654 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16655 else if (warn_on_deprecated
)
16656 as_tsktsk (_("Use of PC here is deprecated"));
16659 if (inst
.operands
[0].issingle
)
16662 do_vfp_nsyn_opcode ("flds");
16664 do_vfp_nsyn_opcode ("fsts");
16666 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16667 if (inst
.vectype
.el
[0].size
== 16)
16668 do_scalar_fp16_v82_encode ();
16673 do_vfp_nsyn_opcode ("fldd");
16675 do_vfp_nsyn_opcode ("fstd");
16679 /* "interleave" version also handles non-interleaving register VLD1/VST1
16683 do_neon_ld_st_interleave (void)
16685 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16686 N_8
| N_16
| N_32
| N_64
);
16687 unsigned alignbits
= 0;
16689 /* The bits in this table go:
16690 0: register stride of one (0) or two (1)
16691 1,2: register list length, minus one (1, 2, 3, 4).
16692 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16693 We use -1 for invalid entries. */
16694 const int typetable
[] =
16696 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16697 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16698 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16699 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16703 if (et
.type
== NT_invtype
)
16706 if (inst
.operands
[1].immisalign
)
16707 switch (inst
.operands
[1].imm
>> 8)
16709 case 64: alignbits
= 1; break;
16711 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16712 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16713 goto bad_alignment
;
16717 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16718 goto bad_alignment
;
16723 first_error (_("bad alignment"));
16727 inst
.instruction
|= alignbits
<< 4;
16728 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16730 /* Bits [4:6] of the immediate in a list specifier encode register stride
16731 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16732 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16733 up the right value for "type" in a table based on this value and the given
16734 list style, then stick it back. */
16735 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16736 | (((inst
.instruction
>> 8) & 3) << 3);
16738 typebits
= typetable
[idx
];
16740 constraint (typebits
== -1, _("bad list type for instruction"));
16741 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16742 _("bad element type for instruction"));
16744 inst
.instruction
&= ~0xf00;
16745 inst
.instruction
|= typebits
<< 8;
16748 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16749 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16750 otherwise. The variable arguments are a list of pairs of legal (size, align)
16751 values, terminated with -1. */
16754 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16757 int result
= FAIL
, thissize
, thisalign
;
16759 if (!inst
.operands
[1].immisalign
)
16765 va_start (ap
, do_alignment
);
16769 thissize
= va_arg (ap
, int);
16770 if (thissize
== -1)
16772 thisalign
= va_arg (ap
, int);
16774 if (size
== thissize
&& align
== thisalign
)
16777 while (result
!= SUCCESS
);
16781 if (result
== SUCCESS
)
16784 first_error (_("unsupported alignment for instruction"));
16790 do_neon_ld_st_lane (void)
16792 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16793 int align_good
, do_alignment
= 0;
16794 int logsize
= neon_logbits (et
.size
);
16795 int align
= inst
.operands
[1].imm
>> 8;
16796 int n
= (inst
.instruction
>> 8) & 3;
16797 int max_el
= 64 / et
.size
;
16799 if (et
.type
== NT_invtype
)
16802 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16803 _("bad list length"));
16804 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16805 _("scalar index out of range"));
16806 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16808 _("stride of 2 unavailable when element size is 8"));
16812 case 0: /* VLD1 / VST1. */
16813 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16815 if (align_good
== FAIL
)
16819 unsigned alignbits
= 0;
16822 case 16: alignbits
= 0x1; break;
16823 case 32: alignbits
= 0x3; break;
16826 inst
.instruction
|= alignbits
<< 4;
16830 case 1: /* VLD2 / VST2. */
16831 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16832 16, 32, 32, 64, -1);
16833 if (align_good
== FAIL
)
16836 inst
.instruction
|= 1 << 4;
16839 case 2: /* VLD3 / VST3. */
16840 constraint (inst
.operands
[1].immisalign
,
16841 _("can't use alignment with this instruction"));
16844 case 3: /* VLD4 / VST4. */
16845 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16846 16, 64, 32, 64, 32, 128, -1);
16847 if (align_good
== FAIL
)
16851 unsigned alignbits
= 0;
16854 case 8: alignbits
= 0x1; break;
16855 case 16: alignbits
= 0x1; break;
16856 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16859 inst
.instruction
|= alignbits
<< 4;
16866 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16867 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16868 inst
.instruction
|= 1 << (4 + logsize
);
16870 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16871 inst
.instruction
|= logsize
<< 10;
16874 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16877 do_neon_ld_dup (void)
16879 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16880 int align_good
, do_alignment
= 0;
16882 if (et
.type
== NT_invtype
)
16885 switch ((inst
.instruction
>> 8) & 3)
16887 case 0: /* VLD1. */
16888 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16889 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16890 &do_alignment
, 16, 16, 32, 32, -1);
16891 if (align_good
== FAIL
)
16893 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16896 case 2: inst
.instruction
|= 1 << 5; break;
16897 default: first_error (_("bad list length")); return;
16899 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16902 case 1: /* VLD2. */
16903 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16904 &do_alignment
, 8, 16, 16, 32, 32, 64,
16906 if (align_good
== FAIL
)
16908 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16909 _("bad list length"));
16910 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16911 inst
.instruction
|= 1 << 5;
16912 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16915 case 2: /* VLD3. */
16916 constraint (inst
.operands
[1].immisalign
,
16917 _("can't use alignment with this instruction"));
16918 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16919 _("bad list length"));
16920 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16921 inst
.instruction
|= 1 << 5;
16922 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16925 case 3: /* VLD4. */
16927 int align
= inst
.operands
[1].imm
>> 8;
16928 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16929 16, 64, 32, 64, 32, 128, -1);
16930 if (align_good
== FAIL
)
16932 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16933 _("bad list length"));
16934 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16935 inst
.instruction
|= 1 << 5;
16936 if (et
.size
== 32 && align
== 128)
16937 inst
.instruction
|= 0x3 << 6;
16939 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16946 inst
.instruction
|= do_alignment
<< 4;
16949 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16950 apart from bits [11:4]. */
16953 do_neon_ldx_stx (void)
16955 if (inst
.operands
[1].isreg
)
16956 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16958 switch (NEON_LANE (inst
.operands
[0].imm
))
16960 case NEON_INTERLEAVE_LANES
:
16961 NEON_ENCODE (INTERLV
, inst
);
16962 do_neon_ld_st_interleave ();
16965 case NEON_ALL_LANES
:
16966 NEON_ENCODE (DUP
, inst
);
16967 if (inst
.instruction
== N_INV
)
16969 first_error ("only loads support such operands");
16976 NEON_ENCODE (LANE
, inst
);
16977 do_neon_ld_st_lane ();
16980 /* L bit comes from bit mask. */
16981 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16982 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16983 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16985 if (inst
.operands
[1].postind
)
16987 int postreg
= inst
.operands
[1].imm
& 0xf;
16988 constraint (!inst
.operands
[1].immisreg
,
16989 _("post-index must be a register"));
16990 constraint (postreg
== 0xd || postreg
== 0xf,
16991 _("bad register for post-index"));
16992 inst
.instruction
|= postreg
;
16996 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16997 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16998 || inst
.reloc
.exp
.X_add_number
!= 0,
17001 if (inst
.operands
[1].writeback
)
17003 inst
.instruction
|= 0xd;
17006 inst
.instruction
|= 0xf;
17010 inst
.instruction
|= 0xf9000000;
17012 inst
.instruction
|= 0xf4000000;
17017 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17019 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17020 D register operands. */
17021 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17025 NEON_ENCODE (FPV8
, inst
);
17027 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17029 do_vfp_sp_dyadic ();
17031 /* ARMv8.2 fp16 instruction. */
17033 do_scalar_fp16_v82_encode ();
17036 do_vfp_dp_rd_rn_rm ();
17039 inst
.instruction
|= 0x100;
17041 inst
.instruction
|= 0xf0000000;
17047 set_it_insn_type (OUTSIDE_IT_INSN
);
17049 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17050 first_error (_("invalid instruction shape"));
17056 set_it_insn_type (OUTSIDE_IT_INSN
);
17058 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17061 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17064 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17068 do_vrint_1 (enum neon_cvt_mode mode
)
17070 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17071 struct neon_type_el et
;
17076 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17077 D register operands. */
17078 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17079 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17082 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17084 if (et
.type
!= NT_invtype
)
17086 /* VFP encodings. */
17087 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17088 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17089 set_it_insn_type (OUTSIDE_IT_INSN
);
17091 NEON_ENCODE (FPV8
, inst
);
17092 if (rs
== NS_FF
|| rs
== NS_HH
)
17093 do_vfp_sp_monadic ();
17095 do_vfp_dp_rd_rm ();
17099 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17100 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17101 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17102 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17103 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17104 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17105 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17109 inst
.instruction
|= (rs
== NS_DD
) << 8;
17110 do_vfp_cond_or_thumb ();
17112 /* ARMv8.2 fp16 vrint instruction. */
17114 do_scalar_fp16_v82_encode ();
17118 /* Neon encodings (or something broken...). */
17120 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17122 if (et
.type
== NT_invtype
)
17125 set_it_insn_type (OUTSIDE_IT_INSN
);
17126 NEON_ENCODE (FLOAT
, inst
);
17128 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17134 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17135 inst
.instruction
|= neon_quad (rs
) << 6;
17136 /* Mask off the original size bits and reencode them. */
17137 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17138 | neon_logbits (et
.size
) << 18);
17142 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17143 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17144 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17145 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17146 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17147 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17148 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17153 inst
.instruction
|= 0xfc000000;
17155 inst
.instruction
|= 0xf0000000;
17162 do_vrint_1 (neon_cvt_mode_x
);
17168 do_vrint_1 (neon_cvt_mode_z
);
17174 do_vrint_1 (neon_cvt_mode_r
);
17180 do_vrint_1 (neon_cvt_mode_a
);
17186 do_vrint_1 (neon_cvt_mode_n
);
17192 do_vrint_1 (neon_cvt_mode_p
);
17198 do_vrint_1 (neon_cvt_mode_m
);
17201 /* Crypto v1 instructions. */
17203 do_crypto_2op_1 (unsigned elttype
, int op
)
17205 set_it_insn_type (OUTSIDE_IT_INSN
);
17207 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17213 NEON_ENCODE (INTEGER
, inst
);
17214 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17215 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17216 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17217 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17219 inst
.instruction
|= op
<< 6;
17222 inst
.instruction
|= 0xfc000000;
17224 inst
.instruction
|= 0xf0000000;
17228 do_crypto_3op_1 (int u
, int op
)
17230 set_it_insn_type (OUTSIDE_IT_INSN
);
17232 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17233 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17238 NEON_ENCODE (INTEGER
, inst
);
17239 neon_three_same (1, u
, 8 << op
);
17245 do_crypto_2op_1 (N_8
, 0);
17251 do_crypto_2op_1 (N_8
, 1);
17257 do_crypto_2op_1 (N_8
, 2);
17263 do_crypto_2op_1 (N_8
, 3);
17269 do_crypto_3op_1 (0, 0);
17275 do_crypto_3op_1 (0, 1);
17281 do_crypto_3op_1 (0, 2);
17287 do_crypto_3op_1 (0, 3);
17293 do_crypto_3op_1 (1, 0);
17299 do_crypto_3op_1 (1, 1);
17303 do_sha256su1 (void)
17305 do_crypto_3op_1 (1, 2);
17311 do_crypto_2op_1 (N_32
, -1);
17317 do_crypto_2op_1 (N_32
, 0);
17321 do_sha256su0 (void)
17323 do_crypto_2op_1 (N_32
, 1);
17327 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17329 unsigned int Rd
= inst
.operands
[0].reg
;
17330 unsigned int Rn
= inst
.operands
[1].reg
;
17331 unsigned int Rm
= inst
.operands
[2].reg
;
17333 set_it_insn_type (OUTSIDE_IT_INSN
);
17334 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17335 inst
.instruction
|= LOW4 (Rn
) << 16;
17336 inst
.instruction
|= LOW4 (Rm
);
17337 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17338 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17340 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17341 as_warn (UNPRED_REG ("r15"));
17342 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17343 as_warn (UNPRED_REG ("r13"));
17383 /* Overall per-instruction processing. */
17385 /* We need to be able to fix up arbitrary expressions in some statements.
17386 This is so that we can handle symbols that are an arbitrary distance from
17387 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17388 which returns part of an address in a form which will be valid for
17389 a data instruction. We do this by pushing the expression into a symbol
17390 in the expr_section, and creating a fix for that. */
17393 fix_new_arm (fragS
* frag
,
17407 /* Create an absolute valued symbol, so we have something to
17408 refer to in the object file. Unfortunately for us, gas's
17409 generic expression parsing will already have folded out
17410 any use of .set foo/.type foo %function that may have
17411 been used to set type information of the target location,
17412 that's being specified symbolically. We have to presume
17413 the user knows what they are doing. */
17417 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17419 symbol
= symbol_find_or_make (name
);
17420 S_SET_SEGMENT (symbol
, absolute_section
);
17421 symbol_set_frag (symbol
, &zero_address_frag
);
17422 S_SET_VALUE (symbol
, exp
->X_add_number
);
17423 exp
->X_op
= O_symbol
;
17424 exp
->X_add_symbol
= symbol
;
17425 exp
->X_add_number
= 0;
17431 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17432 (enum bfd_reloc_code_real
) reloc
);
17436 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17437 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17441 /* Mark whether the fix is to a THUMB instruction, or an ARM
17443 new_fix
->tc_fix_data
= thumb_mode
;
17446 /* Create a frg for an instruction requiring relaxation. */
17448 output_relax_insn (void)
17454 /* The size of the instruction is unknown, so tie the debug info to the
17455 start of the instruction. */
17456 dwarf2_emit_insn (0);
17458 switch (inst
.reloc
.exp
.X_op
)
17461 sym
= inst
.reloc
.exp
.X_add_symbol
;
17462 offset
= inst
.reloc
.exp
.X_add_number
;
17466 offset
= inst
.reloc
.exp
.X_add_number
;
17469 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17473 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17474 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17475 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17478 /* Write a 32-bit thumb instruction to buf. */
17480 put_thumb32_insn (char * buf
, unsigned long insn
)
17482 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17483 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17487 output_inst (const char * str
)
17493 as_bad ("%s -- `%s'", inst
.error
, str
);
17498 output_relax_insn ();
17501 if (inst
.size
== 0)
17504 to
= frag_more (inst
.size
);
17505 /* PR 9814: Record the thumb mode into the current frag so that we know
17506 what type of NOP padding to use, if necessary. We override any previous
17507 setting so that if the mode has changed then the NOPS that we use will
17508 match the encoding of the last instruction in the frag. */
17509 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17511 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17513 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17514 put_thumb32_insn (to
, inst
.instruction
);
17516 else if (inst
.size
> INSN_SIZE
)
17518 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17519 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17520 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17523 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17525 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17526 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17527 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17530 dwarf2_emit_insn (inst
.size
);
17534 output_it_inst (int cond
, int mask
, char * to
)
17536 unsigned long instruction
= 0xbf00;
17539 instruction
|= mask
;
17540 instruction
|= cond
<< 4;
17544 to
= frag_more (2);
17546 dwarf2_emit_insn (2);
17550 md_number_to_chars (to
, instruction
, 2);
17555 /* Tag values used in struct asm_opcode's tag field. */
17558 OT_unconditional
, /* Instruction cannot be conditionalized.
17559 The ARM condition field is still 0xE. */
17560 OT_unconditionalF
, /* Instruction cannot be conditionalized
17561 and carries 0xF in its ARM condition field. */
17562 OT_csuffix
, /* Instruction takes a conditional suffix. */
17563 OT_csuffixF
, /* Some forms of the instruction take a conditional
17564 suffix, others place 0xF where the condition field
17566 OT_cinfix3
, /* Instruction takes a conditional infix,
17567 beginning at character index 3. (In
17568 unified mode, it becomes a suffix.) */
17569 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17570 tsts, cmps, cmns, and teqs. */
17571 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17572 character index 3, even in unified mode. Used for
17573 legacy instructions where suffix and infix forms
17574 may be ambiguous. */
17575 OT_csuf_or_in3
, /* Instruction takes either a conditional
17576 suffix or an infix at character index 3. */
17577 OT_odd_infix_unc
, /* This is the unconditional variant of an
17578 instruction that takes a conditional infix
17579 at an unusual position. In unified mode,
17580 this variant will accept a suffix. */
17581 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17582 are the conditional variants of instructions that
17583 take conditional infixes in unusual positions.
17584 The infix appears at character index
17585 (tag - OT_odd_infix_0). These are not accepted
17586 in unified mode. */
17589 /* Subroutine of md_assemble, responsible for looking up the primary
17590 opcode from the mnemonic the user wrote. STR points to the
17591 beginning of the mnemonic.
17593 This is not simply a hash table lookup, because of conditional
17594 variants. Most instructions have conditional variants, which are
17595 expressed with a _conditional affix_ to the mnemonic. If we were
17596 to encode each conditional variant as a literal string in the opcode
17597 table, it would have approximately 20,000 entries.
17599 Most mnemonics take this affix as a suffix, and in unified syntax,
17600 'most' is upgraded to 'all'. However, in the divided syntax, some
17601 instructions take the affix as an infix, notably the s-variants of
17602 the arithmetic instructions. Of those instructions, all but six
17603 have the infix appear after the third character of the mnemonic.
17605 Accordingly, the algorithm for looking up primary opcodes given
17608 1. Look up the identifier in the opcode table.
17609 If we find a match, go to step U.
17611 2. Look up the last two characters of the identifier in the
17612 conditions table. If we find a match, look up the first N-2
17613 characters of the identifier in the opcode table. If we
17614 find a match, go to step CE.
17616 3. Look up the fourth and fifth characters of the identifier in
17617 the conditions table. If we find a match, extract those
17618 characters from the identifier, and look up the remaining
17619 characters in the opcode table. If we find a match, go
17624 U. Examine the tag field of the opcode structure, in case this is
17625 one of the six instructions with its conditional infix in an
17626 unusual place. If it is, the tag tells us where to find the
17627 infix; look it up in the conditions table and set inst.cond
17628 accordingly. Otherwise, this is an unconditional instruction.
17629 Again set inst.cond accordingly. Return the opcode structure.
17631 CE. Examine the tag field to make sure this is an instruction that
17632 should receive a conditional suffix. If it is not, fail.
17633 Otherwise, set inst.cond from the suffix we already looked up,
17634 and return the opcode structure.
17636 CM. Examine the tag field to make sure this is an instruction that
17637 should receive a conditional infix after the third character.
17638 If it is not, fail. Otherwise, undo the edits to the current
17639 line of input and proceed as for case CE. */
17641 static const struct asm_opcode
*
17642 opcode_lookup (char **str
)
17646 const struct asm_opcode
*opcode
;
17647 const struct asm_cond
*cond
;
17650 /* Scan up to the end of the mnemonic, which must end in white space,
17651 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17652 for (base
= end
= *str
; *end
!= '\0'; end
++)
17653 if (*end
== ' ' || *end
== '.')
17659 /* Handle a possible width suffix and/or Neon type suffix. */
17664 /* The .w and .n suffixes are only valid if the unified syntax is in
17666 if (unified_syntax
&& end
[1] == 'w')
17668 else if (unified_syntax
&& end
[1] == 'n')
17673 inst
.vectype
.elems
= 0;
17675 *str
= end
+ offset
;
17677 if (end
[offset
] == '.')
17679 /* See if we have a Neon type suffix (possible in either unified or
17680 non-unified ARM syntax mode). */
17681 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17684 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17690 /* Look for unaffixed or special-case affixed mnemonic. */
17691 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17696 if (opcode
->tag
< OT_odd_infix_0
)
17698 inst
.cond
= COND_ALWAYS
;
17702 if (warn_on_deprecated
&& unified_syntax
)
17703 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17704 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17705 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17708 inst
.cond
= cond
->value
;
17712 /* Cannot have a conditional suffix on a mnemonic of less than two
17714 if (end
- base
< 3)
17717 /* Look for suffixed mnemonic. */
17719 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17720 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17722 if (opcode
&& cond
)
17725 switch (opcode
->tag
)
17727 case OT_cinfix3_legacy
:
17728 /* Ignore conditional suffixes matched on infix only mnemonics. */
17732 case OT_cinfix3_deprecated
:
17733 case OT_odd_infix_unc
:
17734 if (!unified_syntax
)
17736 /* else fall through */
17740 case OT_csuf_or_in3
:
17741 inst
.cond
= cond
->value
;
17744 case OT_unconditional
:
17745 case OT_unconditionalF
:
17747 inst
.cond
= cond
->value
;
17750 /* Delayed diagnostic. */
17751 inst
.error
= BAD_COND
;
17752 inst
.cond
= COND_ALWAYS
;
17761 /* Cannot have a usual-position infix on a mnemonic of less than
17762 six characters (five would be a suffix). */
17763 if (end
- base
< 6)
17766 /* Look for infixed mnemonic in the usual position. */
17768 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17772 memcpy (save
, affix
, 2);
17773 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17774 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17776 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17777 memcpy (affix
, save
, 2);
17780 && (opcode
->tag
== OT_cinfix3
17781 || opcode
->tag
== OT_cinfix3_deprecated
17782 || opcode
->tag
== OT_csuf_or_in3
17783 || opcode
->tag
== OT_cinfix3_legacy
))
17786 if (warn_on_deprecated
&& unified_syntax
17787 && (opcode
->tag
== OT_cinfix3
17788 || opcode
->tag
== OT_cinfix3_deprecated
))
17789 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17791 inst
.cond
= cond
->value
;
17798 /* This function generates an initial IT instruction, leaving its block
17799 virtually open for the new instructions. Eventually,
17800 the mask will be updated by now_it_add_mask () each time
17801 a new instruction needs to be included in the IT block.
17802 Finally, the block is closed with close_automatic_it_block ().
17803 The block closure can be requested either from md_assemble (),
17804 a tencode (), or due to a label hook. */
17807 new_automatic_it_block (int cond
)
17809 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17810 now_it
.mask
= 0x18;
17812 now_it
.block_length
= 1;
17813 mapping_state (MAP_THUMB
);
17814 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17815 now_it
.warn_deprecated
= FALSE
;
17816 now_it
.insn_cond
= TRUE
;
17819 /* Close an automatic IT block.
17820 See comments in new_automatic_it_block (). */
17823 close_automatic_it_block (void)
17825 now_it
.mask
= 0x10;
17826 now_it
.block_length
= 0;
17829 /* Update the mask of the current automatically-generated IT
17830 instruction. See comments in new_automatic_it_block (). */
17833 now_it_add_mask (int cond
)
17835 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17836 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17837 | ((bitvalue) << (nbit)))
17838 const int resulting_bit
= (cond
& 1);
17840 now_it
.mask
&= 0xf;
17841 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17843 (5 - now_it
.block_length
));
17844 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17846 ((5 - now_it
.block_length
) - 1) );
17847 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17850 #undef SET_BIT_VALUE
17853 /* The IT blocks handling machinery is accessed through the these functions:
17854 it_fsm_pre_encode () from md_assemble ()
17855 set_it_insn_type () optional, from the tencode functions
17856 set_it_insn_type_last () ditto
17857 in_it_block () ditto
17858 it_fsm_post_encode () from md_assemble ()
17859 force_automatic_it_block_close () from label habdling functions
17862 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17863 initializing the IT insn type with a generic initial value depending
17864 on the inst.condition.
17865 2) During the tencode function, two things may happen:
17866 a) The tencode function overrides the IT insn type by
17867 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17868 b) The tencode function queries the IT block state by
17869 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17871 Both set_it_insn_type and in_it_block run the internal FSM state
17872 handling function (handle_it_state), because: a) setting the IT insn
17873 type may incur in an invalid state (exiting the function),
17874 and b) querying the state requires the FSM to be updated.
17875 Specifically we want to avoid creating an IT block for conditional
17876 branches, so it_fsm_pre_encode is actually a guess and we can't
17877 determine whether an IT block is required until the tencode () routine
17878 has decided what type of instruction this actually it.
17879 Because of this, if set_it_insn_type and in_it_block have to be used,
17880 set_it_insn_type has to be called first.
17882 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17883 determines the insn IT type depending on the inst.cond code.
17884 When a tencode () routine encodes an instruction that can be
17885 either outside an IT block, or, in the case of being inside, has to be
17886 the last one, set_it_insn_type_last () will determine the proper
17887 IT instruction type based on the inst.cond code. Otherwise,
17888 set_it_insn_type can be called for overriding that logic or
17889 for covering other cases.
17891 Calling handle_it_state () may not transition the IT block state to
17892 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17893 still queried. Instead, if the FSM determines that the state should
17894 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17895 after the tencode () function: that's what it_fsm_post_encode () does.
17897 Since in_it_block () calls the state handling function to get an
17898 updated state, an error may occur (due to invalid insns combination).
17899 In that case, inst.error is set.
17900 Therefore, inst.error has to be checked after the execution of
17901 the tencode () routine.
17903 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17904 any pending state change (if any) that didn't take place in
17905 handle_it_state () as explained above. */
17908 it_fsm_pre_encode (void)
17910 if (inst
.cond
!= COND_ALWAYS
)
17911 inst
.it_insn_type
= INSIDE_IT_INSN
;
17913 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17915 now_it
.state_handled
= 0;
17918 /* IT state FSM handling function. */
17921 handle_it_state (void)
17923 now_it
.state_handled
= 1;
17924 now_it
.insn_cond
= FALSE
;
17926 switch (now_it
.state
)
17928 case OUTSIDE_IT_BLOCK
:
17929 switch (inst
.it_insn_type
)
17931 case OUTSIDE_IT_INSN
:
17934 case INSIDE_IT_INSN
:
17935 case INSIDE_IT_LAST_INSN
:
17936 if (thumb_mode
== 0)
17939 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17940 as_tsktsk (_("Warning: conditional outside an IT block"\
17945 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17946 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17948 /* Automatically generate the IT instruction. */
17949 new_automatic_it_block (inst
.cond
);
17950 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17951 close_automatic_it_block ();
17955 inst
.error
= BAD_OUT_IT
;
17961 case IF_INSIDE_IT_LAST_INSN
:
17962 case NEUTRAL_IT_INSN
:
17966 now_it
.state
= MANUAL_IT_BLOCK
;
17967 now_it
.block_length
= 0;
17972 case AUTOMATIC_IT_BLOCK
:
17973 /* Three things may happen now:
17974 a) We should increment current it block size;
17975 b) We should close current it block (closing insn or 4 insns);
17976 c) We should close current it block and start a new one (due
17977 to incompatible conditions or
17978 4 insns-length block reached). */
17980 switch (inst
.it_insn_type
)
17982 case OUTSIDE_IT_INSN
:
17983 /* The closure of the block shall happen immediatelly,
17984 so any in_it_block () call reports the block as closed. */
17985 force_automatic_it_block_close ();
17988 case INSIDE_IT_INSN
:
17989 case INSIDE_IT_LAST_INSN
:
17990 case IF_INSIDE_IT_LAST_INSN
:
17991 now_it
.block_length
++;
17993 if (now_it
.block_length
> 4
17994 || !now_it_compatible (inst
.cond
))
17996 force_automatic_it_block_close ();
17997 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17998 new_automatic_it_block (inst
.cond
);
18002 now_it
.insn_cond
= TRUE
;
18003 now_it_add_mask (inst
.cond
);
18006 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18007 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18008 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18009 close_automatic_it_block ();
18012 case NEUTRAL_IT_INSN
:
18013 now_it
.block_length
++;
18014 now_it
.insn_cond
= TRUE
;
18016 if (now_it
.block_length
> 4)
18017 force_automatic_it_block_close ();
18019 now_it_add_mask (now_it
.cc
& 1);
18023 close_automatic_it_block ();
18024 now_it
.state
= MANUAL_IT_BLOCK
;
18029 case MANUAL_IT_BLOCK
:
18031 /* Check conditional suffixes. */
18032 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18035 now_it
.mask
&= 0x1f;
18036 is_last
= (now_it
.mask
== 0x10);
18037 now_it
.insn_cond
= TRUE
;
18039 switch (inst
.it_insn_type
)
18041 case OUTSIDE_IT_INSN
:
18042 inst
.error
= BAD_NOT_IT
;
18045 case INSIDE_IT_INSN
:
18046 if (cond
!= inst
.cond
)
18048 inst
.error
= BAD_IT_COND
;
18053 case INSIDE_IT_LAST_INSN
:
18054 case IF_INSIDE_IT_LAST_INSN
:
18055 if (cond
!= inst
.cond
)
18057 inst
.error
= BAD_IT_COND
;
18062 inst
.error
= BAD_BRANCH
;
18067 case NEUTRAL_IT_INSN
:
18068 /* The BKPT instruction is unconditional even in an IT block. */
18072 inst
.error
= BAD_IT_IT
;
18082 struct depr_insn_mask
18084 unsigned long pattern
;
18085 unsigned long mask
;
18086 const char* description
;
18089 /* List of 16-bit instruction patterns deprecated in an IT block in
18091 static const struct depr_insn_mask depr_it_insns
[] = {
18092 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18093 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18094 { 0xa000, 0xb800, N_("ADR") },
18095 { 0x4800, 0xf800, N_("Literal loads") },
18096 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18097 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18098 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18099 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18100 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18105 it_fsm_post_encode (void)
18109 if (!now_it
.state_handled
)
18110 handle_it_state ();
18112 if (now_it
.insn_cond
18113 && !now_it
.warn_deprecated
18114 && warn_on_deprecated
18115 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18117 if (inst
.instruction
>= 0x10000)
18119 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18120 "deprecated in ARMv8"));
18121 now_it
.warn_deprecated
= TRUE
;
18125 const struct depr_insn_mask
*p
= depr_it_insns
;
18127 while (p
->mask
!= 0)
18129 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18131 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18132 "of the following class are deprecated in ARMv8: "
18133 "%s"), p
->description
);
18134 now_it
.warn_deprecated
= TRUE
;
18142 if (now_it
.block_length
> 1)
18144 as_tsktsk (_("IT blocks containing more than one conditional "
18145 "instruction are deprecated in ARMv8"));
18146 now_it
.warn_deprecated
= TRUE
;
18150 is_last
= (now_it
.mask
== 0x10);
18153 now_it
.state
= OUTSIDE_IT_BLOCK
;
18159 force_automatic_it_block_close (void)
18161 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18163 close_automatic_it_block ();
18164 now_it
.state
= OUTSIDE_IT_BLOCK
;
18172 if (!now_it
.state_handled
)
18173 handle_it_state ();
18175 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18178 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18179 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18180 here, hence the "known" in the function name. */
18183 known_t32_only_insn (const struct asm_opcode
*opcode
)
18185 /* Original Thumb-1 wide instruction. */
18186 if (opcode
->tencode
== do_t_blx
18187 || opcode
->tencode
== do_t_branch23
18188 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18189 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18192 /* Wide-only instruction added to ARMv8-M. */
18193 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m
)
18194 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18195 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18196 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18202 /* Whether wide instruction variant can be used if available for a valid OPCODE
18206 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18208 if (known_t32_only_insn (opcode
))
18211 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18212 of variant T3 of B.W is checked in do_t_branch. */
18213 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18214 && opcode
->tencode
== do_t_branch
)
18217 /* Wide instruction variants of all instructions with narrow *and* wide
18218 variants become available with ARMv6t2. Other opcodes are either
18219 narrow-only or wide-only and are thus available if OPCODE is valid. */
18220 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18223 /* OPCODE with narrow only instruction variant or wide variant not
18229 md_assemble (char *str
)
18232 const struct asm_opcode
* opcode
;
18234 /* Align the previous label if needed. */
18235 if (last_label_seen
!= NULL
)
18237 symbol_set_frag (last_label_seen
, frag_now
);
18238 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18239 S_SET_SEGMENT (last_label_seen
, now_seg
);
18242 memset (&inst
, '\0', sizeof (inst
));
18243 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18245 opcode
= opcode_lookup (&p
);
18248 /* It wasn't an instruction, but it might be a register alias of
18249 the form alias .req reg, or a Neon .dn/.qn directive. */
18250 if (! create_register_alias (str
, p
)
18251 && ! create_neon_reg_alias (str
, p
))
18252 as_bad (_("bad instruction `%s'"), str
);
18257 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18258 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18260 /* The value which unconditional instructions should have in place of the
18261 condition field. */
18262 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18266 arm_feature_set variant
;
18268 variant
= cpu_variant
;
18269 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18270 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18271 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18272 /* Check that this instruction is supported for this CPU. */
18273 if (!opcode
->tvariant
18274 || (thumb_mode
== 1
18275 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18277 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18280 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18281 && opcode
->tencode
!= do_t_branch
)
18283 as_bad (_("Thumb does not support conditional execution"));
18287 /* Two things are addressed here:
18288 1) Implicit require narrow instructions on Thumb-1.
18289 This avoids relaxation accidentally introducing Thumb-2
18291 2) Reject wide instructions in non Thumb-2 cores.
18293 Only instructions with narrow and wide variants need to be handled
18294 but selecting all non wide-only instructions is easier. */
18295 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18296 && !t32_insn_ok (variant
, opcode
))
18298 if (inst
.size_req
== 0)
18300 else if (inst
.size_req
== 4)
18302 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18303 as_bad (_("selected processor does not support 32bit wide "
18304 "variant of instruction `%s'"), str
);
18306 as_bad (_("selected processor does not support `%s' in "
18307 "Thumb-2 mode"), str
);
18312 inst
.instruction
= opcode
->tvalue
;
18314 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18316 /* Prepare the it_insn_type for those encodings that don't set
18318 it_fsm_pre_encode ();
18320 opcode
->tencode ();
18322 it_fsm_post_encode ();
18325 if (!(inst
.error
|| inst
.relax
))
18327 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18328 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18329 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18331 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18336 /* Something has gone badly wrong if we try to relax a fixed size
18338 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18340 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18341 *opcode
->tvariant
);
18342 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18343 set those bits when Thumb-2 32-bit instructions are seen. The impact
18344 of relaxable instructions will be considered later after we finish all
18346 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18347 variant
= arm_arch_none
;
18349 variant
= cpu_variant
;
18350 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18351 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18354 check_neon_suffixes
;
18358 mapping_state (MAP_THUMB
);
18361 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18365 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18366 is_bx
= (opcode
->aencode
== do_bx
);
18368 /* Check that this instruction is supported for this CPU. */
18369 if (!(is_bx
&& fix_v4bx
)
18370 && !(opcode
->avariant
&&
18371 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18373 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18378 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18382 inst
.instruction
= opcode
->avalue
;
18383 if (opcode
->tag
== OT_unconditionalF
)
18384 inst
.instruction
|= 0xFU
<< 28;
18386 inst
.instruction
|= inst
.cond
<< 28;
18387 inst
.size
= INSN_SIZE
;
18388 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18390 it_fsm_pre_encode ();
18391 opcode
->aencode ();
18392 it_fsm_post_encode ();
18394 /* Arm mode bx is marked as both v4T and v5 because it's still required
18395 on a hypothetical non-thumb v5 core. */
18397 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18399 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18400 *opcode
->avariant
);
18402 check_neon_suffixes
;
18406 mapping_state (MAP_ARM
);
18411 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18419 check_it_blocks_finished (void)
18424 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18425 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18426 == MANUAL_IT_BLOCK
)
18428 as_warn (_("section '%s' finished with an open IT block."),
18432 if (now_it
.state
== MANUAL_IT_BLOCK
)
18433 as_warn (_("file finished with an open IT block."));
18437 /* Various frobbings of labels and their addresses. */
18440 arm_start_line_hook (void)
18442 last_label_seen
= NULL
;
18446 arm_frob_label (symbolS
* sym
)
18448 last_label_seen
= sym
;
18450 ARM_SET_THUMB (sym
, thumb_mode
);
18452 #if defined OBJ_COFF || defined OBJ_ELF
18453 ARM_SET_INTERWORK (sym
, support_interwork
);
18456 force_automatic_it_block_close ();
18458 /* Note - do not allow local symbols (.Lxxx) to be labelled
18459 as Thumb functions. This is because these labels, whilst
18460 they exist inside Thumb code, are not the entry points for
18461 possible ARM->Thumb calls. Also, these labels can be used
18462 as part of a computed goto or switch statement. eg gcc
18463 can generate code that looks like this:
18465 ldr r2, [pc, .Laaa]
18475 The first instruction loads the address of the jump table.
18476 The second instruction converts a table index into a byte offset.
18477 The third instruction gets the jump address out of the table.
18478 The fourth instruction performs the jump.
18480 If the address stored at .Laaa is that of a symbol which has the
18481 Thumb_Func bit set, then the linker will arrange for this address
18482 to have the bottom bit set, which in turn would mean that the
18483 address computation performed by the third instruction would end
18484 up with the bottom bit set. Since the ARM is capable of unaligned
18485 word loads, the instruction would then load the incorrect address
18486 out of the jump table, and chaos would ensue. */
18487 if (label_is_thumb_function_name
18488 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18489 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18491 /* When the address of a Thumb function is taken the bottom
18492 bit of that address should be set. This will allow
18493 interworking between Arm and Thumb functions to work
18496 THUMB_SET_FUNC (sym
, 1);
18498 label_is_thumb_function_name
= FALSE
;
18501 dwarf2_emit_label (sym
);
18505 arm_data_in_code (void)
18507 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18509 *input_line_pointer
= '/';
18510 input_line_pointer
+= 5;
18511 *input_line_pointer
= 0;
18519 arm_canonicalize_symbol_name (char * name
)
18523 if (thumb_mode
&& (len
= strlen (name
)) > 5
18524 && streq (name
+ len
- 5, "/data"))
18525 *(name
+ len
- 5) = 0;
18530 /* Table of all register names defined by default. The user can
18531 define additional names with .req. Note that all register names
18532 should appear in both upper and lowercase variants. Some registers
18533 also have mixed-case names. */
18535 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18536 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18537 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18538 #define REGSET(p,t) \
18539 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18540 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18541 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18542 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18543 #define REGSETH(p,t) \
18544 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18545 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18546 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18547 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18548 #define REGSET2(p,t) \
18549 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18550 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18551 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18552 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18553 #define SPLRBANK(base,bank,t) \
18554 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18555 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18556 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18557 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18558 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18559 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18561 static const struct reg_entry reg_names
[] =
18563 /* ARM integer registers. */
18564 REGSET(r
, RN
), REGSET(R
, RN
),
18566 /* ATPCS synonyms. */
18567 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18568 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18569 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18571 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18572 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18573 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18575 /* Well-known aliases. */
18576 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18577 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18579 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18580 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18582 /* Coprocessor numbers. */
18583 REGSET(p
, CP
), REGSET(P
, CP
),
18585 /* Coprocessor register numbers. The "cr" variants are for backward
18587 REGSET(c
, CN
), REGSET(C
, CN
),
18588 REGSET(cr
, CN
), REGSET(CR
, CN
),
18590 /* ARM banked registers. */
18591 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18592 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18593 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18594 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18595 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18596 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18597 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18599 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18600 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18601 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18602 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18603 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18604 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18605 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18606 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18608 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18609 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18610 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18611 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18612 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18613 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18614 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18615 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18616 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18618 /* FPA registers. */
18619 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18620 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18622 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18623 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18625 /* VFP SP registers. */
18626 REGSET(s
,VFS
), REGSET(S
,VFS
),
18627 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18629 /* VFP DP Registers. */
18630 REGSET(d
,VFD
), REGSET(D
,VFD
),
18631 /* Extra Neon DP registers. */
18632 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18634 /* Neon QP registers. */
18635 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18637 /* VFP control registers. */
18638 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18639 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18640 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18641 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18642 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18643 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18645 /* Maverick DSP coprocessor registers. */
18646 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18647 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18649 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18650 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18651 REGDEF(dspsc
,0,DSPSC
),
18653 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18654 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18655 REGDEF(DSPSC
,0,DSPSC
),
18657 /* iWMMXt data registers - p0, c0-15. */
18658 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18660 /* iWMMXt control registers - p1, c0-3. */
18661 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18662 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18663 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18664 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18666 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18667 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18668 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18669 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18670 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18672 /* XScale accumulator registers. */
18673 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18679 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18680 within psr_required_here. */
18681 static const struct asm_psr psrs
[] =
18683 /* Backward compatibility notation. Note that "all" is no longer
18684 truly all possible PSR bits. */
18685 {"all", PSR_c
| PSR_f
},
18689 /* Individual flags. */
18695 /* Combinations of flags. */
18696 {"fs", PSR_f
| PSR_s
},
18697 {"fx", PSR_f
| PSR_x
},
18698 {"fc", PSR_f
| PSR_c
},
18699 {"sf", PSR_s
| PSR_f
},
18700 {"sx", PSR_s
| PSR_x
},
18701 {"sc", PSR_s
| PSR_c
},
18702 {"xf", PSR_x
| PSR_f
},
18703 {"xs", PSR_x
| PSR_s
},
18704 {"xc", PSR_x
| PSR_c
},
18705 {"cf", PSR_c
| PSR_f
},
18706 {"cs", PSR_c
| PSR_s
},
18707 {"cx", PSR_c
| PSR_x
},
18708 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18709 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18710 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18711 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18712 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18713 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18714 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18715 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18716 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18717 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18718 {"scf", PSR_s
| PSR_c
| PSR_f
},
18719 {"scx", PSR_s
| PSR_c
| PSR_x
},
18720 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18721 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18722 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18723 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18724 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18725 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18726 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18727 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18728 {"csf", PSR_c
| PSR_s
| PSR_f
},
18729 {"csx", PSR_c
| PSR_s
| PSR_x
},
18730 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18731 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18732 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18733 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18734 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18735 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18736 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18737 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18738 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18739 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18740 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18741 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18742 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18743 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18744 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18745 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18746 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18747 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18748 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18749 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18750 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18751 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18752 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18753 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18754 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18755 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18758 /* Table of V7M psr names. */
18759 static const struct asm_psr v7m_psrs
[] =
18761 {"apsr", 0 }, {"APSR", 0 },
18762 {"iapsr", 1 }, {"IAPSR", 1 },
18763 {"eapsr", 2 }, {"EAPSR", 2 },
18764 {"psr", 3 }, {"PSR", 3 },
18765 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18766 {"ipsr", 5 }, {"IPSR", 5 },
18767 {"epsr", 6 }, {"EPSR", 6 },
18768 {"iepsr", 7 }, {"IEPSR", 7 },
18769 {"msp", 8 }, {"MSP", 8 },
18770 {"psp", 9 }, {"PSP", 9 },
18771 {"primask", 16}, {"PRIMASK", 16},
18772 {"basepri", 17}, {"BASEPRI", 17},
18773 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18774 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18775 {"faultmask", 19}, {"FAULTMASK", 19},
18776 {"control", 20}, {"CONTROL", 20}
18779 /* Table of all shift-in-operand names. */
18780 static const struct asm_shift_name shift_names
[] =
18782 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18783 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18784 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18785 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18786 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18787 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18790 /* Table of all explicit relocation names. */
18792 static struct reloc_entry reloc_names
[] =
18794 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18795 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18796 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18797 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18798 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18799 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18800 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18801 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18802 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18803 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18804 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18805 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18806 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18807 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18808 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18809 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18810 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18811 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18815 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18816 static const struct asm_cond conds
[] =
18820 {"cs", 0x2}, {"hs", 0x2},
18821 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18835 #define UL_BARRIER(L,U,CODE,FEAT) \
18836 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18837 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18839 static struct asm_barrier_opt barrier_opt_names
[] =
18841 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18842 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18843 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18844 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18845 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18846 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18847 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18848 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18849 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18850 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18851 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18852 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18853 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18854 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18855 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18856 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18861 /* Table of ARM-format instructions. */
18863 /* Macros for gluing together operand strings. N.B. In all cases
18864 other than OPS0, the trailing OP_stop comes from default
18865 zero-initialization of the unspecified elements of the array. */
18866 #define OPS0() { OP_stop, }
18867 #define OPS1(a) { OP_##a, }
18868 #define OPS2(a,b) { OP_##a,OP_##b, }
18869 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18870 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18871 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18872 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18874 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18875 This is useful when mixing operands for ARM and THUMB, i.e. using the
18876 MIX_ARM_THUMB_OPERANDS macro.
18877 In order to use these macros, prefix the number of operands with _
18879 #define OPS_1(a) { a, }
18880 #define OPS_2(a,b) { a,b, }
18881 #define OPS_3(a,b,c) { a,b,c, }
18882 #define OPS_4(a,b,c,d) { a,b,c,d, }
18883 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18884 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18886 /* These macros abstract out the exact format of the mnemonic table and
18887 save some repeated characters. */
18889 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18890 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18891 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18892 THUMB_VARIANT, do_##ae, do_##te }
18894 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18895 a T_MNEM_xyz enumerator. */
18896 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18897 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18898 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18899 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18901 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18902 infix after the third character. */
18903 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18904 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18905 THUMB_VARIANT, do_##ae, do_##te }
18906 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18907 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18908 THUMB_VARIANT, do_##ae, do_##te }
18909 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18910 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18911 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18912 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18913 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18914 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18915 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18916 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18918 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18919 field is still 0xE. Many of the Thumb variants can be executed
18920 conditionally, so this is checked separately. */
18921 #define TUE(mnem, op, top, nops, ops, ae, te) \
18922 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18923 THUMB_VARIANT, do_##ae, do_##te }
18925 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18926 Used by mnemonics that have very minimal differences in the encoding for
18927 ARM and Thumb variants and can be handled in a common function. */
18928 #define TUEc(mnem, op, top, nops, ops, en) \
18929 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18930 THUMB_VARIANT, do_##en, do_##en }
18932 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18933 condition code field. */
18934 #define TUF(mnem, op, top, nops, ops, ae, te) \
18935 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18936 THUMB_VARIANT, do_##ae, do_##te }
18938 /* ARM-only variants of all the above. */
18939 #define CE(mnem, op, nops, ops, ae) \
18940 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18942 #define C3(mnem, op, nops, ops, ae) \
18943 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18945 /* Legacy mnemonics that always have conditional infix after the third
18947 #define CL(mnem, op, nops, ops, ae) \
18948 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18949 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18951 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18952 #define cCE(mnem, op, nops, ops, ae) \
18953 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18955 /* Legacy coprocessor instructions where conditional infix and conditional
18956 suffix are ambiguous. For consistency this includes all FPA instructions,
18957 not just the potentially ambiguous ones. */
18958 #define cCL(mnem, op, nops, ops, ae) \
18959 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18960 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18962 /* Coprocessor, takes either a suffix or a position-3 infix
18963 (for an FPA corner case). */
18964 #define C3E(mnem, op, nops, ops, ae) \
18965 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18966 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18968 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18969 { m1 #m2 m3, OPS##nops ops, \
18970 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18971 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18973 #define CM(m1, m2, op, nops, ops, ae) \
18974 xCM_ (m1, , m2, op, nops, ops, ae), \
18975 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18976 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18977 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18978 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18979 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18980 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18981 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18982 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18983 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18984 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18985 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18986 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18987 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18988 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18989 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18990 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18991 xCM_ (m1, le, m2, op, nops, ops, ae), \
18992 xCM_ (m1, al, m2, op, nops, ops, ae)
18994 #define UE(mnem, op, nops, ops, ae) \
18995 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18997 #define UF(mnem, op, nops, ops, ae) \
18998 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19000 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19001 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19002 use the same encoding function for each. */
19003 #define NUF(mnem, op, nops, ops, enc) \
19004 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19005 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19007 /* Neon data processing, version which indirects through neon_enc_tab for
19008 the various overloaded versions of opcodes. */
19009 #define nUF(mnem, op, nops, ops, enc) \
19010 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19011 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19013 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19015 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19016 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19017 THUMB_VARIANT, do_##enc, do_##enc }
19019 #define NCE(mnem, op, nops, ops, enc) \
19020 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19022 #define NCEF(mnem, op, nops, ops, enc) \
19023 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19025 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19026 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19027 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19028 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19030 #define nCE(mnem, op, nops, ops, enc) \
19031 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19033 #define nCEF(mnem, op, nops, ops, enc) \
19034 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19038 static const struct asm_opcode insns
[] =
19040 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19041 #define THUMB_VARIANT & arm_ext_v4t
19042 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19043 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19044 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19045 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19046 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19047 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19048 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19049 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19050 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19051 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19052 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19053 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19054 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19055 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19056 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19057 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19059 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19060 for setting PSR flag bits. They are obsolete in V6 and do not
19061 have Thumb equivalents. */
19062 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19063 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19064 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19065 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19066 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19067 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19068 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19069 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19070 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19072 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19073 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19074 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19075 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19077 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19078 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19079 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19081 OP_ADDRGLDR
),ldst
, t_ldst
),
19082 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19084 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19085 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19086 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19087 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19088 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19089 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19091 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19092 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19093 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19094 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19097 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19098 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19099 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19100 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19102 /* Thumb-compatibility pseudo ops. */
19103 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19104 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19105 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19106 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19107 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19108 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19109 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19110 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19111 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19112 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19113 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19114 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19116 /* These may simplify to neg. */
19117 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19118 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19120 #undef THUMB_VARIANT
19121 #define THUMB_VARIANT & arm_ext_v6
19123 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19125 /* V1 instructions with no Thumb analogue prior to V6T2. */
19126 #undef THUMB_VARIANT
19127 #define THUMB_VARIANT & arm_ext_v6t2
19129 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19130 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19131 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19133 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19134 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19135 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19136 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19138 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19139 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19141 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19142 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19144 /* V1 instructions with no Thumb analogue at all. */
19145 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19146 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19148 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19149 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19150 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19151 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19152 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19153 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19154 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19155 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19158 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19159 #undef THUMB_VARIANT
19160 #define THUMB_VARIANT & arm_ext_v4t
19162 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19163 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19165 #undef THUMB_VARIANT
19166 #define THUMB_VARIANT & arm_ext_v6t2
19168 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19169 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19171 /* Generic coprocessor instructions. */
19172 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19173 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19174 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19175 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19176 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19177 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19178 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19181 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19183 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19184 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19187 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19188 #undef THUMB_VARIANT
19189 #define THUMB_VARIANT & arm_ext_msr
19191 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19192 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19195 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19196 #undef THUMB_VARIANT
19197 #define THUMB_VARIANT & arm_ext_v6t2
19199 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19200 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19201 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19202 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19203 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19204 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19205 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19206 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19209 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19210 #undef THUMB_VARIANT
19211 #define THUMB_VARIANT & arm_ext_v4t
19213 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19214 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19215 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19216 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19217 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19218 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19221 #define ARM_VARIANT & arm_ext_v4t_5
19223 /* ARM Architecture 4T. */
19224 /* Note: bx (and blx) are required on V5, even if the processor does
19225 not support Thumb. */
19226 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19229 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19230 #undef THUMB_VARIANT
19231 #define THUMB_VARIANT & arm_ext_v5t
19233 /* Note: blx has 2 variants; the .value coded here is for
19234 BLX(2). Only this variant has conditional execution. */
19235 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19236 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19238 #undef THUMB_VARIANT
19239 #define THUMB_VARIANT & arm_ext_v6t2
19241 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19242 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19243 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19244 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19245 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19246 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19247 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19248 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19251 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19252 #undef THUMB_VARIANT
19253 #define THUMB_VARIANT & arm_ext_v5exp
19255 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19256 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19257 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19258 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19260 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19261 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19263 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19264 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19265 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19266 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19268 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19269 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19270 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19271 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19273 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19274 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19276 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19277 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19278 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19279 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19282 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19283 #undef THUMB_VARIANT
19284 #define THUMB_VARIANT & arm_ext_v6t2
19286 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19287 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19289 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19290 ADDRGLDRS
), ldrd
, t_ldstd
),
19292 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19293 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19296 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19298 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19301 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19302 #undef THUMB_VARIANT
19303 #define THUMB_VARIANT & arm_ext_v6
19305 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19306 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19307 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19308 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19309 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19310 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19311 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19312 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19313 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19314 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19316 #undef THUMB_VARIANT
19317 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19319 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19320 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19322 #undef THUMB_VARIANT
19323 #define THUMB_VARIANT & arm_ext_v6t2
19325 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19326 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19328 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19329 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19331 /* ARM V6 not included in V7M. */
19332 #undef THUMB_VARIANT
19333 #define THUMB_VARIANT & arm_ext_v6_notm
19334 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19335 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19336 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19337 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19338 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19339 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19340 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19341 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19342 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19343 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19344 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19345 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19346 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19347 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19348 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19349 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19350 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19351 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19352 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19354 /* ARM V6 not included in V7M (eg. integer SIMD). */
19355 #undef THUMB_VARIANT
19356 #define THUMB_VARIANT & arm_ext_v6_dsp
19357 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19358 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19359 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19360 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19361 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19362 /* Old name for QASX. */
19363 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19364 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19365 /* Old name for QSAX. */
19366 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19367 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19368 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19369 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19370 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19371 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19372 /* Old name for SASX. */
19373 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19374 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19375 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19376 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19377 /* Old name for SHASX. */
19378 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19379 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19380 /* Old name for SHSAX. */
19381 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19382 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19383 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19384 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19385 /* Old name for SSAX. */
19386 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19387 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19388 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19389 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19390 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19391 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19392 /* Old name for UASX. */
19393 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19394 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19395 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19396 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19397 /* Old name for UHASX. */
19398 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19399 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19400 /* Old name for UHSAX. */
19401 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19402 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19404 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19405 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19407 /* Old name for UQASX. */
19408 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19409 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19410 /* Old name for UQSAX. */
19411 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19412 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19413 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19414 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19416 /* Old name for USAX. */
19417 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19418 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19419 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19420 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19421 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19422 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19423 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19424 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19425 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19426 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19427 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19429 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19430 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19431 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19432 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19433 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19434 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19435 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19436 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19437 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19438 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19439 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19440 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19441 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19442 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19443 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19444 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19445 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19446 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19447 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19448 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19449 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19450 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19453 #define ARM_VARIANT & arm_ext_v6k
19454 #undef THUMB_VARIANT
19455 #define THUMB_VARIANT & arm_ext_v6k
19457 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19458 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19459 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19460 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19462 #undef THUMB_VARIANT
19463 #define THUMB_VARIANT & arm_ext_v6_notm
19464 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19466 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19467 RRnpcb
), strexd
, t_strexd
),
19469 #undef THUMB_VARIANT
19470 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19471 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19473 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19475 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19477 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19479 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19482 #define ARM_VARIANT & arm_ext_sec
19483 #undef THUMB_VARIANT
19484 #define THUMB_VARIANT & arm_ext_sec
19486 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19489 #define ARM_VARIANT & arm_ext_virt
19490 #undef THUMB_VARIANT
19491 #define THUMB_VARIANT & arm_ext_virt
19493 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19494 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19497 #define ARM_VARIANT & arm_ext_pan
19498 #undef THUMB_VARIANT
19499 #define THUMB_VARIANT & arm_ext_pan
19501 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19504 #define ARM_VARIANT & arm_ext_v6t2
19505 #undef THUMB_VARIANT
19506 #define THUMB_VARIANT & arm_ext_v6t2
19508 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19509 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19510 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19511 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19513 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19514 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19516 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19517 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19518 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19519 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19521 #undef THUMB_VARIANT
19522 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19523 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19524 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19526 /* Thumb-only instructions. */
19528 #define ARM_VARIANT NULL
19529 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19530 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19532 /* ARM does not really have an IT instruction, so always allow it.
19533 The opcode is copied from Thumb in order to allow warnings in
19534 -mimplicit-it=[never | arm] modes. */
19536 #define ARM_VARIANT & arm_ext_v1
19537 #undef THUMB_VARIANT
19538 #define THUMB_VARIANT & arm_ext_v6t2
19540 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19541 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19542 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19543 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19544 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19545 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19546 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19547 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19548 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19549 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19550 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19551 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19552 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19553 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19554 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19555 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19556 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19557 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19559 /* Thumb2 only instructions. */
19561 #define ARM_VARIANT NULL
19563 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19564 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19565 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19566 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19567 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19568 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19570 /* Hardware division instructions. */
19572 #define ARM_VARIANT & arm_ext_adiv
19573 #undef THUMB_VARIANT
19574 #define THUMB_VARIANT & arm_ext_div
19576 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19577 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19579 /* ARM V6M/V7 instructions. */
19581 #define ARM_VARIANT & arm_ext_barrier
19582 #undef THUMB_VARIANT
19583 #define THUMB_VARIANT & arm_ext_barrier
19585 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19586 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19587 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19589 /* ARM V7 instructions. */
19591 #define ARM_VARIANT & arm_ext_v7
19592 #undef THUMB_VARIANT
19593 #define THUMB_VARIANT & arm_ext_v7
19595 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19596 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19599 #define ARM_VARIANT & arm_ext_mp
19600 #undef THUMB_VARIANT
19601 #define THUMB_VARIANT & arm_ext_mp
19603 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19605 /* AArchv8 instructions. */
19607 #define ARM_VARIANT & arm_ext_v8
19609 /* Instructions shared between armv8-a and armv8-m. */
19610 #undef THUMB_VARIANT
19611 #define THUMB_VARIANT & arm_ext_atomics
19613 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19614 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19615 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19616 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19617 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19618 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19619 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19620 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19621 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19622 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19624 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19626 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19628 #undef THUMB_VARIANT
19629 #define THUMB_VARIANT & arm_ext_v8
19631 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19632 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19633 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19635 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19637 /* ARMv8 T32 only. */
19639 #define ARM_VARIANT NULL
19640 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19641 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19642 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19644 /* FP for ARMv8. */
19646 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19647 #undef THUMB_VARIANT
19648 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19650 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19651 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19652 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19653 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19654 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19655 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19656 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19657 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19658 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19659 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19660 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19661 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19662 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19663 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19664 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19665 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19666 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19668 /* Crypto v1 extensions. */
19670 #define ARM_VARIANT & fpu_crypto_ext_armv8
19671 #undef THUMB_VARIANT
19672 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19674 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19675 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19676 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19677 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19678 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19679 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19680 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19681 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19682 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19683 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19684 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19685 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19686 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19687 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19690 #define ARM_VARIANT & crc_ext_armv8
19691 #undef THUMB_VARIANT
19692 #define THUMB_VARIANT & crc_ext_armv8
19693 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19694 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19695 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19696 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19697 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19698 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19700 /* ARMv8.2 RAS extension. */
19702 #define ARM_VARIANT & arm_ext_v8_2
19703 #undef THUMB_VARIANT
19704 #define THUMB_VARIANT & arm_ext_v8_2
19705 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19708 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19709 #undef THUMB_VARIANT
19710 #define THUMB_VARIANT NULL
19712 cCE("wfs", e200110
, 1, (RR
), rd
),
19713 cCE("rfs", e300110
, 1, (RR
), rd
),
19714 cCE("wfc", e400110
, 1, (RR
), rd
),
19715 cCE("rfc", e500110
, 1, (RR
), rd
),
19717 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19718 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19719 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19720 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19722 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19723 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19724 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19725 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19727 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19728 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19729 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19730 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19731 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19732 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19733 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19734 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19735 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19736 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19737 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19738 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19740 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19741 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19936 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19937 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19938 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19939 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19940 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19941 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19942 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19943 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19944 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19945 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19946 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19948 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19949 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20104 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20105 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20106 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20107 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20109 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20110 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20111 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20112 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20113 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20114 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20115 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20116 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20117 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20118 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20119 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20120 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20122 /* The implementation of the FIX instruction is broken on some
20123 assemblers, in that it accepts a precision specifier as well as a
20124 rounding specifier, despite the fact that this is meaningless.
20125 To be more compatible, we accept it as well, though of course it
20126 does not set any bits. */
20127 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20128 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20129 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20130 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20131 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20132 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20133 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20134 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20135 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20136 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20137 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20138 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20139 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20141 /* Instructions that were new with the real FPA, call them V2. */
20143 #define ARM_VARIANT & fpu_fpa_ext_v2
20145 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20146 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20147 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20148 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20149 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20150 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20153 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20155 /* Moves and type conversions. */
20156 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20157 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20158 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20159 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20160 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20161 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20162 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20163 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20164 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20165 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20166 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20167 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20168 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20169 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20171 /* Memory operations. */
20172 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20173 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20174 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20175 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20176 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20177 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20178 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20179 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20180 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20181 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20182 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20183 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20184 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20185 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20186 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20187 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20188 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20189 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20191 /* Monadic operations. */
20192 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20193 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20194 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20196 /* Dyadic operations. */
20197 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20198 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20199 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20200 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20201 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20202 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20203 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20204 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20205 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20208 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20209 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20210 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20211 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20213 /* Double precision load/store are still present on single precision
20214 implementations. */
20215 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20216 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20217 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20218 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20219 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20220 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20221 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20222 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20223 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20224 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20227 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20229 /* Moves and type conversions. */
20230 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20231 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20232 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20233 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20234 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20235 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20236 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20237 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20238 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20239 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20240 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20241 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20242 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20244 /* Monadic operations. */
20245 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20246 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20247 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20249 /* Dyadic operations. */
20250 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20251 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20252 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20253 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20254 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20255 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20256 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20257 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20258 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20261 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20262 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20263 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20264 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20267 #define ARM_VARIANT & fpu_vfp_ext_v2
20269 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20270 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20271 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20272 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20274 /* Instructions which may belong to either the Neon or VFP instruction sets.
20275 Individual encoder functions perform additional architecture checks. */
20277 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20278 #undef THUMB_VARIANT
20279 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20281 /* These mnemonics are unique to VFP. */
20282 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20283 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20284 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20285 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20286 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20287 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20288 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20289 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20290 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20291 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20293 /* Mnemonics shared by Neon and VFP. */
20294 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20295 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20296 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20298 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20299 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20301 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20302 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20304 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20305 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20306 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20307 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20308 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20309 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20310 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20311 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20313 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20314 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20315 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20316 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20319 /* NOTE: All VMOV encoding is special-cased! */
20320 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20321 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20324 #define ARM_VARIANT & arm_ext_fp16
20325 #undef THUMB_VARIANT
20326 #define THUMB_VARIANT & arm_ext_fp16
20327 /* New instructions added from v8.2, allowing the extraction and insertion of
20328 the upper 16 bits of a 32-bit vector register. */
20329 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20330 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20332 #undef THUMB_VARIANT
20333 #define THUMB_VARIANT & fpu_neon_ext_v1
20335 #define ARM_VARIANT & fpu_neon_ext_v1
20337 /* Data processing with three registers of the same length. */
20338 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20339 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20340 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20341 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20342 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20343 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20344 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20345 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20346 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20347 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20348 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20349 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20350 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20351 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20352 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20353 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20354 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20355 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20356 /* If not immediate, fall back to neon_dyadic_i64_su.
20357 shl_imm should accept I8 I16 I32 I64,
20358 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20359 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20360 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20361 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20362 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20363 /* Logic ops, types optional & ignored. */
20364 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20365 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20366 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20367 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20368 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20369 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20370 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20371 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20372 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20373 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20374 /* Bitfield ops, untyped. */
20375 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20376 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20377 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20378 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20379 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20380 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20381 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20382 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20383 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20384 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20385 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20386 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20387 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20388 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20389 back to neon_dyadic_if_su. */
20390 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20391 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20392 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20393 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20394 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20395 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20396 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20397 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20398 /* Comparison. Type I8 I16 I32 F32. */
20399 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20400 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20401 /* As above, D registers only. */
20402 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20403 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20404 /* Int and float variants, signedness unimportant. */
20405 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20406 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20407 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20408 /* Add/sub take types I8 I16 I32 I64 F32. */
20409 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20410 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20411 /* vtst takes sizes 8, 16, 32. */
20412 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20413 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20414 /* VMUL takes I8 I16 I32 F32 P8. */
20415 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20416 /* VQD{R}MULH takes S16 S32. */
20417 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20418 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20419 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20420 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20421 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20422 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20423 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20424 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20425 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20426 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20427 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20428 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20429 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20430 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20431 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20432 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20433 /* ARM v8.1 extension. */
20434 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20435 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20436 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20437 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20439 /* Two address, int/float. Types S8 S16 S32 F32. */
20440 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20441 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20443 /* Data processing with two registers and a shift amount. */
20444 /* Right shifts, and variants with rounding.
20445 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20446 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20447 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20448 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20449 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20450 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20451 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20452 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20453 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20454 /* Shift and insert. Sizes accepted 8 16 32 64. */
20455 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20456 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20457 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20458 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20459 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20460 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20461 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20462 /* Right shift immediate, saturating & narrowing, with rounding variants.
20463 Types accepted S16 S32 S64 U16 U32 U64. */
20464 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20465 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20466 /* As above, unsigned. Types accepted S16 S32 S64. */
20467 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20468 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20469 /* Right shift narrowing. Types accepted I16 I32 I64. */
20470 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20471 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20472 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20473 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20474 /* CVT with optional immediate for fixed-point variant. */
20475 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20477 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20478 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20480 /* Data processing, three registers of different lengths. */
20481 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20482 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20483 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20484 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20485 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20486 /* If not scalar, fall back to neon_dyadic_long.
20487 Vector types as above, scalar types S16 S32 U16 U32. */
20488 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20489 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20490 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20491 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20492 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20493 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20494 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20495 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20496 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20497 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20498 /* Saturating doubling multiplies. Types S16 S32. */
20499 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20500 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20501 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20502 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20503 S16 S32 U16 U32. */
20504 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20506 /* Extract. Size 8. */
20507 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20508 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20510 /* Two registers, miscellaneous. */
20511 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20512 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20513 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20514 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20515 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20516 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20517 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20518 /* Vector replicate. Sizes 8 16 32. */
20519 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20520 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20521 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20522 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20523 /* VMOVN. Types I16 I32 I64. */
20524 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20525 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20526 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20527 /* VQMOVUN. Types S16 S32 S64. */
20528 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20529 /* VZIP / VUZP. Sizes 8 16 32. */
20530 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20531 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20532 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20533 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20534 /* VQABS / VQNEG. Types S8 S16 S32. */
20535 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20536 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20537 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20538 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20539 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20540 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20541 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20542 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20543 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20544 /* Reciprocal estimates. Types U32 F16 F32. */
20545 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20546 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20547 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20548 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20549 /* VCLS. Types S8 S16 S32. */
20550 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20551 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20552 /* VCLZ. Types I8 I16 I32. */
20553 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20554 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20555 /* VCNT. Size 8. */
20556 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20557 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20558 /* Two address, untyped. */
20559 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20560 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20561 /* VTRN. Sizes 8 16 32. */
20562 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20563 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20565 /* Table lookup. Size 8. */
20566 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20567 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20569 #undef THUMB_VARIANT
20570 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20572 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20574 /* Neon element/structure load/store. */
20575 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20576 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20577 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20578 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20579 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20580 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20581 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20582 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20584 #undef THUMB_VARIANT
20585 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20587 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20588 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20589 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20590 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20591 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20592 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20593 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20594 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20595 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20596 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20598 #undef THUMB_VARIANT
20599 #define THUMB_VARIANT & fpu_vfp_ext_v3
20601 #define ARM_VARIANT & fpu_vfp_ext_v3
20603 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20604 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20605 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20606 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20607 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20608 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20609 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20610 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20611 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20614 #define ARM_VARIANT & fpu_vfp_ext_fma
20615 #undef THUMB_VARIANT
20616 #define THUMB_VARIANT & fpu_vfp_ext_fma
20617 /* Mnemonics shared by Neon and VFP. These are included in the
20618 VFP FMA variant; NEON and VFP FMA always includes the NEON
20619 FMA instructions. */
20620 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20621 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20622 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20623 the v form should always be used. */
20624 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20625 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20626 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20627 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20628 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20629 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20631 #undef THUMB_VARIANT
20633 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20635 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20636 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20637 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20638 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20639 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20640 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20641 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20642 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20645 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20647 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20648 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20649 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20650 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20651 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20652 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20653 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20654 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20655 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20656 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20657 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20658 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20659 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20660 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20661 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20662 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20663 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20664 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20665 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20666 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20667 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20668 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20669 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20670 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20671 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20672 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20673 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20674 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20675 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20676 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20677 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20678 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20679 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20680 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20681 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20682 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20683 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20684 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20685 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20686 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20687 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20688 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20689 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20690 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20691 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20692 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20693 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20694 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20695 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20696 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20697 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20698 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20699 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20700 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20701 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20702 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20703 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20704 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20708 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20710 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20711 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20712 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20713 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20714 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20715 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20716 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20717 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20728 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20729 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20730 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20731 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20732 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20735 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20736 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20738 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20748 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20749 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20750 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20751 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20752 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20753 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20758 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20759 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20760 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20761 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20762 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20763 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20764 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20765 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20766 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20767 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20768 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20769 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20770 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20771 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20772 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20773 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20774 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20775 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20776 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20777 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20778 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20779 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20780 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20787 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20789 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20790 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20791 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20792 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20793 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20794 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20795 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20799 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20800 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20801 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20802 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20803 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20804 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20811 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20813 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20814 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20815 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20816 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20817 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20818 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20819 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20824 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20825 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20826 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20827 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20828 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20829 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20830 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20831 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20832 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20833 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20834 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20858 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20860 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20874 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20875 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20876 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20877 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20878 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20879 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20880 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20881 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20882 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20883 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20884 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20885 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20886 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20887 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20888 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20889 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20890 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20891 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20892 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20893 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20894 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20895 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20896 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20897 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20898 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20899 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20900 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20901 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20902 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20903 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20904 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20905 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20906 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20907 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20908 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20909 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20910 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20911 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20912 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20913 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20914 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20915 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20916 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20917 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20918 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20919 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20920 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20921 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20922 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20923 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20924 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20925 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20926 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20927 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20928 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20929 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20930 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20931 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20932 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20933 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20934 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20935 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20936 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20937 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20938 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20939 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20940 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20941 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20942 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20943 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20944 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20945 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20946 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20947 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20948 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20949 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20952 #define ARM_VARIANT NULL
20953 #undef THUMB_VARIANT
20954 #define THUMB_VARIANT & arm_ext_v8m
20955 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20956 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20959 #undef THUMB_VARIANT
20985 /* MD interface: bits in the object file. */
20987 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20988 for use in the a.out file, and stores them in the array pointed to by buf.
20989 This knows about the endian-ness of the target machine and does
20990 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20991 2 (short) and 4 (long) Floating numbers are put out as a series of
20992 LITTLENUMS (shorts, here at least). */
20995 md_number_to_chars (char * buf
, valueT val
, int n
)
20997 if (target_big_endian
)
20998 number_to_chars_bigendian (buf
, val
, n
);
21000 number_to_chars_littleendian (buf
, val
, n
);
21004 md_chars_to_number (char * buf
, int n
)
21007 unsigned char * where
= (unsigned char *) buf
;
21009 if (target_big_endian
)
21014 result
|= (*where
++ & 255);
21022 result
|= (where
[n
] & 255);
21029 /* MD interface: Sections. */
21031 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21032 that an rs_machine_dependent frag may reach. */
21035 arm_frag_max_var (fragS
*fragp
)
21037 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21038 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21040 Note that we generate relaxable instructions even for cases that don't
21041 really need it, like an immediate that's a trivial constant. So we're
21042 overestimating the instruction size for some of those cases. Rather
21043 than putting more intelligence here, it would probably be better to
21044 avoid generating a relaxation frag in the first place when it can be
21045 determined up front that a short instruction will suffice. */
21047 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21051 /* Estimate the size of a frag before relaxing. Assume everything fits in
21055 md_estimate_size_before_relax (fragS
* fragp
,
21056 segT segtype ATTRIBUTE_UNUSED
)
21062 /* Convert a machine dependent frag. */
21065 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21067 unsigned long insn
;
21068 unsigned long old_op
;
21076 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21078 old_op
= bfd_get_16(abfd
, buf
);
21079 if (fragp
->fr_symbol
)
21081 exp
.X_op
= O_symbol
;
21082 exp
.X_add_symbol
= fragp
->fr_symbol
;
21086 exp
.X_op
= O_constant
;
21088 exp
.X_add_number
= fragp
->fr_offset
;
21089 opcode
= fragp
->fr_subtype
;
21092 case T_MNEM_ldr_pc
:
21093 case T_MNEM_ldr_pc2
:
21094 case T_MNEM_ldr_sp
:
21095 case T_MNEM_str_sp
:
21102 if (fragp
->fr_var
== 4)
21104 insn
= THUMB_OP32 (opcode
);
21105 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21107 insn
|= (old_op
& 0x700) << 4;
21111 insn
|= (old_op
& 7) << 12;
21112 insn
|= (old_op
& 0x38) << 13;
21114 insn
|= 0x00000c00;
21115 put_thumb32_insn (buf
, insn
);
21116 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21120 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21122 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21125 if (fragp
->fr_var
== 4)
21127 insn
= THUMB_OP32 (opcode
);
21128 insn
|= (old_op
& 0xf0) << 4;
21129 put_thumb32_insn (buf
, insn
);
21130 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21134 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21135 exp
.X_add_number
-= 4;
21143 if (fragp
->fr_var
== 4)
21145 int r0off
= (opcode
== T_MNEM_mov
21146 || opcode
== T_MNEM_movs
) ? 0 : 8;
21147 insn
= THUMB_OP32 (opcode
);
21148 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21149 insn
|= (old_op
& 0x700) << r0off
;
21150 put_thumb32_insn (buf
, insn
);
21151 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21155 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21160 if (fragp
->fr_var
== 4)
21162 insn
= THUMB_OP32(opcode
);
21163 put_thumb32_insn (buf
, insn
);
21164 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21167 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21171 if (fragp
->fr_var
== 4)
21173 insn
= THUMB_OP32(opcode
);
21174 insn
|= (old_op
& 0xf00) << 14;
21175 put_thumb32_insn (buf
, insn
);
21176 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21179 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21182 case T_MNEM_add_sp
:
21183 case T_MNEM_add_pc
:
21184 case T_MNEM_inc_sp
:
21185 case T_MNEM_dec_sp
:
21186 if (fragp
->fr_var
== 4)
21188 /* ??? Choose between add and addw. */
21189 insn
= THUMB_OP32 (opcode
);
21190 insn
|= (old_op
& 0xf0) << 4;
21191 put_thumb32_insn (buf
, insn
);
21192 if (opcode
== T_MNEM_add_pc
)
21193 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21195 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21198 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21206 if (fragp
->fr_var
== 4)
21208 insn
= THUMB_OP32 (opcode
);
21209 insn
|= (old_op
& 0xf0) << 4;
21210 insn
|= (old_op
& 0xf) << 16;
21211 put_thumb32_insn (buf
, insn
);
21212 if (insn
& (1 << 20))
21213 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21215 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21218 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21224 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21225 (enum bfd_reloc_code_real
) reloc_type
);
21226 fixp
->fx_file
= fragp
->fr_file
;
21227 fixp
->fx_line
= fragp
->fr_line
;
21228 fragp
->fr_fix
+= fragp
->fr_var
;
21230 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21231 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21232 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21233 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21236 /* Return the size of a relaxable immediate operand instruction.
21237 SHIFT and SIZE specify the form of the allowable immediate. */
21239 relax_immediate (fragS
*fragp
, int size
, int shift
)
21245 /* ??? Should be able to do better than this. */
21246 if (fragp
->fr_symbol
)
21249 low
= (1 << shift
) - 1;
21250 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21251 offset
= fragp
->fr_offset
;
21252 /* Force misaligned offsets to 32-bit variant. */
21255 if (offset
& ~mask
)
21260 /* Get the address of a symbol during relaxation. */
21262 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21268 sym
= fragp
->fr_symbol
;
21269 sym_frag
= symbol_get_frag (sym
);
21270 know (S_GET_SEGMENT (sym
) != absolute_section
21271 || sym_frag
== &zero_address_frag
);
21272 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21274 /* If frag has yet to be reached on this pass, assume it will
21275 move by STRETCH just as we did. If this is not so, it will
21276 be because some frag between grows, and that will force
21280 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21284 /* Adjust stretch for any alignment frag. Note that if have
21285 been expanding the earlier code, the symbol may be
21286 defined in what appears to be an earlier frag. FIXME:
21287 This doesn't handle the fr_subtype field, which specifies
21288 a maximum number of bytes to skip when doing an
21290 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21292 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21295 stretch
= - ((- stretch
)
21296 & ~ ((1 << (int) f
->fr_offset
) - 1));
21298 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21310 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21313 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21318 /* Assume worst case for symbols not known to be in the same section. */
21319 if (fragp
->fr_symbol
== NULL
21320 || !S_IS_DEFINED (fragp
->fr_symbol
)
21321 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21322 || S_IS_WEAK (fragp
->fr_symbol
))
21325 val
= relaxed_symbol_addr (fragp
, stretch
);
21326 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21327 addr
= (addr
+ 4) & ~3;
21328 /* Force misaligned targets to 32-bit variant. */
21332 if (val
< 0 || val
> 1020)
21337 /* Return the size of a relaxable add/sub immediate instruction. */
21339 relax_addsub (fragS
*fragp
, asection
*sec
)
21344 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21345 op
= bfd_get_16(sec
->owner
, buf
);
21346 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21347 return relax_immediate (fragp
, 8, 0);
21349 return relax_immediate (fragp
, 3, 0);
21352 /* Return TRUE iff the definition of symbol S could be pre-empted
21353 (overridden) at link or load time. */
21355 symbol_preemptible (symbolS
*s
)
21357 /* Weak symbols can always be pre-empted. */
21361 /* Non-global symbols cannot be pre-empted. */
21362 if (! S_IS_EXTERNAL (s
))
21366 /* In ELF, a global symbol can be marked protected, or private. In that
21367 case it can't be pre-empted (other definitions in the same link unit
21368 would violate the ODR). */
21369 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21373 /* Other global symbols might be pre-empted. */
21377 /* Return the size of a relaxable branch instruction. BITS is the
21378 size of the offset field in the narrow instruction. */
21381 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21387 /* Assume worst case for symbols not known to be in the same section. */
21388 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21389 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21390 || S_IS_WEAK (fragp
->fr_symbol
))
21394 /* A branch to a function in ARM state will require interworking. */
21395 if (S_IS_DEFINED (fragp
->fr_symbol
)
21396 && ARM_IS_FUNC (fragp
->fr_symbol
))
21400 if (symbol_preemptible (fragp
->fr_symbol
))
21403 val
= relaxed_symbol_addr (fragp
, stretch
);
21404 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21407 /* Offset is a signed value *2 */
21409 if (val
>= limit
|| val
< -limit
)
21415 /* Relax a machine dependent frag. This returns the amount by which
21416 the current size of the frag should change. */
21419 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21424 oldsize
= fragp
->fr_var
;
21425 switch (fragp
->fr_subtype
)
21427 case T_MNEM_ldr_pc2
:
21428 newsize
= relax_adr (fragp
, sec
, stretch
);
21430 case T_MNEM_ldr_pc
:
21431 case T_MNEM_ldr_sp
:
21432 case T_MNEM_str_sp
:
21433 newsize
= relax_immediate (fragp
, 8, 2);
21437 newsize
= relax_immediate (fragp
, 5, 2);
21441 newsize
= relax_immediate (fragp
, 5, 1);
21445 newsize
= relax_immediate (fragp
, 5, 0);
21448 newsize
= relax_adr (fragp
, sec
, stretch
);
21454 newsize
= relax_immediate (fragp
, 8, 0);
21457 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21460 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21462 case T_MNEM_add_sp
:
21463 case T_MNEM_add_pc
:
21464 newsize
= relax_immediate (fragp
, 8, 2);
21466 case T_MNEM_inc_sp
:
21467 case T_MNEM_dec_sp
:
21468 newsize
= relax_immediate (fragp
, 7, 2);
21474 newsize
= relax_addsub (fragp
, sec
);
21480 fragp
->fr_var
= newsize
;
21481 /* Freeze wide instructions that are at or before the same location as
21482 in the previous pass. This avoids infinite loops.
21483 Don't freeze them unconditionally because targets may be artificially
21484 misaligned by the expansion of preceding frags. */
21485 if (stretch
<= 0 && newsize
> 2)
21487 md_convert_frag (sec
->owner
, sec
, fragp
);
21491 return newsize
- oldsize
;
21494 /* Round up a section size to the appropriate boundary. */
21497 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21500 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21501 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21503 /* For a.out, force the section size to be aligned. If we don't do
21504 this, BFD will align it for us, but it will not write out the
21505 final bytes of the section. This may be a bug in BFD, but it is
21506 easier to fix it here since that is how the other a.out targets
21510 align
= bfd_get_section_alignment (stdoutput
, segment
);
21511 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21518 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21519 of an rs_align_code fragment. */
21522 arm_handle_align (fragS
* fragP
)
21524 static unsigned char const arm_noop
[2][2][4] =
21527 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21528 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21531 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21532 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21535 static unsigned char const thumb_noop
[2][2][2] =
21538 {0xc0, 0x46}, /* LE */
21539 {0x46, 0xc0}, /* BE */
21542 {0x00, 0xbf}, /* LE */
21543 {0xbf, 0x00} /* BE */
21546 static unsigned char const wide_thumb_noop
[2][4] =
21547 { /* Wide Thumb-2 */
21548 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21549 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21552 unsigned bytes
, fix
, noop_size
;
21554 const unsigned char * noop
;
21555 const unsigned char *narrow_noop
= NULL
;
21560 if (fragP
->fr_type
!= rs_align_code
)
21563 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21564 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21567 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21568 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21570 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21572 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21574 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21575 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21577 narrow_noop
= thumb_noop
[1][target_big_endian
];
21578 noop
= wide_thumb_noop
[target_big_endian
];
21581 noop
= thumb_noop
[0][target_big_endian
];
21589 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21590 ? selected_cpu
: arm_arch_none
,
21592 [target_big_endian
];
21599 fragP
->fr_var
= noop_size
;
21601 if (bytes
& (noop_size
- 1))
21603 fix
= bytes
& (noop_size
- 1);
21605 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21607 memset (p
, 0, fix
);
21614 if (bytes
& noop_size
)
21616 /* Insert a narrow noop. */
21617 memcpy (p
, narrow_noop
, noop_size
);
21619 bytes
-= noop_size
;
21623 /* Use wide noops for the remainder */
21627 while (bytes
>= noop_size
)
21629 memcpy (p
, noop
, noop_size
);
21631 bytes
-= noop_size
;
21635 fragP
->fr_fix
+= fix
;
21638 /* Called from md_do_align. Used to create an alignment
21639 frag in a code section. */
21642 arm_frag_align_code (int n
, int max
)
21646 /* We assume that there will never be a requirement
21647 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21648 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21653 _("alignments greater than %d bytes not supported in .text sections."),
21654 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21655 as_fatal ("%s", err_msg
);
21658 p
= frag_var (rs_align_code
,
21659 MAX_MEM_FOR_RS_ALIGN_CODE
,
21661 (relax_substateT
) max
,
21668 /* Perform target specific initialisation of a frag.
21669 Note - despite the name this initialisation is not done when the frag
21670 is created, but only when its type is assigned. A frag can be created
21671 and used a long time before its type is set, so beware of assuming that
21672 this initialisationis performed first. */
21676 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21678 /* Record whether this frag is in an ARM or a THUMB area. */
21679 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21682 #else /* OBJ_ELF is defined. */
21684 arm_init_frag (fragS
* fragP
, int max_chars
)
21686 int frag_thumb_mode
;
21688 /* If the current ARM vs THUMB mode has not already
21689 been recorded into this frag then do so now. */
21690 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21691 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21693 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21695 /* Record a mapping symbol for alignment frags. We will delete this
21696 later if the alignment ends up empty. */
21697 switch (fragP
->fr_type
)
21700 case rs_align_test
:
21702 mapping_state_2 (MAP_DATA
, max_chars
);
21704 case rs_align_code
:
21705 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21712 /* When we change sections we need to issue a new mapping symbol. */
21715 arm_elf_change_section (void)
21717 /* Link an unlinked unwind index table section to the .text section. */
21718 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21719 && elf_linked_to_section (now_seg
) == NULL
)
21720 elf_linked_to_section (now_seg
) = text_section
;
21724 arm_elf_section_type (const char * str
, size_t len
)
21726 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21727 return SHT_ARM_EXIDX
;
21732 /* Code to deal with unwinding tables. */
21734 static void add_unwind_adjustsp (offsetT
);
21736 /* Generate any deferred unwind frame offset. */
21739 flush_pending_unwind (void)
21743 offset
= unwind
.pending_offset
;
21744 unwind
.pending_offset
= 0;
21746 add_unwind_adjustsp (offset
);
21749 /* Add an opcode to this list for this function. Two-byte opcodes should
21750 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21754 add_unwind_opcode (valueT op
, int length
)
21756 /* Add any deferred stack adjustment. */
21757 if (unwind
.pending_offset
)
21758 flush_pending_unwind ();
21760 unwind
.sp_restored
= 0;
21762 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21764 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21765 if (unwind
.opcodes
)
21766 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21767 unwind
.opcode_alloc
);
21769 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21774 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21776 unwind
.opcode_count
++;
21780 /* Add unwind opcodes to adjust the stack pointer. */
21783 add_unwind_adjustsp (offsetT offset
)
21787 if (offset
> 0x200)
21789 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21794 /* Long form: 0xb2, uleb128. */
21795 /* This might not fit in a word so add the individual bytes,
21796 remembering the list is built in reverse order. */
21797 o
= (valueT
) ((offset
- 0x204) >> 2);
21799 add_unwind_opcode (0, 1);
21801 /* Calculate the uleb128 encoding of the offset. */
21805 bytes
[n
] = o
& 0x7f;
21811 /* Add the insn. */
21813 add_unwind_opcode (bytes
[n
- 1], 1);
21814 add_unwind_opcode (0xb2, 1);
21816 else if (offset
> 0x100)
21818 /* Two short opcodes. */
21819 add_unwind_opcode (0x3f, 1);
21820 op
= (offset
- 0x104) >> 2;
21821 add_unwind_opcode (op
, 1);
21823 else if (offset
> 0)
21825 /* Short opcode. */
21826 op
= (offset
- 4) >> 2;
21827 add_unwind_opcode (op
, 1);
21829 else if (offset
< 0)
21832 while (offset
> 0x100)
21834 add_unwind_opcode (0x7f, 1);
21837 op
= ((offset
- 4) >> 2) | 0x40;
21838 add_unwind_opcode (op
, 1);
21842 /* Finish the list of unwind opcodes for this function. */
21844 finish_unwind_opcodes (void)
21848 if (unwind
.fp_used
)
21850 /* Adjust sp as necessary. */
21851 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21852 flush_pending_unwind ();
21854 /* After restoring sp from the frame pointer. */
21855 op
= 0x90 | unwind
.fp_reg
;
21856 add_unwind_opcode (op
, 1);
21859 flush_pending_unwind ();
21863 /* Start an exception table entry. If idx is nonzero this is an index table
21867 start_unwind_section (const segT text_seg
, int idx
)
21869 const char * text_name
;
21870 const char * prefix
;
21871 const char * prefix_once
;
21872 const char * group_name
;
21876 size_t sec_name_len
;
21883 prefix
= ELF_STRING_ARM_unwind
;
21884 prefix_once
= ELF_STRING_ARM_unwind_once
;
21885 type
= SHT_ARM_EXIDX
;
21889 prefix
= ELF_STRING_ARM_unwind_info
;
21890 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21891 type
= SHT_PROGBITS
;
21894 text_name
= segment_name (text_seg
);
21895 if (streq (text_name
, ".text"))
21898 if (strncmp (text_name
, ".gnu.linkonce.t.",
21899 strlen (".gnu.linkonce.t.")) == 0)
21901 prefix
= prefix_once
;
21902 text_name
+= strlen (".gnu.linkonce.t.");
21905 prefix_len
= strlen (prefix
);
21906 text_len
= strlen (text_name
);
21907 sec_name_len
= prefix_len
+ text_len
;
21908 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21909 memcpy (sec_name
, prefix
, prefix_len
);
21910 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21911 sec_name
[prefix_len
+ text_len
] = '\0';
21917 /* Handle COMDAT group. */
21918 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21920 group_name
= elf_group_name (text_seg
);
21921 if (group_name
== NULL
)
21923 as_bad (_("Group section `%s' has no group signature"),
21924 segment_name (text_seg
));
21925 ignore_rest_of_line ();
21928 flags
|= SHF_GROUP
;
21932 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21934 /* Set the section link for index tables. */
21936 elf_linked_to_section (now_seg
) = text_seg
;
21940 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21941 personality routine data. Returns zero, or the index table value for
21942 an inline entry. */
21945 create_unwind_entry (int have_data
)
21950 /* The current word of data. */
21952 /* The number of bytes left in this word. */
21955 finish_unwind_opcodes ();
21957 /* Remember the current text section. */
21958 unwind
.saved_seg
= now_seg
;
21959 unwind
.saved_subseg
= now_subseg
;
21961 start_unwind_section (now_seg
, 0);
21963 if (unwind
.personality_routine
== NULL
)
21965 if (unwind
.personality_index
== -2)
21968 as_bad (_("handlerdata in cantunwind frame"));
21969 return 1; /* EXIDX_CANTUNWIND. */
21972 /* Use a default personality routine if none is specified. */
21973 if (unwind
.personality_index
== -1)
21975 if (unwind
.opcode_count
> 3)
21976 unwind
.personality_index
= 1;
21978 unwind
.personality_index
= 0;
21981 /* Space for the personality routine entry. */
21982 if (unwind
.personality_index
== 0)
21984 if (unwind
.opcode_count
> 3)
21985 as_bad (_("too many unwind opcodes for personality routine 0"));
21989 /* All the data is inline in the index table. */
21992 while (unwind
.opcode_count
> 0)
21994 unwind
.opcode_count
--;
21995 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21999 /* Pad with "finish" opcodes. */
22001 data
= (data
<< 8) | 0xb0;
22008 /* We get two opcodes "free" in the first word. */
22009 size
= unwind
.opcode_count
- 2;
22013 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22014 if (unwind
.personality_index
!= -1)
22016 as_bad (_("attempt to recreate an unwind entry"));
22020 /* An extra byte is required for the opcode count. */
22021 size
= unwind
.opcode_count
+ 1;
22024 size
= (size
+ 3) >> 2;
22026 as_bad (_("too many unwind opcodes"));
22028 frag_align (2, 0, 0);
22029 record_alignment (now_seg
, 2);
22030 unwind
.table_entry
= expr_build_dot ();
22032 /* Allocate the table entry. */
22033 ptr
= frag_more ((size
<< 2) + 4);
22034 /* PR 13449: Zero the table entries in case some of them are not used. */
22035 memset (ptr
, 0, (size
<< 2) + 4);
22036 where
= frag_now_fix () - ((size
<< 2) + 4);
22038 switch (unwind
.personality_index
)
22041 /* ??? Should this be a PLT generating relocation? */
22042 /* Custom personality routine. */
22043 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22044 BFD_RELOC_ARM_PREL31
);
22049 /* Set the first byte to the number of additional words. */
22050 data
= size
> 0 ? size
- 1 : 0;
22054 /* ABI defined personality routines. */
22056 /* Three opcodes bytes are packed into the first word. */
22063 /* The size and first two opcode bytes go in the first word. */
22064 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22069 /* Should never happen. */
22073 /* Pack the opcodes into words (MSB first), reversing the list at the same
22075 while (unwind
.opcode_count
> 0)
22079 md_number_to_chars (ptr
, data
, 4);
22084 unwind
.opcode_count
--;
22086 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22089 /* Finish off the last word. */
22092 /* Pad with "finish" opcodes. */
22094 data
= (data
<< 8) | 0xb0;
22096 md_number_to_chars (ptr
, data
, 4);
22101 /* Add an empty descriptor if there is no user-specified data. */
22102 ptr
= frag_more (4);
22103 md_number_to_chars (ptr
, 0, 4);
22110 /* Initialize the DWARF-2 unwind information for this procedure. */
22113 tc_arm_frame_initial_instructions (void)
22115 cfi_add_CFA_def_cfa (REG_SP
, 0);
22117 #endif /* OBJ_ELF */
22119 /* Convert REGNAME to a DWARF-2 register number. */
22122 tc_arm_regname_to_dw2regnum (char *regname
)
22124 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22128 /* PR 16694: Allow VFP registers as well. */
22129 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22133 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22142 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22146 exp
.X_op
= O_secrel
;
22147 exp
.X_add_symbol
= symbol
;
22148 exp
.X_add_number
= 0;
22149 emit_expr (&exp
, size
);
22153 /* MD interface: Symbol and relocation handling. */
22155 /* Return the address within the segment that a PC-relative fixup is
22156 relative to. For ARM, PC-relative fixups applied to instructions
22157 are generally relative to the location of the fixup plus 8 bytes.
22158 Thumb branches are offset by 4, and Thumb loads relative to PC
22159 require special handling. */
22162 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22164 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22166 /* If this is pc-relative and we are going to emit a relocation
22167 then we just want to put out any pipeline compensation that the linker
22168 will need. Otherwise we want to use the calculated base.
22169 For WinCE we skip the bias for externals as well, since this
22170 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22172 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22173 || (arm_force_relocation (fixP
)
22175 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22181 switch (fixP
->fx_r_type
)
22183 /* PC relative addressing on the Thumb is slightly odd as the
22184 bottom two bits of the PC are forced to zero for the
22185 calculation. This happens *after* application of the
22186 pipeline offset. However, Thumb adrl already adjusts for
22187 this, so we need not do it again. */
22188 case BFD_RELOC_ARM_THUMB_ADD
:
22191 case BFD_RELOC_ARM_THUMB_OFFSET
:
22192 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22193 case BFD_RELOC_ARM_T32_ADD_PC12
:
22194 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22195 return (base
+ 4) & ~3;
22197 /* Thumb branches are simply offset by +4. */
22198 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22199 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22200 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22201 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22202 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22205 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22207 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22208 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22209 && ARM_IS_FUNC (fixP
->fx_addsy
)
22210 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22211 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22214 /* BLX is like branches above, but forces the low two bits of PC to
22216 case BFD_RELOC_THUMB_PCREL_BLX
:
22218 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22219 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22220 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22221 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22222 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22223 return (base
+ 4) & ~3;
22225 /* ARM mode branches are offset by +8. However, the Windows CE
22226 loader expects the relocation not to take this into account. */
22227 case BFD_RELOC_ARM_PCREL_BLX
:
22229 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22230 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22231 && ARM_IS_FUNC (fixP
->fx_addsy
)
22232 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22233 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22236 case BFD_RELOC_ARM_PCREL_CALL
:
22238 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22239 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22240 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22241 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22242 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22245 case BFD_RELOC_ARM_PCREL_BRANCH
:
22246 case BFD_RELOC_ARM_PCREL_JUMP
:
22247 case BFD_RELOC_ARM_PLT32
:
22249 /* When handling fixups immediately, because we have already
22250 discovered the value of a symbol, or the address of the frag involved
22251 we must account for the offset by +8, as the OS loader will never see the reloc.
22252 see fixup_segment() in write.c
22253 The S_IS_EXTERNAL test handles the case of global symbols.
22254 Those need the calculated base, not just the pipe compensation the linker will need. */
22256 && fixP
->fx_addsy
!= NULL
22257 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22258 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22266 /* ARM mode loads relative to PC are also offset by +8. Unlike
22267 branches, the Windows CE loader *does* expect the relocation
22268 to take this into account. */
22269 case BFD_RELOC_ARM_OFFSET_IMM
:
22270 case BFD_RELOC_ARM_OFFSET_IMM8
:
22271 case BFD_RELOC_ARM_HWLITERAL
:
22272 case BFD_RELOC_ARM_LITERAL
:
22273 case BFD_RELOC_ARM_CP_OFF_IMM
:
22277 /* Other PC-relative relocations are un-offset. */
22283 static bfd_boolean flag_warn_syms
= TRUE
;
22286 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22288 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22289 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22290 does mean that the resulting code might be very confusing to the reader.
22291 Also this warning can be triggered if the user omits an operand before
22292 an immediate address, eg:
22296 GAS treats this as an assignment of the value of the symbol foo to a
22297 symbol LDR, and so (without this code) it will not issue any kind of
22298 warning or error message.
22300 Note - ARM instructions are case-insensitive but the strings in the hash
22301 table are all stored in lower case, so we must first ensure that name is
22303 if (flag_warn_syms
&& arm_ops_hsh
)
22305 char * nbuf
= strdup (name
);
22308 for (p
= nbuf
; *p
; p
++)
22310 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22312 static struct hash_control
* already_warned
= NULL
;
22314 if (already_warned
== NULL
)
22315 already_warned
= hash_new ();
22316 /* Only warn about the symbol once. To keep the code
22317 simple we let hash_insert do the lookup for us. */
22318 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22319 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22328 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22329 Otherwise we have no need to default values of symbols. */
22332 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22335 if (name
[0] == '_' && name
[1] == 'G'
22336 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22340 if (symbol_find (name
))
22341 as_bad (_("GOT already in the symbol table"));
22343 GOT_symbol
= symbol_new (name
, undefined_section
,
22344 (valueT
) 0, & zero_address_frag
);
22354 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22355 computed as two separate immediate values, added together. We
22356 already know that this value cannot be computed by just one ARM
22359 static unsigned int
22360 validate_immediate_twopart (unsigned int val
,
22361 unsigned int * highpart
)
22366 for (i
= 0; i
< 32; i
+= 2)
22367 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22373 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22375 else if (a
& 0xff0000)
22377 if (a
& 0xff000000)
22379 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22383 gas_assert (a
& 0xff000000);
22384 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22387 return (a
& 0xff) | (i
<< 7);
22394 validate_offset_imm (unsigned int val
, int hwse
)
22396 if ((hwse
&& val
> 255) || val
> 4095)
22401 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22402 negative immediate constant by altering the instruction. A bit of
22407 by inverting the second operand, and
22410 by negating the second operand. */
22413 negate_data_op (unsigned long * instruction
,
22414 unsigned long value
)
22417 unsigned long negated
, inverted
;
22419 negated
= encode_arm_immediate (-value
);
22420 inverted
= encode_arm_immediate (~value
);
22422 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22425 /* First negates. */
22426 case OPCODE_SUB
: /* ADD <-> SUB */
22427 new_inst
= OPCODE_ADD
;
22432 new_inst
= OPCODE_SUB
;
22436 case OPCODE_CMP
: /* CMP <-> CMN */
22437 new_inst
= OPCODE_CMN
;
22442 new_inst
= OPCODE_CMP
;
22446 /* Now Inverted ops. */
22447 case OPCODE_MOV
: /* MOV <-> MVN */
22448 new_inst
= OPCODE_MVN
;
22453 new_inst
= OPCODE_MOV
;
22457 case OPCODE_AND
: /* AND <-> BIC */
22458 new_inst
= OPCODE_BIC
;
22463 new_inst
= OPCODE_AND
;
22467 case OPCODE_ADC
: /* ADC <-> SBC */
22468 new_inst
= OPCODE_SBC
;
22473 new_inst
= OPCODE_ADC
;
22477 /* We cannot do anything. */
22482 if (value
== (unsigned) FAIL
)
22485 *instruction
&= OPCODE_MASK
;
22486 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22490 /* Like negate_data_op, but for Thumb-2. */
22492 static unsigned int
22493 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22497 unsigned int negated
, inverted
;
22499 negated
= encode_thumb32_immediate (-value
);
22500 inverted
= encode_thumb32_immediate (~value
);
22502 rd
= (*instruction
>> 8) & 0xf;
22503 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22506 /* ADD <-> SUB. Includes CMP <-> CMN. */
22507 case T2_OPCODE_SUB
:
22508 new_inst
= T2_OPCODE_ADD
;
22512 case T2_OPCODE_ADD
:
22513 new_inst
= T2_OPCODE_SUB
;
22517 /* ORR <-> ORN. Includes MOV <-> MVN. */
22518 case T2_OPCODE_ORR
:
22519 new_inst
= T2_OPCODE_ORN
;
22523 case T2_OPCODE_ORN
:
22524 new_inst
= T2_OPCODE_ORR
;
22528 /* AND <-> BIC. TST has no inverted equivalent. */
22529 case T2_OPCODE_AND
:
22530 new_inst
= T2_OPCODE_BIC
;
22537 case T2_OPCODE_BIC
:
22538 new_inst
= T2_OPCODE_AND
;
22543 case T2_OPCODE_ADC
:
22544 new_inst
= T2_OPCODE_SBC
;
22548 case T2_OPCODE_SBC
:
22549 new_inst
= T2_OPCODE_ADC
;
22553 /* We cannot do anything. */
22558 if (value
== (unsigned int)FAIL
)
22561 *instruction
&= T2_OPCODE_MASK
;
22562 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22566 /* Read a 32-bit thumb instruction from buf. */
22567 static unsigned long
22568 get_thumb32_insn (char * buf
)
22570 unsigned long insn
;
22571 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22572 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22578 /* We usually want to set the low bit on the address of thumb function
22579 symbols. In particular .word foo - . should have the low bit set.
22580 Generic code tries to fold the difference of two symbols to
22581 a constant. Prevent this and force a relocation when the first symbols
22582 is a thumb function. */
22585 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22587 if (op
== O_subtract
22588 && l
->X_op
== O_symbol
22589 && r
->X_op
== O_symbol
22590 && THUMB_IS_FUNC (l
->X_add_symbol
))
22592 l
->X_op
= O_subtract
;
22593 l
->X_op_symbol
= r
->X_add_symbol
;
22594 l
->X_add_number
-= r
->X_add_number
;
22598 /* Process as normal. */
22602 /* Encode Thumb2 unconditional branches and calls. The encoding
22603 for the 2 are identical for the immediate values. */
22606 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22608 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22611 addressT S
, I1
, I2
, lo
, hi
;
22613 S
= (value
>> 24) & 0x01;
22614 I1
= (value
>> 23) & 0x01;
22615 I2
= (value
>> 22) & 0x01;
22616 hi
= (value
>> 12) & 0x3ff;
22617 lo
= (value
>> 1) & 0x7ff;
22618 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22619 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22620 newval
|= (S
<< 10) | hi
;
22621 newval2
&= ~T2I1I2MASK
;
22622 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22623 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22624 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22628 md_apply_fix (fixS
* fixP
,
22632 offsetT value
= * valP
;
22634 unsigned int newimm
;
22635 unsigned long temp
;
22637 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22639 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22641 /* Note whether this will delete the relocation. */
22643 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22646 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22647 consistency with the behaviour on 32-bit hosts. Remember value
22649 value
&= 0xffffffff;
22650 value
^= 0x80000000;
22651 value
-= 0x80000000;
22654 fixP
->fx_addnumber
= value
;
22656 /* Same treatment for fixP->fx_offset. */
22657 fixP
->fx_offset
&= 0xffffffff;
22658 fixP
->fx_offset
^= 0x80000000;
22659 fixP
->fx_offset
-= 0x80000000;
22661 switch (fixP
->fx_r_type
)
22663 case BFD_RELOC_NONE
:
22664 /* This will need to go in the object file. */
22668 case BFD_RELOC_ARM_IMMEDIATE
:
22669 /* We claim that this fixup has been processed here,
22670 even if in fact we generate an error because we do
22671 not have a reloc for it, so tc_gen_reloc will reject it. */
22674 if (fixP
->fx_addsy
)
22676 const char *msg
= 0;
22678 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22679 msg
= _("undefined symbol %s used as an immediate value");
22680 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22681 msg
= _("symbol %s is in a different section");
22682 else if (S_IS_WEAK (fixP
->fx_addsy
))
22683 msg
= _("symbol %s is weak and may be overridden later");
22687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22688 msg
, S_GET_NAME (fixP
->fx_addsy
));
22693 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22695 /* If the offset is negative, we should use encoding A2 for ADR. */
22696 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22697 newimm
= negate_data_op (&temp
, value
);
22700 newimm
= encode_arm_immediate (value
);
22702 /* If the instruction will fail, see if we can fix things up by
22703 changing the opcode. */
22704 if (newimm
== (unsigned int) FAIL
)
22705 newimm
= negate_data_op (&temp
, value
);
22708 if (newimm
== (unsigned int) FAIL
)
22710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22711 _("invalid constant (%lx) after fixup"),
22712 (unsigned long) value
);
22716 newimm
|= (temp
& 0xfffff000);
22717 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22720 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22722 unsigned int highpart
= 0;
22723 unsigned int newinsn
= 0xe1a00000; /* nop. */
22725 if (fixP
->fx_addsy
)
22727 const char *msg
= 0;
22729 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22730 msg
= _("undefined symbol %s used as an immediate value");
22731 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22732 msg
= _("symbol %s is in a different section");
22733 else if (S_IS_WEAK (fixP
->fx_addsy
))
22734 msg
= _("symbol %s is weak and may be overridden later");
22738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22739 msg
, S_GET_NAME (fixP
->fx_addsy
));
22744 newimm
= encode_arm_immediate (value
);
22745 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22747 /* If the instruction will fail, see if we can fix things up by
22748 changing the opcode. */
22749 if (newimm
== (unsigned int) FAIL
22750 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22752 /* No ? OK - try using two ADD instructions to generate
22754 newimm
= validate_immediate_twopart (value
, & highpart
);
22756 /* Yes - then make sure that the second instruction is
22758 if (newimm
!= (unsigned int) FAIL
)
22760 /* Still No ? Try using a negated value. */
22761 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22762 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22763 /* Otherwise - give up. */
22766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22767 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22772 /* Replace the first operand in the 2nd instruction (which
22773 is the PC) with the destination register. We have
22774 already added in the PC in the first instruction and we
22775 do not want to do it again. */
22776 newinsn
&= ~ 0xf0000;
22777 newinsn
|= ((newinsn
& 0x0f000) << 4);
22780 newimm
|= (temp
& 0xfffff000);
22781 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22783 highpart
|= (newinsn
& 0xfffff000);
22784 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22788 case BFD_RELOC_ARM_OFFSET_IMM
:
22789 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22792 case BFD_RELOC_ARM_LITERAL
:
22798 if (validate_offset_imm (value
, 0) == FAIL
)
22800 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22802 _("invalid literal constant: pool needs to be closer"));
22804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22805 _("bad immediate value for offset (%ld)"),
22810 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22812 newval
&= 0xfffff000;
22815 newval
&= 0xff7ff000;
22816 newval
|= value
| (sign
? INDEX_UP
: 0);
22818 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22821 case BFD_RELOC_ARM_OFFSET_IMM8
:
22822 case BFD_RELOC_ARM_HWLITERAL
:
22828 if (validate_offset_imm (value
, 1) == FAIL
)
22830 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22832 _("invalid literal constant: pool needs to be closer"));
22834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22835 _("bad immediate value for 8-bit offset (%ld)"),
22840 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22842 newval
&= 0xfffff0f0;
22845 newval
&= 0xff7ff0f0;
22846 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22848 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22851 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22852 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22854 _("bad immediate value for offset (%ld)"), (long) value
);
22857 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22859 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22862 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22863 /* This is a complicated relocation used for all varieties of Thumb32
22864 load/store instruction with immediate offset:
22866 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22867 *4, optional writeback(W)
22868 (doubleword load/store)
22870 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22871 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22872 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22873 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22874 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22876 Uppercase letters indicate bits that are already encoded at
22877 this point. Lowercase letters are our problem. For the
22878 second block of instructions, the secondary opcode nybble
22879 (bits 8..11) is present, and bit 23 is zero, even if this is
22880 a PC-relative operation. */
22881 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22883 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22885 if ((newval
& 0xf0000000) == 0xe0000000)
22887 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22889 newval
|= (1 << 23);
22892 if (value
% 4 != 0)
22894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22895 _("offset not a multiple of 4"));
22901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22902 _("offset out of range"));
22907 else if ((newval
& 0x000f0000) == 0x000f0000)
22909 /* PC-relative, 12-bit offset. */
22911 newval
|= (1 << 23);
22916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22917 _("offset out of range"));
22922 else if ((newval
& 0x00000100) == 0x00000100)
22924 /* Writeback: 8-bit, +/- offset. */
22926 newval
|= (1 << 9);
22931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22932 _("offset out of range"));
22937 else if ((newval
& 0x00000f00) == 0x00000e00)
22939 /* T-instruction: positive 8-bit offset. */
22940 if (value
< 0 || value
> 0xff)
22942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22943 _("offset out of range"));
22951 /* Positive 12-bit or negative 8-bit offset. */
22955 newval
|= (1 << 23);
22965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22966 _("offset out of range"));
22973 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22974 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22977 case BFD_RELOC_ARM_SHIFT_IMM
:
22978 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22979 if (((unsigned long) value
) > 32
22981 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22984 _("shift expression is too large"));
22989 /* Shifts of zero must be done as lsl. */
22991 else if (value
== 32)
22993 newval
&= 0xfffff07f;
22994 newval
|= (value
& 0x1f) << 7;
22995 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22998 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22999 case BFD_RELOC_ARM_T32_ADD_IMM
:
23000 case BFD_RELOC_ARM_T32_IMM12
:
23001 case BFD_RELOC_ARM_T32_ADD_PC12
:
23002 /* We claim that this fixup has been processed here,
23003 even if in fact we generate an error because we do
23004 not have a reloc for it, so tc_gen_reloc will reject it. */
23008 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23011 _("undefined symbol %s used as an immediate value"),
23012 S_GET_NAME (fixP
->fx_addsy
));
23016 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23018 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23021 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23022 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23024 newimm
= encode_thumb32_immediate (value
);
23025 if (newimm
== (unsigned int) FAIL
)
23026 newimm
= thumb32_negate_data_op (&newval
, value
);
23028 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23029 && newimm
== (unsigned int) FAIL
)
23031 /* Turn add/sum into addw/subw. */
23032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23033 newval
= (newval
& 0xfeffffff) | 0x02000000;
23034 /* No flat 12-bit imm encoding for addsw/subsw. */
23035 if ((newval
& 0x00100000) == 0)
23037 /* 12 bit immediate for addw/subw. */
23041 newval
^= 0x00a00000;
23044 newimm
= (unsigned int) FAIL
;
23050 if (newimm
== (unsigned int)FAIL
)
23052 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23053 _("invalid constant (%lx) after fixup"),
23054 (unsigned long) value
);
23058 newval
|= (newimm
& 0x800) << 15;
23059 newval
|= (newimm
& 0x700) << 4;
23060 newval
|= (newimm
& 0x0ff);
23062 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23063 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23066 case BFD_RELOC_ARM_SMC
:
23067 if (((unsigned long) value
) > 0xffff)
23068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23069 _("invalid smc expression"));
23070 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23071 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23072 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23075 case BFD_RELOC_ARM_HVC
:
23076 if (((unsigned long) value
) > 0xffff)
23077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23078 _("invalid hvc expression"));
23079 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23080 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23081 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23084 case BFD_RELOC_ARM_SWI
:
23085 if (fixP
->tc_fix_data
!= 0)
23087 if (((unsigned long) value
) > 0xff)
23088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23089 _("invalid swi expression"));
23090 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23092 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23096 if (((unsigned long) value
) > 0x00ffffff)
23097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23098 _("invalid swi expression"));
23099 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23101 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23105 case BFD_RELOC_ARM_MULTI
:
23106 if (((unsigned long) value
) > 0xffff)
23107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23108 _("invalid expression in load/store multiple"));
23109 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23110 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23114 case BFD_RELOC_ARM_PCREL_CALL
:
23116 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23118 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23119 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23120 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23121 /* Flip the bl to blx. This is a simple flip
23122 bit here because we generate PCREL_CALL for
23123 unconditional bls. */
23125 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23126 newval
= newval
| 0x10000000;
23127 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23133 goto arm_branch_common
;
23135 case BFD_RELOC_ARM_PCREL_JUMP
:
23136 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23138 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23139 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23140 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23142 /* This would map to a bl<cond>, b<cond>,
23143 b<always> to a Thumb function. We
23144 need to force a relocation for this particular
23146 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23150 case BFD_RELOC_ARM_PLT32
:
23152 case BFD_RELOC_ARM_PCREL_BRANCH
:
23154 goto arm_branch_common
;
23156 case BFD_RELOC_ARM_PCREL_BLX
:
23159 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23161 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23162 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23163 && ARM_IS_FUNC (fixP
->fx_addsy
))
23165 /* Flip the blx to a bl and warn. */
23166 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23167 newval
= 0xeb000000;
23168 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23169 _("blx to '%s' an ARM ISA state function changed to bl"),
23171 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23177 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23178 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23182 /* We are going to store value (shifted right by two) in the
23183 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23184 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23185 also be be clear. */
23187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23188 _("misaligned branch destination"));
23189 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23190 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23193 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23195 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23196 newval
|= (value
>> 2) & 0x00ffffff;
23197 /* Set the H bit on BLX instructions. */
23201 newval
|= 0x01000000;
23203 newval
&= ~0x01000000;
23205 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23209 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23210 /* CBZ can only branch forward. */
23212 /* Attempts to use CBZ to branch to the next instruction
23213 (which, strictly speaking, are prohibited) will be turned into
23216 FIXME: It may be better to remove the instruction completely and
23217 perform relaxation. */
23220 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23221 newval
= 0xbf00; /* NOP encoding T1 */
23222 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23229 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23231 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23232 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23233 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23238 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23239 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23242 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23244 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23245 newval
|= (value
& 0x1ff) >> 1;
23246 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23250 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23251 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23254 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23256 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23257 newval
|= (value
& 0xfff) >> 1;
23258 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23262 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23264 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23265 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23266 && ARM_IS_FUNC (fixP
->fx_addsy
)
23267 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23269 /* Force a relocation for a branch 20 bits wide. */
23272 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23274 _("conditional branch out of range"));
23276 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23279 addressT S
, J1
, J2
, lo
, hi
;
23281 S
= (value
& 0x00100000) >> 20;
23282 J2
= (value
& 0x00080000) >> 19;
23283 J1
= (value
& 0x00040000) >> 18;
23284 hi
= (value
& 0x0003f000) >> 12;
23285 lo
= (value
& 0x00000ffe) >> 1;
23287 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23288 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23289 newval
|= (S
<< 10) | hi
;
23290 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23291 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23292 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23296 case BFD_RELOC_THUMB_PCREL_BLX
:
23297 /* If there is a blx from a thumb state function to
23298 another thumb function flip this to a bl and warn
23302 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23303 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23304 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23306 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23307 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23308 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23310 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23311 newval
= newval
| 0x1000;
23312 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23313 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23318 goto thumb_bl_common
;
23320 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23321 /* A bl from Thumb state ISA to an internal ARM state function
23322 is converted to a blx. */
23324 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23325 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23326 && ARM_IS_FUNC (fixP
->fx_addsy
)
23327 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23329 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23330 newval
= newval
& ~0x1000;
23331 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23332 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23338 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23339 /* For a BLX instruction, make sure that the relocation is rounded up
23340 to a word boundary. This follows the semantics of the instruction
23341 which specifies that bit 1 of the target address will come from bit
23342 1 of the base address. */
23343 value
= (value
+ 3) & ~ 3;
23346 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23347 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23348 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23351 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23353 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23355 else if ((value
& ~0x1ffffff)
23356 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23358 _("Thumb2 branch out of range"));
23361 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23362 encode_thumb2_b_bl_offset (buf
, value
);
23366 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23367 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23370 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23371 encode_thumb2_b_bl_offset (buf
, value
);
23376 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23381 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23382 md_number_to_chars (buf
, value
, 2);
23386 case BFD_RELOC_ARM_TLS_CALL
:
23387 case BFD_RELOC_ARM_THM_TLS_CALL
:
23388 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23389 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23390 case BFD_RELOC_ARM_TLS_GOTDESC
:
23391 case BFD_RELOC_ARM_TLS_GD32
:
23392 case BFD_RELOC_ARM_TLS_LE32
:
23393 case BFD_RELOC_ARM_TLS_IE32
:
23394 case BFD_RELOC_ARM_TLS_LDM32
:
23395 case BFD_RELOC_ARM_TLS_LDO32
:
23396 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23399 case BFD_RELOC_ARM_GOT32
:
23400 case BFD_RELOC_ARM_GOTOFF
:
23403 case BFD_RELOC_ARM_GOT_PREL
:
23404 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23405 md_number_to_chars (buf
, value
, 4);
23408 case BFD_RELOC_ARM_TARGET2
:
23409 /* TARGET2 is not partial-inplace, so we need to write the
23410 addend here for REL targets, because it won't be written out
23411 during reloc processing later. */
23412 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23413 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23417 case BFD_RELOC_RVA
:
23419 case BFD_RELOC_ARM_TARGET1
:
23420 case BFD_RELOC_ARM_ROSEGREL32
:
23421 case BFD_RELOC_ARM_SBREL32
:
23422 case BFD_RELOC_32_PCREL
:
23424 case BFD_RELOC_32_SECREL
:
23426 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23428 /* For WinCE we only do this for pcrel fixups. */
23429 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23431 md_number_to_chars (buf
, value
, 4);
23435 case BFD_RELOC_ARM_PREL31
:
23436 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23438 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23439 if ((value
^ (value
>> 1)) & 0x40000000)
23441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23442 _("rel31 relocation overflow"));
23444 newval
|= value
& 0x7fffffff;
23445 md_number_to_chars (buf
, newval
, 4);
23450 case BFD_RELOC_ARM_CP_OFF_IMM
:
23451 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23452 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23453 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23455 newval
= get_thumb32_insn (buf
);
23456 if ((newval
& 0x0f200f00) == 0x0d000900)
23458 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23459 has permitted values that are multiples of 2, in the range 0
23461 if (value
< -510 || value
> 510 || (value
& 1))
23462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23463 _("co-processor offset out of range"));
23465 else if (value
< -1023 || value
> 1023 || (value
& 3))
23466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23467 _("co-processor offset out of range"));
23472 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23473 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23474 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23476 newval
= get_thumb32_insn (buf
);
23478 newval
&= 0xffffff00;
23481 newval
&= 0xff7fff00;
23482 if ((newval
& 0x0f200f00) == 0x0d000900)
23484 /* This is a fp16 vstr/vldr.
23486 It requires the immediate offset in the instruction is shifted
23487 left by 1 to be a half-word offset.
23489 Here, left shift by 1 first, and later right shift by 2
23490 should get the right offset. */
23493 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23495 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23496 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23497 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23499 put_thumb32_insn (buf
, newval
);
23502 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23503 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23504 if (value
< -255 || value
> 255)
23505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23506 _("co-processor offset out of range"));
23508 goto cp_off_common
;
23510 case BFD_RELOC_ARM_THUMB_OFFSET
:
23511 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23512 /* Exactly what ranges, and where the offset is inserted depends
23513 on the type of instruction, we can establish this from the
23515 switch (newval
>> 12)
23517 case 4: /* PC load. */
23518 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23519 forced to zero for these loads; md_pcrel_from has already
23520 compensated for this. */
23522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23523 _("invalid offset, target not word aligned (0x%08lX)"),
23524 (((unsigned long) fixP
->fx_frag
->fr_address
23525 + (unsigned long) fixP
->fx_where
) & ~3)
23526 + (unsigned long) value
);
23528 if (value
& ~0x3fc)
23529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23530 _("invalid offset, value too big (0x%08lX)"),
23533 newval
|= value
>> 2;
23536 case 9: /* SP load/store. */
23537 if (value
& ~0x3fc)
23538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23539 _("invalid offset, value too big (0x%08lX)"),
23541 newval
|= value
>> 2;
23544 case 6: /* Word load/store. */
23546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23547 _("invalid offset, value too big (0x%08lX)"),
23549 newval
|= value
<< 4; /* 6 - 2. */
23552 case 7: /* Byte load/store. */
23554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23555 _("invalid offset, value too big (0x%08lX)"),
23557 newval
|= value
<< 6;
23560 case 8: /* Halfword load/store. */
23562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23563 _("invalid offset, value too big (0x%08lX)"),
23565 newval
|= value
<< 5; /* 6 - 1. */
23569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23570 "Unable to process relocation for thumb opcode: %lx",
23571 (unsigned long) newval
);
23574 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23577 case BFD_RELOC_ARM_THUMB_ADD
:
23578 /* This is a complicated relocation, since we use it for all of
23579 the following immediate relocations:
23583 9bit ADD/SUB SP word-aligned
23584 10bit ADD PC/SP word-aligned
23586 The type of instruction being processed is encoded in the
23593 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23595 int rd
= (newval
>> 4) & 0xf;
23596 int rs
= newval
& 0xf;
23597 int subtract
= !!(newval
& 0x8000);
23599 /* Check for HI regs, only very restricted cases allowed:
23600 Adjusting SP, and using PC or SP to get an address. */
23601 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23602 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23604 _("invalid Hi register with immediate"));
23606 /* If value is negative, choose the opposite instruction. */
23610 subtract
= !subtract
;
23612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23613 _("immediate value out of range"));
23618 if (value
& ~0x1fc)
23619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23620 _("invalid immediate for stack address calculation"));
23621 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23622 newval
|= value
>> 2;
23624 else if (rs
== REG_PC
|| rs
== REG_SP
)
23626 /* PR gas/18541. If the addition is for a defined symbol
23627 within range of an ADR instruction then accept it. */
23630 && fixP
->fx_addsy
!= NULL
)
23634 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23635 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23636 || S_IS_WEAK (fixP
->fx_addsy
))
23638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23639 _("address calculation needs a strongly defined nearby symbol"));
23643 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23645 /* Round up to the next 4-byte boundary. */
23650 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23655 _("symbol too far away"));
23665 if (subtract
|| value
& ~0x3fc)
23666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23667 _("invalid immediate for address calculation (value = 0x%08lX)"),
23668 (unsigned long) (subtract
? - value
: value
));
23669 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23671 newval
|= value
>> 2;
23676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23677 _("immediate value out of range"));
23678 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23679 newval
|= (rd
<< 8) | value
;
23684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23685 _("immediate value out of range"));
23686 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23687 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23690 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23693 case BFD_RELOC_ARM_THUMB_IMM
:
23694 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23695 if (value
< 0 || value
> 255)
23696 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23697 _("invalid immediate: %ld is out of range"),
23700 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23703 case BFD_RELOC_ARM_THUMB_SHIFT
:
23704 /* 5bit shift value (0..32). LSL cannot take 32. */
23705 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23706 temp
= newval
& 0xf800;
23707 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23709 _("invalid shift value: %ld"), (long) value
);
23710 /* Shifts of zero must be encoded as LSL. */
23712 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23713 /* Shifts of 32 are encoded as zero. */
23714 else if (value
== 32)
23716 newval
|= value
<< 6;
23717 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23720 case BFD_RELOC_VTABLE_INHERIT
:
23721 case BFD_RELOC_VTABLE_ENTRY
:
23725 case BFD_RELOC_ARM_MOVW
:
23726 case BFD_RELOC_ARM_MOVT
:
23727 case BFD_RELOC_ARM_THUMB_MOVW
:
23728 case BFD_RELOC_ARM_THUMB_MOVT
:
23729 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23731 /* REL format relocations are limited to a 16-bit addend. */
23732 if (!fixP
->fx_done
)
23734 if (value
< -0x8000 || value
> 0x7fff)
23735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23736 _("offset out of range"));
23738 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23739 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23744 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23745 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23747 newval
= get_thumb32_insn (buf
);
23748 newval
&= 0xfbf08f00;
23749 newval
|= (value
& 0xf000) << 4;
23750 newval
|= (value
& 0x0800) << 15;
23751 newval
|= (value
& 0x0700) << 4;
23752 newval
|= (value
& 0x00ff);
23753 put_thumb32_insn (buf
, newval
);
23757 newval
= md_chars_to_number (buf
, 4);
23758 newval
&= 0xfff0f000;
23759 newval
|= value
& 0x0fff;
23760 newval
|= (value
& 0xf000) << 4;
23761 md_number_to_chars (buf
, newval
, 4);
23766 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23767 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23768 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23769 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23770 gas_assert (!fixP
->fx_done
);
23773 bfd_boolean is_mov
;
23774 bfd_vma encoded_addend
= value
;
23776 /* Check that addend can be encoded in instruction. */
23777 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23779 _("the offset 0x%08lX is not representable"),
23780 (unsigned long) encoded_addend
);
23782 /* Extract the instruction. */
23783 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23784 is_mov
= (insn
& 0xf800) == 0x2000;
23789 if (!seg
->use_rela_p
)
23790 insn
|= encoded_addend
;
23796 /* Extract the instruction. */
23797 /* Encoding is the following
23802 /* The following conditions must be true :
23807 rd
= (insn
>> 4) & 0xf;
23809 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23811 _("Unable to process relocation for thumb opcode: %lx"),
23812 (unsigned long) insn
);
23814 /* Encode as ADD immediate8 thumb 1 code. */
23815 insn
= 0x3000 | (rd
<< 8);
23817 /* Place the encoded addend into the first 8 bits of the
23819 if (!seg
->use_rela_p
)
23820 insn
|= encoded_addend
;
23823 /* Update the instruction. */
23824 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23828 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23829 case BFD_RELOC_ARM_ALU_PC_G0
:
23830 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23831 case BFD_RELOC_ARM_ALU_PC_G1
:
23832 case BFD_RELOC_ARM_ALU_PC_G2
:
23833 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23834 case BFD_RELOC_ARM_ALU_SB_G0
:
23835 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23836 case BFD_RELOC_ARM_ALU_SB_G1
:
23837 case BFD_RELOC_ARM_ALU_SB_G2
:
23838 gas_assert (!fixP
->fx_done
);
23839 if (!seg
->use_rela_p
)
23842 bfd_vma encoded_addend
;
23843 bfd_vma addend_abs
= abs (value
);
23845 /* Check that the absolute value of the addend can be
23846 expressed as an 8-bit constant plus a rotation. */
23847 encoded_addend
= encode_arm_immediate (addend_abs
);
23848 if (encoded_addend
== (unsigned int) FAIL
)
23849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23850 _("the offset 0x%08lX is not representable"),
23851 (unsigned long) addend_abs
);
23853 /* Extract the instruction. */
23854 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23856 /* If the addend is positive, use an ADD instruction.
23857 Otherwise use a SUB. Take care not to destroy the S bit. */
23858 insn
&= 0xff1fffff;
23864 /* Place the encoded addend into the first 12 bits of the
23866 insn
&= 0xfffff000;
23867 insn
|= encoded_addend
;
23869 /* Update the instruction. */
23870 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23874 case BFD_RELOC_ARM_LDR_PC_G0
:
23875 case BFD_RELOC_ARM_LDR_PC_G1
:
23876 case BFD_RELOC_ARM_LDR_PC_G2
:
23877 case BFD_RELOC_ARM_LDR_SB_G0
:
23878 case BFD_RELOC_ARM_LDR_SB_G1
:
23879 case BFD_RELOC_ARM_LDR_SB_G2
:
23880 gas_assert (!fixP
->fx_done
);
23881 if (!seg
->use_rela_p
)
23884 bfd_vma addend_abs
= abs (value
);
23886 /* Check that the absolute value of the addend can be
23887 encoded in 12 bits. */
23888 if (addend_abs
>= 0x1000)
23889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23890 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23891 (unsigned long) addend_abs
);
23893 /* Extract the instruction. */
23894 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23896 /* If the addend is negative, clear bit 23 of the instruction.
23897 Otherwise set it. */
23899 insn
&= ~(1 << 23);
23903 /* Place the absolute value of the addend into the first 12 bits
23904 of the instruction. */
23905 insn
&= 0xfffff000;
23906 insn
|= addend_abs
;
23908 /* Update the instruction. */
23909 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23913 case BFD_RELOC_ARM_LDRS_PC_G0
:
23914 case BFD_RELOC_ARM_LDRS_PC_G1
:
23915 case BFD_RELOC_ARM_LDRS_PC_G2
:
23916 case BFD_RELOC_ARM_LDRS_SB_G0
:
23917 case BFD_RELOC_ARM_LDRS_SB_G1
:
23918 case BFD_RELOC_ARM_LDRS_SB_G2
:
23919 gas_assert (!fixP
->fx_done
);
23920 if (!seg
->use_rela_p
)
23923 bfd_vma addend_abs
= abs (value
);
23925 /* Check that the absolute value of the addend can be
23926 encoded in 8 bits. */
23927 if (addend_abs
>= 0x100)
23928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23929 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23930 (unsigned long) addend_abs
);
23932 /* Extract the instruction. */
23933 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23935 /* If the addend is negative, clear bit 23 of the instruction.
23936 Otherwise set it. */
23938 insn
&= ~(1 << 23);
23942 /* Place the first four bits of the absolute value of the addend
23943 into the first 4 bits of the instruction, and the remaining
23944 four into bits 8 .. 11. */
23945 insn
&= 0xfffff0f0;
23946 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23948 /* Update the instruction. */
23949 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23953 case BFD_RELOC_ARM_LDC_PC_G0
:
23954 case BFD_RELOC_ARM_LDC_PC_G1
:
23955 case BFD_RELOC_ARM_LDC_PC_G2
:
23956 case BFD_RELOC_ARM_LDC_SB_G0
:
23957 case BFD_RELOC_ARM_LDC_SB_G1
:
23958 case BFD_RELOC_ARM_LDC_SB_G2
:
23959 gas_assert (!fixP
->fx_done
);
23960 if (!seg
->use_rela_p
)
23963 bfd_vma addend_abs
= abs (value
);
23965 /* Check that the absolute value of the addend is a multiple of
23966 four and, when divided by four, fits in 8 bits. */
23967 if (addend_abs
& 0x3)
23968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23969 _("bad offset 0x%08lX (must be word-aligned)"),
23970 (unsigned long) addend_abs
);
23972 if ((addend_abs
>> 2) > 0xff)
23973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23974 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23975 (unsigned long) addend_abs
);
23977 /* Extract the instruction. */
23978 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23980 /* If the addend is negative, clear bit 23 of the instruction.
23981 Otherwise set it. */
23983 insn
&= ~(1 << 23);
23987 /* Place the addend (divided by four) into the first eight
23988 bits of the instruction. */
23989 insn
&= 0xfffffff0;
23990 insn
|= addend_abs
>> 2;
23992 /* Update the instruction. */
23993 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23997 case BFD_RELOC_ARM_V4BX
:
23998 /* This will need to go in the object file. */
24002 case BFD_RELOC_UNUSED
:
24004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24005 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24009 /* Translate internal representation of relocation info to BFD target
24013 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24016 bfd_reloc_code_real_type code
;
24018 reloc
= XNEW (arelent
);
24020 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24021 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24022 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24024 if (fixp
->fx_pcrel
)
24026 if (section
->use_rela_p
)
24027 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24029 fixp
->fx_offset
= reloc
->address
;
24031 reloc
->addend
= fixp
->fx_offset
;
24033 switch (fixp
->fx_r_type
)
24036 if (fixp
->fx_pcrel
)
24038 code
= BFD_RELOC_8_PCREL
;
24043 if (fixp
->fx_pcrel
)
24045 code
= BFD_RELOC_16_PCREL
;
24050 if (fixp
->fx_pcrel
)
24052 code
= BFD_RELOC_32_PCREL
;
24056 case BFD_RELOC_ARM_MOVW
:
24057 if (fixp
->fx_pcrel
)
24059 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24063 case BFD_RELOC_ARM_MOVT
:
24064 if (fixp
->fx_pcrel
)
24066 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24070 case BFD_RELOC_ARM_THUMB_MOVW
:
24071 if (fixp
->fx_pcrel
)
24073 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24077 case BFD_RELOC_ARM_THUMB_MOVT
:
24078 if (fixp
->fx_pcrel
)
24080 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24084 case BFD_RELOC_NONE
:
24085 case BFD_RELOC_ARM_PCREL_BRANCH
:
24086 case BFD_RELOC_ARM_PCREL_BLX
:
24087 case BFD_RELOC_RVA
:
24088 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24089 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24090 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24091 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24092 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24093 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24094 case BFD_RELOC_VTABLE_ENTRY
:
24095 case BFD_RELOC_VTABLE_INHERIT
:
24097 case BFD_RELOC_32_SECREL
:
24099 code
= fixp
->fx_r_type
;
24102 case BFD_RELOC_THUMB_PCREL_BLX
:
24104 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24105 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24108 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24111 case BFD_RELOC_ARM_LITERAL
:
24112 case BFD_RELOC_ARM_HWLITERAL
:
24113 /* If this is called then the a literal has
24114 been referenced across a section boundary. */
24115 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24116 _("literal referenced across section boundary"));
24120 case BFD_RELOC_ARM_TLS_CALL
:
24121 case BFD_RELOC_ARM_THM_TLS_CALL
:
24122 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24123 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24124 case BFD_RELOC_ARM_GOT32
:
24125 case BFD_RELOC_ARM_GOTOFF
:
24126 case BFD_RELOC_ARM_GOT_PREL
:
24127 case BFD_RELOC_ARM_PLT32
:
24128 case BFD_RELOC_ARM_TARGET1
:
24129 case BFD_RELOC_ARM_ROSEGREL32
:
24130 case BFD_RELOC_ARM_SBREL32
:
24131 case BFD_RELOC_ARM_PREL31
:
24132 case BFD_RELOC_ARM_TARGET2
:
24133 case BFD_RELOC_ARM_TLS_LDO32
:
24134 case BFD_RELOC_ARM_PCREL_CALL
:
24135 case BFD_RELOC_ARM_PCREL_JUMP
:
24136 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24137 case BFD_RELOC_ARM_ALU_PC_G0
:
24138 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24139 case BFD_RELOC_ARM_ALU_PC_G1
:
24140 case BFD_RELOC_ARM_ALU_PC_G2
:
24141 case BFD_RELOC_ARM_LDR_PC_G0
:
24142 case BFD_RELOC_ARM_LDR_PC_G1
:
24143 case BFD_RELOC_ARM_LDR_PC_G2
:
24144 case BFD_RELOC_ARM_LDRS_PC_G0
:
24145 case BFD_RELOC_ARM_LDRS_PC_G1
:
24146 case BFD_RELOC_ARM_LDRS_PC_G2
:
24147 case BFD_RELOC_ARM_LDC_PC_G0
:
24148 case BFD_RELOC_ARM_LDC_PC_G1
:
24149 case BFD_RELOC_ARM_LDC_PC_G2
:
24150 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24151 case BFD_RELOC_ARM_ALU_SB_G0
:
24152 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24153 case BFD_RELOC_ARM_ALU_SB_G1
:
24154 case BFD_RELOC_ARM_ALU_SB_G2
:
24155 case BFD_RELOC_ARM_LDR_SB_G0
:
24156 case BFD_RELOC_ARM_LDR_SB_G1
:
24157 case BFD_RELOC_ARM_LDR_SB_G2
:
24158 case BFD_RELOC_ARM_LDRS_SB_G0
:
24159 case BFD_RELOC_ARM_LDRS_SB_G1
:
24160 case BFD_RELOC_ARM_LDRS_SB_G2
:
24161 case BFD_RELOC_ARM_LDC_SB_G0
:
24162 case BFD_RELOC_ARM_LDC_SB_G1
:
24163 case BFD_RELOC_ARM_LDC_SB_G2
:
24164 case BFD_RELOC_ARM_V4BX
:
24165 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24166 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24167 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24168 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24169 code
= fixp
->fx_r_type
;
24172 case BFD_RELOC_ARM_TLS_GOTDESC
:
24173 case BFD_RELOC_ARM_TLS_GD32
:
24174 case BFD_RELOC_ARM_TLS_LE32
:
24175 case BFD_RELOC_ARM_TLS_IE32
:
24176 case BFD_RELOC_ARM_TLS_LDM32
:
24177 /* BFD will include the symbol's address in the addend.
24178 But we don't want that, so subtract it out again here. */
24179 if (!S_IS_COMMON (fixp
->fx_addsy
))
24180 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24181 code
= fixp
->fx_r_type
;
24185 case BFD_RELOC_ARM_IMMEDIATE
:
24186 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24187 _("internal relocation (type: IMMEDIATE) not fixed up"));
24190 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24192 _("ADRL used for a symbol not defined in the same file"));
24195 case BFD_RELOC_ARM_OFFSET_IMM
:
24196 if (section
->use_rela_p
)
24198 code
= fixp
->fx_r_type
;
24202 if (fixp
->fx_addsy
!= NULL
24203 && !S_IS_DEFINED (fixp
->fx_addsy
)
24204 && S_IS_LOCAL (fixp
->fx_addsy
))
24206 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24207 _("undefined local label `%s'"),
24208 S_GET_NAME (fixp
->fx_addsy
));
24212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24213 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24220 switch (fixp
->fx_r_type
)
24222 case BFD_RELOC_NONE
: type
= "NONE"; break;
24223 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24224 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24225 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24226 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24227 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24228 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24229 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24230 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24231 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24232 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24233 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24234 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24235 default: type
= _("<unknown>"); break;
24237 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24238 _("cannot represent %s relocation in this object file format"),
24245 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24247 && fixp
->fx_addsy
== GOT_symbol
)
24249 code
= BFD_RELOC_ARM_GOTPC
;
24250 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24254 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24256 if (reloc
->howto
== NULL
)
24258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24259 _("cannot represent %s relocation in this object file format"),
24260 bfd_get_reloc_code_name (code
));
24264 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24265 vtable entry to be used in the relocation's section offset. */
24266 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24267 reloc
->address
= fixp
->fx_offset
;
24272 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24275 cons_fix_new_arm (fragS
* frag
,
24279 bfd_reloc_code_real_type reloc
)
24284 FIXME: @@ Should look at CPU word size. */
24288 reloc
= BFD_RELOC_8
;
24291 reloc
= BFD_RELOC_16
;
24295 reloc
= BFD_RELOC_32
;
24298 reloc
= BFD_RELOC_64
;
24303 if (exp
->X_op
== O_secrel
)
24305 exp
->X_op
= O_symbol
;
24306 reloc
= BFD_RELOC_32_SECREL
;
24310 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24313 #if defined (OBJ_COFF)
24315 arm_validate_fix (fixS
* fixP
)
24317 /* If the destination of the branch is a defined symbol which does not have
24318 the THUMB_FUNC attribute, then we must be calling a function which has
24319 the (interfacearm) attribute. We look for the Thumb entry point to that
24320 function and change the branch to refer to that function instead. */
24321 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24322 && fixP
->fx_addsy
!= NULL
24323 && S_IS_DEFINED (fixP
->fx_addsy
)
24324 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24326 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24333 arm_force_relocation (struct fix
* fixp
)
24335 #if defined (OBJ_COFF) && defined (TE_PE)
24336 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24340 /* In case we have a call or a branch to a function in ARM ISA mode from
24341 a thumb function or vice-versa force the relocation. These relocations
24342 are cleared off for some cores that might have blx and simple transformations
24346 switch (fixp
->fx_r_type
)
24348 case BFD_RELOC_ARM_PCREL_JUMP
:
24349 case BFD_RELOC_ARM_PCREL_CALL
:
24350 case BFD_RELOC_THUMB_PCREL_BLX
:
24351 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24355 case BFD_RELOC_ARM_PCREL_BLX
:
24356 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24357 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24358 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24359 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24368 /* Resolve these relocations even if the symbol is extern or weak.
24369 Technically this is probably wrong due to symbol preemption.
24370 In practice these relocations do not have enough range to be useful
24371 at dynamic link time, and some code (e.g. in the Linux kernel)
24372 expects these references to be resolved. */
24373 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24374 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24375 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24376 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24377 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24378 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24379 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24385 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24386 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24389 /* Always leave these relocations for the linker. */
24390 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24391 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24392 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24395 /* Always generate relocations against function symbols. */
24396 if (fixp
->fx_r_type
== BFD_RELOC_32
24398 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24401 return generic_force_reloc (fixp
);
24404 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24405 /* Relocations against function names must be left unadjusted,
24406 so that the linker can use this information to generate interworking
24407 stubs. The MIPS version of this function
24408 also prevents relocations that are mips-16 specific, but I do not
24409 know why it does this.
24412 There is one other problem that ought to be addressed here, but
24413 which currently is not: Taking the address of a label (rather
24414 than a function) and then later jumping to that address. Such
24415 addresses also ought to have their bottom bit set (assuming that
24416 they reside in Thumb code), but at the moment they will not. */
24419 arm_fix_adjustable (fixS
* fixP
)
24421 if (fixP
->fx_addsy
== NULL
)
24424 /* Preserve relocations against symbols with function type. */
24425 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24428 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24429 && fixP
->fx_subsy
== NULL
)
24432 /* We need the symbol name for the VTABLE entries. */
24433 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24434 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24437 /* Don't allow symbols to be discarded on GOT related relocs. */
24438 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24439 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24440 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24448 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24449 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24450 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24451 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24454 /* Similarly for group relocations. */
24455 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24456 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24457 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24460 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24461 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24462 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24463 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24464 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24465 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24467 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24471 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24472 offsets, so keep these symbols. */
24473 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24474 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24479 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24483 elf32_arm_target_format (void)
24486 return (target_big_endian
24487 ? "elf32-bigarm-symbian"
24488 : "elf32-littlearm-symbian");
24489 #elif defined (TE_VXWORKS)
24490 return (target_big_endian
24491 ? "elf32-bigarm-vxworks"
24492 : "elf32-littlearm-vxworks");
24493 #elif defined (TE_NACL)
24494 return (target_big_endian
24495 ? "elf32-bigarm-nacl"
24496 : "elf32-littlearm-nacl");
24498 if (target_big_endian
)
24499 return "elf32-bigarm";
24501 return "elf32-littlearm";
24506 armelf_frob_symbol (symbolS
* symp
,
24509 elf_frob_symbol (symp
, puntp
);
24513 /* MD interface: Finalization. */
24518 literal_pool
* pool
;
24520 /* Ensure that all the IT blocks are properly closed. */
24521 check_it_blocks_finished ();
24523 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24525 /* Put it at the end of the relevant section. */
24526 subseg_set (pool
->section
, pool
->sub_section
);
24528 arm_elf_change_section ();
24535 /* Remove any excess mapping symbols generated for alignment frags in
24536 SEC. We may have created a mapping symbol before a zero byte
24537 alignment; remove it if there's a mapping symbol after the
24540 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24541 void *dummy ATTRIBUTE_UNUSED
)
24543 segment_info_type
*seginfo
= seg_info (sec
);
24546 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24549 for (fragp
= seginfo
->frchainP
->frch_root
;
24551 fragp
= fragp
->fr_next
)
24553 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24554 fragS
*next
= fragp
->fr_next
;
24556 /* Variable-sized frags have been converted to fixed size by
24557 this point. But if this was variable-sized to start with,
24558 there will be a fixed-size frag after it. So don't handle
24560 if (sym
== NULL
|| next
== NULL
)
24563 if (S_GET_VALUE (sym
) < next
->fr_address
)
24564 /* Not at the end of this frag. */
24566 know (S_GET_VALUE (sym
) == next
->fr_address
);
24570 if (next
->tc_frag_data
.first_map
!= NULL
)
24572 /* Next frag starts with a mapping symbol. Discard this
24574 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24578 if (next
->fr_next
== NULL
)
24580 /* This mapping symbol is at the end of the section. Discard
24582 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24583 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24587 /* As long as we have empty frags without any mapping symbols,
24589 /* If the next frag is non-empty and does not start with a
24590 mapping symbol, then this mapping symbol is required. */
24591 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24594 next
= next
->fr_next
;
24596 while (next
!= NULL
);
24601 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24605 arm_adjust_symtab (void)
24610 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24612 if (ARM_IS_THUMB (sym
))
24614 if (THUMB_IS_FUNC (sym
))
24616 /* Mark the symbol as a Thumb function. */
24617 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24618 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24619 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24621 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24622 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24624 as_bad (_("%s: unexpected function type: %d"),
24625 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24627 else switch (S_GET_STORAGE_CLASS (sym
))
24630 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24633 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24636 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24644 if (ARM_IS_INTERWORK (sym
))
24645 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24652 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24654 if (ARM_IS_THUMB (sym
))
24656 elf_symbol_type
* elf_sym
;
24658 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24659 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24661 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24662 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24664 /* If it's a .thumb_func, declare it as so,
24665 otherwise tag label as .code 16. */
24666 if (THUMB_IS_FUNC (sym
))
24667 elf_sym
->internal_elf_sym
.st_target_internal
24668 = ST_BRANCH_TO_THUMB
;
24669 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24670 elf_sym
->internal_elf_sym
.st_info
=
24671 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24676 /* Remove any overlapping mapping symbols generated by alignment frags. */
24677 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24678 /* Now do generic ELF adjustments. */
24679 elf_adjust_symtab ();
24683 /* MD interface: Initialization. */
24686 set_constant_flonums (void)
24690 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24691 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24695 /* Auto-select Thumb mode if it's the only available instruction set for the
24696 given architecture. */
24699 autoselect_thumb_from_cpu_variant (void)
24701 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24702 opcode_select (16);
24711 if ( (arm_ops_hsh
= hash_new ()) == NULL
24712 || (arm_cond_hsh
= hash_new ()) == NULL
24713 || (arm_shift_hsh
= hash_new ()) == NULL
24714 || (arm_psr_hsh
= hash_new ()) == NULL
24715 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24716 || (arm_reg_hsh
= hash_new ()) == NULL
24717 || (arm_reloc_hsh
= hash_new ()) == NULL
24718 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24719 as_fatal (_("virtual memory exhausted"));
24721 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24722 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24723 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24724 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24725 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24726 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24727 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24728 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24729 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24730 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24731 (void *) (v7m_psrs
+ i
));
24732 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24733 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24735 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24737 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24738 (void *) (barrier_opt_names
+ i
));
24740 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24742 struct reloc_entry
* entry
= reloc_names
+ i
;
24744 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24745 /* This makes encode_branch() use the EABI versions of this relocation. */
24746 entry
->reloc
= BFD_RELOC_UNUSED
;
24748 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24752 set_constant_flonums ();
24754 /* Set the cpu variant based on the command-line options. We prefer
24755 -mcpu= over -march= if both are set (as for GCC); and we prefer
24756 -mfpu= over any other way of setting the floating point unit.
24757 Use of legacy options with new options are faulted. */
24760 if (mcpu_cpu_opt
|| march_cpu_opt
)
24761 as_bad (_("use of old and new-style options to set CPU type"));
24763 mcpu_cpu_opt
= legacy_cpu
;
24765 else if (!mcpu_cpu_opt
)
24766 mcpu_cpu_opt
= march_cpu_opt
;
24771 as_bad (_("use of old and new-style options to set FPU type"));
24773 mfpu_opt
= legacy_fpu
;
24775 else if (!mfpu_opt
)
24777 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24778 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24779 /* Some environments specify a default FPU. If they don't, infer it
24780 from the processor. */
24782 mfpu_opt
= mcpu_fpu_opt
;
24784 mfpu_opt
= march_fpu_opt
;
24786 mfpu_opt
= &fpu_default
;
24792 if (mcpu_cpu_opt
!= NULL
)
24793 mfpu_opt
= &fpu_default
;
24794 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24795 mfpu_opt
= &fpu_arch_vfp_v2
;
24797 mfpu_opt
= &fpu_arch_fpa
;
24803 mcpu_cpu_opt
= &cpu_default
;
24804 selected_cpu
= cpu_default
;
24806 else if (no_cpu_selected ())
24807 selected_cpu
= cpu_default
;
24810 selected_cpu
= *mcpu_cpu_opt
;
24812 mcpu_cpu_opt
= &arm_arch_any
;
24815 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24817 autoselect_thumb_from_cpu_variant ();
24819 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24821 #if defined OBJ_COFF || defined OBJ_ELF
24823 unsigned int flags
= 0;
24825 #if defined OBJ_ELF
24826 flags
= meabi_flags
;
24828 switch (meabi_flags
)
24830 case EF_ARM_EABI_UNKNOWN
:
24832 /* Set the flags in the private structure. */
24833 if (uses_apcs_26
) flags
|= F_APCS26
;
24834 if (support_interwork
) flags
|= F_INTERWORK
;
24835 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24836 if (pic_code
) flags
|= F_PIC
;
24837 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24838 flags
|= F_SOFT_FLOAT
;
24840 switch (mfloat_abi_opt
)
24842 case ARM_FLOAT_ABI_SOFT
:
24843 case ARM_FLOAT_ABI_SOFTFP
:
24844 flags
|= F_SOFT_FLOAT
;
24847 case ARM_FLOAT_ABI_HARD
:
24848 if (flags
& F_SOFT_FLOAT
)
24849 as_bad (_("hard-float conflicts with specified fpu"));
24853 /* Using pure-endian doubles (even if soft-float). */
24854 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24855 flags
|= F_VFP_FLOAT
;
24857 #if defined OBJ_ELF
24858 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24859 flags
|= EF_ARM_MAVERICK_FLOAT
;
24862 case EF_ARM_EABI_VER4
:
24863 case EF_ARM_EABI_VER5
:
24864 /* No additional flags to set. */
24871 bfd_set_private_flags (stdoutput
, flags
);
24873 /* We have run out flags in the COFF header to encode the
24874 status of ATPCS support, so instead we create a dummy,
24875 empty, debug section called .arm.atpcs. */
24880 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24884 bfd_set_section_flags
24885 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24886 bfd_set_section_size (stdoutput
, sec
, 0);
24887 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24893 /* Record the CPU type as well. */
24894 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24895 mach
= bfd_mach_arm_iWMMXt2
;
24896 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24897 mach
= bfd_mach_arm_iWMMXt
;
24898 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24899 mach
= bfd_mach_arm_XScale
;
24900 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24901 mach
= bfd_mach_arm_ep9312
;
24902 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24903 mach
= bfd_mach_arm_5TE
;
24904 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24907 mach
= bfd_mach_arm_5T
;
24909 mach
= bfd_mach_arm_5
;
24911 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24913 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24914 mach
= bfd_mach_arm_4T
;
24916 mach
= bfd_mach_arm_4
;
24918 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24919 mach
= bfd_mach_arm_3M
;
24920 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24921 mach
= bfd_mach_arm_3
;
24922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24923 mach
= bfd_mach_arm_2a
;
24924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24925 mach
= bfd_mach_arm_2
;
24927 mach
= bfd_mach_arm_unknown
;
24929 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24932 /* Command line processing. */
24935 Invocation line includes a switch not recognized by the base assembler.
24936 See if it's a processor-specific option.
24938 This routine is somewhat complicated by the need for backwards
24939 compatibility (since older releases of gcc can't be changed).
24940 The new options try to make the interface as compatible as
24943 New options (supported) are:
24945 -mcpu=<cpu name> Assemble for selected processor
24946 -march=<architecture name> Assemble for selected architecture
24947 -mfpu=<fpu architecture> Assemble for selected FPU.
24948 -EB/-mbig-endian Big-endian
24949 -EL/-mlittle-endian Little-endian
24950 -k Generate PIC code
24951 -mthumb Start in Thumb mode
24952 -mthumb-interwork Code supports ARM/Thumb interworking
24954 -m[no-]warn-deprecated Warn about deprecated features
24955 -m[no-]warn-syms Warn when symbols match instructions
24957 For now we will also provide support for:
24959 -mapcs-32 32-bit Program counter
24960 -mapcs-26 26-bit Program counter
24961 -macps-float Floats passed in FP registers
24962 -mapcs-reentrant Reentrant code
24964 (sometime these will probably be replaced with -mapcs=<list of options>
24965 and -matpcs=<list of options>)
24967 The remaining options are only supported for back-wards compatibility.
24968 Cpu variants, the arm part is optional:
24969 -m[arm]1 Currently not supported.
24970 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24971 -m[arm]3 Arm 3 processor
24972 -m[arm]6[xx], Arm 6 processors
24973 -m[arm]7[xx][t][[d]m] Arm 7 processors
24974 -m[arm]8[10] Arm 8 processors
24975 -m[arm]9[20][tdmi] Arm 9 processors
24976 -mstrongarm[110[0]] StrongARM processors
24977 -mxscale XScale processors
24978 -m[arm]v[2345[t[e]]] Arm architectures
24979 -mall All (except the ARM1)
24981 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24982 -mfpe-old (No float load/store multiples)
24983 -mvfpxd VFP Single precision
24985 -mno-fpu Disable all floating point instructions
24987 The following CPU names are recognized:
24988 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24989 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24990 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24991 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24992 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24993 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24994 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24998 const char * md_shortopts
= "m:k";
25000 #ifdef ARM_BI_ENDIAN
25001 #define OPTION_EB (OPTION_MD_BASE + 0)
25002 #define OPTION_EL (OPTION_MD_BASE + 1)
25004 #if TARGET_BYTES_BIG_ENDIAN
25005 #define OPTION_EB (OPTION_MD_BASE + 0)
25007 #define OPTION_EL (OPTION_MD_BASE + 1)
25010 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25012 struct option md_longopts
[] =
25015 {"EB", no_argument
, NULL
, OPTION_EB
},
25018 {"EL", no_argument
, NULL
, OPTION_EL
},
25020 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25021 {NULL
, no_argument
, NULL
, 0}
25025 size_t md_longopts_size
= sizeof (md_longopts
);
25027 struct arm_option_table
25029 const char *option
; /* Option name to match. */
25030 const char *help
; /* Help information. */
25031 int *var
; /* Variable to change. */
25032 int value
; /* What to change it to. */
25033 const char *deprecated
; /* If non-null, print this message. */
25036 struct arm_option_table arm_opts
[] =
25038 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25039 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25040 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25041 &support_interwork
, 1, NULL
},
25042 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25043 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25044 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25046 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25047 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25048 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25049 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25052 /* These are recognized by the assembler, but have no affect on code. */
25053 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25054 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25056 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25057 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25058 &warn_on_deprecated
, 0, NULL
},
25059 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25060 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25061 {NULL
, NULL
, NULL
, 0, NULL
}
25064 struct arm_legacy_option_table
25066 const char *option
; /* Option name to match. */
25067 const arm_feature_set
**var
; /* Variable to change. */
25068 const arm_feature_set value
; /* What to change it to. */
25069 const char *deprecated
; /* If non-null, print this message. */
25072 const struct arm_legacy_option_table arm_legacy_opts
[] =
25074 /* DON'T add any new processors to this list -- we want the whole list
25075 to go away... Add them to the processors table instead. */
25076 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25077 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25078 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25079 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25080 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25081 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25082 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25083 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25084 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25085 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25086 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25087 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25088 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25089 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25090 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25091 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25092 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25093 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25094 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25095 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25096 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25097 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25098 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25099 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25100 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25101 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25102 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25103 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25104 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25105 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25106 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25107 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25108 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25109 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25110 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25111 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25112 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25113 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25114 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25115 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25116 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25117 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25118 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25119 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25120 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25121 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25122 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25123 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25124 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25125 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25126 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25127 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25128 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25129 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25130 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25131 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25132 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25133 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25134 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25135 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25136 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25137 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25138 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25139 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25140 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25141 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25142 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25143 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25144 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25145 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25146 N_("use -mcpu=strongarm110")},
25147 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25148 N_("use -mcpu=strongarm1100")},
25149 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25150 N_("use -mcpu=strongarm1110")},
25151 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25152 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25153 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25155 /* Architecture variants -- don't add any more to this list either. */
25156 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25157 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25158 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25159 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25160 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25161 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25162 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25163 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25164 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25165 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25166 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25167 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25168 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25169 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25170 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25171 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25172 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25173 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25175 /* Floating point variants -- don't add any more to this list either. */
25176 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25177 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25178 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25179 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25180 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25182 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25185 struct arm_cpu_option_table
25189 const arm_feature_set value
;
25190 /* For some CPUs we assume an FPU unless the user explicitly sets
25192 const arm_feature_set default_fpu
;
25193 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25195 const char *canonical_name
;
25198 /* This list should, at a minimum, contain all the cpu names
25199 recognized by GCC. */
25200 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25201 static const struct arm_cpu_option_table arm_cpus
[] =
25203 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25204 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25205 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25206 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25207 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25208 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25209 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25210 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25211 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25212 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25213 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25214 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25215 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25216 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25217 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25218 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25219 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25220 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25221 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25222 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25223 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25224 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25225 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25226 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25227 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25228 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25229 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25230 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25231 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25232 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25233 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25234 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25236 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25237 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25238 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25239 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25240 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25241 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25242 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25243 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25244 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25245 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25246 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25247 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25248 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25249 /* For V5 or later processors we default to using VFP; but the user
25250 should really set the FPU type explicitly. */
25251 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25252 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25253 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25254 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25255 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25256 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25257 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25258 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25259 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25260 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25261 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25262 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25263 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25264 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25265 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25266 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25267 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25268 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25269 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25270 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25272 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25273 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25274 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25275 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25276 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25277 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25278 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25279 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25280 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25282 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25283 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25284 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25285 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25286 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25287 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25288 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25289 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25290 FPU_NONE
, "Cortex-A5"),
25291 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25293 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25294 ARM_FEATURE_COPROC (FPU_VFP_V3
25295 | FPU_NEON_EXT_V1
),
25297 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25298 ARM_FEATURE_COPROC (FPU_VFP_V3
25299 | FPU_NEON_EXT_V1
),
25301 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25303 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25305 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25307 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25309 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25311 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25313 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25315 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25317 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25318 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25320 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25321 FPU_NONE
, "Cortex-R5"),
25322 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25323 FPU_ARCH_VFP_V3D16
,
25325 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25326 FPU_ARCH_VFP_V3D16
,
25328 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25329 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25330 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25331 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25332 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25333 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25334 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25337 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25341 /* ??? XSCALE is really an architecture. */
25342 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25343 /* ??? iwmmxt is not a processor. */
25344 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25345 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25346 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25348 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25349 FPU_ARCH_MAVERICK
, "ARM920T"),
25350 /* Marvell processors. */
25351 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25353 ARM_EXT2_V6T2_V8M
),
25354 FPU_ARCH_VFP_V3D16
, NULL
),
25355 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25357 ARM_EXT2_V6T2_V8M
),
25358 FPU_ARCH_NEON_VFP_V4
, NULL
),
25359 /* APM X-Gene family. */
25360 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25362 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25365 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25369 struct arm_arch_option_table
25373 const arm_feature_set value
;
25374 const arm_feature_set default_fpu
;
25377 /* This list should, at a minimum, contain all the architecture names
25378 recognized by GCC. */
25379 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25380 static const struct arm_arch_option_table arm_archs
[] =
25382 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25383 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25384 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25385 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25386 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25387 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25388 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25389 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25390 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25391 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25392 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25393 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25394 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25395 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25396 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25397 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25398 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25399 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25400 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25401 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25402 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25403 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25404 kept to preserve existing behaviour. */
25405 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25406 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25407 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25408 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25409 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25410 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25411 kept to preserve existing behaviour. */
25412 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25413 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25414 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25415 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25416 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25417 /* The official spelling of the ARMv7 profile variants is the dashed form.
25418 Accept the non-dashed form for compatibility with old toolchains. */
25419 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25420 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25421 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25422 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25423 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25424 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25425 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25426 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25427 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25428 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25429 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25430 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25431 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25432 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25433 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25434 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25435 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25437 #undef ARM_ARCH_OPT
25439 /* ISA extensions in the co-processor and main instruction set space. */
25440 struct arm_option_extension_value_table
25444 const arm_feature_set merge_value
;
25445 const arm_feature_set clear_value
;
25446 const arm_feature_set allowed_archs
;
25449 /* The following table must be in alphabetical order with a NULL last entry.
25451 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25452 static const struct arm_option_extension_value_table arm_extensions
[] =
25454 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25455 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25456 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25457 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25458 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25459 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25460 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25461 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25462 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25464 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25465 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25466 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25467 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25468 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
25469 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25470 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
25471 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25472 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
25473 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25474 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25475 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25476 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25477 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25478 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25479 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25480 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25481 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25482 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25483 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25484 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25485 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25486 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25487 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
25488 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25489 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25490 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25491 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25493 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25494 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25495 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25496 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25497 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25501 /* ISA floating-point and Advanced SIMD extensions. */
25502 struct arm_option_fpu_value_table
25505 const arm_feature_set value
;
25508 /* This list should, at a minimum, contain all the fpu names
25509 recognized by GCC. */
25510 static const struct arm_option_fpu_value_table arm_fpus
[] =
25512 {"softfpa", FPU_NONE
},
25513 {"fpe", FPU_ARCH_FPE
},
25514 {"fpe2", FPU_ARCH_FPE
},
25515 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25516 {"fpa", FPU_ARCH_FPA
},
25517 {"fpa10", FPU_ARCH_FPA
},
25518 {"fpa11", FPU_ARCH_FPA
},
25519 {"arm7500fe", FPU_ARCH_FPA
},
25520 {"softvfp", FPU_ARCH_VFP
},
25521 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25522 {"vfp", FPU_ARCH_VFP_V2
},
25523 {"vfp9", FPU_ARCH_VFP_V2
},
25524 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25525 {"vfp10", FPU_ARCH_VFP_V2
},
25526 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25527 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25528 {"vfpv2", FPU_ARCH_VFP_V2
},
25529 {"vfpv3", FPU_ARCH_VFP_V3
},
25530 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25531 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25532 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25533 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25534 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25535 {"arm1020t", FPU_ARCH_VFP_V1
},
25536 {"arm1020e", FPU_ARCH_VFP_V2
},
25537 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25538 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25539 {"maverick", FPU_ARCH_MAVERICK
},
25540 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25541 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25542 {"vfpv4", FPU_ARCH_VFP_V4
},
25543 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25544 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25545 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25546 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25547 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25548 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25549 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25550 {"crypto-neon-fp-armv8",
25551 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25552 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25553 {"crypto-neon-fp-armv8.1",
25554 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25555 {NULL
, ARM_ARCH_NONE
}
25558 struct arm_option_value_table
25564 static const struct arm_option_value_table arm_float_abis
[] =
25566 {"hard", ARM_FLOAT_ABI_HARD
},
25567 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25568 {"soft", ARM_FLOAT_ABI_SOFT
},
25573 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25574 static const struct arm_option_value_table arm_eabis
[] =
25576 {"gnu", EF_ARM_EABI_UNKNOWN
},
25577 {"4", EF_ARM_EABI_VER4
},
25578 {"5", EF_ARM_EABI_VER5
},
25583 struct arm_long_option_table
25585 const char * option
; /* Substring to match. */
25586 const char * help
; /* Help information. */
25587 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25588 const char * deprecated
; /* If non-null, print this message. */
25592 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25594 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25596 /* We insist on extensions being specified in alphabetical order, and with
25597 extensions being added before being removed. We achieve this by having
25598 the global ARM_EXTENSIONS table in alphabetical order, and using the
25599 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25600 or removing it (0) and only allowing it to change in the order
25602 const struct arm_option_extension_value_table
* opt
= NULL
;
25603 int adding_value
= -1;
25605 /* Copy the feature set, so that we can modify it. */
25606 *ext_set
= **opt_p
;
25609 while (str
!= NULL
&& *str
!= 0)
25616 as_bad (_("invalid architectural extension"));
25621 ext
= strchr (str
, '+');
25626 len
= strlen (str
);
25628 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25630 if (adding_value
!= 0)
25633 opt
= arm_extensions
;
25641 if (adding_value
== -1)
25644 opt
= arm_extensions
;
25646 else if (adding_value
!= 1)
25648 as_bad (_("must specify extensions to add before specifying "
25649 "those to remove"));
25656 as_bad (_("missing architectural extension"));
25660 gas_assert (adding_value
!= -1);
25661 gas_assert (opt
!= NULL
);
25663 /* Scan over the options table trying to find an exact match. */
25664 for (; opt
->name
!= NULL
; opt
++)
25665 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25667 /* Check we can apply the extension to this architecture. */
25668 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25670 as_bad (_("extension does not apply to the base architecture"));
25674 /* Add or remove the extension. */
25676 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25678 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25683 if (opt
->name
== NULL
)
25685 /* Did we fail to find an extension because it wasn't specified in
25686 alphabetical order, or because it does not exist? */
25688 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25689 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25692 if (opt
->name
== NULL
)
25693 as_bad (_("unknown architectural extension `%s'"), str
);
25695 as_bad (_("architectural extensions must be specified in "
25696 "alphabetical order"));
25702 /* We should skip the extension we've just matched the next time
25714 arm_parse_cpu (const char *str
)
25716 const struct arm_cpu_option_table
*opt
;
25717 const char *ext
= strchr (str
, '+');
25723 len
= strlen (str
);
25727 as_bad (_("missing cpu name `%s'"), str
);
25731 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25732 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25734 mcpu_cpu_opt
= &opt
->value
;
25735 mcpu_fpu_opt
= &opt
->default_fpu
;
25736 if (opt
->canonical_name
)
25738 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25739 strcpy (selected_cpu_name
, opt
->canonical_name
);
25745 if (len
>= sizeof selected_cpu_name
)
25746 len
= (sizeof selected_cpu_name
) - 1;
25748 for (i
= 0; i
< len
; i
++)
25749 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25750 selected_cpu_name
[i
] = 0;
25754 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25759 as_bad (_("unknown cpu `%s'"), str
);
25764 arm_parse_arch (const char *str
)
25766 const struct arm_arch_option_table
*opt
;
25767 const char *ext
= strchr (str
, '+');
25773 len
= strlen (str
);
25777 as_bad (_("missing architecture name `%s'"), str
);
25781 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25782 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25784 march_cpu_opt
= &opt
->value
;
25785 march_fpu_opt
= &opt
->default_fpu
;
25786 strcpy (selected_cpu_name
, opt
->name
);
25789 return arm_parse_extension (ext
, &march_cpu_opt
);
25794 as_bad (_("unknown architecture `%s'\n"), str
);
25799 arm_parse_fpu (const char * str
)
25801 const struct arm_option_fpu_value_table
* opt
;
25803 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25804 if (streq (opt
->name
, str
))
25806 mfpu_opt
= &opt
->value
;
25810 as_bad (_("unknown floating point format `%s'\n"), str
);
25815 arm_parse_float_abi (const char * str
)
25817 const struct arm_option_value_table
* opt
;
25819 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25820 if (streq (opt
->name
, str
))
25822 mfloat_abi_opt
= opt
->value
;
25826 as_bad (_("unknown floating point abi `%s'\n"), str
);
25832 arm_parse_eabi (const char * str
)
25834 const struct arm_option_value_table
*opt
;
25836 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25837 if (streq (opt
->name
, str
))
25839 meabi_flags
= opt
->value
;
25842 as_bad (_("unknown EABI `%s'\n"), str
);
25848 arm_parse_it_mode (const char * str
)
25850 bfd_boolean ret
= TRUE
;
25852 if (streq ("arm", str
))
25853 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25854 else if (streq ("thumb", str
))
25855 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25856 else if (streq ("always", str
))
25857 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25858 else if (streq ("never", str
))
25859 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25862 as_bad (_("unknown implicit IT mode `%s', should be "\
25863 "arm, thumb, always, or never."), str
);
25871 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25873 codecomposer_syntax
= TRUE
;
25874 arm_comment_chars
[0] = ';';
25875 arm_line_separator_chars
[0] = 0;
25879 struct arm_long_option_table arm_long_opts
[] =
25881 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25882 arm_parse_cpu
, NULL
},
25883 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25884 arm_parse_arch
, NULL
},
25885 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25886 arm_parse_fpu
, NULL
},
25887 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25888 arm_parse_float_abi
, NULL
},
25890 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25891 arm_parse_eabi
, NULL
},
25893 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25894 arm_parse_it_mode
, NULL
},
25895 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25896 arm_ccs_mode
, NULL
},
25897 {NULL
, NULL
, 0, NULL
}
25901 md_parse_option (int c
, const char * arg
)
25903 struct arm_option_table
*opt
;
25904 const struct arm_legacy_option_table
*fopt
;
25905 struct arm_long_option_table
*lopt
;
25911 target_big_endian
= 1;
25917 target_big_endian
= 0;
25921 case OPTION_FIX_V4BX
:
25926 /* Listing option. Just ignore these, we don't support additional
25931 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25933 if (c
== opt
->option
[0]
25934 && ((arg
== NULL
&& opt
->option
[1] == 0)
25935 || streq (arg
, opt
->option
+ 1)))
25937 /* If the option is deprecated, tell the user. */
25938 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25939 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25940 arg
? arg
: "", _(opt
->deprecated
));
25942 if (opt
->var
!= NULL
)
25943 *opt
->var
= opt
->value
;
25949 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25951 if (c
== fopt
->option
[0]
25952 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25953 || streq (arg
, fopt
->option
+ 1)))
25955 /* If the option is deprecated, tell the user. */
25956 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25957 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25958 arg
? arg
: "", _(fopt
->deprecated
));
25960 if (fopt
->var
!= NULL
)
25961 *fopt
->var
= &fopt
->value
;
25967 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25969 /* These options are expected to have an argument. */
25970 if (c
== lopt
->option
[0]
25972 && strncmp (arg
, lopt
->option
+ 1,
25973 strlen (lopt
->option
+ 1)) == 0)
25975 /* If the option is deprecated, tell the user. */
25976 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25977 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25978 _(lopt
->deprecated
));
25980 /* Call the sup-option parser. */
25981 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25992 md_show_usage (FILE * fp
)
25994 struct arm_option_table
*opt
;
25995 struct arm_long_option_table
*lopt
;
25997 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25999 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26000 if (opt
->help
!= NULL
)
26001 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26003 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26004 if (lopt
->help
!= NULL
)
26005 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26009 -EB assemble code for a big-endian cpu\n"));
26014 -EL assemble code for a little-endian cpu\n"));
26018 --fix-v4bx Allow BX in ARMv4 code\n"));
26026 arm_feature_set flags
;
26027 } cpu_arch_ver_table
;
26029 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26030 must be sorted least features first but some reordering is needed, eg. for
26031 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26032 static const cpu_arch_ver_table cpu_arch_ver
[] =
26038 {4, ARM_ARCH_V5TE
},
26039 {5, ARM_ARCH_V5TEJ
},
26043 {11, ARM_ARCH_V6M
},
26044 {12, ARM_ARCH_V6SM
},
26045 {8, ARM_ARCH_V6T2
},
26046 {10, ARM_ARCH_V7VE
},
26047 {10, ARM_ARCH_V7R
},
26048 {10, ARM_ARCH_V7M
},
26049 {14, ARM_ARCH_V8A
},
26050 {16, ARM_ARCH_V8M_BASE
},
26051 {17, ARM_ARCH_V8M_MAIN
},
26055 /* Set an attribute if it has not already been set by the user. */
26057 aeabi_set_attribute_int (int tag
, int value
)
26060 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26061 || !attributes_set_explicitly
[tag
])
26062 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26066 aeabi_set_attribute_string (int tag
, const char *value
)
26069 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26070 || !attributes_set_explicitly
[tag
])
26071 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26074 /* Set the public EABI object attributes. */
26076 aeabi_set_public_attributes (void)
26081 int fp16_optional
= 0;
26082 arm_feature_set flags
;
26083 arm_feature_set tmp
;
26084 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26085 const cpu_arch_ver_table
*p
;
26087 /* Choose the architecture based on the capabilities of the requested cpu
26088 (if any) and/or the instructions actually used. */
26089 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26090 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26091 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26093 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26094 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26096 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26097 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26099 selected_cpu
= flags
;
26101 /* Allow the user to override the reported architecture. */
26104 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26105 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26108 /* We need to make sure that the attributes do not identify us as v6S-M
26109 when the only v6S-M feature in use is the Operating System Extensions. */
26110 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26111 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26112 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26116 for (p
= cpu_arch_ver
; p
->val
; p
++)
26118 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26121 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26125 /* The table lookup above finds the last architecture to contribute
26126 a new feature. Unfortunately, Tag13 is a subset of the union of
26127 v6T2 and v7-M, so it is never seen as contributing a new feature.
26128 We can not search for the last entry which is entirely used,
26129 because if no CPU is specified we build up only those flags
26130 actually used. Perhaps we should separate out the specified
26131 and implicit cases. Avoid taking this path for -march=all by
26132 checking for contradictory v7-A / v7-M features. */
26133 if (arch
== TAG_CPU_ARCH_V7
26134 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26135 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26136 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26137 arch
= TAG_CPU_ARCH_V7E_M
;
26139 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26140 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26141 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26143 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26144 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26145 ARMv8-M, -march=all must be detected as ARMv8-A. */
26146 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26147 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26148 arch
= TAG_CPU_ARCH_V8
;
26150 /* Tag_CPU_name. */
26151 if (selected_cpu_name
[0])
26155 q
= selected_cpu_name
;
26156 if (strncmp (q
, "armv", 4) == 0)
26161 for (i
= 0; q
[i
]; i
++)
26162 q
[i
] = TOUPPER (q
[i
]);
26164 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26167 /* Tag_CPU_arch. */
26168 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26170 /* Tag_CPU_arch_profile. */
26171 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26172 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26173 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26174 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
)))
26176 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26178 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26183 if (profile
!= '\0')
26184 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26186 /* Tag_ARM_ISA_use. */
26187 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26189 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26191 /* Tag_THUMB_ISA_use. */
26192 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26197 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26198 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26200 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26204 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26207 /* Tag_VFP_arch. */
26208 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26209 aeabi_set_attribute_int (Tag_VFP_arch
,
26210 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26212 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26213 aeabi_set_attribute_int (Tag_VFP_arch
,
26214 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26216 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26219 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26221 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26223 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26226 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26227 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26228 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26229 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26230 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26232 /* Tag_ABI_HardFP_use. */
26233 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26234 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26235 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26237 /* Tag_WMMX_arch. */
26238 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26239 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26240 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26241 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26243 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26244 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26245 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26246 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26247 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26248 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26250 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26252 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26256 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26261 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26262 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26263 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26267 We set Tag_DIV_use to two when integer divide instructions have been used
26268 in ARM state, or when Thumb integer divide instructions have been used,
26269 but we have no architecture profile set, nor have we any ARM instructions.
26271 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26272 by the base architecture.
26274 For new architectures we will have to check these tests. */
26275 gas_assert (arch
<= TAG_CPU_ARCH_V8
26276 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26277 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26278 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26279 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26280 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26281 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26282 || (profile
== '\0'
26283 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26284 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26285 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26287 /* Tag_MP_extension_use. */
26288 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26289 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26291 /* Tag Virtualization_use. */
26292 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26294 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26297 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26300 /* Add the default contents for the .ARM.attributes section. */
26304 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26307 aeabi_set_public_attributes ();
26309 #endif /* OBJ_ELF */
26312 /* Parse a .cpu directive. */
26315 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26317 const struct arm_cpu_option_table
*opt
;
26321 name
= input_line_pointer
;
26322 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26323 input_line_pointer
++;
26324 saved_char
= *input_line_pointer
;
26325 *input_line_pointer
= 0;
26327 /* Skip the first "all" entry. */
26328 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26329 if (streq (opt
->name
, name
))
26331 mcpu_cpu_opt
= &opt
->value
;
26332 selected_cpu
= opt
->value
;
26333 if (opt
->canonical_name
)
26334 strcpy (selected_cpu_name
, opt
->canonical_name
);
26338 for (i
= 0; opt
->name
[i
]; i
++)
26339 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26341 selected_cpu_name
[i
] = 0;
26343 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26344 *input_line_pointer
= saved_char
;
26345 demand_empty_rest_of_line ();
26348 as_bad (_("unknown cpu `%s'"), name
);
26349 *input_line_pointer
= saved_char
;
26350 ignore_rest_of_line ();
26354 /* Parse a .arch directive. */
26357 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26359 const struct arm_arch_option_table
*opt
;
26363 name
= input_line_pointer
;
26364 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26365 input_line_pointer
++;
26366 saved_char
= *input_line_pointer
;
26367 *input_line_pointer
= 0;
26369 /* Skip the first "all" entry. */
26370 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26371 if (streq (opt
->name
, name
))
26373 mcpu_cpu_opt
= &opt
->value
;
26374 selected_cpu
= opt
->value
;
26375 strcpy (selected_cpu_name
, opt
->name
);
26376 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26377 *input_line_pointer
= saved_char
;
26378 demand_empty_rest_of_line ();
26382 as_bad (_("unknown architecture `%s'\n"), name
);
26383 *input_line_pointer
= saved_char
;
26384 ignore_rest_of_line ();
26388 /* Parse a .object_arch directive. */
26391 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26393 const struct arm_arch_option_table
*opt
;
26397 name
= input_line_pointer
;
26398 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26399 input_line_pointer
++;
26400 saved_char
= *input_line_pointer
;
26401 *input_line_pointer
= 0;
26403 /* Skip the first "all" entry. */
26404 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26405 if (streq (opt
->name
, name
))
26407 object_arch
= &opt
->value
;
26408 *input_line_pointer
= saved_char
;
26409 demand_empty_rest_of_line ();
26413 as_bad (_("unknown architecture `%s'\n"), name
);
26414 *input_line_pointer
= saved_char
;
26415 ignore_rest_of_line ();
26418 /* Parse a .arch_extension directive. */
26421 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26423 const struct arm_option_extension_value_table
*opt
;
26426 int adding_value
= 1;
26428 name
= input_line_pointer
;
26429 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26430 input_line_pointer
++;
26431 saved_char
= *input_line_pointer
;
26432 *input_line_pointer
= 0;
26434 if (strlen (name
) >= 2
26435 && strncmp (name
, "no", 2) == 0)
26441 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26442 if (streq (opt
->name
, name
))
26444 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
26446 as_bad (_("architectural extension `%s' is not allowed for the "
26447 "current base architecture"), name
);
26452 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26455 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26457 mcpu_cpu_opt
= &selected_cpu
;
26458 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26459 *input_line_pointer
= saved_char
;
26460 demand_empty_rest_of_line ();
26464 if (opt
->name
== NULL
)
26465 as_bad (_("unknown architecture extension `%s'\n"), name
);
26467 *input_line_pointer
= saved_char
;
26468 ignore_rest_of_line ();
26471 /* Parse a .fpu directive. */
26474 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26476 const struct arm_option_fpu_value_table
*opt
;
26480 name
= input_line_pointer
;
26481 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26482 input_line_pointer
++;
26483 saved_char
= *input_line_pointer
;
26484 *input_line_pointer
= 0;
26486 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26487 if (streq (opt
->name
, name
))
26489 mfpu_opt
= &opt
->value
;
26490 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26491 *input_line_pointer
= saved_char
;
26492 demand_empty_rest_of_line ();
26496 as_bad (_("unknown floating point format `%s'\n"), name
);
26497 *input_line_pointer
= saved_char
;
26498 ignore_rest_of_line ();
26501 /* Copy symbol information. */
26504 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26506 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26510 /* Given a symbolic attribute NAME, return the proper integer value.
26511 Returns -1 if the attribute is not known. */
26514 arm_convert_symbolic_attribute (const char *name
)
26516 static const struct
26521 attribute_table
[] =
26523 /* When you modify this table you should
26524 also modify the list in doc/c-arm.texi. */
26525 #define T(tag) {#tag, tag}
26526 T (Tag_CPU_raw_name
),
26529 T (Tag_CPU_arch_profile
),
26530 T (Tag_ARM_ISA_use
),
26531 T (Tag_THUMB_ISA_use
),
26535 T (Tag_Advanced_SIMD_arch
),
26536 T (Tag_PCS_config
),
26537 T (Tag_ABI_PCS_R9_use
),
26538 T (Tag_ABI_PCS_RW_data
),
26539 T (Tag_ABI_PCS_RO_data
),
26540 T (Tag_ABI_PCS_GOT_use
),
26541 T (Tag_ABI_PCS_wchar_t
),
26542 T (Tag_ABI_FP_rounding
),
26543 T (Tag_ABI_FP_denormal
),
26544 T (Tag_ABI_FP_exceptions
),
26545 T (Tag_ABI_FP_user_exceptions
),
26546 T (Tag_ABI_FP_number_model
),
26547 T (Tag_ABI_align_needed
),
26548 T (Tag_ABI_align8_needed
),
26549 T (Tag_ABI_align_preserved
),
26550 T (Tag_ABI_align8_preserved
),
26551 T (Tag_ABI_enum_size
),
26552 T (Tag_ABI_HardFP_use
),
26553 T (Tag_ABI_VFP_args
),
26554 T (Tag_ABI_WMMX_args
),
26555 T (Tag_ABI_optimization_goals
),
26556 T (Tag_ABI_FP_optimization_goals
),
26557 T (Tag_compatibility
),
26558 T (Tag_CPU_unaligned_access
),
26559 T (Tag_FP_HP_extension
),
26560 T (Tag_VFP_HP_extension
),
26561 T (Tag_ABI_FP_16bit_format
),
26562 T (Tag_MPextension_use
),
26564 T (Tag_nodefaults
),
26565 T (Tag_also_compatible_with
),
26566 T (Tag_conformance
),
26568 T (Tag_Virtualization_use
),
26569 /* We deliberately do not include Tag_MPextension_use_legacy. */
26577 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26578 if (streq (name
, attribute_table
[i
].name
))
26579 return attribute_table
[i
].tag
;
26585 /* Apply sym value for relocations only in the case that they are for
26586 local symbols in the same segment as the fixup and you have the
26587 respective architectural feature for blx and simple switches. */
26589 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26592 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26593 /* PR 17444: If the local symbol is in a different section then a reloc
26594 will always be generated for it, so applying the symbol value now
26595 will result in a double offset being stored in the relocation. */
26596 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26597 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26599 switch (fixP
->fx_r_type
)
26601 case BFD_RELOC_ARM_PCREL_BLX
:
26602 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26603 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26607 case BFD_RELOC_ARM_PCREL_CALL
:
26608 case BFD_RELOC_THUMB_PCREL_BLX
:
26609 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26620 #endif /* OBJ_ELF */